Delay adjustment device, delay adjustment method, and delay adjustment program

Abstract

This makes it possible to synchronize the delay times of two broadcast streams. [Solution] The delay adjustment device calculates a first adjustment time and a second adjustment time based on the first timestamp contained in the first packet, the second timestamp contained in the second packet, and a counter value based on the reference clock. It then controls the packet output of the first packet from the first buffer to the time the first adjustment time has elapsed, from the time the first packet arrives at the first buffer until the second adjustment time has elapsed, and controls the packet output of the second packet from the second buffer to the time the second adjustment time has elapsed, and at the output timing generated based on the output clock, it takes out the first packet from the first buffer and outputs it, and at the same timing as the output, it takes out the second packet from the second buffer.

Description

Technical Field

[0001] The present disclosure relates to a delay adjustment device, a delay adjustment method, and a delay adjustment program.

Background Art

[0002] With the start of terrestrial digital broadcasting in 2003, the digitalization of STL (Studio to Transmitter Link) was carried out. STL is a line for sending a broadcast stream from a performance venue (studio) to a transmitter. Note that a broadcast stream is a series of data flows in which broadcast contents are multiplexed. Also, broadcast contents are individual information elements transmitted in broadcasting, specifically, video data, audio data, data for data broadcasting, and the like.

[0003] FIG. 22 shows a configuration example of STL. A broadcast stream generated at a performance venue is input to STL. Two systems (for example, an active system and a standby system) of broadcast streams are input to STL. In STL, a modulator applies single carrier 16QAM (Quadrature Amplitude Modulation) modulation to the broadcast stream to generate an IF (Intermediate Frequency) signal. Also, a transmitter converts the IF signal into a SHF (Super High Frequency) signal. Then, a SHF switch transmits either one of the two systems of SHF signals via an antenna. Also, a SHF distributor that has received a SHF signal distributes the received SHF signal to two receivers. A receiver converts the distributed SHF signal into an IF signal. Also, a demodulator demodulates the IF signal into a broadcast stream.

[0004] Note that Patent Document 1 describes a method for correcting time stamps of a plurality of streams so that the time stamps of the plurality of streams are synchronized with a common reference clock in a multiplexing device that multiplexes a plurality of streams having different reference clocks for time stamps.

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Publication No. 2001-053703 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] For an SHF switch to seamlessly switch between transmitted SHF signals, it is desirable to minimize the delay time difference between the two SHF signals input to the switch. For example, the delay time difference between the SHF signals may need to be within approximately 10 ns.

[0007] The delay time is the elapsed time from when the packets constituting the broadcast stream are output from the input device. The input device is the device that inputs the broadcast stream to the STL. The delay time difference is the difference in delay times between the two broadcast streams. The delay time difference arises, for example, from differences in the path length and path environment from the time the packets constituting the broadcast stream are input to the STL.

[0008] To minimize the delay time difference between two SHF signals, it is desirable to minimize the delay time difference between the broadcast streams output from each of the two modulators. In some cases, the delay time difference between the broadcast streams output from the modulators may need to be within a few nanoseconds.

[0009] Furthermore, in order to minimize the delay time difference between the broadcast streams output from each of the two modulators, it is desirable to minimize the delay time difference between the two broadcast streams input to the two modulators.

[0010] Furthermore, the method described in Patent Document 1 corrects the timestamps of multiple streams to synchronize with a common reference clock, and therefore cannot reduce the delay time difference between the two broadcast streams input to the STL's SHF switch.

[0011] Another method to reduce the delay time difference of the broadcast stream input to the modulator is to adjust the cable length of the input signal to the modulator. However, this method is time-consuming to construct the STL.

[0012] The purpose of this disclosure is to provide a delay adjustment device, a delay adjustment method, and a delay adjustment program that enable the synchronization of delay times between two broadcast streams, in view of the aforementioned problems. [Means for solving the problem]

[0013] In one embodiment of the present disclosure, the delay adjustment device includes: a first receiving unit that stores a received first packet in a first buffer; a second receiving unit that stores a received second packet in a second buffer; a calculation unit that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp which is a timestamp contained in the first packet, a second timestamp which is a timestamp contained in the second packet, and a counter value that is counted up by a reference clock; a delay adjustment unit that controls the packet output of the first packet from the first buffer from the time the first packet arrives in the first buffer until the first adjustment time has elapsed, and controls the packet output of the second packet from the second buffer from the time the second packet arrives in the second buffer until the second adjustment time has elapsed; and an output unit that takes out the first packet from the first buffer and outputs it at an output timing generated based on an output clock for packet output, and takes out the second packet from the second buffer at the same timing as the output timing.

[0014] In another embodiment of the present disclosure, the delay adjustment method includes a delay adjustment device that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp which is a timestamp contained in the first received packet, a second timestamp which is a timestamp contained in the second received packet, and a counter value which is counted up by a reference clock; controls to delay the packet output of the first packet from the first buffer storing the first packet from the time the first packet arrives in the first buffer storing the first packet until the first adjustment time has elapsed; controls to delay the packet output of the second packet from the second buffer storing the second packet from the time the second packet arrives in the second buffer storing the second packet until the second adjustment time has elapsed; and at an output timing generated based on an output clock for packet output, the first packet is taken out of the first buffer and output, and at the same timing as the output timing, the second packet is taken out of the second buffer.

[0015] Furthermore, in another aspect of the present disclosure, the delay adjustment program enables the computer to perform a calculation function that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp which is a timestamp contained in the first received packet, a second timestamp which is a timestamp contained in the second received packet, and a counter value which is counted up by a reference clock; a delay adjustment function that controls the packet output of the first packet from the first buffer storing the first packet from the time the first packet arrives in the first buffer storing the first packet until the first adjustment time has elapsed; and controls the packet output of the second packet from the second buffer storing the second packet from the time the second packet arrives in the second buffer storing the second packet until the second adjustment time has elapsed; and an output function that takes out the first packet from the first buffer and outputs it at an output timing generated based on an output clock for packet output, and takes out the second packet from the second buffer at the same timing as the output timing. [Effects of the Invention]

[0016] According to this disclosure, it will be possible to synchronize the delay times of two broadcast streams. [Brief explanation of the drawing]

[0017] [Figure 1] This figure shows an example configuration of the delay adjustment device of the present disclosure. [Figure 2] This figure shows an example of the operation flow of the delay adjustment device in this disclosure. [Figure 3] This figure shows an example of the structure of the STL in this disclosure. [Figure 4] This figure shows an example configuration of the delay adjustment device of the present disclosure. [Figure 5] This figure shows an example configuration of the first buffer of this disclosure. [Figure 6] This figure shows an example configuration of the second buffer of this disclosure. [Figure 7] It is a diagram showing a configuration example of the calculation unit of the present disclosure. [Figure 8] It is a diagram showing a configuration example of the output unit of the present disclosure. [Figure 9] It is a diagram showing a configuration example of the STL of the present disclosure. [Figure 10] It is a diagram showing a configuration example of the delay adjustment device of the present disclosure. [Figure 11] It is a diagram showing a configuration example of the output unit of the present disclosure. [Figure 12] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 13] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 14] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 15] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 16] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 17] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 18] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 19] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 20] It is a diagram showing an example of the operation flow of the delay adjustment device of the present disclosure. [Figure 21] It is a diagram showing a hardware configuration example of each embodiment of the present disclosure. [Figure 22] It is a diagram showing a configuration example of the STL.

Embodiments for Carrying Out the Invention

[0018] [First Embodiment] The first embodiment of the present disclosure will be described.

[0019] Furthermore, a specific example of the delay adjustment device 10 in the first embodiment is the delay adjustment device 20 in the second embodiment, which will be described later.

[0020] First, an example of the configuration of the delay adjustment device 10 will be described. Figure 1 shows an example of the configuration of the delay adjustment device 10. The delay adjustment device 10 includes a first receiving unit 11, a second receiving unit 12, a first buffer 13, a second buffer 14, a calculation unit 15, a delay adjustment unit 16, and an output unit 17.

[0021] The first receiving unit 11 stores the received first packet in the first buffer 13. The second receiving unit 12 stores the received second packet in the second buffer 14.

[0022] The calculation unit 15 calculates the first adjustment time for the first packet and the second adjustment time for the second packet based on the first timestamp, the second timestamp, and the counter value. The first timestamp is the timestamp contained in the first packet. The second timestamp is the timestamp contained in the second packet. The counter value is incremented by the reference clock.

[0023] The delay adjustment unit 16 controls the packet output of the first packet from the first buffer 13 from the time the first packet arrives at the first buffer 13 until the first adjustment time has elapsed. The delay adjustment unit 16 also controls the packet output of the second packet from the second buffer 14 from the time the second packet arrives at the second buffer 14 until the second adjustment time has elapsed.

[0024] The output unit 17 extracts the first packet from the first buffer 13 and outputs it at the output timing. The output unit 17 also extracts the second packet from the second buffer 14 at the same timing as the output timing. The output timing is generated based on the output clock for packet output.

[0025] Next, an example of the operation flow of the delay adjustment device 10 will be described. Figure 2 shows an example of the operation flow of the delay adjustment device 10.

[0026] The calculation unit 15 calculates the first adjustment time for the first packet and the second adjustment time for the second packet based on the first timestamp, the second timestamp, and the counter value (step S101).

[0027] The delay adjustment unit 16 controls the packet output of the first packet from the first buffer 13 from the time the first packet arrives at the first buffer 13 until the first adjustment time has elapsed. The delay adjustment unit 16 also controls the packet output of the second packet from the second buffer 14 from the time the second packet arrives at the second buffer 14 until the second adjustment time has elapsed (step S102).

[0028] The output unit 17 takes the first packet from the first buffer 13 and outputs it at the output timing. Also, at the same timing as the output timing, the output unit 17 takes the second packet from the second buffer 14 (step S103).

[0029] As described above, in the first embodiment of this disclosure, the delay adjustment device 10 includes a first receiving unit 11, a second receiving unit 12, a first buffer 13, a second buffer 14, a calculation unit 15, a delay adjustment unit 16, and an output unit 17. The first receiving unit 11 stores the received first packet in the first buffer 13. The second receiving unit 12 stores the received second packet in the second buffer 14. The calculation unit 15 calculates the first adjustment time for the first packet and the second adjustment time for the second packet based on the first timestamp, the second timestamp, and a counter value. The first timestamp is the timestamp contained in the first packet. The second timestamp is the timestamp contained in the second packet. The counter value is counted up by a reference clock. The delay adjustment unit 16 controls the packet output of the first packet from the first buffer 13 from the time the first packet arrives in the first buffer 13 until the first adjustment time has elapsed. Furthermore, the delay adjustment unit 16 controls the packet output of the second packet from the second buffer 14 from the time the second packet arrives at the second buffer 14 until the second adjustment time has elapsed. The output unit 17 takes the first packet from the first buffer 13 and outputs it at the output timing. Also, at the same timing as the output timing, the output unit 17 takes the second packet from the second buffer 14. The output timing is generated based on the output clock for packet output.

[0030] In this way, the delay adjustment device 10 adjusts the delay time difference between the first packet taken from the first buffer 13 and the second packet taken from the second buffer 14, based on the first adjustment time and the second adjustment time. Then, at the output timing, the delay adjustment device 10 takes out the first packet and the second packet at the same time. The output timing is generated based on the output clock for packet output. This makes it possible to take out and output packets from the buffers of both systems at the same time. Therefore, it becomes possible to synchronize the delay times of the two broadcast streams.

[0031] [Second Embodiment] Next, the delay adjustment device 20 in the second embodiment of the present disclosure will be described. Note that a specific example of the delay adjustment device 10 in the first embodiment is the delay adjustment device 20 in the second embodiment.

[0032] [Configuration Example of STL] First, a configuration example of the STL 200 will be described using FIG. 3. FIG. 3 is a diagram showing a configuration example of the STL.

[0033] Two systems of packets are input to the STL 200. Two systems (for example, the active system and the standby system) of packets are input to the STL 200. Of the two systems of packets input to the STL 200, one is called packet A and the other is called packet B.

[0034] When the two systems of packets input to the STL are packets of the active system and the standby system, packets with the same data content are input to the STL. However, even in this case, packet A and packet B may have different input timings to the STL due to differences in the path lengths until they are input to the STL.

[0035] The packet is a packet for transmitting broadcast content. The packet is, for example, a packet transmitted in a TS (Transport Stream) conforming to the MPEG (Moving Picture Experts Group)-2 system standard. Note that the packet is not limited to a packet transmitted in a TS. For example, the packet may be a packet for transmitting broadcast content by IP (Internet Protocol).

[0036] Also, a series of transmitted packet groups may be called a stream. Also, the stream for transmitting packet A may be called stream A. Also, the stream for transmitting packet B may be called stream B.

[0037] In the STL200, modulator 201a generates an IF signal by applying single-carrier 16QAM modulation to stream A. Modulator 201b generates an IF signal by applying single-carrier 16QAM modulation to stream B.

[0038] Furthermore, transmitter 202a converts the IF signal generated by modulator 201a into an SHF signal. Transmitter 202b also converts the IF signal generated by modulator 201b into an SHF signal. Finally, SHF switch 203 transmits one of the two SHF signals via antenna 204.

[0039] Furthermore, the SHF distributor 206, which receives the SHF signal via antenna 205, distributes the received SHF signal to receivers 207a and 207b. Receiver 207a converts the distributed SHF signal into an IF signal. Receiver 207b also converts the distributed SHF signal into an IF signal.

[0040] Then, demodulator 208a demodulates the IF signal output from receiver 207a into a broadcast stream. Similarly, demodulator 208b demodulates the IF signal output from receiver 207b into a broadcast stream.

[0041] <Example of delay adjustment device configuration> Next, Figure 4 shows an example configuration of the delay adjustment device 20. The delay adjustment device 20 is included in both modulator 201a and modulator 201b. The delay adjustment device 20 included in modulator 201a is sometimes called delay adjustment device 20a. Similarly, the delay adjustment device 20 included in modulator 201b is sometimes called delay adjustment device 20b. Furthermore, hereafter, "modulator 201" refers to modulator 201a if modulator 201 includes delay adjustment device 20a, and to modulator 201b if modulator 201b includes delay adjustment device 20b. Note that the delay adjustment device 20 may be located outside modulator 201.

[0042] The delay adjustment device 20 adjusts the delay time of packets input to the STL200 and outputs packets with adjusted delay times. The packets output from the delay adjustment device 20 are then modulated by the modulator 201.

[0043] The delay adjustment device 20 receives a first packet and a second packet as input. If the STL200 has the configuration shown in Figure 3, the first packet is a packet from the system output by the delay adjustment device 20. The second packet is a packet from the system used by the delay adjustment device 20 to adjust the delay time of the first packet. In this case, the first packet may also be called the primary packet, and the second packet may also be called the secondary packet.

[0044] Packet A is input to delay adjustment device 20a as the first packet. Packet B is input to delay adjustment device 20a as the second packet. Packet B is input to delay adjustment device 20b as the first packet. Packet A is input to delay adjustment device 20b as the second packet.

[0045] The delay adjustment device 20 includes a first receiving unit 21, a second receiving unit 22, a first buffer 23, a second buffer 24, a calculation unit 25, a delay adjustment unit 26, an output unit 27, a clock generation unit 28, and a counter unit 29.

[0046] The clock generation unit 28 generates a reference clock and an output clock. The reference clock is a clock with a clock period that is an integer multiple of the internal clock. The internal clock is a clock with a frequency of 27 MHz. The internal clock is generated by a crystal oscillator included in the modulator 201. The clock generation unit 28 generates the reference clock by dividing the internal clock. If the timestamp count-up frequency is 90 kHz, the clock period of the reference clock will be 300 times that of the internal clock (the frequency will be 1 / 300th). The frequency of the reference clock is adjusted by the timestamp included in the first packet.

[0047] The output clock is a clock with a frequency that is an integer multiple of the modulation clock. The modulation clock is the modulation clock according to the ISDB-T (Integrated Services Digital Broadcasting-Terrestrial) standard. The frequency of the modulation clock is 512 / 63 MHz. The clock generation unit 28 generates the output clock by frequency-converting the internal clock. The output clock has, for example, a frequency four times that of the modulation clock. This frequency corresponds to the output rate of TS packets (1 packet = 204 bytes) at 2028 / 63 Mbps.

[0048] The counter unit 29 increments the counter value using a reference clock. The counter value of the counter unit 29 is a timestamp generated inside the delay adjustment device 20.

[0049] In this embodiment, it is assumed that the reference clock used by delay adjustment device 20a and the reference clock used by delay adjustment device 20b are synchronized. Furthermore, it is assumed that the output clock used by delay adjustment device 20a and the output clock used by delay adjustment device 20b are synchronized. The method of synchronization is arbitrary. For example, delay adjustment device 20a and delay adjustment device 20b may share the clock generation unit 28 and the counter unit 29.

[0050] The first receiving unit 21 stores the first received packet in the first buffer 23. The second receiving unit 22 stores the second received packet in the second buffer 24. The first buffer 23 and the second buffer 24 are FIFO (First In First Out) buffers.

[0051] Figure 5 shows an example configuration of the first buffer 23. The first buffer 23 may include a first basic adjustment buffer 231 and a first output buffer 232. In this case, packets output from the first basic adjustment buffer 231 are input to the first output buffer 232. Also, the first buffer 23 does not have to be divided into two parts: the first basic adjustment buffer 231 and the first output buffer 232.

[0052] Figure 6 also shows an example configuration of the second buffer 24. The second buffer 24 may include a second basic adjustment buffer 241 and a second output buffer 242. In this case, packets output from the second basic adjustment buffer 241 are input to the second output buffer 242. Furthermore, the second buffer 24 does not necessarily have to be divided into two parts: a second basic adjustment buffer 241 and a second output buffer 242.

[0053] The calculation unit 25 calculates the first adjustment time and the second adjustment time based on the first timestamp and the second timestamp. The first timestamp is the timestamp contained in the first packet. The second timestamp is the timestamp contained in the second packet. The first adjustment time indicates how much the packet output from the first buffer 23 is delayed from the time the first packet was input to the first buffer 23. The second adjustment time indicates how much the packet output from the second buffer 24 is delayed from the time the second packet was input to the second buffer 24.

[0054] Figure 7 shows an example of the configuration of the calculation unit 25. The calculation unit 25 includes a first timestamp detection unit 251, a second timestamp detection unit 252, a first counter value storage unit 253, a second counter value storage unit 254, and a delay time calculation unit 255.

[0055] The first timestamp detection unit 251 detects the first timestamp from the first packet. The second timestamp detection unit 252 detects the second timestamp from the second packet.

[0056] Furthermore, the first timestamp detection unit 251 stores the first counter value in the first counter value storage unit 253. The first counter value is the counter value indicated by the counter unit 29 at the time the first timestamp is detected. Furthermore, the second timestamp detection unit 252 stores the second counter value in the second counter value storage unit 254. The second counter value is the counter value indicated by the counter unit 29 at the time the second timestamp is detected.

[0057] The delay time calculation unit 255 calculates the first delay time by subtracting the first timestamp from the first counter value. The delay time calculation unit 255 also calculates the second delay time by subtracting the second timestamp from the second counter value. Then, the delay time calculation unit 255 determines the fixed delay time based on the larger of the first delay time and the second delay time.

[0058] More specifically, the delay time calculation unit 255 calculates a first average delay time by averaging the first delay times for a predetermined number of first packets. The delay time calculation unit 255 also calculates a second average delay time by averaging the second delay times for a predetermined number of second packets. Then, the delay time calculation unit 255 determines the fixed delay time as the larger of the first and second average delay times, plus a margin value. The margin value may include, for example, the fluctuation time of packet input when the first and second packets are input via an IP line.

[0059] Furthermore, the statistical processing performed during the first delay time and the statistical processing performed during the second delay time do not have to be averaging. The delay time calculation unit 255 may, for example, use the median of the first delay times for a predetermined number of first packets as the first average delay time. Also, the packets subject to statistical processing may be a predetermined number of packets, or packets received during a predetermined time period.

[0060] Furthermore, in this embodiment, it is assumed that the fixed delay time used by delay adjustment device 20a and the fixed delay time used by delay adjustment device 20b are the same. The method of synchronizing the fixed delay times is arbitrary. For example, delay adjustment device 20a and delay adjustment device 20b may share the calculated fixed delay times and adopt the larger value.

[0061] Furthermore, the delay time calculation unit 255 calculates a first adjustment time. The first adjustment time indicates how much the packet output from the first buffer 23 is delayed from the time the first packet was input to the first buffer 23. The delay time calculation unit 255 calculates the first adjustment time by subtracting the first delay time from the fixed delay time. More specifically, the delay time calculation unit 255 calculates the first adjustment time by subtracting the first average delay time from the fixed delay time.

[0062] Furthermore, the delay time calculation unit 255 calculates a second adjustment time. The second adjustment time indicates how much the packet output from the second buffer 24 is delayed from the time the second packet was input to the second buffer 24. The delay time calculation unit 255 calculates the second adjustment time by subtracting the second delay time from the fixed delay time. More specifically, the delay time calculation unit 255 calculates the second adjustment time by subtracting the second average delay time from the fixed delay time.

[0063] The delay adjustment unit 26 controls the packet output of the first packet from the time the first packet arrives at the first buffer 23 until the first adjustment time has elapsed. The delay adjustment unit 26 also controls the packet output of the second packet from the time the second packet arrives at the second buffer 24 until the second adjustment time has elapsed.

[0064] If the first buffer 23 has the configuration shown in Figure 5 and the second buffer has the configuration shown in Figure 6, the delay adjustment unit 26 outputs the first packet to the first output buffer 232 when the first adjustment time has elapsed from the time the first packet arrived at the first basic adjustment buffer 231. The delay adjustment unit 26 also outputs the second packet to the second output buffer 242 when the second adjustment time has elapsed from the time the second packet arrived at the second basic adjustment buffer 241. As a result, the first output buffer 232 stores the first packet after the first adjustment time has elapsed from the time it arrived at the first buffer 23 (first basic adjustment buffer 231). The second output buffer 242 stores the second packet after the second adjustment time has elapsed from the time it arrived at the second buffer 24 (second basic adjustment buffer 241).

[0065] The output unit 27 outputs the first packet from the first buffer 23 at the output timing, after the first adjustment time has elapsed since its arrival in the first buffer 23. The output unit 27 also outputs the second packet from the second buffer 24 at the same timing as the first packet is output from the first buffer 23, after the second adjustment time has elapsed since its arrival in the second buffer 24. The output unit 27 also outputs the first packet output from the first buffer 23. The second packet output from the second buffer 24 is discarded.

[0066] The output timing is the timing at which the beginning of the first packet is output from the first buffer. The output timing is generated based on the output clock. The output timing is a timing with a period of time equal to the time it takes for one packet to be output from the output unit 27 in the output clock.

[0067] Figure 8 shows an example of the configuration of the output unit 27. The output unit 27 includes a timing generation unit 271, a selection unit 272, a null packet generation unit 273, and a packet output unit 274.

[0068] The timing generation unit 271 generates the output timing. The output timing is the timing at which the first packet is output from the output unit 27. The output clock is used to read the first packet from the first buffer 23 and the second packet from the second buffer 24. For example, if the output data width of the first buffer is 1 bit, the period of the output timing will be 204 × 8 times the period of the output clock (data amount (bits) of one packet of TS).

[0069] In this embodiment, it is assumed that the output timing used by delay adjustment device 20a and the output timing used by delay adjustment device 20b are synchronized. The method of synchronizing the output timings is arbitrary. For example, delay adjustment device 20a and delay adjustment device 20b may share the timing generation unit 271.

[0070] The null packet generation unit 273 generates a null packet.

[0071] The selection unit 272 selects a packet to be output from the output unit 27 based on the output conditions of the first packet at the output timing. The output conditions are based on the number of first packets that have arrived at the first buffer 23 after a first adjustment time has elapsed, and the number of second packets that have arrived at the second buffer 24 after a second adjustment time has elapsed. If the output conditions are met, the selection unit 272 selects the first packet to be output from the output unit 27. If the output conditions are not met, the selection unit 272 selects a null packet to be output from the output unit 27.

[0072] The number of first packets that have arrived at the first buffer 23 and have not yet been retrieved from the first buffer 23 after the first adjustment time has elapsed is sometimes called the first number of stagnant packets. Similarly, the number of second packets that have arrived at the second buffer 24 and have not yet been retrieved from the second buffer 24 after the second adjustment time has elapsed is sometimes called the second number of stagnant packets.

[0073] The selection unit 272 may receive information on the first number of backlogged packets and information on the second number of backlogged packets from the delay adjustment unit 26.

[0074] If the first buffer 23 has the configuration shown in Figure 5 and the second buffer 24 has the configuration shown in Figure 6, then the first number of pending packets is the number of packets stored in the first output buffer 232. In this case, the second number of pending packets is the number of packets stored in the second output buffer 242.

[0075] The selection unit 272 instructs the packet output unit 274 to output the first packet if one or more packets are accumulated in the first output buffer 232 and one or more packets are accumulated in the second output buffer 242. The selection unit 272 instructs the packet output unit 274 to output the first packet if there are fewer than one packet in the first output buffer 232 or fewer than one packet in the second output buffer 242.

[0076] Furthermore, when the selection unit 272 instructs the packet output unit 274 to output the first packet at the output timing, it outputs the first packet from the first buffer 23 to the packet output unit 274. Also, when the selection unit 272 instructs the packet output unit 274 to output the first packet at the output timing, it reads the second packet from the second buffer 24. The read second packet is discarded.

[0077] The packet output unit 274 outputs the packet instructed by the selection unit 272 at the output timing. If the packet output unit 274 is instructed by the selection unit 272 to output the first packet, it outputs the first packet output from the first buffer 23. Also, if the packet output unit 274 is instructed by the selection unit 272 to output a null packet, it outputs the null packet generated by the null packet generation unit 273.

[0078] By operating delay adjustment devices 20a and 20b as described above, the timing at which packet A is output from modulator 201a and the timing at which packet B is output from modulator 201b can be synchronized. In the above method, the delay times of packet A and packet B are roughly synchronized using the first adjustment time and the second adjustment time, and both packets are output at synchronized output timings. Therefore, the effort required to adjust the cable length of the input signals to the STL in order to adjust the delay time can be reduced.

[0079] Furthermore, in this disclosure, the output clock is a clock with a frequency that is an integer multiple of the modulation clock. Therefore, the delay time difference between packet A and packet B output from the delay adjustment device 20 is less than or equal to an integer fraction of the period of the modulation clock. As a result, the delay time difference of the stream modulated by the modulator 201 can be kept below the period of the modulation clock.

[0080] In addition, in the present disclosure, when the output condition of the first packet is not satisfied at the output timing, the output unit 27 outputs a null packet. As a result, the delay time of the first packet output from the delay adjustment device 20 can be made shorter than when the null packet is not output. When the null packet is not output, in order to avoid a state where there is no packet that can be output at the output timing, it is necessary to sufficiently delay the packet input to the delay adjustment device 20 so that fluctuations in the delay time of the packet input to the STL can be sufficiently absorbed. In the present disclosure, since a null packet is output when there is no packet that can be output at the output timing, the delay time of the first packet output from the delay adjustment device 20 can be made shorter than when the null packet is not output.

[0081] In addition, in the present disclosure, the reference clock is frequency-adjusted by the time stamp included in the first packet. As a result, the reference clock is synchronized with the packet input. Further, the delay adjustment device 20 generates a reference clock and an output clock from an internal clock. Further, the delay adjustment device 20 generates an output timing synchronized with the output clock. As a result, the delay adjustment device 20 can operate even when no frame synchronization signal or clock is input from the outside.

[0082] <Another configuration example of the STL and the delay adjustment device> In addition, FIG. 9 shows a configuration example of another STL300. The STL300 may have the configuration shown in FIG. 9. In FIG. 9, the illustration of the subsequent stage of the modulators 201a and 201b is omitted, but the subsequent stage of the STL300 also has the same configuration as the STL200 in FIG. 3.

[0083] In the STL300 shown in FIG. 9, packet A and packet B are input to the delay adjustment device 30, and packet A and packet B with adjusted delay times are output from the delay adjustment device 30.

[0084] Figure 10 also shows an example configuration of the delay adjustment device 30. The delay adjustment device 30 includes an output unit 37 instead of an output unit 27. The output unit 37 outputs two streams of packets (packet A and packet B) with adjusted delay times.

[0085] Figure 11 also shows an example configuration of the output unit 37. The output unit 37 includes a selection unit 372 instead of the selection unit 272. In addition, the output unit 37 includes a packet output unit 374 instead of the packet output unit 274.

[0086] The packet output unit 374 outputs two packets based on instructions from the selection unit 372 at the output timing. In this configuration, the first packet and the second packet are each of the two packet systems. In this configuration, the second packet is not a packet used for auxiliary purposes, but one of the two packet systems. Here, the first packet is packet A, and the second packet is packet B.

[0087] The selection unit 372 selects the first packet and the second packet to be output from the output unit 37 when the output conditions are met. If the output conditions are not met, it selects a null packet to be output from the output unit 37.

[0088] The selection unit 372 instructs the packet output unit 374 to output the first packet and the second packet if the number of first pending packets is 1 or more and the number of second pending packets is 1 or more. The selection unit 372 instructs the packet output unit 374 to output the first packet and the second packet if the number of first pending packets is less than 1 or the number of second pending packets is less than 1.

[0089] Furthermore, when the selection unit 372 instructs the packet output unit 374 to output the first packet and the second packet at the output timing, it causes the first packet to be output from the first buffer 23 to the packet output unit 374. Also, when the selection unit 372 instructs the packet output unit 374 to output the first packet and the second packet at the output timing, it causes the second packet to be output from the second buffer 24 to the packet output unit 374.

[0090] The packet output unit 374 outputs the packets instructed by the selection unit 372 at the output timing. When the selection unit 372 instructs the packet output unit 374 to output the first packet (packet A) output from the first buffer 23 and the second packet (packet B) output from the second buffer 24, respectively. Also, when the selection unit 372 instructs the packet output unit 374 to output a null packet, it outputs the null packet generated by the null packet generation unit 273 as each of the two packet systems.

[0091] As described above, the delay adjustment device 30 can operate in such a way that the timing at which packet A is input to modulator 201a and the timing at which packet B is input to modulator 201b can be synchronized.

[0092] <Operation Flow of Delay Adjustment Device> Next, an example of the operation flow of the delay adjustment device 20 will be described. Figures 12 to 15 show an example of the operation flow of the delay adjustment device 20.

[0093] The first receiving unit 21 of the delay adjustment device 20 stores the received first packet in the first buffer 23 (steps S201 and S202 in Figure 12). The second receiving unit 22 stores the received second packet in the second buffer 24 (steps S203 and S204 in Figure 13).

[0094] The calculation unit 25 of the delay adjustment device 20 calculates the first adjustment time and the second adjustment time at a predetermined timing, such as after startup (step S301 in Figure 14).

[0095] The delay adjustment unit 26 then controls the packet output of the first packet to be delayed from the time the first packet arrives at the first buffer 23 until a first adjustment time has elapsed. The delay adjustment unit 26 also controls the packet output of the second packet to be delayed from the time the second packet arrives at the second buffer 24 until a second adjustment time has elapsed (step S302 in Figure 15).

[0096] Furthermore, the output unit 27 retrieves the first packet from the first buffer 23 at the output timing, after the first adjustment time has elapsed since its arrival in the first buffer 23. Also, the output unit 27 retrieves the second packet from the second buffer 24 at the same timing as the first packet is output from the first buffer 23, after the second adjustment time has elapsed since its arrival in the second buffer 24 (step S303 in Figure 15). The output unit 27 outputs the first packet retrieved from the first buffer 23 to the next stage.

[0097] When a delay adjustment device 20a is provided for modulator 201a and a delay adjustment device 20b is provided for modulator 201b, the second packet output from the second buffer 24 is discarded. In other words, the second packet (packet B) in delay adjustment device 20a is discarded in delay adjustment device 20a. Similarly, the second packet (packet A) in delay adjustment device 20b is discarded in delay adjustment device 20b. As shown in Figure 9, when the first packet (packet A) output from delay adjustment device 30 is input to modulator 201a, and the second packet (packet B) output from delay adjustment device 30 is input to modulator 201b, the output unit 37 outputs the second packet (packet B) to modulator 201b.

[0098] Next, a specific example of the processing flow of the delay adjustment device 20 for calculating the first adjustment time and the second adjustment time in step S301 of Figure 14 will be described. Figures 17 to 19 show examples of the operation flow of the delay adjustment device 20 for calculating the first adjustment time and the second adjustment time. The calculation unit 25 calculates the first adjustment time and the second adjustment time based on the first timestamp and the second timestamp.

[0099] The first timestamp detection unit 251 detects the first timestamp from the first packet received by the first receiving unit 21 (step S401 in Figure 17). The first timestamp detection unit 251 also stores the first counter value in the first counter value storage unit 253 (step S402). The delay time calculation unit 255 calculates the first delay time by subtracting the first timestamp from the first counter value (step S403). The calculation unit 25 repeats steps S401 to S403, for example, until a predetermined time has elapsed since the start of calculating the first adjustment time and the second adjustment time (NO in step S404).

[0100] Furthermore, the second timestamp detection unit 252 detects a second timestamp from the second packet received by the second receiving unit 22 (step S405 in Figure 18). The second timestamp detection unit 252 also stores the second counter value in the second counter value storage unit 254 (step S406). The delay time calculation unit 255 calculates the second delay time by subtracting the second timestamp from the second counter value (step S407). The calculation unit 25 repeats steps S405 to S407, for example, until a predetermined time has elapsed since the start of calculating the first adjustment time and the second adjustment time (NO in step S408).

[0101] Then, for example, when a predetermined time has elapsed since the calculation of the first adjustment time and the second adjustment time began (YES in step S409 of Figure 19), the delay time calculation unit 255 performs statistical processing on the first delay time for the first packet received at the predetermined time. The delay time calculation unit 255 also performs statistical processing on the second delay time for the second packet received at the predetermined time. Then, the delay time calculation unit 255 determines the fixed delay time based on the larger of the first and second delay times after the statistical processing (step S410).

[0102] Furthermore, the delay time calculation unit 255 calculates the first adjustment time and the second adjustment time (step S411). The delay time calculation unit 255 calculates the first adjustment time by subtracting the first delay time from the fixed delay time. Furthermore, the delay time calculation unit 255 calculates the second adjustment time by subtracting the second delay time from the fixed delay time.

[0103] Next, a specific example of the processing flow of the delay adjustment device 20 regarding packet output in step S303 of Figure 16 will be described. Figure 20 shows an example of the operation flow of the delay adjustment device 20 regarding packet output.

[0104] The selection unit 272 selects the packets to be output from the output unit 27 based on the first number of lingering packets and the second number of lingering packets at the output timing.

[0105] If the number of first backlogged packets is 1 or more (YES in step S501) and the number of second backlogged packets is 1 or more (YES in step S502), the selection unit 272 instructs the packet output unit 274 to make the packet output by the packet output unit 274 the first packet (step S503). If the number of first backlogged packets is less than 1 (NO in step S501) or the number of second backlogged packets is less than 1 (NO in step S502), the selection unit 272 instructs the packet output by the packet output unit 274 to make the packet output by the packet output unit 274 a null packet (step S504).

[0106] Furthermore, when the selection unit 272 instructs the packet output unit 274 to output the first packet, it retrieves the first packet from the first buffer 23 and the second packet from the second buffer 24 (step S505).

[0107] The packet output unit 274 outputs the packets instructed by the selection unit 272. If the selection unit 272 instructs the packet output unit 274 to output the first packet, the packet output unit 274 outputs the first packet taken from the first buffer 23 (step S506). Also, if the selection unit 272 instructs the packet output unit 274 to output a null packet, the packet output unit 274 outputs a null packet generated by the null packet generation unit 273 (step S507).

[0108] As shown in Figure 9, when the first packet (packet A) output from the delay adjustment device 30 is input to the modulator 201a, and the second packet (packet B) output from the delay adjustment device 30 is input to the modulator 201b, the selection unit 372 instructs the packet output unit 374 to output the first and second packets in step S503. The packet output unit 274 then outputs the first and second packets in step S506.

[0109] As described above, in the second embodiment of the present disclosure, the delay adjustment device 20 includes a first receiving unit 21, a second receiving unit 22, a first buffer 23, a second buffer 24, a calculation unit 25, a delay adjustment unit 26, and an output unit 27. The first receiving unit 21 stores the received first packet in the first buffer 23. The second receiving unit 22 stores the received second packet in the second buffer 24. The calculation unit 25 calculates the first adjustment time for the first packet and the second adjustment time for the second packet based on the first timestamp, the second timestamp, and a counter value. The first timestamp is the timestamp contained in the first packet. The second timestamp is the timestamp contained in the second packet. The counter value is counted up by a reference clock. The delay adjustment unit 26 controls the packet output of the first packet from the first buffer 23 from the time the first packet arrives in the first buffer 23 until the first adjustment time has elapsed. Furthermore, the delay adjustment unit 26 controls the packet output of the second packet from the second buffer 24 from the time the second packet arrives at the second buffer 24 until the second adjustment time has elapsed. The output unit 27 takes the first packet from the first buffer 23 and outputs it at the output timing. Also, at the same timing as the output timing, the output unit 27 takes the second packet from the second buffer 24. The output timing is generated based on the output clock for packet output.

[0110] In this way, the delay adjustment device 20 adjusts the delay time difference between the first packet taken from the first buffer 23 and the second packet taken from the second buffer 24, based on the first adjustment time and the second adjustment time. Then, at the output timing, the delay adjustment device 20 takes out the first packet and the second packet at the same time. The output timing is generated based on the output clock for packet output. This makes it possible to take out and output packets from the buffers of both systems at the same time. Therefore, it becomes possible to synchronize the delay times of the two broadcast streams.

[0111] [Example Hardware Configuration] This section describes an example of hardware resource configurations for realizing the delay adjustment devices (10, 20, 30) in each embodiment of the present disclosure described above using a single information processing device (computer). Note that the delay adjustment device may be realized using at least two information processing devices, either physically or functionally. Furthermore, the delay adjustment device may be realized as a dedicated device. Also, only some of the functions of the delay adjustment device may be realized using an information processing device.

[0112] Figure 22 is a schematic diagram showing an example of the hardware configuration of an information processing device capable of realizing the delay adjustment device of each embodiment of the present disclosure. The information processing device 90 includes a communication interface 91, an input / output interface 92, an arithmetic unit 93, a storage device 94, a non-volatile storage device 95, and a drive device 96.

[0113] For example, the first receiving unit 11, the second receiving unit 12, and the output unit 17 in Figure 1 can be implemented using the communication interface 91 and the arithmetic unit 93. The calculation unit 15 and the delay adjustment unit 16 can also be implemented using the arithmetic unit 93. Furthermore, the first buffer 13 and the second buffer 14 can be implemented using the storage device 94.

[0114] The communication interface 91 is a communication means for the delay adjustment device of each embodiment to communicate with an external device by wire and / or wireless. If the delay adjustment device is implemented using at least two information processing devices, these devices may be connected via the communication interface 91 to enable mutual communication.

[0115] The input / output interface 92 is a human-machine interface, such as a keyboard as an example of an input device, or a display as an output device.

[0116] The arithmetic unit 93 is implemented by a general-purpose CPU (Central Processing Unit) or microprocessor, as well as multiple electrical circuits. The arithmetic unit 93 can, for example, read various programs stored in the non-volatile memory device 95 into the memory device 94 and execute processing according to the read programs.

[0117] The storage device 94 is a memory device such as RAM (Random Access Memory) that can be accessed by the arithmetic unit 93, and stores programs and various data. The storage device 94 may also be a volatile memory device.

[0118] The non-volatile storage device 95 is a non-volatile storage device such as ROM (Read Only Memory) or flash memory, and is capable of storing various programs and data.

[0119] The drive device 96 is, for example, a device that processes data reading and writing to the recording medium 97, which will be described later.

[0120] The recording medium 97 is any recording medium capable of recording data, such as an optical disc, magneto-optical disc, or semiconductor flash memory.

[0121] Each embodiment of the present disclosure may be implemented, for example, by configuring a delay adjustment device with the information processing device 90 illustrated in Figure 21, and supplying this delay adjustment device with a program capable of realizing the functions described in each embodiment above.

[0122] In this case, the embodiment can be realized by having the arithmetic unit 93 execute the program supplied to the delay adjustment device. Furthermore, it is also possible to configure some, rather than all, of the functions of the delay adjustment device in the information processing device 90.

[0123] Furthermore, the delay adjustment device may be configured such that the above program is recorded on the recording medium 97, and the program is stored in the non-volatile storage device 95 as appropriate during the shipping or operation phase of the delay adjustment device. In this case, the method of supplying the above program may be to install it into the delay adjustment device using an appropriate jig during the manufacturing phase before shipping or during the operation phase. Alternatively, the method of supplying the above program may be to use a general procedure such as downloading it from an external source via a communication line such as the Internet.

[0124] Some or all of the above embodiments may also be described as follows, but are not limited to the following:

[0125] (Note 1) A first receiving unit that stores the first received packet in a first buffer, A second receiving unit that stores the received second packet in a second buffer, A calculation unit that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp which is a timestamp contained in the first packet, a second timestamp which is a timestamp contained in the second packet, and a counter value that is counted up by a reference clock, A delay adjustment unit that controls the packet output of the first packet from the first buffer from the time the first packet arrives in the first buffer until the first adjustment time has elapsed, and controls the packet output of the second packet from the second buffer from the time the second packet arrives in the second buffer until the second adjustment time has elapsed. An output unit that, at an output timing generated based on an output clock for packet output, takes the first packet from the first buffer and outputs it, and at the same timing as the output timing, takes the second packet from the second buffer. A delay adjustment device equipped with the following features.

[0126] (Note 2) The output clock is a clock having a frequency that is an integer multiple of the modulation clock. The delay adjustment device described in Appendix 1.

[0127] (Note 3) The aforementioned output timing is a timing whose period is defined as the time it takes for one packet to be output in synchronization with the output clock. The delay adjustment device described in Appendix 1 or Appendix 2.

[0128] (Note 4) The reference clock's frequency is adjusted by the first timestamp. A delay adjustment device as described in any one of the appendices 1 to 3.

[0129] (Note 5) Clock generation unit that generates the reference clock and the output clock from the internal clock. A delay adjustment device described in any one of the appendices 1 to 4, further comprising the above.

[0130] (Note 6) The output unit outputs a null packet if the output conditions for the first packet are not met at the output timing. A delay adjustment device as described in any one of the appendices 1 through 5.

[0131] (Note 7) The output conditions are based on a first number of stagnant packets, which is the number of first packets that have not been removed from the first buffer after the first adjustment time has elapsed since their arrival at the first buffer, and a second number of stagnant packets, which is the number of second packets that have not been removed from the second buffer after the second adjustment time has elapsed since their arrival at the second buffer. The delay adjustment device described in Appendix 6.

[0132] (Note 8) The output conditions are that the number of first pending packets is 1 or more and the number of second pending packets is 1 or more. The delay adjustment device described in Appendix 7.

[0133] (Note 9) The aforementioned first buffer includes a first basic adjustment buffer and a first output buffer, The aforementioned second buffer includes a second basic adjustment buffer and a second output buffer. The aforementioned delay adjustment unit is The first packet input to the first basic adjustment buffer is taken out of the first basic adjustment buffer and input to the first output buffer at the time when the first adjustment time has elapsed from the time the first packet arrived at the first basic adjustment buffer. The second packet input to the second basic adjustment buffer is taken out of the second basic adjustment buffer and input to the second output buffer at the time when the second adjustment time has elapsed from the time the second packet arrived at the second basic adjustment buffer. A delay adjustment device as described in any one of the appendices 1 through 8.

[0134] (Note 10) The calculation unit described above, The first delay time is calculated by subtracting the first timestamp from the first counter value, which is the counter value at the time the first timestamp was detected. The second delay time is calculated by subtracting the second timestamp from the second counter value, which is the counter value at the time the second timestamp was detected. A fixed delay time is determined based on the larger of the first delay time and the second delay time. The first adjustment time is calculated by subtracting the first delay time from the fixed delay time. The second adjustment time is calculated by subtracting the second delay time from the fixed delay time. A delay adjustment device as described in any one of the appendices 1 through 9.

[0135] (Note 11) The delay adjustment device, Based on the first timestamp, which is the timestamp contained in the first received packet, the second timestamp, which is the timestamp contained in the second received packet, and a counter value that is counted up by the reference clock, the first adjustment time of the first packet and the second adjustment time of the second packet are calculated. The system performs the following controls: delaying the packet output of the first packet from the first buffer, which stores the first packet, from the time the first packet arrives in the first buffer, which stores the second packet, until the time the first adjustment period has elapsed; and delaying the packet output of the second packet from the second buffer, which stores the second packet, from the time the second packet arrives in the second buffer, which stores the second packet, until the time the second adjustment period has elapsed. At an output timing generated based on an output clock for packet output, the first packet is taken from the first buffer and output, and at the same timing as the output timing, the second packet is taken from the second buffer. Delay adjustment method.

[0136] (Note 12) On the computer, A calculation function that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp, which is a timestamp contained in the first received packet, a second timestamp, which is a timestamp contained in the second received packet, and a counter value that is counted up by a reference clock, A delay adjustment function that controls the packet output of the first packet from the first buffer, which stores the first packet, from the time the first packet arrives in the first buffer, which stores the first packet, until the time the first adjustment period has elapsed; and controls the packet output of the second packet from the second buffer, which stores the second packet, from the time the second packet arrives in the second buffer, which stores the second packet, until the time the second adjustment period has elapsed. An output function that, at an output timing generated based on an output clock for packet output, retrieves the first packet from the first buffer and outputs it, and at the same timing as the output timing, retrieves the second packet from the second buffer. A delay adjustment program that achieves this.

[0137] Furthermore, some or all of the configurations described in Appendices 2 to 10, which are subordinate to Appendice 1 above, may also be subordinate to Appendices 11 and 12 in the same way as those described in Appendices 2 to 10. Moreover, not limited to Appendices 1, 11, and 12, some or all of the configurations described as appendices may also be subordinate to various hardware, software, various recording means for recording software, or systems, without departing from the embodiments described above.

[0138] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be made as can be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate. [Explanation of Symbols]

[0139] 10, 20, 30 Delay Adjustment Device 11, 21 First receiving unit 12, 22 Second receiving section 13, 23 First buffer 14, 24 Second buffer 15, 25 Calculation section 16, 26 Delay adjustment section 17, 27, 37 Output section 28 Clock generation unit 29 Counter section 90 Information Processing Equipment 91 Communication Interface 92 Input / Output Interfaces 93 Arithmetic unit 94 Storage device 95 Non-volatile memory devices 96 Drive unit 97 Recording media 201 Modulator 202 Transmitter 203 SHF Switch 204 Antenna 205 Antenna 206 SHF distributor 207 Receiver 208 Demodulator 231 First Basic Adjustment Buffer 232 First output buffer 241 Second Basic Adjustment Buffer 242 Second output buffer 251 First timestamp detection unit 252 Second timestamp detection unit 253 First counter value storage unit 254 Second counter value storage unit 255 Delay Time Calculation Unit 271 Timing generation unit 272, 372 Selection section 273 Null packet generation unit 274, 374 packet output section

Claims

1. A first receiving unit that stores the first received packet in a first buffer, A second receiving unit that stores the received second packet in a second buffer, A calculation unit that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp which is a timestamp contained in the first packet, a second timestamp which is a timestamp contained in the second packet, and a counter value that is counted up by a reference clock, A delay adjustment unit that controls the packet output of the first packet from the first buffer from the time the first packet arrives in the first buffer until the first adjustment time has elapsed, and controls the packet output of the second packet from the second buffer from the time the second packet arrives in the second buffer until the second adjustment time has elapsed. An output unit that, at an output timing generated based on an output clock for packet output, takes the first packet from the first buffer and outputs it, and at the same timing as the output timing, takes the second packet from the second buffer. A delay adjustment device equipped with the following features.

2. The output clock is a clock having a frequency that is an integer multiple of the modulation clock. The delay adjustment device according to claim 1.

3. The output timing is defined as a timing period in which the time it takes for one packet to be output in synchronization with the output clock. A delay adjustment device according to claim 1 or claim 2.

4. The reference clock's frequency is adjusted according to the first timestamp. A delay adjustment device according to claim 1 or claim 2.

5. Clock generation unit that generates the reference clock and the output clock from the internal clock. The delay adjustment device according to claim 1 or claim 2, further comprising:

6. The output unit outputs a null packet if the output conditions for the first packet are not met at the output timing. A delay adjustment device according to claim 1 or claim 2.

7. The aforementioned first buffer includes a first basic adjustment buffer and a first output buffer, The aforementioned second buffer includes a second basic adjustment buffer and a second output buffer. The aforementioned delay adjustment unit is The first packet input to the first basic adjustment buffer is taken out of the first basic adjustment buffer and input to the first output buffer at the time when the first adjustment time has elapsed from the time the first packet arrived at the first basic adjustment buffer. The second packet input to the second basic adjustment buffer is taken out of the second basic adjustment buffer and input to the second output buffer at the time when the second adjustment time has elapsed from the time the second packet arrived at the second basic adjustment buffer. A delay adjustment device according to claim 1 or claim 2.

8. The calculation unit described above, The first delay time is calculated by subtracting the first timestamp from the first counter value, which is the counter value at the time the first timestamp was detected. The second delay time is calculated by subtracting the second timestamp from the second counter value, which is the counter value at the time the second timestamp was detected. A fixed delay time is determined based on the larger of the first delay time and the second delay time. The first adjustment time is calculated by subtracting the first delay time from the fixed delay time. The second adjustment time is calculated by subtracting the second delay time from the fixed delay time. A delay adjustment device according to claim 1 or claim 2.

9. The delay adjustment device, Based on the first timestamp, which is the timestamp contained in the first received packet, the second timestamp, which is the timestamp contained in the second received packet, and a counter value that is counted up by the reference clock, the first adjustment time of the first packet and the second adjustment time of the second packet are calculated. The system performs the following controls: delaying the packet output of the first packet from the first buffer, which stores the first packet, from the time the first packet arrives in the first buffer, which stores the second packet, until the time the first adjustment period has elapsed; and delaying the packet output of the second packet from the second buffer, which stores the second packet, from the time the second packet arrives in the second buffer, which stores the second packet, until the time the second adjustment period has elapsed. At an output timing generated based on an output clock for packet output, the first packet is taken from the first buffer and output, and at the same timing as the output timing, the second packet is taken from the second buffer. Delay adjustment method.

10. On the computer, A calculation function that calculates a first adjustment time for the first packet and a second adjustment time for the second packet based on a first timestamp, which is a timestamp contained in the first received packet, a second timestamp, which is a timestamp contained in the second received packet, and a counter value that is counted up by a reference clock, A delay adjustment function that controls the packet output of the first packet from the first buffer, which stores the first packet, from the time the first packet arrives in the first buffer, which stores the first packet, until the time the first adjustment period has elapsed; and controls the packet output of the second packet from the second buffer, which stores the second packet, from the time the second packet arrives in the second buffer, which stores the second packet, until the time the second adjustment period has elapsed. An output function that, at an output timing generated based on an output clock for packet output, retrieves the first packet from the first buffer and outputs it, and at the same timing as the output timing, retrieves the second packet from the second buffer. A delay adjustment program that achieves this.

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