Vertical and horizontal broadcast of shared operands

Abstract

The present invention provides an apparatus, method, and storage medium for reducing the bandwidth of a memory fabric and increasing its efficiency in an array processor system. [Solution] The array processor 300 includes processor element arrays 311 to 384 distributed in rows and columns and performing operations on parameter values; a memory interface that broadcasts a set of parameter values ​​to mutually exclusive subsets of rows and columns of the processor element arrays; SIMD units 310 to 380 that include a subset of the processor element array for the corresponding row; and DMA engines 301 to 304 interconnected with mutually exclusive subsets of the processor element arrays 311 to 384.

Description

[Background technology]

[0001] Graphics Processing Units (GPUs) and other multithreaded processing units typically implement multiple processing elements (also called processor cores or compute units) that simultaneously execute multiple instances of a single program on multiple datasets. For example, a processing element can implement the Single-Instruction-Multiple-Data (SIMD) protocol to simultaneously execute the same instruction on multiple datasets using multiple compute units. Therefore, a processing element is called a SIMD unit. A hierarchical execution model is used to fit the hierarchy implemented in the hardware. The execution model defines the kernel of instructions executed by all waves (also called wavefronts, threads, streams, or work items). In some cases, the processing power of a GPU or other multithreaded processing unit implemented within a processing system is complemented by one or more accelerators that also implement the SIMD protocol. An example of an accelerator circuit implemented within a GPU or other multithreaded processing unit is an array processor.

[0002] In one embodiment, the device includes a processor element array distributed in rows and columns, the processor element array being configured to perform operations on parameter values, and further includes a memory interface configured to broadcast a set of parameter values ​​to mutually exclusive subsets of rows and columns of the processor element array.In various embodiments, the processor element array comprises a vector arithmetic logic unit (ALU) processor, the memory interface comprises a direct memory access (DMA) engine, each of the memory interfaces broadcasts parameter values to the corresponding rows and corresponding columns of the processor element array, and / or the first memory interface of the memory interfaces broadcasts a first parameter value to the processor element array within the first row and the first column, the second memory interface of the memory interfaces broadcasts a second parameter value to the processor element array within the second row and the second column, the memory interface is connected to mutually exclusive subsets of the rows and columns of the processor element array via individual physical connections, the memory interface is configured to simultaneously populate parameter values into registers associated with the processor element array within the mutually exclusive subsets of the rows and columns, the apparatus further includes a single instruction multiple data (SIMD) unit comprising a subset of the processor element array within the corresponding row, the memory interface broadcasts parameter values to the SIMD unit comprising the processor element array within the row associated with the memory interface, the apparatus further includes a workgroup processor comprising a subset of the SIMD units, the memory interface broadcasts parameter values to the columns of the processor element array implemented across the SIMD units within the workgroup processor, and / or the apparatus further includes a memory fabric configured to interconnect with an external memory storing parameter values, the memory interface is configured to access parameter values from the external memory via the memory fabric.

[0003] In another embodiment, the method includes fetching parameter values ​​from memory via a memory interface, broadcasting the parameter values ​​from the memory interface to mutually exclusive subsets of rows and columns of a processor element array, and performing operations on the parameter values ​​in the processor element array.

[0004] In various embodiments, broadcasting a parameter value from a memory interface includes broadcasting the parameter value from each of the memory interfaces to a processor element array in a corresponding row and a corresponding column, broadcasting a parameter value includes broadcasting a first parameter value from a first memory interface to a processor element array in a first row and a first column, broadcasting a parameter value includes broadcasting a second parameter value from a second memory interface to a processor element array in a second row and a second column, broadcasting a parameter value includes broadcasting the parameter value via separate physical connections between the memory interface and the corresponding row and column, broadcasting a parameter value via rows and Broadcasting a parameter value involves populating the parameter value in registers associated with processor element arrays in mutually exclusive subsets of columns, where each subset of processor element arrays in a row is implemented within a corresponding single-instruction multiple data (SIMD) unit, and broadcasting the parameter value involves broadcasting the parameter value to a SIMD unit having processor element arrays in a row associated with a memory interface, and / or where a subset of SIMD units is implemented within a corresponding workgroup processor, and broadcasting the parameter value involves broadcasting the parameter value to columns of processor element arrays implemented across SIMD units within the workgroup processor, and / or fetching the parameter value involves accessing the parameter value via a memory fabric configured to interconnect with memory storing the parameter value.

[0005] This disclosure will be better understood by referring to the accompanying drawings, and its many features and advantages may become apparent to those skilled in the art. The use of the same reference numerals in different drawings indicates similar or identical items. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram of a processing system that performs vertical and horizontal broadcasting of shared operands in an array processor, according to several embodiments. [Figure 2] This is a partial block diagram of a processing system that supports vertical and horizontal broadcasting of parameter values, according to several embodiments. [Figure 3] This is a block diagram of an array processor that implements vertical and horizontal broadcasting of parameter values ​​to mutually exclusive subsets of a processor element array, according to several embodiments. [Figure 4] This is a flowchart illustrating a method for broadcasting parameter values ​​to rows or columns of a processor element array, according to several embodiments. [Modes for carrying out the invention]

[0007] An array processor system includes one or more Workgroup Processors (WGPs), each containing a set of SIMD units. For example, an array processor may include four WGPs, each implementing four SIMD units. A SIMD unit includes a set of processor element arrays that perform vector operations, such as multiply-accumulate operations, on vectors or matrices. For example, a SIMD unit may include four processor element arrays in each processor element array, and include an 8x8 array of circuits for performing operations (such as multiply-accumulate operations) on pairs of input vectors. As used herein, the term “vector” may also refer to individual rows or columns of a matrix. Furthermore, the term “matrix” generally refers to an array of values ​​containing vectors, which is understood as a 1xN matrix. Processor element arrays in an array processor system perform kernel operations, such as matrix multiplication, on matrices having dimensions corresponding to the number of processor element arrays. For example, an array processor including four WGPs, each containing four SIMD units composed of four processor element arrays, can multiply a 64x64 matrix.

[0008] Input values ​​for kernel operations performed by the processor element array are retrieved from memory via the memory fabric by one or more direct memory access (DMA) engines, and the DMA engines write output values ​​back to memory via the memory fabric. For example, each of the four WGPs may include a pair of DMA engines that fetch the corresponding pairs of values ​​for the SIMD units. Many kernel operations performed on matrices by array processor systems reuse the same parameter values ​​multiple times. For example, multiply-accumulate operations used to implement machine learning applications may reuse the same vector or matrix values ​​several times when performing vector or matrix multiplication. Repeatedly prefetching the same parameters consumes considerable memory bandwidth within the array processor system, reducing the efficiency of the array processor system when the system is bandwidth-limited.

[0009] Figures 1 to 4 disclose embodiments of an array processor system that use a direct memory access (DMA) engine to broadcast sets of parameter values ​​to processor element arrays in mutually exclusive rows and columns of the array processor system, thereby reducing the bandwidth consumed by fetching parameters to the processor element arrays. The processor element arrays are implemented as vector operation logic unit (ALU) processors. In some embodiments, each DMA engine broadcasts parameter values ​​to one row and one column of the processor element array. If the array processor system supports multiple workgroup processors (WGPs), each DMA engine broadcasts parameter values ​​to a row of the processor element array implemented in a SIMD unit associated with the DMA engine and to a column of the processor element array implemented across the SIMD units of the WGPs. For example, the first DMA engine broadcasts parameter values ​​to the first row and first column of the processor element array, the second DMA engine broadcasts parameter values ​​to the second row and second column of the processor element array, the third DMA engine broadcasts parameter values ​​to the third row and third column of the processor element array, and so on. By associating DMA engines with mutually exclusive sets of rows / columns, simultaneous population of registers holding input values ​​for different processor element arrays becomes possible. Consequently, the bandwidth of the memory fabric consumed by fetching reused parameter values ​​is reduced, and the efficiency of the array processor system is increased.

[0010] Figure 1 is a block diagram of a processing system 100 that performs vertical and horizontal broadcasting of shared operands in an array processor 101, according to several embodiments. The processing system 100 includes, or has access to, memory 105 or other storage components implemented using non-temporary computer-readable storage media such as Dynamic Random-Access Memory (DRAM). However, in some cases, memory 105 may also be implemented using other types of memory, including Static Random-Access Memory (SRAM), non-volatile RAM, etc. Memory 105 is called external memory because it is implemented outside the processing units implemented in the processing system 100. The processing system 100 also includes a bus 110 for supporting communication between entities implemented in the processing system 100, such as memory 105. Some embodiments of the processing system 100 include other buses, bridges, switches, routers, etc., which are not shown in Figure 1 for clarity.

[0011] The techniques described herein are used in various embodiments with any of the various parallel processors (e.g., vector processors, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), non-scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, and other multithreaded processing units). Figure 1 shows an example of a parallel processor, in particular a GPU 115, according to several embodiments. The GPU 115 renders an image for presentation on a display 120. For example, the GPU 115 renders an object to generate pixel values ​​to be provided to the display 120, and the display 120 uses the pixel values ​​to display an image representing the rendered object. The CPU 115 implements multiple processor cores 121, 122, 123 (collectively referred to herein as "processor cores 121-123") that execute instructions simultaneously or in parallel. Some embodiments of processor cores 121-123 operate as SIMD units that perform the same operation on different datasets. The number of processor cores 121-123 implemented within the GPU 115 is a matter of design choice, and some embodiments of the GPU 115 may contain more or fewer processor cores than those shown in Figure 1. Some embodiments of the GPU 115 are used for general-purpose computing. The GPU 115 executes instructions such as program code 125 stored in memory 105, and the GPU 115 stores information such as the results of the executed instructions in memory 105.

[0012] The processing system 100 also includes a central processing unit (CPU) 130 connected to a bus 110 and therefore communicating with the GPU 115 and memory 105 via the bus 110. The CPU 130 implements a plurality of processor cores 131, 132, 133 (collectively referred to herein as "processor cores 131-133") that execute instructions simultaneously or in parallel. Some embodiments of processor cores 131-133 operate as SIMD units that perform the same operation on different datasets. The number of processor cores 131-133 implemented in the CPU 130 is a matter of design choice, and some embodiments include more or fewer processor cores than those shown in Figure 1. Processor cores 131-133 execute instructions such as program code 135 stored in memory 105, and the CPU 130 stores information such as the results of the executed instructions in memory 105. The CPU 130 can also initiate graphics processing by issuing a draw call to the GPU 115. Some embodiments of the CPU 130 implement multiple processor cores (not shown in Figure 1 for clarity) that execute instructions simultaneously or in parallel.

[0013] The input / output (I / O) engine 145 handles input or output operations associated with the display 120 and other elements of the processing system 100, such as a keyboard, mouse, printer, and external disk. The I / O engine 145 is coupled to a bus 110 so that it can communicate with memory 105, GPU 115, or CPU 130. In the illustrated embodiment, the I / O engine 145 reads information stored in an external storage component 150, which is implemented using a non-temporary computer-readable storage medium such as a Compact Disc (CD) or Digital Video Disc (DVD). The I / O engine 145 can also write information, such as the results of processing by the GPU 115 or CPU 130, to the external storage component 150.

[0014] The array processor 101 complements the processing power of the GPU 115, and possibly the CPU 130. The set of processor element arrays 155 is used to perform operations that accelerate or improve the performance of the GPU 115 by allowing the GPU 115 to offload tasks to one or more of the processor element arrays in the set 155. The processor element array then returns the results to the GPU 115. In some embodiments, the processor element array is implemented as a vector arithmetic logic unit (ALU) that includes circuitry for performing arithmetic and bitwise operations on integer binary numbers. Thus, the processor element array takes one or more inputs (or operands) and generates a corresponding output based on the operands and opcodes indicating the operations performed by the processor element array. The operands, opcodes, and other status values ​​are stored in registers associated with the processor element array.

[0015] The processor element arrays within set 155 are distributed across rows and columns. As described below, the array processor 101 also includes a memory interface that reads parameter values ​​(e.g., from memory 105) and broadcasts the set of parameter values ​​to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor 101 includes single-instruction multiple data (SIMD) units containing a subset of the processor element arrays in the corresponding rows, a workgroup processor (WGP) containing a subset of the SIMD units, and a memory fabric configured to interconnect with external memory (e.g., memory 105) that stores the parameter values. The memory interface broadcasts the parameter values ​​to SIMD units containing the processor element arrays in the rows associated with the memory interface and the columns of the processor element arrays implemented across the SIMD units in the WGP. The memory interface accesses the parameter values ​​from the external memory via the memory fabric.

[0016] Figure 2 is a block diagram of a portion (part) 200 of a processing system supporting vertical and horizontal broadcasting of parameter values, according to several embodiments. Part 200 is used to implement several embodiments of the array processor 101 shown in Figure 1. Part 200 includes a set of WGPs 205, 206, 207, 208 (collectively referred to herein as "WGP205-208") that implement pairs of compute units 210, 215. Although compute units 210, 215 are shown only within WGP205 for clarity, WGP206-208 also include pairs of compute units. Some embodiments of Part 200 implement more or fewer WGPs and corresponding compute units.

[0017] WGP205-208 includes SIMD units 220, 221, 222, and 223 (collectively referred to herein as “SIMD units 220-223”) and memory interfaces such as direct memory access (DMA) engines 225 and 230. Some embodiments of the memory interfaces also include TA / TD logic interfaces and TCP interfaces that operate in conjunction with the DMA engines 225 and 230. Each of the SIMD units 220-223 implements a portion of the set of processor element arrays. In the illustrated embodiments, SIMD unit 221 includes a subset 235 of processor element arrays 240, 241, 242, and 243 (collectively referred to herein as “processor element arrays 240-243”), and SIMD unit 223 includes a subset 245 of processor element arrays 250, 251, 252, and 253 (collectively referred to herein as “processor element arrays 250-253”). SIMD units 220 and 222 also include, for clarity, other subsets of the processor element array not shown in Figure 2.

[0018] The DMA engines 225 and 230 are connected to a memory fabric 255 that provides one or more channels between the DMA engines 225 and 230 and random-access memory (RAM) such as SRAM 260. In the illustrated embodiment, SRAM 260 is connected to system memory 265 such as memory 105 shown in Figure 1. The portion 200 also includes an asynchronous compute engine 270 that communicates with WGPs 205-208 and the memory fabric 255.

[0019] The DMA engines 225 and 230 fetch parameter values ​​from the SRAM 260 or system memory 265 via the memory fabric 255. The fetched parameter values ​​are then broadcast to mutually exclusive subsets of processor element arrays, including processor element arrays 240-243 and 250-253. In some embodiments, the DMA engines 225 and 230 broadcast parameter values ​​to processor element arrays in corresponding rows and columns of the set of processor element arrays. For example, the DMA engine 225 may broadcast a first parameter value to a processor element array in a first row (e.g., the row containing processor element arrays 240-243) and a first column (e.g., the column containing processor element arrays 240 and 250). The DMA engine 230 may broadcast a second parameter value to a processor element array in a second row (e.g., processor element arrays 250-253) and a second column (e.g., processor element arrays 241 and 251). In this case, a subset of processor element arrays 240-243 and one row are mutually exclusive with respect to a subset of processor element arrays 250-253 in another row. A subset of processor element arrays in a column containing processor element arrays 240, 250 is mutually exclusive with respect to a subset of processor element arrays in a column containing processor element arrays 241, 251. Therefore, DMA engines 225, 230 simultaneously populate the registers associated with the processor element arrays in the mutually exclusive subsets of rows and columns with their corresponding fetched parameter values.

[0020] Figure 3 is a block diagram of an array processor 300 that implements vertical and horizontal broadcasting of parameter values ​​to mutually exclusive subsets of a processor element array in several embodiments. The array processor 300 is used to implement several embodiments of the array processor 101 shown in Figure 1. The array processor 300 includes DMA engines 301, 302, 303, 304 (collectively referred to herein as "DMA engines 301-304") that fetch parameters from memory such as memory 105 shown in Figure 1 or memory 260, 265 shown in Figure 2. Furthermore, the array processor 300 includes SIMD units 310, 320, 330, 340, 350, 360, 370, and 380, which are implemented using corresponding subsets of processor element arrays 311, 312, 313, 314, 321, 322, 323, 324, 331, 332, 333, 334, 341, 342, 343, 344, 351, 352, 353, 354, 361, 362, 363, 364, 371, 372, 373, 374, 381, 382, ​​383, and 384 (collectively referred to herein as "processor element arrays 311-384" for brevity, and therefore the hyphens are not intended to indicate a consecutive sequence of numbers between 311 and 384). Several embodiments of the SIMD units 310, 320, 330, 340, 350, 360, 370, and 380 are implemented within different WGPs. For example, a first WGP may implement SIMD units 310 and 320, a second WGP may implement SIMD units 330 and 340, a third WGP may implement SIMD units 350 and 360, and a fourth WGP may implement SIMD units 370 and 380.

[0021] DMA engines 301-304 are interconnected with mutually exclusive subsets of processor element arrays 311-384. In the illustrated embodiment, DMA engines 301-304 are interconnected with mutually exclusive rows and columns within the arrays of processor element arrays 311-384 using physical connections, including wires, traces, etc. DMA engine 301 is connected by physical connection 391 to the row containing processor element arrays 311-314, 321-324, and the column containing processor element arrays 311, 331, 351, 371. Thus, DMA engine 301 can broadcast parameter values ​​fetched from memory to processor element arrays 311-314, 321-324, processor element arrays 311, 331, 351, 371, subsets of these processor element arrays, or combinations thereof. DMA engine 302 is connected by physical connection 392 to rows containing processor element arrays 331-334, 341-344, and columns containing processor element arrays 312, 332, 352, 372. Therefore, DMA engine 302 can broadcast parameter values ​​fetched from memory to processor element arrays 331-334, 341-344, processor element arrays 312, 332, 352, 372, subsets of these processor element arrays, or combinations thereof. DMA engine 303 is connected by physical connection 393 to rows containing processor element arrays 351-354, 361-364, and columns containing processor element arrays 313, 333, 353, 373. Therefore, the DMA engine 303 can broadcast the parameter values ​​fetched from memory to processor element arrays 351-354, 361-364, processor element arrays 313, 333, 353, 373, subsets of these processor element arrays, or combinations thereof. The DMA engine 304 is connected by physical connection 394 to the rows containing processor element arrays 371-374, 381-384, and the columns containing processor element arrays 324, 344, 364, 384.Therefore, the DMA engine 304 can broadcast the parameter values ​​fetched from memory to processor element arrays 371-374, 381-384, processor element arrays 324, 344, 364, 384, subsets of these processor element arrays, or combinations thereof.

[0022] Figure 4 is a flowchart of a method 400 for broadcasting parameter values ​​to rows or columns of a processor element array, according to several embodiments. The method 400 is implemented in several embodiments of the processing system 100 shown in Figure 1, a portion of the processing system 200 shown in Figure 2, and the array processor 300 shown in Figure 3.

[0023] Method 400 begins in block 401. In block 405, one or more memory interfaces (such as a DMA engine) access the corresponding parameter values ​​for SIMD instructions from memory. In block 410, the DMA engine broadcasts the parameter values ​​to mutually exclusive columns or rows of the processor element array. As described herein, the DMA engine broadcasts the parameter values ​​using a physical interconnect between the DMA engine and a mutually exclusive subset of columns or rows of the processor element array.

[0024] In decision block 415, the system determines whether additional parameter values ​​should be fetched from memory. If so, method 400 returns to block 405, and the additional parameter values ​​are fetched from memory. If there are no additional parameter values ​​to fetch, method 400 proceeds to block 420, and method 400 terminates.

[0025] In some embodiments, the apparatus and techniques described above are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the array processor described above with reference to FIGS. 1-4. Electronic design automation (EDA) and computer aided design (CAD) software tools can be used to design and manufacture these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs operate a computer system to act on code representing the circuits of the one or more IC devices to perform at least a portion of the process for designing or adapting a manufacturing system for fabricating the circuits and include code executable by the computer system. This code can include instructions, data, or a combination of instructions and data. Software instructions representing design or manufacturing tools are typically stored on a computer-readable storage medium accessible to a computing system. Similarly, code representing one or more stages of the design or manufacture of an IC device is stored on and accessed from the same computer-readable storage medium or a different computer-readable storage medium.

[0026] Computer-readable storage media include any non-temporary storage media or combination of non-temporary storage media that are accessible by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray® discs), magnetic media (e.g., floppy disks, magnetic tapes, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical system (MEMS) based storage media. Computer-readable storage media (e.g., system RAM or ROM) may be built into the computing system, computer-readable storage media (e.g., magnetic hard drives) may be permanently mounted to the computing system, computer-readable storage media (e.g., optical disks or Universal Serial Bus (USB) based flash memory) may be detachably mounted to the computing system, and computer-readable storage media (e.g., network-accessible storage (NAS)) may be connected to the computer system via a wired or wireless network.

[0027] In some embodiments, certain aspects of the above-described techniques are implemented by one or more processors of a processing system that executes software. The software includes one or more sets of executable instructions stored on a non-transitory computer-readable storage medium or otherwise tangibly embodied. The software may include instructions and certain data, and when executed by one or more processors, the instructions and certain data operate one or more processors to perform one or more aspects of the above-described techniques. The non-transitory computer-readable storage medium may include, for example, magnetic or optical disk storage devices, solid-state storage devices such as flash memory, cache, random access memory (RAM), or other non-volatile memory device(s), etc. The executable instructions stored on the non-transitory computer-readable storage medium can be implemented in source code, assembly language code, object code, or other instruction formats interpretable or otherwise executable by one or more processors.

[0028] In addition to those described above, note that not all activities or elements described in the summary description are required, and some activities or parts of a particular device may not be required, and one or more additional activities may be performed and one or more additional elements may be included. Further, the order in which activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to particular embodiments. However, those skilled in the art will understand that various changes and modifications can be made without departing from the scope of the invention as recited in the claims. Accordingly, the specification and drawings are to be considered in an illustrative rather than a limiting sense, and all such modifications are intended to be included within the scope of the invention.

[0029] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, benefits, advantages, solutions to problems, and features that may give rise to or manifest any benefits, advantages, or solutions are not to be construed as essential, necessary, or indispensable features to any or all of the claims. Furthermore, the disclosed invention can be modified and implemented in different but similar ways, in ways that are obvious to those skilled in the art who are interested in the teachings of this specification; therefore, the specific embodiments described above are merely illustrative. There are no limitations to the details of the configuration or design shown herein beyond those described in the appended claims. Accordingly, the specific embodiments described above may be modified or altered, and it is clear that all such modifications are within the scope of the disclosed invention. Accordingly, the protection sought herein is described in the appended claims.

Claims

1. It is a device, A processor element array distributed in rows and columns, wherein the processor element array is configured to perform operations on parameter values, A memory interface configured to broadcast the set of parameter values ​​to mutually exclusive subsets of rows and columns of the processor element array, A single instruction multiple data (SIMD) unit comprising a subset of the processor element array for a corresponding row, wherein the memory interface broadcasts the parameter values ​​to the SIMD unit comprising the processor element array for a row associated with the memory interface, A workgroup processor comprising a subset of the SIMD units, wherein the memory interface broadcasts the parameter values ​​to a column of processor element arrays implemented across the SIMD units of the workgroup processor. Device.

2. The processor element array comprises a vector logic unit (ALU) processor, and the memory interface comprises a direct memory access (DMA) engine. The apparatus according to claim 1.

3. Each of the memory interfaces broadcasts the parameter value to the processor element array of the corresponding row and the corresponding column. The apparatus according to claim 1.

4. Of the memory interfaces, the first memory interface broadcasts a first parameter value to the processor element array of the first row and the first column, and the second memory interface broadcasts a second parameter value to the processor element array of the second row and the second column. The apparatus according to claim 3.

5. The memory interface is connected to mutually exclusive subsets of rows and columns of the processor element array via separate physical connections. The apparatus according to claim 1.

6. The memory interface is configured to simultaneously populate the parameter values ​​in registers associated with the processor element array of mutually exclusive subsets of rows and columns. The apparatus according to claim 1.

7. The memory fabric is further configured to interconnect with an external memory that stores the aforementioned parameter values, The memory interface is configured to access the parameter value from the external memory via the memory fabric. The apparatus according to claim 1.

8. It is a method, Fetching parameter values ​​from memory via the memory interface, Broadcasting the parameter values ​​from the memory interface to mutually exclusive subsets of rows and columns of the processor element array, The processor element array includes performing calculations on the parameter values, A subset of the processor element array for each row is implemented in a corresponding single instruction multiple data (SIMD) unit, and broadcasting the parameter value includes broadcasting the parameter value to the SIMD unit comprising the processor element array for the row associated with the memory interface. A subset of the SIMD units is implemented in the corresponding workgroup processor, and broadcasting the parameter value includes broadcasting the parameter value to a column of the processor element array implemented across the SIMD units of the workgroup processor. method.

9. The processor element array comprises a vector logic unit (ALU) processor, and the memory interface comprises a direct memory access (DMA) engine. The method of claim 8.

10. Broadcasting the parameter value from the memory interface includes broadcasting the parameter value from each of the memory interfaces to the processor element array of the corresponding row and the corresponding column. The method of claim 8.

11. Broadcasting the parameter value includes broadcasting the first parameter value from a first memory interface to the processor element array of a first row and a first column, and broadcasting the parameter value includes broadcasting the second parameter value from a second memory interface to the processor element array of a second row and a second column. The method of claim 10.

12. Broadcasting the parameter value includes broadcasting the parameter value via separate physical connections between the memory interface and the corresponding rows and columns. The method of claim 8.

13. Broadcasting the parameter value includes simultaneously populating the parameter value in registers associated with the processor element array of mutually exclusive subsets of rows and columns. The method of claim 8.

14. Fetching the parameter value includes accessing the parameter value via a memory fabric configured to interconnect with the memory storing the parameter value. The method of claim 8.

15. A computer-readable storage medium that embodies a set of executable instructions, The set of executable instructions is configured to cause a computer system to perform part of the process of manufacturing at least part of the processor, The aforementioned processor, A processor element array distributed in rows and columns, wherein the processor element array is configured to perform operations on parameter values, A memory interface configured to broadcast the set of parameter values ​​to mutually exclusive subsets of rows and columns of the processor element array, A single instruction multiple data (SIMD) unit comprising a subset of the processor element array for a corresponding row, wherein the memory interface broadcasts the parameter values ​​to the SIMD unit comprising the processor element array for a row associated with the memory interface, A workgroup processor comprising a subset of the SIMD units, wherein the memory interface broadcasts the parameter values ​​to a column of processor element arrays implemented across the SIMD units of the workgroup processor, A memory fabric configured to interconnect with an external memory that stores the parameter values, wherein the memory interface is configured to access the parameter values ​​from the external memory via the memory fabric. Computer-readable storage medium.

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