Apparatus and methods, media, devices, and system-on-a-chip for patching boot code.

Abstract

This disclosure discloses devices and methods, media, equipment, and systems-on-chips for patching boot code. [Solution] The boot code patching device stores the boot code in a first memory and pre-configured patch data in a second memory. The processor reads and executes the boot code from the first memory, reads the patch data in response to execution to reach a first pre-configured instruction, sets a breakpoint in the boot code via a debug control path based on the patch data, continues executing the boot code, jumps to the patch code corresponding to the breakpoint in response to execution to reach any of the breakpoints in the boot code, jumps to the return address corresponding to the breakpoint in response to completion of execution of this patch code, and continues executing the boot code.

Claims

1. A first memory configured to store the boot code, A second memory configured to store pre-set patch data, Read the boot code from the first memory, execute the boot code, In response to the first preset instruction in the boot code, the patch data is read from the second memory. Based on the aforementioned patch data, a breakpoint is set in the boot code via the debug control path. In response to executing the boot code to reach the breakpoint, the patch data jumps to the patch code corresponding to the breakpoint. A boot code patching device, including a processor configured to jump to a return address corresponding to a breakpoint and continue execution of the boot code in response to the completion of execution of the patch code corresponding to the breakpoint.

2. After reading the patch data from the second memory, the processor then, specifically, Set up the debug control path and turn it on. Based on the aforementioned patch data, patch information corresponding to at least one patch is determined, and the patch information corresponding to any one of the patches includes the source address corresponding to that patch. The boot code patching device according to claim 1, configured to set at least one breakpoint in the boot code based on the source address corresponding to the at least one patch, and to set a debug logic unit so that when the code is executed to reach the breakpoint, the debug logic unit generates debug exception information corresponding to the breakpoint.

3. Setting and enabling the debug control path is possible. This includes setting a first preset register corresponding to the debug control path to a first preset state, and / or, Setting up a debug logic unit is A device for patching boot code according to claim 2, comprising setting a second preset register corresponding to the debug logic unit to a second preset state.

4. In response to executing the boot code to reach the breakpoint, jumping to the patch code in the patch data corresponding to the breakpoint is: In response to the execution of the boot code to reach the breakpoint, the debug logic unit generates target debug exception information corresponding to the breakpoint, Based on the target debug exception information, the patch code of the target patch corresponding to the breakpoint is determined from the patch data, and the patch code of the target patch is determined as the patch code corresponding to the breakpoint. A boot code patching device according to claim 1, comprising executing the patch code corresponding to the breakpoint.

5. After reading the patch data from the second memory, the processor further: The aforementioned patch data is configured to be stored in a third memory, The previous 3 memory is volatile memory, Based on the target debug exception information, determining the patch code of the target patch corresponding to the breakpoint from the patch data is: Based on the aforementioned target debug exception information, the target source address corresponding to the breakpoint is determined, The patch data is read from the third memory, patch information corresponding to at least one patch is determined based on the patch data, and the patch information corresponding to any one patch includes the source address, return address, and patch code corresponding to that patch. The boot code patching apparatus according to claim 4, comprising matching the target source address with the source address in the patch information corresponding to the at least one patch, and determining the patch code of the target patch corresponding to the breakpoint according to the matching result.

6. After reading the patch data from the second memory, the processor further: The system is configured to analyze the patch data according to a pre-configured patch format, obtain patch information corresponding to at least one patch, and store the patch information corresponding to at least one patch in a third memory, wherein the patch information corresponding to at least one patch includes the source address, return address, and patch code corresponding to that patch. The previous 3 memory is volatile memory, Based on the target debug exception information, determining the patch code of the target patch corresponding to the breakpoint from the patch data is: Based on the aforementioned target debug exception information, the target source address corresponding to the breakpoint is determined, Reading patch information corresponding to at least one patch from the third memory, The boot code patching apparatus according to claim 4, comprising matching the target source address with the source address in the patch information corresponding to the at least one patch, and determining the patch code of the target patch corresponding to the breakpoint according to the matching result.

7. The aforementioned patch data includes a return address corresponding to at least one patch, In response to the completion of the execution of the patch code corresponding to the breakpoint, jumping to the return address corresponding to the breakpoint and continuing the execution of the boot code is: In response to the completion of the execution of the patch code corresponding to the breakpoint, the return address corresponding to the breakpoint is obtained from the patch data, A boot code patching device according to claim 4, comprising jumping to the return address and executing an instruction in the boot code corresponding to the return address.

8. The second memory is a one-time programmable memory, and after reading the patch data from the second memory, the processor further: It is configured to verify the validity and completeness of the aforementioned patch data and to obtain the verification results. Setting a breakpoint in the boot code via the debug control path based on the aforementioned patch data is: A boot code patching device according to any one of claims 1 to 7, comprising setting a breakpoint in the boot code via a debug control path based on the patch data in response to the verification result being satisfactory.

9. The steps include reading the boot code from the first memory and executing the boot code, The steps include reading patch data from the second memory in response to the first preset instruction in the boot code, The steps include setting a breakpoint in the boot code via the debug control path based on the aforementioned patch data, In response to executing the boot code to reach the breakpoint, the step of jumping to the patch code in the patch data that corresponds to the breakpoint, The process includes the step of jumping to the return address corresponding to the breakpoint and continuing the execution of the boot code in response to the completion of the execution of the patch code corresponding to the breakpoint, A method for patching boot code, executed by a device that patches boot code.

10. A computer-readable storage medium that, when executed by a processor, stores a computer program for performing the method of patching the boot code described in claim 9.

11. Processor and The processor includes a memory for storing executable instructions, The processor is an electronic device used to read and execute the executable instructions from the memory to implement the method of patching the boot code described in claim 9.

12. A system-on-a-chip including a device for patching the boot code according to any one of claims 1 to 7.

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