Imaging device

Abstract

This technology is suitable for providing a micro- and low-noise imaging device. [Solution] The first structure 171 includes a photoelectric conversion unit 110, one of the first wiring layer pairs 151b and 152a, and a first substrate 141. The second structure 172 includes the other of the first wiring layer pairs 151b and 152a, and a second substrate 142. The first via 161 penetrates the first substrate 141 and directly connects the first wiring layer pairs 151b and 152a. The charge storage region 35 is provided on one of a plurality of substrates, including the first substrate 141 and the second substrate 142. The charge storage region 35 is electrically connected to the first via 161 and stores charge. The first wiring layer pairs 151b and 152a, the first substrate 141, the other of the first wiring layer pairs 151b and 152a, and the second substrate 142 are arranged in this order.

Description

Technical Field

[0001] This disclosure relates to an imaging device.

Background Art

[0002] Imaging devices are used in digital still cameras, digital video cameras, etc. Amplification-type imaging devices typified by MOS-type image sensors such as CMOS (Complementary Metal Oxide Semiconductor), and charge transfer-type imaging devices typified by CCD (Charge Coupled Device) image sensors are known. In recent years, in particular, imaging devices mounted on mobile devices such as mobile phones with cameras and smartphones are severely restricted in mounting space, and miniaturization of the imaging device has been studied.

[0003] As a means of miniaturization, it is conceivable to integrate not only in the planar direction but also in the height direction of the imaging device.

[0004] In Patent Document 1, a structure in which transistors constituting pixels are provided on a plurality of wafers is disclosed as a separated unit pixel of an image sensor having a three-dimensional structure.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] There is a need for a technology suitable for providing a fine and low-noise imaging device.

Means for Solving the Problems

[0007] The imaging device according to this disclosure includes at least one pixel, Each of the at least one of the aforementioned pixels is A first structure having a photoelectric conversion unit that converts light into electric charge, one of a first wiring layer pair, and a first substrate, A second structure having the other of the first wiring layer pair and a second substrate, A first via that penetrates the first substrate and directly connects the first wiring layer pair, A charge storage region is provided on any of the plurality of substrates, including the first substrate and the second substrate, for storing the charge and being electrically connected to the first via, Equipped with, The first wiring layer pair, the first substrate, the other part of the first wiring layer pair, and the second substrate are arranged in this order. [Effects of the Invention]

[0008] The technology described herein is suitable for providing a fine and low-noise imaging device. [Brief explanation of the drawing]

[0009] [Figure 1A] Figure 1A is a circuit diagram of the imaging device according to the first embodiment. [Figure 1B] Figure 1B is a cross-sectional view of the imaging device according to the first embodiment. [Figure 1C] Figure 1C is a cross-sectional view showing the structure around the first substrate. [Figure 2] Figure 2 is a cross-sectional view of an imaging device according to the first reference embodiment. [Figure 3] Figure 3 is a cross-sectional view of an imaging device according to the second reference embodiment. [Figure 4A] Figure 4A is a circuit diagram of the imaging device with transistor arrangement (6) shown in Table 1. [Figure 4B] Figure 4B is a cross-sectional view of the imaging device with transistor arrangement (6) shown in Table 1. [Figure 5] Figure 5 is a circuit diagram of the imaging device with transistor arrangement (4) shown in Table 1. [Figure 6A]FIG. 6A is an explanatory diagram of a method for manufacturing an imaging device according to the first embodiment. [Figure 6B] FIG. 6B is an explanatory diagram of a method for manufacturing an imaging device according to the first embodiment. [Figure 6C] FIG. 6C is an explanatory diagram of a method for manufacturing an imaging device according to the first embodiment. [Figure 6D] FIG. 6D is an explanatory diagram of a method for manufacturing an imaging device according to the first embodiment. [Figure 6E] FIG. 6E is an explanatory diagram of a method for manufacturing an imaging device according to the first embodiment. [Figure 7] FIG. 7 is a flowchart of a method for manufacturing an imaging device according to the first embodiment. [Figure 8A] FIG. 8A is a circuit diagram of an imaging device according to the second embodiment. [Figure 8B] FIG. 8B is a cross-sectional view of an imaging device according to the second embodiment. [Figure 9A] FIG. 9A is a circuit diagram of an imaging device according to the third embodiment. [Figure 9B] FIG. 9B is a cross-sectional view of an imaging device according to the third embodiment. [Figure 10A] FIG. 10A is a circuit diagram of an imaging device according to the fourth embodiment. [Figure 10B] FIG. 10B is a cross-sectional view of an imaging device according to the fourth embodiment. [Figure 10C] FIG. 10C is a cross-sectional view showing the structure around the second substrate. [Figure 11] FIG. 11 is a circuit diagram of an imaging device with the transistor arrangement (11) in Table 3B. [Figure 12] FIG. 12 is a circuit diagram of an imaging device with the transistor arrangement (12) in Table 3B. [Figure 13] FIG. 13 is a circuit diagram of an imaging device with the transistor arrangement (19) in Table 3D [Figure 14] FIG. 14 is a circuit diagram of an imaging device with the transistor arrangement (23) in Table 3D. [Figure 15] FIG. 15 is a circuit diagram of an imaging device with the transistor arrangement (24) in Table 3D. [Figure 16] Figure 16 is a circuit diagram of the imaging device with the transistor arrangement (35) shown in Table 3F. [Figure 17] Figure 17 is a circuit diagram of the imaging device with the transistor arrangement (36) shown in Table 3F. [Figure 18A] Figure 18A is a circuit diagram of the imaging device according to the fifth embodiment. [Figure 18B] Figure 18B is a cross-sectional view of an imaging device according to the fifth embodiment. [Figure 18C] Figure 18C is a cross-sectional view showing the structure around the third substrate. [Figure 19] Figure 19 is a circuit diagram of the imaging device with transistor arrangement (7) shown in Table 4B. [Figure 20A] Figure 20A is a circuit diagram of the imaging device according to the sixth embodiment. [Figure 20B] Figure 20B is a cross-sectional view of an imaging device according to the sixth embodiment. [Figure 21] Figure 21 is a schematic diagram showing an example of the configuration of a camera system according to an embodiment. [Modes for carrying out the invention]

[0010] The embodiments of this disclosure will be described in detail below with reference to the drawings. The numerical values, shapes, materials, components, positions and connection configurations of components, steps, and the order of steps shown in the embodiments are examples only and are not intended to limit this disclosure.

[0011] In the embodiments, terms such as "upper" and "lower" are used solely to specify the relative positions of the components, and are not intended to limit the orientation of the imaging device during use or the orientation of the components of the imaging device and the manufacturing equipment during the manufacturing process.

[0012] In embodiments, "via" refers to wiring that connects wiring layers. Vias include a conductor provided within a hole. "Trench" refers to a groove. "Substrate" may also be called "wafer".

[0013] In the embodiments, "connection" and "electrically connected" may be interpreted interchangeably, unless otherwise inconsistent.

[0014] (First embodiment) Figures 1A and 1B are a circuit diagram and a cross-sectional view of an imaging device 101 according to a first embodiment, respectively. The imaging device 101 is a front-side illumination (FSI) type. The imaging device 101 includes a photoelectric conversion unit 110, a protective film 119, a color filter 120, a microlens 130, a reset transistor 13, an amplification transistor 11, a selection transistor 12, a first substrate 141, a second substrate 142, a first plurality of wiring layers 151, a second plurality of wiring layers 152, a first via 161, and a via 166. These elements are contained within the pixels 190 of the imaging device 101. In a typical example, these elements are contained within each of the plurality of pixels 190 of the imaging device 101. In Figure 1B, the first plurality of wiring layers 151 and the second plurality of wiring layers 152 are depicted in a simplified manner.

[0015] As shown in Figure 1A, the imaging device 101 includes a charge storage node 30. The charge storage node 30 stores charge. The charge storage node 30 includes a charge storage region 35 as shown in Figure 1B.

[0016] The photoelectric conversion unit 110 includes a photoelectric conversion film 111, a pixel electrode 112, and a counter electrode 113. The photoelectric conversion film 111 is positioned between the pixel electrode 112 and the counter electrode 113. The photoelectric conversion film 111 is located outside the first substrate 141. In this embodiment, the photoelectric conversion film 111 contains an organic material. However, the photoelectric conversion film 111 may also contain an inorganic material.

[0017] The microlens 130 has a light-gathering function that focuses light onto the photoelectric conversion unit 110. The color filter 120 performs color separation. The protective film 119 protects the photoelectric conversion unit 110.

[0018] As shown in Figure 1A, the photoelectric conversion unit 110 is electrically connected to one of the source and drain of the reset transistor 13 and to the gate 11g of the amplification transistor 11. Specifically, the pixel electrode 112 is electrically connected to these. One of the source and drain of the reset transistor 13 constitutes a charge storage region 35. In other words, the charge storage region 35 is included in the reset transistor 13. The charge storage region 35 is a diffusion region provided on the substrate. One of the source and drain of the amplification transistor 11 and one of the source and drain of the selection transistor 12 are electrically connected.

[0019] The photoelectric conversion unit 110, specifically the photoelectric conversion film 111, converts light into electric charge. The charge is stored in the charge storage node 30. The power supply voltage is supplied to the source and the other drain of the amplification transistor 11 through the voltage line 21. The amplification transistor 11 outputs a signal corresponding to the potential of the charge storage node 30 to the signal line 22 via the selection transistor 12. The selection transistor 12 determines the timing of the signal output from the amplification transistor 11. Specifically, a voltage is supplied to the gate 12g of the selection transistor 12 at the pixel 190 selected by a control circuit (not shown). This turns on the selection transistor 12, and a signal is output from its source and the other drain.

[0020] A reset voltage is supplied to the source and the other drain of the reset transistor 13 through a voltage line 23. The reset transistor 13 resets the charge stored in the charge storage node 30. Specifically, when a voltage is supplied to the gate 13g of the reset transistor 13, the reset transistor 13 turns on, the reset voltage is supplied to the charge storage node 30, and the charge in the charge storage node 30 is reset.

[0021] The reset transistor 13 is provided on the first substrate 141. The amplification transistor 11 and the selection transistor 12 are provided on the second substrate 142. The microlens 130, color filter 120, protective film 119, photoelectric conversion unit 110, first plurality of wiring layers 151, first substrate 141, second plurality of wiring layers 152, and second substrate 142 are arranged in this order. The first plurality of wiring layers 151 are located on the light incidence side of the first substrate 141. The second plurality of wiring layers 152 are located on the light incidence side of the second substrate 142.

[0022] Figure 1C is a cross-sectional view showing the structure around the first substrate 141. The first plurality of wiring layers 151 include wiring layer 151a and wiring layer 151b. The photoelectric conversion unit 110, wiring layer 151a, wiring layer 151b, and the first substrate 141 are arranged in this order. The second plurality of wiring layers 152 include wiring layer 152a and wiring layer 152b. The first substrate 141, wiring layer 152a, wiring layer 152b, and the second substrate 142 are arranged in this order.

[0023] The first plurality of wiring layers 151 are electrically connected to each other. The first plurality of wiring layers 151 are conductors, including, for example, metals. In the illustrated example, wiring layers 151a and 151b are electrically connected by vias 151x. The second plurality of wiring layers 152 are electrically connected to each other. The second plurality of wiring layers 152 are conductors, including, for example, metals. In the illustrated example, wiring layers 152a and 152b are electrically connected by vias 152x. The first via 161 penetrates the first substrate 141 and electrically connects wiring layers 151b and 152a. The first via 161 is a conductor, including, for example, a metal. The first plurality of wiring layers 151, the second plurality of wiring layers 152, and the first via 161 are electrically connected to the charge storage region 35.

[0024] Via 166 electrically connects the wiring layer 151b and the charge storage region 35.

[0025] The imaging device 101 includes a first structure 171 and a second structure 172. The first structure 171 includes a microlens 130, a color filter 120, a protective film 119, a photoelectric conversion unit 110, a first plurality of wiring layers 151, and a first substrate 141. The second structure 172 includes a second plurality of wiring layers 152 and a second substrate 142. The first structure 171 and the second structure 172 are joined to each other at a first bonding interface 181.

[0026] As will be described later, in the manufacturing of the imaging device 101, a structure 170 including the first substrate 141 is formed and bonded to the second structure 172. The first bonding interface 181 is, in detail, the bonding interface related to this bonding. After bonding, the first via 161 is formed.

[0027] The wiring layers 151b and 152a constitute the first wiring layer pair 151b and 152a. The first via 161 directly connects the first wiring layer pair 151b and 152a. This configuration is suitable for providing a fine and low-noise imaging device 101. The reasons for this will be explained in detail below, in comparison with the first reference embodiment.

[0028] Figure 2 is a cross-sectional view of an imaging device 801 according to the first reference embodiment. The imaging device 801 includes a photoelectric conversion unit 810, a microlens 130, a color filter 120, a protective film 119, a transfer transistor 15, a reset transistor 13, an amplification transistor 11, a selection transistor 12, a first substrate 841, a second substrate 842, a plurality of wiring layers 852, and a Cu-Cu junction 861. The Cu-Cu junction 861 includes a first Cu pad 861a and a second Cu pad 861b.

[0029] The photoelectric conversion unit 810 is a photodiode provided on the first substrate 841. The transfer transistor 15 is provided on the first substrate 841. The reset transistor 13, the amplification transistor 11, and the selection transistor 12 are provided on the second substrate 842. The microlens 130, the color filter 120, the protective film 119, the first substrate 841, the multiple wiring layers 852, and the second substrate 842 are arranged in this order.

[0030] One of the source and drain of the transfer transistor 15 is connected to the photoelectric conversion unit 810. The other of the source and drain of the transfer transistor 15 constitutes a charge storage region 35. The charge storage region 35 is electrically connected to one of the source and drain of the reset transistor 13 and to the gate 11g of the amplification transistor 11 via a Cu-Cu junction 861 and a plurality of wiring layers 852 in that order.

[0031] The imaging device 801 includes structures 870 and 872. Structure 870 includes a first Cu pad 861a and a first substrate 841. Structure 872 includes a second Cu pad 861b, a plurality of wiring layers 852 and a second substrate 842. Structures 870 and 872 are joined to each other by a Cu-Cu junction 861 at the bonding interface 881. The use of the Cu-Cu junction 861 is disadvantageous from the viewpoint of providing a fine and low-noise imaging device 801. This is because the Cu-Cu junction 861 tends to increase the size of the imaging device 801 and also tends to increase the parasitic capacitance of the charge storage node 30.

[0032] In contrast, as described above, in this embodiment, the first wiring layer pair 151b and 152a are directly connected by the first via 161. Furthermore, the first wiring layer pair 151b and 152a are connected using the first via 161 and without using Cu-Cu junctions. More generally, the first wiring layer pair 151b and 152a are connected using the first via 161 and without using conductor pad pairs. The first via 161 does not easily increase the size of the imaging device 101, nor does it easily increase the parasitic capacitance of the charge storage node 30. For this reason, this configuration is suitable for providing a small and low-noise imaging device 101.

[0033] The imaging device 101 includes one or more pixels 190. Each of the one or more pixels 190 includes a first structure 171, a second structure 172, a first via 161, and a charge storage region 35.

[0034] The first structure 171, the second structure 172, the first via 161, and the charge storage region 35 may be positioned at a location that overlaps with at least one of the microlens 130 and the color filter 120 in a planar view.

[0035] In this embodiment, the wiring layer 151b is the wiring layer closest to the first substrate 141 among the first plurality of wiring layers 151 in the first structure 171. The wiring layer 151b may also be the only wiring layer in the first structure 171. Both embodiments are advantageous from the viewpoint of shortening the first via 161. This is advantageous from the viewpoint of suppressing parasitic capacitance of the charge storage node 30.

[0036] In this embodiment, the wiring layer 152a is the wiring layer closest to the first substrate 141 among the second plurality of wiring layers 152 in the second structure 172. The wiring layer 152a may also be the only wiring layer in the second structure 172. Both embodiments are advantageous from the viewpoint of shortening the first via 161. This is advantageous from the viewpoint of suppressing parasitic capacitance of the charge storage node 30.

[0037] The first substrate 141 includes a first semiconductor layer 141x and a first oxide film 141y. The first via 161 penetrates the first oxide film 141y. The first oxide film 141y prevents electrical conductivity between the first via 161 and the first semiconductor layer 141x. Specifically, the first oxide film 141y is an embedded oxide film. The first oxide film 141y, embedded in the first substrate 141, isolates the semiconductor elements on the first substrate 141. The embedded oxide film can reduce the parasitic capacitance of the charge storage node 30 caused by the first semiconductor layer 141x. In the illustrated example, the first oxide film 141y penetrates the first substrate 141. This configuration is advantageous from the viewpoint of preventing electrical conductivity between the first via 161 and the first semiconductor layer 141x. However, the first oxide film 141y does not have to penetrate the first substrate 141.

[0038] In this embodiment, the first semiconductor layer 141x contains silicon. The first oxide film 141y is an insulating film. The first oxide film 141y contains silicon oxide.

[0039] As can be understood from the above explanation, the first transistor is provided on the first substrate 141. The second transistor is provided on the second substrate 142. The third transistor is provided on the second substrate 142. Specifically, the first transistor, the second transistor, and the third transistor are provided on one pixel 190, or on each of multiple pixels 190. This configuration, in which multiple transistors are provided on separate substrates, is advantageous from the viewpoint of ensuring the size of each transistor. This can contribute to realizing low-noise transistors. Specifically, ensuring the gate length L and gate width W of the transistors can contribute to realizing low-noise transistors. Alternatively, this configuration, in which multiple transistors are provided on separate substrates, is advantageous from the viewpoint of miniaturizing the imaging device 101.

[0040] One of the first and second transistors may be an amplification transistor 11. Ensuring the size of the amplification transistor 11 and realizing a low-noise amplification transistor 11 is particularly advantageous from the viewpoint of realizing a high-performance imaging device 101.

[0041] The other of the first and second transistors may be a reset transistor 13. The third transistor may be a selection transistor 12.

[0042] In the illustrated example, the first transistor is the reset transistor 13. The second transistor is the amplification transistor 11. The third transistor is the selection transistor 12.

[0043] In this embodiment, the gate of the second transistor (amplifying transistor 11 in the illustrated example) is positioned between the photoelectric conversion unit 110 and the second substrate 142 with respect to the thickness direction of the second substrate 142. This configuration is advantageous from the viewpoint of realizing a low-noise second transistor. The reasons for this will be explained in detail below, in comparison with the second reference embodiment.

[0044] Figure 3 is a cross-sectional view of an imaging device 901 according to a second reference embodiment. The imaging device 901 includes a photoelectric conversion unit 910, a microlens 130, a color filter 120, a protective film 119, a transfer transistor 15, a reset transistor 13, an amplification transistor 11, a selection transistor 12, a first substrate 941, a second substrate 942, a wiring layer 952, vias 961 and 962.

[0045] The photoelectric conversion unit 910 is a photodiode provided on the first substrate 941. The transfer transistor 15 is provided on the first substrate 941. The reset transistor 13, the amplification transistor 11, and the selection transistor 12 are provided on the second substrate 942. The microlens 130, the color filter 120, the protective film 119, the first substrate 941, the second substrate 942, and the wiring layer 952 are arranged in this order.

[0046] One of the source and drain of the transfer transistor 15 is connected to the photoelectric conversion unit 910. The other of the source and drain of the transfer transistor 15 constitutes a charge storage region 35. The charge storage region 35 is electrically connected to the gate 11g of the amplification transistor 11 via via 961, wiring layer 952, and via 962 in that order.

[0047] The imaging device 901 includes structures 970 and 972. Structure 970 includes a first substrate 941. Structure 972 includes a wiring layer 952 and a second substrate 942. Structures 970 and 972 are joined to each other at a bonding interface 981.

[0048] In the second reference embodiment, via 961 penetrates the second substrate 942 from the first substrate 941 side to the wiring layer 952 side and is connected to the wiring layer 952. The gate 11g of the amplifying transistor 11 is located on the wiring layer 952 side of the second substrate 942 and is connected to the wiring layer 952 by via 962. In this way, via 961, wiring layer 952 and via 962 constitute an electrical path 965 connecting the charge storage region 35 and the gate 11g.

[0049] In Figure 3, the gate 11g is located below the second substrate 942. The via 961 of the electrical path 965 extends downward from the charge storage region 35 side, penetrating the second substrate 942. Subsequently, the electrical path 965 has a return section 966 that returns upward to reach the gate 11g. In a configuration where the gate 11g is located below the second substrate 942 and the via 961 penetrates the second substrate 942 downward, it is difficult to position the gate 11g on the second substrate 942 in the peripheral portion 967 of the via 961.

[0050] In contrast, as described above, in this embodiment, the gate of the second transistor (amplifier transistor 11 in the illustrated example) is positioned between the photoelectric conversion unit 110 and the second substrate 142 with respect to the thickness direction of the second substrate 142. In this configuration, the charge storage region 35 and the gate of the second transistor can be electrically connected by the first via 161 without vias penetrating the second substrate 142. Therefore, the constraints on gate placement arising from vias penetrating the second substrate 142 are not imposed. This is advantageous from the viewpoint of avoiding unnecessary miniaturization of the second transistor and realizing a low-noise second transistor.

[0051] In this embodiment, with respect to the thickness direction of the first substrate 141, the gate of the first transistor (reset transistor 13 in the illustrated example) is located between the photoelectric conversion unit 110 and the first substrate 141. With respect to the thickness direction of the second substrate 142, the gate of the third transistor (selection transistor 12 in the illustrated example) is located between the photoelectric conversion unit 110 and the second substrate 142.

[0052] In this embodiment, the reset transistor 13 is provided on the first substrate 141. The amplification transistor 11 is provided on the second substrate 142. The selection transistor 12 is provided on the second substrate 142. This configuration is advantageous from the viewpoint of reducing the number of vias that penetrate the substrate in the imaging device 101. By reducing the number of vias that penetrate the substrate, the area required to arrange the vias can be reduced. This is advantageous from the viewpoint of ensuring the size of the transistors. In addition, by reducing the number of vias that penetrate the substrate, the manufacturing of the imaging device 101 becomes easier. This can contribute to improving the reliability of the imaging device 101.

[0053] Specifically, in this embodiment, a reset transistor 13, an amplification transistor 11, and a selection transistor 12 are provided in one pixel 190, or in each of multiple pixels 190. This is also true for the examples in Figures 4A to 5.

[0054] According to the inventors' research, it is possible to reduce the number of vias that penetrate the substrate to connect the transistors by devising the arrangement of the transistors. Table 1 shows the results of the research. Table 1 shows the relationship between the substrate on which various transistors are arranged and the above number. Specifically, in Table 1, "RX" is reset transistor 13. "SF" is the amplification transistor 11. • "SEL" is the selection transistor 12. The "first layer" is a transistor provided on the first substrate 141. The "second layer" is a transistor located on the second substrate 142. The number of vias between the first and second layers is the number of vias that penetrate the first substrate 141. Note that "RX" is not intended to be a restrictive expression for the reset transistor 13. The same applies to "SF," "SEL," and "OF" described later. [Table 1]

[0055] As can be seen from Figure 1B, the first embodiment corresponds to transistor arrangement (1) in Table 1.

[0056] Figures 4A and 4B are the circuit diagram and cross-sectional view, respectively, of the imaging device with transistor arrangement (6) in Table 1. Figure 5 is the circuit diagram of the imaging device with transistor arrangement (4) in Table 1. The electrical circuits in Figures 1A, 4A, and 5 are electrically equivalent.

[0057] In the transistor arrangement (6) in Table 1, i.e., the examples in Figures 4A and 4B, the amplification transistor 11 is located on the first substrate 141. The selection transistor 12 is located on the first substrate 141. The reset transistor 13 is located on the second substrate 142.

[0058] In the transistor arrangement (4) in Table 1, i.e., the example in Figure 5, the reset transistor 13 is located on the first substrate 141. The amplification transistor 11 is located on the first substrate 141. The selection transistor 12 is located on the second substrate 142.

[0059] Various modifications can be applied to the imaging device 101. The number of wiring layers included in the first plurality of wiring layers 151 is not particularly limited and may be 2, 3, or 4 or more, as shown in the figure. The number of wiring layers included in the second plurality of wiring layers 152 is not particularly limited and may be 2, 3, or 4 or more, as shown in the figure. Some elements of the imaging device 101 are optional. For example, the protective film 119, color filter 120, and microlens 130 are optional. The number of pixels 190 in the imaging device 101 may be one or more. The first oxide film 141y is optional.

[0060] Figures 6A to 6E are explanatory diagrams of the manufacturing method of the imaging device 101 according to the first embodiment. Figure 7 is a flowchart of the manufacturing method of the imaging device 101 according to the first embodiment. The manufacturing method of the imaging device 101 will be described below with reference to Figures 6A to 6E and Figure 7.

[0061] In parts (1) to (3) of Figure 6A and steps S101 to S103 of Figure 7, the second structure 172 is formed. In parts (4) to (7) of Figure 6B and steps S104 to S107 of Figure 7, structure 170 is formed. In parts (8) to (10) of Figure 6C and steps S108 to S110 of Figure 7, a joint of the second structure 172 and structure 170 is formed. In parts (11) to (13) of Figure 6D and steps S111 to S113 of Figure 7, the structure up to the wiring layer 151b is formed. In parts (14) and (15) of Figure 6E and steps S114 and S115 of Figure 7, the structure above the wiring layer 151b is formed. The manufacturing method of the imaging device 101 will be described in detail below.

[0062] In step S101, the second substrate 142 is prepared as shown in part (1) of Figure 6A.

[0063] Next, in step S102, as shown in part (2) of Figure 6A, an amplifying transistor 11 and a selecting transistor 12 are formed on the second substrate 142. An insulating film 186a is formed on top of the second substrate 142 so as to cover the amplifying transistor 11 and the selecting transistor 12. Then, the upper surface 186as of the insulating film 186a is flattened. In this example, the insulating film 186a is a silicon oxide film.

[0064] Next, in step S103, a second set of wiring layers 152 are formed as shown in part (3) of Figure 6A. Specifically, the formation of wiring layers and the formation of insulating layers are repeated alternately. This creates a configuration in which the second set of wiring layers 152 are covered with an insulating film 186 above the second substrate 142. The upper surface 186s of the insulating film 186 is flattened. The insulating film 186 includes an insulating film 186a. In this example, the insulating film 186 is a silicon oxide film. Thus, the second structure 172 is obtained.

[0065] In step S104, the first substrate 141 is prepared as shown in part (4) of Figure 6B. In this example, an SOI (Silicon on Insulator) substrate is prepared as the first substrate 141. Specifically, the first substrate 141 prepared is a laminated substrate in which a silicon film 141a, an insulating film 141b, and a silicon film 141c are stacked in this order. In this example, the insulating film 141b is a silicon oxide film.

[0066] Next, in step S105, a reset transistor 13 is formed on the first substrate 141 as shown in part (5) of Figure 6B. An insulating film 185a is formed on top of the first substrate 141 so as to cover the reset transistor 13. Then, the upper surface 185as of the insulating film 185a is flattened.

[0067] Next, in step S106, as shown in part (6) of Figure 6B, the support substrate 187 is attached to the upper surface 185as of the insulating film 185a.

[0068] Next, in step S107, as shown in part (7) of Figure 6B, the first substrate 141 is thinned from the opposite side of the support substrate 187. Thinning is performed, for example, by grinding. In the illustrated example, thinning selectively removes the silicon film 141a, exposing the lower surface 141bs of the insulating film 141b. Thus, a structure 170 is obtained that includes the first substrate 141 from which the silicon film 141a has been removed and is supported by the support substrate 187.

[0069] Next, in step S108, as shown in part (8) of Figure 6C, the lower surface 141bs of the insulating film 141b and the upper surface 186s of the insulating film 186 are superimposed. In this way, the second structure 172 and the structure 170 are superimposed.

[0070] Next, in step S109, the lower surface 141bs and the upper surface 186s are joined together, as shown in part (9) of Figure 6C. The joining is performed, for example, by plasma activation, application of pressure, etc. This joins the second structure 172 and structure 170. In part (9) of Figure 6C, the first joining interface 181, which is the joining interface between the second structure 172 and structure 170, is shown.

[0071] Next, in step S110, the support substrate 187 is peeled off the structure 170 as shown in part (10) of Figure 6C.

[0072] Next, in step S111, trenches 188a and 188b are formed on the upper surface 185as of the insulating film 185a, as shown in part (11) of Figure 6D.

[0073] Next, in step S112, a first through-hole 189a and a through-hole 189b are formed as shown in part (12) of Figure 6D. The first through-hole 189a communicates with the trench 188a and extends in this order through the insulating film 185a, the silicon film 141c, the insulating film 141b, and the insulating film 186, exposing the wiring layer 152a. The through-hole 189b communicates with the trench 188b and extends through the insulating film 185a, exposing the gate 13g of the reset transistor 13.

[0074] Next, in step S113, as shown in part (13) of Figure 6D, the first through-hole 189a, trench 188a, through-hole 189b, and trench 188b are filled with a conductor. The conductor is, for example, a metal. The conductor in the first through-hole 189a constitutes the first via 161. The conductor in the through-hole 189b constitutes the via 167. The conductors in the trenches 188a and 188b constitute the wiring layer 151b. In this embodiment, the first via 161, via 167, and wiring layer 151b are formed in a single operation of filling with a conductor.

[0075] Next, in step S114, a conductive structure 176 is formed above the wiring layer 151b, as shown in part (14) of Figure 6E. The conductive structure 176 includes the parts of the first plurality of wiring layers 151 other than the wiring layer 151b and the pixel electrode 112. The details of step S114 will be described below.

[0076] Firstly, in step S114, the portion of the first plurality of wiring layers 151 other than the wiring layer 151b is formed. Specifically, the formation of the wiring layer and the subsequent formation of the insulating portion are performed once each, or the formation of the wiring layer and the formation of the insulating portion are repeated alternately. As a result, a configuration is formed above the second substrate 142 in which the first plurality of wiring layers 151 are covered with an insulating film 185. The upper surface 185s of the insulating film 185 is flattened. The insulating film 185 includes an insulating film 185a. In this example, the insulating film 185 is a silicon oxide film.

[0077] Secondly, in step S114, a pixel electrode 112 is formed on the upper surface 185s of the insulating film 185.

[0078] Next, in step S115, as shown in part (15) of Figure 6E, the photoelectric conversion film 111, counter electrode 113, protective film 119, color filter 120, and microlens 130 are formed on top of the conductive structure 176. The photoelectric conversion film 111 is formed, for example, by vacuum deposition, spin coating, etc. As described above, in this embodiment, the photoelectric conversion film 111 contains an organic material.

[0079] As can be understood from the above description, the manufacturing method according to this embodiment includes, in this order, a first bonding step, a first drilling step, a first via formation step, and a first film formation step. In the first bonding step, a structure 170 including the first substrate 141 is bonded to the second structure 172. In the first drilling step, a first through hole 189a is formed in the first substrate 141. In the first via formation step, a first via 161 is formed by filling the first through hole 189a with a first conductor. In the first film formation step, a photoelectric conversion film 111 is formed.

[0080] In the above manufacturing method, no wiring layers belonging to the first plurality of wiring layers 151 are formed immediately after step S105. This allows the first through-hole 189a and the first via 161 to be shortened. This facilitates the manufacture of the imaging device 101. This may contribute to improving the reliability of the imaging device 101. However, some or all of the first plurality of wiring layers 151 may be formed immediately after step S105.

[0081] As can be understood from the above explanation, it is possible to use a single wiring layer instead of the first multiple wiring layers 151. In this case, no wiring layer is formed in step S114. Also, it is possible to use a single wiring layer instead of the second multiple wiring layers 152. In this case, the number of wiring layers formed in step S103 is one.

[0082] The first substrate 141 prepared in step S104 does not have to be an SOI substrate. For example, a silicon substrate may be prepared as the first substrate 141 in step S104. In one example of this case, an insulating film is formed on the first substrate 141. Then, in step S109, the formed insulating film and the insulating film 186 are joined together. The insulating film formed on the first substrate 141 is, for example, a silicon oxide film.

[0083] In step S109, the second structure 172 and structure 170 may be joined by adhesive, bumps, conductor pad pairs, etc. In that case, preparations for joining can be made according to the joining method. Joining by conductor pad pairs is, for example, a Cu-Cu joining.

[0084] The thinning in step S107 may shorten the first through-hole 189a and the first via 161. However, this thinning is not essential. Also, in step S113, it is not essential to form the first via 161, via 167 and the wiring layer 151b in a single operation of filling the conductor.

[0085] The above explanation omits the description of the formation of the first oxide film 141y. The first oxide film 141y can be formed by any appropriate method.

[0086] Other embodiments will be described below. In the following, elements common to embodiments already described and those described later will be given the same reference numerals, and their descriptions may be omitted. The descriptions of each embodiment may be mutually applicable, as long as they do not technically contradict each other. As long as they do not technically contradict each other, each embodiment may be combined with each other.

[0087] (Second embodiment) Figures 8A and 8B are a circuit diagram and a cross-sectional view of the imaging device 201 according to the second embodiment, respectively. The imaging device 201 includes an overflow transistor 14. The overflow transistor 14 is included in the pixels 190 of the imaging device 201. In a typical example, the overflow transistor 14 is included in each of the multiple pixels 190 of the imaging device 201.

[0088] The photoelectric conversion unit 110 is electrically connected to one of the source and drain of the reset transistor 13, one of the source and drain of the overflow transistor 14, the gate 14g of the overflow transistor 14, and the gate 11g of the amplification transistor 11. Specifically, the pixel electrode 112 is electrically connected to these. One of the source and drain of the reset transistor 13 constitutes a charge storage region 35. Also, one of the source and drain of the overflow transistor 14 constitutes a charge storage region 35. In other words, the charge storage region 35 is shared by the reset transistor 13 and the overflow transistor 14. The first via 161 is electrically connected to the charge storage region 35.

[0089] A voltage is applied to the source and the other drain of the overflow transistor 14 through the voltage line 24. As described above, the gate 14g of the overflow transistor 14 is electrically connected to the charge storage region 35. When strong light is incident on the photoelectric conversion unit 110, the charge in the charge storage region 35 increases, and the overflow transistor 14 turns on. As a result, the excess charge accumulated in the charge storage region 35 is discharged through the overflow transistor 14. This protects the various transistors and ensures the safety of the imaging device 201.

[0090] The imaging device 201 includes four transistors: a reset transistor 13, an overflow transistor 14, an amplification transistor 11, and a selection transistor 12. Two of the four transistors are provided on the first substrate 141, and the remaining two are provided on the second substrate 142. This configuration, with two transistors on separate substrates, is advantageous from the standpoint of ensuring the size of each individual transistor. Alternatively, this configuration is advantageous from the standpoint of miniaturizing the imaging device 201.

[0091] With respect to the thickness direction of the first substrate 141, the gate 14g of the overflow transistor 14 is positioned between the photoelectric conversion unit 110 and the first substrate 141.

[0092] The reset transistor 13 and the overflow transistor 14 are provided on the first substrate 141. The amplification transistor 11 and the selection transistor 12 are provided on the second substrate 142. This configuration is advantageous in terms of reducing the number of vias that penetrate the substrate in the imaging device 201.

[0093] Specifically, a reset transistor 13, an overflow transistor 14, an amplification transistor 11, and a selection transistor 12 are provided in each of a set of pixels 190, or in each of a set of pixels 190. This is also true for the examples in Figures 9A to 19.

[0094] According to the inventors' studies, in the second embodiment, as in the first embodiment, it is possible to reduce the number of vias that penetrate the substrate to connect the transistors by devising the arrangement of the transistors. The results of the study are shown in Table 2. Table 2 shows the relationship between the substrate on which various transistors are arranged and the above number. Specifically, in Table 2, "OF" refers to the overflow transistor 14. [Table 2]

[0095] As can be seen from Figure 8B, the second embodiment corresponds to transistor arrangement (1) in Table 2.

[0096] The manufacturing method for the imaging device 201 according to the second embodiment is the same as the manufacturing method for the imaging device 101 according to the first embodiment, with the addition of the formation of an overflow transistor 14. Specifically, in step S105, the overflow transistor 14 is formed on the first substrate 141 together with the reset transistor 13. An insulating film 185a is formed on top of the first substrate 141 so as to cover the reset transistor 13 and the overflow transistor 14.

[0097] (Third embodiment) Figures 9A and 9B are a circuit diagram and a cross-sectional view of the imaging device 301 according to the third embodiment, respectively.

[0098] The reset transistor 13 and the overflow transistor 14 are located on the second substrate 142. The amplification transistor 11 and the selection transistor 12 are located on the first substrate 141.

[0099] Via 166 electrically connects the wiring layer 151b and the gate 11g of the amplification transistor 11.

[0100] In this embodiment, with respect to the thickness direction of the first substrate 141, the gate 11g of the amplification transistor 11 and the gate 12g of the selection transistor 12 are located between the photoelectric conversion unit 110 and the first substrate 141. With respect to the thickness direction of the second substrate 142, the gate 13g of the reset transistor 13 and the gate 14g of the overflow transistor 14 are located between the photoelectric conversion unit 110 and the second substrate 142.

[0101] The reset transistor 13 and the overflow transistor 14 are located on the second substrate 142. The amplification transistor 11 and the selection transistor 12 are located on the first substrate 141. This configuration is advantageous in terms of reducing the number of vias that penetrate the substrate in the imaging device 301.

[0102] As can be seen from Figure 9B, the third embodiment corresponds to transistor arrangement (6) in Table 2.

[0103] The manufacturing method for the imaging device 301 according to the third embodiment is a modification of the manufacturing method for the imaging device 201 according to the second embodiment, with changes made to the steps related to the transistors. Specifically, in step S102, a reset transistor 13 and an overflow transistor 14 are formed on the second substrate 142. An insulating film 186a is formed above the second substrate 142 so as to cover the reset transistor 13 and the overflow transistor 14. In step S105, an amplification transistor 11 and a selection transistor 12 are formed. An insulating film 185a is formed above the first substrate 141 so as to cover the amplification transistor 11 and the selection transistor 12. In step S112, the through hole 189b communicates with the trench 188b, extends through the insulating film 185a, and exposes the gate 12g of the selection transistor 12.

[0104] The electrical circuits in Figure 9A of the third embodiment and Figure 8A of the second embodiment are electrically equivalent. Now, let's compare the third embodiment with the second embodiment. In the third embodiment, the first via 161 penetrates the first substrate 141, which is the substrate on which the amplification transistor 11 is provided. In contrast, in the second embodiment, the first via 161 does not penetrate the second substrate 142, which is the substrate on which the amplification transistor 11 is provided. In the second embodiment, the area on the second substrate 142 on which the amplification transistor 11 can be mounted is less likely to be limited by the first via 161. This is advantageous from the viewpoint of ensuring the size of the amplification transistor 11.

[0105] (Fourth embodiment) Figures 10A and 10B are a circuit diagram and a cross-sectional view of an imaging device 401 according to a fourth embodiment, respectively. The imaging device 401 includes a third substrate 143, a third plurality of wiring layers 153, and a second via 162. These elements are included in the pixels 190 of the imaging device 401. In a typical example, these elements are included in each of the plurality of pixels 190 of the imaging device 401.

[0106] The reset transistor 13 and the overflow transistor 14 are located on the first substrate 141. The amplification transistor 11 is located on the second substrate 142. The selection transistor 12 is located on the third substrate 143. The microlens 130, color filter 120, protective film 119, photoelectric conversion unit 110, first multiple wiring layers 151, first substrate 141, second multiple wiring layers 152, second substrate 142, third multiple wiring layers 153, and third substrate 143 are arranged in this order. The third multiple wiring layers 153 are located on the light incidence side of the third substrate 143.

[0107] Figure 10C is a cross-sectional view showing the structure around the second substrate 142. The third set of wiring layers 153 includes wiring layer 153a and wiring layer 153b. The second substrate 142, wiring layer 153a, wiring layer 153b, and the third substrate 143 are arranged in this order.

[0108] The third set of wiring layers 153 are electrically connected to one another. The third set of wiring layers 153 are conductors, including, for example, metals. In the illustrated example, wiring layers 153a and 153b are electrically connected by vias 153x. A second via 162 penetrates the second substrate 142 and electrically connects wiring layers 152b and 153a. The second via 162 is a conductor, including, for example, a metal. The second set of wiring layers 152, the third set of wiring layers 153, and the second via 162 are electrically connected to the charge storage region 35.

[0109] The imaging device 401 includes a third structure 173. The third structure 173 includes a third plurality of wiring layers 153 and a third substrate 143. The second structure 172 and the third structure 173 are joined to each other at a second bonding interface 182.

[0110] As will be described later, in the manufacturing of the imaging device 401, a structure including the second substrate 142 is formed and bonded to the third structure 173. The second bonding interface 182 is, in detail, the bonding interface related to this bonding. After bonding, the second via 162 is formed.

[0111] The wiring layers 152b and 153a constitute a second wiring layer pair 152b, 153a. The second via 162 directly connects the second wiring layer pair 152b, 153a. Furthermore, the second wiring layer pair 152b, 153a is connected using the second via 162 and without using Cu-Cu junctions. This configuration is suitable for providing a fine and low-noise imaging device 401. More generally, the second wiring layer pair 152b, 153a is connected using the second via 162 and without using conductor pad pairs.

[0112] The imaging device 401 includes one or more pixels 190. Each of the one or more pixels 190 includes a first structure 171, a second structure 172, a third structure 173, a first via 161, a second via 162, and a charge storage region 35.

[0113] The first structure 171, the second structure 172, the third structure 173, the first via 161, the second via 162, and the charge storage region 35 may be positioned at locations that overlap with at least one of the microlens 130 and the color filter 120 in a planar view.

[0114] In this embodiment, the wiring layer 152b is the wiring layer closest to the second substrate 142 among the second plurality of wiring layers 152 in the second structure 172. The wiring layer 152b may also be the only wiring layer in the second structure 172.

[0115] In this embodiment, the wiring layer 153a is the wiring layer closest to the second substrate 142 among the third plurality of wiring layers 153 in the third structure 173. The wiring layer 153a may also be the only wiring layer in the third structure 173.

[0116] The first substrate 141 may include a first semiconductor layer 141x and a first oxide film 141y. The first via 161 may penetrate the first oxide film 141y. Specifically, the first oxide film 141y may be an embedded oxide film. The first oxide film 141y, while embedded in the first substrate 141, can isolate semiconductor devices on the first substrate 141. In one example, the first oxide film 141y penetrates the first substrate 141. However, the first oxide film 141y does not have to penetrate the first substrate 141.

[0117] The second substrate 142 may include a second semiconductor layer 142x and a second oxide film 142y. The second via 162 may penetrate the second oxide film 142y. Specifically, the second oxide film 142y may be an embedded oxide film. The second oxide film 142y, while embedded in the second substrate 142, can isolate semiconductor elements on the second substrate 142. In one example, the second oxide film 142y penetrates the second substrate 142. However, the second oxide film 142y does not have to penetrate the second substrate 142.

[0118] The first semiconductor layer 141x and the second semiconductor layer 142x may contain silicon. The first oxide film 141y and the second oxide film 142y may be insulating films. The first oxide film 141y and the second oxide film 142y may contain silicon oxide.

[0119] As can be understood from the above description, the first transistor is provided on the first substrate 141. The second transistor is provided on the second substrate 142. The third transistor is provided on the third substrate 143. Specifically, the first transistor, the second transistor, and the third transistor are provided on one pixel 190, or on each of multiple pixels 190. The configuration of providing multiple transistors on three substrates is advantageous from the viewpoint of securing the size of each individual transistor. In this embodiment, the fourth transistor is provided on the first substrate 141.

[0120] In the illustrated example, the first transistor is a reset transistor 13. The second transistor is an amplification transistor 11. The third transistor is a selection transistor 12. The fourth transistor is an overflow transistor 14.

[0121] As described above, ensuring the size of the amplification transistor 11 and realizing a low-noise amplification transistor 11 is particularly advantageous from the viewpoint of realizing a high-performance imaging device 401. From this viewpoint, it is effective to provide the amplification transistor 11 on a substrate with a relatively small number of transistors. In this embodiment, in one pixel 190, there are two transistors on the first substrate 141 and one transistor on the second substrate 142. The amplification transistor 11 is provided on the second substrate 142. Therefore, this embodiment conforms to the above viewpoint.

[0122] In this embodiment, with respect to the thickness direction of the first substrate 141, the gates of the first transistor and the fourth transistor are positioned between the photoelectric conversion unit 110 and the first substrate 141. With respect to the thickness direction of the second substrate 142, the gate of the second transistor is positioned between the photoelectric conversion unit 110 and the second substrate 142. With respect to the thickness direction of the third substrate 143, the gate of the third transistor is positioned between the photoelectric conversion unit 110 and the third substrate 143.

[0123] In this embodiment, the reset transistor 13 is provided on the first substrate 141. The overflow transistor 14 is provided on the first substrate 141. The amplification transistor 11 is provided on the second substrate 142. The selection transistor 12 is provided on the third substrate 143. This configuration is advantageous from the viewpoint of reducing the number of vias penetrating the substrates in the imaging device 401.

[0124] According to the inventors' studies, in the fourth embodiment, as in the first to third embodiments, it is possible to reduce the number of vias that penetrate the substrate to connect the transistors by devising the arrangement of the transistors. The results of the studies are shown in Tables 3A to 3F. Tables 3A to 3F show the relationship between the substrate on which various transistors are arranged and the above number. Specifically, in Tables 3A to 3F, The "third layer" is a transistor located on the third substrate 143. The number of vias between the second and third layers is the number of vias that penetrate the second board 142. [Table 3A] [Table 3B] [Table 3C] [Table 3D] [Table 3E] [Table 3F]

[0125] As can be seen from Figure 10B, the fourth embodiment corresponds to transistor arrangement (1) in Table 3A.

[0126] Figure 11 is a circuit diagram of the imaging device with the transistor arrangement (11) shown in Table 3B. In the example in Figure 11, the amplification transistor 11 is located on the first substrate 141. The selection transistor 12 is located on the first substrate 141. The overflow transistor 14 is located on the second substrate 142. The reset transistor 13 is located on the third substrate 143.

[0127] Figure 12 is a circuit diagram of the imaging device with the transistor arrangement (12) shown in Table 3B. In the example of Figure 12, the amplification transistor 11 is located on the first substrate 141. The selection transistor 12 is located on the first substrate 141. The reset transistor 13 is located on the second substrate 142. The overflow transistor 14 is located on the third substrate 143.

[0128] Figure 13 is a circuit diagram of the imaging device with the transistor arrangement (19) shown in Table 3D. In the example in Figure 13, the reset transistor 13 is located on the first substrate 141. The overflow transistor 14 is located on the second substrate 142. The amplification transistor 11 is located on the second substrate 142. The selection transistor 12 is located on the third substrate 143.

[0129] Figure 14 is a circuit diagram of the imaging device with the transistor arrangement (23) shown in Table 3D. In the example in Figure 14, the overflow transistor 14 is located on the first substrate 141. The amplification transistor 11 is located on the second substrate 142. The selection transistor 12 is located on the second substrate 142. The reset transistor 13 is located on the third substrate 143.

[0130] Figure 15 is a circuit diagram of the imaging device with the transistor arrangement (24) shown in Table 3D. In the example in Figure 15, the reset transistor 13 is located on the first substrate 141. The amplification transistor 11 is located on the second substrate 142. The selection transistor 12 is located on the second substrate 142. The overflow transistor 14 is located on the third substrate 143.

[0131] Figure 16 is a circuit diagram of the imaging device with the transistor arrangement (35) shown in Table 3F. In the example in Figure 16, the overflow transistor 14 is located on the first substrate 141. The reset transistor 13 is located on the second substrate 142. The amplification transistor 11 is located on the third substrate 143. The selection transistor 12 is located on the third substrate 143.

[0132] Figure 17 is a circuit diagram of the imaging device with the transistor arrangement (36) shown in Table 3F. In the example in Figure 17, the reset transistor 13 is located on the first substrate 141. The overflow transistor 14 is located on the second substrate 142. The amplification transistor 11 is located on the third substrate 143. The selection transistor 12 is located on the third substrate 143.

[0133] The electrical circuits in Figure 10A and Figures 11 through 17 are electrically equivalent.

[0134] Various modifications can be applied to the imaging device 401. For example, the overflow transistor 14 can be omitted. The number of wiring layers included in the third plurality of wiring layers 153 is not particularly limited and may be 2, 3, or 4 or more, as shown in the figure. The second oxide film 142y may be omitted.

[0135] In the first embodiment, the method for manufacturing the second structure 172 was described in steps S101 to S103. This description can be adapted to the method for manufacturing the third structure 173 in the fourth embodiment, with appropriate modifications. • Reinterpretation of "Second board 142" to "Third board 143" • Reinterpretation of "amplifying transistor 11 and selecting transistor 12" to "selecting transistor 12". • Reinterpretation of "second multiple wiring layers 152" to "third multiple wiring layers 153", Includes, etc.

[0136] In the first embodiment, steps S104 to S114 described the method for manufacturing the structural 170 and conductive structure 176 portions of the first structural 171. This description can be adapted to the method for manufacturing the second structural 172 of the fourth embodiment (excluding the pixel electrode 112), with appropriate modifications. • Reinterpretation of "First board 141" to "Second board 142" • Reinterpretation of "reset transistor 13" as "amplifier transistor 11", • Reinterpretation of "Structure 170" as "Structure", • Reinterpretation of "Second Structure 172" to "Third Structure 173" • Reinterpretation of "first through-hole 189a" as "second through-hole". • Reinterpretation of "First Via 161" to "Second Via 162" • Reinterpretation of "the first multiple wiring layers 151" as "the second multiple wiring layers 152", Includes, etc.

[0137] In the fourth embodiment, the first structure 171 may be formed following the second embodiment.

[0138] The same modifications as those applied to the first to third embodiments can also be applied to the manufacturing method of the imaging device 401 of the fourth embodiment.

[0139] As can be understood from the above description, the manufacturing method according to this embodiment includes a second bonding step, a second drilling step, and a second via formation step in this order. In the second bonding step, the structure including the second substrate 142 is bonded to the third structure 173. In the second drilling step, a second through hole is formed in the second substrate 142. In the second via formation step, a second via 162 is formed by filling the second through hole with a second conductor.

[0140] (Fifth embodiment) Figures 18A and 18B are a circuit diagram and a cross-sectional view of an imaging device 501 according to a fifth embodiment, respectively. The imaging device 501 includes a fourth substrate 144, a fourth plurality of wiring layers 154, and a third via 163. These elements are contained within the pixels 190 of the imaging device 501. In a typical example, these elements are contained within each of the plurality of pixels 190 of the imaging device 501.

[0141] The overflow transistor 14 is located on the first substrate 141. The reset transistor 13 is located on the second substrate 142. The amplification transistor 11 is located on the third substrate 143. The selection transistor 12 is located on the fourth substrate 144. The microlens 130, color filter 120, protective film 119, photoelectric conversion unit 110, first multiple wiring layers 151, first substrate 141, second multiple wiring layers 152, second substrate 142, third multiple wiring layers 153, third substrate 143, fourth multiple wiring layers 154, and fourth substrate 144 are arranged in this order. The fourth multiple wiring layers 154 are located on the light incidence side of the fourth substrate 144.

[0142] Figure 18C is a cross-sectional view showing the structure around the third substrate 143. The fourth set of wiring layers 154 includes wiring layer 154a and wiring layer 154b. The third substrate 143, wiring layer 154a, wiring layer 154b, and the fourth substrate 144 are arranged in this order.

[0143] The fourth set of wiring layers 154 are electrically connected to one another. The fourth set of wiring layers 154 are electrically connected to one another. The fourth set of wiring layers 154 are conductors, including, for example, metal. In the illustrated example, wiring layers 154a and 154b are electrically connected by vias 154x. A third via 163 penetrates the third substrate 143 and electrically connects wiring layers 153b and 154a. The third via 163 is a conductor, including, for example, metal. The third set of wiring layers 153, the fourth set of wiring layers 154, and the third via 163 are electrically connected to the charge storage region 35.

[0144] The imaging device 501 includes a fourth structure 174. The fourth structure 174 includes a fourth plurality of wiring layers 154 and a fourth substrate 144. The third structure 173 and the fourth structure 174 are joined to each other at a third bonding interface 183.

[0145] As will be described later, in the manufacturing of the imaging device 501, a structure including the third substrate 143 is formed and bonded to the fourth structure 174. The third bonding interface 183 is, in detail, the bonding interface related to this bonding. After bonding, the third via 163 is formed.

[0146] Wiring layers 153b and 154a constitute a third wiring layer pair 153b and 154a. The third via 163 directly connects the third wiring layer pair 153b and 154a. Furthermore, the third wiring layer pair 153b and 154a are connected using the third via 163 and without using Cu-Cu junctions. This configuration is suitable for providing a fine and low-noise imaging device 501. More generally, the third wiring layer pair 153b and 154a are connected using the third via 163 and without using conductor pad pairs.

[0147] The imaging device 501 includes one or more pixels 190. Each of the one or more pixels 190 includes a first structure 171, a second structure 172, a third structure 173, a fourth structure 174, a first via 161, a second via 162, a third via 163, and a charge storage region 35.

[0148] The first structure 171, second structure 172, third structure 173, fourth structure 174, first via 161, second via 162, third via 163, and charge storage region 35 may be positioned at locations that overlap with at least one of the microlens 130 and the color filter 120 in a planar view.

[0149] In this embodiment, the wiring layer 153b is the wiring layer closest to the third substrate 143 among the third plurality of wiring layers 153 in the third structure 173. The wiring layer 153b may also be the only wiring layer in the third structure 173.

[0150] In this embodiment, the wiring layer 154a is the wiring layer closest to the third substrate 143 among the fourth plurality of wiring layers 154 in the fourth structure 174. The wiring layer 154a may also be the only wiring layer in the fourth structure 174.

[0151] The first substrate 141 may include a first semiconductor layer 141x and a first oxide film 141y. The first via 161 may penetrate the first oxide film 141y. Specifically, the first oxide film 141y may be an embedded oxide film. The first oxide film 141y, while embedded in the first substrate 141, can isolate semiconductor devices on the first substrate 141. In one example, the first oxide film 141y penetrates the first substrate 141. However, the first oxide film 141y does not have to penetrate the first substrate 141.

[0152] The second substrate 142 may include a second semiconductor layer 142x and a second oxide film 142y. The second via 162 may penetrate the second oxide film 142y. Specifically, the second oxide film 142y may be an embedded oxide film. The second oxide film 142y, while embedded in the second substrate 142, can isolate semiconductor elements on the second substrate 142. In one example, the second oxide film 142y penetrates the second substrate 142. However, the second oxide film 142y does not have to penetrate the second substrate 142.

[0153] The third substrate 143 may include a third semiconductor layer 143x and a third oxide film 143y. The third via 163 may penetrate the third oxide film 143y. Specifically, the third oxide film 143y may be an embedded oxide film. The third oxide film 143y, while embedded in the third substrate 143, can isolate semiconductor elements on the third substrate 143. In one example, the third oxide film 143y penetrates the third substrate 143. However, the third oxide film 143y does not have to penetrate the third substrate 143.

[0154] The first semiconductor layer 141x, the second semiconductor layer 142x, and the third semiconductor layer 143x may contain silicon. The first oxide film 141y, the second oxide film 142y, and the third oxide film 143y may be insulating films. The first oxide film 141y, the second oxide film 142y, and the third oxide film 143y may contain silicon oxide.

[0155] As can be understood from the above explanation, the first transistor is provided on the first substrate 141. The second transistor is provided on the second substrate 142. The third transistor is provided on the third substrate 143. The fourth transistor is provided on the fourth substrate 144. Specifically, the first transistor, second transistor, third transistor, and fourth transistor are provided on one pixel 190, or on each of multiple pixels 190. The configuration of providing multiple transistors on four substrates is advantageous from the standpoint of securing the size of each individual transistor.

[0156] In the illustrated example, the first transistor is the overflow transistor 14. The second transistor is the reset transistor 13. The third transistor is the amplification transistor 11. The fourth transistor is the selection transistor 12.

[0157] In this embodiment, with respect to the thickness direction of the first substrate 141, the gate of the first transistor is located between the photoelectric conversion unit 110 and the first substrate 141. With respect to the thickness direction of the second substrate 142, the gate of the second transistor is located between the photoelectric conversion unit 110 and the second substrate 142. With respect to the thickness direction of the third substrate 143, the gate of the third transistor is located between the photoelectric conversion unit 110 and the third substrate 143. With respect to the thickness direction of the fourth substrate 144, the gate of the fourth transistor is located between the photoelectric conversion unit 110 and the fourth substrate 144.

[0158] In this embodiment, the overflow transistor 14 is provided on the first substrate 141. The reset transistor 13 is provided on the second substrate 142. The amplification transistor 11 is provided on the third substrate 143. The selection transistor 12 is provided on the fourth substrate 144. This configuration is advantageous from the viewpoint of reducing the number of vias penetrating the substrates in the imaging device 501.

[0159] According to the inventors' studies, in the fifth embodiment, as in the first to fourth embodiments, it is possible to reduce the number of vias that penetrate the substrate to connect the transistors by devising the arrangement of the transistors. The results of the studies are shown in Tables 4A to 4D. Tables 4A to 4D show the relationship between the substrate on which various transistors are arranged and the above number. Specifically, in Tables 4A to 4D, The "fourth layer" is a transistor located on the fourth substrate 144. The number of vias between the third and fourth layers is the number of vias that penetrate the third board 143. [Table 4A] [Table 4B] [Table 4C] [Table 4D]

[0160] As can be seen from Figure 18B, the fifth embodiment corresponds to transistor arrangement (1) in Table 4A.

[0161] Figure 19 is a circuit diagram of the imaging device with transistor arrangement (7) in Table 4B. In the example in Figure 19, the reset transistor 13 is located on the first substrate 141. The overflow transistor 14 is located on the second substrate 142. The amplification transistor 11 is located on the third substrate 143. The selection transistor 12 is located on the fourth substrate 144.

[0162] The electrical circuits in Figures 18A and 19 are electrically equivalent.

[0163] Various modifications can be applied to the imaging device 501. The number of wiring layers included in the fourth plurality of wiring layers 154 is not particularly limited and may be 2, 3, or 4 or more, as shown in the figure. The third oxide film 143y is optional.

[0164] In the first embodiment, the method for manufacturing the second structure 172 was described in steps S101 to S103. This description can be adapted to the method for manufacturing the fourth structure 174 in the fifth embodiment, with appropriate modifications. • Reinterpretation of "Second board 142" to "Fourth board 144" • Reinterpretation of "amplifying transistor 11 and selecting transistor 12" to "selecting transistor 12". • Reinterpretation of "second multiple wiring layers 152" to "fourth multiple wiring layers 154", Includes, etc.

[0165] In the first embodiment, steps S104 to S114 described the method for manufacturing the structural 170 and conductive structure 176 portions of the first structural 171. This description can be adapted to the method for manufacturing the third structural 173 of the fifth embodiment (excluding the pixel electrode 112), with appropriate modifications. • Reinterpretation of "First board 141" to "Third board 143" • Reinterpretation of "reset transistor 13" as "amplifier transistor 11", • Reinterpretation of "Structure 170" as "Structure", • Reinterpretation of "Second Structure 172" to "Fourth Structure 174" • Reinterpretation of "First through-hole 189a" as "Third through-hole", • Reinterpretation of "First Via 161" to "Third Via 163" • Reinterpretation of "the first multiple wiring layers 151" to "the third multiple wiring layers 153", Includes, etc.

[0166] In the first embodiment, steps S104 to S114 described the method for manufacturing the structural 170 and conductive structure 176 portions of the first structural 171. This description can be adapted to the method for manufacturing the second structural 172 of the fifth embodiment (excluding the pixel electrode 112), with appropriate modifications. • Reinterpretation of "First board 141" to "Second board 142" • Reinterpretation of "Structure 170" as "Structure", • Reinterpretation of "Second Structure 172" to "Third Structure 173" • Reinterpretation of "first through-hole 189a" as "second through-hole". • Reinterpretation of "First Via 161" to "Second Via 162" • Reinterpretation of "the first multiple wiring layers 151" as "the second multiple wiring layers 152", Includes, etc.

[0167] Regarding the manufacture of the first structure 171, the description of step S105 of the first embodiment may be incorporated into the description of the fifth embodiment with appropriate modifications. • Reinterpretation of "reset transistor 13" as "overflow transistor 14", Includes, etc.

[0168] The same modifications as those applied to the first to fourth embodiments can also be applied to the manufacturing method of the imaging device 501 of the fifth embodiment.

[0169] As can be understood from the above description, the manufacturing method according to this embodiment includes a third bonding step, a third drilling step, and a third via formation step in this order. In the third bonding step, the structure including the third substrate 143 is bonded to the fourth structure 174. In the third drilling step, a third through hole is formed in the third substrate 143. In the third via formation step, a third via 163 is formed by filling the third through hole with a third conductor.

[0170] From the fourth and fifth embodiments, the following techniques are derived: a method for manufacturing an imaging device includes a repetition step and a film formation step. The repetition step repeats a unit step that includes, in this order, a raising step, a drilling step, and a via formation step. In the raising step, the structure is raised by stacking a substrate on top of the already formed structure. In the drilling step, through holes are formed in the substrate. In the via formation step, vias are formed in the through holes. In the film formation step, a photoelectric conversion film is formed on top of the structure. The number of repetitions of the unit step in the repetition step may be two, three, four, or five or more. Typically, the film formation step is performed after the repetition step.

[0171] (Sixth embodiment) Figures 20A and 20B are a circuit diagram and a cross-sectional view of the imaging device 601 according to the sixth embodiment, respectively. In the imaging device 601, the photoelectric conversion unit 110 is a photodiode. The photoelectric conversion unit 110 is provided in the first substrate 141. The imaging device 601 also includes a transfer transistor 15. The transfer transistor 15 is provided on the first substrate 141. The photoelectric conversion unit 110 and the transfer transistor 15 are included in the pixels 190 of the imaging device 601. In a typical example, the photoelectric conversion unit 110 and the transfer transistor 15 are included in each of the multiple pixels 190 of the imaging device 601.

[0172] The photoelectric conversion unit 110 is electrically connected to one of the source and drain of the transfer transistor 15. The other of the source and drain of the transfer transistor 15 is electrically connected to one of the source and drain of the reset transistor 13 and the gate 11g of the amplification transistor 11. One of the source and drain of the reset transistor 13 constitutes a charge storage region 35. The other of the source and drain of the transfer transistor 15 also constitutes a charge storage region 35. In other words, the charge storage region 35 is shared by the reset transistor 13 and the transfer transistor 15. The first via 161 is electrically connected to the charge storage region 35.

[0173] In this embodiment, with respect to the thickness direction of the first substrate 141, the gate 13g of the reset transistor 13 and the gate 15g of the transfer transistor 15 are located between the microlens 130 and the first substrate 141. With respect to the thickness direction of the second substrate 142, the gate 11g of the amplification transistor 11 and the gate 12g of the selection transistor 12 are located between the microlens 130 and the second substrate 142.

[0174] The photoelectric conversion unit 110 converts light into electric charge. The transfer transistor 15 transfers the charge from the photoelectric conversion unit 110 to the charge storage region 35.

[0175] (Comparison of the manufacturing methods of the first to fifth embodiments and the manufacturing method of the sixth embodiment) As described above, in the sixth embodiment, the photoelectric conversion unit 110 is a photodiode. In the sixth embodiment, step S105 is modified to form the transfer transistor 15 and the photodiode on the first substrate 141 together with the reset transistor 13. For this purpose, the photodiode is formed, then the junction in step S109 is performed, and then the first via 161, the first plurality of wiring layers 151, etc. are formed in steps S111 to S114.

[0176] In contrast, in the first to fifth embodiments, the photoelectric conversion unit 110 includes a photoelectric conversion film 111. In the manufacturing method of the imaging device when the photoelectric conversion unit 110 includes a photoelectric conversion film 111, a transistor is formed on the first substrate 141 in step S105, then the junction in step S109 is performed, then the first via 161, the first plurality of wiring layers 151, etc. are formed in steps S111 to S114, and then the photoelectric conversion unit 110 can be formed. Because the timing of the formation of the photoelectric conversion unit 110 can be delayed, according to the first to fifth embodiments, degradation of the photoelectric conversion unit 110 during the manufacturing of the imaging device can be suppressed compared to the sixth embodiment. This is advantageous from the viewpoint of realizing a reliable imaging device. When the photoelectric conversion film 111 contains organic materials, the photoelectric conversion film 111 tends to be easily damaged during manufacturing. For this reason, the above degradation suppression effect is particularly useful when the photoelectric conversion film 111 contains organic materials.

[0177] (Camera system) The camera system 705 according to this embodiment will be described with reference to Figure 21.

[0178] Figure 21 schematically shows an example of the configuration of a camera system 705 according to this embodiment. The camera system 705 comprises a lens optical system 701, an imaging device 702, a system controller 703, and a camera signal processing circuit 704. The camera system 705 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0179] The lens optical system 701 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. The lens optical system 701 focuses light onto the imaging plane of the imaging device 702. The imaging device 702 can be broadly selected from the imaging devices according to the first to sixth embodiments described above. In addition, the imaging devices further described in the first to sixth embodiments can be broadly selected from the imaging device 702.

[0180] The system controller 703 controls the entire camera system 705. The system controller 703 is typically a semiconductor integrated circuit, such as a CPU (Central Processing Unit).

[0181] The signal processing circuit 704 has the function of processing the output signal from the imaging device 702. The signal processing circuit 704 receives output data from the imaging device 702 and performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The imaging device 702 and the signal processing circuit 704 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). With such a configuration, the electronic device including the imaging device 702 as part can be made smaller. The signal processing circuit 704 may be, for example, a DSP (Digital Signal Processor).

[0182] As can be understood from the above explanation, a camera system may include a lens optical system, an imaging device, and a signal processing circuit. The imaging device receives light that has passed through the lens optical system and outputs a signal. The signal processing circuit processes the signal.

[0183] (Note) This disclosure provides for the following technologies:

[0184] (Technology 1) It has at least one pixel, Each of the at least one of the aforementioned pixels is A first structure having a photoelectric conversion unit that converts light into electric charge, one of a first wiring layer pair, and a first substrate, A second structure having the other of the first wiring layer pair and a second substrate, A first via that penetrates the first substrate and directly connects the first wiring layer pair, A charge storage region is provided on any of the plurality of substrates, including the first substrate and the second substrate, for storing the charge and being electrically connected to the first via, Equipped with, The first wiring layer pair, the first substrate, the other part of the first wiring layer pair, and the second substrate are arranged in this order. Imaging device.

[0185] Technology 1 is suitable for providing a fine and low-noise imaging device. Note that the phrase "each of at least one pixel" means each of multiple pixels if there are multiple pixels. If there is only one pixel, this phrase means that single pixel.

[0186] (Technology 2) One of the first pair of wiring layers is either the only wiring layer in the first structure, or the wiring layer closest to the first substrate among a plurality of wiring layers in the first structure. The other of the first pair of wiring layers is the only wiring layer in the second structure, or the wiring layer closest to the first substrate among a plurality of wiring layers in the second structure. The imaging device described in Technical 1.

[0187] Technology 2 is advantageous in terms of suppressing parasitic capacitance in charge storage nodes, including charge storage regions.

[0188] (Technology 3) The first substrate has a first embedded oxide film, The first via penetrates the first embedded oxide film. An imaging device as described in Technology 1 or 2.

[0189] Technology 3 is advantageous in terms of suppressing parasitic capacitance in charge storage nodes, including charge storage regions.

[0190] (Technology 4) Each of the at least one of the aforementioned pixels is The first transistor provided on the first substrate, The second transistor provided on the second substrate, Equipped with, An imaging device as described in any one of the three technical specifications (1 to 3).

[0191] Technology 4 is advantageous in that it achieves at least one of the following: securing the size of the transistors and reducing the size of the imaging device.

[0192] (Technology 5) One of the first transistor and the second transistor is an amplifying transistor that outputs a signal corresponding to the potential of the charge storage region. The imaging device described in Technical 4.

[0193] Technology 5 is advantageous from the standpoint of realizing a high-performance imaging device.

[0194] (Technology 6) The other of the first transistor and the second transistor is a reset transistor that resets the charge stored in the charge storage region. The imaging device described in Technical 5.

[0195] Technology 6 is advantageous from the standpoint of realizing a high-performance imaging device.

[0196] (Technology 7) Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, A selection transistor that determines the timing for outputting the signal from the amplification transistor, Equipped with, (a1) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the second substrate, or (a2) The amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the second substrate. An imaging apparatus as described in any one of the technical items 1 to 6.

[0197] Technology 7 is advantageous in terms of reducing the number of vias that penetrate the substrate in the imaging device.

[0198] (Technology 8) Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, An overflow transistor includes a gate electrically connected to the charge storage region, which discharges the charge from the charge storage region by turning on in accordance with the potential of the charge storage region, Equipped with, (A1) The overflow transistor is provided on the first substrate, the reset transistor is provided on the first substrate, and the amplification transistor is provided on the second substrate, or (A2) The amplification transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the reset transistor is provided on the second substrate. An imaging device as described in any one of the technical items 1 to 7.

[0199] Technology 8 is advantageous in terms of reducing the number of vias that penetrate the substrate in the imaging device.

[0200] (Technology 9) Each of the at least one of the aforementioned pixels is The third structure and Second Via and Equipped with, The second structure has one of the second wiring layer pairs, The third structure comprises the other of the second wiring layer pair and the third substrate among the plurality of substrates, The second via penetrates the second substrate and directly connects the second wiring layer pair. The one of the second wiring layer pair, the second substrate, the other of the second wiring layer pair, and the third substrate are arranged in this order. An imaging device as described in any one of the technical items 1 to 8.

[0201] Technology 9 is suitable for providing a fine and low-noise imaging device. Regarding Technology 1 and Technology 9, the other of the first wiring layer pair and the one of the second wiring layer pair may be the same or different.

[0202] (Technology 10) Each of the at least one of the aforementioned pixels is The first transistor provided on the first substrate, The second transistor provided on the second substrate, A third transistor provided on the third substrate, Equipped with, The imaging device described in Technical 9.

[0203] Technology 10 is advantageous in terms of achieving at least one of the following: ensuring sufficient transistor size and reducing the size of the imaging device.

[0204] (Technology 11) Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, A selection transistor that determines the timing for outputting the signal from the amplification transistor, Equipped with, (d1) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the third substrate. (d2) The amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the third substrate. (d3) The amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the second substrate. (d4) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the third substrate. (d5) The amplification transistor is provided on the second substrate, the selection transistor is provided on the second substrate, and the reset transistor is provided on the third substrate. (d6) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the second substrate. (d7) The reset transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the third substrate, or (d8) The reset transistor is provided on the first substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the third substrate. The imaging device according to Technique 9 or 10.

[0205] Technique 11 is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device.

[0206] (Technique 12) Each of the at least one pixel includes an amplification transistor that outputs a signal according to the potential of the charge storage region, a reset transistor that resets the charge stored in the charge storage region, an overflow transistor that includes a gate electrically connected to the charge storage region and discharges the charge from the charge storage region by turning on according to the potential of the charge storage region, and is provided with (D1) The reset transistor is provided on the first substrate, the overflow transistor is provided on the first substrate, and the amplification transistor is provided on the second substrate. (D2) The amplification transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the reset transistor is provided on the third substrate. (D3) The amplification transistor is provided on the first substrate, the reset transistor is provided on the second substrate, and the overflow transistor is provided on the third substrate. (D4) The reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the amplification transistor is provided on the second substrate. (D5) The overflow transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the reset transistor is provided on the third substrate. (D6) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the overflow transistor is provided on the third substrate. (D7) The overflow transistor is provided on the first substrate, the reset transistor is provided on the second substrate, and the amplification transistor is provided on the third substrate, or (D8) The reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the amplification transistor is provided on the third substrate. The imaging device according to any one of Technologies 9 to 11.

[0207] Technology 12 is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device.

[0208] (Technology 13) Each of the at least one pixel a fourth structure, a third via, and includes The third structure has one of a pair of third wiring layers. The fourth structure comprises the other of the third wiring layer pair and the fourth substrate among the plurality of substrates, The third via penetrates the third substrate and directly connects the third wiring layer pair. The one of the third wiring layer pair, the third substrate, the other of the third wiring layer pair, and the fourth substrate are arranged in this order. An imaging apparatus as described in any one of the technical items 9 to 12.

[0209] Technology 13 is suitable for providing a fine and low-noise imaging device. Regarding Technology 9 and Technology 13, the other of the second wiring layer pair and the one of the third wiring layer pair may be the same or different.

[0210] (Technology 14) Each of the at least one of the aforementioned pixels is The first transistor provided on the first substrate, The second transistor provided on the second substrate, A third transistor provided on the third substrate, The fourth transistor provided on the fourth substrate, Equipped with, The imaging device described in Technical 13.

[0211] Technology 14 is advantageous in terms of achieving at least one of the following: ensuring sufficient transistor size and reducing the size of the imaging device.

[0212] (Technology 15) Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, A selection transistor that determines the timing for outputting the signal from the amplification transistor, An overflow transistor including a gate electrically connected to the charge storage region, and discharging the charge from the charge storage region by turning on according to the potential of the charge storage region; comprising; (f1) The overflow transistor is provided on the first substrate, the reset transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the fourth substrate, or (f2) The reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the fourth substrate. The imaging device according to Technique 13 or 14.

[0213] Technique 15 is advantageous from the viewpoint of suppressing the number of vias penetrating the substrate in the imaging device.

[0214] (Technique 16) Each of the at least one pixel includes a transistor provided on the second substrate, The transistor includes a gate, In the thickness direction of the second substrate, the gate is disposed between the photoelectric conversion unit and the second substrate. The imaging device according to any one of Techniques 1 to 15.

[0215] Technique 16 is advantageous from the viewpoint of realizing a low-noise first transistor.

[0216] (Technique 17) The photoelectric conversion unit includes a photoelectric conversion film. The imaging device according to any one of Techniques 1 to 16.

[0217] The configuration of Technique 17 is one configuration example.

[0218] (Technique 18) The photoelectric conversion film includes an organic material. The imaging device described in Technical 17.

[0219] The configuration of Technology 18 is just one example.

[0220] (Technology 19) A first structure having a photoelectric conversion unit that converts light into electric charge, one of a first wiring layer pair, and a first substrate, A second structure having the other of the first wiring layer pair and a second substrate, A first via that penetrates the aforementioned first substrate, A charge storage region is provided on any of the plurality of substrates, including the first substrate and the second substrate, for storing the charge and being electrically connected to the first via, Equipped with, The first wiring layer pair, the first substrate, the other part of the first wiring layer pair, and the second substrate are arranged in this order. The first wiring layer pair is connected using the first via and without using Cu-Cu junctions. Imaging device.

[0221] Technology 19 is suitable for providing a fine and low-noise imaging device.

[0222] (Technology 20) Lens optical system, An imaging device according to any one of the techniques 1 to 19, which receives light that has passed through the aforementioned lens optical system and outputs a signal, A signal processing circuit that processes the aforementioned signal, Equipped with, Camera system.

[0223] Technology 20 is suitable for providing a fine and low-noise imaging device.

[0224] (Technology 21) A first structure comprising a photoelectric conversion film that converts light into electric charge, one of a first wiring layer pair, and a first substrate, A second structure having the other of the first wiring layer pair and a second substrate, A first via that penetrates the first substrate and directly connects the first wiring layer pair, A charge storage region is provided on any of the plurality of substrates, including the first substrate and the second substrate, for storing the charge and being electrically connected to the first via, A method for manufacturing an imaging device equipped with, The second structure is joined to the structure including the first substrate, The first substrate is formed to create a first through-hole, The first via is formed by filling the first through hole with the first conductor, Forming the aforementioned photoelectric conversion film, A manufacturing method that includes these elements in this order.

[0225] Technology 21 is suitable for providing a fine and low-noise imaging device.

[0226] (Technology 22) The imaging device is The third structure and Second Via and Equipped with, The second structure has one of the second wiring layer pairs, The third structure comprises the other of the second wiring layer pair and the third substrate among the plurality of substrates, The second via penetrates the second substrate and directly connects the second wiring layer pair. The aforementioned manufacturing method is The third structure is joined to the structure including the second substrate, The second substrate is formed to create a second through-hole, The second via is formed by filling the second through-hole with the second conductor, It includes in this order, Manufacturing method as described in Technical 21.

[0227] Technology 22 is suitable for providing a fine and low-noise imaging device.

[0228] (Technology 23) The imaging device is The fourth structure, Third Via and Equipped with, The third structure has one of the third wiring layer pairs, The fourth structure comprises the other of the third wiring layer pair and the fourth substrate among the plurality of substrates, The third via penetrates the third substrate and directly connects the third wiring layer pair. The aforementioned manufacturing method is The fourth structure is joined to the structure including the third substrate, To form a third through-hole in the third substrate, The third via is formed by filling the third through hole with a third conductor, A manufacturing method described in Technical 22, comprising the elements in this order.

[0229] Technology 23 is suitable for providing a fine and low-noise imaging device.

[0230] (Technology 24) Repeating the following steps in this order: raising the structure by stacking a substrate on top of the already formed structure, forming through holes in the substrate, and forming vias in the through holes. A photoelectric conversion film is formed on top of the aforementioned structure, including, A method for manufacturing an imaging device.

[0231] Technology 24 is suitable for providing a fine and low-noise imaging device. [Industrial applicability]

[0232] The imaging device of this disclosure is useful for digital cameras and the like. The imaging device of this disclosure can be used, for example, in mobile terminals and the like. [Explanation of symbols]

[0233] 11, 12, 13, 14, 15 Transistors 11g, 12g, 13g, 14g, 15g gate 21, 23, 24 Voltage lines 22 signal lines 30 Charge Storage Nodes 35 Charge storage region 101, 201, 301, 401, 501, 601, 801, 901 Imaging devices 110, 810, 910 Photoelectric conversion unit 111 Photoelectric conversion film 112 Pixel Electrodes 113 Counter electrode 965 Electrical Path 151x, 152x, 153x, 161, 162, 163, 166, 167, 961, 962 Beer 119 Protective film 120 Color Filters 130 Microlenses 141, 142, 143, 144, 841, 842, 941, 942 circuit boards 141a, 141c Silicon film 141b, 185, 186 insulating film 141bs bottom 141x, 142x, 143x semiconductor layers 141y, 142y, 143y oxide film 151, 152, 153, 154, 852, 952 wiring layer 170, 171, 172, 173, 174, 870, 872, 970, 972 structure 176 Conductive structure 181, 182, 183, 881, 981 Joint interface 185s, 186s top surface 187 Support substrate 188a, 188b Trench 189a, 189b through hole 190 pixels 200 Camera System 701 Lens Optics 702 Imaging device 703 System Controller 704 Signal Processing Circuit 704 Camera signal processing unit 705 Camera System 861 Cu-Cu junction 861a, 861b Cu pad 966 Return section 967 Peripheral area

Claims

1. It has at least one pixel, Each of the at least one of the aforementioned pixels is A first structure having a photoelectric conversion unit that converts light into electric charge, one of a first wiring layer pair, and a first substrate, A second structure having the other of the first wiring layer pair and a second substrate, A first via that penetrates the first substrate and directly connects the first wiring layer pair, A charge storage region is provided on any of the plurality of substrates, including the first substrate and the second substrate, for storing the charge and being electrically connected to the first via, Equipped with, The first wiring layer pair, the first substrate, the other part of the first wiring layer pair, and the second substrate are arranged in this order. Imaging device.

2. One of the first pair of wiring layers is the only wiring layer in the first structure, or is the wiring layer closest to the first substrate among a plurality of wiring layers in the first structure. The other of the first pair of wiring layers is the only wiring layer in the second structure, or the wiring layer closest to the first substrate among a plurality of wiring layers in the second structure. The imaging apparatus according to claim 1.

3. The first substrate has a first embedded oxide film, The first via penetrates the first embedded oxide film. The imaging apparatus according to claim 1.

4. Each of the at least one of the aforementioned pixels is The first transistor provided on the first substrate, The second transistor provided on the second substrate, Equipped with, The imaging apparatus according to claim 1.

5. One of the first transistor and the second transistor is an amplifying transistor that outputs a signal corresponding to the potential of the charge storage region. The imaging apparatus according to claim 4.

6. The other of the first transistor and the second transistor is a reset transistor that resets the charge stored in the charge storage region. The imaging apparatus according to claim 5.

7. Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, A selection transistor that determines the timing for outputting the signal from the amplification transistor, Equipped with, (a1) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the second substrate, or (a2) The amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the second substrate. The imaging apparatus according to claim 1.

8. Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, An overflow transistor includes a gate electrically connected to the charge storage region, which discharges the charge from the charge storage region by turning on in accordance with the potential of the charge storage region, Equipped with, (A1) The overflow transistor is provided on the first substrate, the reset transistor is provided on the first substrate, and the amplification transistor is provided on the second substrate, or (A2) The amplification transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the reset transistor is provided on the second substrate. The imaging apparatus according to claim 1.

9. Each of the at least one of the aforementioned pixels is The third structure, Second Via and Equipped with, The second structure has one of the second wiring layer pairs, The third structure comprises the other of the second wiring layer pair and the third substrate among the plurality of substrates, The second via penetrates the second substrate and directly connects the second wiring layer pair. The one of the second wiring layer pair, the second substrate, the other of the second wiring layer pair, and the third substrate are arranged in this order. The imaging apparatus according to claim 1.

10. Each of the at least one of the aforementioned pixels is The first transistor provided on the first substrate, The second transistor provided on the second substrate, A third transistor provided on the third substrate, Equipped with, The imaging device according to claim 9.

11. Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, A selection transistor that determines the timing for outputting the signal from the amplification transistor, Equipped with, (d1) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the third substrate. (d2) The amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the third substrate. (d3) The amplification transistor is provided on the first substrate, the selection transistor is provided on the first substrate, and the reset transistor is provided on the second substrate. (d4) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the third substrate. (d5) The amplification transistor is provided on the second substrate, the selection transistor is provided on the second substrate, and the reset transistor is provided on the third substrate. (d6) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the selection transistor is provided on the second substrate. (d7) The reset transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the third substrate, or (d8) The reset transistor is provided on the first substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the third substrate. The imaging device according to claim 9.

12. Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, An overflow transistor includes a gate electrically connected to the charge storage region, which discharges the charge from the charge storage region by turning on in accordance with the potential of the charge storage region, Equipped with, (D1) The reset transistor is provided on the first substrate, the overflow transistor is provided on the first substrate, and the amplification transistor is provided on the second substrate. (D2) The amplification transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the reset transistor is provided on the third substrate. (D3) The amplification transistor is provided on the first substrate, the reset transistor is provided on the second substrate, and the overflow transistor is provided on the third substrate. (D4) The reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the amplification transistor is provided on the second substrate. (D5) The overflow transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the reset transistor is provided on the third substrate. (D6) The reset transistor is provided on the first substrate, the amplification transistor is provided on the second substrate, and the overflow transistor is provided on the third substrate. (D7) The overflow transistor is provided on the first substrate, the reset transistor is provided on the second substrate, and the amplification transistor is provided on the third substrate, or (D8) The reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, and the amplification transistor is provided on the third substrate. The imaging device according to claim 9.

13. Each of the at least one of the aforementioned pixels is The fourth structure, Third Via and Equipped with, The third structure has one of the third wiring layer pairs, The fourth structure comprises the other of the third wiring layer pair and the fourth substrate among the plurality of substrates, The third via penetrates the third substrate and directly connects the third wiring layer pair. The one of the third wiring layer pair, the third substrate, the other of the third wiring layer pair, and the fourth substrate are arranged in this order. The imaging device according to claim 9.

14. Each of the at least one of the aforementioned pixels is The first transistor provided on the first substrate, The second transistor provided on the second substrate, A third transistor provided on the third substrate, The fourth transistor provided on the fourth substrate, Equipped with, The imaging device according to claim 13.

15. Each of the at least one of the aforementioned pixels is An amplifying transistor that outputs a signal corresponding to the potential of the charge storage region, A reset transistor for resetting the charge accumulated in the charge storage region, A selection transistor that determines the timing for outputting the signal from the amplification transistor, An overflow transistor includes a gate electrically connected to the charge storage region, which discharges the charge from the charge storage region by turning on in accordance with the potential of the charge storage region, Equipped with, (f1) The overflow transistor is provided on the first substrate, the reset transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the fourth substrate, or (f2) The reset transistor is provided on the first substrate, the overflow transistor is provided on the second substrate, the amplification transistor is provided on the third substrate, and the selection transistor is provided on the fourth substrate. The imaging device according to claim 13.

16. Each of the at least one pixels comprises a transistor provided on the second substrate, The transistor includes a gate, With respect to the thickness direction of the second substrate, the gate is positioned between the photoelectric conversion unit and the second substrate. The imaging apparatus according to claim 1.

17. The photoelectric conversion unit includes a photoelectric conversion film, The imaging apparatus according to claims 1 to 16.

18. The aforementioned photoelectric conversion film includes an organic material. The imaging apparatus according to claim 17.

Images