Imaging device

Abstract

The present invention provides an imaging device that enables low-noise imaging when mixing adjacent pixels. [Solution] An imaging device 1 according to one aspect of the present disclosure comprises a plurality of unit pixels 101, each of which includes a photoelectric conversion layer 120 including a first surface on the light incident side and a second surface opposite to the first surface, a plurality of pixel electrodes 102 located on the second surface of the photoelectric conversion layer 120, a plurality of transistors corresponding one-to-one to the plurality of pixel electrodes 102, and an auxiliary electrode 104 located on the second surface of the photoelectric conversion layer 120 and surrounding the plurality of pixel electrodes 102 in a plan view. The signals output by each of the two or more transistors corresponding to two or more of the plurality of pixel electrodes 102 are combined into a single analog signal. The auxiliary electrode 104 is not present between two adjacent pixel electrodes 102 of the two or more pixel electrodes 102.

Description

Technical Field

[0001] The present disclosure relates to an imaging device.

Background Art

[0002] In an imaging device having a photoelectric conversion section in which a photoelectric conversion layer is sandwiched between a pixel electrode and a counter electrode, a configuration in which a shield electrode is provided between adjacent pixel electrodes has been proposed (see, for example, Patent Document 1). With this configuration, it is possible to prevent signal charges generated in each pixel from mixing with each other, and to suppress color mixing between pixels and deterioration of image quality.

[0003] In addition, an imaging element has been proposed in which a unit pixel includes a total of four photodiodes, two vertically and two horizontally, and the signals obtained by the four photodiodes are combined (see, for example, Patent Document 2). In this imaging element, distance measurement is possible during imaging depending on the method of combining the signals obtained by the four photodiodes. Note that the color filters are arranged in a Bayer pattern with four photodiodes as one color unit.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] There is a demand for an imaging device with reduced noise.

Means for Solving the Problems

[0006] To solve the above problems, an imaging device according to one aspect of the present disclosure includes a plurality of unit pixels, each of which includes a first surface on the light incident side and a second surface opposite to the first surface, a photoelectric conversion layer that converts light into signal charges, a plurality of first electrodes located on the second surface of the photoelectric conversion layer that collect signal charges, a plurality of transistors corresponding one-to-one to the plurality of first electrodes, each outputting a signal corresponding to the amount of signal charge collected by the corresponding first electrode among the plurality of first electrodes, and a second electrode located on the second surface of the photoelectric conversion layer that surrounds the plurality of first electrodes in a plan view. The signals output by each of the two or more transistors corresponding to two or more of the plurality of first electrodes are combined into a single analog signal. The second electrode does not exist between two adjacent first electrodes among the two or more first electrodes. [Effects of the Invention]

[0007] According to one aspect of this disclosure, an imaging device with reduced noise can be provided. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram showing an exemplary configuration of an imaging device according to the first embodiment. [Figure 2] Figure 2 is a schematic circuit diagram showing an exemplary circuit configuration of a unit pixel according to the first embodiment. [Figure 3A] Figure 3A is a plan view showing an exemplary configuration of multiple pixel electrodes and auxiliary electrodes in a unit pixel according to the first embodiment. [Figure 3B] Figure 3B is a plan view showing an exemplary configuration of multiple microlenses in a unit pixel according to the first embodiment. [Figure 4] Figure 4 is a schematic cross-sectional view showing an exemplary configuration of a unit pixel according to the first embodiment. [Figure 5A] Figure 5A is a plan view showing an exemplary configuration of multiple pixel electrodes and auxiliary electrodes in multiple unit pixels according to the first embodiment. [Figure 5B]Figure 5B is a plan view showing an exemplary configuration of multiple microlenses in multiple unit pixels according to the first embodiment. [Figure 6] Figure 6 is a plan view of multiple unit pixels when using the color filter according to the first embodiment. [Figure 7] Figure 7 is a plan view of multiple unit pixels in the case of monochrome imaging according to the first embodiment. [Figure 8] Figure 8 is a circuit diagram showing an exemplary configuration of an imaging device according to a modified example of the first embodiment. [Figure 9] Figure 9 is an illustrative circuit diagram of a unit pixel according to a modified example of the first embodiment. [Figure 10A] Figure 10A is an exemplary circuit diagram showing the connection between a unit pixel and a column circuit according to a modified example of the first embodiment. [Figure 10B] Figure 10B is an exemplary circuit diagram showing the connection between a unit pixel and a column circuit according to a modified example of the first embodiment. [Figure 11] Figure 11 is a plan view showing an exemplary configuration of a microlens in a unit pixel according to the second embodiment. [Figure 12] Figure 12 is a schematic cross-sectional view showing an exemplary configuration of a unit pixel according to the second embodiment. [Figure 13A] Figure 13A is a plan view showing an exemplary configuration of multiple pixel electrodes and auxiliary electrodes in a unit pixel according to the third embodiment. [Figure 13B] Figure 13B is a plan view showing an exemplary configuration of multiple microlenses in a unit pixel according to the third embodiment. [Figure 14A] Figure 14A is a plan view showing an exemplary configuration of multiple pixel electrodes and auxiliary electrodes in a unit pixel according to the fourth embodiment. [Figure 14B] Figure 14B is a plan view showing an exemplary configuration of a microlens in a unit pixel according to the fourth embodiment. [Figure 15A] Figure 15A is a plan view showing an exemplary configuration of multiple pixel electrodes and auxiliary electrodes in a unit pixel according to the fifth embodiment. [Figure 15B] FIG. 15B is a plan view showing an exemplary configuration of a microlens in a unit pixel according to the fifth embodiment. [Figure 16A] FIG. 16A is a plan view showing an exemplary configuration of a plurality of pixel electrodes and auxiliary electrodes in a unit pixel according to a modification of the fifth embodiment. [Figure 16B] FIG. 16B is a plan view showing an exemplary configuration of a microlens in a unit pixel according to a modification of the fifth embodiment. [Figure 17A] FIG. 17A is a layout view showing an exemplary configuration of a plurality of pixel electrodes and auxiliary electrodes in a unit pixel according to the sixth embodiment. [Figure 17B] FIG. 17B is a plan view showing an exemplary configuration of a microlens in a unit pixel according to the sixth embodiment. [Figure 18A] FIG. 18A is a plan view showing an exemplary configuration of a plurality of pixel electrodes and auxiliary electrodes in a unit pixel according to a modification of the sixth embodiment. [Figure 18B] FIG. 18B is a plan view showing an exemplary configuration of a microlens in a unit pixel according to a modification of the sixth embodiment. [Figure 19] FIG. 19 is a circuit diagram showing an exemplary configuration of a unit pixel according to the seventh embodiment. [Figure 20] FIG. 20 is an exemplary circuit diagram showing the connection between a unit pixel and a column circuit according to the seventh embodiment. [Figure 21] FIG. 21 is a plan view showing an exemplary configuration of a plurality of pixel electrodes and auxiliary electrodes in a unit pixel according to the seventh embodiment. [Figure 22] FIG. 22 is a schematic cross-sectional view showing an exemplary configuration of a unit pixel according to the seventh embodiment. [Figure 23] FIG. 23 is a block diagram showing a configuration example of a camera system according to the eighth embodiment. [Embodiments for Carrying Out the Invention]

[0009] (Findings on which the present disclosure is based) First, let me explain the background leading to this disclosure. The organic CMOS (Complementary MOS (Metal Oxide Semiconductor)) sensor has a stacked structure in which a photoelectric conversion section having an organic photoelectric conversion film is stacked on a CMOS chip that includes a detection circuit (also called a readout circuit). The charge generated in the photoelectric conversion film (also called a photoelectric conversion layer) is stored in a charge storage region via the pixel electrodes and wiring. The charge stored in the charge storage region is read out as a voltage by the detection circuit and output as image data. In imaging devices using such organic CMOS sensors, there is a need to reduce noise.

[0010] To address the above issues, the inventors of this invention considered a configuration in which a unit pixel is divided into multiple cells and the signals obtained from the multiple cells are combined, and focused on auxiliary electrodes between pixel electrodes in this configuration. Capacitive coupling between auxiliary electrodes and pixel electrodes increases the FD (Floating Diffusion Node) capacitance. An increase in FD capacitance can be a contributing factor to increased noise. As a result of the investigation, the inventors arrived at the configuration of this disclosure in which auxiliary electrodes are provided between pixel electrodes that are not in a signal-combining relationship, and auxiliary electrodes are not provided between pixel electrodes that are in a signal-combining relationship. With this configuration, capacitive coupling between pixel electrodes and auxiliary electrodes can be reduced, while charge mixing (charge transfer) between pixel electrodes that are not in a signal-combining relationship can be reduced. Furthermore, by not providing auxiliary electrodes between pixel electrodes within a unit pixel, the degree of design freedom for the arrangement and shape of pixel electrodes within a unit pixel is improved. By utilizing this and devising the arrangement of microlenses and pixel electrodes that constitute the unit pixel, the inventors arrived at other configurations of this disclosure that can improve performance such as sensitivity while reducing noise.

[0011] The imaging device relating to one aspect of this disclosure is as described in items 1 to 15 below.

[0012] [Item 1] An imaging device comprising: a photoelectric conversion layer that converts light into signal charges, each of which has multiple unit pixels, each of which includes a first surface on the light incident side and a second surface opposite to the first surface; a plurality of first electrodes located on the second surface of the photoelectric conversion layer that collect signal charges; a plurality of transistors that correspond one-to-one with the plurality of first electrodes, each outputting a signal corresponding to the amount of signal charge collected by the corresponding first electrode among the plurality of first electrodes; and a second electrode located on the second surface of the photoelectric conversion layer that surrounds the plurality of first electrodes in a plan view, wherein the signals output by each of the two or more transistors corresponding to two or more of the plurality of first electrodes are combined into a single analog signal, and the second electrode does not exist between two adjacent first electrodes among the two or more first electrodes.

[0013] This configuration reduces noise in each unit pixel while mitigating charge mixing between unit pixels.

[0014] [Item 2] The imaging apparatus as described in item 1, wherein the second electrode is not located between any two adjacent first electrodes among the two or more first electrodes.

[0015] With this configuration, all of the second electrodes between the first electrodes that synthesize the signals can be removed, thus further reducing noise.

[0016] [Item 3] The imaging apparatus described in item 1, wherein the signals output by each of the multiple transistors are combined into a single analog signal, and the second electrode is not located between any two adjacent first electrodes among the multiple first electrodes.

[0017] This configuration allows for noise reduction when combining signals generated by all cells within a unit pixel.

[0018] [Item 4] The imaging apparatus according to item 3, wherein the plurality of unit pixels include a first unit pixel and a second unit pixel adjacent to the first unit pixel, and the shortest distance between the two closest first electrodes between the plurality of first electrodes of the first unit pixel and the plurality of first electrodes of the second unit pixel is longer than the shortest distance between the two closest first electrodes among the plurality of first electrodes of the first unit pixel.

[0019] With this configuration, the sensitivity of the sensor can be improved by increasing the area of ​​the first electrode.

[0020] [Item 5] The imaging apparatus described in item 1, wherein multiple first electrodes are arranged in a matrix.

[0021] This configuration allows for noise reduction when the first electrodes are arranged in a matrix (grid) pattern.

[0022] [Item 6] The imaging apparatus according to item 5 includes four first electrodes arranged in a 2x2 grid.

[0023] This configuration allows for noise reduction when combining signals from four first electrodes arranged in a 2x2 grid.

[0024] [Item 7] The imaging apparatus according to item 1, wherein a plurality of unit pixels are located on the first surface side of the photoelectric conversion layer, and the apparatus includes a plurality of color filters corresponding one-to-one to the plurality of unit pixels, and the plurality of color filters are arranged in a Bayer array with the unit pixels as one unit of color.

[0025] This configuration allows for noise reduction in color imaging.

[0026] [Item 8] The imaging apparatus according to item 1, wherein each of the multiple unit pixels includes a plurality of microlenses located on the first surface side of the photoelectric conversion layer, and each of the two or more first electrodes is located on the optical axis of a corresponding microlens among the plurality of microlenses.

[0027] With this configuration, the sensitivity of the sensor can be improved by incorporating microlenses.

[0028] [Item 9] The imaging apparatus according to item 1, wherein each of the multiple unit pixels includes one microlens located on the first surface side of the photoelectric conversion layer, and each of the two or more first electrodes overlaps with one microlens at least partially in a planar view.

[0029] With this configuration, the larger and taller the microlenses, the grazing incidence characteristics can be improved.

[0030] [Item 10] The imaging apparatus described in item 9, wherein one of the multiple first electrodes is located on the optical axis of a microlens.

[0031] With this configuration, the sensitivity of the sensor can be improved by placing the first electrode on the optical axis of the microlens.

[0032] [Item 11] The imaging apparatus according to item 8, wherein at least one of the plurality of first electrodes has a portion that does not overlap with the one microlens in a plan view.

[0033] With this configuration, the sensitivity of the sensor can be improved by placing the first electrode in a location where light reaches the second surface of the photoelectric conversion layer without passing through the microlens.

[0034] [Item 12] The imaging apparatus according to item 1, wherein the plurality of first electrodes include one or more first electrodes different from two or more first electrodes, the signals output by each of the one or more transistors corresponding to the one or more first electrodes are not combined into a single analog signal, and the second electrode is positioned between the two or more first electrodes and the one or more first electrodes.

[0035] With this configuration, for example, when a unit pixel is divided into a high-sensitivity cell and a low-sensitivity cell, charge mixing between the high-sensitivity cell and the low-sensitivity cell can be suppressed.

[0036] [Item 13] The second electrode is an imaging device described in any one of items 1 to 12, in which the potential is fixed.

[0037] This configuration allows for the suppression of charge mixing between unit pixels.

[0038] [Item 14] The imaging apparatus according to any one of items 1 to 12, wherein the second electrodes of a plurality of unit pixels are electrically connected to one another.

[0039] This configuration allows for flexible placement of the second electrode.

[0040] [Item 15] An imaging apparatus according to any one of items 1 to 12, wherein the second electrode of multiple unit pixels is a single continuous electrode.

[0041] This configuration makes the second electrode easier to manufacture.

[0042] Embodiments of this disclosure will be described below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In the following description, components having substantially the same function will be indicated by a common reference numeral and their description may be omitted.

[0043] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily be consistent across all figures.

[0044] Furthermore, in this specification, terms indicating relationships between elements, such as equality, terms indicating the shape of elements, such as square or circle, and numerical ranges are not expressions that represent only strict meanings, but also expressions that include substantially equivalent ranges, such as differences of a few percent.

[0045] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in the stacked configuration. Specifically, the light-receiving side of the imaging device is defined as "upper," and the side opposite the light-receiving side is defined as "lower." Similarly, for the "upper surface" and "lower surface" of each component, the surface facing the light-receiving side of the imaging device is defined as the "upper surface," and the surface facing the opposite side is defined as the "lower surface." Note that terms such as "upper," "lower," "upper surface," and "lower surface" are used solely to specify the relative arrangement of components and are not intended to limit the orientation of the imaging device when in use. In addition, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close contact with each other and touching. Furthermore, in this specification, "planar view" refers to a view from a direction perpendicular to the semiconductor substrate.

[0046] (First embodiment) The configuration of the imaging device according to the first embodiment of this disclosure will be described with reference to Figures 1 to 7.

[0047] Figure 1 is a diagram showing an exemplary circuit configuration of an imaging device according to the first embodiment of the present disclosure. The imaging device 1 shown in Figure 1 has a pixel array 10 including a plurality of unit pixels 101 and peripheral circuits. A unit pixel 101 is the smallest unit of the pixel array 10. In this example, the plurality of unit pixels 101 are arranged in an n x m matrix. The unit pixel 101 also includes four 2x2 cells 100 arranged in a matrix. A cell 100 is the smallest unit in which photoelectric conversion is performed within the unit pixel 101. The plurality of cells 100 are arranged in two dimensions, for example, on a semiconductor substrate, to form an imaging area. In the example shown in Figure 1, the plurality of cells 100 are arranged in a 2n x 2m matrix. The number of rows and columns of the plurality of cells 100 included in the unit pixel 101 can be any number. For example, the plurality of cells 100 may be 3 x 3.

[0048] In the illustrated example, the center of each cell 100 is located on a grid point of a square grid, and similarly, the center of each unit pixel 101 is located on a grid point of a square grid. Of course, the arrangement of the multiple cells 100 is not limited to the illustrated example; for example, the multiple cells 100 may be arranged such that each center is located on a grid point of a triangular grid, a hexagonal grid, or the like. The multiple unit pixels 101 may be arranged in one dimension. In other words, the arrangement of the multiple cells 100 can be n rows and 2 columns or 2 rows and m columns. In this case, the imaging device 1 can be used as a line sensor.

[0049] In the configuration illustrated in Figure 1, the peripheral circuitry includes a row scanning circuit 310, a column circuit group 312, a signal processing circuit 313, an output circuit 314, and a control unit 311. The peripheral circuitry may be arranged on the semiconductor substrate on which the pixel array 10 is formed, or a portion of it may be arranged on another substrate.

[0050] The row scanning circuit 310 has connections to a plurality of reset control lines RSTi and a plurality of selection control lines SELi. The reset control lines RSTi and selection control lines SELi are provided corresponding to each row of the pixel array 10. That is, of the plurality of cells 100, one or more cells 100 belonging to the i-th row are connected to the reset control line RSTi and selection control line SELi. Here, i = 0 to 2n-1, and n is an integer of 2 or more.

[0051] The row scanning circuit 310 selects multiple cells 100 row by row by applying a predetermined voltage to the selection control line SELi, reads the signal voltages from the multiple cells in the selected row, and performs a reset operation on those multiple cells, which will be described later. The row scanning circuit 310 is also called a vertical scanning circuit.

[0052] The column circuit group 312 has connections to multiple vertical signal lines SIGj provided corresponding to columns of multiple unit pixels 101 of the pixel array 10. Here, j = 0 to m-1, and m is an integer of 1 or greater. Of the multiple unit pixels 101, one or more unit pixels 101 belonging to the j-th column are connected to the vertical signal line SIGj. Multiple output signals from multiple cells 100 selected row by row scanning circuit 310 are read out to the column circuit group 312 via the multiple vertical signal lines SIGj. The column circuit group 312 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion) on the multiple output signals read out from the multiple cells 100. The column circuit group 312 includes multiple column circuits, each provided corresponding to a column or a vertical signal line SIGj. Each column circuit performs noise suppression signal processing and AD conversion on the output signal of the corresponding column.

[0053] The signal processing circuit 313 performs various processes on the image signals acquired from the multiple cells 100. In this specification, "image signal" refers to the output signal used for image formation among the signals read out via the multiple vertical signal lines SIGj. The output circuit 314 outputs the processed image signal to the outside of the imaging device 1.

[0054] The control unit 311 receives, for example, command data and a clock from outside the imaging device 1, and controls the entire imaging device 1. The control unit 311 typically has a timing generator and supplies drive signals to the row scanning circuit 310 and the column circuit group 312, etc.

[0055] Figure 2 shows an exemplary circuit configuration of a unit pixel 101 according to this embodiment. The unit pixel 101 includes four 2x2 cells 100 arranged in a matrix. Each cell 100 has a photoelectric conversion unit 130 that converts light into an electrical signal, and a detection circuit 200 that is electrically connected to the photoelectric conversion unit 130 and reads out the electrical signal generated by the photoelectric conversion unit 130.

[0056] The photoelectric conversion unit 130 generates an electrical signal using light incident on the photosensitive area. The photoelectric conversion unit 130 includes a photoelectric conversion layer 120 (photoelectric conversion film) formed from, for example, an organic material or an inorganic material such as amorphous silicon. In the following description, a stacked configuration in which the photoelectric conversion unit 130 includes the photoelectric conversion layer 120 will be used as an example. The photoelectric conversion unit 130 is provided on a semiconductor substrate 2 on which an amplifying transistor 205 is arranged. The photoelectric conversion unit 130 has a pixel electrode 102, a counter electrode 121, and a photoelectric conversion layer 120 disposed between these electrodes.

[0057] For example, two adjacent cells 100 are electrically isolated by a gap between them. The pixel electrode 102 has a connection to a charge storage node (also called a "floating diffusion node") FD. The control terminal (in this case, the gate) of an amplifying transistor 205 is connected to the charge storage node FD.

[0058] The counter electrode 121 is an electrode positioned on the light-receiving surface side of the photoelectric conversion layer 120 and is formed from a transparent conductive material such as ITO (Indium Tin Oxide). When the imaging device 1 is operating, a predetermined voltage Vp is applied to the counter electrode 121. The counter electrode 121 and the photoelectric conversion layer 120 may be formed in common for all cells 100, or they may be formed for each unit pixel 101. By applying a voltage Vp to the counter electrode 121, either one of the hole-electron pairs generated by photoelectric conversion can be collected by the pixel electrode 102. When using holes as signal charges, a voltage of approximately 10V is applied to the counter electrode 121 as the voltage Vp. By making the potential of the counter electrode 121 higher than the potential of the pixel electrode 102, holes can be accumulated in the charge storage node FD.

[0059] The voltage Vp may be a common voltage supplied to all cells 100, or a different voltage may be supplied to each unit pixel 101. By supplying a different voltage to each unit pixel 101, the sensitivity of each unit pixel 101 can be made variable.

[0060] The detection circuit 200 includes an amplification transistor 205, a selection transistor 206, and a reset transistor 202.

[0061] The gate of the amplification transistor 205 is connected to the photoelectric conversion unit 130. The amplification transistor 205 amplifies the electrical signal generated by the photoelectric conversion unit 130. One of the source and drain of the amplification transistor 205 is connected to one of the source and drain of the selection transistor 206. The other of the source and drain of the amplification transistor 205 is connected to a power line to which the power supply voltage VDD is supplied.

[0062] The selection transistor 206 selectively outputs the signal amplified by the amplification transistor 205. One of the source and drains of the selection transistor 206 is connected to one of the source and drains of the amplification transistor 205. The other of the source and drains of the selection transistor 206 is connected to the vertical signal line 208.

[0063] The vertical signal line 208 is connected to four selection transistors 206 of four cells 100 within a unit pixel 101. When these four selection transistors 206 are turned on, the signals from the four cells 100 are mixed and transmitted to a single vertical signal line 208. By reading this signal externally, the signals from the four cells 100 within the unit pixel 101 can be combined.

[0064] The reset transistor 202 resets (initializes) the charge storage node FD connected to the pixel electrode 102 of the photoelectric conversion unit 130 to the reference voltage VR. One of the source and drain of the reset transistor 202 is connected to the charge storage node FD. The reference voltage VR is supplied to the other of the source and drain of the reset transistor 202.

[0065] The following describes an example using holes as signal charges. Electrons may also be used as signal charges. Unless otherwise specified, the following examples use an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as the transistor. However, other types of transistors are also acceptable. For example, a P-channel MOSFET or a transistor other than a MOSFET may be used. Furthermore, multiple types of transistors may be used.

[0066] Figures 3A and 3B are plan views showing exemplary configurations of a unit pixel 101 according to this embodiment. Figure 3A shows the layout of a plurality of pixel electrodes 102 and auxiliary electrodes 104, and Figure 3B shows the layout of a plurality of microlenses 123.

[0067] Each unit pixel 101 includes a first surface on the light incidence side and a second surface opposite the first surface, a photoelectric conversion layer 120 that converts light into signal charge, a plurality of pixel electrodes 102 located on the second surface of the photoelectric conversion layer 120 that collect signal charge, a plurality of amplifying transistors 205 that correspond one-to-one with the plurality of pixel electrodes 102 and each outputs a signal corresponding to the amount of signal charge collected by the corresponding pixel electrode 102 among the plurality of pixel electrodes 102, and auxiliary electrodes 104 located on the second surface of the photoelectric conversion layer 120 that surround the plurality of pixel electrodes 102 in a plan view.

[0068] The four pixel electrodes 102 correspond to the four cells 100 within the unit pixel 101.

[0069] Although not shown in Figures 3A and 3B, the signals output by each of the four transistors corresponding to the four pixel electrodes 102 are all combined into a single analog signal. In this configuration, auxiliary electrodes 104 are formed around the unit pixel 101. Also, no auxiliary electrodes 104 are formed between the four pixel electrodes 102. The four pixel electrodes 102 are arranged in a matrix. Specifically, the unit pixel 101 contains four pixel electrodes 102 arranged in a 2x2 grid.

[0070] The auxiliary electrode 104 is arranged around the four pixel electrodes 102 within the unit pixel 101. Within the pixel electrodes 102, a pixel contact 105 is provided for electrical connection between the pixel electrode 102 and the charge storage node FD. The auxiliary electrode 104 is connected to the underlying wiring via an auxiliary contact 106. The pixel electrodes 102 are electrodes for collecting charge generated in the photoelectric conversion layer 120. The plurality of pixel electrodes 102 are all the pixel electrodes 102 contained within the unit pixel 101. The plurality of pixel electrodes 102 and the auxiliary electrode 104 are made of a metallic material, such as titanium nitride (TiN). The plurality of pixel electrodes 102 and the auxiliary electrode 104 may also be made of copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), or compounds thereof. Furthermore, the plurality of pixel electrodes 102 and the auxiliary electrode 104 have a uniform film thickness and a flattened upper surface. Furthermore, if there is a location among the four pixel electrodes 102 where an auxiliary electrode 104 is not provided, an auxiliary electrode 104 may be provided between the other pixel electrodes 102. Even in this configuration, by omitting one auxiliary electrode 104, the coupling capacitance between the pixel electrode 102 and the auxiliary electrode 104 is reduced, resulting in a noise reduction effect.

[0071] The microlenses 123 are each positioned on one of the four pixel electrodes 102 within a unit pixel 101. In other words, each of the multiple unit pixels 101 contains multiple microlenses 123 located on the upper surface (first surface) side of the photoelectric conversion layer 120. Furthermore, each of the multiple pixel electrodes 102 is positioned on the optical axis of the corresponding microlens 123. Note that the microlenses 123 are not required to be installed.

[0072] Figure 4 is a cross-sectional view of a unit pixel 101, showing the cross-sectional structure along line AA shown in Figure 3A. Note that Figures 3A to 4 primarily illustrate the components necessary for explanation, for clarity, and do not depict all wiring and circuit elements included in the unit pixel 101. Furthermore, the positions and numbers of contacts such as the multiple pixel contacts 105 and the multiple auxiliary contacts 106 are examples only and are not limited to those shown in each figure. For example, if the auxiliary electrodes 104 are electrically connected to each other, the auxiliary contacts 106 may be located outside the pixel array 10. The same applies to the other cross-sectional and plan views described below.

[0073] As shown in Figure 4, the imaging device 1 comprises a semiconductor substrate 2, a plurality of pixel electrodes 102 located on an insulating layer 3, an auxiliary electrode 104 located on the insulating layer 3, a counter electrode 121 located above the plurality of pixel electrodes 102 and the auxiliary electrode 104, a photoelectric conversion layer 120 sandwiched between the plurality of pixel electrodes 102 and the auxiliary electrode 104 and the counter electrode 121, and a detection circuit 200 located on the semiconductor substrate 2 for detecting the potential of the pixel electrodes 102. The imaging device 1 also comprises a buffer layer 4, a sealing layer 5, a color filter 122, a planarization layer 6, and a microlens 123.

[0074] A detection circuit 200 is formed so as to straddle the interface between the semiconductor substrate 2 and the insulating layer 3. Multiple pixel electrodes 102 and auxiliary electrodes 104 are formed on the upper side (positive side in the Z-axis direction), i.e., the upper surface, of the insulating layer 3. The constituent layers of the insulating layer 3 are interposed in the gaps between adjacent pixel electrodes 102 and auxiliary electrodes 104.

[0075] The insulating layer 3 is formed on the semiconductor substrate 2 and includes a plurality of constituent layers 3a, 3b, 3c, 3d, and 3e (hereinafter referred to as 3a to 3e), a plurality of pixel contacts 105, a plurality of auxiliary contacts 106, a plurality of auxiliary wirings 107, a plurality of upper FD wirings 110, a plurality of lower FD wirings 111, and a plurality of pixel contacts 112.

[0076] Multiple constituent layers 3a, 3b, 3c, 3d, and 3e are stacked in this order from the semiconductor substrate 2 side. Hereinafter, multiple constituent layers 3a, 3b, 3c, 3d, and 3e may be referred to as multiple constituent layers 3a to 3e. Multiple constituent layers 3a to 3e are made of, for example, silicon dioxide (SiO2). Multiple wiring layers such as wiring and contact plugs are arranged in each constituent layer 3a to 3e. Note that the number of constituent layers within the insulating layer 3 can be set arbitrarily and is not limited to the example of five constituent layers 3a to 3e shown in Figure 4.

[0077] The pixel electrode 102 is an example of a first electrode and is located on the second surface (bottom surface) of the photoelectric conversion layer 120 (bottom in Figure 4) to collect signal charge. The pixel electrode 102 is electrically connected to the detection circuit 200 via the pixel contact 105, upper FD wiring 110, pixel contact 112, and lower FD wiring 111.

[0078] The auxiliary electrode 104 is an example of a second electrode, located on the second surface (bottom surface) of the photoelectric conversion layer 120 (below in Figure 4), and surrounds multiple pixel electrodes 102 in a plan view. In other words, the auxiliary electrode 104 surrounds multiple pixel electrodes 102 contained in a unit pixel 101 in a plan view. To put it another way, the auxiliary electrode 104 surrounds the region (unit pixel 101) where multiple pixel electrodes 102 are arranged in a plan view. The auxiliary electrode 104 is connected to the auxiliary wiring 107 via an auxiliary contact 106. The auxiliary electrode 104 is not formed between multiple pixel electrodes 102 within a unit pixel 101. In other words, the auxiliary electrode 104 does not exist between two adjacent pixel electrodes 102 among the multiple pixel electrodes 102. Furthermore, the auxiliary electrode 104 does not exist between any two adjacent pixel electrodes 102 among the multiple pixel electrodes 102.

[0079] The counter electrode 121 is an electrode that faces the multiple pixel electrodes 102 and auxiliary electrodes 104. The counter electrode 121 may be translucent in order to allow light to enter the photoelectric conversion layer 120. The material of the counter electrode 121 is, for example, a transparent oxide conductive material such as ITO or IZO (Indium Zinc Oxide).

[0080] The photoelectric conversion layer 120 includes a first surface (upper surface) on the light incident side and a second surface (lower surface) opposite the first surface, and converts light into signal charge. The photoelectric conversion layer 120 is a layer composed of a photoelectric conversion material that generates charge according to the intensity of the received light, and is sandwiched between the pixel electrode 102 and auxiliary electrode 104 and the counter electrode 121. The photoelectric conversion material is, for example, an organic semiconductor material, and includes at least one of a p-type organic semiconductor and an n-type organic semiconductor. It is desirable that the photoelectric conversion layer 120 has a uniform film thickness in the pixel array 10.

[0081] The pixel contact 105, upper FD wiring 110, pixel contact 112, lower FD wiring 111, auxiliary contact 106, and auxiliary wiring 107 are formed by embedding conductive materials such as copper (Cu) and tungsten (W) in the insulating layer 3, and have a lower electrical resistivity than the pixel electrode 102 and auxiliary electrode 104.

[0082] A photoelectric conversion layer 120 is stacked on the upper surface of a constituent layer 3e on which multiple pixel electrodes 102 and auxiliary electrodes 104 are arranged. A counter electrode 121, a buffer layer 4, and a sealing layer 5 are stacked in order on the upper surface of the photoelectric conversion layer 120. A color filter 122 corresponding to the transmission wavelength range of each unit pixel 101 is formed on the upper surface of the sealing layer 5. In other words, a microlens 123 corresponding to each pixel electrode 102 is further formed on the upper surface of the color filter 122 via a planarization layer 6. Note that if the imaging device 1 is a monochrome sensor, the color filter 122 is not formed.

[0083] The semiconductor substrate 2 is made of, for example, silicon (Si). However, the semiconductor substrate 2 is not limited to a substrate that is entirely semiconductor. The semiconductor substrate may be an insulating substrate with a semiconductor layer on the surface where the photosensitive area is formed.

[0084] The detection circuit 200 is provided in correspondence to each of the multiple pixel electrodes 102, detects the signal charge collected by the corresponding pixel electrode 102, and outputs a signal voltage corresponding to the signal charge. The detection circuit 200 is composed of, for example, a MOS circuit or a TFT (Thin Film Transistor) circuit. The detection circuit 200 includes, for example, an amplifying transistor 205 whose gate is connected to the pixel electrode 102, and the amplifying transistor 205 outputs a signal voltage corresponding to the amount of signal charge. In other words, the detection circuit 200 includes multiple transistors (for example, multiple amplifying transistors 205) that correspond one-to-one with the multiple pixel electrodes 102, each outputting a signal corresponding to the amount of signal charge collected by the corresponding pixel electrode 102 among the multiple pixel electrodes 102. Furthermore, the signals output by each of the multiple transistors (amplifying transistors 205) corresponding to the multiple pixel electrodes 102 are combined into a single analog signal.

[0085] Figures 5A and 5B are plan views of a plurality of unit pixels 101 arranged in an array according to this embodiment. Figure 5A shows the layout of a plurality of pixel electrodes 102 and auxiliary electrodes 104, and Figure 5B shows the layout of a plurality of microlenses 123. Figures 5A and 5B show the layout of four 2x2 unit pixels 101. As shown in Figure 5A, the auxiliary electrode 104 between two adjacent unit pixels 101 is shared for those two unit pixels 101.

[0086] Furthermore, as shown in Figure 5A, the shortest distance between two or more pixel electrodes 102 contained in a single unit pixel 101 is represented by d1. The shortest distance between the nearest pixel electrode 102 and 101J contained in adjacent but different unit pixels 101 and 101J is represented by d2. d1 and d2 may be equal. Note that d1 and d2 may be different.

[0087] Furthermore, the potential of the auxiliary electrode 104 may be fixed. For example, the auxiliary electrode 104 may be fixed to the ground potential (GND). Also, the auxiliary electrodes 104 of multiple unit pixels 101 may be electrically connected to each other. For example, the auxiliary electrodes 104 of multiple unit pixels 101 may be a single continuous electrode. Note that the auxiliary electrodes 104 of multiple unit pixels 101 may include multiple auxiliary electrodes 104 that are electrically connected via other wiring layers or the like.

[0088] Figure 6 is a plan view showing an example of the arrangement of multiple color filters 122 in this embodiment. Each of the multiple unit pixels 101 includes a color filter 122 located on the first surface (top surface) side of the photoelectric conversion layer 120. As shown in Figure 6, the color filters 122 corresponding to the four cells 100 within the unit pixel 101 are the same color, and the signals of the four cells 100 are combined. Furthermore, the multiple color filters 122 of the multiple unit pixels 101 are arranged in a Bayer array. That is, the color filters 122 are arranged in a Bayer pattern with the unit pixel 101 (four cells 100) as one unit of color. Note that the arrangement of the color filters 122 does not have to be a Bayer array. For example, it may be an RGB-IR array.

[0089] Figure 7 is a plan view of the four unit pixels 101 when the imaging device 1 performs monochrome imaging. As shown in Figure 7, no color filter is placed when the imaging device 1 performs monochrome imaging. In this case as well, the signals of the four cells 100 are mixed and output within the unit pixel 101.

[0090] Thus, in this embodiment, since the four cells 100 within a unit pixel 101 are mixed with the same color, auxiliary electrodes 104 are not placed between the four pixel electrodes 102 to suppress color mixing between the pixel electrodes 102, as shown in Figure 3A. This reduces the coupling capacitance between the pixel electrodes 102 and the auxiliary electrodes 104. This reduction in coupling capacitance leads to a reduction in FD capacitance. As a result, the signal-to-noise ratio increases, and the noise becomes relatively smaller compared to the output voltage signal. On the other hand, by providing auxiliary electrodes 104 around the unit pixel 101, charge mixing between the unit pixels 101 can be reduced. In other words, in the configuration of this embodiment, charge mixing between the unit pixels 101 can be reduced while reducing the coupling capacitance between the pixel electrodes 102 and the auxiliary electrodes 104. This reduces noise.

[0091] In the above description, the unit pixel 101 contains four 2x2 cells 100 arranged in a matrix, but it may also contain four or more cells 100, such as 3x3 or 4x4. Furthermore, the number of rows and columns of the multiple cells 100 contained in the unit pixel 101 do not have to be equal; for example, six 2x3 cells 100 may be contained in the unit pixel 101. In addition, the multiple pixel electrodes 102 within the unit pixel 101 may be arranged in a line. Furthermore, the multiple pixel electrodes 102 within the unit pixel 101 do not have to be arranged in a matrix.

[0092] (Modified version of the first embodiment) Modifications of the first embodiment will be described using Figures 8, 9, 10A, and 10B. Figure 8 is a circuit diagram showing an exemplary configuration of an imaging device 1A according to a modification of the first embodiment. The imaging device 1A shown in Figure 8 differs from the imaging device 1 shown in Figure 1 in that a vertical signal line SIGj is provided for each row of cells 100. Specifically, in the imaging device 1 shown in Figure 1, a vertical signal line SIGj is provided for each row of unit pixels 101 (i.e., every two rows of cells 100), and m vertical signal lines SIGj are provided, but in the imaging device 1A shown in Figure 8, 2 × m vertical signal lines SIGj are provided. Each vertical signal line SIGj is connected to multiple cells 100 belonging to the j-th column.

[0093] Figure 9 is a schematic circuit diagram showing an exemplary circuit configuration of a unit pixel 101A according to this embodiment. The unit pixel 101A includes four cells 100a, 100b, 100c, and 100d. The configuration of cells 100a, 100b, 100c, and 100d is the same as that of cell 100 shown in Figure 2. When cells 100a, 100b, 100c, and 100d are not distinguished, they are also referred to as cell 100. Cells 100a and 100b are connected to vertical signal line 208a, and cells 100c and 100d are connected to vertical signal line 208b. In other words, the two vertical signal lines 208a and 208b are each connected to a plurality of cells 100 belonging to the column corresponding to the vertical signal line within the unit pixel 101A. In this configuration, vertical signal lines 208a and 208b may be electrically connected to each other.

[0094] Figures 10A and 10B show the specific circuit configuration for electrically connecting vertical signal lines 208a and 208b. Vertical signal line 208a is connected to column circuit 312a via switch SW1. Vertical signal line 208b is connected to column circuit 312b via switch SW2 and to column circuit 312a via switch SW3. Note that column circuits 312a and 312b are column-unit circuits included in the column circuit group 312 shown in Figure 8.

[0095] As shown in Figure 10A, by turning on switches SW1 and SW3 and turning off switch SW2, the vertical signal lines 208a and 208b are electrically connected. Therefore, the signals output by the four cells 100a, 100b, 100c, and 100d that constitute the unit pixel 101A can be combined. This combined signal is input to the column circuit 312a and undergoes AD conversion.

[0096] Furthermore, as shown in Figure 10B, by turning on switches SW1 and SW2 and turning off switch SW3, the signals from cells 100a and 100b are individually converted using AD conversion by column circuit 312a. Similarly, the signals from cells 100c and 100d are individually converted using AD conversion by column circuit 312b.

[0097] Thus, switches SW1 to SW3 allow switching between a mode in which the output signals of the four cells 100a, 100b, 100c, and 100d shown in Figure 10A are combined and read out, and a mode in which the output signals of the four cells 100a, 100b, 100c, and 100d shown in Figure 10B are read out as individual pixel data. Alternatively, the imaging device 1A may not have switches SW1 to SW3 and may always combine the output signals of the four cells 100a, 100b, 100c, and 100d.

[0098] (Second embodiment) A second embodiment will be described using Figures 11 and 12. The second embodiment describes a modification of the first embodiment. In the first embodiment, four microlenses 123 were provided for four cells 100 contained in a unit pixel 101, but in the second embodiment, one microlens 123B is provided for four cells 100 contained in a unit pixel 101B. In other words, one microlens 123B is provided for one unit pixel 101B. For example, if a unit pixel 101B contains a 3x3 cell 100, one microlens 123B is provided for these nine cells 100.

[0099] Figure 11 is a plan view showing an exemplary configuration of a unit pixel 101B according to the second embodiment. Figure 11 shows the layout of the microlens 123B. The layout of the multiple pixel electrodes 102 and auxiliary electrodes 104 is the same as in Figure 3A. Figure 12 is a schematic cross-sectional view along the line BB in Figure 11.

[0100] One microlens 123B is arranged for every four cells 100 within a unit pixel 101B. In other words, each of the multiple unit pixels 101B contains one microlens 123B located on the first surface (top surface) of the photoelectric conversion layer 120. Each of the multiple pixel electrodes 102 overlaps with one microlens 123B in at least part of its form in a plan view.

[0101] As shown in Figure 12, the height of the microlens 123B is greater than the height of the microlens 123 shown in Figure 4. As a result, the structure shown in Figure 12 has improved oblique incidence characteristics compared to the structure shown in Figure 4. In addition, as shown in Figure 11, the oblique incidence characteristics are improved by increasing the diameter of the microlens 123B in a planar view.

[0102] Although sharing one microlens 123B among four cells 100 may increase color mixing across the four cells 100, this is not a problem because the signals from these four cells 100 are combined.

[0103] (Third embodiment) A third embodiment will be described with reference to Figures 13A and 13B. Figures 13A and 13B are plan views showing an exemplary configuration of a unit pixel 101C according to the third embodiment. Figure 13A shows the layout of a plurality of pixel electrodes 102C and auxiliary electrodes 104, and Figure 13B shows the layout of a plurality of microlenses 123.

[0104] The unit pixel 101C shown in Figures 13A and 13B differs from the unit pixel 101 shown in Figures 3A and 3B in that the area of ​​the pixel electrode 102C is larger than the area of ​​the pixel electrode 102. Specifically, the pixel electrode 102C extends further towards the center of the unit pixel 101C than the pixel electrode 102. In Figure 13A, the shape of the pixel electrode 102 shown in Figure 3A is indicated by a dotted line. Also, Figure 13A shows the layout of two adjacent unit pixels 101C and 101K.

[0105] In other words, pixel electrode 102C is larger than pixel electrode 102. As shown in Figure 13A, the shortest distance between pixel electrodes 102C included in one unit pixel 101C is represented by d3. The shortest distance between pixel electrode 102 included in one unit pixel 101C and pixel electrode 102K included in a different adjacent unit pixel 101K is represented by d4. d3 is smaller than d4. That is, the shortest distance d4 between the two closest pixel electrodes 102C and 102K between multiple pixel electrodes 102C of the first unit pixel 101C and multiple pixel electrodes 102K of the second unit pixel 101K is longer than the shortest distance d3 between the two closest pixel electrodes 102C among the multiple pixel electrodes 102C included in the first unit pixel 101C. With this configuration, the area of ​​pixel electrodes 102C and 102K can be increased while reducing the parasitic capacitance of the pixel electrodes 102C and 101K and the auxiliary electrode 104, thereby improving sensitivity.

[0106] In this example, the dimensions in the Y direction and the X direction are equal, but the dimensions in the Y direction and the X direction may be different. This also applies to other embodiments.

[0107] Furthermore, the layout of the microlens 123 shown in Figure 13B may also be a layout in which one microlens 123B is provided for every four cells 100 contained in the unit pixel 101C, as shown in Figure 11.

[0108] (Fourth embodiment) A fourth embodiment will be described with reference to Figures 14A and 14B. Figures 14A and 14B are plan views showing an exemplary configuration of a unit pixel 101D according to the fourth embodiment. Figure 14A shows the layout of a plurality of pixel electrodes 102D and auxiliary electrodes 104, and Figure 14B shows the layout of a microlens 123B.

[0109] The unit pixel 101D shown in Figures 14A and 14B differs from the unit pixel 101 shown in Figures 3A and 3B in that the area of ​​the pixel electrode 102D is larger than the area of ​​the pixel electrode 102. Specifically, in the first embodiment, the pixel electrode 102D extends further towards the center of the unit pixel 101D than the pixel electrode 102 shown in Figures 3A and 3B. In other words, the distance d5 between the pixel electrodes 102D shown in Figure 14A is shorter than the distance d1 between the pixel electrodes 102 shown in Figure 5A. Here, d5 may be equal to, for example, d6, which is the distance (shortest distance) between the pixel electrode 102D and the auxiliary electrode 104. Note that d5 may be different from d6; for example, d5 may be smaller than d6. With such a configuration, the area of ​​the pixel electrode 102D can be increased while reducing the parasitic capacitance of the pixel electrode 102D and the auxiliary electrode 104, thereby improving sensitivity.

[0110] The layout of the microlens 123B shown in Figure 14B may also be a layout in which a microlens 123 is provided on each of the four pixel electrodes 102D within the unit pixel 101D, as shown in Figure 3B.

[0111] (Fifth embodiment) A fifth embodiment will be described using Figures 15A, 15B, 16A, and 16B. The fifth embodiment describes a modification of the second embodiment. Figures 15A and 15B are plan views showing an exemplary configuration of a unit pixel 101E according to the fifth embodiment. Figure 15A shows the layout of a plurality of pixel electrodes 102E and auxiliary electrodes 104, and Figure 15B shows the layout of a microlens 123B.

[0112] The unit pixel 101E shown in Figures 15A and 15B differs from the unit pixel 101B shown in Figure 11 in the arrangement of the pixel electrodes 102E. Specifically, one of the four pixel electrodes 102E is positioned at the center of the unit pixel 101E. The remaining three pixel electrodes 102E are positioned around it. In other words, the four pixel electrodes 102E are arranged asymmetrically.

[0113] Light is focused along the optical axis of the microlens 123B. One of the multiple pixel electrodes 102E is located along the optical axis of the microlens 123B. By positioning the pixel electrode 102E in a location where light is easily focused in the central part of the microlens 123B in this way, sensitivity can be improved.

[0114] Furthermore, as shown in Figure 15A, the remaining three pixel electrodes 102E are positioned in three directions from above, below, left, and right of the central pixel electrode 102E.

[0115] Figures 16A and 16B are plan views showing exemplary configurations of a unit pixel 101F according to a modified example of the fifth embodiment. Figure 16A shows the layout of a plurality of pixel electrodes 102F and auxiliary electrodes 104, and Figure 16B shows the layout of a microlens 123B.

[0116] The unit pixel 101F shown in Figures 16A and 16B differs from the unit pixel 101E shown in Figures 15A and 15B in that the area of ​​the central pixel electrode 102F is larger than the area of ​​the central pixel electrode 102E. Specifically, the central pixel electrode 102F extends further than the central pixel electrode 102E towards the side where other pixel electrodes 102F are not located. In this way, increasing the area of ​​the central pixel electrode 102F can improve sensitivity.

[0117] (Sixth embodiment) A sixth embodiment will be described with reference to Figures 17A and 17B. The sixth embodiment describes a modification of the fifth embodiment. Figures 17A and 17B are plan views showing an exemplary configuration of a unit pixel 101G according to the sixth embodiment. Figure 17A shows the layout of a plurality of pixel electrodes 102G and auxiliary electrodes 104, and Figure 17B shows the layout of a microlens 123B.

[0118] In the unit pixel 101G shown in Figures 17A and 17B, the arrangement of the peripheral pixel electrodes 102G, excluding the center, differs from that of the unit pixel 101E shown in Figures 15A and 15B. Specifically, the three pixel electrodes 102G are positioned in three directions from the upper right, lower right, upper left, and lower left directions relative to the central pixel electrode 102G. Furthermore, in the example shown in Figures 15A and 15B, all pixel electrodes 102E are arranged to overlap (i.e., be encompassed) the microlens 123B in a plan view, whereas in the example shown in Figures 17A and 17B, at least one of the multiple pixel electrodes 102G has a portion that does not overlap with the microlens 123B in a plan view. In other words, the three pixel electrodes 102G are positioned at the corners of the unit pixel 101G. Here, the light intensity is stronger not only along the optical axis of the microlens 123B but also at the corners. In a planar view, the corner portions of unit pixels 101G that do not overlap with the microlens 123B receive more incident light than the peripheral portions of the microlens 123B in a planar view, because the light is not focused by the microlens 123B. Therefore, sensitivity can be improved by placing pixel electrodes 102G at the central and corner portions of the microlens 123B.

[0119] Figures 18A and 18B are plan views showing exemplary configurations of a unit pixel 101H according to a modification of the sixth embodiment. Figure 18A shows the layout of a plurality of pixel electrodes 102H and auxiliary electrodes 104, and Figure 18B shows the layout of a microlens 123B.

[0120] The unit pixel 101H shown in Figures 18A and 18B differs from the unit pixel 101G shown in Figures 17A and 17B in that the area of ​​the central pixel electrode 102H is larger than the area of ​​the central pixel electrode 102G. Specifically, the central pixel electrode 102H extends further than the central pixel electrode 102G towards the side where other pixel electrodes 102H are not located. In this way, increasing the area of ​​the central pixel electrode 102H can improve sensitivity.

[0121] (Seventh Embodiment) The imaging device according to this embodiment will be described with reference to Figures 19 to 23. The seventh embodiment will describe a modification of the first embodiment. In the first embodiment, an example was described in which the signals of four cells 100 contained in a unit pixel 101 are combined. In this embodiment, a case will be described in which the signals of some of the multiple cells 100 contained in a unit pixel 101I are combined. The overall configuration of the imaging device is the same as in Figure 8, and a vertical signal line SIGj is provided for each row of cells 100.

[0122] Figure 19 is a circuit diagram showing an exemplary configuration of a unit pixel 101I according to the seventh embodiment. The unit pixel 101I includes four cells 100a, 100b, 100c, and 100d. The configuration of cells 100a, 100b, 100c, and 100d is the same as that of cell 100 shown in Figure 2. When cells 100a, 100b, 100c, and 100d are not distinguished, they are also referred to as cell 100. Cells 100a, 100b, and 100c are connected to the vertical signal line 208c, and cell 100d is connected to the vertical signal line 208d. In other words, three of the four cells 100 are connected to the vertical signal line 208c, and the vertical signal line 208d is connected to the remaining cell 100.

[0123] Figure 20 is a schematic circuit diagram showing the connection between the unit pixel 101I and the column circuits 312c and 312d according to this embodiment. Note that column circuits 312c and 312d are column-unit circuits included in the column circuit group 312 shown in Figure 8. Signals from the three cells 100a, 100b, and 100c included in the unit pixel 101I are output to the vertical signal line 208c and combined. This combined signal is AD converted by the column circuit 312a. The AD converted signal is used as image data for high sensitivity. On the other hand, the signal from the other cell 100d included in the unit pixel 101I is output to the vertical signal line 208d and AD converted by the column circuit 312d. Note that a configuration in which the connection between the vertical signal line 208c and the vertical signal line 208d is switched by switches SW1 to SW2 may be used, similar to the configuration shown in Figures 10A and 10B.

[0124] Figure 21 is a plan view showing an exemplary configuration of a unit pixel 101I according to the seventh embodiment. Figure 21 shows the layout of a plurality of pixel electrodes 102 and auxiliary electrodes 104I. Note that the layout of the microlens 123 is the same as in Figure 3B. Figure 22 is a cross-sectional view of the unit pixel 101I, showing the cross-sectional structure along the CC line in Figure 21.

[0125] The auxiliary electrode 104I is provided around the four pixel electrodes 102. The auxiliary electrode 104I is further positioned between three pixel electrodes 102 and one pixel electrode 102. This suppresses optical and electrical color mixing between the three cells 100a, 100b, and 100c and the one cell 100d. Furthermore, the auxiliary electrode 104I is not provided between the three pixel electrodes 102 corresponding to the three cells 100a, 100b, and 100c. This reduces the coupling capacitance between the pixel electrodes 102 and the auxiliary electrode 104I.

[0126] By turning on the selection transistors 206 for the four cells 100a, 100b, 100c, and 100d of the unit pixel 101I, the signals from three cells 100a, 100b, and 100c are mixed on one vertical signal line 208c. Additionally, the signal from one cell 100d is output to another vertical signal line 208d. By reading these signals externally, a high-sensitivity signal, which is a mixture of the signals from the three cells 100a, 100b, and 100c within the unit pixel 101I, and a low-sensitivity signal, which is the signal from a single cell 100d, are obtained. By combining these high-sensitivity and low-sensitivity signals, a signal with a wider dynamic range can be generated.

[0127] Thus, each of the multiple unit pixels 101I includes two or more pixel electrodes 102 from the multiple pixel electrodes 102 (for example, the three pixel electrodes 102 in the upper left, lower left, and upper right shown in Figure 21) and one or more pixel electrodes 102 that are different from the two or more pixel electrodes 102 (for example, the single pixel electrode 102 in the lower right shown in Figure 21). The signals output by each of the two or more transistors (amplifying transistors 205) corresponding to the two or more pixel electrodes 102 are combined into a single analog signal. However, the analog signal obtained from the signals output by each of the one or more transistors corresponding to the one or more pixel electrodes 102 is not combined into a single analog signal. The auxiliary electrode 104I does not exist between two adjacent pixel electrodes 102 from the two or more pixel electrodes 102. The auxiliary electrode 104I does not have to exist between any two of the two or more pixel electrodes 102. Furthermore, the auxiliary electrode 104I is placed between two or more pixel electrodes 102 and one or more pixel electrodes 102. If there is a place between two or more pixel electrodes 102 where an auxiliary electrode 104I is not provided, an auxiliary electrode 104 may be provided between the other two or more pixel electrodes 102.

[0128] (Eighth embodiment) In this embodiment, a camera system 400 comprising an imaging device 1 according to the first embodiment will be described. Figure 23 is a block diagram showing an example configuration of the camera system 400 according to this embodiment. The camera system 400 includes an imaging device 1, an optical system 401, a camera signal processing unit 402, and a system controller 403.

[0129] The optical system 401 is a lens or the like for focusing light onto the imaging area of ​​the imaging device 1. The imaging device 1 is, for example, the imaging device 1 according to the first embodiment.

[0130] The camera signal processing unit 402 functions as a signal processing circuit that processes the output signal from the imaging device 1. The camera signal processing unit 402 performs processes such as gamma correction, color interpolation, spatial interpolation, auto white balance, distance measurement calculation, and wavelength information separation. The camera signal processing unit 402 is implemented, for example, by a DSP (Digital Signal Processor).

[0131] The system controller 403 controls the entire camera system 400. The system controller 403 may be implemented, for example, by a processor or microcomputer with a built-in program.

[0132] The camera system 400, by using the imaging device 1 according to the embodiment of this disclosure, can reduce noise in each unit pixel while suppressing color mixing between adjacent cells.

[0133] The camera system 400 may include any of the imaging devices according to other embodiments instead of the imaging device 1 according to the first embodiment.

[0134] (Other embodiments) Although imaging devices and camera systems according to one or more embodiments have been described above based on each embodiment and each modification, this disclosure is not limited to these embodiments and modifications. Within the scope of this disclosure, various modifications conceivable by those skilled in the art, as well as configurations constructed by combining components from different embodiments and modifications, are also included, as long as they do not deviate from the spirit of this disclosure.

[0135] Furthermore, each of the above embodiments and modifications can be modified, replaced, added, or omitted within the scope of the claims or their equivalents. [Industrial applicability]

[0136] The imaging device relating to this disclosure can be used, for example, as an image sensor in cameras such as digital cameras and in-vehicle cameras. [Explanation of Symbols]

[0137] 1.1A Imaging device 2 Semiconductor substrates 3. Insulating layer 3a, 3b, 3c, 3d, 3e composition layers 4 Buffer layer 5. Sealing layer 6 Planarization layer 10-pixel array 100, 100a, 100b, 100c, 100d cells 101, 101A, 101B, 101C, 101D, 101E, 101F, 101G, 101H, 101I, 101J, 101K Unit pixels 102, 102C, 102D, 102E, 102F, 102G, 102H, 102J, 102K pixel electrodes 104, 104I auxiliary electrode 105 pixel contact 106 Auxiliary Contact 107 Auxiliary wiring 110 Upper FD wiring 111 Lower layer FD wiring 112-pixel contact 120 Photoelectric conversion layer 121 Counter electrode 122 Color Filters 123, 123B Microlenses 130 Photoelectric conversion unit 200 detection circuit 202 Reset Transistor 205 Amplifying Transistors 206 Selective Transistors 208, 208a, 208b, 208c, 208d Vertical signal line 310-line scanning circuit 311 Control Unit 312 column circuit group 312a, 312b, 312c, 312d column circuit 313 Signal Processing Circuit 314 Output Circuit 400 Camera System 401 Optical system 402 Camera signal processing unit 403 System Controller RSTi reset control line SELi Selective Control Line SIGj Vertical Signal Line VR Reference Voltage

Claims

1. Equipped with multiple unit pixels, Each of the aforementioned plurality of unit pixels is A photoelectric conversion layer comprising a first surface on the light incidence side and a second surface opposite the first surface, which converts light into a signal charge, A plurality of first electrodes are located on the second surface of the photoelectric conversion layer and collect the signal charge, A plurality of transistors, each corresponding one-to-one to the plurality of first electrodes, each outputting a signal corresponding to the amount of signal charge collected by the corresponding first electrode among the plurality of first electrodes, The photoelectric conversion layer includes a second electrode located on the second surface and surrounding the plurality of first electrodes in a plan view, The signals output by each of the two or more transistors corresponding to two or more of the multiple first electrodes are combined into a single analog signal. The second electrode is not located between two adjacent first electrodes among the two or more first electrodes. Imaging device.

2. The imaging apparatus according to claim 1, wherein the second electrode is not located between any two adjacent first electrodes among the two or more first electrodes.

3. The signals output by each of the aforementioned transistors are combined into a single analog signal. The imaging apparatus according to claim 1, wherein the second electrode is not located between any two adjacent first electrodes among the plurality of first electrodes.

4. The plurality of unit pixels include a first unit pixel and a second unit pixel adjacent to the first unit pixel. The imaging apparatus according to claim 3, wherein the shortest distance between the two closest first electrodes between the plurality of first electrodes of the first unit pixel and the plurality of first electrodes of the second unit pixel is longer than the shortest distance between the two closest first electrodes among the plurality of first electrodes of the first unit pixel.

5. The imaging apparatus according to claim 1, wherein the plurality of first electrodes are arranged in a matrix.

6. The imaging apparatus according to claim 5, wherein the plurality of first electrodes include four first electrodes arranged in a 2x2 grid.

7. The plurality of unit pixels are located on the first surface side of the photoelectric conversion layer and include a plurality of color filters that correspond one-to-one with the plurality of unit pixels. The imaging apparatus according to claim 1, wherein the plurality of color filters are arranged in a Bayer array with the unit pixel as a single color unit.

8. Each of the plurality of unit pixels includes a plurality of microlenses located on the first surface side of the photoelectric conversion layer, The imaging apparatus according to claim 1, wherein each of the two or more first electrodes is located on the optical axis of a corresponding microlens among the plurality of microlenses.

9. Each of the plurality of unit pixels includes a microlens located on the first surface side of the photoelectric conversion layer, The imaging apparatus according to claim 1, wherein each of the two or more first electrodes overlaps with one of the microlenses in at least part of a plan view.

10. The imaging apparatus according to claim 9, wherein one of the plurality of first electrodes is located on the optical axis of the one microlens.

11. The imaging apparatus according to claim 9, wherein at least one of the plurality of first electrodes has a portion that does not overlap with the one microlens in a plan view.

12. The plurality of first electrodes include one or more first electrodes that are different from the two or more first electrodes. The signals output by each of the one or more transistors corresponding to the one or more first electrodes are not combined into the single analog signal. The imaging apparatus according to claim 1, wherein the second electrode is disposed between the two or more first electrodes and the one or more first electrodes.

13. The imaging apparatus according to any one of claims 1 to 12, wherein the potential of the second electrode is fixed.

14. The imaging apparatus according to any one of claims 1 to 12, wherein the second electrodes of the plurality of unit pixels are electrically connected to one another.

15. The imaging apparatus according to any one of claims 1 to 12, wherein the second electrode of the plurality of unit pixels is a single continuous electrode.

Images