A readout circuit for a terahertz detector array

Abstract

The present application relates to the technical field of electronic circuit, and especially relates to a readout circuit of a terahertz detection array, which comprises: a readout link at least comprising a current feedback instrumentation amplifier, a programmable gain amplifier and an incremental analog-to-digital converter connected in sequence; the current feedback instrumentation amplifier amplifies the signal output by the detector and outputs a first-stage amplified signal, the current feedback instrumentation amplifier comprises an instrumentation amplifier body and a first ripple suppression module, the first ripple suppression module comprises a first redundant segmented current steering DAC and a first DAC code register; the programmable gain amplifier further amplifies the first-stage amplified signal, the programmable gain amplifier comprises a gain amplifier body and a second ripple suppression module, and the second ripple suppression module comprises a second redundant segmented current steering DAC and a second DAC code register. The present application effectively reduces the chip area and power consumption while ensuring that the readout circuit of the terahertz detection array has high gain, low noise and low offset.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and in particular relates to a readout circuit for a terahertz detection array. Background Technology

[0002] In the readout circuit of a large-scale terahertz detector, the design of the readout link is crucial. Its main task is to amplify, filter, and perform analog-to-digital conversion on the weak terahertz detection signal. Therefore, the accuracy and speed of the terahertz readout link directly determine the spatial resolution and imaging frame rate of the system. Since the output signal amplitude of the terahertz detector is extremely small, it is usually necessary to first use an instrumentation amplifier to amplify it with low noise, and then use a programmable gain amplifier to further amplify the signal. At the same time, the programmable gain amplifier also needs to drive the subsequent analog-to-digital converter. In the final stage of the terahertz readout link, an analog-to-digital converter is usually configured to realize the conversion of analog signals to digital signals.

[0003] To reduce system noise levels, chopping techniques are typically introduced in the readout link to suppress the amplifier's own flicker noise. Although chopping can also eliminate amplifier offset, it essentially modulates the offset to the high-frequency region. It still needs to be combined with a subsequent incremental analog-to-digital converter and a cascaded integrator-comb filter to effectively filter out the ripple introduced by chopping. Since the detector signal is extremely weak, the system often requires a large overall gain. However, excessively high gain will significantly amplify the chopping ripple and even cause system saturation. Therefore, chopping techniques must be used in conjunction with ripple suppression techniques. Integrating these multiple techniques in a space-constrained column-level processing circuit poses a significant challenge to circuit structure design.

[0004] Furthermore, there is an inherent trade-off between the gain and speed of a programmable gain amplifier: higher gain usually limits its bandwidth, making it difficult to effectively drive the subsequent analog-to-digital converter; if the system gain and accuracy are increased at the same time, power consumption will inevitably increase, which may lead to problems in chip thermal management. Summary of the Invention

[0005] In view of this, the present invention aims to provide a readout circuit for a terahertz detection array, which effectively reduces chip area and power consumption while ensuring high gain, low noise, and low offset of the readout circuit for the terahertz detection array.

[0006] To achieve the above objectives, the technical solution created by this invention is implemented as follows: This invention provides a readout circuit for a terahertz detection array, comprising: at least one readout link, each readout link including at least a current feedback instrumentation amplifier, a programmable gain amplifier, and an incremental analog-to-digital converter connected in sequence; wherein, the current feedback instrumentation amplifier amplifies the signal output from the detector in the first stage and outputs a first-stage amplified signal, the current feedback instrumentation amplifier including an instrumentation amplifier body and a first ripple suppression module, the first ripple suppression module including a first redundant segmented current rudder DAC and a first DAC code register, the first DAC code register being used to output a first target DAC control code to the first redundant segmented current rudder DAC, the first redundant segmented current rudder DAC outputting a first target DAC control code to the instrumentation amplifier body based on the first target DAC control code. The first preset node outputs a first compensation current to suppress ripple; the programmable gain amplifier receives the first-stage amplified signal and further amplifies it to obtain a second-stage amplified signal. The programmable gain amplifier includes a gain amplifier body and a second ripple suppression module. The second ripple suppression module includes a second redundant segmented current steering DAC and a second DAC code register. The second DAC code register is used to output a second target DAC control code to the second redundant segmented current steering DAC. The second redundant segmented current steering DAC outputs a second compensation current to the second preset node of the gain amplifier body based on the second target DAC control code to suppress ripple; the incremental analog-to-digital converter receives the second-stage amplified signal and performs analog-to-digital conversion to output a digital signal.

[0007] Compared with existing technologies, this invention achieves the following beneficial effects: Addressing the problems existing in current terahertz readout circuits, this invention proposes a readout circuit for a terahertz detection array. The readout link of the circuit employs a current feedback instrumentation amplifier in the first stage and introduces a redundant segmented digital-to-analog converter (first redundant segmented current rudder DAC) to suppress chopping ripple. The first redundant segmented current rudder DAC has strong anti-mismatch capability and can achieve high-precision ripple suppression under area-constrained conditions. Local chopping technology is introduced in the second-stage programmable gain amplifier to avoid additional non-ideal effects introduced by the current feedback instrumentation amplifier due to large signal swing during chopping switch switching. Furthermore, if ripple suppression is implemented only in the programmable gain amplifier, the chopping ripple from the current feedback instrumentation amplifier is easily amplified further. Therefore, this invention adopts a joint ripple suppression strategy where the current feedback instrumentation amplifier and the programmable gain amplifier work together, effectively compressing the system chopping ripple to an extremely low level.

[0008] Furthermore, to alleviate the inherent trade-off between gain and speed in programmable gain amplifiers, a pre-charge buffer based on a source follower is introduced between the programmable gain amplifier and the incremental analog-to-digital converter. The source follower uses native NMOS devices as its core transistors, and its near-zero threshold voltage characteristics effectively reduce the input dynamic range required for subsequent variable gain amplification, thereby improving the overall system performance. To further enhance the pull-up and pull-down drive capabilities of the source follower, a coupling capacitor is introduced between the gate and drain of its current source transistor, and appropriate timing is used to significantly improve the transient response characteristics of the source follower.

[0009] Meanwhile, this invention moves the complex digital control logic (i.e., global control unit) out of the column-level processing circuit. The DAC control signal is transmitted through a bus and the corresponding DAC data is latched from the bus using one control line per column. This helps to significantly shorten the length of the column-level processing circuit, so that only one set of ripple suppression control logic needs to be configured in a large-scale readout array, thereby effectively reducing the overall chip area. Attached Figure Description

[0010] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 A schematic diagram illustrating the connection relationship between the readout link and the detector as described in an embodiment of the present invention; Figure 2 A partial structural schematic diagram of the current feedback instrumentation amplifier described in the embodiment of the present invention; Figure 3 A schematic diagram of the structure of the instrumentation amplifier body of the current feedback instrumentation amplifier described in the embodiment of the present invention; Figure 4 A partial structural schematic diagram of the programmable gain amplifier described in the embodiments of the present invention; Figure 5 A schematic diagram of the structure of the gain amplifier body of the programmable gain amplifier described in the embodiment of the present invention; Figure 6 A schematic diagram of the structure of the precharge buffer described in the embodiment of the present invention; Figure 7 Timing diagram of the precharge buffer described in the embodiments of the present invention; Figure 8 A schematic diagram of the source follower of a precharge buffer as described in an embodiment of the present invention; Figure 9A schematic diagram of the transmission curve of the source follower of the precharge buffer described in the embodiment of the present invention; Figure 10 A schematic diagram of the pull-up and pull-down transient response of a precharge buffer as described in an embodiment of the present invention; Figure 11 A schematic diagram of the source follower based on output coupling of the precharge buffer described in the embodiment of the present invention; Figure 12 A schematic diagram of the pull-up and pull-down transient response of the improved precharge buffer described in the embodiment of the present invention; Figure 13 A schematic diagram of the readout circuit of the terahertz detection array described in the embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not constitute a limitation thereof.

[0012] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0013] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0014] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0015] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0016] refer to Figures 1 to 13 This invention provides a readout circuit for a terahertz detection array, comprising: at least one readout link, each readout link including at least a current feedback instrumentation amplifier 11, a programmable gain amplifier 12, and an incremental analog-to-digital converter 14 connected in sequence; wherein, the current feedback instrumentation amplifier 11 amplifies the signal output from the detector 10 in the first stage and outputs a first-stage amplified signal, the current feedback instrumentation amplifier 11 including an instrumentation amplifier body and a first ripple suppression module, the first ripple suppression module including a first redundant segmented current rudder DAC and a first DAC code register, the first DAC code register being used to output a first target DAC control code to the first redundant segmented current rudder DAC, the first redundant segmented current rudder DAC outputting a first target DAC control code to the instrumentation amplifier based on the first target DAC control code. The first preset node of the main body outputs a first compensation current to suppress ripple; the programmable gain amplifier 12 receives the first-stage amplified signal and further amplifies the first-stage amplified signal to obtain the second-stage amplified signal. The programmable gain amplifier 12 includes a gain amplifier body and a second ripple suppression module. The second ripple suppression module includes a second redundant segmented current steering DAC and a second DAC code register. The second DAC code register is used to output a second target DAC control code to the second redundant segmented current steering DAC. The second redundant segmented current steering DAC outputs a second compensation current to the second preset node of the gain amplifier body based on the second target DAC control code to suppress ripple; the incremental analog-to-digital converter 14 receives the second-stage amplified signal and performs analog-to-digital conversion to output a digital signal.

[0017] The first redundant segmented current rudder DAC and the second redundant segmented current rudder DAC both adopt a redundant segmented structure, which is beneficial to improving the robustness of the ripple suppression calibration process to device mismatch.

[0018] It should be noted that, under the combined influence of bandwidth limitations imposed by imaging rate, area requirements limited by array size, and noise demands constrained by signal quality, the key to developing terahertz image sensor readout circuits lies in achieving comprehensive performance optimization centered on high gain, low noise, low offset, and area compactness. The output signal of terahertz detectors is only in the millivolt or even microvolt range, which places high demands on the gain, noise, offset control, and overall complexity of CMOS (Complementary Metal Oxide Semiconductor) front-end signal processing circuits. At the same time, the limited pixel area also significantly restricts the expansion space of circuit functions.

[0019] In the key technologies of CMOS readout integrated circuits for terahertz detectors, the core task lies in the efficient amplification, filtering, and analog-to-digital conversion of weak terahertz signals. These functions are uniformly implemented by the array-arranged readout links, such as... Figure 1 As shown, the weak voltage signal output by the detector is first amplified with low noise by the current feedback instrumentation amplifier 11, and then further amplified to near full swing by the programmable gain amplifier 12. In some embodiments, the amplified signal is enhanced by the pre-charge buffer 13 to enhance the driving capability, and finally sent to the oversampled noise-shaping analog-to-digital converter (incremental analog-to-digital converter) to achieve high-precision analog-to-digital conversion.

[0020] Furthermore, the readout circuit of the terahertz detection array also includes a global control unit (not shown), which is configured to at least: calibrate the current feedback instrumentation amplifier 11 of the readout link to determine a first target DAC control code, and calibrate the programmable gain amplifier 12 of the readout link to determine a second target DAC control code before the readout circuit of the terahertz detection array enters the operating mode.

[0021] Furthermore, the global control unit calibrates the current feedback instrumentation amplifier 11 by: controlling the instrumentation amplifier body to enter open-loop mode, using a binary search algorithm to determine the first target DAC control code with the best ripple suppression effect, and sending the first target DAC control code to the first DAC code register; the global control unit calibrates the programmable gain amplifier 12 by: controlling the instrumentation amplifier body to enter normal operation mode and disabling the chopping function of the instrumentation amplifier body, controlling the differential input terminal of the instrumentation amplifier body to input a common-mode level, the first DAC code register outputting the first target DAC control code to the first redundant segmented current steering DAC, the first redundant segmented current steering DAC outputting a first compensation current to the first preset node of the instrumentation amplifier body to suppress ripple, and then controlling the gain amplifier body to enter open-loop mode, using a binary search algorithm to determine the second target DAC control code with the best ripple suppression effect, and sending the second target DAC control code to the second DAC code register.

[0022] Furthermore, the readout circuit of the terahertz detection array includes multiple readout links. Before the readout circuit of the terahertz detection array enters the working mode, the global control unit calibrates the current feedback instrumentation amplifier 11 and the programmable gain amplifier 12 of each readout link in sequence. The first DAC code register of each readout link is connected to the global control unit through the same first DAC code bus, and the second DAC code register of each readout link is connected to the global control unit through the same second DAC code bus. After the global control unit determines all target DAC control codes, it sends the corresponding target DAC control codes to the corresponding DAC code registers through the first DAC code bus and the second DAC code bus, and sends the corresponding latch clock signal to each DAC code register to trigger the corresponding DAC code register to latch the corresponding target DAC control code.

[0023] Furthermore, the instrumentation amplifier body includes a first chopper switch CH1, a second chopper switch CH2, a third chopper switch CH3, a first input stage transconductance Gm1, a feedback stage transconductance Gm2, and a first high-gain amplification unit. The first high-gain amplification unit includes a first-stage gain and a second-stage gain. The third chopper switch CH3 is located between the first-stage gain and the second-stage gain. The second-stage gain outputs a first positive output voltage Voutp1 and a first negative output voltage Voutn1. The first input terminal of the first chopper switch CH1 is connected to the reference common-mode voltage VCM through a first switch S1. The first input terminal of the first chopper switch CH1 is also connected to the first positive input voltage Vinp1 through a second switch S2. The second input terminal of the first chopper switch CH1 is connected to the first negative input voltage Vinn1 through a third switch S3. The second input terminal of the first chopper switch CH1 is also connected to a fourth switch... S4 is connected to the reference common-mode voltage VCM; the two outputs of the first chopper switch CH1 are respectively connected to the two inputs of the first input stage transconductance Gm1; the first input of the second chopper switch CH2 is connected to the reference common-mode voltage VCM through the fifth switch S5, and the first input of the second chopper switch CH2 is also connected to the positive feedback voltage Vfbp through the sixth switch S6; the second input of the second chopper switch CH2 is connected to the negative feedback voltage Vfbn through the seventh switch S7, and the second input of the second chopper switch CH2 is also connected to the reference common-mode voltage VCM through the eighth switch S8; the two outputs of the second chopper switch CH2 are respectively connected to the two inputs of the feedback stage transconductance Gm2; the two outputs of the feedback stage transconductance Gm2 are respectively connected to the two inputs of the first stage gain, and the two outputs of the first input stage transconductance Gm1 are also respectively connected to the two inputs of the first stage gain;The first-stage gain includes transistors M7 (7th), M8 (8th), M9 (9th), M10 (10th), M11 (11th), M12 (12th), M13 (13th), and M14 (14th). The sources of both transistors M7 and M8 are connected to ground. M7 and M8 share a common gate. The drain of M7 is connected to the source of M9, and the drain of M8 is connected to the source of M10. M10 and M9 share a common gate. The sources of M9 and M10 serve as the two input terminals of the first-stage gain. The drain of M9 and... The drain of the tenth transistor M10 serves as the two output terminals of the first-stage gain. The sources of the thirteenth transistor M13 and the fourteenth transistor M14 are both connected to the power supply voltage. The thirteenth transistor M13 and the fourteenth transistor M14 share a common gate. The drain of the thirteenth transistor M13 is connected to the source of the eleventh transistor M11. The drain of the fourteenth transistor M14 is connected to the source of the twelfth transistor M12. The eleventh transistor M11 and the twelfth transistor M12 share a common gate. The drain of the ninth transistor M9 is connected to the drain of the eleventh transistor M11. The drain of the tenth transistor M10 is connected to the drain of the twelfth transistor M12. The first preset node is either the drain of the thirteenth transistor M13 or the drain of the fourteenth transistor M14.

[0024] In the readout link, the current feedback instrumentation amplifier 11 occupies the most critical position. It directly interfaces with the weak output signal of the detector and undertakes the core task of realizing low-noise, high-gain front-end amplification. Currently, the instrumentation amplifier structures commonly used in academia and industry mainly include three operational amplifier instrumentation amplifiers, switched capacitor instrumentation amplifiers, capacitively coupled instrumentation amplifiers, and current feedback instrumentation amplifier 11, etc. Considering the characteristics of terahertz detectors such as extremely small output signal amplitude and low equivalent resistance, this invention first studies a low-noise, high-gain chopper amplifier circuit structure suitable for weak signal processing, providing a reliable foundation for subsequent analog-to-digital conversion.

[0025] For readout circuits, common implementation methods mainly include voltage readout and current readout. Voltage readout typically treats the detector as an equivalent voltage source with internal resistance and amplifies its output voltage through a front-end amplifier. This type of amplifier generally operates in closed-loop mode to achieve high gain accuracy and good stability against process, voltage, and temperature variations. When the detector output signal is mainly distributed in the low-frequency range, chopper modulation technology can be further introduced to effectively suppress the flicker noise of the amplifier device itself, thereby improving the system signal-to-noise ratio. In contrast, current readout typically treats the detector as an equivalent current source with parallel resistance and achieves current-to-voltage conversion through current integration. Since the integration time and integration capacitor can be flexibly adjusted, this readout method can theoretically achieve a larger equivalent gain and has high flexibility. However, terahertz detectors are diverse, mainly including thermal detectors, CMOS detectors, and detectors based on two-dimensional materials. Different device characteristics place significantly different requirements on the readout method.

[0026] For thermistor-type terahertz detectors, the output resistance is usually large, and the amplifier offset has a relatively small impact on the detector's operating point. Therefore, current readout can meet the system requirements, and the related readout circuit technology is relatively mature. In contrast, the output resistance of CMOS detectors and two-dimensional material terahertz detectors is usually small. After the amplifier offset voltage is applied to the detector's output resistance, it will introduce a significant offset current, which can easily lead to saturation of the integration node. At the same time, the output signal of these detectors is mainly distributed in the low-frequency region, and the flicker noise of the amplifier itself will significantly degrade the system's signal-to-noise ratio.

[0027] Therefore, considering signal amplitude, output impedance characteristics, and system noise performance, a voltage readout structure based on chopper technology is more suitable for CMOS detectors and terahertz detection applications of two-dimensional materials. The signal chain proposed in this invention is suitable for such terahertz detection systems. Specifically, this invention adopts a current feedback instrumentation amplifier architecture in the first stage of the readout chain to meet the comprehensive requirements of terahertz CMOS readout circuits for high gain, low noise, low power consumption, and small area. Compared with other instrumentation amplifier architectures, the current feedback structure processes signals in the current domain, which has unique advantages. Compared with traditional three-op-amp instrumentation amplifiers, the current feedback architecture can significantly improve common-mode rejection capability by isolating the input stage. At the same time, its overall structure contains only one amplifier unit, resulting in a smaller circuit area and lower power consumption, making it suitable for integration into large-scale terahertz focal plane arrays. In addition, unlike capacitively coupled instrumentation amplifiers, the current feedback instrumentation amplifier architecture provided by this invention does not rely on a large number of capacitors, thereby avoiding the area overhead caused by excessive capacitors and further improving the integration efficiency of the circuit.

[0028] In some embodiments, the input stage transconductance Gm1 includes a first transistor M1, a second transistor M2, and a third transistor M3. The second transistor M2 and the third transistor M3 form a differential pair. The first transistor M1 serves as a current source. The connection configuration of the first transistor M1, the second transistor M2, and the third transistor M3 is referenced. Figure 2 This will not be elaborated upon here; the feedback stage transconductance Gm2 includes the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. The fifth transistor M5 and the sixth transistor M6 form a differential pair. The fourth transistor M4 serves as a current source. The connection method of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 is referenced. Figure 2 The details are omitted here; the second-stage gain includes the first resistor R1, the second resistor R2, the third resistor, the fourth resistor R4, the fifth resistor R5, the first capacitor C1, the second capacitor C2, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, and the nineteenth transistor M19. The connection methods of the capacitors, resistors, and transistors in the second-stage gain can be found in [reference needed]. Figure 1 and Figure 2 This will not be elaborated upon here.

[0029] refer to Figure 1 and Figure 2 The input stage transconductance Gm1 and the feedback stage transconductance Gm2 are connected to the output stage (high-gain amplifier unit Gm3) as the input stage and feedback stage, respectively. The input stage transconductance Gm1 converts the input voltage Vin into an input current, and the feedback stage transconductance Gm2 converts the feedback voltage Vfb into a feedback current. The difference in current between the two is suppressed by the high-gain amplifier unit Gm3 to ensure precise current matching between the input and feedback paths. Under high open-loop gain conditions, the closed-loop gain of the current feedback instrumentation amplifier 11 is: ; in, Represents the differential output voltage. Represents differential input voltage. , This represents the resistance value of the first resistor, R1. This represents the resistance value of the third resistor, R3. This represents the resistance value of the second resistor, R2. The transconductance parameter representing the feedback stage transconductance Gm2, The transconductance parameter Gm1 represents the input stage transconductance. Therefore, by adjusting the value of the second resistor R2, the chopper current feedback amplifier can achieve adjustable gain, thus adapting to diverse application requirements under different terahertz detection conditions. Since the output signal of the terahertz detector is mainly concentrated in the low-frequency region, the flicker noise of the amplifier input stage will dominate in this frequency band and significantly reduce the system's signal-to-noise ratio. To effectively suppress this low-frequency noise source, chopper modulation technology is introduced into the circuit to shift the flicker noise to a higher frequency and filter it out in the subsequent stage, thereby achieving low-noise amplification.

[0030] The third chopper switch CH3 of this invention is located between the first-stage gain and the second-stage gain. In conventional designs, demodulation chopper switches are usually arranged between common-source and common-gate current mirrors. By chopping the current mirrors, a higher chopping frequency can be achieved, and the chopping speed can be higher than the operating speed of the amplifier itself. However, this type of current mirror chopping structure cannot effectively eliminate the offset and low-frequency noise introduced by the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12. To address this problem, this invention moves the demodulation chopper switch (the third chopper switch CH3) forward to between the first-stage gain and the second-stage gain, thereby suppressing the offset and noise of the aforementioned devices during the chopping and demodulation process. In addition, since the signal swing is small at this node, this structure can ensure a high chopping speed without introducing additional dynamic performance degradation, thus balancing noise suppression and high-speed operation.

[0031] The gates of the first transistor M1 and the fourth transistor M4 are connected to the bias voltage node generated by the on-chip bias circuit, serving as the tail current source for the differential pair of the input and feedback stages. The seventh transistor M7 and the eighth transistor M8 also serve as tail current sources, with their gates provided with corresponding bias voltages by the bias circuit to set the bias current of the subsequent circuits. The ninth transistor M9 and the tenth transistor M10 are common-gate transistors, with their gates connected to the same bias voltage node to improve the output impedance and mirroring accuracy of the current mirror. The eleventh transistor M11 and the twelfth transistor M12 are also biased by the bias circuit, forming a high-output-impedance common-source common-gate current mirror together with the thirteenth transistor M13 and the fourteenth transistor M14.

[0032] The nineteenth transistor M19 is used as a tail current source. Its gate is also connected to the bias voltage node generated by the on-chip bias circuit to set the bias current of the corresponding branch. Under normal conditions, the second-stage gain does not have the nineteenth transistor M19 as a tail current source. However, since this amplifier is a two-stage common-mode feedback amplifier, the instability of the common-mode level inside the first-stage gain can easily cause the operating current of the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17 and the eighteenth transistor in the second-stage gain to not conform to the set current, thus causing the output common-mode level to deviate from the expected value. Therefore, a tail current source is added here to set the operating current of the fifteenth transistor M15 and the seventeenth transistor M17. As long as the common-mode level of the first-stage gain is within a certain range, the operating current of the second-stage gain will not be affected by the common-mode level of the first-stage gain.

[0033] Furthermore, the global control unit includes a dynamic comparator and a logic module. The two input terminals of the dynamic comparator are respectively connected to the two output terminals of the instrumentation amplifier body, and the output terminal of the dynamic comparator is connected to the logic module. A binary search algorithm is used to determine the first target DAC control code with optimal ripple suppression effect. This includes: during the ripple suppression calibration phase, the logic module controls the first DAC code register to output the first DAC control code based on the logic signal output by the dynamic comparator. The first redundant segmented current steering DAC outputs compensation current to the first preset node of the instrumentation amplifier body based on the first DAC control code to suppress ripple. The ripple suppression calibration phase includes initialization and a binary search process. Initialization includes... The logic module clears the first DAC control code to zero, the instrumentation amplifier switches to open-loop mode, and amplifies the initial ripple using the high gain of the open loop. The dynamic comparator performs polarity determination on the amplified initial ripple and outputs a logic signal representing the determination result to the logic module. The binary search process includes: the logic module iteratively updates the first DAC control code based on the logic signal from high to low bits, with the number of iterations equal to the number of bits in the first DAC control code. The first DAC control code is dynamically updated by retaining valid bits and backing up excess bits, so that the compensation current output by the first redundant segmented current steering DAC gradually approaches the target value for canceling the ripple, and finally the first target DAC control code is obtained.

[0034] In some embodiments, the dynamic comparator performs polarity determination on the amplified initial ripple and outputs a logic signal characterizing the determination result, including: if the amplified initial ripple is a positive ripple, the dynamic comparator outputs a high level, and the logic module sets a compensation current to be injected into the drain of the fourteenth transistor M14 to offset the positive offset; if the amplified initial ripple is a negative ripple, the dynamic comparator outputs a low level, and the logic module sets a compensation current to be injected into the drain of the thirteenth transistor M13 to offset the negative offset.

[0035] In some embodiments, the specific process of obtaining the first target DAC control code is as follows: Starting from the most significant bit, the current bit is set to 1, and the first DAC control code is generated and sent to the first redundant segmented current steering DAC. The first redundant segmented current steering DAC activates the current unit with the corresponding weight to adjust the magnitude of the compensation current. After the analog node stabilizes, the dynamic comparator outputs a logic signal representing the new decision result. If the polarity of the current decision result is the same as the polarity of the initial decision result, the current bit is kept as 1. If the polarity of the current decision result is different from the polarity of the initial decision result, the current bit is reset to 0. The next bit is updated until all bits of the DAC control code are updated.

[0036] It should be noted that because the signal output by the terahertz detector is extremely weak, in the μV range, the gain of the entire system in this invention is several thousand times. If the total gain of the system is 2000 times, and the offset of the front-end instrumentation amplifier is 2mV, the final amplification voltage will be 4V. Such a large voltage will cause extremely large chopping ripple, saturating the entire system. Therefore, it is necessary to eliminate the chopping ripple of the system. For the current feedback instrumentation amplifier 11, only one first redundant segmented current rudder DAC is used. By switching, it selects between the M13 branch and the M14 branch, injecting current into one branch to complete the ripple elimination. This invention uses successive approximation calibration logic. In some embodiments, the redundant segmented current rudder DAC is a 9-bit DAC. In this case, only 10 cycles are needed to complete the ripple suppression.

[0037] Specifically, under negative feedback, the system establishes a steady-state operating point by adjusting the voltage of the feedback stage. The equivalent current mismatch introduced by input stage device mismatch is absorbed by the feedback loop under closed-loop conditions and converted into the steady-state voltage offset required by the feedback stage to compensate for the input stage mismatch effect. Therefore, without the introduction of the first redundant segmented current rudder DAC, the input stage offset is mainly manifested as a DC voltage offset on the feedback stage, which corresponds to the system's equivalent input offset. After introducing the first redundant segmented current rudder DAC, the offset compensation mechanism shifts from feedback voltage regulation to the current domain. The first redundant segmented current rudder DAC directly corrects the equivalent current mismatch introduced by input stage mismatch by injecting controllable compensation current into key nodes, thereby reducing the steady-state voltage offset required by the feedback stage to maintain closed-loop balance. This method weakens the impact of input mismatch on the system operating point before feedback regulation, making the system steady state closer to the ideal symmetrical state and achieving effective calibration of input offset.

[0038] From the perspective of the equivalent model, the input offset voltage of the system can be approximated as: ; in, Represents the offset voltage. The equivalent current offset introduced by the input differential pair. To ensure effective transconductance of the feedback stage, the first redundant segmented current rudder DAC minimizes the injected current by adjusting the current. This allows for the correction of input mismatch.

[0039] It should be noted that system offset does not originate solely from input stage component mismatch. Parameter mismatches in each stage of the amplifier circuit can introduce offset components. Under negative feedback, these offset sources collectively determine the system's steady-state operating point under closed-loop conditions. Their impact ultimately manifests as an output voltage shift under zero-input conditions, i.e., the system's equivalent offset voltage. By introducing a first redundant segmented current-steering DAC and adjusting its injection current, these various offset effects can be uniformly compensated at the system level, minimizing the output voltage under zero-input conditions and effectively reducing the overall system offset level. This calibration process does not rely on the distinction of specific offset sources but rather uses minimizing the overall output offset as the optimization objective, thus enabling simultaneous compensation of offset components from different circuit stages.

[0040] Under chopping conditions, the DC offset in the system is modulated to the chopping frequency and its harmonics, and the DC component is converted into chopping ripple. Therefore, under non-chopping conditions, the system offset is effectively suppressed, which is equivalent to reducing the ripple amplitude generated after chopping modulation.

[0041] Because terahertz readout circuits have strict area limitations, the self-zeroing high-precision comparators traditionally used in binary search ripple calibration logic are not suitable. To avoid using self-zeroing high-precision comparators that occupy a large area, this solution will briefly operate the amplifier in open-loop mode before entering the comparison stage. Figure 2 In this circuit, clk1 controls the second switch S2, the third switch S3, the sixth switch S6, and the seventh switch S7 to open, while clk2 controls the first switch S1, the fourth switch S4, the fifth switch S5, and the eighth switch S8 to close. The inputs of Gm1 and Gm2 are simultaneously connected to VCM, thus entering open-loop mode. In open-loop mode, any small offset of the amplifier will be amplified to near full swing. Under these conditions, only a dynamic comparator with a very small footprint is needed to achieve high-precision comparison operation.

[0042] Furthermore, the gain amplifier body includes a fourth chopper switch CH4, a fifth chopper switch CH5, a fourth input stage transconductance Gm4, a second high-gain amplification unit, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a thirteenth switch S13, and a fourteenth switch S14. The second high-gain amplification unit includes a third-stage gain and a fourth-stage gain. The fifth chopper switch CH5 is located between the third-stage gain and the fourth-stage gain. The fourth-stage gain outputs a second positive output voltage Voutp2 and a second negative output voltage Voutn2. The first input terminal of the fourth chopper switch CH4 is connected to the second positive input voltage Vinp2 through the sixth resistor R6. The second positive input voltage Vinp2 is the first positive output voltage Voutp1. The second input terminal of the fourth chopper switch CH4 is connected to the second negative input voltage Vinn2 through the seventh resistor R7. The second negative input voltage Vinn2 is the first negative output voltage Voutn1. The two output terminals of the fourth chopper switch CH4 are respectively connected to the two input terminals of the fourth input stage transconductance Gm4. The two output terminals of the fourth input stage transconductance Gm4 are respectively connected to the two input terminals of the third stage gain. The eighth resistor R8 and the thirteenth switch S13 are connected in series to the first input terminal of the fourth chopper switch CH4 and the output terminal of the fourth stage gain outputting the second negative output voltage Voutn2. The ninth resistor R9 and the fourteenth switch S14 are connected in series to the second input terminal of the fourth chopper switch CH4 and the output terminal of the fourth stage gain outputting the second positive output voltage Voutp2.The third-stage gain stage includes transistors M27 (27th), M28 (28th), M29 (29th), M30 (30th), M31 (31st), M32 (32nd), M33 (33rd), and M34 (34th). The sources of transistors M27 and M28 are both connected to ground. Transistors M27 and M28 share a common gate. The drain of transistor M27 is connected to the source of transistor M29. The drain of transistor M28 is connected to the source of transistor M30. Transistors M30 and M29 share a common gate. The sources of transistors M29 and M30 serve as the two input terminals of the third-stage gain stage. The drains of transistors M29 (29th) and M30 (30th) serve as the two output terminals of the third-stage gain. The sources of transistors M33 (33rd) and M34 (34th) are both connected to the power supply voltage. Transistors M33 and M34 share a common gate. The drain of transistor M33 is connected to the source of transistor M31 (31st), and the drain of transistor M34 is connected to the source of transistor M32 (32nd). Transistors M31 and M32 also share a common gate. The drain of transistor M29 is connected to the drain of transistor M31 (31st), and the drain of transistor M30 is connected to the drain of transistor M32 (32nd). The second preset node is either the drain of transistor M33 (33rd) or the drain of transistor M34 (34th).

[0043] In some embodiments, the fourth input stage transconductance Gm4 includes a twenty-first transistor M21, a twenty-second transistor M22, and a twenty-third transistor M23. The twenty-second transistor M22 and the twenty-third transistor M23 form a differential pair. The twenty-first transistor M21 serves as a current source. The connection configuration of the twenty-first transistor M21, the twenty-second transistor M22, and the twenty-third transistor M23 is referenced. Figure 5 The details are omitted here. The connection method of each transistor in the fourth-stage gain is the same as that in the second-stage gain. The fourth-stage gain includes resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, capacitor C21 (21st), capacitor C22 (22nd), transistor M35 (35th), transistor M36 (36th), transistor M37 (37th), transistor M38 (38th), and transistor M39 (39th). The connection method of the capacitors, resistors, and transistors in the fourth-stage gain can be found in [reference needed]. Figure 5 This will not be elaborated upon here.

[0044] The process of determining the second target DAC control code with the best ripple suppression effect using the binary search algorithm is similar to the process of determining the first target DAC control code with the best ripple suppression effect using the binary search algorithm, and will not be described in detail here.

[0045] It should be noted that after the chopper-modulated instrumentation amplifier, the signal enters the programmable gain amplifier stage. The main function of the programmable gain amplifier is to further amplify the signal output from the chopper-modulated low-noise instrumentation amplifier, bringing it closer to full swing, thereby enabling the analog-to-digital converter (ADC) to achieve higher quantization accuracy. Simultaneously, the programmable gain amplifier provides the necessary drive capability to ensure the ADC operates normally. Programmable gain amplifiers typically achieve programmable gain adjustment based on a basic amplifier structure by adjusting the transistor transconductance, changing the load impedance, or introducing an attenuation network. Depending on the gain adjustment method, programmable gain amplifiers can be divided into two main categories: analog control and digital control. The digital control structure is also referred to as a programmable gain amplifier. In analog variable gain structures, the typical example of gain control by adjusting transconductance is the Gilbert programmable gain amplifier. This structure has the advantages of high bandwidth and suitability for wideband signal amplification, but its inherent circuit characteristics limit the gain accuracy and gain adjustment range. Programmable gain amplifiers with closed-loop structures mainly include resistive variable feedback closed-loop amplifiers and capacitive variable feedback closed-loop amplifiers. Considering that the terahertz readout circuit needs to accurately amplify DC and low-frequency signals while taking into account high gain accuracy, this invention selects the resistive variable feedback closed-loop amplifier as the programmable gain amplifier.

[0046] like Figure 4As shown, the programmable gain amplifier 12 is based on a two-stage operational amplifier architecture and achieves programmable gain adjustment through digital control, meeting the comprehensive requirements of the terahertz focal plane array in terms of dynamic range, gain accuracy, and driving capability. The programmable gain amplifier 12 also employs chopping technology, but here it uses a local chopping structure. The chopping modulation switch is placed inside the loop, modulating only the core amplification stage, effectively eliminating offset and low-frequency noise generated by the operational amplifier. This noise typically accounts for the majority of the noise in the entire closed-loop amplifier. Another advantage of local chopping is the extremely small voltage difference at the amplifier input. Therefore, when the chopping switch switches, it does not cause a large voltage jump, thus avoiding excessive bandwidth requirements on the front-stage current feedback instrumentation amplifier 11. Since the front-stage needs to achieve high gain, its operational amplifier bandwidth-gain product is significantly distributed by the closed-loop gain. If the programmable gain amplifier 12 adopts a global chopping structure, the front-stage will find it difficult to drive the large node oscillations caused by chopping switching. However, the local chopping technique does not modulate the input and feedback resistors. Therefore, the mismatch between resistors cannot be eliminated by chopping, which means that the common-mode rejection ratio of the entire amplifier will mainly depend on the matching accuracy of the feedback resistor, thus limiting its common-mode rejection performance. However, in the application scenario of this invention, the input common mode of the programmable gain amplifier 12 is stably set and kept constant by the pre-amplifier, so the common-mode rejection ratio of this structure is not a key indicator.

[0047] Figure 5 The internal two-stage amplification structure of the programmable gain amplifier 12 is shown. To suppress the ripple generated by the programmable gain amplifier 12 after chopping modulation, a current rudder DAC is also introduced at the corresponding position to compensate for the offset ripple caused by chopping. Its principle is the same as the ripple elimination method of the current feedback instrumentation amplifier 11. The compensation process adopts binary search logic. By continuously adjusting the output current of the current rudder DAC, the optimal operating point that minimizes the chopping ripple is found. In the ripple elimination stage, in order to keep the programmable gain amplifier 12 in open-loop operation and thus amplify the internal offset for comparison and judgment, the circuit is equipped with the thirteenth switch S13 and the fourteenth switch S14 to temporarily disconnect the feedback.

[0048] If the ripple suppression DAC code value is set independently for the programmable gain amplifier 12 to minimize its own output ripple, the variable gain amplifier can be placed in open-loop mode during the calibration phase, and its differential input terminals can be connected to the common-mode level simultaneously. The DAC control code obtained through binary search can minimize the chopping ripple of the PGA (Programmable Gain Amplifier). However, in this case, the chopping ripple generated by the CFIA (Current-Feedback Instrumentation Amplifier) ​​will still be further amplified by the gain of the PGA, resulting in a still large overall system ripple.

[0049] To address the aforementioned issues, this invention employs a joint ripple suppression strategy, coordinating the calibration of both the pre-amplifier and post-amplifier stages. Specifically, firstly, chopper ripple suppression calibration is performed on the CFIA to minimize its output ripple. After calibration, the CFIA enters normal operating mode while maintaining chopper off, with its inputs connected to zero input (i.e., both differential terminals are connected to common-mode levels). Under these conditions, the programmable gain amplifier 12 is placed in open-loop mode, with its input directly connected to the output node of the CFIA. This allows the residual chopper ripple of the CFIA to be effectively treated as an offset term of the PGA and suppressed during the PGA ripple suppression search process. Through this joint ripple suppression process, the final residual chopper ripple of the system is equivalent to the minimum ripple level obtained by independently optimizing the PGA under ideal pre-amplifier conditions. This avoids the problem of the pre-amplifier ripple being further amplified during the subsequent amplification process, significantly improving the overall ripple suppression effect of the readout link.

[0050] After completing the above calibration process, both the current feedback instrumentation amplifier 11 and the variable gain amplifier enter normal operating mode and start chopping operation. The configured DAC control code remains unchanged during normal operation.

[0051] Furthermore, the readout circuit of the terahertz detection array also includes a precharge buffer 13, which is located between the programmable gain amplifier 12 and the incremental analog-to-digital converter 14. The precharge buffer 13 includes a first source follower SF1, a second source follower SF2, an eleventh switch S11, a twelfth switch S12, a ninth switch S9, and a tenth switch S10. The input terminal of the first source follower SF1 is connected to the positive output terminal of the programmable gain amplifier 12, and the input terminal of the second source follower SF2 is connected to the programmable gain amplifier 12. The negative output terminal of the first source follower SF1 is connected to the positive input terminal of the incremental analog-to-digital converter 14 through the eleventh switch S11, the output terminal of the second source follower SF2 is connected to the negative input terminal of the incremental analog-to-digital converter 14 through the twelfth switch S12, the connection between the positive output terminal of the programmable gain amplifier 12 and the positive input terminal of the incremental analog-to-digital converter 14 is controlled by the ninth switch S9, and the connection between the negative output terminal of the programmable gain amplifier 12 and the negative input terminal of the incremental analog-to-digital converter 14 is controlled by the tenth switch S10.

[0052] Furthermore, the first source follower SF1 includes a forty-first transistor M41, a forty-second transistor M42, a forty-third transistor M43, and a first coupling capacitor C3. The forty-fourth transistor M44 serves as the ninth switch S9. The gate of the forty-first transistor M41 serves as the input terminal of the first source follower SF1, and the source of the forty-first transistor M41 serves as the output terminal of the first source follower SF1. The drain of the forty-first transistor M41 is connected to the power supply voltage. The source of the forty-second transistor M42 is connected to the drain of the forty-third transistor M43, and the drain of the forty-second transistor M42 is connected to the forty-third transistor M43. The source of transistor M41, the gate of transistor M42 (42) is connected to the corresponding bias voltage, the gate of transistor M43 (43) is connected to the first terminal of the first coupling capacitor C3, the second terminal of the first coupling capacitor C3 is connected to the source of transistor M41, the source of transistor M43 is connected to ground, the source of transistor M44 (44) is connected to the corresponding bias voltage, the gate of transistor M44 receives the third clock signal clk3, and the drain of transistor M44 is connected to the gate of transistor M43. Transistor M41 is native. The second source follower SF2 includes a 51st transistor, a 52nd transistor, a 53rd transistor, and a second coupling capacitor. The 54th transistor acts as the 10th switch S10. The gate of the 51st transistor serves as the input terminal of the second source follower SF2, and the source of the 51st transistor serves as the output terminal of the second source follower SF2. The drain of the 51st transistor is connected to the power supply voltage. The source of the 52nd transistor is connected to the drain of the 53rd transistor, and the drain of the 52nd transistor is connected to the source of the 51st transistor. The gate of the 52nd transistor is connected to the corresponding bias voltage. The gate of the 53rd transistor is connected to the first terminal of the second coupling capacitor, and the second terminal of the second coupling capacitor is connected to the source of the 51st transistor. The source of the 53rd transistor is connected to the ground voltage. The source of the 54th transistor is connected to the corresponding bias voltage. The gate of the 54th transistor receives the third clock signal clk3, and the drain of the 54th transistor is connected to the gate of the 53rd transistor. The 51st transistor is a native NMOS transistor.

[0053] Furthermore, the eleventh switch S11 and the twelfth switch S12 are controlled by the fourth clock signal clk4. During the sampling period, the pre-charge buffer 13 first performs a pre-sampling mode and then a precise sampling mode. The pre-sampling mode includes: the eleventh switch S11 and the twelfth switch S12 are both closed by the fourth clock signal clk4, and the ninth switch S9 and the tenth switch S10 are both open by the third clock signal clk3. The two output signals of the current feedback instrumentation amplifier 11 pass through the first source follower SF1 and the second source follower SF2 respectively and enter the sampling capacitor inside the incremental analog-to-digital converter 14 to pre-charge the sampling capacitor. The precise sampling mode includes: the eleventh switch S11 and the twelfth switch S12 are both open by the fourth clock signal clk4, and the ninth switch S9 and the tenth switch S10 are both on by the third clock signal clk3. The output terminal of the current feedback instrumentation amplifier 11 is directly connected to the input terminal of the incremental analog-to-digital converter 14. There is a time interval tov between the pre-sampling mode and the precise sampling mode.

[0054] It should be noted that during each incremental noise-shaping ADC sampling process, the voltage of the lower plate of the ADC sampling capacitor undergoes a significant jump. The programmable gain amplifier 12 must pull the voltage of the lower plate of the sampling capacitor back to its normal output level within a very short sampling time. This process places high demands on the op-amp bandwidth-gain product and transient response capability of the programmable gain amplifier 12. Although a lower gain is beneficial for improving the closed-loop bandwidth, it will lead to insufficient input swing of the subsequent ADC, making it difficult to fully utilize the full scale of the ADC. To alleviate this problem, this invention introduces a pre-charge buffer stage between the programmable gain amplifier 12 and the ADC to pre-charge the ADC sampling capacitor. This ensures that the ADC input is close to full swing without significantly increasing the op-amp bandwidth-gain product of the programmable gain amplifier 12, thereby maximizing the ADC accuracy.

[0055] refer to Figure 6 The precharge buffer 13 is a dedicated amplification stage whose core purpose is to significantly reduce the drive capability required by the programmable gain amplifier 12 at the sampling instant without compromising the ADC accuracy. The timing of the precharge buffer 13 is as follows: Figure 7As shown. In the first half of each sampling cycle, the precharge buffer 13 operates in "pre-sampling mode". At this time, the third clock signal clk3 is low to control the corresponding switch to open, and the fourth clock signal clk4 is high to control the corresponding switch to close. The programmable gain amplifier 12 is connected to the internal sampling capacitor of the ADC via the source follower to realize the pre-charging of the sampling capacitor. Since the precharge buffer 13 undertakes most of the charging task of the sampling capacitor, the voltage change at the input of the ADC is mainly driven by the precharge buffer 13. The programmable gain amplifier 12 only needs to drive the input node of the source follower. Therefore, its bandwidth and transient performance requirements are effectively reduced.

[0056] In the latter half of the sampling cycle, the system enters "precise sampling mode." At this time, the third clock signal clk3 goes high to control the corresponding switch to close, and the fourth clock signal clk4 goes low to control the corresponding switch to open. The precharge buffer 13 is disconnected from the signal chain, and the built-in sampling capacitor is directly connected to the output of the programmable gain amplifier 12. This structure ensures that the signal ultimately falling on the sampling capacitor is entirely determined by the programmable gain amplifier 12, thereby eliminating the errors and distortions caused by the precharge buffer 13. This prevents the accuracy of the ADC input from being affected by the precharge operation of the preceding stage. By adopting the precharge buffer 13 structure, the bandwidth and dynamic response requirements of the programmable gain amplifier 12 driving the large capacitor are significantly relaxed on the one hand, and on the other hand, it is ensured that the precharge buffer 13 will not become the accuracy bottleneck of the overall signal chain, thus achieving an effective trade-off between bandwidth and accuracy requirements under high-speed, large-capacitor sampling conditions.

[0057] After the sampling period is completed, the amplifier setup process begins. Its function is to gradually transfer the voltage (or equivalent charge) stored on the sampling capacitor to the feedback capacitor through closed-loop negative feedback, thereby forming the final stable output voltage. This setup process is determined by the closed-loop dynamic characteristics of the amplifier. Its setup speed and residual error are mainly limited by the op-amp bandwidth-gain product and the available setup time.

[0058] like Figure 8 As shown, the core structure of the precharge buffer 13 is a source follower (SF). The forty-first transistor M41 is a native NMOS with a negative threshold voltage. The advantage of using a native NMOS device is that it significantly reduces the voltage difference between the input terminal Vin and the output terminal Vout. For the subsequent precision programmable gain amplifier 12, this effectively reduces the required range of output voltage variation.

[0059] Figure 9 The static transfer characteristic curves of the source follower are given, from Figure 9It can be observed that the input and output are close. Figure 10 The pull-up and pull-down transient response of the precharge buffer 13 is demonstrated. Under a static bias current of 25µA and a sampling capacitor of 400fF for the ΔΣADC, it can be seen that this structure has a fast response speed on the rising edge, but a relatively slow response speed on the falling edge. This is because the pull-down speed is determined by the static current of transistor M24 in the pull-down path. To improve the pull-down capability of the source follower without increasing static power consumption, this invention introduces a coupling capacitor (C3) between the gate of the current mirror transistor M43 of the source follower and the output node, such as... Figure 11 As shown, the first coupling capacitor C3 modulates the gate potential of M43 during the transient process, which not only significantly enhances the pull-down capability of the source follower, but also improves the pull-up capability.

[0060] When the precharge buffer 13 is in precise sampling mode, M44 is normally turned on, and the gate potential of M43 is pulled to the bias voltage Vbn1. At this time, the circuit behavior is consistent with that of a conventional source follower. When entering the precharge mode, the programmable gain amplifier 12 charges the subsequent node through the source follower. Due to the switching of the working mode, the output node Vout3 will produce a large transient change.

[0061] When the sampling capacitor of the ΔΣADC (ΔΣ analog-to-digital converter) is initially connected to the power supply voltage, Vout3 will jump upwards. Due to the effect of the first coupling capacitor C3, the gate potential of M43 will synchronously rise, causing its drain current to increase rapidly, thus quickly pulling Vout3 back to the normal operating level. During this process, the transient current of M43 is much greater than its static bias current, significantly enhancing the pull-down capability of the source follower. Conversely, when the sampling capacitor is initially connected to ground, Vout3 will jump downwards. Under the coupling effect of the first coupling capacitor C3, the gate potential of M43 will decrease accordingly, reducing its current, while the current of M41 will increase, thus achieving a similarly rapid recovery of Vout3.

[0062] Figure 12 The dynamic response results of the improved source follower provided by this invention are given. It can be seen that under the condition of only 10µA static bias current, facing a 400fF ΔΣADC sampling capacitor, the source follower can recover to the steady-state operating level within about 13ns, and its pull-up and pull-down capabilities are basically symmetrical, which verifies the effectiveness of this structure in terms of dynamic driving capability.

[0063] In other words, a pre-charge buffer 13 is provided between the variable gain amplifier and the subsequent analog-to-digital converter. The pre-charge buffer 13 adopts a source follower structure, and a coupling capacitor is provided between the gate of the current mirror transistor of the source follower and the output node to enhance the transient drive capability without increasing the static power consumption. The analog-to-digital converter is an incremental ΔΣ analog-to-digital converter. The pre-charge buffer 13 is used to quickly charge and discharge the sampling capacitor of the analog-to-digital converter during the switching of the sampling stage.

[0064] refer to Figure 13The column-level readout circuit architecture of the large-scale terahertz readout array proposed in this invention is implemented in a column-parallel manner. Each column readout link consists of a current feedback instrumentation amplifier 11, a programmable gain amplifier 12, a source follower-based precharge buffer 13, and an analog-to-digital converter, etc., and is integrated at high density through a shared control bus and independent timing. In each column, the weak analog signal output by the detector is first fed into the current feedback instrumentation amplifier 11. This stage integrates a ripple suppression DAC, which is used to achieve low-noise amplification under high gain conditions and suppress the output ripple introduced by the chopping mechanism. The digital control code of the ripple suppression DAC in the CFIA is loaded by the column-level DAC code register group. Its control information is broadcast to each column through a shared ripple suppression DAC code bus and is locally latched at the column level. During ripple suppression configuration, the global ripple suppression control logic sequentially evaluates each column of channels and selects the optimal DAC code value that minimizes output ripple based on the unique chopping ripple characteristics of each column amplifier. The selected code value is then transmitted via the broadcast bus and independently latched in the corresponding column. This broadcast plus local latching control mechanism ensures that the ripple suppression strategy remains consistent at the system level, while the specific DAC configuration can be adaptively optimized for the non-ideals of each column channel. This avoids redundant integration of complex digital control logic at the column level while effectively compensating for inter-column mismatch and offset differences. Subsequently, the amplified signal enters the programmable gain amplifier 12 (PGA) to further adjust the signal amplitude to match the input dynamic range of the subsequent analog-to-digital converter. The PGA also integrates an independent ripple suppression DAC, and loads control codes through the corresponding DAC code register, thus forming a joint ripple suppression mechanism with the preceding CFIA to effectively reduce the overall chopping ripple level of the system. To alleviate the trade-off between speed and drive capability between the PGA and the analog-to-digital converter under high-gain conditions, a source follower-based pre-charge buffer 13 is introduced between the PGA and the analog-to-digital converter. This buffer improves the transient response capability of the interface node through pre-charging, thereby ensuring the accuracy of the subsequent analog-to-digital conversion process. Each column signal is finally sent to an incremental CIFF Delta-Sigma ADC to complete high-precision analog-to-digital conversion and output the corresponding digital result. Among them, each column-level channel independently latches different ripple suppression ADC control codes according to the differences in its own amplifier offset and chopping ripple characteristics to achieve adaptive compensation for non-ideal differences between columns.

[0065] It should be noted that, for Figure 2 , Figure 4 , Figure 5 as well as Figure 6, Vinn3=Voutn2, Vinp3=Voutp2, Vinn2=Voutn1, Vinp2=Voutp1.

[0066] This invention proposes a joint ripple suppression strategy for large-scale arrays. By performing phased and coordinated calibration of the front-stage current feedback instrumentation amplifier 11 and the rear-stage programmable gain amplifier 12, it effectively avoids the problem of further amplification of the chopping ripple in the front-stage amplification process, significantly reducing the overall chopping ripple level of the system. It uses an open-loop mode combined with redundant segmented DACs and a binary search algorithm for ripple suppression calibration. During the calibration phase, a high-precision closed-loop amplification structure is not required; the optimal DAC code value search can be completed solely by a simple comparison decision, thereby reducing circuit complexity and improving robustness to device mismatch. A DAC code distribution mechanism of global broadcast and column-level local latching is introduced. The centralized ripple suppression control logic (global control unit) generates the DAC control code and broadcasts it to each column channel via a shared bus. Each column independently latches the optimal code value, ensuring inter-column adaptive calibration capability while avoiding column-level re-calibration. The complex digital control logic is integrated to significantly reduce column-level area and digital noise coupling. By uniformly suppressing the residual chopping ripple of the pre-stage amplifier as equivalent to the offset of the subsequent amplifier, the final residual ripple of the system is equivalent to the minimum ripple level obtained by independently optimizing the subsequent amplifier under ideal pre-stage conditions, thus ensuring ripple suppression effect under high-gain conditions at the system level. The pre-charge source follower buffer structure based on output coupling (pre-charge buffer 13) enhances transient current through capacitive coupling without increasing static power consumption, significantly improving the pull-up and pull-down drive capability of the interface node and meeting the fast recovery requirement of the incremental ΔΣADC sampling capacitor under high-speed conditions. Through the collaborative design of multiple circuit-level and architecture-level technologies, while ensuring high gain, low noise and low offset performance, a scalable implementation of a large-scale terahertz readout array that is highly sensitive to area and power consumption is achieved, which has good engineering practicality and promotion value.

[0067] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this invention can be achieved, and this is not limited herein.

[0068] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A readout circuit for a terahertz detection array, characterized in that, include: At least one readout link, the readout link comprising at least a current feedback instrumentation amplifier, a programmable gain amplifier, and an incremental analog-to-digital converter connected in sequence; The current feedback instrumentation amplifier amplifies the signal output by the detector in the first stage and outputs the first amplified signal. The current feedback instrumentation amplifier includes an instrumentation amplifier body and a first ripple suppression module. The first ripple suppression module includes a first redundant segmented current rudder DAC and a first DAC code register. The first DAC code register is used to output a first target DAC control code to the first redundant segmented current rudder DAC. The first redundant segmented current rudder DAC outputs a first compensation current to a first preset node of the instrumentation amplifier body based on the first target DAC control code to suppress ripple. The programmable gain amplifier receives the first-stage amplified signal and further amplifies the first-stage amplified signal to obtain the second-stage amplified signal. The programmable gain amplifier includes a gain amplifier body and a second ripple suppression module. The second ripple suppression module includes a second redundant segmented current steering DAC and a second DAC code register. The second DAC code register is used to output a second target DAC control code to the second redundant segmented current steering DAC. The second redundant segmented current steering DAC outputs a second compensation current to the second preset node of the gain amplifier body based on the second target DAC control code to suppress ripple. The incremental analog-to-digital converter receives the second-stage amplified signal and performs analog-to-digital conversion to output a digital signal.

2. The readout circuit of the terahertz detection array according to claim 1, characterized in that, The readout circuit of the terahertz detection array also includes a global control unit, which is configured to at least: Before the readout circuit of the terahertz detection array enters the operating mode, the current feedback instrumentation amplifier of the readout link is calibrated to determine the first target DAC control code, and the programmable gain amplifier of the readout link is calibrated to determine the second target DAC control code.

3. The readout circuit of the terahertz detection array according to claim 2, characterized in that, The global control unit calibrates the current feedback instrumentation amplifier by: controlling the instrumentation amplifier body to enter open-loop mode, using a binary search algorithm to determine the first target DAC control code with the best ripple suppression effect, and sending the first target DAC control code to the first DAC code register; The global control unit calibrates the programmable gain amplifier by: controlling the instrumentation amplifier body to enter normal operating mode and disabling the chopping function of the instrumentation amplifier body; controlling the differential input terminal of the instrumentation amplifier body to input a common-mode level to eliminate the influence of the input signal on the calibration decision; the first DAC code register outputs the first target DAC control code to the first redundant segmented current steering DAC; the first redundant segmented current steering DAC outputs a first compensation current to the first preset node of the instrumentation amplifier body to suppress ripple; then controlling the gain amplifier body to enter open-loop mode; using a binary search algorithm to determine the second target DAC control code with the best ripple suppression effect; and sending the second target DAC control code to the second DAC code register.

4. The readout circuit of the terahertz detection array according to claim 2, characterized in that, The readout circuit of the terahertz detection array includes multiple readout links. Before the readout circuit of the terahertz detection array enters the working mode, the global control unit calibrates the current feedback instrumentation amplifier and programmable gain amplifier of each readout link in sequence. The first DAC code register of each readout link is connected to the global control unit through the same first DAC code bus, and the second DAC code register of each readout link is connected to the global control unit through the same second DAC code bus. After determining all target DAC control codes, the global control unit sends the corresponding target DAC control codes to the corresponding DAC code registers through the first DAC code bus and the second DAC code bus, and sends the corresponding latch clock signal to each DAC code register to trigger the corresponding DAC code register to latch the corresponding target DAC control code.

5. The readout circuit of the terahertz detection array according to claim 1, characterized in that, The instrumentation amplifier body includes a first chopper switch, a second chopper switch, a third chopper switch, a first input stage transconductance Gm1, a feedback stage transconductance Gm2, and a first high-gain amplification unit. The first high-gain amplification unit includes a first-stage gain and a second-stage gain. The third chopper switch is located between the first-stage gain and the second-stage gain. The second-stage gain outputs a first positive output voltage Voutp1 and a first negative output voltage Voutn1. The first input terminal of the first chopper switch is connected to a reference common-mode voltage VCM through a first switch. The first input terminal of the first chopper switch is also connected to a first positive input voltage Vinp1 through a second switch. The second input terminal of the first chopper switch is connected to a first negative input voltage Vinn1 through a third switch. The second input terminal of the first chopper switch is also connected to the reference common-mode voltage VCM through a fourth switch. The voltage VCM; the two output terminals of the first chopper switch are respectively connected to the two input terminals of the first input stage transconductance Gm1; the first input terminal of the second chopper switch is connected to the reference common-mode voltage VCM through the fifth switch, the first input terminal of the second chopper switch is also connected to the positive feedback voltage Vfbp through the sixth switch, the second input terminal of the second chopper switch is connected to the negative feedback voltage Vfbn through the seventh switch, and the second input terminal of the second chopper switch is also connected to the reference common-mode voltage VCM through the eighth switch; the two output terminals of the second chopper switch are respectively connected to the two input terminals of the feedback stage transconductance Gm2; the two output terminals of the feedback stage transconductance Gm2 are respectively connected to the two input terminals of the first stage gain, and the two output terminals of the first input stage transconductance Gm1 are also respectively connected to the two input terminals of the first stage gain; The first-stage gain includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The sources of the seventh and eighth transistors are both connected to ground voltage. The seventh and eighth transistors share a common gate. The drain of the seventh transistor is connected to the source of the ninth transistor. The drain of the eighth transistor is connected to the source of the tenth transistor. The tenth and ninth transistors share a common gate. The sources of the ninth and tenth transistors serve as the two input terminals of the first-stage gain. The drains of the ninth and tenth transistors serve as the two output terminals of the first-stage gain. The sources of the thirteenth and fourteenth transistors are both connected to the power supply voltage. The thirteenth and fourteenth transistors share a common gate. The drain of the thirteenth transistor is connected to the source of the eleventh transistor. The drain of the fourteenth transistor is connected to the source of the twelfth transistor. The eleventh and twelfth transistors share a common gate. The drain of the ninth transistor is connected to the drain of the eleventh transistor. The drain of the tenth transistor is connected to the drain of the twelfth transistor. The first preset node is the drain of the thirteenth transistor or the drain of the fourteenth transistor.

6. The readout circuit of the terahertz detection array according to claim 5, characterized in that, The gain amplifier body includes a fourth chopper switch, a fifth chopper switch, a fourth input stage transconductance Gm4, a second high-gain amplification unit, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a thirteenth switch, and a fourteenth switch. The second high-gain amplification unit includes a third-stage gain and a fourth-stage gain. The fifth chopper switch is located between the third-stage gain and the fourth-stage gain. The fourth-stage gain outputs a second positive output voltage Voutp2 and a second negative output voltage Voutn2. The first input terminal of the fourth chopper switch is connected to the second positive input voltage Vinp2 through the sixth resistor. The second positive input voltage Vinp2 is the first positive output voltage Voutp1. The second input terminal of the fourth chopper switch... The terminal is connected to the second negative input voltage Vinn2 through the seventh resistor, and the second negative input voltage Vinn2 is the first negative output voltage Voutn1; the two output terminals of the fourth chopper switch are respectively connected to the two input terminals of the fourth input stage transconductance Gm4; the two output terminals of the fourth input stage transconductance Gm4 are respectively connected to the two input terminals of the third stage gain; the eighth resistor and the thirteenth switch are connected in series to the first input terminal of the fourth chopper switch and the output terminal of the fourth stage gain outputting the second negative output voltage Voutn2; the ninth resistor and the fourteenth switch are connected in series to the second input terminal of the fourth chopper switch and the output terminal of the fourth stage gain outputting the second positive output voltage Voutp2. The third-stage gain includes transistors 27, 28, 29, 30, 31, 32, 33, and 34. The sources of transistors 27 and 28 are both connected to ground. Transistors 27 and 28 share a common gate. The drain of transistor 27 is connected to the source of transistor 29. The drain of transistor 28 is connected to the source of transistor 30. Transistors 30 and 29 share a common gate. The sources of transistors 29 and 30 serve as the two input terminals of the third-stage gain. The drains of transistors 29 and 30 serve as the two output terminals of the third-stage gain. The sources of transistors 33 and 34 are both connected to the power supply voltage. Transistors 33 and 34 share a common gate. The drain of transistor 33 is connected to the source of transistor 31. The drain of transistor 34 is connected to the source of transistor 32. Transistors 31 and 32 share a common gate. The drain of transistor 29 is connected to the drain of transistor 31. The drain of transistor 30 is connected to the drain of transistor 32. The second preset node is the drain of the thirty-third transistor or the drain of the thirty-fourth transistor.

7. The readout circuit of the terahertz detection array according to claim 1, characterized in that, The readout circuit of the terahertz detection array also includes a precharge buffer, which is located between the programmable gain amplifier and the incremental analog-to-digital converter; The precharge buffer includes a first source follower, a second source follower, an eleventh switch, a twelfth switch, a ninth switch, and a tenth switch. The input of the first source follower is connected to the positive output of the programmable gain amplifier, the input of the second source follower is connected to the negative output of the programmable gain amplifier, the output of the first source follower is connected to the positive input of the incremental analog-to-digital converter (ADC) via the eleventh switch, the output of the second source follower is connected to the negative input of the ADC via the twelfth switch, the connection between the positive output of the programmable gain amplifier and the positive input of the ADC is controlled by the ninth switch, and the connection between the negative output of the programmable gain amplifier and the negative input of the ADC is controlled by the tenth switch.

8. The readout circuit of the terahertz detection array according to claim 7, characterized in that, The first source follower includes a forty-first transistor, a forty-second transistor, a forty-third transistor, and a first coupling capacitor. The forty-fourth transistor acts as a ninth switch. The gate of the forty-first transistor serves as the input terminal of the first source follower, and the source of the forty-first transistor serves as the output terminal of the first source follower. The drain of the forty-first transistor is connected to the power supply voltage. The source of the forty-second transistor is connected to the drain of the forty-third transistor, and the drain of the forty-second transistor is connected to the source of the forty-first transistor. The gate of the forty-second transistor is connected to a corresponding bias voltage. The gate of the forty-third transistor is connected to the first terminal of the first coupling capacitor, and the second terminal of the first coupling capacitor is connected to the source of the forty-first transistor. The source of the forty-third transistor is connected to ground voltage. The source of the forty-fourth transistor is connected to a corresponding bias voltage. The gate of the forty-fourth transistor receives a third clock signal, and the drain of the forty-fourth transistor is connected to the gate of the forty-third transistor. The forty-first transistor is a native NMOS transistor. The second source follower includes a 51st transistor, a 52nd transistor, a 53rd transistor, and a second coupling capacitor. The 54th transistor acts as the 10th switch. The gate of the 51st transistor serves as the input terminal of the second source follower, and the source of the 51st transistor serves as the output terminal. The drain of the 51st transistor is connected to the power supply voltage. The source of the 52nd transistor is connected to the drain of the 53rd transistor, and the drain of the 52nd transistor is connected to the source of the 51st transistor. The gate of the 52nd transistor is connected to a corresponding bias voltage. The gate of the 53rd transistor is connected to the first terminal of the second coupling capacitor, and the second terminal of the second coupling capacitor is connected to the source of the 51st transistor. The source of the 53rd transistor is connected to ground. The source of the 54th transistor is connected to a corresponding bias voltage. The gate of the 54th transistor receives a third clock signal, and the drain of the 54th transistor is connected to the gate of the 53rd transistor. The 51st transistor is a native NMOS transistor.

9. The readout circuit of the terahertz detection array according to claim 8, characterized in that, The eleventh and twelfth switches are controlled by the fourth clock signal. During the sampling period, the pre-charge buffer first performs a pre-sampling mode and then a precise sampling mode. The pre-sampling mode includes: using a fourth clock signal to control the eleventh and twelfth switches to be in the closed state, using a third clock signal to control the ninth and tenth switches to be in the open state, and the two output signals of the current feedback instrumentation amplifier entering the sampling capacitor inside the incremental analog-to-digital converter after passing through the first source follower and the second source follower, respectively, to pre-charge the sampling capacitor. The precise sampling mode includes: using a fourth clock signal to control both the eleventh and twelfth switches to be in the off state, using a third clock signal to control both the ninth and tenth switches to be in the on state, and the output of the current feedback instrumentation amplifier being directly connected to the input of the incremental analog-to-digital converter. There is a time interval tov between the presampling mode and the precise sampling mode.

10. The readout circuit of the terahertz detection array according to claim 3, characterized in that, The global control unit includes a dynamic comparator and a logic module. The two input terminals of the dynamic comparator are respectively connected to the two output terminals of the instrumentation amplifier body, and the output terminal of the dynamic comparator is connected to the logic module. The method of using a binary search algorithm to determine the first target DAC control code with the best ripple suppression effect includes: during the ripple suppression calibration stage, the logic module controls the first DAC code register to output the first DAC control code based on the logic signal output by the dynamic comparator, and the first redundant segmented current steering DAC outputs compensation current to the first preset node of the instrumentation amplifier body based on the first DAC control code to suppress ripple. The ripple suppression calibration stage includes an initialization and a binary search process. The initialization includes: the logic module clears the first DAC control code to zero, the instrumentation amplifier body switches to open-loop mode, and amplifies the initial ripple using open-loop high gain. The dynamic comparator performs polarity determination on the amplified initial ripple and outputs a logic signal characterizing the determination result to the logic module. The binary search process includes: the logic module iteratively updates the first DAC control code based on the logic signal from high bit to low bit, the number of iterations being equal to the number of bits in the first DAC control code, and dynamically updates the first DAC control code by retaining valid bits and backing up excessive bits, so that the compensation current output by the first redundant segmented current steering DAC gradually approaches the target value for offsetting ripple, and finally obtains the first target DAC control code.

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