High-performance input buffer and memory device having the same

Abstract

We provide a high-performance input buffer and a memory device having the same. [Solution] A method for operating a memory device includes the steps of receiving an input including a command signal, an address signal, and a data signal; sending the command signal or the address signal to a slow buffer; and sending the data signal to a fast buffer.

Description

【Technical Field】 【0001】 This application relates to the field of semiconductor technology, and more particularly, to three-dimensional (3D) memory devices, input buffer structures, and methods of constructing input buffers. 【Background Art】 【0002】 Not-AND (NAND) memory is a non-volatile type of memory that does not require power to retain stored data. As the demand for consumer electronics, cloud computing, and big databases increases, there is a constant need for larger capacity and better performing NAND memory. Since conventional two-dimensional (2D) NAND memory is approaching its physical limits, three-dimensional (3D) NAND memory currently plays an important role. 3D NAND memory uses multiple stacked layers on a single die to achieve higher density, larger capacity, faster performance, lower power consumption, and higher cost efficiency. 【0003】 As the input / output (I / O) speed of NAND devices increases, more static power is consumed during idle cycles. For example, the bus idle current may increase as the I / O speed increases. There is a problem of speeding up the I / O performance while meeting the power consumption requirements in NAND devices. The disclosed systems and methods are directed to solving one or more of the problems described above and other problems. 【Summary of the Invention】 【Means for Solving the Problems】 【0004】 In one aspect of the present disclosure, a method for operating a memory device includes receiving an input including a command signal, an address signal, and a data signal via an input / output (I / O) component, transmitting the command signal or the address signal to a low-speed buffer, and transmitting the data signal to a high-speed buffer. 【0005】 In another aspect of the present disclosure, a memory device includes an I / O component for receiving inputs including command signals, address signals, and data signals; a slow buffer for buffering command signals or address signals; and a fast buffer for buffering data signals. The I / O component is adaptable to transmit command signals or address signals to the slow buffer and data signals to the fast buffer. 【0006】 In another aspect of the present disclosure, a method for operating a memory device includes the steps of receiving an input including a command signal, an address signal, and a data signal; enabling a slow buffer; executing a command cycle and buffering the command signal using the slow buffer, or executing an address cycle and buffering the address signal using the slow buffer; enabling a fast buffer; and executing a data input cycle and buffering the fast signal using the fast buffer. 【0007】 One aspect of this disclosure can be understood by those skilled in the art in light of the description, claims, and drawings of this disclosure. [Brief explanation of the drawing] 【0008】 [Figure 1] This is a cross-sectional view of an exemplary three-dimensional (3D) memory device according to various embodiments of the present disclosure. [Figure 2] This is a block diagram of a 3D memory device according to various embodiments of the present disclosure. [Figure 3] This is a block diagram of high-speed and low-speed routes according to various embodiments of the present disclosure. [Figure 4] This is a timing diagram of the command cycle according to various embodiments of the present disclosure. [Figure 5] This is a timing diagram of the address cycle according to various embodiments of the present disclosure. [Figure 6] This is a timing diagram of the data input cycle according to various embodiments of the present disclosure. [Figure 7] This is a block diagram of a buffer configuration according to various embodiments of the present disclosure. [Figure 8] This diagram shows the timing of the address cycle and data input cycle according to various embodiments of the present disclosure. [Figure 9] This diagram shows the timing of command / address cycles and data input cycles according to various embodiments of the present invention. [Figure 10] This refers to timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 11] This refers to timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 12] This refers to timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 13] This refers to timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 14] This refers to timing including command cycles, address cycles, and data input cycles according to various embodiments of the present invention. [Figure 15] This is a schematic flowchart illustrating methods for buffering input signals according to various aspects of this disclosure. [Figure 16] This is a schematic flowchart illustrating methods for buffering input signals according to various aspects of this disclosure. [Modes for carrying out the invention] 【0009】 The technical solutions in embodiments of the present disclosure are described below with reference to the accompanying drawings. Throughout the drawings, the same or similar reference numerals are used wherever possible when referring to the same or similar parts. It is clear that the embodiments described are only a selection of, and not all, embodiments of the present disclosure. Features in the various embodiments may be interchangeable and / or combined. Other embodiments that can be obtained without ingenuity by those skilled in the art based on embodiments of the present disclosure are within the scope of the present disclosure. 【0010】 Figure 1 schematically shows a cross-sectional view of an exemplary 3D memory device according to an embodiment of the present disclosure. The 3D memory device 100 may be an independently operating discrete memory device. The 3D memory device 100 may be part of a memory system having a plurality of memory devices 100. In some embodiments, the 3D memory device 100 may be coupled to or embedded in a host device (not shown). The host device may include, among many other host devices, computing devices such as mobile phones, smartphones, smartwatches, tablet computers, laptop computers, personal computers, data servers, and workstations. 【0011】 In some cases, the 3D memory device 100 may include a memory array device 110 and peripheral devices 120. The memory array device 110 may include memory cells that form one or more 3D arrays. The peripheral devices 120 may include circuits that include a control circuit for controlling the operation of the 3D memory device 100. In some embodiments, the memory array device 110 and peripheral devices 120 may be manufactured separately and then combined to form a stacked structure as shown in Figure 1. Alternatively, the memory array device 110 and peripheral devices 120 may be integrated as a single device. For example, the peripheral devices 120 may be manufactured first, and then the memory array device 110 may be fabricated on top of the peripheral devices 120, using the peripheral devices 120 as a substrate. In some other embodiments, the memory array device 110 and peripheral devices 120 may be manufactured separately and then mounted side by side on a printed circuit board (PCB). 【0012】 Figure 2 shows a block diagram of a 3D memory device 200 according to an embodiment of the present disclosure. The 3D memory device 200 may include a memory array 210 and a control circuit 212 that functions as a controller for the 3D memory device 200. The memory array 210 may include a 3D array (not shown) of memory cells. The memory cells may include Not-AND (NAND) memory cells, Not-OR (NOR) memory cells, and / or other types of memory cells. In some cases, the memory array 210 may include a 2D array (not shown) of memory cells, including NAND memory cells, NOR memory cells, and / or other types of memory cells. The 3D memory device 200 may further include an input / output (I / O) interface 214, a slow buffer 216, a fast buffer 218, a row decoder 220, and a column decoder 222. In some embodiments, the term “slow” as used herein may refer to a speed lower than 100 megahertz (MHz), and the term “fast” as used herein may refer to a speed of 1 gigahertz (GHz) or higher. In some cases, and in some other cases, “fast” and “slow” may be defined relative to each other, and “fast” may indicate that it is at least an order of magnitude faster than “slow.” That is, a fast buffer may be at least an order of magnitude faster than a slow buffer. The control circuit 212 may perform various functions of the 3D memory device 200. For example, the control circuit 212 may perform read, write, and erase operations. The I / O interface 214, sometimes called an I / O component or I / O connection, may include I / O circuitry for receiving command, address, and data signals to the 3D memory device 200 and for sending data and status information from the 3D memory device 200 to another device (e.g., a host device). The slow buffer 216, also called a slow page buffer, buffers or temporarily stores command / address signals, while the fast buffer 218, also called a fast page buffer, buffers or temporarily stores data signals.The row decoder 220 and column decoder 222 may each decode row address signals and column address signals for accessing the memory array 210. The row decoder 220 and column decoder 222 may also each receive different voltages from a voltage generator circuit (not shown) and transfer the received voltages to selected objects such as word lines or bit lines of the memory array 210. 【0013】 The I / O interface 214 may detect command signals, address signals, and data signals from its inputs. In some embodiments, the I / O interface 214 may send command and / or address signals to a slow buffer 216 and data signals to a fast buffer 218. In some cases, the I / O interface 214 may send command and / or address signals only to the slow buffer 216 and data signals only to the fast buffer 218. In some cases, the control circuit 212 may send command signals, address signals, and data signals to buffers 216 and 218 by sending instructions to the I / O interface 214. The slow buffer 216 may include one or more slow buffers and be configured to receive and buffer command signals, address signals, and / or other signals that do not require fast processing. When the slow buffer 216 includes multiple slow buffers, one of the slow buffers may be used to receive command signals and another slow buffer may be used to store address signals. The fast buffer 218 may include one or more fast buffers and be configured to receive and buffer data signals and / or other signals that require fast processing. 【0014】 In some memory devices, all of the command signal, address signal, and data signal are sent from an I / O interface to a high-speed buffer to facilitate high-speed operation. Thereafter, the high-speed buffer passes the command / address signal to a command / address latch and the data signal to a deserializor. The command / address signal is latched and accepts a command / address sequence having a write enable (WE_n) cycle. The data signal is deserialized and synchronized with a data strobe (DQS) signal (e.g., DQS_t or DQS_c signal) for writing cache data in a high-speed clock cycle. However, the high-speed buffer consumes high static power and requires a high-speed reference bias wake-up process. The data signal requires a high-speed buffer for high-speed operation. For example, the speed of the data signal sent to the buffer may reach at least 1 GHz in some cases. However, for the command / address signal, a speed less than 100 MHz may be sufficient to support the operation in the WE_n cycle in some cases. Therefore, the command / address signal may not require high-speed operation in some cases. A low-speed buffer may achieve sufficient efficiency for the command / address signal in such cases. 【0015】 As shown in FIG. 2, the low-speed buffer 216 is configured to receive and buffer the command and / or address signal, while the high-speed buffer 218 is configured to receive and buffer the data signal. In some embodiments, the command / address signal may be passed only to the low-speed buffer 216, and the data signal may be passed only to the high-speed buffer 218. Since the command / address signal is processed by the low-speed buffer 216, the static power in the idle mode may be reduced compared to a scenario where a high-speed buffer is configured for all input signals. Also, since the command / address signal is processed by the low-speed buffer 216, the active power may also be reduced. Further, while the static power consumption is controlled, the operating frequency of the high-speed buffer 218 may increase and the high-speed performance of the 3D memory device 200 may be improved. 【0016】 FIG. 3 shows a block diagram 300 of a high-speed path and a low-speed path configured to process an input signal for a memory device according to an embodiment of the present disclosure. The high-speed path may be configured to propagate and process data signals, and the low-speed path may be configured to propagate and process command / address signals. The high-speed path may include devices such as a current-mode logic (CML) buffer 310, an amplifier 312, and a deserializator 314. The CML buffer is based on a differential circuit. For example, the CML buffer 310 may receive differential input signals Vinp and Vinn and generate differential output signals Vop and Von. The CML buffer can operate at a low signal voltage and can operate at high speed (e.g., 1 GHz) with a low supply voltage, but draws a high static current and remains in the common mode. The high-speed path may include a plurality of CML buffers (not shown). The amplifier 312 may be, for example, a differential operational amplifier. The differential operational amplifier amplifies the difference between two input signals such as two input voltages. The high-speed path may include a plurality of amplifiers, for example, a plurality of amplifiers 312. The deserializator 314 may include a deserialization circuit that converts serial data into parallel data. The parallel data may be sent to a write cache and temporarily stored in the write cache before being written to the memory array. 【0017】 The low-speed path may include an amplifier 316 and a command / address latch 318. Similar to the amplifier 312, the amplifier 316 may be, for example, a differential operational amplifier. The low-speed path may include a plurality of amplifiers, for example, a plurality of amplifiers 316. The command / address latch 318 may latch the command / address signals transmitted to the row decoder and the column decoder. 【0018】 A metal-oxide-semiconductor field-effect transistor (MOSFET) M1 may be connected to the CML buffer 310 and provide a HighSpeedEnable signal to the CML buffer 310. A MOSFET M2 may be connected to the amplifier 312 and provide a HighSpeedEnable signal to the amplifier 312. A MOSFET M3 may be connected to the CML buffer 310 and provide a reference signal to the CML buffer 310. A MOSFET M4 may be connected to the amplifier 316 and provide a LowSpeedEnable signal to the amplifier 316. As used herein, the term "connected" indicates an electrical connection. 【0019】 Therefore, an input signal received in a memory device may be divided into two parts: one part containing a data signal and the other part containing a command / address signal. The data signal may be transmitted and buffered along a high-speed path, and the command / address signal may be transmitted and buffered along a low-speed path. In some embodiments, the data signal may be transmitted and buffered along only the high-speed path, and the command / address signal may be transmitted and buffered along only the low-speed path. Since the command / address signal is not transmitted along the high-speed path, the static power consumption of the memory device may be controlled when high-speed operation is performed in the memory device. 【0020】 Figure 4 shows schematic timing diagrams of the command cycle of a memory device according to various embodiments of the present disclosure. The command cycle may include command signals such as the chip enable (CE_n) signal, command latch enable (CLE) signal, address latch enable (ALE) signal, WE_n signal, read enable (RE_t) signal, read enable auxiliary (RE_c) signal, DQS_t signal, DQS_c signal, and DQ[7:0] signal. The CE_n signal may be used to select a NAND target. The NAND target may include a set of logic units (LUNs) that share one CE_n signal within a NAND package. tCS is the CE_n setup time, and tCH is the CE_n hold time. The CLE signal may be used to indicate the type of bus cycle (e.g., a command bus cycle, an address bus cycle, or a data bus cycle). The ALE signal may be used to indicate the type of bus cycle (e.g., a command bus cycle, an address bus cycle, or a data bus cycle). tCALS is the CLE and ALE setup time, and tCALH is the CLE and ALE hold time. tCSD is the ALE, CLE, and WE_n hold time from CE_n high. The WE_n signal may be used to control the latching of command, address, and input data. tWP is the WE_n low pulse width. The RE_t signal may be used to enable serial data output. The RE-c signal is a complement to the RE_t signal. The DQS_t signal is the data strobe signal, and the DQS_c signal is a complement to the DQS_t signal. The DQ[7:0] signal is the data I / O signal. tCAS is the command / address DQ setup time, and tCAH is the command / address DQ hold time. 【0021】 Referring to Figure 4, the LowSpeedEnable signal is used to enable the slow buffer for the command cycle. For example, the slow buffer may be enabled at the start of tCS and disabled at the end of tCH. As shown above, the command signal may be passed to the slow buffer and buffered at a slow speed. Therefore, the static power consumption of the memory device may be reduced compared to when the command signal is buffered using a fast buffer. 【0022】 Figure 5 shows a schematic timing diagram 500 of the address cycle of a memory device according to various embodiments of the present disclosure. The address cycle may have command signals similar to those of the command cycle in Figure 4, such as the CE_n signal, CLE signal, ALE signal, WE_n signal, RE_t signal, RE_c signal, DQS_t signal, DQS_c signal, and DQ[7:0] signal. The LowSpeedEnable signal may be used to enable a slow buffer for the address cycle. For example, the slow buffer may be enabled at the start of tCS and disabled at the end of tCH. As shown above, the address signal may be passed to the slow buffer and buffered at a slow speed. Therefore, the static power consumption of the memory device may be reduced compared to when the address signal is buffered using a fast buffer. 【0023】 In some cases, the idle mode of a memory device may be implemented only when the slow buffer is enabled and the fast buffer is in standby or off mode. In some embodiments, command or address cycles are executed using only the slow buffer; that is, command / address signals are buffered using only the slow buffer. Consequently, lower active power and lower static power may be achieved compared to buffering command / address signals using the fast buffer. 【0024】 Figure 6 shows a schematic timing diagram 600 of the data input cycle of a memory device according to various embodiments of the present disclosure. The data input cycle may have command signals such as the CE_n signal, CLE signal, ALE signal, WE_n signal, RE_t signal, RE_c signal, DQS_t signal, DQS_c signal, and DQ[7:0] signal. tCS1 is the CE_n setup time for data bursts with the termination resistor (ODT) disabled, and tCS2 is the CE_n setup time with the DQS / DQ[7:0] ODT enabled. tCALS are the CLE and ALE setup times, while tCALS2 are the CLE and ALE setup times when the ODT is enabled. tCD is the CE_n setup time from when CE_n was high for longer than 1 microsecond until DQS (DQS_t) went low. tDBS is the DQS (DQS_t) high and RE_n (RE_t) high setup up to ALE, CLE, and CE_n low during a data burst. tCDQSS is the DQS setup time for the start of data entry. tWPRE is the DQS write preamble, and tWPRE2 is the DQS write preamble when ODT is enabled. tDQSH is the DQS high-level width, while tDQSL is the DQS low-level width. tDSC is the DQS cycle time. tDS is the data setup time. tDH is the data hold time. tWPST is the DQS write postamble. tWPSTH is the DQS write postamble hold time. tCDQSH is the DQS hold time for the end of the data entry burst. D0~D N is the data bytes / word to be written to the addressed page. 10h is the second cycle of the page program command. 【0025】 Referring to Figure 6, the HighSpeedEnable signal may be used to enable a high-speed buffer for data input cycles. For example, the high-speed buffer may be enabled when ODT is enabled and disabled when ODT is disabled. As illustrated above, data input signals may be passed to the high-speed buffer and buffered at high speed. In idle mode, the high-speed buffer may be disabled. Therefore, the static power consumption of the memory device in idle mode may be reduced compared to when the high-speed buffer remains enabled in idle mode. 【0026】 Figure 7 shows a schematic block diagram 700 of a buffer configuration of a memory device according to an embodiment of the present disclosure. The buffer configuration may include a high-speed buffer 710, a low-speed buffer 712, an input buffer control 714, a reference bias 716, a high-speed deserializer 718, and a command / address latch 720. The input buffer control 714 may use the ChipEnable signal to select a NAND target and use the DDR_DINCYCLE signal to detect a command signal, an address signal, and a data signal from the input signal, respectively. When the input signal is a data signal, the input buffer control 714 may generate a HighSpeedEnable signal and send the HighSpeedEnable signal to the high-speed buffer 710. The HighSpeedEnable signal enables the high-speed buffer 710. When the input signal is a command signal or an address signal, the input buffer control 714 may generate a LowSpeedEnable signal and send the LowSpeedEnable signal to the low-speed buffer 712. The LowSpeedEnable signal enables the low-speed buffer 712. The ChipEnable signal may enable a reference bias 716 that provides a reference signal to the fast buffer 710 when the fast buffer 710 is enabled. The input signals include command signals, address signals, and / or data signals, which may include differential data or single-ended data. Command / address signals are sent to the slow buffer 712. Data signals are sent to the fast buffer 710. Furthermore, the fast buffer 710 may pass data signals to the fast deserializer 718, and the slow buffer 712 may forward command / address signals to the command / address latch 720. In some embodiments, command / address signals are sent only to the slow buffer 712 for the purpose of reducing the active and static power of the memory device. In some cases, the idle mode of the memory device may be enabled only when the fast buffer 710 is disabled for the purpose of reducing the static power of the memory device. Thus, the slow buffer may be enabled in idle mode. 【0027】 Figure 8 shows schematic timing diagram 800 of the address cycle and subsequent data input cycle of a memory device according to various embodiments of the present disclosure. In some cases, the address cycle may be replaced by a command cycle. As shown in Figure 8, the address cycle and data input cycle may have command signals such as the CE_n signal, CLE signal, ALE signal, WE_n signal, RE_t signal, RE_c signal, DQS_t signal, DQS_c signal, and DQ[7:0] signal. The LowSpeedEnable signal may be used to enable a low-speed buffer for the address cycle. The HighSpeedEnable signal may be used to enable a high-speed buffer for the data input cycle. As illustrated above, the address signal may be passed to a low-speed buffer and buffered by low-speed operation, and the data input signal may be passed to a high-speed buffer and buffered by high-speed operation. For example, the low-speed buffer may be enabled at the start of tCS and deactivated at the end of tCH. On the other hand, the high-speed buffer may be enabled when ODT is enabled and deactivated when ODT is deactivated. In the idle mode of a memory device, while the high-speed buffer may be disabled, the slow buffer may be enabled to reduce static power consumption. 【0028】 Referring to Figure 8, the memory device controller may, for example, first detect the address signal. Furthermore, the slow buffer may be enabled by the controller. The address signal may be sent to the slow buffer, and the address cycle may be performed using the slow buffer. After the address cycle is complete and the slow buffer is deactivated, the controller may detect the data signal. Subsequently, the fast buffer may be enabled by the controller when the ODT is enabled, and the data signal may be sent to the fast buffer. The data input cycle may be performed using the fast buffer. When the ODT is deactivated, the fast buffer is deactivated, and the data input cycle ends. Therefore, the fast buffer is deactivated when the address cycle and / or command cycle are performed. The fast buffer is enabled only when the data input cycle is performed, or when the data input cycle is performed in page program operation. Therefore, the active and static power consumption of the memory device may be reduced compared to a scenario where the fast buffer is used to store command / address data. 【0029】 Figure 9 shows schematic timing diagrams of slow command / address cycles and fast data input cycles of a memory device according to various embodiments of the present disclosure. The memory device includes a controller for controlling specific operations. As shown in Figure 9, operations may include command signals such as the CE_n signal, CLE signal, ALE signal, DQS_t signal, DQ[7:0] signal, WE_n signal, LowSpeedEnable signal, and HighSpeedEnable signal. Other command signals are omitted in Figure 9 for simplification of the diagram. As illustrated above, the LowSpeedEnable signal is used to enable a slow buffer for slow command / address cycles, while the HighSpeedEnable signal is used to enable a fast buffer for fast data input cycles. Command / address signals may be sent to a slow buffer and buffered by slow operations, and data input signals may be sent to a fast buffer and buffered by fast operations. 【0030】 Referring to Figure 9, the LowSpeedEnable signal may be high before time t1 and during the period between t1 and t2, and the HighSpeedEnable signal may be low. Therefore, during this period, the controller may enable the slow buffer and disable the fast buffer. The controller may use the DQ[7:0] signal to obtain the command / address signal and the WE_n signal to control the latching of the command / address signal. The command / address signal may be latched to the slow buffer in the slow command / address cycle. 【0031】 At time t2, when the command / address cycle is complete and the CE_n / CLE / ALE / DQS_t signals (i.e., the CE_n signal, CLE signal, ALE signal, and DQS_t signal) are low, the controller may activate the high-speed mode by setting the HighSpeedEnable signal high and deactivate the low-speed mode by setting the LowSpeedEnable signal low. That is, the high-speed buffer may be enabled and the low-speed buffer may be disabled. The controller may then perform a high-speed data input cycle in the high-speed buffer. At time t3, the controller may set the HighSpeedEnable signal low and the LowSpeedEnable signal high. The high-speed buffer may then be disabled, the low-speed buffer may be enabled, and another command / address cycle may be performed. 【0032】 Figure 10 shows a schematic timing diagram 1000 for a memory device, including address cycles, command cycles, and data input cycles, according to various embodiments of the present disclosure. When the I / O interface of the memory device receives input, the controller of the memory device may cause the I / O interface to pass the command / address signals of the input to a slow buffer and the data signals to a fast buffer. The command signals, address signals, and data signals may be transmitted sequentially from the I / O interface. The command cycle, address cycle, and data input cycle may be executed sequentially. For example, at time t1, the controller may activate the slow buffer and execute the address cycle. The address cycle may end at time t2 when the slow buffer is deactivated. Then, at time t3, the controller may activate the fast buffer and execute the data input cycle. In some embodiments, the fast mode is activated and the fast buffer is activated when the CE_n / CLE / ALE / DQS_t signal is low. At time t4, the controller may deactivate the fast buffer and end the data input cycle. At time t5, the controller may re-enable the slow buffer and execute a command cycle, which may terminate when the slow buffer is disabled at time t6. Thus, address and command cycles may be executed using the slow buffer. Furthermore, when address and command cycles are executed, the fast buffer may be disabled to reduce power consumption in active mode. The fast buffer may be enabled only when a data input cycle is executed. 【0033】 Figure 11 shows a schematic timing diagram 1100 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, a slow buffer, a fast buffer, and a controller that controls the operation of the memory device. After the I / O connection receives input, the command / address signals of the input may be sent to the slow buffer, and the data signals may be sent to the fast buffer. The command signals, address signals, and data signals may be sent sequentially or in parallel from the I / O connection. The command cycles, address cycles, and data input cycles may be performed sequentially or in parallel by the controller. For example, at time t1, the controller may enable the slow buffer and perform a first address cycle. The first address cycle may end at time t2 when the slow buffer is deactivated. The controller may then enable the fast buffer and perform a data input cycle at time t3. In some embodiments, the fast buffer is enabled when the CE_n / CLE / ALE / DQS_t signal is low. During the data input cycle, the I / O connection may receive additional address signals. At time t4, the controller may enable the slow buffer and execute a second address cycle. The second address cycle and the data input cycle are performed in parallel because the two cycles fall within the same period from t4 to t5. During the period from t4 to t5, address and data signals may be sent simultaneously from the I / O connection to the slow buffer and the fast buffer. That is, in some embodiments, address signals (or command signals) and data signals may be sent in parallel from the I / O connection. The second address cycle may end at time t5 when the slow buffer is disabled. At time t6, the controller may disable the fast buffer and stop the data input cycle. At time t7, the controller may re-enable the slow buffer and execute a command cycle, which may end when the slow buffer is disabled at time t8.Therefore, address and command cycles may be executed using only slow buffers. Furthermore, fast buffers may be enabled only when data input cycles are being executed. 【0034】 Figure 12 shows a schematic timing diagram 1200 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, a slow buffer, a fast buffer, and a controller that controls the operation of the memory device. After the I / O connection receives input, the command / address signals of the input may be sent to the slow buffer, and the data signals may be sent to the fast buffer. In some embodiments, the I / O connection may represent an I / O interface and simultaneously receive command signals, address signals, and data signals, and simultaneously forward the command signals, address signals, and data signals to different destinations (e.g., different buffers). At time t1, the controller may enable the slow buffer and perform a first address cycle. The first address cycle may end at time t2, when the slow buffer is deactivated. Furthermore, at time t3, the controller may enable the fast buffer and perform a data input cycle. In some embodiments, the fast buffer is enabled when the CE_n / CLE / ALE / DQS_t signal is low. During the data input cycle, the I / O connection may receive address and / or command signals. For example, at time t4, the controller may enable the slow buffer and use it to perform a second address cycle. The second address cycle may end at time t5 when the slow buffer is disabled. At time t6, the controller may re-enable the slow buffer and use it to perform a command cycle. At time t7, the slow buffer may be disabled and the command cycle may end. At time t8, the controller may disable the fast buffer and stop the data input cycle. Thus, the address and command cycles may be performed using only the slow buffer. The fast buffer may be enabled only when the data input cycle is being performed. 【0035】 Figure 13 shows a schematic timing diagram 1300 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, one or more slow buffers, a fast buffer, and a controller that controls the operation of the memory device. The I / O connection may, in response to receiving input, forward the command / address signals of the input to one or more slow buffers, and the data signals of the input to the fast buffer, respectively. In some embodiments, the I / O connection may receive command signals, address signals, and data signals simultaneously, and may send the command, address, and data signals simultaneously to different destinations (e.g., different buffers, respectively). At time t1, the controller may activate one or more slow buffers and perform address cycles and command cycles. The address and command cycles may be performed simultaneously or in parallel by the controller. During the period from t1 to t2, address signals and command signals may be sent simultaneously or in parallel from the I / O connection to one or more slow buffers. For example, address and command signals may be transmitted in parallel from the I / O connection to the first and second slow buffers during the period from t1 to t2. The address and command cycle may end at time t2 when one or more slow buffers are disabled. At time t3, the controller may enable the fast buffer and execute the data input cycle. At time t4, the controller may disable the fast buffer and terminate the data input cycle. Thus, the address and command cycle may be executed using the slow buffer. Also, the fast buffer may be enabled only when the data input cycle is executed. 【0036】 Figure 14 shows a schematic timing diagram 1400 for performing address cycles, command cycles, and data input cycles for a memory device according to various embodiments of the present disclosure. The memory device may include an I / O connection, one or more slow buffers, a fast buffer, and a controller that controls the operation of the memory device. The I / O connection may, in response to receiving input, forward the command / address signals of the input to one or more slow buffers and the data signals of the input to the fast buffer, respectively. In some embodiments, the I / O connection may simultaneously receive command signals, address signals, and data signals and simultaneously send the command, address, and data signals to different destinations, respectively. At time t1, the controller may activate one or more slow buffers and perform a first address cycle and command cycle. The first address cycle and command cycle may be performed simultaneously by the controller. The first address cycle and command cycle may end at time t2 when one or more slow buffers are deactivated. At time t3, the controller may activate the fast buffer and perform a data input cycle. During the period of the data input cycle, the I / O connection may receive additional address signals. At time t4, the controller may enable one of the slow buffers and execute a second address cycle. Similarly, if additional command signals are received via the I / O connection, the controller may execute an additional command cycle between t3 and t6. The second address cycle may end at time t5 when one of the slow buffers is disabled. At time t6, the controller may disable the fast buffer and end the data input cycle. Thus, the address and command cycles may be executed using the slow buffers. Furthermore, the fast buffer may be enabled only when the data input cycle is executed. 【0037】 Figure 15 shows a schematic flowchart 1500 illustrating a method for buffering input signals to a memory device according to embodiments of the present disclosure. The memory device may include a controller, an I / O interface, a slow buffer, and a fast buffer. The controller controls the operation of the memory device. 【0038】 At 1510, the I / O interface receives an input. The input may include command signals, address signals, and data signals. The I / O interface may receive signals sequentially or in parallel. At 1520, the I / O interface detects command signals, address signals, and data signals from the input. 【0039】 In 1530, the I / O interface sends command / address signals to a slow buffer. Alternatively, the controller may prompt the I / O interface to send command / address signals to the slow buffer. In some embodiments, the I / O interface may send command signals to the slow buffer, and the controller may execute one or more command cycles over a period of time. The I / O interface may send address signals to the slow buffer, and the controller may execute one or more address cycles over a different period of time. When a command or address cycle is executed, the slow buffer is activated and used to buffer the command or address signals. In some cases, when a command or address cycle is executed, the command or address signals are buffered using only the slow buffer. 【0040】 In 1540, the I / O interface sends data signals to a fast buffer. Alternatively, the controller may prompt the I / O interface to send data signals to the fast buffer. In some embodiments, the I / O interface may send data signals to the fast buffer, and the controller may perform one or more data input cycles over a period of time. When a data input cycle is performed, the fast buffer is activated and used to buffer data signals. In some embodiments, the fast buffer may be activated only when a data input cycle is performed. 【0041】 Figure 16 shows a schematic flowchart 1600 illustrating a method for buffering input signals in a memory device according to an embodiment of the present disclosure. The memory device may include a controller, an I / O interface, a slow buffer, and a fast buffer. The controller controls the operation of the memory device. 【0042】 In the 1610, the I / O interface receives inputs. These inputs may include command signals, address signals, and data signals. The I / O interface passes command and address signals to a slow buffer and data signals to a fast buffer. 【0043】 In 1620, the controller enables a slow buffer and executes command and address cycles to buffer command / address signals. After the slow buffer is enabled, for example, the controller executes a command cycle, and then an address cycle. That is, the command and address cycles may be executed sequentially. Alternatively, the command and address cycles may be executed in parallel, i.e., the command and address cycles may be performed over the same period. In some embodiments, the command and / or address cycles may be initiated only when the slow buffer is enabled. In some cases, the command and / or address cycles may be executed only via the slow buffer. 【0044】 In 1630, the controller enables the fast buffer and executes a data input cycle to buffer the data signal. In some embodiments, the controller activates fast mode and enables the fast buffer when the CE_n / CLE / ALE / DQS_t signal is low. After the fast buffer is enabled, the controller may execute one or more data input cycles. The command or address cycle and the data input cycle may be executed sequentially. For example, a command cycle or address cycle may be executed in a first period. A data input cycle may be executed in a second period following the end of the first period. Alternatively, the command or address cycle and the data input cycle may be executed in parallel. For example, a command cycle or address cycle may be executed in a first period. A data input cycle may be executed in a second period overlapping with the first period. In some embodiments, the fast buffer may be enabled only when a data input cycle is executed. 【0045】 Therefore, slow buffers and fast buffers may be used to buffer input signals. Command / address signals may be sent to the slow buffer. Data signals may be sent to the fast buffer. Active power and static power may be reduced compared to when the fast buffer is used to buffer command, address, and data signals. 【0046】 While the principles and implementations of this disclosure have been illustrated by using specific embodiments herein, the above description of embodiments is intended solely to aid in understanding this disclosure. Furthermore, additional embodiments may be formed by combining features of the different embodiments described above. Those skilled in the art may modify specific implementations and scopes in accordance with the spirit of this disclosure. Therefore, the contents of this specification should not be construed as limitations of this disclosure. 【0047】 [1] A method for operating a memory device, A step of receiving an input via an input / output (I / O) component, wherein the input includes a command signal, an address signal, and a data signal. The steps include sending the command signal or the address signal to a slow buffer, A method comprising the step of transmitting the data signal to a high-speed buffer. [2] The method according to [1], further comprising the step of sending the command signal or the address signal only to the slow buffer. [3] The step of enabling the slow buffer, The method according to [1], further comprising the steps of executing a command cycle and buffering the command signal using the slow buffer, or executing an address cycle and buffering the address signal using the slow buffer. [4] The method according to [3], further comprising the step of executing the command cycle using only the slow buffer or executing the address cycle using only the slow buffer. [5] The step of enabling the high-speed buffer, The method according to [1], further comprising the steps of performing a data input cycle and buffering the data signal using the high-speed buffer. [6] The method according to [5], wherein the high-speed buffer is activated only when the data input cycle is being performed. [7] The method according to [1], wherein the steps of transmitting the command signal or the address signal to the slow buffer and transmitting the data signal to the fast buffer are performed sequentially. [8] The method according to [1], wherein the steps of transmitting the command signal or the address signal to the slow buffer and transmitting the data signal to the fast buffer are performed in parallel. [9] The method according to [1], further comprising the step of starting idle mode only when the fast buffer is disabled.

[10] The method according to [1], further comprising the step of detecting the command signal, the address signal, and / or the data signal from the input.

[11] The method according to [1], wherein the high-speed buffer is faster than the low-speed buffer by a predetermined coefficient.

[12] A memory device, An input / output (I / O) component for receiving input, wherein the input includes a command signal, an address signal, and a data signal. A slow buffer for buffering the command signal or the address signal, The system includes a high-speed buffer for buffering the aforementioned data signals, A memory device in which the I / O components are adaptable to transmit the command signal or the address signal to the slow buffer and the data signal to the fast buffer.

[13] A controller for controlling the memory device, which is coupled to the I / O component, The command signal or the address signal is transmitted only to the slow buffer. The memory device according to

[12] further comprises a controller configured to transmit the data signal only to the high-speed buffer.

[14] The controller is Enable the aforementioned slow buffer, The memory device described in

[13] is further configured to execute a command cycle and buffer the command signal using the slow buffer, or to execute an address cycle and buffer the address signal using the slow buffer.

[15] The controller is The memory device according to

[14] , further configured to execute the command cycle using only the slow buffer, or to execute the address cycle using only the slow buffer.

[16] The controller is Enable the aforementioned high-speed buffer, A memory device according to

[13] , further configured to perform a data input cycle and to buffer the data signal using the high-speed buffer.

[17] The high-speed buffer is enabled only when the data input cycle is performed, as described in

[16] .

[18] The controller is The memory device described in

[13] is further configured to control the memory device so that it enters idle mode only when the high-speed buffer is disabled.

[19] The memory device according to

[12] , further comprising input buffer control for detecting the command signal, the address signal, and / or the data signal from the input.

[20] The memory device according to

[12] , further comprising a three-dimensional (3D) NAND memory device.

[21] The memory device according to

[12] , wherein the high-speed buffer is faster than the low-speed buffer by a predetermined coefficient.

[22] A method for operating a memory device, The steps include receiving an input that includes a command signal, an address signal, and a data signal, The steps include enabling a slow buffer and using the slow buffer to execute a command cycle and buffer the command signal, or to execute an address cycle and buffer the address signal, A method comprising the steps of enabling a high-speed buffer, performing a data input cycle, and buffering a high-speed signal using the high-speed buffer.

[23] The method of

[22] , further comprising the step of performing the command cycle or the address cycle using only the slow buffer.

[24] The method of

[22] , further comprising the step of sending the command signal or the address signal only to the slow buffer.

[25] The method according to

[22] , further comprising the step of transmitting the data signal to the high-speed buffer.

[26] The method according to

[22] , wherein the high-speed buffer is enabled only when the data input cycle is being performed.

[27] The method according to

[22] , wherein the command cycle or the address cycle and the data input cycle are executed sequentially.

[28] The method according to

[22] , wherein the command cycle or the address cycle and the data input cycle are performed in parallel.

[29] The method according to

[22] , further comprising the step of starting idle mode only when the fast buffer is disabled.

[30] The method according to

[22] , further comprising the step of detecting the command signal, the address signal, and / or the data signal from the input.

[31] The method according to

[22] , wherein the high-speed buffer is faster than the low-speed buffer by a predetermined coefficient. [Explanation of symbols] 【0048】 100 3D memory devices 110 Memory Array Devices 120 Peripheral Devices 200 3D memory devices 210 memory array 212 Control circuits 214 Input / Output (I / O) Interfaces 216 Slow buffer 218 High-speed buffer 220-line decoder 222-row decoder 300 Block Diagram 310 Current-mode logic (CML) buffer 312 Amplifier 314 Deserializer 316 Amplifier 500 Schematic Timing Diagram 600 Schematic Timing Diagram 700 Schematic Block Diagram 710 High-speed buffer 712 Slow buffer 714 Input Buffer Control 716 Reference Bias 718 High-speed deserializer 720 Command / Address Latch 800 Schematic Timing Diagram 900 Schematic Timing Diagram 1000 Schematic Timing Diagram 1100 Schematic Timing Diagram 1200 Schematic Timing Diagram 1300 Schematic Timing Diagram 1400 Schematic Timing Diagram 1500 Outline Flowchart 1600 Outline Flowchart

Claims

[Claim 1] Non-volatile memory device, A first pin configured to receive a command signal or an address signal, A second pin configured to receive a data signal, A first buffer coupled to the first pin, A second buffer coupled to the second pin, An input buffer controller coupled to the first buffer and the second buffer, The first buffer is activated during a first period in a command cycle or address cycle to buffer the command signal or the address signal. The second buffer is activated during a second period in the data input cycle to buffer the data signal. It is configured in such a way, At least a portion of the second period overlaps with the first period. Input buffer controller, A non-volatile memory device equipped with the following features. [Claim 2] The aforementioned input buffer controller is The second buffer is invalidated when the aforementioned data input cycle ends. The non-volatile memory device according to claim 1, further configured as follows. [Claim 3] The non-volatile memory device according to claim 1, wherein the second buffer is dedicated to buffering the data signal. [Claim 4] The non-volatile memory device according to claim 1, wherein the first buffer is enabled solely for buffering the command signal or the address signal. [Claim 5] The aforementioned input buffer controller is Outputs a first enable signal and a second enable signal. The non-volatile memory device according to claim 1, further configured as follows. [Claim 6] The non-volatile memory device according to claim 5, wherein the first buffer is activated by the first enable signal, and the second buffer is activated by the second enable signal. [Claim 7] The second buffer mentioned above is A current-mode logic (CML) circuit coupled to the second pin, A transistor coupled to the CML circuit and configured to receive the second enable signal, A non-volatile memory device according to claim 5, comprising: [Claim 8] The non-volatile memory device according to claim 7, further comprising a deserializer coupled to the CML circuit. [Claim 9] The non-volatile memory device according to claim 1, wherein the first buffer is enabled to buffer the command signal or the address signal at a first speed, and the second buffer is enabled to buffer the data signal at a second speed faster than the first speed. [Claim 10] The non-volatile memory device according to claim 9, wherein the first speed is less than 1 gigahertz (GHz). [Claim 11] The non-volatile memory device according to claim 1, wherein the second buffer is activated when the termination resistor (ODT) is activated. [Claim 12] The non-volatile memory device according to claim 1, wherein the second buffer is disabled when the termination resistor (ODT) is disabled. [Claim 13] The aforementioned input buffer controller is When the chip enable signal is at a low level, the first buffer is enabled to buffer the command signal. The non-volatile memory device according to claim 1, further configured as follows. [Claim 14] Non-volatile memory device, A memory array comprising an array of memory cells, The memory array is coupled, A first buffer connected to the first pin, A second buffer connected to the second pin, A peripheral circuit comprising the following: the first buffer is enabled to buffer a command signal or address signal received from the first pin, and the second buffer is enabled to buffer a data signal received from the second pin. A non-volatile memory device equipped with the following features. [Claim 15] The aforementioned peripheral circuitry is An input buffer controller configured to output a first enable signal and a second enable signal. Furthermore, The non-volatile memory device according to claim 14, wherein the first buffer is activated by the first enable signal, and the second buffer is activated by the second enable signal. [Claim 16] The non-volatile memory device according to claim 14, wherein the first buffer is enabled only for buffering the command signal or the address signal, and the second buffer is enabled only for buffering the data signal. [Claim 17] A method for operating a non-volatile memory device, The steps include: activating a first buffer during a first period in a command cycle or address cycle to buffer a command signal or address signal received from a first pin; A step of enabling a second buffer during a second period in a data input cycle to buffer the data signal received from a second pin, wherein at least a portion of the second period overlaps with the first period. Methods that include... [Claim 18] The step of invalidating the second buffer when the aforementioned data input cycle ends. The method according to claim 17, further comprising: [Claim 19] A step of outputting an active enable signal, wherein the second buffer is activated by the active enable signal. The method according to claim 17, further comprising: [Claim 20] Step to start idle mode only when the second buffer is disabled. The method according to claim 17, further comprising:

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