Semiconductor devices and motor control systems

Abstract

This improves the control accuracy when a controller controls equipment via a semiconductor device. [Solution] The semiconductor device includes a timer control circuit (timer) and an AD converter (ADC) connected to a sensor that obtains operation-related information of the device. Based on the ADC output, the device generates a PWM signal using the periodic signal of the timer. After receiving an AD conversion start request signal (ADR signal), the ADC starts AD conversion in synchronization with the most recent AD synchronization signal. The timer includes a phase synchronization counter, a timer phase register, and an AD synchronization phase register that are started when the device is started. When the phase synchronization counter value and the timer phase register value match, the timer outputs a timer phase signal which is the basis for starting the generation of the periodic signal and the ADR signal. When the counter value and the AD synchronization phase register value match, the timer outputs an AD synchronization phase signal which is the basis for starting the generation of the AD synchronization signal, controlling the phase difference between the ADR signal and the AD synchronization signal to be constant regardless of the device startup timing.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and can be suitably used, for example, in a semiconductor device including an AD converter and a motor control system using the semiconductor device.

Background Art

[0002] A method of controlling the operation of a device using a semiconductor device is known. The device is, for example, a motor. Such a control method is described in, for example, Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When controlling the above-described device using a semiconductor device including an AD converter for acquiring information related to the operation of the device, one of the problems is to improve the control accuracy.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, the semiconductor device has a phase-locked counter that starts counting with the startup of the semiconductor device. The semiconductor device uses the value of the phase-locked counter to control the timing of starting the generation of various signals so that the phase difference between the AD conversion start request signal and the AD conversion synchronization signal becomes constant regardless of the timing of starting up the semiconductor device.

Effects of the Invention

[0007] According to the above embodiment, when controlling the device using a semiconductor device equipped with an AD converter for acquiring information related to the operation of the device, the control accuracy can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This figure shows an example of the basic configuration of a motor control system. [Figure 2] This figure shows the timing charts for major signals and processes in semiconductor devices. [Figure 3] This figure shows an example of the configuration of circuit and functional blocks in the main part of a standard semiconductor device. [Figure 4] This timing chart shows an example of an ideal latency Da. [Figure 5] This is a timing chart representing the first example of actual latency Da. [Figure 6] This is a timing chart showing a second example of actual latency Da. [Figure 7] This figure shows an example of the configuration of the circuit and functional blocks in the main part of the semiconductor device according to the first embodiment. [Figure 8] This figure shows an example of a timing chart for each signal in a semiconductor device according to the first embodiment. [Figure 9] This figure shows an example of the configuration of the circuit and functional blocks in the main part of the semiconductor device according to the second embodiment. [Figure 10] This figure shows an example of a timing chart for each signal in a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0009] The embodiments will now be described. First, the basic configuration, function, and operation of the motor control system will be explained, followed by a description of the inventors' research process. After that, the embodiments proposed by the inventors will be described.

[0010] In this specification, the rotation, amount of rotation, rotational angular position, and rotational speed of the rotating body, i.e., the rotor, in a motor are also simply referred to as the motor's rotation, amount of rotation, rotational angular position, and rotational speed, respectively. Furthermore, in this specification, the phase of various signals is, in principle, a relative phase with respect to the phase of the periodic signal, i.e., the carrier, used to generate the PWM control signal. In this specification, the rotational angular position of the rotor is also referred to as the rotor position, and the rotational speed of the rotor is also referred to as the rotor speed. In addition, the same reference numerals are used for the same or corresponding components in each embodiment, and repeated explanations are omitted except where necessary.

[0011] (Basic configuration, function, and operation of a motor control system) A motor control system is known in which a controller controls the operation of a motor via a semiconductor device. Here, we will describe the basic configuration, function, and operation of such a motor control system as an example.

[0012] Figure 1 shows an example of the basic configuration of a motor control system. As shown in Figure 1, the motor control system 1 includes, for example, a controller 2, a semiconductor device 3, an inverter 4, and a motor 5.

[0013] Controller 2 is located outside of semiconductor device 3 and inputs instruction information representing instructions related to the rotation of motor 5 to semiconductor device 3. These instructions include, for example, acceleration, deceleration, and speed maintenance of the motor 5's rotor. Controller 2 is, for example, a higher-level controller relative to semiconductor device 3. Based on the input instruction information, semiconductor device 3 generates a PWM (Pulse Width Modulation) control signal and inputs it to inverter 4. The PWM control signal is also called a PWM signal, PWM pulse, or PWM control pulse.

[0014] The inverter 4 supplies current to the motor 5 based on the input PWM control signal. The inverter 4 controls the output current, for example, by turning on and off a power switching device by PWM control and supplies the current to the motor 5. The power switching device is, for example, an IGBT (Insulated Gate Bipolar Transistor). The motor 5 is driven according to the supplied current, and the amount of rotation, rotation angle, rotation speed, etc. of the rotor in the motor 5 are controlled. The motor 5 is, for example, a DC motor.

[0015] The motor 5 is provided with a hall sensor 61, an encoder 62, and a resolver 63. The hall sensor 61 detects a magnetic field corresponding to the rotor position in the motor 5 and outputs a pulse signal according to the detected magnetic field. The encoder 62 outputs a pulse signal according to the rotor position or rotor speed in the motor 5. The resolver 63 outputs an analog signal according to the rotor position or rotor speed in the motor 5.

[0016] Also, the inverter 4 is provided with a current sensor 64 and a temperature sensor 65. The current sensor 64 detects the output current of the inverter 4 and outputs an analog signal according to the detected current value. The temperature sensor 65 detects the temperature of the inverter 4 itself or the ambient temperature of the inverter 4 and outputs an analog signal according to the detected temperature value.

[0017] The semiconductor device 3 not only controls the rotation of the motor 5 but also monitors information related to the rotation operation of the motor 5 with high real-time performance by the plurality of sensors described above. The semiconductor device 3 outputs a signal representing the rotor position, rotor speed, etc. in the motor 5 as a feedback signal to the controller 2 based on the information related to the rotation operation of the monitored motor 5.

[0018] The processor (CPU) 31 generates instruction information for the timer control circuit 32 based on the feedback signal and controls the motor 5. The semiconductor device 3 generates a PWM control signal for controlling the output current of the inverter 4 based on the information related to the rotational operation of the motor 5 and the instruction information from the controller 2, and outputs it to the inverter 4. That is, the semiconductor device 3 directly and quickly performs feedback control on the motor 5. The controller 2 indirectly controls the motor 5 via the semiconductor device 3.

[0019] More specifically, the semiconductor device 3 is as follows. As shown in FIG. 1, the semiconductor device 3 is, for example, an MCU (Micro Controller Unit). The semiconductor device 3 includes, for example, a processor 31, a timer control circuit 32, an RD converter 33, a plurality of AD converters, an AD conversion synchronization signal generation unit 36, an event control unit 37, and a communication bus 38. Here, the plurality of AD converters includes an AD converter (A) 34 and an AD converter (B) 35. The processor 31, the timer control circuit 32, the RD converter 33, the AD converter (A) 34, the AD converter (B) 35, the AD conversion synchronization signal generation unit 36, and the event control unit 37 are each electrically connected to the bus 38. Each unit connected to the bus 38 can exchange information with each other as needed.

[0020] The timer control circuit 32 performs hall sensor pulse input processing and encoder pulse input processing. The hall sensor pulse input processing is a process of receiving a pulse signal corresponding to the rotor position from the hall sensor 61, generating data representing the rotor position based on the pulse signal, and outputting the data to the processor 31. The encoder pulse input processing is a process of receiving a pulse signal corresponding to the position and speed of the rotor from the encoder 62, generating data representing the position and speed of the rotor based on the pulse signal, and outputting it to the processor 31.

[0021] The RD converter 33 performs resolver analog signal processing. Resolver analog signal processing involves receiving an analog signal from the resolver 63 that can identify the rotor speed, generating data representing the rotor speed based on that analog signal, and outputting it to the processor 31.

[0022] The AD converter (A) 34 performs AD conversion (A). AD conversion (A) is a process that receives an analog signal corresponding to the current of the inverter 4 from the current sensor 64, converts that analog signal into a digital signal, and outputs the converted digital signal data to the processor 31. When the AD converter (A) 34 receives an AD conversion start request signal from the timer control circuit 32, it starts AD conversion (A) in response to the AD conversion start request signal.

[0023] The AD converter (B) 35 performs AD conversion (B). AD conversion (B) is a process that receives an analog signal corresponding to the temperature of the inverter 4 from the temperature sensor 65, converts that analog signal into a digital signal, and outputs the converted digital signal data to the processor 31. When the AD converter (B) 35 receives an AD conversion start request signal from the event control unit 37, it starts AD conversion (A) in response to the AD conversion start request signal.

[0024] The AD conversion synchronization signal generation unit 36 ​​generates an AD conversion synchronization signal and outputs the generated AD conversion synchronization signal to the AD converter (A) 34 and the AD converter (B) 35, respectively. The AD conversion synchronization signal is an example of an "AD synchronization signal" in this application, and is a signal that determines the timing at which the AD converter starts AD conversion. The AD converter does not start AD conversion immediately after receiving the AD conversion start request signal, but waits until the "AD synchronization signal" rises, and starts AD conversion in synchronization with the "AD synchronization signal". Therefore, generally, there is a time difference, or phase difference, between the timing at which the AD conversion start request signal is input and the timing at which AD conversion starts.

[0025] The timer control circuit 32 also performs PWM control signal output processing. Furthermore, as will be described later, the timer control circuit 32 has a timer counter, and in response to the output of the timer phase signal, it causes the timer counter to start counting. Based on the counter value of the timer counter, the timer control circuit 32 generates a periodic signal used for PWM and an AD conversion start request signal that requests the start of AD conversion.

[0026] The PWM control signal output process involves generating a PWM control signal to control the output current of the inverter 4 using PWM, and outputting the generated PWM control signal to the inverter 4. If the inverter 4 is a three-phase inverter, the PWM control signal can be, for example, the on / off signals for the U-phase, V-phase, and W-phase. The timer counter starts counting when a start trigger is input, and its counter value repeatedly changes from zero to a predetermined value. In order to generate the PWM control signal, the timer control circuit 32 generates a periodic signal drawn by the time change of the timer counter's counter value, i.e., a triangular wave (sawtooth wave) signal, as the carrier in the PWM.

[0027] Furthermore, the timer control circuit 32 generates an AD conversion start request signal (A) in synchronization with the carrier phase, that is, with the same period as the triangular wave signal, and inputs it to the AD converter (A) 34 connected to the current sensor 64. By inputting the AD conversion start request signal (A) synchronized with the carrier phase to the AD converter (A) 34, the semiconductor device 3 becomes capable of monitoring the output current of the inverter 4 at high speed with a relatively short period.

[0028] The event control unit 37 generates an AD conversion start request signal (B) as an event and inputs it to the AD converter (B) 35 connected to the temperature sensor 65. The AD conversion start request signal (B) is generated aperiodically or with a longer period compared to the AD conversion start request signal (A). This is because the temperature of the inverter 4 detected by the temperature sensor 65 does not fluctuate rapidly, so it is sufficient to monitor it with a relatively long period. Lowering the frequency of AD conversion reduces the power consumption of the AD converter, making it possible to save energy.

[0029] The processor 31 performs calculations. These calculations involve determining the signal values ​​necessary for the PWM control signal output processing in the timer control circuit 32, based on the input command information and multiple pieces of information related to the rotational operation of the motor 5. The processor 31 outputs the signal values ​​determined by the calculations to the timer control circuit 32.

[0030] The commands represented by the command information include, for example, acceleration, deceleration, and maintenance of the rotor speed of motor 5. The information related to the rotational operation of motor 5 includes data representing the rotor position obtained by Hall sensor pulse input processing. The information related to the rotational operation of motor 5 also includes data representing the rotor position and speed obtained by encoder pulse input processing, and data representing the rotor speed obtained by resolver analog signal processing. Furthermore, the information related to the rotational operation of motor 5 also includes data representing the output current of inverter 4 obtained by AD conversion (A), and data representing the temperature of inverter 4 obtained by AD conversion (B).

[0031] Figure 2 shows the timing charts of the main signals and processes in the semiconductor device. The timing chart in Figure 2 shows the AD conversion synchronization signal in the AD conversion synchronization signal generation unit 36, the timer counter value in the timer control circuit 32, the PWM control signal, and the AD conversion start request signal (A). The timing chart in Figure 2 also shows the AD conversion (A) in the AD converter (A) 34, the AD conversion start request signal (B) in the event control unit 37, and the AD conversion (B) in the AD converter (B) 35. Here, the inverter 4 is assumed to be a three-phase inverter, and the on / off signal of the U phase in the inverter 4 is shown as a representative example of the PWM control signal.

[0032] The timer control circuit 32 has a comparator (not shown). The PWM control signal can be obtained by taking the carrier timer counter value as one input to the comparator and the judgment voltage value as the other input to the comparator, and outputting the comparator. This judgment voltage value is determined by calculation in the processor 31. Here, the PWM control signal becomes high when the carrier timer counter value is greater than or equal to the judgment voltage value, and low when the carrier timer counter value is less than the judgment voltage value.

[0033] AD converter (A) 34 starts AD conversion (A) after receiving the AD conversion start request signal (A), in synchronization with the most recent AD conversion synchronization signal. Similarly, AD converter (B) 35 starts AD conversion (B) after receiving the AD conversion start request signal (B), in synchronization with the most recent AD conversion synchronization signal.

[0034] Figure 3 shows an example of the configuration of circuit and functional blocks in the main part of a reference semiconductor device. As shown in Figure 3, the main part 30 of the semiconductor device 3 receives a common clock input and performs processing in synchronization with the common clock.

[0035] The circuit and functional blocks constituting the timer control circuit 32 will now be described. As shown in Figure 3, the timer control circuit 32 has a timer control unit 321 and a PWM control signal output processing unit 322 as its main circuit and functional blocks. The timer control unit 321 has a timer period register 3211, a compare match register 3212, a timer counter 3213, and a compare match unit 3214. The compare match register 3212 includes compare match register (1) and compare match register (2).

[0036] When the timer counter 3213 receives a start trigger, it begins counting. In the semiconductor device 3, the controller 2 outputs a start trigger to the timer counter 3213. The timer period register 3211 is set to a reset value, which is the counter value that resets the timer counter 3213. When the counter value of the timer counter 3213 reaches the reset value set in the timer period register 3211, the timer counter 3213 resets the counter value to zero and resumes counting. In other words, after the timer counter 3213 is activated by receiving the start trigger signal, it repeats the operation of counting from zero to the reset value at regular intervals.

[0037] The compare match register (1) is set with a counter value (A) that determines the timing at which the compare match unit 3214 outputs the AD conversion start request signal (A). The compare match register (2) is set with a counter value (B) that determines the judgment voltage value necessary for generating the PWM control signal. The counter value (B) is set by the controller 2 every cycle. When the compare match unit 3214 detects that the value of the timer counter 3213 matches the set value of the compare match register (1), it outputs the AD conversion start request signal (A) to the AD converter (A) 34. Also, when the compare match unit 3214 detects that the value of the timer counter 3213 matches the set value of the compare match register (2), it outputs a signal representing the judgment voltage value to the PWM control signal output processing unit 322.

[0038] The circuit and functional blocks constituting the AD conversion synchronization signal generation unit 36 ​​will now be described. As shown in Figure 3, the AD conversion synchronization signal generation unit 36 ​​includes an AD synchronization counter 361 and an AD synchronization period register 362. The AD synchronization counter 361 starts counting when it receives a start trigger. In the semiconductor device 3, the controller 2 outputs a start trigger signal to the AD synchronization counter 361. The AD synchronization period register 362 has a reset value set, which is the counter value that resets the AD synchronization counter 361. When the counter value of the AD synchronization counter 361 reaches the reset value set in the AD synchronization period register 362, it outputs an AD conversion synchronization signal, resetting the counter value to zero and restarting counting. In other words, the AD conversion synchronization signal generation unit 36 ​​in the timer control circuit 32 starts generating an AD conversion synchronization signal corresponding to a specific phase in the carrier, which is a periodic signal, in response to the output of the AD synchronization phase signal. This specific phase is a relative phase with reference to the phase corresponding to the period of the carrier, which is a periodic signal.

[0039] The circuit and functional blocks constituting the AD converter (A) 34 will now be described. As shown in Figure 3, the AD converter (A) 34 includes a synchronization signal wait processing unit 341 and an AD conversion control unit 342. The synchronization signal wait processing unit 341 receives the AD conversion synchronization signal output from the AD synchronization counter 361. When the synchronization signal wait processing unit 341 receives an AD conversion start request signal (A) from the compare match unit 3214, it waits until it receives the AD conversion synchronization signal. After receiving the AD conversion start request signal (A), the synchronization signal wait processing unit 341 receives the AD conversion synchronization signal and, in synchronization with the AD conversion synchronization signal, transmits a conversion start signal to the AD conversion control unit 342.

[0040] The AD conversion control unit 342 receives a conversion start signal, starts the AD conversion (A), and outputs the AD conversion result (A). Here, the AD conversion control unit 342 samples the analog signal, which is the output of the current sensor 64, converts it into a digital signal, and outputs the converted digital signal as the AD conversion result (A) to the processor 31.

[0041] The circuit and functional blocks constituting the AD converter (B) 35 will now be described. As shown in Figure 3, the AD converter (B) 35 includes a synchronization signal wait processing unit 351 and an AD conversion control unit 352. The synchronization signal wait processing unit 351 receives the AD conversion synchronization signal output from the AD synchronization counter 361. When the synchronization signal wait processing unit 351 receives an AD conversion start request signal (B) from the event control unit 37, it waits until it receives the AD conversion synchronization signal. After receiving the AD conversion start request signal (B), the synchronization signal wait processing unit 351 receives the AD conversion synchronization signal and, in synchronization with the AD conversion synchronization signal, transmits a conversion start signal to the AD conversion control unit 342.

[0042] The AD conversion control unit 352 receives a conversion start signal, starts the AD conversion (B), and outputs the AD conversion result (B). Here, the AD conversion control unit 352 samples the analog signal output from the temperature sensor 65, converts it into a digital signal, and outputs the converted digital signal as the AD conversion result (B) to the processor 31.

[0043] (History of the inventor's research) Next, we will explain the process of the inventor's research. First, we will describe the technical background of the motor control system, and then we will describe the problems that the inventor identified.

[0044] <Technical background in motor control systems> In recent years, semiconductor devices used in equipment control systems have become more high-performance and multi-functional. For example, semiconductor devices for motor control systems, with their increased performance and multi-functionality, acquire multiple pieces of information related to the rotational movement of the motor and, based on this information, perform PWM control of the inverter that supplies current to the motor. This PWM control of the inverter by such a semiconductor device enables feedback control of the motor. Furthermore, in modern motor control, in order to achieve high-speed rotation, high efficiency, and low noise, the information used in feedback control is diverse and requires greater accuracy.

[0045] For these reasons, the information used in motor feedback control is not limited to conventional information such as the motor's rotational position and rotational speed obtained from Hall sensors, encoders, etc. In addition to this conventional information, the information used in motor feedback control also includes information such as the inverter's current value and temperature value obtained from current sensors and temperature sensors installed in the inverter that drives the motor. Semiconductor devices need to receive all of this diverse information as analog signals and observe it at extremely high speed, for example, in near real time. For this reason, semiconductor devices are increasingly equipped with multiple AD converters.

[0046] However, A / D converters generate power supply noise when they start the conversion process. More specifically, A / D conversion is the process of sampling an analog signal multiple times to accumulate analog charge, and then converting that analog charge into a digital value. Because A / D converters consume a large amount of power, especially when they start the process of converting analog charge into a digital value, source noise is likely to occur at this time.

[0047] When there are multiple AD converters, power supply noise can interfere between AD conversions, causing noise interference and degrading the accuracy of the AD conversion. For example, if AD converter (B) starts performing AD conversion (B) while AD converter (A) is performing AD conversion (A), the power supply noise generated by AD conversion (B) will interfere with AD conversion (A), degrading the accuracy of AD conversion (A).

[0048] Therefore, semiconductor devices equipped with multiple AD converters control the start timing of AD conversion so that each AD converter starts AD conversion at a time when noise interference is unlikely to occur, in order to suppress the degradation of AD conversion accuracy.

[0049] For example, as shown in Figure 2, the AD conversion synchronization signal generation unit generates a periodic signal used to generate the PWM control signal in the timer control circuit, i.e., an AD conversion synchronization signal synchronized with the carrier. The AD converters (A) and (B) of the semiconductor device each start AD conversion in synchronization with the most recent AD conversion synchronization signal after receiving an AD conversion start request signal. By synchronizing the start timing of AD conversion with the AD conversion synchronization signal in this way, noise interference can be suppressed.

[0050] <Problems identified by the inventors> Incidentally, a higher-level controller that controls a semiconductor device generally outputs a start trigger to the timer counter of the timer control circuit and the AD synchronous counter of the AD conversion synchronous signal generation unit, respectively, to initiate counting. The start trigger is issued at different timings each time the controller or the semiconductor device is started. Therefore, the delay between the timing when the timer counter starts counting and the timing when the AD synchronous counter starts counting varies each time the controller or the semiconductor device is started. Here, we will refer to the delay between the timing when the timer counter starts counting and the timing when the AD synchronous counter starts counting as latency Dt. Latency can also be described as the relative phase difference when the phase corresponding to the period of the carrier, which is a periodic signal, is used as a reference.

[0051] Latency Dt varies each time the controller or semiconductor device is started. Therefore, the delay between the issuance of the AD conversion start request signal (A) from the timer control circuit and the start of AD conversion by the AD converter (A) also fluctuates. Here, we will refer to the delay between the issuance of the AD conversion start request signal (A) and the start of AD conversion by the AD converter (A) as latency Da.

[0052] When latency Da fluctuates, an error occurs in the AD conversion result of the inverter's current value. This error-laden current value is then fed back to the processor. As a result, the duty cycle of the PWM control signal calculated by the processor also fluctuates. When the duty cycle of the PWM control signal fluctuates, the accuracy of controlling the current output by the inverter deteriorates, and ultimately, the accuracy of motor control deteriorates. This point will be explained in more detail with reference to the diagram.

[0053] Figure 4 is a timing chart representing an example of an ideal latency Da (ideal case). Figure 5 is a timing chart representing the first example of an actual latency Da (actual case 1). Figure 6 is a timing chart representing the second example of an actual latency Da (actual case 2).

[0054] The ideal operation of an AD converter is to operate in a way that minimizes latency Da, that is, to start AD conversion immediately after receiving the AD conversion start request signal. Therefore, as shown in Figure 4, for example, in the case of AD converter (A), ideally, it takes the latency Da(0), which is the minimum value of latency Da, and starts AD conversion immediately after receiving the AD conversion start request signal. In order to achieve such operation, latency Dt must be maintained at a latency Dt(0) such that latency Da takes the latency Da(0), which is the minimum value of latency Da. If the AD converter operates ideally, the calculations in the processor will be performed correctly, and the PWM control signal will be turned on and off at the ideal timing.

[0055] However, in reality, latency Dt fluctuates depending on the startup timing of the semiconductor device. For example, as shown in Figure 5, in some cases latency Dt may be a relatively long latency Dt(1). In this case, latency Da will also be a longer latency Da(1), and the on / off timing of the PWM control signal will deviate from the ideal. Also, as shown in Figure 6, for example, in some cases latency Dt may be a relatively short latency Dt(2). In this case, latency Da will also be a shorter latency Da(2), although not the minimum value, and the on / off timing of the PWM control signal will deviate from the ideal.

[0056] While conducting research and development on semiconductor devices, the inventors discovered, as described above, that the latency Da fluctuates each time the semiconductor device is started up, resulting in a deterioration of the accuracy of motor control.

[0057] (Semiconductor device proposed by the present inventor) Next, an embodiment of the semiconductor device proposed by the present inventor to solve the above-mentioned problems will be described. Regarding the configuration, function, and operation of the semiconductor device according to the embodiment, matters other than those described below will be substantially the same as those of the standard semiconductor device described above.

[0058] <First Embodiment> The semiconductor device according to the first embodiment has a phase-synchronous counter that starts counting when the semiconductor device is started up. The semiconductor device uses the value of the phase-synchronous counter to control the timing of the start of various signal generation so that the phase difference between the AD conversion start request signal and the AD conversion synchronization signal remains constant regardless of the timing of the semiconductor device's startup. A more detailed explanation is as follows.

[0059] According to the first embodiment, the semiconductor device includes a timer control circuit and an AD converter connected to a sensor that obtains information related to the operation of the controlled device. Based on the output of the AD converter, the semiconductor device generates a PWM control signal for controlling the device using a periodic signal in the timer control circuit. After receiving an AD conversion start request signal, the AD converter starts AD conversion in synchronization with the most recent AD conversion synchronization signal.

[0060] The timer control circuit includes a phase-synchronous counter that starts counting when the semiconductor device is started, a timer phase register, and an AD-synchronous phase register. The timer control circuit outputs a timer phase signal that forms the basis for starting the generation of a periodic signal and an AD conversion start request signal when the value of the phase-synchronous counter and the set value of the timer phase register match. The timer control circuit also outputs an AD-synchronous phase signal that forms the basis for starting the generation of an AD conversion synchronization signal when the counter value of the phase-synchronous counter and the set value of the AD-synchronous phase register match. By performing the above processes, the timer control circuit controls the phase difference between the AD conversion start request signal and the AD conversion synchronization signal to remain constant regardless of the timing of the semiconductor device's startup.

[0061] Figure 7 shows an example of the configuration of the circuit and functional blocks in the main part of the semiconductor device according to the first embodiment. Figure 8 shows an example of the timing chart of each signal in the semiconductor device according to the first embodiment.

[0062] As shown in Figure 7, the main part 30A of the semiconductor device according to the first embodiment differs from the main part 30 of the reference semiconductor device described earlier in that the timer control circuit 32 further comprises a phase-synchronous signal generation unit 323. Furthermore, the timer control unit 321 further comprises a timer phase processing unit 3215, and the AD conversion synchronous signal generation unit 36 ​​further comprises an AD synchronous phase processing unit 363.

[0063] The phase-synchronized signal generation unit 323 includes a phase-synchronized counter 3231, a timer phase register 3232, an AD-synchronous phase register 3233, a match detection unit (1) 3234, and a match detection unit (2) 3235. Note that the timer phase register 3232 and the AD-synchronous phase register 3233 may be common to each other.

[0064] The phase-synchronous counter 3231 starts counting when the semiconductor device is powered up. The timer phase register 3232 is set with a counter value that determines the timing for outputting the timer phase signal. The timer phase signal is the signal that causes the timer counter 3213 to start counting. The AD-synchronous phase register 3233 is set with a counter value that determines the timing for outputting the AD-synchronous phase signal. The AD-synchronous phase signal is the signal that causes the AD-synchronous counter 361 to start counting.

[0065] The match detection unit (1) 3234 detects whether the counter value of the phase-synchronous counter 3231 matches the set counter value of the timer phase register 3232. When the match detection unit (1) 3234 detects a match, it outputs a timer phase signal to the timer phase processing unit 3215 with a phase Pa corresponding to the set counter value of the timer phase register 3232, as shown in Figure 8. Note that the phase Pa is a relative phase with reference to the phase of the carrier, which is a periodic signal. The timer phase processing unit 3215 sends a start trigger to the timer counter 3213 in response to the input timer phase signal. The timer counter 3213 receives the start trigger and begins counting.

[0066] Furthermore, the match detection unit (2) 3235 detects whether the counter value of the phase-synchronous counter 3231 matches the set counter value of the AD-synchronous phase register 3233. When the match detection unit (2) 3235 detects a match, it outputs an AD-synchronous phase signal to the AD-synchronous phase processing unit 363 with a phase Pt corresponding to the set value of the AD-synchronous phase register 3233, as shown in Figure 8. Note that the phase Pt is a relative phase with reference to the phase of the carrier, which is a periodic signal. The AD-synchronous phase processing unit 363 sends a start trigger to the AD-synchronous counter 361 in response to the input AD-synchronous phase signal. The AD-synchronous counter 361 receives the start trigger and begins counting.

[0067] Due to the operation of each part in the timer control circuit 32 described above, the latency Dt becomes constant. Latency Dt is the phase difference between the timing when the timer counter 3213 starts counting and the timing when the AD synchronization counter 361 starts counting. As latency Dt becomes constant, latency Da also becomes constant. Latency Da is the phase difference, which is the delay amount from when the AD conversion start request signal (A) is issued until the AD converter (A) 34 starts AD conversion.

[0068] Furthermore, at least one of the timer phase register 3232 and the AD synchronization phase register 3233 may be configured to allow the user to set a desired value. In this case, the user can set the phase difference between the AD conversion start request signal and the AD conversion synchronization signal (AD synchronization signal) to a phase difference that is considered convenient from a design or implementation perspective.

[0069] Alternatively, at least one of the timer phase register 3232 and the AD synchronization phase register 3233 may be pre-set to a specific value such that the phase difference between the AD conversion start request signal and the AD conversion synchronization signal is a specific phase difference. In this case, the specific value is preferably such that the specific phase difference is the minimum value in terms of design or implementation.

[0070] The settings of each register may be set by the user via a controller, or by the user connecting a computer to the semiconductor device and setting the settings via the computer. Alternatively, the settings of each register may be set automatically by a controller or computer connected to the semiconductor device executing a program.

[0071] Thus, according to the first embodiment, regardless of the startup timing of the semiconductor device, the phase difference between the AD conversion start request signal and the AD conversion synchronization signal remains constant with respect to the PWM control carrier, which is a periodic signal. Therefore, when using a semiconductor device equipped with an AD converter to acquire information related to the rotational operation of a motor with the AD converter and control the motor, the control accuracy can be improved.

[0072] Furthermore, according to the first embodiment, the phase difference between the AD conversion start request signal and the AD conversion synchronization signal can be brought closer to a minimum value. As a result, the control accuracy of the motor 5, which is the controlled device, can be further improved.

[0073] <Modified form of the first embodiment> Incidentally, in the actual circuit, an output delay RDt occurs from the time the AD conversion start request signal (A) is output from the timer counter 3213 to the AD converter (A) 34. Similarly, an output delay Rda occurs from the time the AD conversion synchronization signal is output from the AD synchronization counter 361 to the AD converter (A) 34. Furthermore, due to differences in the circuit path, variations in the characteristics of circuit elements, etc., it is possible that the output delays RDt and Rda may differ. In this case, even if the latency Dt is small, the difference between the output delays RDt and Rda can increase the waiting time in the synchronization signal wait processing unit 341, potentially increasing the latency Da.

[0074] In light of the above circumstances, it is significant to separate the timer phase register 3232 and the AD synchronization phase register 3233, and to allow different counter values ​​to be set for each register. If different counter values ​​can be set for the timer phase register 3232 and the AD synchronization phase register 3233, the phase difference between the AD synchronization phase signal and the AD conversion start request signal can be controlled. In other words, the difference in output delay can be canceled out, and the waiting time in the synchronization signal Wait processing unit 341 can be shortened. As a result, the latency Da can be reduced to its minimum value, i.e., Da(0) in the ideal case shown in Figure 4.

[0075] In the embodiment described above, the phase difference between the AD synchronization phase signal and the AD conversion start request signal is controlled by adjusting the settings of the timer phase register 3232 and the AD synchronization phase register 3233. This control makes it possible to minimize the latency Da. However, the phase difference between the AD synchronization phase signal and the AD conversion start request signal may also be controlled by adding the setting of the AD synchronization phase register 3233 to the setting of the compare match register 3212 of the timer control unit 321. Minimizing the latency Da is also possible with this type of control.

[0076] <Second Embodiment> The AD conversion control circuit, which controls the timing of starting AD conversion in an AD converter, may operate at a slower speed compared to other circuits. Therefore, a configuration is sometimes adopted in which a common clock is divided and the divided clock is supplied to the AD conversion control circuit. In such a configuration, the phase Dd of the divided clock at the startup of the frequency division circuit affects the variation in the accuracy of AD conversion. Note that the phase Dd is a relative phase with respect to the phase of the carrier, which is a periodic signal. In the semiconductor device according to the second embodiment, even in such a case, the latency Da, i.e., the phase difference between the AD conversion start request signal and the AD conversion synchronization signal, is kept constant regardless of the startup timing of the semiconductor device.

[0077] The semiconductor device according to the second embodiment has a frequency divider circuit that divides a common clock to generate a divided clock and outputs it to an AD converter. The AD converter starts AD conversion in synchronization with the divided clock. The semiconductor device according to the second embodiment controls the phase of the divided clock output from the frequency divider circuit so that the latency Da is constant regardless of the startup timing of the semiconductor device.

[0078] Figure 9 shows an example of the configuration of circuit and functional blocks in the main part of a semiconductor device according to the second embodiment. As shown in Figure 9, the main part 30B of the semiconductor device according to the second embodiment further includes a frequency divider circuit 371 and a frequency divider phase processing unit 372 compared to the semiconductor device according to the first embodiment. A common clock is input to the semiconductor device in order to synchronize the operation of each part. The frequency divider circuit 371 divides the common clock to generate a divided clock and outputs this divided clock to the AD conversion control unit 342 of the AD converter (A) 34 and the AD conversion control unit 352 of the AD converter (B), respectively. The frequency divider phase processing unit 372 adjusts the phase with respect to the frequency divider circuit 371, that is, the phase of the divided clock. By adjusting the phase of the divided clock, the frequency divider phase processing unit 372 makes the phase of the divided clock constant with respect to the timer counter 3213 and the AD synchronization counter 361.

[0079] Figure 10 shows an example of a timing chart for each signal in a semiconductor device according to the second embodiment. In the semiconductor device according to the second embodiment, as shown in Figure 10, a latency Dt occurs that corresponds to the phase difference between the phase Pa of the timer phase signal and the phase Pt of the AD synchronization phase signal. In addition, a latency Da occurs that corresponds to the phase difference from when the AD converter (A) receives the AD conversion start request signal (A) until it receives the AD conversion synchronization signal.

[0080] The lower part of Figure 10 shows an enlarged view of the AD conversion synchronization signal, the AD conversion start request signal (A), the common clock, the frequency divider clock, and the on / off status of AD conversion in the AD converter (A). This enlarged view also shows the timing of the start of AD conversion by the AD converter (A) 34 and the frequency divider clock before and after the application of phase adjustment of the frequency divider clock by the frequency divider phase processing unit 372. The upper part of the enlarged timing chart is the chart before the application of phase adjustment of the frequency divider clock, and the lower part is the chart after the application of phase adjustment of the frequency divider clock.

[0081] As can be seen from this enlarged diagram, the latency, which is the phase difference between the AD conversion start request signal (A) and the divided clock used as the AD conversion synchronization signal, corresponds to a phase difference of Dd. And the latency Dd, which corresponds to a phase difference of Dd, remains constant regardless of the startup timing of the semiconductor device. In other words, even when AD conversion is started in synchronization with the divided clock, the latency Dd can be kept constant regardless of the startup timing of the semiconductor device.

[0082] As a result, the AD conversion synchronization signal maintains a constant phase difference with respect to the PWM control carrier generated in the timer control circuit 32. The phase difference between the timing of PWM control signal generation and the timing of AD conversion commencement will no longer vary with each startup of the semiconductor device according to the second implementation n form. Consequently, the phase difference between the timing of PWM control signal generation and the timing of the AD converter (A) output being input to the processor 31 becomes constant. When the processor 31 performs calculations to generate the PWM control signal based on the output of the AD converter, the output of the AD converter corresponds to the sensor output at the same phase. Therefore, variations in the degree of real-time performance are eliminated, and control accuracy is improved.

[0083] Now, let's consider the latency from when the AD converter (A) receives the AD conversion start request signal (A) until the AD conversion (A) begins, before the phase adjustment of the divided clock is applied. As can be seen from the chart in the upper part of the enlarged view, the latency we are focusing on is the latency Da plus the phase Dd of the divided clock, which is the latency Da plus Dd. In other words, the latency from when the AD converter (A) receives the AD conversion start request signal (A) until the AD conversion (A) begins will always have the phase Dd of the divided clock added to it.

[0084] On the other hand, after applying phase adjustment to the frequency divider clock, as can be seen from the chart in the lower part of the enlarged view, the latency of interest becomes only latency Da. That is, since the phase Dd of the frequency divider clock is adjusted to zero, the latency from when the AD converter (A) receives the AD converter start request signal (A) until the AD converter (A) starts is suppressed to the minimum value of latency Da. Therefore, applying phase adjustment to the frequency divider clock improves the accuracy of the conversion result of the AD converter (A), improves the control accuracy of the inverter 4, and ultimately improves the control accuracy of the motor 5.

[0085] Furthermore, at least one of the phase adjustment amounts of the timer phase register 3232, the AD synchronization phase register 3233, and the frequency division phase processing unit 372 may be configured to allow the user to set a desired value. In this case, the user can set the phase difference between the AD conversion start request signal and the frequency division clock (AD synchronization signal) to a phase difference that is considered convenient from a design or implementation perspective.

[0086] Alternatively, one or more of the timer phase register 3232, AD synchronization phase register 3233, and frequency division phase processing unit 372 (phase adjustment amount) may be pre-set to a specific value so that the above-mentioned phase difference becomes a specific phase difference. In this case, it is preferable that the specific value is such that the above-mentioned specific phase difference becomes the minimum value in terms of design or implementation.

[0087] The system is configured to allow setting a desired value so that the phase difference between the AD conversion start request signal and the frequency divider clock (AD synchronization signal) becomes a desired phase difference. Alternatively, one or more of the timer phase register 3232, AD synchronization phase register 3233, and frequency divider phase processing unit 372 (phase adjustment amount) may be pre-set to a specific value so that the above phase difference becomes a specific phase difference. From the viewpoint of improving the control of the motor 5, it is preferable that the above specific phase difference be the minimum value in terms of design or implementation.

[0088] The settings for each register or the adjustment amount for the frequency divider clock may be set by the user via a controller, or by the user connecting a computer to the semiconductor device and setting them via the computer. Alternatively, the settings for each register may be set automatically by a controller or computer connected to the semiconductor device executing a program.

[0089] Thus, according to the second embodiment, the frequency division phase processing unit 372 can adjust the phase of the divided clock obtained by dividing the common clock based on the AD synchronization phase signal. In other words, even when AD conversion is started in synchronization with the divided clock, the phase difference between the AD conversion start request signal and the divided clock remains constant with respect to the PWM control carrier, regardless of the startup timing of the semiconductor device. Therefore, when using a semiconductor device equipped with an AD converter to acquire information related to the rotational operation of a motor with the AD converter and control the motor, the control accuracy can be improved.

[0090] Furthermore, according to the second embodiment, the phase difference between the AD conversion start request signal and the frequency divider clock can be brought closer to a minimum value. As a result, the control accuracy of the motor 5, which is the controlled device, can be further improved.

[0091] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0092] For example, in each of the above embodiments, the AD converter (A) is connected to a current sensor provided on the inverter, but other sensors may be connected. For example, the AD converter (A) may be a Hall sensor, encoder, or resolver provided on the motor. Even in such cases, the control accuracy of the motor can be improved.

[0093] Furthermore, in each of the above embodiments, if the semiconductor device includes multiple AD converters, the following can be said: If an AD conversion start request signal that is tuned to a periodic carrier is input to at least one of the multiple AD converters, then a non-periodic AD conversion start request signal may be input to the other AD converters. Even in such cases, the possibility of noise interference is reduced, so the phase difference between the AD conversion start request signal and the AD conversion synchronization signal can be kept constant regardless of the startup timing of the semiconductor device, thereby improving control accuracy.

[0094] Furthermore, in each of the above embodiments, at least a portion of the elements constituting the semiconductor device may be provided outside the semiconductor device. In this case, the elements provided outside the semiconductor device may be made of other semiconductors, or they may be made of discretely assembled circuits, etc.

[0095] Furthermore, in each of the embodiments described above, the direct target of PWM control is the output current of the inverter, and the final controlled device is the motor driven by that output current. However, the direct target of PWM control may be a device, circuit, or apparatus other than the inverter. Also, the final controlled device may be a device, circuit, or apparatus other than the motor. In other words, the direct target of PWM control and the final controlled device may be any type of device. [Explanation of symbols]

[0096] 1…Motor control system, 2…Controller, 3…Semiconductor device, 4…Inverter, 5…Motor, 30, 30A, 30B…Main parts of semiconductor device, 31…Processor, 32…Timer control circuit, 33…RD converter, 34…AD converter (A), 35…AD converter (B), 36…AD conversion synchronization signal generation unit, 37…Event control unit, 38…Bus, 321…Timer control unit, 322…PWM control signal output processing unit, 323…Phase synchronization signal generation unit, 341, 351…Synchronization signal Wait processing 342, 352…AD conversion control unit, 361…AD synchronous counter, 362…AD synchronous period register, 371…Frequency divider circuit, 372…Frequency divider phase processing unit, 3211…Timer period register, 3212…Compare match register, 3213…Timer counter, 3214…Compare match unit, 3215…Timer phase processing unit, 3231…Phase synchronous counter, 3232…Timer phase register, 3233…AD synchronous phase register, 3234…Match detection unit (1), 3235…Match detection unit (2)

Claims

1. A semiconductor device comprising a timer control circuit and an AD converter connected to a sensor that obtains information related to the operation of a device to be controlled, wherein a PWM control signal for controlling the device is generated using a periodic signal in the timer control circuit based on the output of the AD converter, The aforementioned AD converter, after receiving an AD conversion start request signal, starts AD conversion in synchronization with the most recent AD synchronization signal. The timer control circuit is The semiconductor device includes a phase-synchronous counter that starts counting upon startup, a timer phase register, and an AD-synchronous phase register. The process involves outputting a timer phase signal that serves as the basis for starting the generation of the periodic signal and the AD conversion start request signal when the counter value of the phase-synchronized counter matches the set value of the timer phase register, The process of outputting an AD synchronization phase signal, which serves as the basis for starting the generation of the AD synchronization signal, is executed when the counter value of the phase synchronization counter matches the set value of the AD synchronization phase register. The phase difference between the AD conversion start request signal and the AD synchronization signal is controlled to remain constant regardless of the startup timing of the semiconductor device. Semiconductor equipment.

2. In the semiconductor device described in claim 1, The timer control circuit is It has a timer counter, In response to the output of the timer phase signal, the timer counter is instructed to start counting. Based on the counter value of the timer counter, the periodic signal and the AD conversion start request signal are generated. Semiconductor equipment.

3. In the semiconductor device described in claim 2, The timer control circuit is In response to the output of the AD synchronization phase signal, the generation of the AD synchronization signal corresponding to a specific phase in the periodic signal is initiated. Semiconductor equipment.

4. In the semiconductor device described in claim 3, Equipped with multiple A / D converters, At least one of the plurality of A / D converters starts A / D conversion in synchronization with the A / D synchronization signal after receiving a non-periodic A / D conversion start request signal. Semiconductor equipment.

5. In the semiconductor device described in claim 3, The aforementioned PWM control signal is used for PWM control of the inverter output. The AD converter is connected to a sensor that obtains information related to the operation of the device driven by the output of the inverter. Semiconductor equipment.

6. In the semiconductor device described in claim 5, The device is controlled by feedback control by performing PWM control based on the output of the AD converter. Semiconductor equipment.

7. In the semiconductor device described in claim 6, At least one of the timer phase register and the AD synchronization phase register is configured to set a desired setting value so that the phase difference between the AD conversion start request signal and the AD synchronization signal becomes a desired phase difference. Semiconductor equipment.

8. In the semiconductor device described in claim 6, At least one of the timer phase register and the AD synchronization phase register is pre-set to a specific value such that the phase difference between the AD conversion start request signal and the AD synchronization signal becomes a specific phase difference. Semiconductor equipment.

9. In the semiconductor device described in claim 6, It has multiple A / D converters, each of which is connected to a separate sensor. The aforementioned device is a motor, The plurality of sensors include at least one of the following: a sensor for detecting the rotational position of the motor, a sensor for detecting the rotational speed of the motor, a sensor for detecting the temperature of the inverter or the ambient temperature around the inverter, and a sensor for detecting the output current of the inverter. Semiconductor equipment.

10. In the semiconductor device described in claim 3, The circuit includes a frequency divider that, in response to the output of the AD synchronization phase signal, starts generating a divided clock obtained by dividing the common clock input to the semiconductor device, which is synchronized to a specific phase in the periodic signal. The AD synchronization signal operates in synchronization with the frequency divider clock. Semiconductor equipment.

11. In the semiconductor device according to claim 10, Equipped with multiple A / D converters, At least one of the plurality of A / D converters starts A / D conversion in synchronization with the A / D synchronization signal after receiving a non-periodic A / D conversion start request signal. Semiconductor equipment.

12. In the semiconductor device according to claim 10, The aforementioned PWM control signal is used for PWM control of the inverter output. The AD converter is connected to a sensor that obtains information related to the operation of the device driven by the output of the inverter. Semiconductor equipment.

13. In the semiconductor device according to claim 12, The device is controlled by feedback control by performing PWM control based on the output of the AD converter. Semiconductor equipment.

14. In the semiconductor device according to claim 13, The system includes a frequency division phase processing unit that adjusts the phase of the frequency division clock, At least one of the timer phase register, the AD synchronization phase register, and the phase adjustment amount in the frequency division phase processing unit is configured to set a desired value so that the phase difference between the AD conversion start request signal and the AD synchronization signal becomes a desired phase difference. Semiconductor equipment.

15. In the semiconductor device according to claim 13, The system includes a frequency division phase processing unit that adjusts the phase of the frequency division clock, At least one of the timer phase register, the AD synchronization phase register, and the phase adjustment amount in the frequency division phase processing unit is set to a specific value in advance so that the phase difference between the AD conversion start request signal and the AD synchronization signal becomes a specific phase difference. Semiconductor equipment.

16. In the semiconductor device according to claim 13, It has multiple A / D converters connected to multiple sensors, The aforementioned device is a motor, The plurality of sensors include at least one of the following: a sensor for detecting the rotational position of the motor, a sensor for detecting the rotational speed of the motor, a sensor for detecting the temperature of the inverter or the ambient temperature around the inverter, and a sensor for detecting the output current of the inverter. Semiconductor equipment.

17. Controller and Binding machines and Inverter and Equipped with a motor, The controller inputs instruction information related to the operation of the motor to the semiconductor device. The semiconductor device includes a timer control circuit and an AD converter connected to a sensor that obtains information related to the operation of the motor, and generates a PWM control signal for controlling the motor using a periodic signal in the timer control circuit based on the instruction information and the output of the AD converter. The aforementioned AD converter, after receiving an AD conversion start request signal, starts AD conversion in synchronization with the most recent AD synchronization signal. The inverter's output is controlled based on the PWM control signal. The motor is driven by the output of the inverter, The timer control circuit is The semiconductor device includes a phase-synchronous counter that starts counting upon startup, a timer phase register, and an AD-synchronous phase register. The process involves outputting a timer phase signal that serves as the basis for starting the generation of the periodic signal and the AD conversion start request signal when the counter value of the phase-synchronized counter matches the set value of the timer phase register, The process of outputting an AD synchronization phase signal, which serves as the basis for starting the generation of the AD synchronization signal, is executed when the counter value of the phase synchronization counter matches the set value of the AD synchronization phase register. The phase difference between the AD conversion start request signal and the AD synchronization signal is controlled to remain constant regardless of the startup timing of the semiconductor device. Motor control system.

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