Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device capable of simultaneously suppressing conduction loss and switching loss. [Solution] In the semiconductor device 101, the bipolar transistor includes a semiconductor substrate 10 and a first electrode 21. The semiconductor substrate includes a drift layer 2, a body layer 3, a charge storage region 4 located on the body layer, and a source region 6 and a contact region 7 formed on the first surface and electrically connected to the first electrode. The bipolar transistor further includes one or more first trench gates 11 and a plurality of second trench gates 12 extending from the first surface 10A toward the second surface 10B. The depth D2 of each of the plurality of second trench gates from the first surface is shallower than the depth D1 of the one or more first trench gates from the first surface. The semiconductor substrate also includes a first region 1 located between the body layer and the contact region between a plurality of adjacent second trench gates 12a, 12b, and having a lower impurity density than the body layer.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] A bipolar transistor is known that comprises a p-type collector layer, an n-type drift layer, a p-type body layer, an n-type charge storage region, and a p-type channel dope layer, and is provided with a trench gate that penetrates the body layer, the charge storage region, and the channel dope layer and reaches the drift layer (see, for example, Japanese Patent Application Publication No. 2009-253004). In the ON state of such a bipolar transistor, the pn junction between the charge storage region and the channel dope layer suppresses the discharge of holes injected from the p-type collector layer into the n-type drift layer to the channel dope layer, thereby contributing to the suppression of conduction loss. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2009-253004 [Overview of the project] [Problems that the invention aims to solve]

[0004] In bipolar transistors equipped with a charge storage region, it is necessary to discharge the numerous holes accumulated in the charge storage region during the on-state when the transistor is turned off, making it difficult to suppress the increase in switching losses.

[0005] The primary object of this disclosure is to provide a semiconductor device capable of simultaneously suppressing conduction loss and switching loss. [Means for solving the problem]

[0006] The semiconductor device according to this disclosure comprises a bipolar transistor. The bipolar transistor includes a semiconductor substrate having a first surface and a second surface located opposite to the first surface, and a first electrode provided on the first surface. The semiconductor substrate includes a drift layer, a body layer located on the first surface side of the drift layer, a charge storage region located on the body layer, and a source region and a contact region formed on the first surface and electrically connected to the first electrode. The bipolar transistor further includes at least one first trench gate and a plurality of second trench gates extending from the first surface toward the second surface. The depth of each of the plurality of second trench gates from the first surface is shallower than the depth of at least one first trench gate from the first surface. The at least one first trench gate penetrates the source region, the charge storage region, and the body layer to reach the drift layer. The plurality of second trench gates are arranged adjacent to each other with space between them. The semiconductor substrate includes a body layer, a contact region, and a first region located between the body layer and the contact region and having a lower impurity density than the body layer, between a plurality of adjacent second trench gates. [Effects of the Invention]

[0007] According to this disclosure, a semiconductor device capable of simultaneously suppressing conduction loss and switching loss can be provided. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic plan view showing an example of a semiconductor device according to Embodiment 1. [Figure 2] This is a schematic plan view showing region II in Figure 1. [Figure 3] This is a schematic cross-sectional view along the cross-sectional line III-III in Figure 2. [Figure 4] This flowchart shows an example of a method for manufacturing a semiconductor device according to Embodiment 1. [Figure 5] This is a schematic cross-sectional diagram illustrating one step in the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 6]This is a schematic cross-sectional diagram illustrating one step after the process shown in Figure 5 in the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 7] This is a schematic cross-sectional diagram illustrating one step after the process shown in Figure 6 in the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 8] This is a schematic cross-sectional diagram illustrating one step after the process shown in Figure 7 in the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 9] This is a schematic cross-sectional diagram illustrating one step after the process shown in Figure 8 in the manufacturing method of a semiconductor device according to Embodiment 1. [Figure 10] This is a schematic cross-sectional view showing a modified example of the semiconductor device according to Embodiment 1. [Figure 11] This is a schematic diagram showing an example of the impurity density profile of the first region in the semiconductor device according to Embodiment 2. [Figure 12] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 3. [Figure 13] This graph shows the relationship between the spacing Wp of multiple adjacent second trenches and the impurity density of the first region in the semiconductor device according to Embodiment 3. [Figure 14] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 4. [Figure 15] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 5. [Figure 16] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 6. [Figure 17] This is a schematic cross-sectional view showing a modified example of the semiconductor device according to Embodiment 6. [Figure 18] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 7. [Figure 19] This is a schematic cross-sectional diagram illustrating one step in the manufacturing method of a semiconductor device according to Embodiment 7. [Figure 20]This is a schematic cross-sectional diagram illustrating one step after the process shown in Figure 19 in the manufacturing method of a semiconductor device according to Embodiment 7. [Figure 21] This is a schematic cross-sectional diagram illustrating one step after the process shown in Figure 20 in the manufacturing method of a semiconductor device according to Embodiment 7. [Figure 22] This is a schematic cross-sectional view illustrating one step in the first modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 23] This is a schematic cross-sectional view illustrating one step after the process shown in Figure 22 in the first modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 24] This is a schematic cross-sectional view illustrating one step after the process shown in Figure 23 in the first modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 25] This is a schematic cross-sectional view illustrating one step in a second modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 26] This is a schematic cross-sectional view illustrating one step after the process shown in Figure 25 in a second modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 27] This is a schematic cross-sectional view illustrating one step after the process shown in Figure 26 in a second modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 28] This is a schematic cross-sectional view illustrating one step after the process shown in Figure 27 in a second modified example of the semiconductor device manufacturing method according to Embodiment 7. [Figure 29] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 8. [Figure 30] This is a schematic cross-sectional diagram illustrating one step in the manufacturing method of a semiconductor device according to Embodiment 8. [Figure 31] This graph shows the relationship between the opening width of the trench mask and the depth of the trench formed by selectively etching the semiconductor substrate through the trench mask, in the method for manufacturing a semiconductor device according to Embodiment 8. [Figure 32] This is a schematic cross-sectional view showing an example of a semiconductor device according to Embodiment 9. [Figure 33] This is a schematic plan view showing an example of a semiconductor device according to Embodiment 9. [Figure 34] This is a waveform diagram illustrating an example of operation of a semiconductor device according to Embodiment 9. [Figure 35] This figure shows the evaluation results of the voltage applied to the trench gate and the conduction loss for embodiments and comparative examples of the semiconductor device according to Embodiment 9. [Figure 36] This is a waveform diagram illustrating an example of operation of a semiconductor device according to Embodiment 10. [Figure 37] This figure shows the evaluation results of the first time difference toff1 and the switching loss Eoff at turn-off for examples and comparative examples of the semiconductor device according to Embodiment 10. [Figure 38] This figure shows the evaluation results of the second time difference ton and the switching loss Eon at turn-on for embodiments and comparative examples of the semiconductor device according to Embodiment 10. [Figure 39] This is a waveform diagram illustrating an example of operation of a semiconductor device according to Embodiment 11. [Figure 40] This figure shows the evaluation results of the third voltage Vdpoff and the switching loss Eoff during turn-off for embodiments and comparative examples of the semiconductor device according to Embodiment 11. [Figure 41] This figure shows the evaluation results of the fourth voltage Vdpon and the switching loss Eon at turn-on for examples and comparative examples of the semiconductor device according to Embodiment 11. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure will be described below with reference to the drawings. In the following, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will not be repeated.

[0010] Embodiment 1. <Configuration of semiconductor device> An example of a semiconductor device 101 according to Embodiment 1 will be described with reference to Figures 1 to 3. The semiconductor device 101 includes a bipolar transistor as a semiconductor element. The bipolar transistor has a trench gate. The bipolar transistor is, for example, an insulated gate bipolar transistor (IGBT) having a trench gate.

[0011] The semiconductor device 101 comprises a semiconductor substrate 10, a first electrode 21 (see Figure 3), and a second electrode 22 (see Figure 3). The semiconductor substrate 10 has a first surface 10A and a second surface 10B (see Figure 3) located on the opposite side of the first surface 10A. The material constituting the semiconductor substrate 10 is not particularly limited, but for example, it may be silicon (Si) or silicon carbide (SiC). Figures 1 and 2 are plan views of the semiconductor device 101 as seen from the first surface 10A side of the semiconductor substrate 10. The first electrode 21 is not shown in Figures 1 and 2.

[0012] As shown in Figure 1, in a plan view from the first surface 10A, the semiconductor substrate 10 includes an element region 120 and an outer peripheral region surrounding the element region 120. A bipolar transistor having a first trench gate 11 and a second trench gate 12 is formed in the element region 120. The first trench gate 11 and the second trench gate 12 extend in a first direction DR1 along the first surface 10A and are spaced apart from each other in a second direction DR2 that is along the first surface 10A and perpendicular to the first direction DR1. Each of the first trench gate 11 and the second trench gate 12 is electrically connected to a gate pad 131. In the semiconductor device 101, the first trench gate 11 and the second trench gate 12 are provided with the same voltage applied to them at the same timing via the gate pad 131.

[0013] As shown in Figures 1 to 3, the semiconductor device 101 comprises a plurality of first trench gates 11 and a plurality of second trench gates 12. The plurality of first trench gates 11 and the plurality of second trench gates 12 extend parallel to each other along the first direction DR1.

[0014] As shown in Figures 2 and 3, the plurality of first trench gates 11 includes a first trench gate 11a and a second trench gate 11b. The first trench gate 11a and the second trench gate 11b are adjacent to each other with a gap between them in the plurality of first trench gates 11. The plurality of second trench gates 12 includes a first second trench gate 12a and a second second trench gate 12b. The first second trench gate 12a and the second second trench gate 12b are adjacent to each other with a gap between them in the plurality of second trench gates 12. The first trench gate 11a, the first second trench gate 12a, the second second trench gate 12b, and the second first trench gate 11b are arranged in this order in the second direction DR2. The first trench gate 11a and the second trench gate 11b are positioned in the second direction DR2 so as to sandwich the first second trench gate 12a and the second second trench gate 12b.

[0015] As shown in Figure 3, the semiconductor substrate 10 includes a first region 1, a drift layer 2, a body layer 3, a charge storage region 4, a channel doping layer 5, a source region 6 (emitter region), a contact region 7, a buffer layer 8, and a collector layer 9.

[0016] The drift layer 2, charge storage region 4, and buffer layer 8 have a first conductivity type. The body layer 3, channel doping layer 5, contact region 7, and collector layer 9 have a second conductivity type. The first region 1 has, for example, a second conductivity type. For example, the first conductivity type is n-type and the second conductivity type is p-type. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0017] The density of first-conductivity impurities in source region 6 is higher than that of first-conductivity impurities in charge storage region 4. The density of second-conductivity impurities in channel-doped layer 5 is higher than that of second-conductivity impurities in body layer 3, but lower than that of second-conductivity impurities in contact region 7. The density of second-conductivity impurities in first region 1 is lower than that of second-conductivity impurities in body layer 3.

[0018] The profile of the second conductivity type impurity density in the first region 1 in the third direction DR3 intersecting the first surface 10A is not particularly limited. The second conductivity type impurity density in the first region 1 may be constant regardless of the position in the third direction DR3.

[0019] Body layer 3 is located on the first surface 10A side of drift layer 2. Body layer 3 is in contact with drift layer 2. Each of the first region 1 and charge storage region 4 is located on the first surface 10A side of body layer 3. Each of the first region 1 and charge storage region 4 is in contact with body layer 3. The first region 1 and charge storage region 4 are adjacent to each other in the second direction DR2, with the second trench gate 12 in between.

[0020] The channel-doped layer 5 is located on the first surface 10A side of the first region 1 and the charge storage region 4. The channel-doped layer 5 is in contact with each of the first region 1 and the charge storage region 4. The source region 6 and the contact region 7 are formed on the first surface 10A. The source region 6 is formed on a portion of the first surface 10A. The contact region 7 is formed on another portion of the first surface 10A. Each of the source region 6 and the contact region 7 is in contact with the channel-doped layer 5.

[0021] The buffer layer 8 is located on the second surface 10B side of the drift layer 2. The buffer layer 8 is in contact with the drift layer 2. The collector layer 9 is formed on the second surface 10B. The collector layer 9 is in contact with the buffer layer 8.

[0022] As shown in Figure 3, the plurality of first trench gates 11 and the plurality of second trench gates 12 extend from the first surface 10A to the second surface 10B of the semiconductor substrate 10. The depth D2 of each of the plurality of second trench gates 12 from the first surface 10A is shallower than the depth D1 of each of the plurality of first trench gates 11 from the first surface 10A. Each of the plurality of first trench gates 11 penetrates the source region 6, the charge storage region 4, and the body layer 3 to reach the drift layer 2. Each of the plurality of second trench gates 12 penetrates the channel doping layer 5, separating the first region 1 and the charge storage region 4. Preferably, each of the plurality of second trench gates 12 reaches the body layer 3.

[0023] Each of the multiple first trench gates 11 is located within a first trench 17 formed in the semiconductor substrate 10. Each of the multiple first trench gates 11 has an electrode portion 13 and an insulating film 14 within the first trench 17. The insulating film 14 is formed on the inner wall surface (bottom and side surface) of the first trench 17. The electrode portion 13 fills the space inside the insulating film 14 within the first trench 17. Each of the multiple first trenches 17 penetrates the source region 6, the charge storage region 4, and the body layer 3 to reach the drift layer 2. The bottom of each of the multiple first trenches 17 is located within the drift layer 2.

[0024] Each of the plurality of second trench gates 12 is located within a second trench 18 formed in the semiconductor substrate 10. Each of the plurality of second trench gates 12 has an electrode portion 15 and an insulating film 16 within the second trench 18. The insulating film 16 is formed on the inner wall surface (bottom surface and side surface) of the second trench 18. The electrode portion 15 fills the space inside the insulating film 16 within the second trench 18. The material constituting the electrode portions 13 and 15 is, for example, polysilicon. The material constituting the insulating films 14 and 16 is, for example, silicon oxide (SiO2). Each of the plurality of second trenches 18 penetrates the channel doped layer 5 and separates the first region 1 and the charge storage region 4. Preferably, the bottom of each of the plurality of second trenches 18 is located on the second surface 10B side of the junction interface between the charge storage region 4 and the body layer 3.

[0025] The opening width of the second direction DR2 of each of the multiple second trenches 18 may be equal to the opening width of the second direction DR2 of the first trench 17.

[0026] The semiconductor substrate 10 includes a region RA sandwiched between a plurality of adjacent second trench gates 12. In region RA, a body layer 3, a first region 1, a channel doping layer 5, and a contact region 7 are arranged in this order from the second surface 10B side toward the first surface 10A side in a third direction DR3 perpendicular to the first surface 10A. The first region 1 is formed only in region RA of the semiconductor substrate 10. The first region 1 is not formed in the region sandwiched between the first trench gate 11 and the second trench gate 12.

[0027] In the region sandwiched between the adjacent first trench gate 11a and first second trench gate 12a, the body layer 3, charge storage region 4, channel doping layer 5, and source region 6 or contact region 7 are arranged in this order from the second surface 10B side toward the first surface 10A side in a third direction DR3 perpendicular to the first surface 10A.

[0028] The first electrode 21 is located on the first surface 10A of the semiconductor substrate 10. The first electrode 21 is electrically connected to the source region 6 and the contact region 7. The first electrode 21 is electrically insulated from the first trench gate 11 and the second trench gate 12 by an interlayer insulating film 23. The interlayer insulating film 23 covers the respective electrode portions 13 and 15 of the first trench gate 11 and the second trench gate 12. The second electrode 22 is located on the second surface 10B of the semiconductor substrate 10. The second electrode 22 is electrically connected to the collector layer 9.

[0029] As shown in Figure 2, a plurality of source regions 6 are formed on the semiconductor substrate 10. The plurality of source regions 6 are arranged, for example, so as to sandwich the first trench gate 11 in the second direction DR2. The plurality of source regions 6 are arranged, for example, spaced apart from each other in the first direction DR1. The contact region 7 is formed, for example, in the entire region where the source regions 6, the first trench gate 11, and the second trench gate 12 are not formed. Note that the arrangement of the source regions 6 and contact region 7 shown in Figure 2 is just an example and is not limited thereto. The source regions 6 can be arranged arbitrarily as long as they are in contact with at least one side of the first trench gate 11 in the second direction DR2. The contact region 7 does not have to be formed in the entire region where the source regions 6, the first trench gate 11, and the second trench gate 12 are not formed.

[0030] <Manufacturing method for semiconductor devices> An example of a manufacturing method for the semiconductor device 101 will be explained with reference to Figures 4 to 9. Figures 4 to 9 are diagrams illustrating a method for forming the structure on the first surface 10A side in the manufacturing method of the semiconductor device 101.

[0031] In the method for manufacturing the semiconductor device 101, a semiconductor substrate having a first conductivity type is prepared (S10). The density of first conductivity type impurities in the semiconductor substrate is equal to the density of first conductivity type impurities in the drift layer 2. The semiconductor substrate has a first surface 10A and a second surface 10B.

[0032] After step S10, impurities for forming the body layer 3, charge storage region 4, channel dope layer 5, and first region 1 are injected from the first surface 10A of the semiconductor substrate (S20). As shown in Figure 5, in step (S20), first, a second conductivity type impurity 33 for forming the body layer 3 is injected into the semiconductor substrate 10 without a mask. Next, as shown in Figure 6, a mask 201 is formed on the first surface 10A to cover the region RB where the first region 1 is to be formed. The mask 201 has an opening 201A that opens onto the region where the charge storage region 4 is to be formed. Next, a first conductivity type impurity 34 for forming the charge storage region 4 and a second conductivity type impurity 35 for forming the channel dope layer 5 are injected into the semiconductor substrate 10 in order through the mask 201. Next, the mask 201 is removed from the first surface 10A. Next, as shown in Figure 7, a mask 221 having an opening 221A that opens onto the region RB where the first region 1 is to be formed is formed on the first surface 10A. The mask 211 covers the region where the charge storage region 4 is to be formed. Next, a second conductivity type impurity for forming the first region 1 is injected into region RB of the semiconductor substrate 10 through the mask 221.

[0033] As described above, the first region 1 in the semiconductor device 101 may have a first conductivity type. In this case, in step (S20), a first conductivity type impurity for forming the first region 1 can be injected into region RB of the semiconductor substrate 10 via the mask 221.

[0034] After process (S20), the semiconductor substrate 10 is heated to diffuse the impurities injected in process (S20) into the semiconductor substrate 10 (S30). As a result, as shown in Figure 8, impurity regions 41, 43, 44, and 45 corresponding to the first region 1, body layer 3, charge storage region 4, and channel doping layer 5 are formed in the semiconductor substrate 10. The region in the semiconductor substrate 10 where impurity regions 41, 43, 44, and 45 are not formed becomes the impurity region 42 corresponding to the drift layer 2.

[0035] After step (S30), a first conductivity type impurity to form the source region 6 is injected into the semiconductor substrate 10 (S40). In this step (S40), a mask covering the first region 1 is used. After step (S40), the semiconductor substrate 10 is heated to diffuse the impurity injected in step (S30) into the semiconductor substrate 10 (S50).

[0036] After step (S50), a first trench gate 11 and a second trench gate 12 are formed on the semiconductor substrate 10 (S60). In this step (S60), for example, a second trench 18 is formed (S61), and then the first trench 17 is formed (S62). In step (S61), the second trench 18 is formed by etching a part of the semiconductor substrate 10 using a mask that opens on the region where the second trench 18 is to be formed on the first surface 10A. In step (S62), the first trench 17 is formed by etching a part of the semiconductor substrate 10 using a mask that opens on the region where the first trench 17 is to be formed on the first surface 10A. Insulating films 14 and 16 are formed on the bottom and side surfaces of the first trench 17 and the second trench 18 (S63). The insulating films 14 and 16 can be formed, for example, by oxidizing the bottom and side surfaces of the first trench 17 and the second trench 18. Electrode portions 13 and 15 are formed on the insulating film 14 in the first trench 17 and the insulating film 16 in the second trench 18. The electrode portions 13 and 15 can be formed, for example, by depositing a conductive film on the surface of the insulating films 14 and 16 and on the first surface 10A, and then etching back the conductive film.

[0037] After step (S60), a second conductivity type impurity for forming the contact region 7 is injected into the semiconductor substrate 10 (S70). In this step (S70), a mask that opens onto the first region 1 is used. After step (S70), the semiconductor substrate 10 is heated to diffuse the impurity injected in step (S70) into the semiconductor substrate 10 (S80). In this way, as shown in Figure 9, a laminated structure of the body layer 3, the first region 1, the channel dope layer 5, and the contact region 7 is formed between two adjacent second trench gates 12 on the semiconductor substrate 10. Furthermore, the interlayer insulating film 23 and the first electrode 21 are formed on the first surface 10A, and the structure on the second surface 10B is formed, thereby manufacturing the semiconductor device 101 shown in Figure 3.

[0038] <Effects of semiconductor device 101> The effects of the semiconductor device 101 will be explained in comparison to those of a conventional bipolar transistor that has a charge storage region.

[0039] As described above, in conventional bipolar transistors, the charge storage region contributes to suppressing conduction losses by suppressing the decrease in the hole density distribution as the hole minority carriers injected from the back collector layer to the drift layer 2 approach the front surface during the ON state. However, during turn-off, it is necessary to discharge the large number of hole minority carriers in the drift layer 2 that were stored by the charge storage region during the ON state, making it difficult to suppress the increase in switching losses.

[0040] In contrast, in the semiconductor device 101, the semiconductor substrate 10 includes a body layer 3, a contact region 7, and a first region 1 located between the body layer 3 and the contact region 7 and having a lower impurity density than the body layer 3, between the plurality of adjacent second trench gates 12. The first region 1 of the semiconductor device 101 has the same second conductivity type as the body layer 3.

[0041] In this case, when the semiconductor device 101 is ON, if a predetermined voltage (e.g., +15V) similar to the voltage applied to the first trench gate 11 is also applied to each of the multiple second trench gates 12, a depletion layer can spread from each of the multiple second trenches 18 toward the inside of the first region 1. From a different perspective, at least a portion of the first region 1 can be depleted before the body layer 3 is depleted. The depletion layer formed within the first region 1, together with the charge storage region 4, suppresses the discharge of holes into the channel doping layer 5 and the contact region 7, and contributes to suppressing conduction losses.

[0042] On the other hand, when the semiconductor device 101 is turned off, the voltage applied to the second trench gate 12 is set to less than the predetermined voltage, thereby achieving a state in which no depletion layer is formed in the first region 1. The first region 1 acts as a simple resistor during turn-off and can serve as a path for discharging the numerous hole minority carriers accumulated on the first surface 10A side of the drift layer 2 from the drift layer 2. As a result, the semiconductor device 101 can suppress the increase in switching loss during turn-off.

[0043] Furthermore, in semiconductor device 101, the impurity density of the body layer 3 is higher than the impurity density of the first region 1 located on a part of the body layer 3, and within region RA, only the first region 1 has an impurity density low enough to form a depletion layer in the ON state. Therefore, compared to the conventional bipolar transistor described above, semiconductor device 101 can more effectively discharge holes during turn-off, thereby suppressing an increase in switching loss.

[0044] Preferably, the bottom of each of the multiple second trenches 18 is positioned on the second surface 10B side of the junction interface between the charge storage region 4 and the body layer 3. This allows for more effective discharge of holes accumulated in the ON state.

[0045] <Variable example of semiconductor device 101> Figure 10 is a cross-sectional view showing a modified semiconductor device 102 of semiconductor device 101. As shown in Figure 10, the first region 1 may have a first conductivity type. The first region 1 may have a conductivity type different from that of the body layer 3 and the channel doping layer 5. In this case, a pnp structure is formed within region RA. A depletion layer at the pn junction interface within region RA is formed when the voltage applied to each of the multiple second trench gates 12 in the ON state is greater than or equal to a predetermined voltage. This depletion layer suppresses the discharge of holes into the channel doping layer 5 and contributes to suppressing conduction loss. When the voltage applied to each of the multiple second trench gates 12 in the turn-off state falls below a predetermined voltage, a p-type channel is formed within the first region 1 along the second trench 18, and holes accumulated in the ON state are discharged into the channel doping layer 5 via the p-type channel. The predetermined voltage varies depending on the conductivity type of the first region 1.

[0046] Embodiment 2. The semiconductor device according to Embodiment 2 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0047] Figure 11 is a schematic diagram showing the impurity density profile in the third direction DR3 of the first region of the semiconductor device according to Embodiment 2. The horizontal axis of Figure 11 shows the depth of the third direction DR3 from the first surface 10A in the first region 1, and the vertical axis of Figure 11 shows the impurity density of the first region 1. As shown in Figure 11, the semiconductor device according to Embodiment 2 differs from the semiconductor device 101 in that the impurity density profile of the first region 1 has a minimum value in the third direction DR3 intersecting the first surface 10A. From a different perspective, the impurity density profile of the first region 1 in the semiconductor device according to Embodiment 2 has a slope.

[0048] The impurity density profile of the first region 1 has a portion showing a minimum value and a portion showing a value greater than the minimum value. The depth from the first surface 10A of the portion showing the minimum value in the impurity density profile of the first region 1 can be set arbitrarily. The portion showing the minimum value of impurity density in the first region 1 may be located at any position between the interface on the first surface 10A side and the interface on the second surface 10B side of the first region 1 in the third direction DR3. For example, as shown by line L1 in Figure 11, the portion showing the minimum value of impurity density in the first region 1 may be located between the interface on the first surface 10A side and the interface on the second surface 10B side of the first region 1 in the third direction DR3. As shown by line L2 in Figure 11, the impurity density at the interface on the first surface 10A side of the first region 1 may be set to show a minimum value. The impurity density of the first region may be set to gradually increase from the first surface 10A side toward the second surface 10B side. As shown by line L3 in Figure 11, the impurity density at the interface on the second surface 10B side of the first region 1 may be set to a minimum value. The impurity density of the first region may be set to gradually decrease from the first surface 10A side toward the second surface 10B side.

[0049] In the semiconductor device according to Embodiment 2, a depletion layer can be formed in the portion of the first region 1 that shows a minimum value in the impurity density profile when the device is on. In other words, in the semiconductor device according to Embodiment 2, the depth of the depletion layer formed in the first region 1 when the device is on can be determined, which simplifies the design.

[0050] Embodiment 3. The semiconductor device according to Embodiment 3 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0051] Figure 12 is a cross-sectional view showing an example of a semiconductor device 102 according to Embodiment 3. Figure 13 shows the spacing Wp between a plurality of adjacent second trenches 18 and the impurity density N of the first region 1 in the semiconductor device 102. AThis graph shows the relationship that satisfies [the conditions]. The horizontal axis of Figure 13 shows the interval Wp between multiple adjacent second trenches, and the vertical axis of Figure 13 shows the impurity density N of the first region 1. A This is shown. In Figure 13, line L4 indicates the boundary line between the region that satisfies the following relation (1) and the region that does not satisfy the following relation (1). In Figure 13, the circular plot shows the simulation results of confirming the point at which conduction loss begins to worsen as the spacing Wp is widened, under four conditions in which only the impurity concentration of the first region 1 differs from one another. It shows the relationship between the impurity density of the first region 1 and the width of the second direction DR2 of the depletion layer that is formed extending from each of the two adjacent second trench gates 12 that are separated by the first region 1 when 15V is applied to each of them. In Figure 13, the dashed line shows the impurity density of the semiconductor substrate (drift layer 2) that constitutes the first region 1.

[0052] The semiconductor device 102 has a first region 1 that has the same second conductivity type (e.g., p-type) as the body layer 3, and the spacing Wp between a plurality of adjacent second trenches 18 on either side of the first region 1 and the impurity density N of the first region 1. A The semiconductor device 102 differs from semiconductor device 101 in that it satisfies the following relation (1). In semiconductor device 102, the spacing between the multiple second trenches 18 is Wp (unit: m), and the impurity density of the first region 1 is N A (Unit: m) -3 ), the intrinsic carrier density of the semiconductor material constituting the first region 1 is n i (Unit: m) -3 ), the dielectric constant of the semiconductor material constituting the first region 1 is ε, and the Boltzmann coefficient is k. B When the absolute temperature is T and the elementary charge is q, the interval Wp between the multiple second trenches satisfies the following relationship (1).

[0053]

number

[0054] Note that the above interval Wp means the maximum interval between a plurality of second trenches 18a and 18b adjacent to each other across the first region 1. For example, in a cross-section orthogonal to the first direction DR1, when the cross-sectional shape of the region RA between the plurality of second trenches 18a and 18b is a mesa shape, the width of the first region 1 changes in the third direction DR3. In such a case, the above interval Wp is not less than the maximum width of the first region 1. Further, when the impurity density profile of the first region 1 has a minimum value, the impurity density N A means the average value of the impurity density of the portion of the first region 1 excluding the contact region 7 and the body layer 3.

[0055] In the semiconductor device 102, the interval Wp between a plurality of adjacent second trenches and the impurity density N A of the first region 1 are designed so that the above relational expression (1) holds.

[0056] As shown in FIG. 13, the inventors have found that the above simulation results approximately coincide with the line L4, that is, in the on state of the semiconductor device 102 in which the above interval Wp and the impurity density N A of the first region 1 are designed to satisfy the above relational expression (1), a depletion layer can be formed so as to extend between a plurality of second trenches 18 in the first region 1.

[0057] In the semiconductor device 102, based on the above relational expression (1), the interval Wp and the impurity density N A of the first region 1 that are necessary and sufficient for forming a depletion layer to extend between a plurality of second trenches 18 in the on state can be easily designed. For example, according to the interval Wp between a plurality of adjacent second trenches, the impurity density N A of the first region 1 that is necessary and sufficient for forming a depletion layer to extend between a plurality of second trenches 18 in the on state can be easily designed. Further, according to the impurity density N A of the first region 1, the interval Wp that is necessary and sufficient for forming a depletion layer to extend between a plurality of second trenches 18 in the on state can be easily designed.

[0058] In the semiconductor device 102, the distance between the first trench 17 and the second trench 18 is not particularly limited. The distance between the first trench 17 and the second trench 18 may be wider than the distance Wp. The distance between the first trench 17 and the second trench 18 may be narrower than the distance Wp.

[0059] The semiconductor device 102 has a first region 1 that has the same second conductivity type (e.g., p-type) as the body layer 3, and the spacing Wp between a plurality of adjacent second trenches 18 on either side of the first region 1 and the impurity density N of the first region 1. A Except that the following relation (1) is satisfied, the semiconductor device may have the same configuration as the semiconductor device according to Embodiment 2.

[0060] Embodiment 4. The semiconductor device according to Embodiment 4 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0061] Figure 14 is a cross-sectional view showing an example of a semiconductor device 104 according to Embodiment 4. As shown in Figure 14, the semiconductor device 104 differs from the semiconductor device 101 in that it has three or more second trench gates 12 arranged between a plurality of first trench gates 11.

[0062] The plurality of second trench gates 12 include a first second trench gate 12a, a second second trench gate 12b, and a third second trench gate 12c, which are positioned between a first first trench gate 11a and a second first trench gate 11b that are adjacent to each other among the plurality of first trench gates 11.

[0063] The first trench gate 11a is located within the first trench 17a. The second trench gate 11b is located within the second trench 17b. The first second trench gate 12a is located within the first trench 18a. The second second trench gate 12b is located within the second trench 18b. The third second trench gate 12c is located within the third trench 18c.

[0064] The region between the first second trench 18a and the second second trench 18b, and the region between the second second trench 18b and the third second trench 18c are equivalent to the region RA of the semiconductor device 101. The semiconductor device 104 has a plurality of regions RA arranged in a second direction DR2. A first region 1 is formed between the first second trench 18a and the second second trench 18b, and between the second second trench 18b and the third second trench 18c.

[0065] Preferably, the distance Wp1 between the first second trench 18a and the second second trench 18b, and the impurity density N of the first region 1 between the first second trench 18a and the second second trench 18b. A This satisfies the above relation (1). Preferably, the distance Wp2 between the second trench 18b and the third trench 18c, and the impurity density N of the first region 1 between the second trench 18b and the third trench 18c. A This satisfies the above relation (1). From a different perspective, it is preferable that the semiconductor device 104 includes three or more second trench gates 12 arranged between a plurality of first trench gates 11.

[0066] The distance Wp1 between the first second trench 18a and the second second trench 18b is equal to, for example, the distance Wp2 between the second second trench 18b and the third second trench 18c. However, the distance Wp1 between the first second trench 18a and the second second trench 18b may be different from the distance Wp2 between the second second trench 18b and the third second trench 18c.

[0067] The number of second trench gates 12 positioned between multiple first trench gates 11 can be any number of three or more.

[0068] The distance between the first trench 17a and the first second trench 18a is, for example, less than the sum of the distance Wp1 between the first second trench 18a and the second second trench 18b and the distance Wp2 between the second second trench 18b and the third second trench 18c.

[0069] In the semiconductor device 104, even when the distance between the first trench 17a and the second trench 17b is long, it is possible to suppress the lengthening of the distance between the first trench 17a and the first second trench 18a, and the distance between the second trench 17b and the third second trench 18c. When the distance between the first trench 17a and the first second trench 18a, and the distance between the second trench 17b and the third second trench 18c are long, holes accumulated in the region closer to each first trench 17 than to each second trench 18 are less likely to be discharged through the first region 1. According to the semiconductor device 104, even when the distance between the first trench 17a and the second first trench 17b is long, holes accumulated in the region closer to each first trench 17 than to each second trench 18 can be efficiently discharged through the first region 1.

[0070] In particular, in the semiconductor device 104, the distance Wp between two adjacent second trenches 18 is restricted to satisfy relation (1). Therefore, when there are two second trench gates 12 positioned between multiple first trench gates 11, if the distance between the first first trench 17a and the second first trench 17b is long, the distance between the first first trench 17a and the first second trench 18a, and the distance between the second first trench 17b and the third second trench 18c tend to be long. According to the semiconductor device 104, even if the distance between the first trench 17a and the second trench 17b is long, and the distance Wp between each of the multiple adjacent sets of second trenches 18 is set to satisfy relation (1), holes accumulated in the region close to each first trench 17 can be efficiently discharged without increasing the distance between the first trench 17a and the first second trench 18a, and the distance between the second trench 17b and the third second trench 18c.

[0071] The semiconductor device 104 may have the same configuration as the semiconductor device according to Embodiment 2, except that it includes three or more second trench gates 12 arranged between a plurality of first trench gates 11.

[0072] Embodiment 5. The semiconductor device according to Embodiment 5 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0073] Figure 15 is a cross-sectional view showing an example of a semiconductor device 105 according to Embodiment 5. As shown in Figure 15, the semiconductor device 105 differs from the semiconductor device 101 in that each of the plurality of first trench gates 11 has a plurality of electrode portions 13a, 13b within the first trench 17. In semiconductor device 105, it is sufficient that at least one first trench gate 11 has a plurality of electrode portions 13a, 13b. Also, at least one first trench gate 11 may have three or more electrode portions.

[0074] Multiple electrode portions 13a and 13b are arranged within the first trench 17 at intervals from each other in a third direction DR3 that intersects the first surface 10A. The insulating film 14 is provided to cover the multiple electrode portions 13a and 13b within the first trench 17. A portion of the insulating film 14 separating electrode portions 13a and 13b in the first trench gate 11 is located, for example, between charge storage regions 4 in a second direction DR2.

[0075] According to semiconductor device 105, noise can be reduced compared to semiconductor device 101. The method for forming the first trench gate 11 is not particularly limited. For example, an insulating film may be formed in the first trench 17, then an electrode portion 13a may be formed, then an insulating film may be formed on the electrode portion 13a, and then an electrode portion 13b may be formed on the insulating film. The first trench gate 11 can be formed in this way as well.

[0076] The semiconductor device 105 may have the same configuration as any of the semiconductor devices of Embodiments 2 to 4, except that each of the plurality of first trench gates 11 has a plurality of electrode portions 13a, 13b within the first trench 17.

[0077] Embodiment 6. The semiconductor device according to Embodiment 6 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0078] Figure 16 is a cross-sectional view showing an example of a semiconductor device 106 according to Embodiment 5. As shown in Figure 16, the semiconductor device 106 differs from the semiconductor device 101 in that, between the first trench gate 11a and the second trench gate, the contact area 7 is located only between a plurality of second trench gates 12.

[0079] The multiple first trench gates 11 include a first trench gate 11a and a second first trench gate 11b, as well as a third first trench gate 11c located on the opposite side of the first trench gate 11a from the second first trench gate 11b. The distance between the first first trench gate 11a and the second first trench gate 11b is longer than the distance between the first first trench gate 11a and the third first trench gate 11c.

[0080] Multiple second trench gates 12 are located only between the first trench gate 11a and the second trench gate 11b. None of the multiple second trench gates 12 are located between the first trench gate 11a and the third trench gate 11c.

[0081] The semiconductor device 106 includes a region RT where a bipolar transistor is formed and a region RS where charge is stored.

[0082] Region RT is located between the first trench gate 11a and the third trench gate 11c. Region RT includes a source region 6 and a contact region 7. In region RT, the source region 6 and the contact region 7 are electrically connected to the first electrode 21.

[0083] Region RS is located between the first trench gate 11a and the second trench gate 11b. Region RS does not include the source region 6. Region RS includes the contact region 7 only between the first trench gate 11a and the second trench gate 11b. In region RS, the contact region 7 is electrically connected to the first electrode 21.

[0084] In the semiconductor device 106, the charge (e.g., holes) accumulated in region RS can be efficiently discharged. Furthermore, in the semiconductor device 106, a region that is not electrically connected to the first electrode 21 (a region not in emitter contact) is formed between the first trench gate 11a and the first second trench gate 12a in region RS, so that input capacitance and feedback capacitance can be reduced.

[0085] <Modified example of semiconductor device 106> Figure 17 is a cross-sectional view showing a modified semiconductor device 107, which is a modified version of semiconductor device 106. As shown in Figure 17, semiconductor device 107 is the same as semiconductor device 106 in that the contact region 7 is located only between a plurality of second trench gates 12 between the first trench gate 11a and the second first trench gate. Therefore, semiconductor device 107 has the same effects as semiconductor device 106. On the other hand, semiconductor device 107 differs from semiconductor device 106 in that a third trench 19 is formed in the semiconductor substrate 10.

[0086] An insulating film 14 is formed on the inner wall surface of the third trench 19. The first electrode 21 is embedded in the space inside the insulating film 14 within the third trench 19.

[0087] The third trench 19 has a first portion 19a corresponding to the first trench 17, a second portion 19b corresponding to the second trench 18, and a third portion 19c that spans between the first and second portions. In the semiconductor substrate 10, the height of the first portion 19a relative to the bottom surface of the region located between two adjacent first trenches 17 is higher than the height of the third portion 19c relative to the bottom surface.

[0088] In the third trench 19, the relative depths of the first part 19a, the second part 19b, and the third part 19c from the first surface 10A are not particularly limited. The depth of the second part 19b from the first surface 10A is, for example, equivalent to the depth of the first part 19a from the first surface 10A. The depth of the second part 19b from the first surface 10A may be shallower or deeper than, for example, the depth of the first part 19a from the first surface 10A. The depth of the third part 19c from the first surface 10A is, for example, shallower than the depths of the first part 19a and the second part 19b from the first surface 10A.

[0089] The semiconductor devices 106 and 107 may have a configuration similar to any of the semiconductor devices in Embodiments 2 to 5, except that the contact area 7 is located only between a plurality of second trench gates 12 between the first trench gate 11a and the second trench gate.

[0090] Embodiment 7. The semiconductor device according to Embodiment 7 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0091] Figure 18 is a cross-sectional view showing an example of a semiconductor device 108 according to Embodiment 7. As shown in Figure 18, the semiconductor device 108 differs from the semiconductor device 101 in that the first region 1 is provided in contact with the contact region 7. In the semiconductor device 108, the first region 1 is formed by the diffusion of a second conductivity type impurity to form a channel dope layer 5 in regions other than region RA. In the semiconductor device 108, the impurity density of the first region 1 gradually increases towards the first surface 10A. In the semiconductor device 108, the first region 1 may have a first conductivity type or a second conductivity type.

[0092] Figures 19 to 21 are cross-sectional views showing an example of a method for manufacturing a semiconductor device 108 having a first region 1 of a second conductivity type. More specifically, Figures 19 to 21 show some steps in the process (S20) of implanting impurities to form the body layer 3, charge storage region 4, channel dope layer 5, and first region 1 from the first surface 10A of the semiconductor substrate. The method for manufacturing the semiconductor device 108 differs from the method for manufacturing the semiconductor device 101 in that, in the above process (S20), after the step shown in Figure 5, the steps shown in Figures 19 to 21 are performed instead of the steps shown in Figures 6 to 8.

[0093] As shown in Figure 19, in the manufacturing method of the semiconductor device 108, only the first conductivity type impurity 34 for forming the charge storage region 4 is injected into the semiconductor substrate 10 via the mask 201 (first mask), thereby forming the first injection region on the semiconductor substrate 10. Next, the mask 201 is removed from the first surface 10A.

[0094] Next, as shown in Figure 20, a mask 202 (second mask) having an opening 202A is formed on the first surface 10A. The opening 202A (second opening) of mask 202 is larger than the opening 201A (first opening) of mask 201. The opening 202A opens over a portion of the area where the first region 1 is to be formed and over the entire area where the channel dope layer 5 is to be formed. Next, a second conductivity type impurity 35 for forming the first region 1 and the channel dope layer 5 is injected into the semiconductor substrate 10 through the mask 202, forming a second injection region in the semiconductor substrate 10. A portion of the second conductivity type impurity 35 is injected on and within region RB.

[0095] Next, after step (S20), the semiconductor substrate 10 is heated to diffuse the impurities implanted in step (S20) into the semiconductor substrate 10 (S30). As a result, at least a portion of the second conductivity type impurities 35 that were implanted on region RB in step (S20) diffuse into region RB. Consequently, as shown in Figure 21, impurity regions 41, 43, 44, and 45 corresponding to the first region 1, body layer 3, charge storage region 4, and channel doped layer 5 are formed on the semiconductor substrate 10. The first region 1 and the channel doped layer 5 are formed from the second implantation region into which the second conductivity type impurities 35 were implanted.

[0096] According to the manufacturing method of the semiconductor device 108, the first region 1 can be formed simultaneously with the channel doping layer 5 in step (S20), and the number of steps for implanting the second conductivity type impurity can be reduced. As a result, the semiconductor device 108 can be manufactured at a lower cost compared to the semiconductor device 101.

[0097] <Modified example of the manufacturing method of semiconductor device 108> Figures 22 to 24 are cross-sectional views showing a first modified example of a method for manufacturing a semiconductor device 108 having a first region 1 of a second conductivity type. Figures 22 to 24 show a first modified example of a part of the above process (S20). In the first modified example of the method for manufacturing the semiconductor device 108, in the above process (S20), after the process shown in Figure 5, the processes shown in Figures 22 to 24 are performed instead of the processes shown in Figures 19 to 21.

[0098] As shown in Figure 22, in the first modified example, only the first conductivity type impurity 34 for forming the charge storage region 4 is injected into the semiconductor substrate 10 via the mask 201 (first mask), thereby forming the first injection region in the semiconductor substrate 10. Next, the mask 201 is removed from the first surface 10A.

[0099] Next, as shown in Figure 23, a second conductivity type impurity 35 for forming the first region 1 and the channel doped layer 5 is injected into the semiconductor substrate 10 without using a mask, thereby forming a second injection region in the semiconductor substrate 10. A portion of the second conductivity type impurity 35 is injected on and within region RB.

[0100] Next, after step (S20), the semiconductor substrate 10 is heated to diffuse the impurities implanted in step (S20) into the semiconductor substrate 10 (S30). As a result, at least a portion of the second conductivity type impurities 35 that were implanted on region RB in step (S20) diffuse into region RB. Consequently, as shown in Figure 24, impurity regions 41, 43, 44, and 45 corresponding to the first region 1, body layer 3, charge storage region 4, and channel doped layer 5 are formed on the semiconductor substrate 10. The first region 1 and the channel doped layer 5 are formed from the second implantation region into which the second conductivity type impurities 35 were implanted.

[0101] In the first modification, the first region 1 can be formed simultaneously with the channel doping layer 5 in process (S20), reducing the number of steps required to inject the second conductivity type impurity. Furthermore, in the first modification, the first region 1 can be formed simultaneously with the channel doping layer 5 without using the second mask used in the process shown in Figure 20. Therefore, the manufacturing cost of the semiconductor device 108 produced by the first modification can be further reduced compared to the manufacturing cost of the semiconductor device 108 produced by the manufacturing method shown in Figures 19 to 21.

[0102] Figures 25 to 27 are cross-sectional views showing a second modified method for manufacturing a semiconductor device 108, which has a first region 1 of a first conductivity type. Figures 25 to 27 show some of the steps in the above process (S20). In the second modified method, after the step shown in Figure 5 in the above process (S20), the steps shown in Figures 25 to 27 are performed instead of the steps shown in Figures 19 to 21.

[0103] As shown in Figure 25, in the second modified example, a mask 203 (third mask) having an opening 203A is formed on the first surface 10A. The opening 203A (third opening) of the mask 203 opens over a part of the area where the first region 1 is to be formed and over the entire area where the charge storage region 4 is to be formed. Next, a first conductivity type impurity 34 for forming the first region 1 and the charge storage region 4 is injected into the semiconductor substrate 10 through the mask 203, forming a fourth injection region in the semiconductor substrate 10. A portion of the first conductivity type impurity 34 is injected into region RB. Next, the mask 203 is removed from the first surface 10A.

[0104] Next, as shown in Figure 26, a mask 204 (fourth mask) having an opening 204A is formed on the first surface 10A. The opening 204A (fourth opening) of the mask 204 is smaller than the opening 203A of the mask 203. The opening 204A opens over a portion of the region where the channel dope layer 5 is to be formed. The mask 204 covers the entire region where the first region 1 is to be formed. Next, a second conductivity type impurity 35 for forming the channel dope layer 5 is injected into the semiconductor substrate 10 through the mask 204, forming a fifth injection region in the semiconductor substrate 10. A portion of the second conductivity type impurity 35 is not injected on or within region RB. Next, the mask 204 is removed from the first surface 10A.

[0105] Next, after step (S20), the semiconductor substrate 10 is heated to diffuse the impurities injected in step (S20) into the semiconductor substrate 10 (S30). As a result, at least a portion of the first conductivity type impurities 34 that were injected into and around region RB in step (S20) diffuse into region RB. A portion of the first conductivity type impurities 34 diffuses towards the first surface 10A. As a result, as shown in Figure 27, impurity regions 41, 43, 44, and 45 corresponding to the first region 1, body layer 3, charge storage region 4, and channel doped layer 5 are formed on the semiconductor substrate 10. Subsequently, steps (S40) to (S80) shown in Figure 4 are carried out, and as shown in Figure 28, the first region 1 is formed from impurity region 41 and the charge storage region 4 is formed from impurity region 44.

[0106] According to the manufacturing method of the semiconductor device 108, the first region 1 can be formed simultaneously with the charge storage region 4 in step (S20), and the number of steps for implanting the first conductivity type impurity can be reduced. As a result, the semiconductor device 108 can be manufactured at a lower cost compared to the semiconductor device 101.

[0107] The semiconductor device 108 may have the same configuration as any of the semiconductor devices of Embodiments 2 to 6, except that the first region 1 is provided so as to be in contact with the contact region 7. A method for manufacturing any of the semiconductor devices of Embodiments 2 to 6, in which the first region 1 has a second conductivity type, may include the steps shown in Figures 19 to 21, Figures 22 to 24, or Figures 25 to 27.

[0108] Embodiment 8. The semiconductor device according to Embodiment 8 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0109] Figure 29 is a cross-sectional view showing an example of a semiconductor device 109 according to Embodiment 8. As shown in Figure 29, the semiconductor device 109 differs from the semiconductor device 101 in that the opening width W2 of each of the multiple second trenches 18 is narrower than the opening width W1 of the first trench 17.

[0110] In the semiconductor device 109, the first trench 17 and the second trench 18 can be formed simultaneously.

[0111] Figure 30 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device 109. More specifically, Figure 30 shows some steps in forming a first trench gate 11 and a second trench gate 12 on a semiconductor substrate 10 (S60).

[0112] As shown in Figure 30, in step (S60), a trench mask 240 having an opening 240A (fifth opening) and a plurality of openings 240B (sixth opening) is formed on the first surface 10A. The opening 240A opens over the area where the first trench 17 is to be formed. The opening 240B opens over the area where the second trench 18 is to be formed. The opening width of the opening 240B in the second direction DR2 is narrower than the opening width of the opening 240A in the second direction DR2.

[0113] This process utilizes the property that, under the same etching conditions, the trench depth depends on the opening width of the trench mask. Figure 31 is a graph illustrating the property that, under the same etching conditions, the trench depth depends on the opening width of the trench mask. As shown in Figure 31, as the width (opening width) of the opening of the trench mask in the second direction DR2 increases, the depth of the trench formed by etching the semiconductor substrate 10 through the opening of the trench mask increases. In the manufacturing method of the semiconductor device 109, the property that the trench depth of the semiconductor substrate 10 depends on the trench mask opening width is evaluated in advance, and based on the evaluation results, the trench mask opening width corresponding to the trench depth to be formed is set. Then, a trench mask 240 having the preset opening width is formed on the first surface 10A, and this process is executed using the trench mask 240. As a result, as shown in Figure 30, a first trench 17 and a second trench 18 with different depths from the first surface 10A can be formed simultaneously using the same trench mask 240.

[0114] The manufacturing method for the semiconductor device 109 allows for a reduction in the number of steps within process (S60). As a result, the semiconductor device 109 can be manufactured at a lower cost compared to the semiconductor device 101.

[0115] Embodiment 9. The semiconductor device according to Embodiment 9 has the same configuration and effects as Embodiment 1 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0116] Figures 32 and 33 are schematic diagrams showing an example of a semiconductor device 110 according to Embodiment 9. As shown in Figures 32 and 33, the semiconductor device 110 differs from the semiconductor device 101 in that it is possible to apply different voltages to each of at least one first trench gate 11 and a plurality of second trench gates 12. As shown in Figure 33, the semiconductor device 110 differs from the semiconductor device 101 in that it includes a first gate pad 133 electrically connected to each of the plurality of first trench gates 11 and a second gate pad 134 electrically connected to each of the plurality of second trench gates 12. The first gate pad 133 and the second gate pad 134 are arranged, for example, spaced apart from each other in the second direction DR2. Each of the plurality of first trench gates 11 has a portion extending from the first gate pad 133 in the first direction DR1 and a comb-shaped portion connected to that portion and spaced apart from each other in the second direction DR2. Similarly, each of the multiple second trench gates 12 has a portion extending from the second gate pad 134 in the first direction DR1, and a comb-shaped portion connected to that portion and spaced apart from each other in the second direction DR2. The comb-shaped portion of the first trench gate 11 and the comb-shaped portion of the second trench gate 12 face each other in the first direction DR1 or the second direction DR2.

[0117] As shown in Figure 32, the semiconductor device 110 further comprises a drive circuit 50 that controls the switching operation of the bipolar transistors. The drive circuit 50 is capable of applying different voltages to each of at least one first trench gate 11 and a plurality of second trench gates 12. The drive circuit 50 includes a control unit 51 and wiring that electrically connects the control unit 51 to each of the first trench gate 11 and the second trench gates 12.

[0118] Figure 34 is a waveform diagram illustrating the relative magnitudes of the voltage V1 applied to the first trench gate 11 and the voltage V2 applied to the second trench gate 12, as well as the timing of the application of each voltage, in the semiconductor device 110 during turn-off, steady-state off, turn-on, and steady-state on. In Figure 34, the thick solid line shows the waveform of the voltage V1 applied to the first trench gate 11, and the thin solid line shows the waveform of the voltage V2 applied to the second trench gate 12.

[0119] As shown in Figure 34, in the semiconductor device 110, in the steady-state off state of the bipolar transistor, an off voltage V is applied to at least one first trench gate 11. G- A voltage is applied, and a first voltage V smaller than the threshold voltage of the second trench gate 12 is applied to each of the multiple second trench gates 12. dep- A voltage is applied. The threshold voltage of the second trench gate 12 is defined as the maximum potential difference between the second trench gate 12 and the first region 1 required to maintain a channel that can serve as a hole discharge path within region RA.

[0120] In the semiconductor device 110, in the steady-state ON state of the bipolar transistor, an ON voltage V is applied to at least one first trench gate 11. G+ A voltage is applied, and a second voltage greater than the threshold voltage is applied to each of the multiple second trench gates 12. Vdep+ It is applied.

[0121] When the conductivity type of the first region 1 is the second conductivity type (e.g., p-type), the threshold voltage of the second trench gate 12 corresponds to the flat-band voltage. The flat-band voltage depends on the work function difference between the constituent material of the electrode portion of the second trench gate 12 and the semiconductor material constituting the semiconductor substrate 10. For example, when the constituent material of the electrode portion of the second trench gate 12 is doped polysilicon and the semiconductor material constituting the semiconductor substrate 10 is Si, the source region 6 (emitter region) is p+ type, so the threshold voltage is approximately -0.8V. In this case, if the voltage applied to the second trench gate 12 is greater than the threshold voltage, the depletion layer spreads within region RA, and channels that can serve as hole discharge paths are not formed within region RA, thus suppressing hole discharge from region RA. On the other hand, when the voltage applied to the second trench gate 12 is less than or equal to the threshold voltage, hole discharge paths are formed within region RA, and hole discharge is promoted. As shown in Figure 34, the voltage applied to the second trench gate 12 during turn-off is below the threshold voltage, and this state is maintained during the steady-state off condition. As a result, hole ejection from region RA is promoted during turn-off and in the steady-state off condition.

[0122] If the conductivity type of the first region 1 is the first conductivity type (e.g., n-type), then, as an example, the n-type impurity density of the first region 1 is 1e 14 / cm 2 In this case, the threshold voltage of the second trench gate 12 is approximately -1.3V. If the voltage applied to the second trench gate 12 is greater than the threshold voltage, the depletion layer formed in the pnp structure within region RA suppresses the discharge of holes from region RA. On the other hand, when the voltage applied to the second trench gate 12 is less than or equal to the threshold voltage, a p-type channel along the second trench 18 is formed within the first region 1. As a result, the discharge of holes from region RA is promoted during turn-off and in the steady-state off state.

[0123] Figure 35 is a graph showing the simulation results regarding the relationship between the voltage applied to the trench gate and conduction loss in the steady-state ON condition. Figure 35 shows the evaluation results for Example 1, in which the conductivity type of the first region 1 is p-type, Example 2, in which the conductivity type of the first region 1 is n-type, Comparative Example 1, which is a CSTBT (Carrier Stored Trench-gate Bipolar Transistor: registered trademark) without a first region, and Comparative Example 2, which is an IGBT with an SBL (Super Body Layer) structure without a first region. The evaluation results for Examples 1 and 2 show the relationship between the voltage applied to the second trench gate 12 and conduction loss in the steady-state ON condition. As shown in Figure 35, the conduction loss of Examples 1 and 2 is about the same as that of Comparative Examples 1 and 2 in the ON condition when a positive voltage is applied to the second trench gate 12. As shown in Figure 35, the conduction loss in Examples 1 and 2 increases compared to the conduction loss in Comparative Examples 1 and 2 because the discharge of holes from region RA is promoted in the off state when a voltage below the threshold voltage is applied to the second trench gate 12.

[0124] In semiconductor device 110, the voltage applied to each of the second trench gates 12 can be freely set without being limited by the voltage applied to the first trench gate 11. As a result, semiconductor device 110 makes it even easier to achieve both suppression of conduction loss in the ON state and suppression of switching loss during turn-off compared to semiconductor device 101.

[0125] Embodiment 10. The semiconductor device according to Embodiment 10 has the same configuration and effects as Embodiment 9 unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0126] In the semiconductor device according to Embodiment 10, the drive circuit 50 can apply different voltages at different timings to each of the at least one first trench gate 11 and the plurality of second trench gates 12 when the bipolar transistor is switching.

[0127] Figure 36 is a waveform diagram illustrating the relative magnitudes of the voltages applied to the first trench gate 11 and the voltages applied to the second trench gate 12, as well as the timing of the application of each voltage, in the semiconductor device according to Embodiment 10 during turn-off, steady-state off, turn-on, and steady-state on. In Figure 36, the thick solid line shows the waveform of the voltage V1 applied to the first trench gate 11, and the thin solid line shows the waveform of the voltage V2 applied to the second trench gate 12.

[0128] As shown in Figure 36, preferably, when the turn is off, the first voltage V dep- After the off voltage V is applied to each of the multiple second trench gates 12, G- The second voltage V is applied to at least one first trench gate 11. More preferably, at turn-on, the second voltage V dep+ After the voltage V is applied to each of the multiple second trench gates 12, G+ This is applied to at least one first trench gate 11.

[0129] The drive circuit 50 includes a second turn-off circuit and a second turn-on circuit that are electrically connected to each of the multiple second trench gates 12. When the bipolar transistor is turned off, the voltage applied to the multiple second trench gates 12 is the second voltage V dep+ The first time difference from when the voltage changes until the voltage applied to at least one first trench gate 11 changes from the ON voltage is t off1 Let's assume that when the bipolar transistor is turned on, the voltage applied to the multiple second trench gates 12 is the first voltage V. dep- The second time difference from when the voltage changes until the voltage applied to at least one first trench gate 11 changes from the off voltage is t on1 The input capacitance of multiple second trench gates 12 is set to C. ies2 (Unit: pF), the first voltage is V dep- (Unit: V), second voltage is V dep+ (Unit: V), the gate resistor of the second turn-off circuit is RGoff2 (Unit: Ω), the gate resistor of the second turn-on circuit is R Gon2 (Unit: Ω), let α be an arbitrary coefficient greater than 0 and less than 1 (0 < α < 1). The arbitrary coefficient α is an index used to calculate the time difference by determining that the set value has been reached when the voltage applied to the first trench gate 11 or the second trench gate 12 reaches 100 * α% of the set value. The arbitrary coefficient α may be set to 0.95.

[0130] More preferably, the first time difference t off1 The following relationship (2) is satisfied, and the second time difference t on1 The following relationship (3) is satisfied.

[0131]

number

[0132]

number

[0133] Figure 37 shows the first time difference t. off1 and the switching loss E during turn-off off This graph shows the simulation results regarding the relationship with the second time difference t. Figure 38 shows the second time difference t. on1 and the switching loss E at turn-on on This graph shows the simulation results regarding the relationship. Figures 37 and 38 show the evaluation results for Examples 1, 2, and 3 and Comparative Examples 1 and 2. In Example 1, the conductivity type of the first region 1 is p-type. In Example 2, the conductivity type of the first region 1 is n-type. In Examples 1 and 2, the first time difference t off1 and the second time difference t on1 Under different conditions, the switching loss E off and switching loss E onThe following was evaluated. In Example 3, the conductivity type of the first region 1 is p-type, and the first trench gate 11 and the second trench gate 12 are each connected to a common gate pad, and the same voltage is applied to each at the same timing to perform turn-off and turn-on. In Comparative Examples 1 and 2, each trench gate is also connected to a common gate pad, and the same voltage is applied to each at the same timing to perform turn-off and turn-on. Therefore, in Example 3, Comparative Example 1 and Comparative Example 2, the first time difference t off1 and the second time difference t on1 It is zero.

[0134] As shown in Figures 37 and 38, the switching loss E for Example 3 is different from that of Comparative Examples 1 and 2. off and E on It was confirmed that the switching loss E can be reduced. In Examples 1 and 2, by performing the turn-off and turn-on operations in the manner shown in Figure 36, the switching loss E can be reduced compared to Example 3 and Comparative Examples 1 and 2. off and E on It was confirmed that this can be reduced.

[0135] In the semiconductor device according to Embodiment 10, a voltage can be applied to the second trench gate 12 during both turn-off and turn-on to activate the first region 1 with respect to the accumulation and discharge of holes described above, and then a voltage can be applied to the first trench gate 11. As a result, the semiconductor device according to Embodiment 10 can reduce switching losses compared to the semiconductor device 101 according to Embodiment 1.

[0136] Embodiment 11. The semiconductor device according to Embodiment 11 has the same configuration and effects as Embodiment 9 described above, unless otherwise specified. Therefore, the same reference numerals are used for components identical to those in Embodiment 1, and the descriptions are not repeated.

[0137] In the semiconductor device according to Embodiment 11, the drive circuit 50 can apply different voltages at different timings to each of the at least one first trench gate 11 and the plurality of second trench gates 12 when the bipolar transistor is switching.

[0138] Figure 39 is a waveform diagram illustrating the relative magnitudes of the voltage applied to the first trench gate 11 and the voltage applied to the second trench gate 12, as well as the timing of the application of each voltage, in the semiconductor device according to Embodiment 11 during turn-off, steady-state off, turn-on, and steady-state on. In Figure 39, the thick solid line shows the waveform of the voltage V1 applied to the first trench gate 11, and the thin solid line shows the waveform of the voltage V2 applied to the second trench gate 12.

[0139] As shown in Figure 39, in the semiconductor device according to Embodiment 11, when the bipolar transistor is turned off, a first voltage V is applied to each of the multiple second trench gates 12. dep- A third voltage V smaller than dpoff A voltage is applied, and then the first voltage V dep- The following is applied: At the time of the above turn-off, at least one first trench gate 11 is subjected to the first voltage V after the third voltage has been applied to each of the multiple second trench gates 12. dep- An off-voltage is applied before the current is applied.

[0140] In the semiconductor device according to Embodiment 11, when the bipolar transistor is turned on, a second voltage V is applied to each of the multiple second trench gates 12. dep+ The fourth voltage V is larger than this. dpon A voltage is applied, and then a second voltage V dep+ The following is applied. When the above turn-on occurs, at least one first trench gate 11 is connected to the second trench gate 12 after the fourth voltage has been applied to each of the multiple second trench gates 12. dep+ The ON voltage is applied before the POWER is applied.

[0141] The drive circuit 50 includes a second turn-off circuit and a second turn-on circuit that are electrically connected to each of the multiple second trench gates 12.

[0142] When a bipolar transistor is turned off, the first time difference between the time the voltage applied to the multiple second trench gates 12 changes from the second voltage and the time the voltage applied to at least one first trench gate 11 changes from the on voltage is defined as t off1 The third time difference between the time the voltage applied to at least one first trench gate 11 changes from the ON voltage and the time the voltage applied to multiple second trench gates 12 changes from the third voltage is defined as t. off2 Let's assume that.

[0143] When a bipolar transistor is turned on, the second time difference between the time the voltage applied to the multiple second trench gates 12 changes from the first voltage and the time the voltage applied to at least one first trench gate 11 changes from the off voltage is defined as t on1 The fourth time difference is defined as the time from when the voltage applied to at least one first trench gate 11 changes from the off voltage until the voltage applied to multiple second trench gates 12 changes from the fourth voltage. on2 Let's assume that.

[0144] The input capacitance of multiple second trench gates is C ies2 , the first voltage is V dep- , the second voltage is V dep+ The gate resistor of the second turn-off circuit is R Goff2 The gate resistor of the second turn-on circuit is R Gon2 Let α be an arbitrary coefficient greater than 0 and less than 1 (0 < α < 1). Let C be the input capacitance of at least one first trench gate 11. iesACT (Unit: F) The return capacity of at least one first trench gate 11 is C resACT (Unit: F) The gate resistor of the first turn-off circuit is R. GoffACT (Unit: Ω) The gate resistance of the first turn-on circuit is R. GonACT (Unit: Ω) Off-voltage is V G-、 On voltage is VG+ Let V be the peak voltage applied between the collector and emitter of the bipolar transistor. Cpeak (Unit: V) The saturation voltage applied between the collector and emitter of a bipolar transistor is V. CEsat (Unit: V) Let the Miller voltage of the bipolar transistor be V Gplateau (Unit: V) The pulse width of the voltage applied to at least one first trench gate 11 is T. p (Unit: s)

[0145] Preferably, the first time difference t off1 The above relation (2) satisfies the second time difference t on1 The above relation (3) is satisfied, and the third time difference t off2 The following relationship (4) is satisfied, and the fourth time difference t on2 The following relation (5) is satisfied.

[0146]

number

[0147]

number

[0148] Figure 40 shows the third voltage V applied to each of the multiple second trench gates 12 when they are turned off. dpoff and the switching loss E during turn-off off This graph shows the simulation results regarding the relationship. Figure 41 shows the fourth voltage V applied to each of the multiple second trench gates 12 when the device is turned on. dpon and the switching loss E at turn-on on This graph shows the simulation results regarding the relationship between the two factors.

[0149] In FIGS. 40 and 41, the evaluation results for Examples 1, 2, 3 and Comparative Examples 1, 2 are shown. In Example 1, the conductivity type of the first region 1 is p-type. In Example 2, the conductivity type of the first region 1 is n-type. In Examples 1 and 2, under conditions where the third voltage V dpoff and the fourth voltage V dpon are different from each other, the switching losses E off and the switching losses E on were evaluated. In Example 3, the conductivity type of the first region 1 is p-type, each of the first trench gate 11 and the second trench gate 12 is connected to a common gate pad, and the same voltage is applied to each at the same timing to perform turn-off and turn-on. For Comparative Examples 1 and 2 as well, each trench gate is connected to a common gate pad, and the same voltage is applied to each at the same timing to perform turn-off and turn-on.

[0150] As shown in FIGS. 40 and 41, for Example 3, it was confirmed that the switching losses E off and E on can be reduced compared to Comparative Examples 1 and 2. For Examples 1 and 2, by performing turn-off and turn-on operations in the manner shown in FIG. 39, it was confirmed that the switching losses E off and E on can be reduced compared to Example 3 and Comparative Examples 1 and 2. Also, for Examples 1 and 2, it was confirmed that the switching losses E off and E on both depend on the third voltage V dpoff and the fourth voltage V dpon applied to the second trench gate 12. At turn-off, it was confirmed that the switching loss can be significantly reduced by applying a voltage sufficiently smaller than the threshold voltage of the second trench gate 12 to the second trench gate 12. At turn-on, it was confirmed that the switching loss can be significantly reduced by applying a voltage sufficiently larger than the threshold voltage of the second trench gate 12 to the second trench gate 12.

[0151] Furthermore, in the semiconductor device according to Embodiment 11, the first voltage V dep- This can be set as the minimum voltage necessary to discharge holes in the steady-state off state as described above. Similarly, the second voltage V dep+ This voltage can be set as the minimum voltage necessary to accumulate holes as described above in the steady-state ON state. Therefore, the semiconductor device according to Embodiment 11 can reduce power consumption compared to the semiconductor device 101 according to Embodiment 1.

[0152] [Note] The various aspects of this disclosure are summarized in the appendix.

[0153] <Note 1> A semiconductor device comprising a bipolar transistor, A semiconductor substrate having a first surface and a second surface located on the opposite side of the first surface, The semiconductor substrate comprises at least one first trench gate and a plurality of second trench gates extending from the first surface toward the second surface, The first electrode is provided on the first surface, The aforementioned semiconductor substrate is Drift layer and A body layer located on the first surface side of the drift layer, A charge accumulation region located on the body layer, The first surface includes a source region and a contact region which are electrically connected to the first electrode, The depth of each of the plurality of second trench gates from the first surface is shallower than the depth of at least one first trench gate from the first surface. The at least one first trench gate penetrates the source region, the charge storage region, and the body layer to reach the drift layer, The aforementioned multiple second trench gates are arranged adjacent to each other with space between them. The semiconductor device comprises a body layer, a contact region, and a first region located between the body layer and the contact region and having a lower impurity density than the body layer, between a plurality of adjacent second trench gates.

[0154] <Note 2> The semiconductor device according to Appendix 1, wherein the impurity density profile of the first region in a direction intersecting the first surface has a minimum value.

[0155] <Note 3> The semiconductor device according to Appendix 1 or 2, wherein the semiconductor substrate further includes a channel-doped layer located between the contact region and the first region between a plurality of adjacent second trench gates and having a higher impurity density than the body layer.

[0156] <Note 4> The plurality of second trench gates are arranged within a plurality of second trenches formed on the first surface of the semiconductor substrate. The first region has the same conductivity type as the body layer, The interval between the plurality of second trenches is Wp, and the impurity density of the first region is N. A The intrinsic carrier density of the semiconductor material constituting the first region is n i The dielectric constant of the semiconductor material constituting the first region is ε, and the Boltzmann coefficient is k. B A semiconductor device as described in any one of the appendices 1 to 3, wherein, when the absolute temperature is T and the elementary charge is q, the spacing Wp between the plurality of second trenches satisfies the above relation (1).

[0157] <Note 5> The at least one first trench gate is a plurality of first trench gates arranged at intervals from one another. The semiconductor device according to Appendix 4, wherein the plurality of second trench gates are three or more second trench gates arranged between the plurality of first trench gates and are formed within three or more second trenches formed in the semiconductor substrate.

[0158] <Note 6> The semiconductor device according to any one of appendices 1 to 5, wherein the at least one first trench gate includes a plurality of electrode portions arranged at intervals from each other in a direction intersecting the first surface within the at least one first trench formed on the first surface of the semiconductor substrate, and a gate insulating film covering the plurality of electrode portions within the at least one first trench.

[0159] <Note 7> The at least one first trench gate comprises a first trench gate, a second trench gate provided on one side of the first trench gate, and a third trench gate provided on the opposite side of the first trench gate from the second trench gate. The distance between the first trench gate and the second trench gate is longer than the distance between the first trench gate and the third trench gate. The plurality of second trench gates are located only between the first trench gate and the second first trench gate. A semiconductor device according to any one of appendices 1 to 6, wherein, between the first trench gate and the second trench gate, the contact region is located only between the plurality of second trench gates.

[0160] <Note 8> In the semiconductor substrate, at least one third trench is formed between the first trench gate and the second trench gate. The first trench gate and one of the plurality of second trench gates are located within the third trench. The at least one third trench reaches the drift layer, The depth of the at least one third trench from the first surface is greater than the depth of each of the plurality of second trench gates from the first surface. The semiconductor device according to Appendix 7, wherein an insulating film is embedded below the plurality of second trench gates within at least one third trench.

[0161] <Note 9> The at least one first trench gate is located within at least one first trench formed on the first surface of the semiconductor substrate. The plurality of second trench gates are arranged within a plurality of second trenches formed on the first surface of the semiconductor substrate. The semiconductor device according to any one of the appendices 1 to 8, wherein the opening width of each of the plurality of second trenches is narrower than the opening width of at least one first trench.

[0162] <Note 10> The system further comprises a drive circuit that controls the switching operation of the bipolar transistor, The drive circuit is capable of applying different voltages to each of the at least one first trench gate and the plurality of second trench gates. In the steady-state off state of the bipolar transistor, an off voltage is applied to at least one first trench gate, and a first voltage smaller than the threshold voltage of the second trench gate is applied to each of the plurality of second trench gates. The semiconductor device according to any one of appendices 1 to 9, wherein, in the steady-state on-state of the bipolar transistor, an on-voltage is applied to at least one first trench gate, and a second voltage greater than the threshold voltage is applied to each of the plurality of second trench gates.

[0163] <Note 11> The semiconductor device according to Appendix 10, wherein the drive circuit is capable of applying different voltages at different timings to each of the at least one first trench gate and the plurality of second trench gates during the switching operation of the bipolar transistor.

[0164] <Note 12> When the bipolar transistor is turned off, the first voltage is applied to each of the plurality of second trench gates, and then the off voltage is applied to at least one of the first trench gates. The semiconductor device according to Appendix 11, wherein, when the bipolar transistor is turned on, the second voltage is applied to each of the plurality of second trench gates, and then the on voltage is applied to at least one of the first trench gates.

[0165] <Note 13> The drive circuit includes a second turn-off circuit and a second turn-on circuit, which are electrically connected to each of the plurality of second trench gates. When the bipolar transistor is turned off, the first time difference between the time the voltage applied to the plurality of second trench gates changes from the second voltage and the time the voltage applied to at least one first trench gate changes from the on voltage is t off1 When the bipolar transistor is turned on, the second time difference between the time the voltage applied to the plurality of second trench gates changes from the first voltage and the time the voltage applied to at least one of the first trench gates changes from the off voltage is defined as t on1 The input capacitance of the plurality of second trench gates is set to C ies2 , the first voltage is V dep- , the second voltage is V dep+ The gate resistor of the second turn-off circuit is R Goff2 The gate resistor of the second turn-on circuit is R Gon2 When α is an arbitrary coefficient greater than 0 and less than 1 (0 < α < 1), the first time difference t off1 The above relation (2) is satisfied, and the second time difference t on1 The semiconductor device described in Appendix 12 satisfies the above relation (3).

[0166] <Note 14> When the bipolar transistor is turned off, a third voltage smaller than the first voltage is applied to each of the plurality of second trench gates, and the first voltage is applied to at least one of the first trench gates after the third voltage is applied to each of the plurality of second trench gates but before the first voltage is applied. The semiconductor device according to Appendix 11, wherein, when the bipolar transistor is turned on, a fourth voltage greater than the second voltage is applied to each of the plurality of second trench gates before the second voltage is applied, and the on voltage is applied to at least one of the first trench gates after the fourth voltage is applied to each of the plurality of second trench gates but before the second voltage is applied.

[0167] <Note 15> The drive circuit includes a first turn-off circuit and a first turn-on circuit electrically connected to at least one first trench gate, and a second turn-off circuit and a second turn-on circuit electrically connected to each of the plurality of second trench gates. When the bipolar transistor is turned off, the first time difference between the time the voltage applied to the plurality of second trench gates changes from the second voltage and the time the voltage applied to at least one first trench gate changes from the on voltage is t off1 , the third time difference between the time the voltage applied to the at least one first trench gate changes from the ON voltage and the time the voltage applied to the plurality of second trench gates changes from the third voltage is t off2 year, When the bipolar transistor is turned on, the second time difference between the time the voltage applied to the plurality of second trench gates changes from the first voltage and the time the voltage applied to at least one of the first trench gates changes from the off voltage is t on1 , the fourth time difference is defined as the time from when the voltage applied to the at least one first trench gate changes from the off voltage until the voltage applied to the plurality of second trench gates changes from the fourth voltage.on2 year, The input capacitance of the plurality of second trench gates is C ies2 , the first voltage is V dep- , the second voltage is V dep+ The gate resistor of the second turn-off circuit is R Goff2 The gate resistor of the second turn-on circuit is R Gon2 Let α be an arbitrary coefficient greater than 0 and less than 1 (0 < α < 1), and further The input capacitance of the at least one first trench gate is C iesACT The return capacity of the at least one first trench gate is set to C resACT The gate resistor of the first turn-off circuit is R GoffACT The gate resistor of the first turn-on circuit is R GonACT , the off voltage is set to V G-、 The aforementioned ON voltage is V G+ The peak voltage applied between the collector and emitter of the bipolar transistor is V Cpeak The saturation voltage applied between the collector and emitter of the bipolar transistor is V CEsat The Miller voltage of the bipolar transistor is set to V Gplateau The pulse width of the voltage applied to the at least one first trench gate is set to t p In that case, The first time difference t off1 The above relation (2) is satisfied, and the second time difference t on1 The above relation (3) is satisfied, and the third time difference t off2 The above relation (4) is satisfied, and the fourth time difference t on2 The semiconductor device described in Appendix 14 satisfies the above relation (5).

[0168] <Note 16> A method for manufacturing a semiconductor device equipped with a bipolar transistor, A step of preparing a semiconductor substrate having a first surface and a first conductivity type, The first step involves forming a body layer having a second conductivity type different from the first conductivity type, a charge storage region having the first conductivity type, and a first region having either the first conductivity type or the second conductivity type on the first surface side of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the first step of forming the first region on a part of the body layer and forming the charge storage region on the remaining part of the body layer.

[0169] <Note 17> The first region has the second conductivity type, In the first step, a channel-doped layer having the second conductivity type is further formed on the first surface side of the charge storage region. The first step described above is, A first implantation step is performed in which impurity ions of the first conductivity type are implanted into the semiconductor substrate via a first mask to form a first implantation region. A second implantation step is performed after the first implantation step, in which impurity ions of the second conductivity type are implanted through a second mask different from the first mask to form a second implantation region. The process includes a diffusion step of heating the semiconductor substrate after the second injection step, The first mask has a first opening that opens onto the region where the charge accumulation region is to be formed, and covers the region where the first region is to be formed. The second mask has a second opening that is larger than the first opening and opens over a portion of the area where the first region is to be formed, and covers the remainder of the area where the first region is to be formed. A method for manufacturing a semiconductor device according to Appendix 16, wherein the charge storage region is formed from the first injection region in the first step, and the first region and the channel doped layer are formed from the second injection region.

[0170] <Note 18> The first region has the second conductivity type, In the first step, a channel-doped layer having the second conductivity type is further formed on the first surface side of the charge storage region. The first step described above is, A first implantation step is performed in which impurity ions of the first conductivity type are implanted into the semiconductor substrate via a first mask to form a first implantation region. A third implantation step is performed after the first implantation step, in which impurity ions of the second conductivity type are implanted to form a third implantation region. The process includes a diffusion step of heating the semiconductor substrate after the third injection step, The first mask has a first opening that opens onto the region where the charge accumulation region is to be formed, and covers the region where the first region is to be formed. A method for manufacturing a semiconductor device according to Appendix 16, wherein the charge storage region is formed from the first injection region in the first step, and the first region and the channel doped layer are formed from the third injection region.

[0171] <Note 19> The first region has the first conductivity type, In the first step, a channel-doped layer having the second conductivity type is further formed on the first surface side of the charge storage region. The first step described above is, A fourth implantation step is performed in which impurity ions of the first conductivity type are implanted into the semiconductor substrate via a third mask to form a fourth implantation region, A fifth implantation step is performed after the fourth implantation step, in which impurity ions of the second conductivity type are implanted through a fourth mask different from the third mask to form a fifth implantation region, The process includes a diffusion step of heating the semiconductor substrate after the fifth injection step, The third mask has a third opening that opens over a portion of the region where the charge storage region is to be formed and the region where the first region is to be formed, The fourth mask has a fourth opening smaller than the third opening and is formed to cover the entire area in which the first region is to be formed. A method for manufacturing a semiconductor device according to Appendix 16, wherein the charge storage region and the first region are formed from the fourth injection region in the first step, and the channel doped layer is formed from the fifth injection region.

[0172] <Note 20> The process further comprises a second step of forming at least one first trench and a plurality of second trenches extending from the first surface toward a second surface located opposite to the first surface, after the first step. In the second step, the semiconductor substrate is selectively etched from the first side using a trench mask having a fifth opening that opens on the region where at least one first trench is to be formed, and a plurality of sixth openings that open on the regions where a plurality of second trenches are to be formed. A method for manufacturing a semiconductor device according to any one of the appendices 16 to 19, wherein the opening width of each of the sixth openings is narrower than the opening width of the fifth opening.

[0173] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of symbols]

[0174] 1 First region, 2 Drift layer, 3 Body layer, 4 Charge storage region, 5 Channel dope layer, 6 Source region, 7 Contact region, 8 Buffer layer, 9 Collector layer, 10 Semiconductor substrate, 10A First surface, 10B Second surface, 11,11a,11b,11c First trench gate, 12,12a,12b,12c Second trench gate, 13,13a,13b,15 Electrode region, 14,16 Insulating film, 17,17a,17b First trench, 18,18a,18b,18c Second trench, 19 Third trench, 19a First part, 19b Second part, 19c Third part, 21 First electrode, 22 Second electrode, 23 Interlayer insulating film, 33,35 Second conductivity type impurity, 34 First conductivity type impurity, 41,43,44,45 Impurity region, 50 drive circuit, 51 control unit, 101, 102, 104, 105, 106, 107, 108, 109, 110 semiconductor device, 120 element region, 131 gate pad, 133 first gate pad, 134 second gate pad, 201, 202, 203, 204, 211, 221 mask, 240 trench mask.

Claims

1. A semiconductor device comprising a bipolar transistor, A semiconductor substrate having a first surface and a second surface located on the opposite side of the first surface, The semiconductor substrate comprises at least one first trench gate and a plurality of second trench gates extending from the first surface toward the second surface, The first electrode is provided on the first surface, The aforementioned semiconductor substrate is Drift layer and A body layer located on the first surface side of the drift layer, A charge accumulation region located on the body layer, The first surface includes a source region and a contact region which are electrically connected to the first electrode, The depth of each of the plurality of second trench gates from the first surface is shallower than the depth of at least one first trench gate from the first surface. The at least one first trench gate penetrates the source region, the charge storage region, and the body layer to reach the drift layer, The aforementioned plurality of second trench gates are arranged adjacent to each other with a gap between them. The semiconductor device comprises a body layer, a contact region, and a first region located between the body layer and the contact region and having a lower impurity density than the body layer, between a plurality of adjacent second trench gates.

2. The semiconductor device according to claim 1, wherein the impurity density profile of the first region in a direction intersecting the first surface has a minimum value.

3. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate further includes a channel-doped layer located between the contact region and the first region between a plurality of adjacent second trench gates and having a higher impurity density than the body layer.

4. The plurality of second trench gates are arranged within a plurality of second trenches formed on the first surface of the semiconductor substrate. The first region has the same conductivity type as the body layer, The interval between the plurality of second trenches is Wp, and the impurity density of the first region is N. A , the intrinsic carrier density of the semiconductor material constituting the first region is n i The dielectric constant of the semiconductor material constituting the first region is ε, and the Boltzmann coefficient is k. B The semiconductor device according to claim 1 or 2, wherein, when the absolute temperature is T and the elementary charge is q, the spacing Wp between the plurality of second trenches satisfies the following relation (1). [Math 1]

5. The at least one first trench gate is a plurality of first trench gates arranged at intervals from one another. The semiconductor device according to claim 4, wherein the plurality of second trench gates are three or more second trench gates arranged between the plurality of first trench gates and are formed within three or more second trenches formed in the semiconductor substrate.

6. The semiconductor device according to claim 1 or 2, wherein the at least one first trench gate includes a plurality of electrode portions arranged at intervals from each other in a direction intersecting the first surface within the at least one first trench formed on the first surface of the semiconductor substrate, and an insulating film covering the plurality of electrode portions within the at least one first trench.

7. The at least one first trench gate comprises a first trench gate, a second trench gate provided on one side of the first trench gate, and a third trench gate provided on the opposite side of the first trench gate from the second trench gate. The distance between the first trench gate and the second trench gate is longer than the distance between the first trench gate and the third trench gate. The plurality of second trench gates are arranged only between the first trench gate and the second first trench gate. The semiconductor device according to claim 1 or 2, wherein, between the first trench gate and the second trench gate, the contact region is located only between the plurality of second trench gates.

8. In the semiconductor substrate, at least one third trench is formed between the first trench gate and the second trench gate. The first trench gate and one of the plurality of second trench gates are arranged within the third trench. The at least one third trench reaches the drift layer, The depth of the at least one third trench from the first surface is greater than the depth of each of the plurality of second trench gates from the first surface. The semiconductor device according to claim 7, wherein an insulating film is embedded in at least one third trench below the plurality of second trench gates.

9. The at least one first trench gate is located within at least one first trench formed on the first surface of the semiconductor substrate. The plurality of second trench gates are arranged within a plurality of second trenches formed on the first surface of the semiconductor substrate. The semiconductor device according to claim 1 or 2, wherein the opening width of each of the plurality of second trenches is narrower than the opening width of at least one first trench.

10. The system further comprises a drive circuit that controls the switching operation of the bipolar transistor, The drive circuit is capable of applying different voltages to each of the at least one first trench gate and the plurality of second trench gates. In the steady-state off state of the bipolar transistor, an off voltage is applied to at least one first trench gate, and a first voltage smaller than the threshold voltage of the plurality of second trench gates is applied to each of the plurality of second trench gates. The semiconductor device according to claim 1 or 2, wherein in the steady-state on-state of the bipolar transistor, an on-voltage is applied to at least one first trench gate, and a second voltage greater than the threshold voltage is applied to each of the plurality of second trench gates.

11. The semiconductor device according to claim 10, wherein the drive circuit is capable of applying different voltages at different timings to each of the at least one first trench gate and the plurality of second trench gates when the bipolar transistor is switching.

12. When the bipolar transistor is turned off, the first voltage is applied to each of the plurality of second trench gates, and then the off voltage is applied to at least one of the first trench gates. The semiconductor device according to claim 11, wherein, when the bipolar transistor is turned on, the second voltage is applied to each of the plurality of second trench gates, and then the on voltage is applied to at least one of the first trench gates.

13. The drive circuit includes a second turn-off circuit and a second turn-on circuit, which are electrically connected to each of the plurality of second trench gates. When the bipolar transistor is turned off, a first time difference t from when the voltage applied to the plurality of second trench gates changes from the second voltage until the voltage applied to the at least one first trench gate changes from the on voltage off1 When the bipolar transistor is turned on, a second time difference t from when the voltage applied to the plurality of second trench gates changes from the first voltage until the voltage applied to the at least one first trench gate changes from the off voltage on1 The input capacitance of the plurality of second trench gates is C ies2 The first voltage is V dep- The second voltage is V dep+ The gate resistance of the second turn-off circuit is R Goff2 The gate resistance of the second turn-on circuit is R Gon2 When an arbitrary coefficient α greater than 0 and less than 1 (0 < α < 1) is defined, the first time difference t off1 satisfies the following relational expression (2), and the second time difference t on1 satisfies the following relational expression (3). The semiconductor device according to claim 12 [Math 2] [Math 3]

14. When the bipolar transistor is turned off, a third voltage smaller than the first voltage is applied to each of the plurality of second trench gates, and then the first voltage is applied to at least one of the first trench gates after the third voltage is applied to each of the plurality of second trench gates but before the first voltage is applied. The semiconductor device according to claim 11, wherein, when the bipolar transistor is turned on, a fourth voltage greater than the second voltage is applied to each of the plurality of second trench gates before the second voltage is applied, and the on voltage is applied to at least one of the first trench gates after the fourth voltage is applied to each of the plurality of second trench gates but before the second voltage is applied.

15. The drive circuit includes a first turn-off circuit and a first turn-on circuit electrically connected to at least one first trench gate, and a second turn-off circuit and a second turn-on circuit electrically connected to each of the plurality of second trench gates. When the bipolar transistor is turned off, the first time difference between the time the voltage applied to the plurality of second trench gates changes from the second voltage and the time the voltage applied to at least one first trench gate changes from the on voltage is t off1 , the third time difference from the time the voltage applied to the at least one first trench gate changes from the ON voltage until the voltage applied to the plurality of second trench gates changes from the third voltage is t off2 year, When the bipolar transistor is turned on, the second time difference between the time the voltage applied to the plurality of second trench gates changes from the first voltage and the time the voltage applied to at least one of the first trench gates changes from the off voltage is t on1 , the fourth time difference is defined as the time from when the voltage applied to at least one first trench gate changes from the off voltage until the voltage applied to the plurality of second trench gates changes from the fourth voltage. on2 year, The input capacitance of the plurality of second trench gates is C ies2 , the first voltage is V dep- , the second voltage is V dep+ The gate resistor of the second turn-off circuit is R Goff2 The gate resistor of the second turn-on circuit is R Gon2 Let α be an arbitrary coefficient greater than 0 and less than 1 (0 < α < 1), and further The input capacitance of the at least one first trench gate is C iesACT The return capacity of the at least one first trench gate is set to C resACT The gate resistor of the first turn-off circuit is R GoffACT The gate resistor of the first turn-on circuit is R GonACT , the off voltage is set to V G-、 The aforementioned ON voltage is V G+ The peak voltage applied between the collector and emitter of the bipolar transistor is V. Cpeak The saturation voltage applied between the collector and emitter of the bipolar transistor is V. CEsat The Miller voltage of the bipolar transistor is set to V Gplateau The pulse width of the voltage applied to the at least one first trench gate is set to T. p In that case, The first time difference t off1 The following relation (2) satisfies, and the second time difference t on1 The following relation (3) is satisfied, and the third time difference t off2 The following relation (4) satisfies, and the fourth time difference t on2 The semiconductor device according to claim 14, satisfying the following relation (5). [Math 2] [Math 3] [Math 4] [Math 5]

16. A method for manufacturing a semiconductor device equipped with a bipolar transistor, A step of preparing a semiconductor substrate having a first surface and a first conductivity type, The first step involves forming a body layer having a second conductivity type different from the first conductivity type, a charge storage region having the first conductivity type, and a first region having either the first conductivity type or the second conductivity type on the first surface side of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the first step of forming the first region on a part of the body layer and forming the charge storage region on the remaining part of the body layer.

17. The first region has the second conductivity type, In the first step, a channel-doped layer having the second conductivity type is further formed on the first surface side of the charge storage region. The first step is, A first implantation step is performed in which impurity ions of the first conductivity type are implanted into the semiconductor substrate via a first mask to form a first implantation region. A second implantation step is performed after the first implantation step, in which impurity ions of the second conductivity type are implanted through a second mask different from the first mask to form a second implantation region. The process includes a diffusion step of heating the semiconductor substrate after the second injection step, The first mask has a first opening that opens onto the region where the charge accumulation region is to be formed, and covers the region where the first region is to be formed. The second mask has a second opening that is larger than the first opening and opens over a portion of the area where the first region is to be formed, and covers the remainder of the area where the first region is to be formed. The method for manufacturing a semiconductor device according to claim 16, wherein the charge storage region is formed from the first injection region in the first step, and the first region and the channel doped layer are formed from the second injection region.

18. The first region has the second conductivity type, In the first step, a channel-doped layer having the second conductivity type is further formed on the first surface side of the charge storage region. The first step is, A first implantation step is performed in which impurity ions of the first conductivity type are implanted into the semiconductor substrate via a first mask to form a first implantation region. A third implantation step is performed after the first implantation step, in which impurity ions of the second conductivity type are implanted to form a third implantation region. The process includes a diffusion step of heating the semiconductor substrate after the third injection step, The first mask has a first opening that opens onto the region where the charge accumulation region is to be formed, and covers the region where the first region is to be formed. The method for manufacturing a semiconductor device according to claim 16, wherein the charge storage region is formed from the first injection region in the first step, and the first region and the channel doped layer are formed from the third injection region.

19. The first region has the first conductivity type, In the first step, a channel-doped layer having the second conductivity type is further formed on the first surface side of the charge storage region. The first step is, A fourth implantation step is performed in which impurity ions of the first conductivity type are implanted into the semiconductor substrate via a third mask to form a fourth implantation region. A fifth implantation step is performed after the fourth implantation step, in which impurity ions of the second conductivity type are implanted through a fourth mask different from the third mask to form a fifth implantation region. The process includes a diffusion step of heating the semiconductor substrate after the fifth injection step, The third mask has a third opening that opens over a region in which the charge accumulation region is to be formed and a portion of the region in which the first region is to be formed. The fourth mask has a fourth opening smaller than the third opening and is formed to cover the entire area in which the first region is to be formed. The method for manufacturing a semiconductor device according to claim 16, wherein the charge storage region and the first region are formed from the fourth injection region in the first step, and the channel doped layer is formed from the fifth injection region.

20. The process further comprises a second step of forming at least one first trench and a plurality of second trenches extending from the first surface toward a second surface located opposite to the first surface, after the first step. In the second step, the semiconductor substrate is selectively etched from the first side using a trench mask having a fifth opening that opens on the region where at least one first trench is to be formed, and a plurality of sixth openings that open on the regions where a plurality of second trenches are to be formed. The method for manufacturing a semiconductor device according to any one of claims 16 to 19, wherein the opening width of the sixth opening is narrower than the opening width of the fifth opening.

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