Quantum computation integral probability extraction

Abstract

This invention provides quantum circuits and methods for quantum computational integral stochastic extraction. [Solution] The method may include discretizing a partial differential equation using initial value conditions to obtain a linear equation. The method may include scaling at least one discretization parameter of the linear equation to obtain a scaled linear equation. The method may include applying a quantum algorithm to the scaled linear equation to obtain a system of linear equations with a pre-formed matrix. The method may further include performing a quantum singular value transformation to obtain a solution by applying the inverse of the pre-formed matrix. The method may further include extracting integral probabilities from the solution using integral interpolation.

Description

[Technical Field]

[0001] This disclosure generally relates to quantum circuits and methods for integral stochastic sampling. [Background technology]

[0002] Quantum computing devices can contain qubits ("qubits") that can represent information as 1, 0, or both 1 and 0 simultaneously. Quantum algorithms implemented on quantum computing devices can leverage qubit properties such as superposition and entanglement to solve certain types of problems (e.g., differential equations, optimization, graph partitioning, quadratic programming, etc.) more efficiently and / or accurately than classical computers (e.g., providing a quantum advantage). Pre-shaping quantum algorithms can reduce the number of qubits used to implement them and / or improve the quantum advantage.

[0003] The subject matter claimed in this disclosure is not limited to embodiments that solve any defects or embodiments that operate only in the environment described above. Rather, this background is provided solely to illustrate exemplary technical aspects in which some embodiments described in this disclosure may be implemented. [Overview of the project] [Means for solving the problem]

[0004] According to one aspect of one embodiment, the method may include discretizing a partial differential equation using an initial value condition to obtain a linear equation. In some embodiments, the method may include scaling at least one discretization parameter of the linear equation to obtain a scaled linear equation. The method may also include applying a quantum algorithm to the scaled linear equation to obtain a system of linear equations with a pre-formed matrix. In some embodiments, the method may include performing a quantum singular value transformation (QSVT) using a quantum circuit in a quantum computing device to obtain a solution by applying the inverse of the pre-formed matrix. The method may further include extracting integral probabilities from the solution using integral interpolation.

[0005] The objectives and advantages of the embodiments are realized and achieved at least by the elements, features, and combinations specifically indicated in the claims. It should be understood that the above general description and the following detailed description are for illustrative purposes only and do not limit the claimed invention. [Brief explanation of the drawing]

[0006] Exemplary embodiments are described and explained with further specificity and detail using the accompanying drawings.

[0007] [Figure 1] This figure shows an exemplary operating environment for an integral probability sampling system according to one or more embodiments of the present disclosure.

[0008] [Figure 2] This disclosure illustrates an exemplary integral probability sampling system according to one or more embodiments thereof.

[0009] [Figure 3] The present disclosure illustrates an exemplary quantum circuit according to one or more embodiments.

[0010] [Figure 4] A flowchart illustrating an exemplary method for extracting integral probabilities according to one or more embodiments of the present disclosure is shown.

[0011] [Figure 5] This document shows a block diagram of an exemplary computing system according to one or more embodiments of the present disclosure. [Modes for carrying out the invention]

[0012] Quantum computing devices use quantum bits, or "qubits," which can be configured to store values ​​of 0, 1, or a superposition of both 0 and 1. Because qubits can store multiple values ​​simultaneously (for example, existing in multiple states), quantum computing devices may be able to perform calculations faster and / or more accurately than classical computers that use only classical bits that can store either 0 or 1. As a result, quantum computing devices can improve computation in a variety of technological fields, such as finance, physics, chemistry, drug discovery, or machine learning.

[0013] Integral stochastic sampling can be involved in determining the probability (for example, based on the amplitude of the quantum system) that a quantum system is in a particular state after measurement. For example, in quantum algorithms (e.g., Grover's algorithm), integral stochastic sampling can be used to find and isolate the amplitude of a target state or solution. Integral stochastic sampling can improve the efficiency of quantum algorithms for performing tasks such as search and optimization by enabling quantum computing devices to converge to solutions more quickly than classical and / or traditional quantum methods.

[0014] Integral stochastic sampling can be difficult and / or impractical because quantum states are stochastic and may require numerous measurements to accurately determine a particular amplitude. For example, accurately measuring low-probability states can be inefficient because many iterations may be required to achieve statistically meaningful results. Integral stochastic sampling can also suffer from noise and / or errors introduced by quantum decoherence. Therefore, it may be beneficial to apply integral stochastic sampling methods that reduce the number of qubits used in a quantum circuit, because using fewer qubits can reduce noise.

[0015] Some embodiments of the present disclosure may describe a method and / or system for extracting an integral probability using a quantum computing device. For example, the present disclosure may describe a method for discretizing a partial differential equation using initial value conditions to obtain a linear equation. In these and other embodiments, at least one discretization parameter of the linear equation may be scaled to obtain a scaled linear equation. In some embodiments, a quantum algorithm may be applied to the scaled linear equation to obtain a system of linear equations with a preconditioned matrix. In these and other embodiments, quantum singular value transformation (QSVT) may be used by a quantum circuit of a quantum computing device to apply the inverse of the preconditioned matrix to obtain a solution. The integral probability may be extracted from the solution using integral interpolation. In some embodiments, the computing process and / or performance of a quantum computing device may be improved by extracting an integral probability more efficiently and / or accurately in accordance with the present disclosure. For example, integral probability extraction may improve a quantum computing process used for financial option pricing by reducing the number of qubits used to solve a differential equation that models the value of a financial asset over time. In some embodiments, the method of the present disclosure may reduce the number of sequential iterations in which a quantum algorithm may be executed on a quantum circuit of a quantum computing device to extract an integral probability with an accuracy exceeding a threshold (e.g., to achieve a specified statistical confidence level). Embodiments of the present disclosure are described with reference to the accompanying drawings.

[0016] Figure 1 shows an exemplary operating environment 100 of an integral probability sampling system according to one or more embodiments of the present disclosure. The operating environment 100 includes a discretization module 104, a scaling module 108, a linear simultaneous equation solver module 112, a quantum singular value transformation module 116 (QSVT module 116), and an integral interpolation module 120, which are configured to take a partial differential equation 102, a linear equation 106, a scaled linear equation 110, a linear simultaneous equation 114 with a pre-formed matrix, a solution 118, and an integral probability 122 as input and / or output.

[0017] In some embodiments, the discretization module 104, the scaling module 108, the linear simultaneous equation solver module 112, the QSVT module 116, and / or the integral interpolation module 120 (collectively, the “Computing Modules”) may include code and routines configured to cause the execution of the operations described with respect to these modules. In some embodiments, one or more of the Computing Modules may be implemented using hardware including one or more processors, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a parallel processing unit (PPU), a microprocessor (for example, to perform or control one or more operations), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an accelerator (for example, a deep learning accelerator (DLA)), one or more programmable vision accelerators (PVAs) which may include one or more vector processing units (VPUs), one or more direct memory access (DMA) systems, one or more pixel processing engines (PPEs), and / or other processor types. In these and other embodiments, the Computing Modules may be implemented using a combination of hardware and software. In this disclosure, operations described as being performed by computing modules may include operations that those modules can be instructed to perform on one or more corresponding computing systems. These computing modules may be configured to perform a series of operations with respect to a partial differential equation 102, a linear equation 106, a scaled linear equation 110, a system of linear equations 114 with a pre-formed matrix, a solution 118, and an integral probability 122. In these or other embodiments, computing modules may be implemented by one or more quantum circuits, as described in more detail with respect to Figure 3, and / or by one or more computing systems, as described in more detail with respect to Figures 2 and / or 5.

[0018] In some embodiments, the partial differential equation 102 can be a mathematical equation that includes two or more independent variables, an unknown function that depends on those independent variables, and partial derivatives of the unknown function with respect to the independent variables (e.g., an exact formula or a function without an exact relationship that can be solved using given data and / or constraints). In some embodiments, the partial differential equation 102 can be a parabolic differential equation. The partial differential equation 102 can be any equation that models a process or phenomenon in which a quantity changes over time. For example, the partial differential equation 102 can model how heat (e.g., as measured by temperature) diffuses through a given region over time. In some embodiments, the partial differential equation 102 can model the change in the value of a financial asset over time. For example, the partial differential equation 102 can be based on the Black - Scholes model for pricing financial options. In some embodiments, the Black - Scholes model can use a differential equation to describe how the price of a financial option changes over time by considering factors such as asset price, volatility, time to expiration, interest rate, etc. In some embodiments, the partial differential equation 102 can be based on the Heston model and / or another financial option pricing model that incorporates stochastic volatility.

[0019] In some embodiments, the partial differential equation 102 may be a modified Black-Scholes equation for pricing Asian options, such as Equation 1 below. Asian options may include financial options in which the final payoff depends on the average price of the underlying asset over a certain period of time, compared to other financial options in which the payoff depends only on the price of the underlying asset at maturity. Asian options may be used in commodity derivatives markets because they may be less volatile than other financial options (e.g., American and European options). Traditional methods for valuing Asian options using the Black-Scholes framework have typically involved complex analytical and / or numerical methods, such as Monte Carlo simulations.

[0020]

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[0021] With respect to Equation 1, in some embodiments, ψ may represent the adjusted payoff, η may represent the average ratio of the average strike option to the underlying asset (e.g., I / ST), or the average ratio of the average minus strike to the average rate option (e.g., (IK) / ST), S may represent the price of the underlying asset, K may represent the strike price for the average rate Asian option, τ1 may represent the time variable after applying time reversal (e.g., τ1=Tt), ​​and W(τ1) is the average

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[0022] In some embodiments, time reversal techniques can be applied to the partial differential equation 102 to transform it into a more solvable form. For example, payoffs for different types of Asian options (e.g., average rate and average strike) may be defined at the outset so that the payoffs drive the solution of the partial differential equation 102. In these and other embodiments, once the partial differential equation 102 is solved, the value of the financial option may be calculated using an equation that incorporates the average price of the underlying asset adjusted for time and dividends. Thus, in some embodiments, applying time reversal to the partial differential equation 102 can improve the accuracy of pricing Asian options using the partial differential equation 102.

[0023] In some embodiments, quantum preconditioning for solving a system of linear equations can be applied to the partial differential equation 102. For example, quantum preconditioning can be used to improve the state of the system of linear equations by reformulating them into an equivalent system with a smaller condition number, thereby making the partial differential equation 102 less sensitive to small changes and / or input errors, and therefore easier to solve.

[0024] In some embodiments, the discretization module 104 may discretize the partial differential equation 102 to obtain the linear equation 106. For example, the discretization module 104 may discretize the time derivative of the partial differential equation 102 in Equation 1. In some embodiments, the discretization module 104 may also discretize the first derivative and / or the second derivative of the ratio. In some embodiments, the discretization module 104 may be included in a quantum computing device and may be implemented by a quantum circuit.

[0025] In some embodiments, the discretization module 104 may discretize the partial differential equation 102 using a finite difference method. For example, the discretization module 104 may discretize the time derivative of the partial differential equation 102 using a central difference method with Dirichlet (e.g., fixed) boundary conditions. In some embodiments, the discretization module 104 may perform discretization using a quantum circuit of a quantum computing device. For example, the discretization module 104 may use a quantum circuit 300, which is further described below with respect to Figure 3.

[0026] In some embodiments, the linear equation 106 may be part of a system of linear equations (e.g., a system of linear equations) that approximates the behavior of the partial differential equation 102 on a discretized domain. In some embodiments, solving the linear equation 106 may require several terabytes or petabytes of data. In some embodiments, the linear equation 106 may be implicitly defined and therefore may require relatively large computational resources to solve, which may be impractical on classical computing devices alone.

[0027] In some embodiments, the scaling module 108 may scale at least one discretization parameter of the linear equation 106 to obtain a scaled linear equation 110. For example, the scaling module 108 may transform at least one variable of the linear equation 106 using a scalar (e.g., by multiplying by a constant). In some embodiments, the linear equation 106 is

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[0028] In some embodiments, a system of linear equations with a pre-formed matrix 114 can be obtained by applying a quantum algorithm configured to solve a system of linear equations to a scaled linear equation 110 using a linear system of linear equations solver module 112. For example, the Harrow-Hassidim-Lloyd (HHL) algorithm could be such a quantum algorithm. In some embodiments, the quantum algorithm can be exponentially faster than a classical algorithm for the same task (e.g., solving the scaled linear equation 110). In some embodiments, the linear system of linear equations solver module 112 may also apply a quantum computing device to the quantum algorithm by encoding the scaled linear equation 110 as a quantum state, estimating eigenvalues ​​of the matrix using quantum phase estimation, and / or performing controlled rotations based on the eigenvalues ​​to obtain a solution vector (e.g., the pre-formed matrix 114).

[0029] In some embodiments, the solution 118 may be obtained by performing a quantum singular value transformation (QSVT) using the QSVT module 116 to apply the inverse of a pre-formed matrix 114. In some embodiments, the QSVT module 116 may apply quantum signal processing. In some embodiments, the QSVT module 116 may use the circuitry of a quantum computing device to perform the QSVT. For example, the QSVT module 116 may use the quantum circuit 300, which is further described below with respect to Figure 3. In some embodiments, the solution 118 may include quantum states representing polynomial transformations of the pre-formed matrix 114. In these and other embodiments, the solution 118 may be stored in the quantum memory of a quantum computing device.

[0030] In some embodiments, the integral probability 122 can be extracted (for example, obtained) from the solution 118 using the integral interpolation module 120. In some embodiments, the integral interpolation module 120 can be configured to extract the integral probability 122 from a smooth function. For example, the integral probability 122 is

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[0031] In some embodiments, the integral interpolation module 120 may perform Chebyshev interpolation on the solution 118. In some embodiments, the integral interpolation module 120 may perform mock Chebyshev interpolation (for example, a technique that mimics Chebyshev interpolation of data containing a subset of evenly spaced collocation points) on the solution 118. In some embodiments, the integral interpolation may be binary decomposition. For example, the integral interpolation may be squared amplitude integral estimation using binary segmentation. In some embodiments, the integral probability 122 may be used to determine the price of a financial option. In some embodiments, the integral interpolation module 120 may be configured to implement the following equation 2.

[0032]

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[0033] With respect to Equation 2, in some embodiments, V perta' may correspond to a perturbed Chebyshev-Vandermonde matrix, a' may correspond to a vector of states after applying the perturbation, and f' may correspond to at least one integral sample with an error (such as one introduced from finite resource amplitude estimation). In some embodiments, the solution to the system of linear equations using Equation 2 may be an interpolating polynomial. In these and other embodiments, the interpolating polynomial may be used to price at least one financial option.

[0034] Modifications, additions, or omissions may be made to the operating environment 100 without departing from the scope of this disclosure. For example, the designation of different elements in the manner described is intended to help illustrate the concepts described herein, and is not intended to limit it. For example, in some embodiments, the operating environment 100 may be described in a particular manner described, but such description is not intended to limit it. Furthermore, the operating environment 100 may include any number of other elements or may be implemented in other systems or contexts other than those described.

[0035] Figure 2 shows an integral probability extraction system 200 (System 200). System 200 may include a classical computing device 204 for obtaining a partial differential equation 202. The classical computing device 204 may include a variety of devices on which computing operations can be performed, such as a computer system or a component thereof. For example, the classical computing device 204 may be any computer and / or computing device that uses classical binary bits for operations, where a classical binary bit is a bit containing only two states, 1 or 0. In some embodiments, the classical computing device 204 may be any electronic or digital device that includes hardware and programming that utilizes at least one classical binary bit for processing and does not use qubits or quantum bits for processing. In some embodiments, the classical computing device 204 may include a first classical computing device that includes a discretization module 206 for discretizing the partial differential equation using initial value conditions to obtain a linear equation, and / or a second classical computing device that includes an integral interpolation module 220 configured to extract integral probabilities from the solution using integral interpolation. In some embodiments, the discretization module 206 and the integral interpolation module 220 may be implemented on the same classical computing device (for example, classical computing device 204).

[0036] As used herein, the term classic computing device 204 is not limited to devices implemented in integrated circuits, but broadly refers to processors, servers, microcontrollers, microcomputers, programmable logic controllers (PLCs), application-specific integrated circuits (ASICs), and other programmable circuits. In some embodiments, classic computing device 204 may include processors, memory, data storage, communication units, and / or any other computing modules. For example, classic computing device 204 may include one or more computers, servers, or other known computing devices as described. Classic computing device 204 includes, for example, server computers such as desktop computers, laptop computers, tablet computers, and rack-mount servers, mobile phones, smartphones, network devices, telecommunications equipment, single-board computers (SBCs), systems on a chip (SOCs), microcontroller units (MCUs), and any other electronic or digital devices having a processor. In some embodiments, classic computing device 204 may include computer peripherals associated with a user interface, such as a computer mouse, keyboard, and / or scanner. Furthermore, in some embodiments, the classic computing device 204 may include output channels such as a user interface monitor and / or a printer.

[0037] In some embodiments, the classical computing device 204 may include a discretization module 206 for accepting a partial differential equation 202 as input and discretizing the partial differential equation 202 to obtain a linear equation such as the linear equation 106 shown in Figure 1. The classical computing device 204 may include any configuration of a non-quantum processing unit and / or system. For example, the classical computing device 204 may include one or more elements of the computing system 500 in Figure 5. In some embodiments, the partial differential equation 202 may be provided to the classical computing device 204 via one or more physical networks, cloud networks, random access memory (RAM) drives, flash memory devices (e.g., solid-state memory devices), and / or any other way in which data can be transferred between devices and / or systems.

[0038] In some embodiments, the classical computing device 204 may be communicatively coupled to the quantum computing device 208. The classical computing device 204 can provide instructions to the quantum computing device 208, preprocess data for the quantum computing device 208, and interpret results from the quantum computing device 208. For example, the classical computing device 204 may be configured to instruct the quantum computing device 208 to prepare quantum states and / or perform measurements on those quantum states according to instructions stored in memory on the classical computing device 204. In some embodiments, the classical computing device 204 and the quantum computing device 208 may be communicatively coupled through a cloud service, such as when the classical computing device 204 transmits computation tasks to a remote quantum computing device 208 over a network.

[0039] In some embodiments, the quantum computing device 208 may include quantum hardware. For example, the quantum hardware may include a quantum processor that includes one or more qubits and the ability to store qubits. In some embodiments, qubits may be physically implemented using, for example, photons, trapped ions, electrons, one or more nuclei, superconducting circuits, and / or quantum dots. For example, qubits may be physically implemented in a variety of ways, including the polarization state of a single photon, the spatial optical path of a single photon, two different energy states of an atom or ion, and / or the spin orientation of one or more particles such as nuclei. Storing qubits may include, for example, supercooling the qubits to maintain them in an environment suitable for quantum computation. In some embodiments, the quantum computing device 208 may be any other computing device configured to operate using noisy intermediate-scale quantum (NISQ) devices and / or qubits.

[0040] In some embodiments, the quantum computing device 208 may include a quantum circuit 214. The quantum circuit 214 may be formed by a suitable arrangement of quantum logic gates and may act on a qubit. For example, in some embodiments, the quantum circuit 214 may be the quantum circuit 300 described with respect to Figure 3. In some embodiments, the quantum circuit 214 may determine the characteristics of an electromagnetic wave that can be applied to a qubit to adjust its state.

[0041] In some embodiments, computing modules may perform the same or similar functions as those described in relation to Figure 1. For example, the discretization module 206 may perform the same or similar functions as those described with respect to the discretization module 104; the scaling module 210 may perform the same or similar functions as those described with respect to the scaling module 108; the linear simultaneous equation solver module 212 may perform the same or similar functions as those described with respect to the linear simultaneous equation solver module 112; the quantum singular value transformation module 216 may perform the same or similar functions as those described with respect to the quantum singular value transformation module 116; and / or the integral interpolation module 220 may perform the same or similar functions as those described with respect to the integral interpolation module 120.

[0042] Herein, an example of the operation of the integral probability sampling system is provided. In some embodiments, a partial differential equation 202 representing an Asian financial option may be provided to the system so that the price / value of the Asian financial option can be determined. The Black-Scholes equation for pricing the Asian financial option may be the partial differential equation 202 provided to the discretization module 206 of the classical computing device 204. The discretization module 206 can discretize the time derivative of the Black-Scholes equation for pricing the Asian financial option to obtain a linear equation. In some embodiments, the discretization module 206 may also discretize the first derivative of the ratio and / or the second derivative of the ratio. In some embodiments, the linear equation may be provided to a quantum computing device 208 which may include a scaling module 210, a linear simultaneous equation solver module 212, and / or a QSVT module 216. In these and other embodiments, the quantum computing device 208 may include a quantum circuit 214 and / or a quantum memory 218. For example, the quantum circuit 214 may be configured to cause a QSVT module 216 to perform a QSVT and / or store the resulting solution in the quantum memory 218. In some embodiments, an integral interpolation module 220, which may be a component of a first classical computing device and / or a second classical computing device (e.g., classical computing device 204), may be used to extract an integral probability 222 from the quantum memory 218 of the quantum computing device 208. In some embodiments, the integral probability 222 may be a representation of a quantum system, the probability corresponding to the likelihood of finding a particle within a defined region when performing a quantum measurement. In some embodiments, the integral probability 222 may be a probability amplitude. In these and other embodiments, the integral probability 222 may be used to price Asian financial options.

[0043] Asian financial options can be difficult to price because their payoff is based on the average price of the underlying asset over a period of time and is path-dependent. For example, Asian options can be priced as the arithmetic or geometric mean of the underlying stock prices, such as measured every 30, 60, or 90 days. Therefore, a system configured to perform only classical methods (e.g., methods that can be performed by a classical computer) and / or traditional quantum methods (e.g., methods that can be performed by a quantum computer without integral stochastic sampling as described in this disclosure) may be inefficient and / or inaccurate for pricing Asian financial options. For example, classical methods and / or traditional quantum methods may use more qubits to obtain a solution, thereby increasing noise and / or errors. In some embodiments, classical methods and / or traditional quantum methods may involve larger gate costs (e.g., involving more classical or quantum logic gates). Therefore, the integral stochastic sampling system of this disclosure can provide quantum advantages and / or exponential advantages, for example, by pricing Asian financial options more efficiently and / or more accurately. In some embodiments, the integral stochastic sampling of this disclosure may include lower gate costs and / or a lower number of qubits than classical and / or other quantum methods. [Table 1]

[0044] For example, the list in Table 1 above includes classical and quantum methods, along with their corresponding gate costs and the number of qubits applicable to the quantum method. In some embodiments, the gate costs and / or number of qubits of the integral stochastic sampling of the Disclosure, as shown in Table 1, may demonstrate the quantum and / or exponential superiority of the Disclosure's method compared to classical and traditional quantum methods for pricing financial options and / or obtaining solution amplitudes from solution memory.

[0045] Without departing from the scope of this disclosure, modifications, additions, or omissions may be made to System 200. For example, the classical computing device 204 and / or the quantum computing device 208 may include one or more additional components. Additionally or alternatively, System 200 may include one or more additional components.

[0046] Figure 3 shows an exemplary quantum circuit 300 according to one or more embodiments of the present disclosure. In some embodiments, the quantum circuit 300 may be an example of the quantum circuit 214 in Figure 2. In some embodiments, the quantum circuit 300 is n τ It may contain n qubits. Here, n τ There are at least four qubits. In some embodiments, the quantum circuit 300 is

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[0047]

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[0048] With respect to Equation 3, in some embodiments, δ tThis may correspond to the interval in at least one Dirichlet boundary condition,

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[0049] In some embodiments, the quantum circuit 300 may operate to perform a quantum computation using a set of quantum logic gates acting on at least one qubit. For example, those quantum logic gates may manipulate the quantum states of at least four qubits. In some embodiments, the quantum circuit 300 may include at least one controlled quantum logic gate. In some embodiments, the quantum states of the at least four qubits may include a basic state (e.g., 0 or 1), a superposition state that can be represented by any value between 0 and 1, and / or an entangled state where the state of one qubit is based on the state of another qubit. In some embodiments, the quantum states of the at least four qubits may be tuned. For example, a quantum logic gate may tune the superposition state of a qubit by rotating the state of the qubit from a first position to a second position. In these and other embodiments, the quantum logic gates may represent operations that can be performed on the qubits. Therefore, quantum logic gates can be implemented by controlling the quantum hardware that encodes qubits, such as by manipulating the energy levels of atoms, ions, photons, and / or superconducting circuits that form the quantum hardware. In these and other embodiments, the quantum hardware can be controlled by the application of electromagnetic waves, such as lasers, microwaves, or other electromagnetic waves.

[0050] In some embodiments, quantum logic gates can be arranged in a specific manner to implement a quantum algorithm. For example, a quantum algorithm may be written to perform a specific task such as QSVT. In some embodiments, a quantum algorithm can be represented by a specific set of quantum logic gates that are arranged in a specific manner to encode the variables and operations of the quantum algorithm into a sequence of quantum logic gates. In these and other embodiments, the quantum logic gates may be unitary quantum logic gates. For example, a unitary quantum logic gate can be a basic operation performed on qubits that can be represented by a unitary matrix such that the total probability of the quantum system is conserved. In these and other embodiments, a unitary quantum logic gate can be a reversible operation (e.g., an operation that can control the manipulation of a quantum state without any loss of information corresponding to the quantum system).

[0051] In some embodiments, the quantum circuit 300 can include a first unitary quantum logic gate 302 configured to prepare the states of at least two of the at least four qubits. In these and other embodiments, the first unitary quantum logic gate 302 may be represented as U prepare and may be expressed as. In some embodiments, the first unitary quantum logic gate 302 can set at least two of the at least four qubits within the quantum circuit 300 to a prepared (e.g., initialized) state. For example, the first unitary quantum logic gate 302 can set a qubit to a superposition state characterized by an amplitude and one or more phase parameters.

[0052] In some embodiments, the quantum circuit 300 may include one or more Y gates 304a, 304b, 304c ("Y gate 304"). For example, a Y gate 304 may be used to perform a phase shift as part of a QSVT. In some embodiments, a Y gate 304 may implement a rotation around the y-axis of a Bloch sphere (e.g., a geometric representation of all possible states of a qubit). In some embodiments, a Y gate 304 may be implemented for the least significant qubit (LSQb) of the quantum circuit 300. In some embodiments, a Y gate 304 may be a controlled gate.

[0053] In some embodiments, the quantum circuit 300 may include a second unitary quantum logic gate 306 configured to perform a first cyclic shift of the at least two qubits to a prepared state to obtain a linear combination. In these and other embodiments, the second unitary quantum logic gate 306 is S +1 It can be expressed as follows.

[0054] In some embodiments, the quantum circuit 300 may include a third unitary quantum logic gate 308 configured to invert a linear combination to obtain an inverted linear combination. In these and other embodiments, the third unitary quantum logic gate 308 is P signflip It can be represented as Y.

[0055] In some embodiments, the quantum circuit 300 may include a fourth unitary quantum logic gate 310 configured to perform a second cyclic shift on an inverted linear combination to obtain a solution, the solution being a transformed linear combination. In these and other embodiments, the fourth unitary quantum logic gate 310 is S † +1 It can be expressed as follows.

[0056] In some embodiments, the quantum circuit 300 may include a fifth unitary quantum logic gate 312 configured to store the transformed linear combination in the quantum memory of the quantum computing device. In these and other embodiments, the fifth unitary quantum logic gate 312 is U † prepare It can be expressed as follows.

[0057] In these and other embodiments, the quantum circuit 300 may offer advantages over other quantum circuits configured for integral stochastic extraction, because the quantum circuit 300 can avoid the oracle workspace required for typical sparse matrix implementations. For example, the quantum circuit 300 can offer the advantages listed in Table 1 above. In some embodiments, the quantum circuit 300 may offer advantages by being implementable on quantum computing devices having fewer than 100 qubits. In some embodiments, the quantum circuit 300 may offer advantages by being implementable on quantum computing devices having fewer than 75 qubits. In some embodiments, the quantum circuit 300 may offer advantages by being embeddable on quantum computing devices having fewer than 50 qubits. In some embodiments, the operators of the quantum algorithm implemented by the quantum circuit 300 may use a variety of qubits. For example, Table 2 below includes exemplary operators and their corresponding qubits that may be used in some embodiments. [Table 2]

[0058] Regarding Table 2, n η This is to store the solution on the quantum memory of a quantum computing device (for example, 2 on the region of the variable η). nη This can correspond to the number of qubits used to store the individual point solutions and the relative variable I / ST.

[0059] Without departing from the scope of this disclosure, modifications, additions, or omissions may be made to the quantum circuit 300. For example, one or more quantum logic gates may be added to the quantum circuit 300 or removed from the quantum circuit 102.

[0060] Figure 4 is a flowchart of an exemplary method 400 of integral probability sampling according to one or more embodiments of the present disclosure. Method 400 can be performed by any suitable system, apparatus, or device. For example, a classical computing device 204, a quantum computing device 208, and / or a quantum circuit 214 can perform one or more of the operations associated with Method 400. Although shown in discrete blocks, the steps and operations associated with one or more of the blocks of Method 400 may be divided into additional blocks, combined into fewer blocks, or deleted, depending on the specific implementation.

[0061] Method 400 may begin in block 402, where the partial differential equation with initial value conditions may be discretized to obtain a linear equation. In these and other embodiments, the partial differential equation may correspond to the Black-Scholes model. For example, the partial differential equation may be the Black-Scholes equation for pricing Asian financial options. In some embodiments, discretizing the partial differential equation may involve applying a central difference operator and / or at least one Dirichlet boundary condition. For example, block 402 uses the central difference operator and Dirichlet boundary condition to obtain the time derivative ∂ψ / ∂ of the Black-Scholes equation (e.g., Equation 1 above). τ1 Discretize

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[0062] In block 404, at least one discretization parameter of the linear equation may be scaled to obtain a scaled linear equation. In some embodiments, scaling may involve transforming at least one variable of the linear equation using a scalar (for example, by multiplying by a constant). For example, the linear equation may have a factor

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[0063] In block 406, a quantum algorithm may be applied to the scaled linear equations to obtain a system of linear equations with a pre-formed matrix. In some embodiments, the quantum algorithm may be an HHL algorithm. In these and other embodiments, the quantum algorithm may be applied to the scaled linear equations using a quantum computing device. This is done by encoding the scaled linear equations as quantum states, estimating the eigenvalues ​​of the matrix using quantum phase estimation, and / or performing controlled rotations based on the eigenvalues ​​to obtain a pre-formed matrix.

[0064] In block 408, a QSVT may be used to obtain a solution by applying the inverse of a pre-formed matrix. In some embodiments, the QSVT may be implemented by a quantum circuit of the quantum computing device. In some embodiments, the quantum circuit may include at least one quantum logic gate that can act on a single qubit. In some embodiments, the quantum circuit may include at least four qubits, a first unitary quantum logic gate configured to prepare the states of at least two of the at least four qubits, a second unitary quantum logic gate configured to perform a first cyclic shift on the prepared states of the at least two qubits to obtain a linear combination, a third unitary quantum logic gate configured to invert the linear combination, a fourth unitary quantum logic gate configured to perform a second cyclic shift on the at least two qubits to obtain a transformed linear combination, and / or a fifth unitary quantum logic gate configured to store the transformed linear combination (e.g., the solution) in the quantum memory of the quantum computing device. In some embodiments, the QSVT may use the quantum circuit to encode the matrix as a unitary operator. In some embodiments, the quantum computing device is

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[0065] In block 410, integral probabilities can be extracted from the solution using integral interpolation. In some embodiments, the solution may be stored in the quantum memory of the quantum computing device. In these and other embodiments, extracting integral probabilities may involve obtaining probability amplitudes by sequentially and iteratively measuring the corresponding wave functions for a given quantitative state of the solution. Thereafter, the absolute values ​​of the complex numbers representing the quantum states can be calculated to a specified level of confidence. For example, extracting integral probabilities may involve obtaining the amplitudes for τ1 and η from the quantum memory of the quantum computing device in the Chebyshev node.

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[0066] Modifications, additions, or omissions may be made to Method 400 without departing from the scope of this disclosure. For example, the designation of various elements in the described embodiments is intended to help illustrate the concepts described herein and is not limiting. Furthermore, Method 400 may include any number of other elements or may be implemented in other systems or contexts other than those described. For example, Method 400 may further include pricing at least one financial option using integral probabilities. In some embodiments, Method 400 may provide a quantum advantage for extracting integral probabilities compared to classical methods such as quantum-inspired sampling, time-domain subsampling, and / or classical Monte Carlo integration. In some embodiments, Method 400 may provide an exponential advantage for extracting integral probabilities compared to conventional quantum methods such as evaluation trees, semi-digital encoding, quantized subsampling, and / or quantum Monte Carlo integration.

[0067] Figure 5 shows an exemplary computing system 500 according to one or more embodiments of the present disclosure. The computing system 500 may include a processor 502, memory 504, data storage 506, and / or a communication unit 508, all of which may be communicatively coupled. For example, the operating environment 100 in Figure 1 may be implemented as a computing system compatible with the computing system 500. As another example, the classical computing device 204 and / or quantum computing device 208 in Figure 2 may include one or more components of the computing system 500.

[0068] Generally, the processor 502 may include any suitable dedicated or general-purpose computer, computing entity, or processing device, including various computer hardware or software modules, and may be configured to execute instructions stored in any applicable computer-readable storage medium. For example, the processor 502 may include a microprocessor, microcontroller, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or any other digital or analog circuitry configured to interpret and / or execute program instructions and / or process data.

[0069] Although shown as a single processor in Figure 5, it is understood that processor 502 may include any number of processors distributed across any number of network or physical locations, configured to individually or collectively perform any number of operations described in this disclosure. In some embodiments, processor 502 may interpret and / or execute program instructions and / or process data stored in memory 504, data storage 506, or memory 504 and data storage 506. In some embodiments, processor 502 may fetch program instructions from data storage 506 and load the program instructions into memory 504.

[0070] After the program instructions are loaded into memory 504, the processor 502 may execute program instructions such as instructions that cause the computing system 500 to perform part of the operation of method 400 in Figure 4. For example, the computing system 500 may execute the program instructions to perform discretization, scaling, extraction, etc.

[0071] The memory 504 and data storage 506 may include computer-readable storage media or one or more computer-readable storage media for storing computer-executable instructions or data structures. Such computer-readable storage media may be any available media that can be accessed by a general-purpose or dedicated computer, such as a processor 502. In some embodiments, the computing system 500 may or may not include either the memory 504 or the data storage 506.

[0072] Such computer-readable storage media may include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory devices (e.g., solid-state memory devices), or any other storage media that can be used to store desired program code in the form of computer-executable instructions or data structures and can be accessed by a general-purpose or dedicated computer. Combinations of the above may also be included within the scope of computer-readable storage media. Computer-executable instructions may include, for example, instructions and data configured to cause processor 502 to perform a particular operation or set of operations.

[0073] The communication unit 508 may include any component, device, system, or combination thereof configured to transmit or receive information over a network. In some embodiments, the communication unit 508 may communicate with other devices located at other locations, at the same location, or even with other components within the same system. For example, the communication unit 508 may include modems, network cards (wireless or wired), optical communication devices, infrared communication devices, wireless communication devices (such as antennas), and / or chipsets (such as Bluetooth® devices, 802.6 devices (e.g., Metropolitan Area Network (MAN)), WiFi devices, WiMAX devices, cellular communication equipment, etc.). The communication unit 508 may enable data to be exchanged with the network and / or any other devices or systems described herein. For example, the communication unit 508 may allow computing system 500 to communicate with other systems such as computing devices and / or other networks.

[0074] A person skilled in the art will recognize, after reviewing this disclosure, that modifications, additions, or omissions may be made to the computing system 500 without departing from the scope of this disclosure. For example, the computing system 500 may include more or fewer components than those expressly illustrated and described.

[0075] The foregoing disclosure is not intended to limit this disclosure to the exact form or specific field of use disclosed. Therefore, various alternative embodiments and / or modifications to this disclosure are possible in light of this disclosure, whether expressly described or implied herein. While embodiments of this disclosure have been described in this manner, it should be recognized that modifications in form and detail may be made without departing from the scope of this disclosure. Therefore, this disclosure is limited solely by the claims.

[0076] In some embodiments, the various components, modules, engines, and services described herein may be implemented as objects or processes (for example, as separate threads) running on a computing system. While some of the systems and methods described herein are generally described as being implemented in software (stored in and / or run by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0077] In accordance with common practice, various features shown in the drawings may not be drawn to scale. The examples presented in this disclosure are not intended to be actual diagrams of any particular apparatus (e.g., devices, systems, etc.) or method, but are merely idealized representations used to illustrate various embodiments of this disclosure. Accordingly, the dimensions of various features may be enlarged or reduced as appropriate for clarity. In addition, some drawings may be simplified for clarity. Thus, the drawings may not show all components of a given apparatus (e.g., a device) or all operations of a particular method.

[0078] The terms used herein, and in particular in the appended claims (for example, in the body of the appended claims), are generally intended to be “open” terms (for example, the term “includes” should be interpreted as “includes, but not limited to…”, the term “has” should be interpreted as “has at least…”, and the term “contains” should be interpreted as “includes, but not limited to…”).

[0079] Furthermore, if a specific number of claims to be introduced is intended, such intention is explicitly stated in the claim; if no such statement is present, such intention does not exist. For example, to aid understanding, the following appended claims may include the use of the introductory phrases “at least one” and “one or more” to introduce a claim. However, the use of such phrases should not be interpreted as implying that the introduction of a claim by the indefinite article “a” or “an” limits any particular claim containing such introduced claim to embodiments containing only one such claim. This is true even if the same claim contains the introductory phrase “one or more” or “at least one” and an indefinite article such as “a” or “an.” (For example, “a” and / or “an” should be interpreted as meaning “at least one” or “one or more.”) The same applies to the use of definite articles used to introduce a claim.

[0080] Furthermore, even if a specific number of claims being introduced is explicitly stated, it should be understood that such a statement should be interpreted as meaning at least that stated number (for example, the statement “two statements” without other modifiers means at least two statements, or two or more statements). Furthermore, when idiomatic expressions similar to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” are used, such constructions are generally intended to include A only, B only, C only, both A and B, both A and C, both B and C, or all of A, B, and C, etc. For example, the use of the term “and / or” is intended to be interpreted in this way.

[0081] Furthermore, any disjunctive phrase that presents two or more alternative terms should be understood in this paper, the claims, or the drawings as potentially including one of those terms, either of those terms, or both of those terms. For example, the phrase "A or B" should be understood as including the possibilities of "A" or "B" or "A and B".

[0082] Furthermore, the use of terms such as “first,” “second,” and “third” is not necessarily used in this specification to imply a particular order or number of elements. Generally, terms such as “first,” “second,” and “third” are used as general identifiers to distinguish different elements. Where there is no indication that terms such as “first,” “second,” and “third” imply a particular order, these terms should not be understood as implying a particular order. Furthermore, where there is no indication that terms such as “first,” “second,” and “third” imply a particular number of elements, these terms should not be understood as implying a particular number of elements. For example, a first widget may be described as having a first side, and a second widget may be described as having a second side. The use of the term “second side” in relation to a second widget may be to distinguish such a side of the second widget from the “first side” of the first widget, and does not imply that the second widget has two sides.

[0083] All examples and conditional statements described herein are intended for educational purposes to help readers understand the present invention and the concepts to which the inventors have contributed to advance the art, and should be construed as not being limited to such specifically described examples and conditions. While embodiments of this disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications can be made to this disclosure without departing from the spirit and scope of this disclosure.

[0084] With regard to embodiments including the above examples, the following additional information is disclosed. (Note 1) The first step involves discretizing the partial differential equation using initial value conditions to obtain a linear equation; The steps include scaling at least one discretization parameter of the linear equation to obtain a scaled linear equation; The step of applying a quantum algorithm to the scaled linear equations to obtain a system of linear equations with pre-formed matrices; The steps include: performing a quantum singular value transformation using a quantum circuit in a quantum computing device in order to obtain a solution by applying the inverse of the aforementioned pre-formed matrix; The step of extracting the integral probability from the solution using integral interpolation. Methods that include... (Note 2) The aforementioned quantum circuit is: At least four qubits; A first unitary quantum logic gate configured to prepare the states of at least two of the four qubits; A second unitary quantum logic gate configured to perform a first cyclic shift on the prepared state of at least two qubits to obtain a linear combination; A third unitary quantum logic gate configured to invert the aforementioned linear combination; A fourth unitary quantum logic gate configured to perform a second cyclic shift on the inverted linear combination on at least two of the aforementioned qubits to obtain the solution, which is the transformed linear combination; A fifth unitary quantum logic gate configured to store the transformed linear combination in the quantum memory of the quantum computing device, The method described in Appendix 1, having the characteristics of the method described in Appendix 1. (Note 3) The aforementioned quantum computing device,

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[0085] 102 Partial differential equations 104 Discretization Module 106 Linear Equations 108 Scaling Modules 110 Scaled linear equations 112 Linear Simultaneous Equation Solver Module 114 Linear systems of equations with pre-formed matrices 116 Quantum Singular Value Transformation Module 118 solution 120 Integral Interpolation Module 122 Integral Probability 202 Partial differential equations 204 Classic Computing Devices 206 Discretization Module 208 Quantum Computing Devices 210 Scaling Modules 212 Linear Simultaneous Equation Solver Module 214 Quantum circuit 216 Quantum Singular Value Transformation Module 218 Quantum Memory 220 Integral Interpolation Module 222 Integral Probability 402 Discretizing a partial differential equation with initial value conditions to obtain a linear equation 404 Scale at least one discretization parameter of the linear equation to obtain the scaled linear equation. 406 Applying a quantum algorithm to scaled linear equations to obtain a system of linear equations with pre-formed matrices 408 Perform a quantum singular value transformation to obtain a solution by applying the inverse of a pre-formed matrix. 410 Extracting the integral probability from the solution using integral interpolation 500 Computing Systems 502 Processors 504 memory 506 Data Storage 508 Communication Unit

Claims

1. The first step is to discretize the partial differential equation using the initial value conditions to obtain a linear equation; The steps include scaling at least one discretization parameter of the linear equation to obtain a scaled linear equation; The step of applying a quantum algorithm to the scaled linear equations to obtain a system of linear equations with pre-formed matrices; The steps include: performing a quantum singular value transformation using a quantum circuit in a quantum computing device in order to obtain a solution by applying the inverse of the aforementioned pre-formed matrix; The step of extracting the integral probability from the solution using integral interpolation. Methods that include...

2. The aforementioned quantum circuit is: At least four qubits; A first unitary quantum logic gate configured to prepare the states of at least two of the four qubits; A second unitary quantum logic gate configured to perform a first cyclic shift on the prepared state of at least two qubits to obtain a linear combination; A third unitary quantum logic gate configured to invert the aforementioned linear combination; A fourth unitary quantum logic gate configured to perform a second cyclic shift on the inverted linear combination on at least two of the aforementioned qubits to obtain the solution, which is the transformed linear combination; A fifth unitary quantum logic gate configured to store the transformed linear combination in the quantum memory of the quantum computing device, The method according to claim 1, comprising:

3. The aforementioned quantum computing device, [Math 1] The method according to claim 1, wherein the number of qubits is included, and ε represents the additive error of the solution.

4. The aforementioned quantum computing device, [Math 2] The method according to claim 1, wherein the number of qubits is included, and ε represents the additive error of the solution.

5. The step further includes pricing at least one financial option using the aforementioned integral probability. The method according to claim 1.

6. The method according to claim 1, which provides a quantum advantage for extracting integral probabilities compared to classical methods.

7. The method according to claim 1, which provides an exponential advantage for extracting integral probabilities compared to conventional quantum methods.

8. The method according to claim 1, wherein the aforementioned partial differential equation corresponds to the Black-Scholes model.

9. The method according to claim 1, wherein discretizing the partial differential equation includes applying a central difference operator and at least one Dirichlet boundary condition.

10. The method according to claim 1, wherein the quantum algorithm is a Halo-Hasidim-Lloyd algorithm.

11. It is a system: One or more processors; The system comprises one or more non-temporary computer-readable storage media configured to store instructions that cause the system to perform an action in response to being executed, wherein the action is: The first step is to discretize the partial differential equation using the initial value conditions to obtain a linear equation; The steps include scaling at least one discretization parameter of the linear equation to obtain a scaled linear equation; The step of applying a quantum algorithm to the scaled linear equations to obtain a system of linear equations with pre-formed matrices; The steps include: performing a quantum singular value transformation using a quantum circuit in a quantum computing device in order to obtain a solution by applying the inverse of the aforementioned pre-formed matrix; The step of extracting the integral probability from the solution using integral interpolation. A system that includes this.

12. The aforementioned quantum circuit is: At least four qubits; A first unitary quantum logic gate configured to prepare the states of at least two of the four qubits; A second unitary quantum logic gate configured to perform a first cyclic shift on the prepared state of at least two qubits to obtain a linear combination; A third unitary quantum logic gate configured to invert the aforementioned linear combination; A fourth unitary quantum logic gate configured to perform a second cyclic shift on the inverted linear combination on at least two of the aforementioned qubits to obtain the solution, which is the transformed linear combination; A fifth unitary quantum logic gate configured to store the transformed linear combination in the quantum memory of the quantum computing device, The system according to claim 11, having the following features.

13. The aforementioned quantum computing device, [Math 3] The system according to claim 11, including the number of qubits, wherein ε represents the additive error of the solution.

14. The aforementioned quantum computing device, [Math 4] The system according to claim 11, including the number of qubits, wherein ε represents the additive error of the solution.

15. The aforementioned operation is: The step further includes pricing at least one financial option using the aforementioned integral probability. The system according to claim 11.

16. The system according to claim 11, which provides a quantum advantage for extracting integral probabilities compared to classical methods.

17. The system according to claim 11, which provides an exponential advantage for extracting integral probabilities compared to conventional quantum methods.

18. The system according to claim 11, wherein the aforementioned partial differential equation corresponds to the Black-Scholes model.

19. One or more non-temporary computer-readable storage media configured to store instructions that cause a system to perform an action in response to being executed, wherein the action is: The first step is to discretize the partial differential equation using the initial value conditions to obtain a linear equation; The steps include scaling at least one discretization parameter of the linear equation to obtain a scaled linear equation; The step of applying a quantum algorithm to the scaled linear equations to obtain a system of linear equations with pre-formed matrices; The steps include: performing a quantum singular value transformation using a quantum circuit in a quantum computing device in order to obtain a solution by applying the inverse of the aforementioned pre-formed matrix; The step of extracting the integral probability from the solution using integral interpolation. Non-temporary computer-readable storage media, including [specific data / information].

20. The aforementioned quantum circuit is: At least four qubits; A first unitary quantum logic gate configured to prepare the states of at least two of the four qubits; A second unitary quantum logic gate configured to perform a first cyclic shift on the prepared state of at least two qubits to obtain a linear combination; A third unitary quantum logic gate configured to invert the aforementioned linear combination; A fourth unitary quantum logic gate configured to perform a second cyclic shift on the inverted linear combination on at least two of the aforementioned qubits to obtain the solution, which is the transformed linear combination; A fifth unitary quantum logic gate configured to store the transformed linear combination in the quantum memory of the quantum computing device, A non-temporary computer-readable storage medium according to claim 19, having the following characteristics.

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