Photoelectric conversion device and photoelectric conversion system

Abstract

The present invention provides a photoelectric converter capable of performing appropriate black level correction even when processing pixel signals using multiple different gain settings. [Solution] The photoelectric converter includes a pixel that outputs an analog reference signal and an analog image signal; a readout unit that outputs a digital reference signal that has undergone gain processing and AD conversion processing on the analog reference signal and a digital image signal that has undergone AD conversion processing and gain processing with a first gain or a second gain on the analog image signal; and a difference processing unit that outputs a first value, which is a value generated by difference processing between the digital image signal and the digital reference signal, when the analog image signal has undergone gain processing with a first gain or the digital signal value, which is the value of the digital reference signal, is less than a first determination value, and outputs a second value, which is different from the value generated by difference processing, when the analog image signal has undergone gain processing with a second gain and the digital signal value is equal to or greater than the first determination value.

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

Background Art

[0002] When high-intensity light is incident, the charges generated in the photoelectric conversion element may overflow into the floating diffusion section, and the value of the reference signal corresponding to the dark state may increase. In such a case, while the image signal is in a saturated state, the reference signal is in an increased state, so the value of the signal obtained as the difference between the image signal and the reference signal becomes smaller than the value corresponding to the actual luminance. As a result, a phenomenon in which a region that is actually high in luminance appears to be low in luminance, so-called black sinking, may occur. Patent Document 1 describes a method of correcting black sinking by replacing a difference signal with a predetermined correction value when the image signal and the reference signal satisfy a predetermined condition such as exceeding a predetermined threshold value.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the technique described in Patent Document 1, when processing pixel signals using a plurality of different gain settings, appropriate black sinking correction may not be possible.

[0005] An object of the present invention is to provide a photoelectric conversion device capable of performing appropriate black sinking correction even when processing pixel signals using a plurality of different gain settings.

Means for Solving the Problems

[0006] According to one disclosure of this specification, a photoelectric conversion device is provided, which has a photoelectric conversion unit that generates electric charge by photoelectric conversion and outputs an analog reference signal and an analog image signal; a readout unit that performs gain processing and analog-to-digital conversion processing on the analog reference signal and the analog image signal and outputs a digital reference signal on which gain processing and analog-to-digital conversion processing have been performed on the analog reference signal and the analog image signal and outputs a digital image signal on which analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain; and a difference processing unit that outputs a first value which is a value generated by difference processing between the digital image signal and the digital reference signal when the gain processing has been performed on the analog image signal with the first gain or the digital signal value which is the value of the digital reference signal is less than a first determination value, and outputs a second value which is different from the value generated by difference processing when the gain processing has been performed on the analog image signal with the second gain and the digital signal value is greater than or equal to the first determination value. [Effects of the Invention]

[0007] According to the present invention, even when processing pixel signals using multiple different gain settings, appropriate black level correction can be performed, and high-quality images can be obtained. [Brief explanation of the drawing]

[0008] [Figure 1] This block diagram shows the schematic configuration of a photoelectric conversion device according to the first embodiment. [Figure 2] This figure shows an example configuration of pixels, a readout unit, and a DSP in a photoelectric conversion device according to the first embodiment. [Figure 3] This is a timing diagram showing the driving method of the photoelectric converter according to the first embodiment. [Figure 4] This block diagram shows the schematic configuration of the photoelectric conversion device according to the second embodiment. [Figure 5] This figure shows the distribution of the count value of the reference signal under normal light conditions. [Figure 6] This block diagram shows the schematic configuration of a photoelectric conversion device according to the third embodiment. [Figure 7] This is a timing diagram showing the driving method of the photoelectric converter according to the third embodiment. [Figure 8] This is a block diagram showing the schematic configuration of a photoelectric conversion device according to the fourth embodiment. [Figure 9] This is a timing diagram showing the driving method of the photoelectric converter according to the fourth embodiment. [Figure 10] This is a block diagram showing the schematic configuration of the imaging system according to the fifth embodiment. [Figure 11] This figure shows an example configuration of an imaging system and a mobile body according to the sixth embodiment. [Figure 12] This is a block diagram showing the schematic configuration of the device according to the seventh embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way.

[0010] In the embodiments described below, the focus will be on photoelectric converters for imaging applications as examples of photoelectric converters. However, each embodiment is not limited to photoelectric converters for imaging applications and can be applied to other photoelectric converters as well. For example, other examples of photoelectric converters include distance measuring devices (devices for distance measurement using focus detection or TOF (Time of Flight)) and photometric devices (devices for measuring the amount of incident light).

[0011] In this specification, even when the ratio of the output voltage to the input voltage is 1 or less, this ratio is expressed as "gain". Also, signal processing with a gain of 1 or less is included in "amplification". That is, generally, what is called "buffering" (gain of about 1) or "attenuation" (gain less than 1) is also included in "amplification".

[0012] [First Embodiment] The photoelectric conversion device according to the first embodiment of the present invention will be described with reference to FIG. 1. FIG. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment.

[0013] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel section 10, a vertical scanning circuit 20, a readout section 30, a reference signal output circuit 40, and a counter 50. The photoelectric conversion device 100 further includes a horizontal scanning circuit 60, a digital signal processor (DSP) 70, and a timing generation circuit (TG) 80.

[0014] The pixel section 10 is provided with a plurality of pixels 12 arranged in a matrix of m rows × n columns over a plurality of rows (m rows) and a plurality of columns (n columns). Each pixel 12 includes a photoelectric conversion section composed of a photoelectric conversion element such as a photodiode, and outputs a pixel signal corresponding to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel section 10 is not particularly limited. In addition to the effective pixels that output pixel signals corresponding to the amount of incident light, the pixel section 10 may be provided with optical black pixels in which the photoelectric conversion section is shielded from light, dummy pixels that do not output signals, and the like. The specific configuration of the pixel 12 will be described later.

[0015] In each row of the pixel section 10, row control signal lines X (X1, X2, …, Xm) are arranged to extend in a first direction (the horizontal direction in FIG. 1). Each of the row control signal lines X is connected to pixels 12 arranged in the first direction, and together they form a common signal line for these pixels 12. The first direction in which the row control signal lines X extend may be referred to as the row direction or the horizontal direction. The row control signal lines X are connected to the vertical scanning circuit 20. Note that each of the row control signal lines X may include a plurality of signal lines.

[0016] In each column of the pixel section 10, signal output lines Y (Y1, …, Yn) are arranged to extend in a second direction (the vertical direction in FIG. 1) that intersects the first direction. Each of the signal output lines Y is connected to pixels 12 arranged in the second direction, and together they form a common signal line for these pixels 12. The second direction in which the signal output lines Y extend may be referred to as the column direction or the vertical direction. The signal output lines Y are connected to the reading section 30.

[0017] The vertical scanning circuit 20 is a control circuit having a function of generating a control signal for driving the pixels 12 and supplying the generated control signal to the pixel section 10. Logic circuits such as a shift register and an address decoder may be used for the vertical scanning circuit 20. The vertical scanning circuit 20 sequentially outputs a control signal to the row control signal lines X of each row, and sequentially drives (vertically scans) the pixels 12 of the pixel section 10 row by row. Thereby, the pixels 12 of each row of the pixel section 10 are sequentially selected, and a pixel signal Vpix, which is an analog signal, is output from each pixel 12. The pixel signal Vpix includes two types of signals, a reference signal Vn (analog reference signal) and an image signal Vs (analog image signal). The reference signal Vn is a signal indicating a reference level at the time of resetting the pixel 12, and the image signal Vs is a signal in which the reference signal Vn is superimposed on a signal corresponding to the amount of incident light to the pixel 12. Note that in this specification, the term “image signal” is used assuming a photoelectric conversion device for image acquisition, but the image signal Vs does not necessarily have to be a signal used for forming an image. The pixel signals Vpix output from the pixels 12 of each column are transmitted to the reading section 30 via the signal output lines Y.

[0018] The readout unit 30 has a plurality of column circuit units corresponding to each column of the pixel unit 10. Each column circuit unit is a processing circuit that performs predetermined processing on the pixel signal read from the pixel 12 of the corresponding column. Examples of processing performed by the column circuit unit include signal processing such as amplification processing and analog-to-digital conversion processing (AD conversion processing). In this embodiment, it is assumed that each column circuit unit has an analog-to-digital conversion circuit (AD conversion circuit) that performs AD conversion processing on the pixel signal Vpix output from the pixel unit 10. Processing in each column circuit unit is performed in parallel.

[0019] Each of the column circuit sections includes a comparison circuit 34, a reference signal selection section 36, memory 44J, memory 46S, memory 46NL, and memory 46NH. In this embodiment, the functional block including the comparison circuit 34 and reference signal selection section 36 of each column is sometimes referred to as the comparison section 32, and the functional block including the memories 44J, 46S, 46NL, and 46NH of each column is sometimes referred to as the memory section 42. The readout section 30 further includes a reference signal selection section 54.

[0020] One input node of the comparator circuit 34 is connected to the signal output line Y of the corresponding column. The other input node of the comparator circuit 34 is connected to the output node of the reference signal selection unit 36. The output nodes of the comparator circuit 34 are connected to the input node of memory 44J and the first input nodes of memories 46S, 46NL, and 46NH. The second input nodes of memories 46S, 46NL, and 46NH are connected to the counter 50. The third input nodes of memories 46S, 46NL, and 46NH are connected to the horizontal scanning circuit 60. The output nodes of memories 44J, 46S, 46NL, and 46NH are connected to the horizontal transfer lines 52J, 52S, 52NL, and 52NH, respectively. The output node of memory 44J is also connected to the control node of the reference signal selection unit 36. The horizontal transfer lines 52NL and 52NH are connected to the input nodes of the reference signal selection unit 54. The output node of the reference signal selection unit 54 is connected to the horizontal transfer line 52N. Horizontal transfer lines 52J, 52S, and 52N are connected to the DSP 70. Horizontal transfer line 52J is also connected to the control node of the reference signal selection unit 54.

[0021] The reference signal output circuit 40 has the function of outputting reference signals Vramp_l and Vramp_h used for AD conversion. The reference signals Vramp_l and Vramp_h output from the reference signal output circuit 40 are supplied to the other input node of the comparison circuit 34 in each column via the reference signal selection unit 36. At this time, the reference signal selection unit 36 ​​selects one of the reference signals Vramp_l and Vramp_h according to the control signal from TG80 (described later) and the brightness identification signal from memory 44J, and outputs it to the other input node of the comparison circuit 34. The reference signal output circuit 40 also has the function of outputting a determination voltage for brightness determination. The reference signal output circuit 40 may also have the function of generating reference signals, or it may be configured to buffer and output reference signals generated outside the photoelectric converter.

[0022] The counter 50 counts the clock pulse signal supplied from the TG80 and supplies a counter signal Φcot indicating the count value to the memory 46S, 46NL, and 46NH of each column. The counter 50 starts counting in synchronization with the timing when the signal level of the reference signals Vramp_l and Vramp_h output from the reference signal output circuit 40 starts to change. Note that the function of the counter 50 may also be provided by the column circuit section of each column.

[0023] The horizontal scanning circuit 60 is a control circuit that generates control signals H(H1,...,Hn) for reading digital data held by the memories 46S, 46NL, and 46NH in each column, and supplies the generated control signals to the memory unit 42. Logic circuits such as shift registers and address decoders may be used in the horizontal scanning circuit 60. The horizontal scanning circuit 60 sequentially outputs control signals H to the memories 46S, 46NL, and 46NH in each column, causing them to sequentially output the digital data they hold to the horizontal transfer lines 52S, 52NL, and 52NH. The signals held by memory 44J are input to the DSP 70 and the reference signal selection unit 54 via the horizontal transfer line 52J. The reference signal selection unit 54 selects one of the signals output from memories 46NL and 46NH in response to the signal from memory 44J and outputs it to the horizontal transfer line 52N. The signals from the horizontal transfer lines 52S and 52N are input to the DSP 70.

[0024] The DSP70 is a signal processing circuit that performs predetermined signal processing based on digital data input via horizontal transfer lines 52S and 52N and a luminance identification signal input via horizontal transfer line 52J, and outputs the processed image data to the outside. Examples of processing performed by the DSP70 include signal processing such as saturation detection and noise reduction of pixel 12. The external interface circuit provided by the DSP70 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied to the external interface circuit. Examples of SerDes transmission circuits include LVDS (Low Voltage Differential Signaling) circuits and SLVS (Scalable Low Voltage Signaling) circuits.

[0025] The TG80 has the function of outputting control signals to the vertical scanning circuit 20, reference signal output circuit 40, counter 50, horizontal scanning circuit 60, and DSP 70, etc., based on a predetermined processing flow, and controlling them. The TG80 performs these operations based on external control. For example, the TG80 can be controlled by the system control unit of the imaging system on which the photoelectric converter 100 is mounted. At least a portion of the control signals supplied to the vertical scanning circuit 20, reference signal output circuit 40, counter 50, horizontal scanning circuit 60, and DSP 70 may be supplied from outside the photoelectric converter 100.

[0026] Next, a more detailed configuration example and operation of the pixel 12, readout unit 30, and DSP 70 will be explained using Figure 2. Figure 2 is a diagram showing a configuration example of the pixel 12, readout unit 30, and DSP 70 in the photoelectric converter according to this embodiment. For the sake of simplicity, Figure 2 shows only one pixel 12 and a column circuit unit located in the i-th column (where i is an integer between 1 and n).

[0027] Pixel 12 may be composed of, for example, a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4, as shown in Figure 2.

[0028] The photoelectric conversion element PD may be, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to a ground voltage node, and the cathode is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. Node FD, to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected, is a so-called floating diffusion section. The floating diffusion section contains a capacitive component (floating diffusion capacitance) and functions as a charge holder. The floating diffusion capacitance may include the gate capacitance of the transistor, the pn junction capacitance, the wiring capacitance, etc. The drains of the reset transistor M2 and the amplifier transistor M3 are connected to a node to which the power supply voltage (voltage Vd) is supplied. The source of the amplifier transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the signal output line Yi.

[0029] In the pixel configuration shown in Figure 2, the row control signal line X for each row includes three signal lines connected to the gates of the transfer transistor M1, the reset transistor M2, and the selection transistor M4. The gate of the transfer transistor M1 is supplied with a control signal ΦTx from the vertical scanning circuit 20. The gate of the reset transistor M2 is supplied with a control signal ΦRes from the vertical scanning circuit 20. The gate of the selection transistor M4 is supplied with a control signal ΦSel from the vertical scanning circuit 20. If each transistor is an N-type MOS transistor, a high-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor ON. Conversely, a low-level control signal supplied from the vertical scanning circuit 20 turns the corresponding transistor OFF.

[0030] In this embodiment, the explanation assumes that electrons are used as the signal charge among the electron-hole pairs generated in the photoelectric conversion element PD by light incidence. When electrons are used as the signal charge, each transistor constituting the pixel 12 may be composed of an N-type MOS transistor. However, the signal charge is not limited to electrons; holes may also be used as the signal charge. When holes are used as the signal charge, the conductivity type of each transistor will be the opposite conductivity type to that described in this embodiment. Also, the names of the source and drain of the MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the source and drain names used in this embodiment may also be referred to by the opposite names.

[0031] The photoelectric element PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and stores the resulting charge. When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric element PD to the node FD. The charge transferred from the photoelectric element PD is held in the capacitive component (stray diffusion capacitance) of the node FD. As a result, the potential of the node FD is determined by the charge-voltage conversion due to the stray diffusion capacitance, corresponding to the amount of charge transferred from the photoelectric element PD.

[0032] The reset transistor M2 controls the reset operation for resetting node FD, which acts as a charge holder. In other words, the reset transistor M2 is a reset unit that, when turned on, resets node FD to a voltage corresponding to the voltage Vd.

[0033] When the select transistor M4 is turned on, it connects the amplification transistor M3 to the signal output line 16. The amplification transistor M3 is configured such that a voltage Vd is supplied to its drain and a bias current is supplied to its source from the current source IR via the select transistor M4, forming an amplification section (source follower circuit) with its gate as the input node. As a result, the amplification transistor M3 outputs a signal (pixel signal Vpix) based on the potential of node FD to the signal output line Yi via the select transistor M4. In this sense, the amplification transistor M3 and the select transistor M4 are output sections that output a pixel signal Vpix corresponding to the amount of charge held at node FD.

[0034] As described above, the pixel signal Vpix includes two types of signals: a reference signal Vn and an image signal Vs. The reference signal Vn is the signal output to the signal output line Yi when the reset transistor M2 is turned on and the node FD is reset. The image signal Vs is the signal output to the signal output line Yi when the transfer transistor M1 is turned on and the photocharge accumulated in the photoelectric conversion element PD is transferred to the node FD. In other words, the image signal Vs is a signal in which the reference signal Vn is superimposed on a signal corresponding to the amount of incident light.

[0035] The readout unit 30 receives the pixel signal Vpix from the pixel 12, the reference signals Vramp_l and Vramp_h from the reference signal output circuit 40, and the control signals ΦRamp_sel and ΦAz from the TG80.

[0036] As mentioned above, the reference signals Vramp_l and Vramp_h are signals used for AD conversion. The reference signals Vramp_l and Vramp_h may be signals that have a predetermined amplitude corresponding to the range of the pixel signal Vpix and whose signal level changes over time. The reference signals are not particularly limited, but for example, a ramp signal whose signal level increases or decreases monotonically over time can be applied. Note that the change in signal level does not necessarily have to be continuous and may be stepwise. Also, the change in signal level does not necessarily have to be linear with respect to time and may be curvilinear with respect to time (for example, a sine wave or cosine wave). In this embodiment, the reference signal output circuit 40 outputs two types of ramp signals (reference signals Vramp_l and Vramp_h) with different rates of change in signal level over time.

[0037] Here, reference signal Vramp_l is a reference signal used when performing AD conversion on a low-luminance signal, and reference signal Vramp_h is a reference signal used when performing AD conversion on a high-luminance signal. Compared to reference signal Vramp_l, reference signal Vramp_h has a larger amplitude and steeper slope by the reciprocal of the gain ratio. The gain ratio here is the ratio (G1 / G2) of the gain G1 when using reference signal Vramp_l to the gain G2 when using reference signal Vramp_h. Reference signals Vramp_l and Vramp_h can be generated, for example, by outputting a current generated using a current-to-digital-to-analog converter (IDAC) through a load element. In this case, the slopes of reference signals Vramp_l and Vramp_h can be controlled by the drive frequency of the IDAC. A dual-slope type AD conversion circuit can be said to have both gain processing and AD conversion processing functions.

[0038] The reference signal selection unit 36 ​​selects one of the reference signals Vramp_l and Vramph supplied from the reference signal output circuit 40 and outputs it to the comparison circuit 34. The control node of the reference signal selection unit 36 ​​receives the control signal ΦRamp_sel and the luminance identification signal J via the OR circuit LC1. As a result, the reference signal selection unit 36 ​​selects the reference signal Vramp_h as the reference signal Vramp if at least one of the control signal ΦRamp_sel and the luminance identification signal J is at a high level. Also, the reference signal selection unit 36 ​​selects the reference signal Vramp_l as the reference signal Vramp if the control signal ΦRamp_sel and the luminance identification signal J are at a low level. In the following description, the reference signal selected by the reference signal selection unit 36 ​​from the reference signals Vramp_l and Vramph may be referred to as the reference signal Vramp.

[0039] The reference signal output circuit 40 further has the function of outputting a judgment voltage Vjudge that indicates the voltage level at which to switch between the low-luminance AD ​​conversion process and the high-luminance AD ​​conversion process. The judgment voltage Vjudge can be set to a voltage less than or equal to the maximum amplitude of the reference signal Vramp_l. The judgment voltage Vjudge can be supplied to the comparator circuit 34 via the same path as the reference signal Vramp_l. The reference signal output circuit 40 outputs either the reference signal Vramp_l or the judgment voltage Vjudge in response to the control signal supplied from TG80 (control signal ΦJudge, described later). For example, the reference signal output circuit 40 outputs the reference signal Vramp_l when the control signal ΦJudge is at a low level, and outputs the judgment voltage Vjudge when the control signal ΦJudge is at a high level.

[0040] The comparator circuit 34 may consist of a comparator 38, clamp capacitors Ci1 and Ci2, and reset switches SW1 and SW2, as shown in Figure 2, for example. The comparator 38 may include a differential amplifier circuit. The comparator 38 has two input nodes and one output node. One input node of the comparator 38 is connected to the signal output line Yi via clamp capacitor Ci1. The other input node of the comparator 38 is connected to the output node of the reference signal selector 36 via clamp capacitor Ci2. Reset switches SW1 and SW2 are connected to the comparator 38. The output node of the comparator 38 is connected to memory 44J, 46S, 46NL, and 46NH.

[0041] The reset switches SW1 and SW2 are controlled by the control signal ΦAZ from the TG80. For example, they turn on (conduct) when the control signal ΦAZ is high, and turn off (non-conduct) when the control signal ΦAZ is low. When reset switches SW1 and SW2 are turned on, the voltages clamped by the clamp capacitors Ci1 and Ci2 are reset.

[0042] The comparator 38 compares the level of the pixel signal Vpix input via clamp capacitor Ci1 with the level of the reference signal Vramp input via clamp capacitor Ci2, and outputs a signal according to the result of the comparison. For example, the comparator 38 outputs a high-level signal when the level of the reference signal Vramp is higher than the level of the pixel signal Vpix, and outputs a low-level signal when the level of the pixel signal Vpix is ​​higher than the level of the reference signal Vramp. Furthermore, the comparator 38 outputs a pulse signal that becomes high-level when the relative magnitude relationship between the levels of the reference signal Vramp and the pixel signal Vpix is ​​reversed. This pulse signal is the latch signal ΦLt. The latch signal ΦLt is output to the memories 46S, 46NL, and 46NH. Note that the relative magnitude relationship of the input signals when the latch signal ΦLt is output may be reversed. The comparison processing in the comparator circuit 34 of each column is performed in parallel.

[0043] Counter 50 starts counting the clock pulse signal supplied from TG80 in synchronization with the timing when the signal level of the reference signal Vramp starts to change, and outputs a counter signal Φcot indicating the count value to memories 46S, 46NL, and 46NH. Memories 46S, 46NL, and 46NH temporarily hold the count value indicated by the counter signal Φcot as digital data of the pixel signal Vpix when they receive the latch signal ΦLt. In this way, AD conversion of the pixel signal Vpix is ​​performed for each column. Memories 46NL and NH hold the reference signal Vn (digital reference signal) after AD conversion, and memory 46S holds the image signal Vs (digital image signal) after AD conversion. The digital data held in memories 46S, 46NL, and 46NH may be, for example, 12-bit binary digital data.

[0044] Furthermore, the comparator 38 compares the level of the pixel signal Vpix input via clamp capacitor Ci1 with the level of the judgment voltage Vjudge input via clamp capacitor Ci2, and outputs a signal according to the result of the comparison. If the comparison result shows that the amplitude of the pixel signal Vpix is ​​greater than the amplitude corresponding to the judgment voltage Vjudge, the memory 44J holds a digital value of 1 as the luminance identification signal J. If the comparison result shows that the amplitude of the pixel signal Vpix is ​​less than or equal to the amplitude corresponding to the judgment voltage Vjudge, the memory 44J holds a digital value of 0 as the luminance identification signal J. The luminance identification signal J held in the memory 44J is output to the reference signal selection unit 54 and the OR circuit LC1.

[0045] Memory 46S outputs the digital signal to be held to the horizontal transfer line 52S in response to the control signal Hi from the horizontal scanning circuit. This digital signal is the digital signal DS (digital image signal) corresponding to the image signal Vs. Similarly, memories 46NL and 46NH output the digital signals to be held to the horizontal transfer lines 52NL and 52NH, respectively, in response to the control signal Hi from the horizontal scanning circuit. Memory 44J also outputs the brightness identification signal J to be held to the reference signal selection unit 54 via the horizontal transfer line 52J. The reference signal selection unit 54 selects one of the digital signals output to the horizontal transfer line 52NL and the digital signal output to the horizontal transfer line 52NH in response to the brightness identification signal J, and outputs it to the horizontal transfer line 52N. That is, the reference signal selection unit 54 selects the digital signal output from memory 46NH when the brightness identification signal J is 1, and selects the digital signal output from memory 46NL when the brightness identification signal J is 0. The digital signal output to the horizontal transfer line 52N is the digital signal DN (digital reference signal) corresponding to the reference signal Vn. The digital signals DS and DN output to the horizontal transfer lines 52S and 52N, and the luminance identification signal J output to the horizontal transfer line 52J are input to the DSP 70.

[0046] The DSP70 includes, for example, a determination unit 72, a difference processing unit 74, and a signal processing unit 76, as shown in Figure 2. The determination unit 72 is connected to horizontal transfer lines 52N and 52J. The difference processing unit 74 is connected to horizontal transfer lines 52S, 52N, and 52J and the determination unit 72. The signal processing unit 76 is connected to the difference processing unit 74.

[0047] The determination unit 72 has the function of determining whether the signal level of the digital signal DN is in a high-brightness blackout state. The high-brightness blackout state occurs when the photoelectric conversion element PD becomes saturated and charge leaks out to the node FD, causing the reference voltage to decrease and the value of the digital signal DN to increase. Since the high-brightness blackout state occurs when excessive light is incident, the brightness identification signal J is 1 when the high-brightness blackout state occurs. Therefore, the determination unit 72 determines that the high-brightness blackout state is occurring when the brightness identification signal J is 1 and the digital signal DN is greater than the digital signal value of the reference voltage that occurs when the incident light amount is within the normal range.

[0048] The determination unit 72 includes a storage unit such as a register and holds a predetermined determination value used for the determination. This predetermined determination value is a threshold value compared with a digital reference signal. The determination value is determined based on a value corresponding to the output value of the reference voltage when the photoelectric conversion element PD is saturated when AD conversion is performed using the reference signal Vramp_h. For example, the determination value can be set to a value that is slightly larger than the value corresponding to the output value of the reference voltage when the photoelectric conversion element PD is saturated when AD conversion is performed using the reference signal Vramp_h, taking into account variations. In this embodiment, this determination value is referred to as the determination data DN_H (digital reference signal determination value).

[0049] The determination unit 72 compares the digital signal DN with the determination data DN_H. If the digital signal value of the digital signal DN is greater than or equal to the determination value of the determination data DN_H, the determination unit 72 outputs a high-level determination signal ΦCT as a signal indicating the determination result. On the other hand, if the digital signal value of the digital signal DN is less than the determination value of the determination data DN_H, the determination unit 72 outputs a low-level determination signal ΦCT as a signal indicating the determination result.

[0050] The difference processing unit 74 includes a difference circuit that calculates the difference between the digital signal DS and the digital signal DN, and a correction circuit for correcting the gain difference between the low-luminance signal and the high-luminance signal. The difference circuit performs a difference process by subtracting the digital signal DN from the digital signal DS, thereby removing the effects of the reference signal voltage of the pixel 12 and the offset voltage of the comparator circuit 34, and outputs a digital signal DS2 corresponding to the photocharge. The correction circuit is a circuit that performs a correction process to make the gain substantially equivalent when AD conversion is performed using the reference signal Vramp_l and when AD conversion is performed using the reference signal Vramp_h. Since the reference signal Vramp has a difference in output value equivalent to the gain ratio between low-luminance and high-luminance conditions, when AD conversion is performed using the reference signal Vramp_h, the difference result is multiplied by the gain ratio to convert it to a value equivalent to when AD conversion is performed using the reference signal Vramp_l.

[0051] The difference processing unit 74 outputs one of the following two types of signals as the digital signal DS2 based on the level of the determination signal ΦCT output from the determination unit 72. That is, when the determination signal ΦCT is at a low level, the difference processing unit 74 outputs the difference value obtained by subtracting the digital signal DN from the digital signal DS as the digital signal DS2. This removes the influence of the voltage of the reference signal Vn of the pixel 12 and the offset voltage of the comparator circuit 34, etc., and makes it possible to obtain the digital signal DS2 corresponding to the photocharge. On the other hand, when the determination signal ΦCT is at a high level, the difference processing unit 74 outputs a digital signal as the digital signal DS2 that has a correction value corresponding to the white level, which is different from the difference value obtained by subtracting the digital signal DN from the digital signal DS. The digital signal corresponding to the white level can be, for example, the maximum value among the values ​​that the digital signal can take.

[0052] In other words, if the luminance identification signal J is 0 or the value of the digital signal DN is less than the determination value of the determination data DN_H, the difference processing unit 74 outputs a first value, which is the difference value obtained by subtracting the digital signal DN from the digital signal DS. Furthermore, if the luminance identification signal J is 1 and the value of the digital signal DN is greater than or equal to the determination value of the determination data DN_H, the difference processing unit 74 outputs a second value corresponding to the white level.

[0053] When the photoelectric conversion element PD becomes saturated, a spurious signal generated by the overflow charge from the photoelectric conversion element PD is superimposed on the digital signal DN. In such a case, the difference processing between the digital signal DS and the digital signal DN may result in the digital signal DS2 having a signal level below the white level. As a result, the captured image may exhibit a black-sinking phenomenon where the brightness of areas that should be white is reduced. Therefore, in this embodiment, when saturation of the photoelectric conversion element PD is detected, the output signal is replaced with a signal with a signal level equivalent to the white level. This makes it possible to suppress the effect of the black-sinking phenomenon.

[0054] The signal processing unit 76 performs the following operations on the digital signal DS2: adding a black offset signal as a measure against shading of the dark signal, data level shifting as digital gain processing of the active signal, adjusting the number of data bits, etc., to acquire the digital signal DS3, which is then output externally.

[0055] In this embodiment, the determination unit 72 and the difference processing unit 74 are circuits provided in common for each column of the reading unit 30, and sequentially process the signals output from the column circuit section of each column. Therefore, in this embodiment, the circuit size can be reduced compared to the case where the determination unit 72 and the difference processing unit 74 are provided for each column. Thus, according to this embodiment, it is possible to reduce the increase in circuit size while reducing the effect of the black saturation phenomenon. Furthermore, according to this embodiment, it is also possible to reduce power consumption by reducing the circuit size.

[0056] The determination signal ΦCT, which indicates the determination result, is a signal supplied from the determination unit 72 to the difference processing unit 74 as described above. However, the determination signal ΦCT may also be output to the outside of the photoelectric converter 100 as a flag signal. For example, if the determination signal ΦCT is at a high level, the signal processing unit outside the photoelectric converter 100 can optimize the correction signal level by not using the corresponding data for correction processing between image data.

[0057] Next, the driving method of the photoelectric converter according to this embodiment will be explained using Figure 3. Figure 3 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. In this embodiment, a method of performing AD conversion of a reference signal using reference signals Vramp_l and Vramp_h will be described. In Figure 3, the horizontal direction represents time, and the vertical direction represents the schematic waveform of each signal.

[0058] The waveforms of the pixel signal Vpix and the reference signal Vramp in Figure 3 show the change in potential of the signals input from the two input nodes of the comparator 38 and compared by the comparator 38. Figure 3 also shows the signals at each stage for the case of low-brightness normal light, high-brightness normal light, and excessive light when the incident light to the photoelectric conversion element PD is low-brightness normal light, high-brightness normal light, and excessive light. Here, low-brightness normal light is incident light within the range in which the photoelectric conversion element PD does not saturate, and the pixel signal Vpix is ​​lower than the judgment voltage Vjudge and AD conversion is performed using the reference signal Vramp_l. High-brightness normal light is incident light within the range in which the photoelectric conversion element PD does not saturate, and the pixel signal Vpix is ​​higher than the judgment voltage Vjudge and AD conversion is performed using the reference signal Vramp_h. Excessive light is incident light with an intensity that saturates the photoelectric conversion element PD.

[0059] In Figure 3, Vn1 represents the reference signal for low-luminance normal light, Vn2 represents the reference signal for high-luminance normal light, and Vn3 represents the reference signal for excessive light. Additionally, Vs1 represents the image signal for low-luminance normal light, Vs2 represents the image signal for high-luminance normal light, and Vs3 represents the image signal for excessive light.

[0060] In Figure 3, the period from time t31 to time t34 is the AD conversion period of the reference signal Vn using the reference signal Vramp_h (NH_AD period). The period from time t41 to time t44 is the AD conversion period of the reference signal Vn using the reference signal Vramp_l (NL_AD period). The period from time t51 to time t52 is the judgment period of the pixel signal Vpix using the judgment voltage Vjudge (JUDGE period). The period from time t61 to time t64 is the AD conversion period of the image signal Vs (S_AD period).

[0061] During the NH_AD period, the comparator circuit 34 performs a comparison between the reference signal Vn (Vn1~Vn3) and the reference signal Vramp_h. The reference signal selection unit 36 ​​selects the reference signal Vramp_h as the reference signal Vramp according to the high-level control signal ΦRamp_sel from TG80. During the NL_AD period, the comparator circuit 34 performs a comparison between the reference signal Vn (Vn1~Vn3) and the reference signal Vramp_l. The reference signal selection unit 36 ​​selects the reference signal Vramp_l as the reference signal Vramp according to the low-level control signal ΦRamp_sel from TG80. During each AD period, the counter 50 starts counting in synchronization with the start of the change in the signal level of the reference signal Vramp and supplies the counter signal Φcot, which indicates the count value, to the memories 46NL and 46NH. When the relative magnitudes of the potential of the pixel signal Vpix and the potential of the reference signal Vramp are reversed, the comparator circuit 34 outputs a latch signal ΦLt based on this comparison result. Memories 46NL and 46NH store the count value indicated by the counter signal Φcot as digital data of the reference signal Vn at the time the latch signal ΦLt is received.

[0062] During the JUDGE period, the comparison circuit 34 compares the image signal Vs (Vs1 to Vs3) with the judgment voltage Vjudge. When the relative magnitudes of the potential of the pixel signal Vpix and the potential of the judgment voltage Vjudge are reversed, the comparison circuit 34 outputs a latch signal ΦLt based on this comparison result. Memory 44J has a digital value of 0 in advance as the brightness identification signal J, and when it receives the latch signal ΦLt, it holds a digital value of 1 as the brightness identification signal J. The reference signal selection unit 36 ​​selects the reference signal Vramp to be used during the S_AD period from the reference signals Vramp_l and Vramp_h based on the brightness identification signal J set during the JUDGE period.

[0063] During the S_AD period, the comparator circuit 34 compares the image signal Vs (Vs1 to Vs3) with a reference signal Vramp selected based on the brightness discrimination signal J. The counter 50 starts counting in synchronization with the start of a change in the signal level of the reference signal Vramp and supplies a counter signal Φcot indicating the count value to the memory 46S. When the relative magnitudes of the potential of the pixel signal Vpix and the potential of the reference signal Vramp are reversed, the comparator circuit 34 outputs a latch signal ΦLt based on this comparison result. The memory 46S stores the count value indicated by the counter signal Φcot as digital data of the image signal Vs at the time it receives the latch signal ΦLt.

[0064] First, we will explain the AD conversion process and signal processing in the DSP70 when the incident light is low-luminance normal light.

[0065] At time t1, the vertical scanning circuit 20 controls the control signal ΦSel for the row to be read from a low level to a high level. This turns on the selection transistor M4 of the pixel 12 of the row to be read, and the source follower circuit of the pixel 12 becomes operational. In other words, the pixel 12 of the row to be read is selected.

[0066] Similarly, at time t1, the vertical scanning circuit 20 controls the control signal ΦRes of the row to be read from a low level to a high level. This turns on the reset transistor M2 of the pixel 12 of the row to be read, and the node FD is reset to a potential corresponding to the voltage Vd. The pixel signal Vpix corresponding to the reset potential of the node FD is output to the signal output line Yi.

[0067] Also, at time t1, TG80 controls the control signal ΦAz from a low level to a high level. This turns on the reset switches SW1 and SW2 of the comparator circuit 34, resetting the comparator circuit 34 to its initial state.

[0068] At the following time t2, the vertical scanning circuit 20 controls the control signal ΦRes of the row to be read from a high level to a low level. This turns off the reset transistor M2 of the pixel 12 of the row to be read, and the reset state of node FD is released. The signal when the reset transistor M2 is turned off and the potential of the signal output line Yi is set is taken as the reference signal Vn1.

[0069] At the following time t3, TG80 controls the control signal ΦAz from a high level to a low level. This releases the reset state of the comparator circuit 34, causing the potential of the input terminal of clamp capacitor Ci1 to be at the level of the reference signal Vn1, and the potential of the output terminal of clamp capacitor Ci1, i.e., one input node of comparator 38, to be clamped to the potential of the reference signal Vn1. Also, the potential of the input terminal of clamp capacitor Ci2 becomes at the level of the reference potential of the reference signal Vramp_h, and the potential of the output terminal of clamp capacitor Ci2, i.e., the other input node of comparator 38, is clamped to the same potential as the reference signal Vn1.

[0070] At the following time t31, the aforementioned NH_AD period begins. TG80 controls the control signal ΦRamp_sel to a high level. This selects the reference signal Vramp_h as the reference signal Vramp. The reference signal output circuit 40 starts changing the potential of the reference signal Vramp_h. Hereafter, the reference signal Vramp_h used for comparison processing during the NH_AD period will be called the reference signal Vramp_NH. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NH.

[0071] At the following time t32, the potential of the reference signal Vramp_NH falls below the potential of the reference signal Vn1. This generates a pulse of the latch signal ΦLt, and the count value NH1 indicated by the counter signal Φcot at time t32 is stored in memory 46NH.

[0072] At the following time t41, the aforementioned NL_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp_l. Hereafter, the reference signal Vramp_h used for comparison processing during the NL_AD period will be called the reference signal Vramp_NL. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NL.

[0073] At the following time t42, the potential of the reference signal Vramp_NL falls below the potential of the reference signal Vn1. This generates a pulse of the latch signal ΦLt, and the count value NL1 indicated by the counter signal Φcot at time t42 is stored in memory 46NL.

[0074] At the following time t4, the vertical scanning circuit 20 controls the control signal ΦTx of the row to be read from a low level to a high level. This turns on the transfer transistor M1 of the pixel 12 of the row to be read, and the charge stored in the photoelectric conversion element PD is transferred to node FD. A pixel signal Vpix corresponding to the amount of charge transferred to node FD is output to the signal output line Yi.

[0075] At the following time t5, the vertical scanning circuit 20 controls the control signal ΦTx of the row to be read from a high level to a low level. This turns off the transfer transistor M1 of the pixel 12 of the row to be read. The signal when the transfer transistor M1 is turned off and the potential of the signal output line Yi is set is taken as the image signal Vs1.

[0076] At the following time t6, the aforementioned JUDGE period begins, and TG80 controls the control signal ΦJudge supplied to the reference signal output circuit 40 from a low level to a high level during the period from time t6 to time t7. The reference signal output circuit 40 sets the reference signal Vramp_l to the judgment voltage Vjudge in response to the high-level control signal ΦJudge. The reference signal selection unit 36 ​​selects the reference signal Vramp_l (judgment voltage Vjudge) as the reference signal Vramp in response to the low-level control signal ΦRamp_sel.

[0077] The comparison circuit 34 compares the level of the image signal Vs1 with the level of the judgment voltage Vjudge. Under low-luminance normal light, the potential of the image signal Vs1 is higher than the potential of the judgment voltage Vjudge, so the output of the comparison circuit 34 does not invert, and no pulse of the latch signal ΦLt is generated. As a result, the memory 44J holds a digital value of 0 as the luminance identification signal J.

[0078] At the following time t61, the aforementioned S_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp. At this time, the reference signal selection unit 36 ​​selects the reference signal Vramp_l as the reference signal Vramp in accordance with the low-level control signal ΦRamp_sel and the luminance identification signal J with a digital value of 0. Hereafter, the reference signal Vramp_l used for comparison processing during the S_AD period will be called the reference signal Vramp_SL.

[0079] At the following time t62, the potential of the reference signal Vramp_SL falls below the potential of the image signal Vs1. This generates a pulse of the latch signal ΦLt, and the count value SL1 indicated by the counter signal Φcot at time t62 is stored in memory 46S.

[0080] The count value SL1 held in memory 46S is output to the horizontal transfer line 52S in response to the control signal Hi from the horizontal scanning circuit 60 and transmitted to the DSP 70 as a digital signal DS. Similarly, the count values ​​NL1 and NH1 held in memories 46NL and 46NH are output to the horizontal transfer lines 52NL and NH respectively in response to the control signal Hi from the horizontal scanning circuit 60 and transmitted to the reference signal selection unit 54. The reference signal selection unit 54 selects the count value NL1 from the count values ​​NH1 and NL1 in response to the luminance identification signal J of digital value 0 held in memory 44J and transmits it to the DSP 70 as a digital signal DN.

[0081] The determination unit 72 determines whether the signal level of the digital signal DN is in a high-brightness black state. In low-brightness normal light, the brightness identification signal J is 0, so the determination signal ΦCT is low level. The difference processing unit 74 subtracts the digital signal DN from the digital signal DS according to the low level determination signal ΦCT and outputs the difference value as the digital signal DS2.

[0082] Next, we will explain the AD conversion process and signal processing in the DSP70 when the incident light is high-brightness normal light. Note that explanations of the same processes as when the incident light is low-brightness normal light will be omitted as appropriate.

[0083] At time t2, the vertical scanning circuit 20 controls the control signal ΦRes of the row to be read from a high level to a low level. This turns off the reset transistor M2 of the pixel 12 of the row to be read, and the reset state of node FD is released. The signal when the reset transistor M2 is turned off and the potential of the signal output line Yi is set is taken as the reference signal Vn2.

[0084] At the following time t3, TG80 controls the control signal ΦAz from a high level to a low level. This releases the reset state of the comparator circuit 34, causing the potential of the input terminal of clamp capacitor Ci1 to be at the level of the reference signal Vn2, and the potential of the output terminal of clamp capacitor Ci1, i.e., one input node of comparator 38, to be clamped to the potential of the reference signal Vn2. Also, the potential of the input terminal of clamp capacitor Ci2 becomes at the level of the reference potential of the reference signal Vramp_h, and the potential of the output terminal of clamp capacitor Ci2, i.e., the other input node of comparator 38, is clamped to the same potential as the reference signal Vn2.

[0085] At the following time t31, the aforementioned NH_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp_NH. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NH.

[0086] At the following time t32, the potential of the reference signal Vramp_NH falls below the potential of the reference signal Vn2. This generates a pulse of the latch signal ΦLt, and the count value NH2 indicated by the counter signal Φcot at time t32 is stored in memory 46NH.

[0087] At the following time t41, the aforementioned NL_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp_NL. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NL.

[0088] At the following time t42, the potential of the reference signal Vramp_NL falls below the potential of the reference signal Vn2. This generates a pulse of the latch signal ΦLt, and the count value NL2 indicated by the counter signal Φcot at time t42 is stored in memory 46NL.

[0089] At the following time t4, the vertical scanning circuit 20 controls the control signal ΦTx of the row to be read from a low level to a high level. This turns on the transfer transistor M1 of the pixel 12 of the row to be read, and the charge stored in the photoelectric conversion element PD is transferred to node FD. A pixel signal Vpix corresponding to the amount of charge transferred to node FD is output to the signal output line Yi.

[0090] At the following time t5, the vertical scanning circuit 20 controls the control signal ΦTx of the row to be read from a high level to a low level. This turns off the transfer transistor M1 of the pixel 12 of the row to be read. The signal when the transfer transistor M1 is turned off and the potential of the signal output line Yi is set is taken as the image signal Vs2.

[0091] At the following time t6, the aforementioned JUDGE period begins, and TG80 controls the control signal ΦJudge supplied to the reference signal output circuit 40 from a low level to a high level during the period from time t6 to time t7. The reference signal output circuit 40 sets the reference signal Vramp_l to the judgment voltage Vjudge in response to the high-level control signal ΦJudge. The reference signal selection unit 36 ​​selects the reference signal Vramp_l (judgment voltage Vjudge) as the reference signal Vramp in response to the low-level control signal ΦRamp_sel.

[0092] The comparison circuit 34 compares the level of the image signal Vs2 with the level of the judgment voltage Vjudge. Under high-brightness normal light, the potential of the judgment voltage Vjudge is higher than the potential of the image signal Vs2, so the output of the comparison circuit 34 is inverted, and a pulse of the latch signal ΦLt is generated. As a result, the memory 44J holds a digital value of 1 as the brightness identification signal J.

[0093] At the following time t61, the aforementioned S_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp. At this time, the reference signal selection unit 36 ​​selects the reference signal Vramp_h as the reference signal Vramp according to the brightness identification signal J of digital value 1. Hereafter, the reference signal Vramp_h used for comparison processing during the S_AD period will be called the reference signal Vramp_SH.

[0094] At the following time t63, the potential of the reference signal Vramp_SH falls below the potential of the image signal Vs2. This generates a pulse of the latch signal ΦLt, and the count value SH2 indicated by the counter signal Φcot at time t63 is stored in memory 46S.

[0095] The count value SH2 held in memory 46S is output to the horizontal transfer line 52S in response to the control signal Hi from the horizontal scanning circuit 60 and transmitted to the DSP 70 as a digital signal DS. Similarly, the count values ​​NL2 and NH2 held in memories 46NL and 46NH are output to the horizontal transfer lines 52NL and NH respectively in response to the control signal Hi from the horizontal scanning circuit 60 and transmitted to the reference signal selection unit 54. The reference signal selection unit 54 selects the count value NH2 from the count values ​​NH2 and NL2 in response to the brightness identification signal J of digital value 1 held in memory 44J and transmits it to the DSP 70 as a digital signal DN.

[0096] The determination unit 72 determines whether the signal level of the digital signal DN is in a high-brightness black state. In high-brightness normal light, the brightness identification signal J is 1, but the digital signal value of the digital signal DN is smaller than the determination value of the determination data DN_H, so the determination signal ΦCT is low level. The difference processing unit 74 subtracts the digital signal DN from the digital signal DS according to the low-level determination signal ΦCT and outputs the difference value as the digital signal DS2.

[0097] Next, we will explain the AD conversion process and signal processing in the DSP70 when the incident light is excessively bright. Note that explanations of the same processes as those for low-brightness and high-brightness normal light will be omitted as appropriate.

[0098] At time t2, the vertical scanning circuit 20 controls the control signal ΦRes of the row to be read from a high level to a low level. This turns off the reset transistor M2 of the pixel 12 of the row to be read, and the reset state of node FD is released. The signal when the reset transistor M2 is turned off and the potential of the signal output line Yi is set is defined as the reference signal Vn3. Note that if excessive light is incident, charge leaks from the saturated photoelectric conversion element PD to node FD, causing the level of the reference signal Vn3 to be lower than the levels of the reference signals Vn1 and Vn2.

[0099] At the following time t3, TG80 controls the control signal ΦAz from a high level to a low level. This releases the reset state of the comparator circuit 34, causing the potential of the input terminal of clamp capacitor Ci1 to be at the level of the reference signal Vn3, and the potential of the output terminal of clamp capacitor Ci1, i.e., one input node of comparator 38, to be clamped to the potential of the reference signal Vn3. Also, the potential of the input terminal of clamp capacitor Ci2 becomes at the level of the reference potential of the reference signal Vramp_h, and the potential of the output terminal of clamp capacitor Ci2, i.e., the other input node of comparator 38, is clamped to the same potential as the reference signal Vn3.

[0100] At the following time t31, the aforementioned NH_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp_NH. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NH.

[0101] At the following time t33, the potential of the reference signal Vramp_NH falls below the potential of the reference signal Vn3. This generates a pulse of the latch signal ΦLt, and the count value NH3 indicated by the counter signal Φcot at time t33 is stored in memory 46NH.

[0102] At the following time t41, the aforementioned NL_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp_NL. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NL.

[0103] At the following time t43, the potential of the reference signal Vramp_NL falls below the potential of the reference signal Vn3. This generates a pulse of the latch signal ΦLt, and the count value NL3 indicated by the counter signal Φcot at time t43 is stored in memory 46NL.

[0104] At the following time t4, the vertical scanning circuit 20 controls the control signal ΦTx of the row to be read from a low level to a high level. This turns on the transfer transistor M1 of the pixel 12 of the row to be read, and the charge stored in the photoelectric conversion element PD is transferred to node FD. A pixel signal Vpix corresponding to the amount of charge transferred to node FD is output to the signal output line Yi.

[0105] At the following time t5, the vertical scanning circuit 20 controls the control signal ΦTx of the row to be read from a high level to a low level. This turns off the transfer transistor M1 of the pixel 12 of the row to be read. The signal when the transfer transistor M1 is turned off and the potential of the signal output line Yi is set is taken as the image signal Vs3.

[0106] At the following time t6, the aforementioned JUDGE period begins, and TG80 controls the control signal ΦJudge supplied to the reference signal output circuit 40 from a low level to a high level during the period from time t6 to time t7. The reference signal output circuit 40 sets the reference signal Vramp_l to the judgment voltage Vjudge in response to the high-level control signal ΦJudge. The reference signal selection unit 36 ​​selects the reference signal Vramp_l (judgment voltage Vjudge) as the reference signal Vramp in response to the low-level control signal ΦRamp_sel.

[0107] The comparison circuit 34 compares the level of the image signal Vs3 with the level of the judgment voltage Vjudge. In the case of excessive light, the potential of the judgment voltage Vjudge is higher than the potential of the image signal Vs3, so the output of the comparison circuit 34 is inverted, and a pulse of the latch signal ΦLt is generated. As a result, the memory 44J holds a digital value of 1 as the brightness identification signal J.

[0108] At the following time t61, the aforementioned S_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp. At this time, the reference signal selection unit 36 ​​selects the reference signal Vramp_h (Vramp_SH) as the reference signal Vramp according to the brightness identification signal J of digital value 1.

[0109] At the subsequent time t64, the potential of the reference signal Vramp_SH transitions to its minimum value, but the potential of the reference signal Vramp_SH does not fall below the potential of the image signal Vs3. As a result, no pulse of the latch signal ΦLt is generated, and the count value SH3, which is the upper limit count value of counter 50, is held in memory 46S.

[0110] The count value SH3 held in memory 46S is output to the horizontal transfer line 52S in response to the control signal Hi from the horizontal scanning circuit 60 and transmitted to the DSP 70 as a digital signal DS. Similarly, the count values ​​NL3 and NH3 held in memories 46NL and 46NH are output to the horizontal transfer lines 52NL and NH respectively in response to the control signal Hi from the horizontal scanning circuit 60 and transmitted to the reference signal selection unit 54. The reference signal selection unit 54 selects the count value NH3 from the count values ​​NH3 and NL3 in response to the brightness identification signal J of digital value 1 held in memory 44J and transmits it to the DSP 70 as a digital signal DN.

[0111] The determination unit 72 determines whether the signal level of the digital signal DN is in a high-brightness blackout state. In high-brightness normal light, the brightness identification signal J is 1 and the digital signal value of the digital signal DN is greater than the determination value of the determination data DN_H, so the determination signal ΦCT is at a high level. The difference processing unit 74, in response to the high-level determination signal ΦCT, converts the difference between the digital signal DS and the digital signal DN into a blackout correction value equivalent to the white level, which is output as the digital signal DS2.

[0112] As described above, by determining the saturation of the photoelectric conversion element PD according to the signal levels of the luminance identification signal J and the digital signal DN, the black level can be appropriately determined and the digital signal DS2 can be corrected to a white level. If black level correction is performed using only the digital signal DN without using the luminance identification signal J, the count value NL of the low-luminance reference signal will be larger than the count value NH of the high-luminance reference signal by the gain ratio. Therefore, if the judgment data DN_H is set to a value slightly larger than the high-luminance count value NH, the count value NL will be larger than the judgment data DN_H even though the incident light is low in intensity, resulting in incorrect black level correction and a breakdown of luminance linearity. In this case, the above problem can be avoided by setting the judgment data DN_H to a value larger than the count value NL of the low-luminance reference signal. However, since the correction is activated only after the count value NH of the reference signal becomes larger than expected when excessive light is incident, the black level correction is activated after black level has occurred, and appropriate correction cannot be performed. In this respect, in this embodiment, since black level correction is activated only at high brightness using the brightness identification signal J, black level correction can be performed more favorably than in conventional methods.

[0113] Thus, according to this embodiment, even when processing pixel signals using multiple different gain settings, appropriate black level correction can be performed, and high-quality images can be obtained.

[0114] [Second Embodiment] A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Figure 4. Components similar to those in the photoelectric conversion device according to the first embodiment are denoted by the same reference numerals, and their descriptions are omitted or simplified. Figure 4 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment.

[0115] In the first embodiment, the configuration and method for performing high-brightness black depth correction using a brightness identification signal J and a digital signal DN were described. In this embodiment, the configuration and method for performing high-brightness black depth correction using a digital signal DS in addition to the brightness identification signal J and digital signal DN are described.

[0116] As shown in Figure 4, the photoelectric conversion device according to this embodiment has a determination unit 72 connected to horizontal transfer line 52N in addition to horizontal transfer lines 52S and 52J. Other aspects are the same as the photoelectric conversion device according to the first embodiment.

[0117] In the first embodiment, high-brightness black sink correction was performed using the brightness identification signal J and the digital signal DN. However, if the correction process is performed using only the digital signal DN, it is possible that the high-brightness black sink correction may not function as expected.

[0118] Figure 5 schematically shows the distribution of the count value of the digital signal DN when normal light, not excessive light, is incident. In Figure 5, the horizontal axis represents the count value of the digital signal DN, and the vertical axis represents the number of pixels. When excessive light is incident, the count value of the digital signal DN becomes larger than the value of the judgment data DN_H, and is subject to correction.

[0119] The count value of the digital signal DN varies from pixel 12 to pixel, and has a distribution as shown in Figure 5(a), for example. Normally, when normal light, not excessive light, is incident, the count value of the digital signal DN at each pixel 12 is lower than the value of the judgment data DN_H. However, for some pixels 12, due to effects such as scratches during the manufacturing process, the count value of the digital signal DN may be slightly larger than the value of the judgment data DN_H even when no light is incident (see the ● mark in Figure 5(a)).

[0120] Furthermore, in the AD conversion of pixel signals, variations in the reference signal may increase due to factors such as temperature during shooting and various noises. As a result, the distribution of the count values ​​of the digital signal DN may broaden compared to the distribution in Figure 5(a), for example, as shown in Figure 5(b). In this case, the count value of pixel 12, which has the count value marked with a ● as described above, may become even larger, potentially exceeding the value of the judgment data DN_H despite being in a non-saturated state. Consequently, unintended black level correction is performed regardless of the amount of incident light, resulting in white-scratch pixels that output a white level regardless of the amount of incident light, leading to a decrease in yield and a decline in image quality.

[0121] From this perspective, in this embodiment, in addition to the luminance identification signal J and the digital signal DN, the digital signal DS is used to determine high-luminance black depth correction. That is, in this embodiment, the digital signal DN is compared with the determination data DN_H, and further, the digital signal value of the digital signal DS is compared with the determination value of the determination data DS_H. Here, the determination data DS_H is determined based on the value of the digital signal DS obtained when the photoelectric conversion element PD is saturated, and can be set to a white level value that is slightly smaller than the saturation state of the digital signal DS at high luminance, for example. The determination data DN_H can be set to a value that is slightly larger than the count value of the digital signal DN at high luminance, taking variability into account, as in the first embodiment. Then, when the luminance identification signal J indicates high luminance and the digital signals DN and DS are greater than or equal to the respective determination data DN_H and DS_H, high-luminance black depth correction is activated.

[0122] In other words, the difference processing unit 74 outputs a second value corresponding to the white level if the luminance identification signal J is 1, the value of the digital signal DN is greater than or equal to the determination value of the determination data DN_H, and the value of the digital signal DS is greater than or equal to the determination value of the determination data DS_H. In all other cases, the difference processing unit 74 outputs a first value, which is the difference value obtained by subtracting the digital signal DN from the digital signal DS.

[0123] In this embodiment, when the amount of incident light is excessive, the luminance identification signal J becomes a digital value of 1 indicating high luminance, the digital signal DN exceeds the judgment data DN_H, and the digital signal DS also exceeds the judgment data DS_H, so high-luminance blackout correction is performed. On the other hand, when a high-luminance amount of light that is not excessive is incident on the pixel 12, the luminance identification signal J becomes a digital value of 1 indicating high luminance. The digital signal DN becomes larger than the judgment data DN_H due to the effect of increased variation. The digital signal DS becomes smaller than the judgment data DS_H because it is in a non-saturated state. As a result, high-luminance blackout correction is not performed. When the amount of incident light is small and the luminance identification signal J is a digital value of 0, high-luminance blackout correction is not performed. Therefore, by performing high-luminance blackout determination using the digital signal DS as well, it is possible to suppress unintended blackout correction processing when a low amount of light is incident.

[0124] In the first embodiment, malfunctions in black level correction can be suppressed by increasing the judgment data DN_H while taking into account the variation increase process. However, in this case, the detection brightness of black level correction becomes higher than expected. According to this embodiment, black level correction can be performed more favorably.

[0125] Thus, according to this embodiment, even when processing pixel signals using multiple different gain settings, appropriate black level correction can be performed, and high-quality images can be obtained.

[0126] [Third Embodiment] A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Figure 6. Components similar to those in the photoelectric conversion devices of the first and second embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figure 6 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment.

[0127] In the first and second embodiments described above, a dual-slope AD conversion was shown in which two AD conversions were performed on a reference signal Vn using reference signals Vramp_l and Vramp_h, and one of them was output as a digital signal Dn based on the luminance identification signal J. In this embodiment, a configuration is shown in which one AD conversion is performed on a reference signal Vn using the reference signal Vramp_l.

[0128] The photoelectric converter according to this embodiment differs from the photoelectric converter according to the second embodiment in that, as shown in Figure 6, it controls the reference signal selection unit 36 ​​based solely on the luminance identification signal J, and has memory 46N instead of memories 46NL and 46NH. That is, the photoelectric converter according to this embodiment does not have an OR circuit LC1 and a reference signal selection unit 54, and does not use the control signal ΦRamp_sel as the control signal for the reference signal selection unit 36. The first input node of memory 46N is connected to the output node of the comparison circuit 34. The second input node of memory 46N is connected to the counter 50. The third input node of memory 46N is connected to the horizontal scanning circuit 60. The output node of memory 46N is connected to the horizontal transfer line 52N.

[0129] The difference processing unit 74 includes a correction circuit that corrects the count value of the digital signal DN according to the brightness identification signal J. When the brightness identification signal J is a digital value of 0, the count value of the input digital signal DN is used. When the brightness identification signal J is a digital value of 1, the count value of the digital signal DN is corrected by the difference in the slopes of the reference signals Vramp_l and Vramp_h, i.e., the gain ratio. Then, a difference processing is performed with the gain ratio correction result of the count value of the digital signal DS, and the digital signal DS2 is output. The signal processing unit 76 may further perform linearity correction processing to correct the gain ratio and offset deviation between the low-brightness signal and the high-brightness signal that occurs in each column circuit section.

[0130] Next, the driving method of the photoelectric converter according to this embodiment will be explained with reference to Figure 7. Figure 7 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. In Figure 7, the horizontal direction represents time, and the vertical direction represents the schematic waveform of each signal. In this embodiment, of the AD conversion period of the reference signal Vn, the AD conversion period using the reference signal Vramp_h (NH_AD period) is not performed, and only the AD conversion period using the reference signal Vramp_h (NL_AD period) is performed. Other points are basically the same as the driving method of the first embodiment explained with reference to Figure 3. Processes similar to those in the driving method of the first embodiment will be omitted from explanation as appropriate.

[0131] At time t41, the NL_AD period begins, and the reference signal output circuit 40 starts changing the potential of the reference signal Vramp_NL. The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_NL. When the potential of the reference signal Vramp_NL falls below the potential of the reference signals Vn(Vn1,Vn2,Vn3), a latch signal ΦLt pulse is generated, and the count value NL(NL1,NL2,NL3) indicated by the counter signal Φcot at that time is stored in memory 46N.

[0132] At the following time t51, the JUDGE period begins, during which the reference signal Vramp (reference Vramp_SL or reference signal Vramp_SH) used for AD conversion of the image signal Vs is selected, and the comparison result is stored in memory 44J.

[0133] At the following time t61, the S-AD period begins, and the potential of the reference signal Vramp, selected during the JUDGE period, starts to change. Counter 50 starts counting in synchronization with the start of the potential change of the reference signal Vramp. When the potential of the reference signal Vramp falls below the potential of the image signal Vs(Vs1,Vs2,Vs3), a latch signal ΦLt pulse is generated, and the count values ​​SL,SH(SL1,SH2,SH3) indicated by the counter signal Φcot at that time are stored in memory 46S.

[0134] High-brightness black level correction in the DSP70 can be performed using the digital signals DN, DS and the brightness identification signal J, in the same manner as in the first or second embodiment.

[0135] Thus, according to this embodiment, even in a dual-slope AD conversion method that performs one AD conversion with respect to the reference voltage, appropriate black level correction can be performed and high-quality images can be obtained.

[0136] [Fourth Embodiment] A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Figure 8. Components similar to those in the photoelectric conversion devices of the first to third embodiments will be denoted by the same reference numerals, and their descriptions will be omitted or simplified. Figure 8 is a block diagram showing the schematic configuration of the photoelectric conversion device according to this embodiment.

[0137] In the first to third embodiments described above, AD conversion results with different gain ratios were obtained by using ramp signals with different slopes. In this embodiment, a method for obtaining AD conversion results with different gain ratios will be described by performing analog amplification processing with different gain ratios on the analog signal output from the pixel 12, followed by AD conversion.

[0138] As shown in Figure 8, the photoelectric converter according to this embodiment further includes an amplification circuit 48 connected between the signal output line Yi and the comparison circuit 34. The amplification circuit 48 performs gain processing on the output voltage of the pixel 12 in accordance with the control signal ΦGain_sel and the brightness identification signal J from TG80, and outputs the pixel signal Vpix after gain processing to the comparison circuit 34.

[0139] The control node of the amplifier circuit 48 receives the control signal ΦGain_sel and the brightness identification signal J via the OR circuit LC2. As a result, when the control signal ΦGain_sel and the brightness identification signal J are at a low level, the amplifier circuit 48 performs gain processing (low brightness gain processing) on ​​the output voltage of the pixel 12 with a first gain. Furthermore, when at least one of the control signal ΦRamp_sel and the brightness identification signal J is at a high level, the amplifier circuit 48 performs gain processing (high brightness gain processing) on ​​the output voltage of the pixel 12 with a second gain smaller than the first gain.

[0140] Next, the driving method of the photoelectric converter according to this embodiment will be described with reference to Figure 9. Figure 9 is a timing diagram showing the driving method of the photoelectric converter according to this embodiment. In Figure 9, the horizontal direction represents time, and the vertical direction represents the schematic waveform of each signal. In this embodiment, during the AD conversion period of the reference signal Vn, AD conversion is performed on the reference signal Vn which has been subjected to high-brightness gain processing. During the AD conversion period of the image signal Vs, AD conversion is performed on the image signal Vs which has been subjected to the gain processing selected in the JUDGE period from among the high-brightness gain processing and low-brightness gain processing. Other points are basically the same as the driving method of the first embodiment described with reference to Figure 3. Processing similar to that of the driving method of the first embodiment will be omitted from explanation as appropriate.

[0141] In Figure 9, the period from time t41 to time t44 is the AD conversion period (N_AD conversion period) of the reference signal Vn that has undergone gain processing with the low-luminance gain. The period from time t51 to time t52 is the judgment period (JUDGE period) of the pixel signal Vpix using the judgment voltage Vjudge. The period from time t61 to time t64 is the AD conversion period (S_AD period) of the image signal Vs.

[0142] During the N_AD period, the comparator circuit 34 performs a comparison between the reference signal Vn, which has undergone low-luminance gain processing by the amplification circuit 48, and the reference signal Vramp. When the N_AD period begins at time t41, the reference signal output circuit 40 starts changing the potential of the reference signal Vramp (Vramp_N). The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_N. When the potential of the reference signal Vramp_N falls below the potential of the reference signals Vn (Vn1, Vn2, Vn3), a latch signal ΦLt pulse is generated, and the count value N (N1, N2, N3) indicated by the counter signal Φcot at that time is stored in the memory 46N.

[0143] During the JUDGE period, the comparison circuit 34 performs a comparison between the image signal Vs, which has undergone low-luminance gain processing by the amplification circuit 48, and the judgment voltage Vjudge. When the relative magnitudes of the potentials of the pixel signal Vpix and the judgment voltage Vjudge are reversed, the comparison circuit 34 generates a latch signal ΦLt based on this comparison result and also stores the comparison result in the memory 44J. The amplification circuit 48 selects the gain to be used during the S_AD period according to the luminance identification signal J indicating the comparison result and performs gain processing on the output voltage of the pixel 12.

[0144] For example, in Figure 9, when low-brightness normal light is incident, the image signal Vs1 is not below the judgment voltage Vjudge, so the amplifier circuit 48 performs low-brightness gain processing on the image signal Vs1. When low-brightness gain processing is selected, there is no change in gain from the JUDGE period, so the S_AD period is performed on the image signal Vs1. Also, when high-brightness normal light and excessive light are incident, the image signals Vs2 and Vs3 are below the judgment voltage Vjudge, so the amplifier circuit 48 performs high-brightness gain processing on the image signals Vs2 and Vs3 to narrow their amplitudes. When high-brightness gain processing is selected, the gain processing on the image signals Vs2 and Vs3 is changed from low-brightness gain processing to high-brightness gain processing. The image signals Vs2 and Vs3 after high-brightness gain processing are denoted as image signals Vs2' and Vs3'.

[0145] During the S_AD period, the comparison circuit 34 performs a comparison between the image signal Vs, which has undergone gain processing by the amplification circuit 48, and the reference signal Vramp. When the S_AD period begins at time t61, the reference signal output circuit 40 starts changing the potential of the reference signal Vramp (Vramp_S). The counter 50 starts counting in synchronization with the start of the change in the potential of the reference signal Vramp_S. When the potential of the reference signal Vramp_S falls below the potential of the image signal Vs (Vs1, Vs2', Vs3'), a latch signal pulse ΦLt is generated, and the count value S(SL1, SH2, SH3) indicated by the counter signal Φcot at that time is stored in the memory 46S.

[0146] The determination unit 72 performs black depth determination processing using the digital signals DS, DN and the brightness identification signal J output from the memories 46S, 46N, and 44J, similar to the first or second embodiment. If the determination result indicates that the amount of incident light is excessive, it outputs a correction signal ΦCt to the difference processing unit 74.

[0147] The difference processing unit 74 performs luminance correction processing and difference calculation of digital signals DS and DN based on the luminance identification signal J. If the correction signal ΦCt output by the determination unit 72 is invalid (low level), the difference processing unit 74 outputs the difference calculation result to the signal processing unit 76. On the other hand, if the correction signal ΦCt is valid (high level), the difference processing unit 74 outputs a white level correction value to the signal processing unit 76 instead of the difference calculation result.

[0148] As described above, this black level correction process can be implemented not only for AD conversion methods that change the slope of the reference signal, as in the first and second embodiments, but also for AD conversion methods in which the gain of the amplification circuit is variable. Similarly, when using AD conversion methods other than those described above that use a brightness identification signal, the black level correction process can be implemented by performing threshold determination using the AD conversion result and the brightness identification signal, as in this disclosure.

[0149] Thus, according to this embodiment, even when processing pixel signals using multiple different gain settings, appropriate black level correction can be performed, and high-quality images can be obtained.

[0150] [Fifth Embodiment] A fifth embodiment of the present invention, specifically an imaging system, will be described with reference to Figure 10. Figure 10 is a block diagram showing the schematic configuration of the imaging system according to this embodiment.

[0151] The photoelectric converter 100 described in the first to fourth embodiments above is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, photocopiers, fax machines, mobile phones, in-vehicle cameras, and observation satellites. Camera modules, which include optical systems such as lenses and imaging devices, are also included in imaging systems. Figure 10 shows a block diagram of a digital still camera as an example of these.

[0152] The imaging system 200 illustrated in Figure 10 includes an imaging device 201, a lens 202 for forming an optical image of a subject onto the imaging device 201, an aperture 204 for varying the amount of light passing through the lens 202, and a barrier 206 for protecting the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light onto the imaging device 201. The imaging device 201 is a photoelectric conversion device 100 described in any of the first to fourth embodiments, which converts the optical image formed by the lens 202 into image data.

[0153] The imaging system 200 also includes a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compressions as needed before outputting the image data. The imaging device 201 may include an AD conversion unit that generates the digital signal processed by the signal processing unit 208. The AD conversion unit may be formed on the semiconductor layer (semiconductor substrate) on which the photoelectric conversion unit of the imaging device 201 is formed, or on a different semiconductor layer (semiconductor substrate) from the semiconductor layer on which the photoelectric conversion unit of the imaging device 201 is formed. Alternatively, the signal processing unit 208 may be formed on the same semiconductor layer (semiconductor substrate) as the imaging device 201.

[0154] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the imaging system 200 includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or it may be detachable.

[0155] Furthermore, the imaging system 200 includes an overall control and calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least an imaging device 201 and a signal processing unit 208 that processes the output signals output from the imaging device 201.

[0156] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0157] Thus, according to this embodiment, an imaging system can be realized that applies the photoelectric converter 100 according to the first to fourth embodiments.

[0158] [Sixth Embodiment] A sixth embodiment of the present invention, consisting of an imaging system and a mobile body, will be described with reference to Figure 11. Figure 11 is a diagram showing the configuration of the imaging system and mobile body according to this embodiment.

[0159] Figure 11(a) shows an example of an imaging system for an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric converter 100 described in any of the first to fourth embodiments above. The imaging system 300 includes an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc. The collision determination unit 318 may use any of this distance information to determine the possibility of collision. The means for acquiring distance information may be implemented by specially designed hardware, or by a software module. It may also be implemented by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or a combination thereof.

[0160] The imaging system 300 is connected to the vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 318. The imaging system 300 is also connected to a warning device 340 that issues a warning to the driver based on the judgment result of the collision judgment unit 318. For example, if the collision judgment result of the collision judgment unit 318 indicates a high probability of collision, the control ECU 330 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 340 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0161] In this embodiment, the imaging system 300 captures images of the area around the vehicle, for example, the front or rear. Figure 11(b) shows the imaging system when capturing images of the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration allows for further improvement of the accuracy of distance measurement.

[0162] The above example illustrates control to prevent collisions with other vehicles, but it can also be applied to control systems that automatically follow other vehicles or automatically prevent vehicles from straying from their lanes. Furthermore, the imaging system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. In addition, it can be applied not only to moving objects but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS).

[0163] [Seventh Embodiment] A device according to the seventh embodiment of the present invention will be described with reference to Figure 12. Figure 12 is a block diagram showing the schematic configuration of the device according to this embodiment.

[0164] Figure 12 is a schematic diagram showing an instrument EQP including a photoelectric converter APR. The photoelectric converter APR has the functions of any of the first to fourth embodiments of the photoelectric converter 100. All or part of the photoelectric converter APR is a semiconductor device IC. The photoelectric converter APR in this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometering sensor, or a distance measuring sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including a photoelectric conversion unit are arranged in a matrix. The semiconductor device IC may have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0165] The photoelectric converter APR may have a stacked structure (chip stacking structure) comprising a first semiconductor chip equipped with multiple photoelectric conversion units and a second semiconductor chip equipped with peripheral circuits. The peripheral circuits on the second semiconductor chip can each be a column circuit corresponding to a pixel row of the first semiconductor chip. Alternatively, the peripheral circuits on the second semiconductor chip can each be a matrix circuit corresponding to a pixel or pixel block of the first semiconductor chip. Connections between the first and second semiconductor chips can be made using through-silicon vias (TSVs), direct bonding of conductors such as copper for inter-chip wiring, microbump connections between chips, or wire bonding.

[0166] The photoelectric converter APR may include a semiconductor device IC as well as a package PKG that houses the semiconductor device IC. The package PKG may include a substrate on which the semiconductor device IC is fixed, a cover made of glass or the like that faces the semiconductor device IC, and connecting members such as bonding wires or bumps that connect terminals provided on the substrate to terminals provided on the semiconductor device IC.

[0167] The EQP device may further comprise at least one of the following: an optical device OPT, a control unit CTRL, a processing unit PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric converter APR as a photoelectric converter, and is, for example, a lens, shutter, or mirror. The control unit CTRL controls the photoelectric converter APR and is, for example, a semiconductor device such as an ASIC. The processing unit PRCS processes the signals output from the photoelectric converter APR and constitutes an AFE (analog front end) or a DFE (digital front end). The processing unit PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or liquid crystal display device that displays information (images) obtained from the photoelectric converter APR. The memory device MMRY is a magnetic device or semiconductor device that stores information (images) obtained from the photoelectric converter APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive. The mechanical device MCHN has movable parts or propulsion parts such as motors and engines. The device EQP displays signals output from the photoelectric converter APR on the display device DSPL, or transmits them to the outside using a communication device (not shown) provided by the device EQP. For this purpose, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS, separate from the memory circuit and arithmetic circuit of the photoelectric converter APR.

[0168] The EQP (Equipment Equipment) shown in Figure 12 can be electronic devices such as information terminals with imaging capabilities (e.g., smartphones and wearable devices) or cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In cameras, the mechanical device MCHN can drive components of the optical device OPT for zooming, focusing, and shutter operation. Furthermore, the EQP can be transportation equipment (mobile devices) such as vehicles, ships, and aircraft. Additionally, the EQP can be medical equipment such as endoscopes and CT scanners.

[0169] The mechanical device MCHN in transport equipment can be used as a mobile device. The device EQP as transport equipment is suitable for transporting the photoelectric converter APR, or for assisting and / or automating driving (operation) through its imaging function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing to operate the mechanical device MCHN as a mobile device based on information obtained from the photoelectric converter APR.

[0170] The photoelectric converter APR according to this embodiment can provide high value to its designers, manufacturers, distributors, buyers, and / or users. Therefore, by installing the photoelectric converter APR in the EQP (Equipment Equipment), the value of the EQP can also be increased. Thus, when manufacturing and selling the EQP, deciding to install the photoelectric converter APR of this embodiment in the EQP is advantageous in increasing the value of the EQP.

[0171] [Modified Embodiment] The present invention is not limited to the embodiments described above and can be modified in various ways.

[0172] For example, an example in which a part of the configuration of one embodiment is added to another embodiment, or in which a part of the configuration of another embodiment is replaced, is also an embodiment of the present invention.

[0173] Furthermore, the circuit configuration of the pixel 12 shown in Figure 2 is illustrative and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. In this case, multiple photoelectric conversion elements may share one floating diffusion section (node ​​FD). Alternatively, multiple photoelectric conversion elements may share one microlens to form a pupil-splitting pixel, enabling the detection of phase differences. Also, the pixel 12 does not necessarily need to have a selection transistor M4. Furthermore, the capacitance value of the node FD may be switchable.

[0174] Furthermore, in the above embodiment, one column circuit section was provided for each row of the pixel section 10, but one column circuit section may be provided for multiple rows of the pixel section 10, or multiple column circuit sections may be provided for each row of the pixel section 10. These examples also include configurations in which each of the multiple column circuit sections is arranged in a row in which the pixels 12 are located.

[0175] Furthermore, although the above embodiments described an example in which the present invention is applied to a photoelectric converter having a slope-type AD conversion circuit, the AD conversion circuit in a photoelectric converter does not necessarily have to be a slope-type AD conversion circuit. The present invention is applicable not only to photoelectric converters having a slope-type AD conversion circuit, but also to photoelectric converters having other AD conversion circuits such as ΔΣ-type AD conversion circuits and successive approximation AD conversion circuits. In addition, although the first to third embodiments described an example in which the present invention is applied to a photoelectric converter having a dual-slope type AD conversion circuit, it is also possible to apply the present invention to a photoelectric converter having a multi-slope type AD conversion circuit using three or more types of reference signals.

[0176] Furthermore, in the above embodiment, the photoelectric converter 100 provided the functions of the DSP 70, but the functions of the DSP 70 do not necessarily have to be provided by the photoelectric converter 100. That is, at least some of the functions of the DSP 70 may be provided by a device other than the photoelectric converter 100. This other device could be, for example, a signal processing device such as a personal computer that includes a processor (e.g., a CPU or MPU) separate from the photoelectric converter 100. Alternatively, this other device could be a circuit such as an ASIC that implements at least some of the functions of the DSP 70.

[0177] Furthermore, the imaging systems shown in the fifth and sixth embodiments above are merely examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and the photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 10 and 11.

[0178] The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0179] It should be noted that the above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted as being limited by them. In other words, the present invention can be implemented in various forms without departing from its technical concept or its main features.

[0180] The above-disclosed embodiments include the following configurations and methods. (Composition 1) It has a photoelectric conversion unit that generates electric charge by photoelectric conversion, and a pixel that outputs an analog reference signal and an analog image signal, A readout unit that performs gain processing and analog-to-digital conversion processing on the analog reference signal and the analog image signal, and outputs a digital reference signal obtained by performing gain processing and analog-to-digital conversion processing on the analog reference signal, and a digital image signal obtained by performing analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain on the analog image signal. A difference processing unit outputs a first value, which is a value generated by difference processing between the digital image signal and the digital reference signal, when the analog image signal is subjected to gain processing with the first gain or the digital signal value, which is the value of the digital reference signal, is less than the first determination value, and outputs a second value, which is different from the value generated by difference processing, when the analog image signal is subjected to gain processing with the second gain and the digital signal value is greater than or equal to the first determination value. A photoelectric conversion device characterized by having the following features. (Configuration 2) The difference processing unit performs gain processing on the analog image signal with the second gain, and outputs the second value if the digital signal value of the digital reference signal is greater than or equal to the first determination value and the digital signal value of the digital image signal is greater than or equal to the second determination value; otherwise, outputs the value generated by the difference processing. A photoelectric conversion device according to configuration 1, characterized by the features described above. (Composition 3) The second determination value is determined based on the digital signal value of the digital image signal obtained when the analog image signal output from the pixel is gain-processed with the second gain when the photoelectric conversion unit is saturated. A photoelectric conversion device according to configuration 2, characterized by the features described above. (Composition 4) The readout unit performs gain processing on the analog image signal with the first gain when the amplitude of the analog image signal is less than or equal to the amplitude corresponding to a predetermined determination voltage, and performs gain processing on the analog image signal with the second gain when the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage. A photoelectric conversion device according to any one of configurations 1 to 3, characterized by the above. (Composition 5) The readout unit has a slope-type analog-to-digital conversion circuit, and if the amplitude of the analog image signal is less than or equal to the amplitude corresponding to the determination voltage, it converts the analog image signal from analog to digital using a first reference signal having a slope corresponding to the first gain, and if the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage, it converts the analog image signal from analog to digital using a second reference signal having a slope corresponding to the second gain. The photoelectric conversion device according to configuration 4, characterized by the features described above. (Composition 6) The readout unit includes an amplification circuit and an analog-to-digital conversion circuit. If the amplitude of the analog image signal is less than or equal to the amplitude corresponding to the determination voltage, the amplification circuit amplifies the analog image signal with a first gain and then converts it to a digital image signal using the analog-to-digital conversion circuit. If the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage, the amplification circuit amplifies the analog image signal with a second gain and then converts it to a digital image signal using the analog-to-digital conversion circuit. The photoelectric conversion device according to configuration 4, characterized by the features described above. (Composition 7) The readout unit performs gain processing on the analog reference signal using the first gain and the second gain. If the amplitude of the analog image signal is less than or equal to the amplitude corresponding to the determination voltage, it outputs the digital reference signal based on the analog reference signal that has been gain-processed with the first gain. If the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage, it outputs the digital reference signal based on the analog reference signal that has been gain-processed with the second gain. A photoelectric conversion device according to any one of configurations 4 to 6, characterized by the above. (Composition 8) The readout unit performs gain processing on the analog reference signal using the first gain and outputs the digital reference signal based on the analog reference signal that has been processed with the first gain. A photoelectric conversion device according to any one of configurations 4 to 6, characterized by the above. (Composition 9) The difference processing unit performs the difference processing after multiplying the digital signal value of the digital reference signal by the ratio of the second gain to the first gain, when the gain processing is performed on the analog image signal with the second gain. A photoelectric conversion device according to configuration 8, characterized by the above. (Composition 10) The second value is the maximum value that the digital signal value, which is the value of the digital image signal, can take. A photoelectric conversion device according to any one of configurations 1 to 9, characterized by the above. (Composition 11) The first determination value is determined based on the digital signal value of the digital reference signal obtained when the analog reference signal output from the pixel when the photoelectric conversion unit is saturated is gain-processed with the second gain. A photoelectric conversion device according to any one of configurations 1 to 10, characterized by the above. (Composition 12) When the analog image signal is subjected to gain processing with the second gain, the difference processing unit outputs a value obtained by multiplying the difference value by the ratio of the second gain to the first gain as the value generated by the difference processing. A photoelectric conversion device according to any one of configurations 1 to 11, characterized by the above. (Composition 13) The aforementioned pixel is composed of multiple pixels arranged in multiple rows and multiple columns, The readout unit has a plurality of column circuit units corresponding to the plurality of columns, and the plurality of column circuit units process the signals output from each of the pixels of the plurality of columns in parallel. A photoelectric conversion device according to any one of configurations 1 to 12, characterized by the above. (Composition 14) The difference processing unit sequentially processes the signals output from the plurality of column circuit units. A photoelectric conversion device according to configuration 13, characterized by the features described above. (Composition 15) A photoelectric conversion device according to any one of configurations 1 to 14, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A photoelectric conversion system characterized by having the following features. (Composition 16) It is a mobile object, A photoelectric conversion device according to any one of configurations 1 to 14, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features. (Composition 17) A photoelectric conversion device according to any one of configurations 1 to 14, An optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features. (Composition 18) A signal processing device that performs processing using a digital reference signal obtained by performing gain processing and analog-to-digital conversion processing on an analog reference signal, and a digital image signal obtained by performing analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain on an analog image signal, The differential processing unit outputs a first value, which is a value generated by the difference processing between the digital image signal and the digital reference signal, when the analog image signal is subjected to gain processing with the first gain or when the digital signal value, which is the value of the digital reference signal, is less than the first determination value. When the analog image signal is subjected to gain processing with the second gain and the digital signal value is greater than or equal to the first determination value, it outputs a second value, which is different from the value generated by the difference processing. A signal processing device characterized by the following: (Composition 19) A signal processing method using a digital reference signal obtained by performing gain processing and analog-to-digital conversion processing on an analog reference signal, and a digital image signal obtained by performing analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain on an analog image signal, The analog image signal is subjected to the gain processing with the second gain, and it is determined whether the digital signal value, which is the value of the digital reference signal, is greater than or equal to the first determination value. If the analog image signal is subjected to gain processing with the first gain or the digital signal value is less than the first determination value, a first value is output, which is a value generated by the difference processing between the digital image signal and the digital reference signal. If the analog image signal is subjected to gain processing with the second gain and the digital signal value is greater than or equal to the first determination value, a second value different from the value generated by the difference processing is output. A signal processing method characterized by the following: [Explanation of Symbols]

[0181] 10...Pixel area 12... pixels 30...Reading section 34…Comparison circuit 44J, 46S, 46N, 46NL, 46NH… Memory 70...DSP 72…Judgment section 74...Differential Processing Unit 76... Signal Processing Unit 80...TG 100... Photoelectric converter

Claims

1. It has a photoelectric conversion unit that generates electric charge by photoelectric conversion, and a pixel that outputs an analog reference signal and an analog image signal, A readout unit that performs gain processing and analog-to-digital conversion processing on the analog reference signal and the analog image signal, and outputs a digital reference signal obtained by performing gain processing and analog-to-digital conversion processing on the analog reference signal, and a digital image signal obtained by performing analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain on the analog image signal. A difference processing unit outputs a first value, which is a value generated by difference processing between the digital image signal and the digital reference signal, when the analog image signal is subjected to gain processing with the first gain or the digital signal value, which is the value of the digital reference signal, is less than the first determination value, and outputs a second value, which is different from the value generated by difference processing, when the analog image signal is subjected to gain processing with the second gain and the digital signal value is greater than or equal to the first determination value. A photoelectric conversion device characterized by having the following features.

2. The difference processing unit performs gain processing on the analog image signal with the second gain, and outputs the second value if the digital signal value of the digital reference signal is greater than or equal to the first determination value and the digital signal value of the digital image signal is greater than or equal to the second determination value; otherwise, outputs the value generated by the difference processing. The photoelectric conversion device according to claim 1, characterized by the features described above.

3. The second determination value is determined based on the digital signal value of the digital image signal obtained when the analog image signal output from the pixel is gain-processed with the second gain when the photoelectric conversion unit is saturated. The photoelectric conversion device according to claim 2.

4. The readout unit performs gain processing on the analog image signal with the first gain when the amplitude of the analog image signal is less than or equal to the amplitude corresponding to a predetermined determination voltage, and performs gain processing on the analog image signal with the second gain when the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage. The photoelectric conversion device according to claim 1, characterized by the features described above.

5. The readout unit has a slope-type analog-to-digital conversion circuit, and if the amplitude of the analog image signal is less than or equal to the amplitude corresponding to the determination voltage, it converts the analog image signal from analog to digital using a first reference signal having a slope corresponding to the first gain, and if the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage, it converts the analog image signal from analog to digital using a second reference signal having a slope corresponding to the second gain. The photoelectric conversion device according to feature 4.

6. The readout unit includes an amplification circuit and an analog-to-digital conversion circuit. If the amplitude of the analog image signal is less than or equal to the amplitude corresponding to the determination voltage, the amplification circuit amplifies the analog image signal with a first gain and then converts it to a digital image signal using the analog-to-digital conversion circuit. If the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage, the amplification circuit amplifies the analog image signal with a second gain and then converts it to a digital image signal using the analog-to-digital conversion circuit. The photoelectric conversion device according to feature 4.

7. The readout unit performs gain processing with the first gain and the second gain on the analog reference signal. If the amplitude of the analog image signal is less than or equal to the amplitude corresponding to the determination voltage, it outputs the digital reference signal based on the analog reference signal that has been gain-processed with the first gain. If the amplitude of the analog image signal is greater than the amplitude corresponding to the determination voltage, it outputs the digital reference signal based on the analog reference signal that has been gain-processed with the second gain. The photoelectric conversion device according to feature 4.

8. The readout unit performs gain processing on the analog reference signal using the first gain and outputs the digital reference signal based on the analog reference signal that has been processed with the first gain. The photoelectric conversion device according to feature 4.

9. The difference processing unit performs the difference processing after multiplying the digital signal value of the digital reference signal by the ratio of the second gain to the first gain, when the gain processing is performed on the analog image signal with the second gain. The photoelectric conversion device according to claim 8.

10. The second value is the maximum value that the digital signal value, which is the value of the digital image signal, can take. The photoelectric conversion device according to any one of claims 1 to 9.

11. The first determination value is determined based on the digital signal value of the digital reference signal obtained when the analog reference signal output from the pixel when the photoelectric conversion unit is saturated is gain-processed with the second gain. The photoelectric conversion device according to any one of claims 1 to 9.

12. When the analog image signal is subjected to gain processing with the second gain, the difference processing unit outputs a value obtained by multiplying the difference value by the ratio of the second gain to the first gain as the value generated by the difference processing. The photoelectric conversion device according to any one of claims 1 to 9.

13. The aforementioned pixel is composed of multiple pixels arranged in multiple rows and multiple columns, The readout unit has a plurality of column circuit units corresponding to the plurality of columns, and the plurality of column circuit units process the signals output from each of the pixels of the plurality of columns in parallel. The photoelectric conversion device according to any one of claims 1 to 9.

14. The difference processing unit sequentially processes the signals output from the plurality of column circuit units. The photoelectric conversion device according to claim 13, characterized in that it is a photoelectric conversion device.

15. A photoelectric conversion device according to any one of claims 1 to 9, A signal processing device that processes the signal output from the aforementioned photoelectric converter and A photoelectric conversion system characterized by having the following features.

16. It is a mobile object, A photoelectric conversion device according to any one of claims 1 to 9, Distance information acquisition means that acquires distance information to an object from a parallax image based on a signal from the aforementioned photoelectric converter, Control means for controlling the moving body based on the distance information A mobile body characterized by having the following features.

17. A photoelectric conversion device according to any one of claims 1 to 9, Optical device corresponding to the aforementioned photoelectric converter, A control device for controlling the aforementioned photoelectric converter, A processing device that processes the signal output from the aforementioned photoelectric converter, A mechanical device controlled based on information obtained from the aforementioned photoelectric converter, A display device for displaying information obtained by the aforementioned photoelectric converter, and A memory device for storing information obtained by the aforementioned photoelectric converter, and at least one of the following: A device characterized by being equipped with the following features.

18. A signal processing device that performs processing using a digital reference signal obtained by performing gain processing and analog-to-digital conversion processing on an analog reference signal, and a digital image signal obtained by performing analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain on an analog image signal, The differential processing unit outputs a first value, which is a value generated by difference processing between the digital image signal and the digital reference signal, when the analog image signal is subjected to gain processing with the first gain or when the digital signal value, which is the value of the digital reference signal, is less than a first determination value. When the analog image signal is subjected to gain processing with the second gain and the digital signal value is greater than or equal to the first determination value, it outputs a second value, which is different from the value generated by the difference processing. A signal processing device characterized by the following:

19. A signal processing method using a digital reference signal obtained by performing gain processing and analog-to-digital conversion processing on an analog reference signal, and a digital image signal obtained by performing analog-to-digital conversion processing and gain processing with a first gain or a second gain smaller than the first gain on an analog image signal, The analog image signal is subjected to the gain processing with the second gain, and it is determined whether the digital signal value, which is the value of the digital reference signal, is greater than or equal to the first determination value. If the analog image signal is subjected to gain processing with the first gain or the digital signal value is less than the first determination value, a first value is output, which is a value generated by the difference processing between the digital image signal and the digital reference signal. If the analog image signal is subjected to gain processing with the second gain and the digital signal value is greater than or equal to the first determination value, a second value different from the value generated by the difference processing is output. A signal processing method characterized by the following:

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