Semiconductor integrated circuits, systems

Abstract

To provide a semiconductor integrated circuit that can be tested under the same conditions as actual operation. [Solution] The image input interface 210 receives a digital video signal from the external circuit 110 and outputs input image data IMG1. The image processing circuit 230 performs predetermined signal processing on the image data output by the input selector SEL1. In test mode, the CRC circuit 240 calculates the CRC value of the output image data output from the image processing circuit 230. The output selector SEL2 selects the output image data IMG2p in normal mode and the dummy image data IMG3 in test mode. The image output interface 260 outputs the image data output by the output selector SEL2 to the display device 120. In test mode, the determination unit 280 compares the CRC value calculated by the CRC circuit 240 with the expected CRC value CRC_EXP.

Description

Technical Field

[0001] This disclosure relates to a semiconductor integrated circuit that handles images.

Background Art

[0002] As semiconductor integrated circuits (ICs) for images, there are bridge ICs, repeater ICs, scalers, serializers / deserializers, etc. A bridge IC has a function of converting one display system interface standard to another. Display system interface standards include LVDS (Low Voltage Differential Signaling), DP, MIPI (Mobile Industry Processor Interface), HDMI (High-Definition Multimedia Interface), etc.

[0003] A scaler has a function of converting the resolution of an input image to a resolution suitable for a display. A repeater IC is inserted into a long transmission path of image data, receives a signal distorted in the transmission path, returns it to its original state, and transmits it.

[0004] Serializers and deserializers are used for long-distance transmission of image data. A serializer receives image data, encodes it, converts it into a serial signal, and transmits it to a deserializer. A deserializer receives a serial signal, decodes it, restores the original image data, and outputs it to another IC.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] When semiconductor integrated circuits for imaging are used in automotive applications, high reliability is required. Therefore, these semiconductor integrated circuits have implemented scan tests and RAMBIST (Random Access Memory Built-In Self Test) to ensure functional safety. However, these conventional methods perform tests under conditions different from actual circuit operation, making it difficult to accurately verify whether the actual circuit is functioning correctly.

[0007] [overview] This disclosure has been made in view of the aforementioned issues, and one exemplary objective of a certain aspect thereof is to provide a semiconductor integrated circuit that can be tested under the same conditions as actual operation.

[0008] A semiconductor integrated circuit in one aspect of the present disclosure includes: an image input interface that receives a digital video signal from an external circuit and outputs input image data; a test image generation unit that generates predetermined test image data; an input selector that selects input image data in normal mode and test image data in test mode; an image processing circuit that performs predetermined signal processing on the image data output by the input selector; a CRC circuit that calculates a CRC (cyclic redundancy check) value of the output image data output from the image processing circuit in test mode; a dummy image generation unit that generates dummy image data that is substantially one color in test mode; an output selector that selects output image data in normal mode and dummy image data in test mode; an image output interface that outputs the image data output by the output selector to a display device; a memory that holds a CRC expected value, which is the CRC value of the output image data that should be obtained when the image processing circuit correctly performs predetermined signal processing on the test image data; and a determination unit that compares the CRC value calculated by the CRC circuit with the CRC expected value in test mode.

[0009] Another aspect of the present disclosure is a system comprising a first semiconductor integrated circuit and a second semiconductor integrated circuit. The first semiconductor integrated circuit comprises an image input interface that receives a digital video signal and outputs input image data, a test image generation unit that generates predetermined test image data, an input selector that selects input image data in normal mode and test image data in test mode, an encoder that encodes the image data output by the input selector, and a transmitter that transmits a serial signal including a bit sequence output by the encoder to the second semiconductor integrated circuit. The second semiconductor integrated circuit includes a receiver that receives a serial signal from the transmitter of the first semiconductor integrated circuit, a decoder that decodes the serial signal received by the receiver into image data, a CRC circuit that calculates the CRC (Cyclic Redundancy Check) value of the output image data output from the decoder in test mode, a dummy image generation unit that generates dummy image data that is substantially one color in test mode, an output selector that selects the output image data output from the encoder in normal mode and selects the dummy image data in test mode, an image output interface that outputs the image data output by the output selector to an image display device, a memory that holds the expected CRC value, which is the CRC value of the output image data that should be obtained when the receiver correctly receives the serial signal and the decoder correctly decodes the serial signal, and a determination unit that compares the CRC value calculated by the CRC circuit with the expected CRC value in test mode.

[0010] Furthermore, any combination of the above components, or any conversion of the expressions of this disclosure between methods, apparatus, etc., is also valid as a form of this disclosure. Moreover, the description in this section does not describe all the essential features of this disclosure, and therefore, subcombinations of these features described may also constitute this disclosure. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a block diagram of a system comprising a semiconductor integrated circuit according to Embodiment 1. [Figure 2] Figure 2 illustrates the CRC value of image data. [Figure 3] Figure 3 is a block diagram of the system in test mode. [Figure 4] Figure 4 illustrates the switching operation of the output selector. [Figure 5] Figure 5 is a block diagram of the system in normal mode. [Figure 6] Figure 6 is a block diagram of the system according to Embodiment 2. [Figure 7] Figure 7 is a block diagram of the system in test mode. [Figure 8] Figure 8 is a block diagram of the system in normal mode. [Figure 9] Figure 9 is a block diagram of the system according to Modification Example 1. [Figure 10] Figure 10 is a block diagram of the system relating to Modification Example 2.

[0012] [Detailed explanation] (Summary of the embodiment) A semiconductor integrated circuit according to one embodiment includes: an image input interface that receives a digital video signal from an external circuit and outputs input image data; a test image generation unit that generates predetermined test image data; an input selector that selects input image data in normal mode and test image data in test mode; an image processing circuit that performs predetermined signal processing on the image data output by the input selector; a CRC (Cyclic Redundancy Check) circuit that calculates the CRC value of the output image data output from the image processing circuit in test mode; a dummy image generation unit that generates dummy image data that is substantially one color in test mode; an output selector that selects output image data in normal mode and dummy image data in test mode; an image output interface that outputs the image data output by the output selector to a display device; a memory that holds a CRC expected value, which is the CRC value of the output image data that should be obtained when the image processing circuit correctly performs predetermined signal processing on the test image data; and a determination unit that compares the CRC value calculated by the CRC circuit with the CRC expected value in test mode.

[0013] In this configuration, predetermined test image data is prepared in advance, and an image processing circuit performs the same processing as in actual operation on it, and the resulting CRC value of the image data is calculated. Then, by comparing the calculated CRC value with a pre-prepared expected CRC value, it becomes possible to perform functional testing of semiconductor integrated circuits under the same conditions as in actual operation. By comparing CRC values, the amount of data and computational load can be reduced compared to comparing image data directly.

[0014] In one embodiment, the CRC circuit may calculate the CRC value for each of the R, G, and B values ​​that constitute each pixel of the output image data.

[0015] In one embodiment, the CRC circuit may left-align the R, G, and B values ​​that constitute each pixel of the output image data, generate a bit sequence in which the lower bits are filled with 0, and then calculate the CRC value.

[0016] In one embodiment, the semiconductor integrated circuit may further include a communication circuit. The communication circuit may obtain parameters that define the operation of the image processing circuit and obtain a CRC expected value when the semiconductor integrated circuit is activated.

[0017] In one embodiment, the test image generation unit may include a pattern generator. By generating test image data by the pattern generator, a memory for storing the test image data becomes unnecessary.

[0018] In one embodiment, the semiconductor integrated circuit may be a bridge IC, a repeater IC, or a scaler IC.

[0019] In one embodiment, after the end of the test mode, the output selector may switch from dummy image data to output image data during the blank period between frames. Thereby, it is possible to prevent the image displayed on the display from being disturbed.

[0020] A system according to an embodiment includes a first semiconductor integrated circuit and a second semiconductor integrated circuit. The first semiconductor integrated circuit includes an image input interface that receives a digital video signal and outputs input image data, a test image generation unit that generates predetermined test image data, an input selector that selects the input image data in a normal mode and selects the test image data in a test mode, an encoder that encodes the image data output by the input selector, and a transmitter that transmits a serial signal including a bit string output by the encoder to the second semiconductor integrated circuit. The second semiconductor integrated circuit includes a receiver that receives the serial signal from the transmitter of the first semiconductor integrated circuit, a decoder that decodes the serial signal received by the receiver into image data, a CRC circuit that calculates a CRC (Cyclic Redundancy Check) value of the output image data output from the decoder in a test mode, a dummy image generation unit that generates dummy image data that is substantially a single color in a test mode, an output selector that selects the output image data output from the encoder in a normal mode and selects the dummy image data in a test mode, an image output interface that outputs the image data output by the output selector to an image display device, a memory that holds a CRC expected value that is the CRC value of the output image data to be obtained when the receiver correctly receives the serial signal and the decoder correctly decodes the serial signal, and a determination unit that compares the CRC value calculated by the CRC circuit with the CRC expected value in a test mode.

[0021] According to this configuration, predetermined test image data is prepared, transmitted from the first semiconductor integrated circuit to the second semiconductor integrated circuit, and the CRC value of the test image data is calculated in the second semiconductor integrated circuit. Then, by comparing the calculated CRC value with the CRC expected value prepared in advance, it becomes possible to perform a function test of the first semiconductor integrated circuit and the second semiconductor integrated circuit under the same conditions as the actual operation. By comparing the CRC values, the data amount and the calculation load can be reduced compared to the case of comparing the image data with each other.

[0022] In one embodiment, the CRC circuit may calculate the CRC value for each of the R, G, and B values ​​that constitute each pixel of the output image data.

[0023] In one embodiment, the CRC circuit may left-align the R, G, and B values ​​that constitute each pixel of the output image data, generate a bit sequence in which the lower bits are filled with 0, and then calculate the CRC value.

[0024] In one embodiment, the first semiconductor integrated circuit may further include a communication circuit. The communication circuit may acquire parameters that define the operation of the system when the system is started, and also acquire a CRC expectation value, which may be supplied to the memory via the encoder and transmitter of the first semiconductor integrated circuit and the receiver and decoder of the second semiconductor integrated circuit.

[0025] In one embodiment, the second semiconductor integrated circuit may further include a communication circuit. The transmitter of the first semiconductor integrated circuit and the receiver of the second semiconductor integrated circuit may be bidirectional. The communication circuit may acquire parameters defining the operation of the system and the CRC expectation value when the system is started up. The parameters defining the operation of the system may be transmitted from the receiver of the second semiconductor integrated circuit to the transmitter of the first semiconductor integrated circuit.

[0026] In one embodiment, the test image generation unit may include a pattern generator.

[0027] (Embodiment) The present invention will be described below with reference to the drawings, based on preferred embodiments. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the invention.

[0028] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not affect the electrical connection or impede their function.

[0029] Similarly, "the state in which member C is provided between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not affect the electrical connection state or impede their function.

[0030] (Embodiment 1) Figure 1 is a block diagram of a system 100 comprising a semiconductor integrated circuit 200 according to Embodiment 1. The system 100 includes an external circuit 110, a display device 120, a non-volatile memory 130, a controller 140, and a semiconductor integrated circuit 200.

[0031] The external circuit 110 generates image data IMG1 to be displayed on the display device 120 and transmits a digital video signal S1 containing the image data IMG1 to the semiconductor integrated circuit 200. The semiconductor integrated circuit 200 receives the digital video signal S1, performs predetermined signal processing on the image data (referred to as input image data) IMG1, and outputs it to the display device 120. The controller 140 controls the entire system 100.

[0032] Examples of semiconductor integrated circuits 200 include bridge ICs, repeater ICs, and scaler ICs. A bridge IC is used when the specifications of the image output interface of the external circuit 110 do not match the specifications of the image input interface of the display device 120. A repeater IC is used when the external circuit 110 and the display device 120 are far apart, provided that the specifications of the image output interface of the external circuit 110 and the image input interface of the display device 120 match. A scaler IC is used when the resolution of the image data generated by the external circuit 110 does not match the resolution of the display device 120. The semiconductor integrated circuit 200 may also have a combination of functions of a bridge IC, a repeater IC, and a scaler IC.

[0033] The semiconductor integrated circuit 200 includes an image input interface 210, a test image generation unit 220, an input selector SEL1, an image processing circuit 230, a CRC circuit 240, a dummy image generation unit 250, an output selector SEL2, an image output interface 260, a memory 270, a determination unit 280, and a communication circuit 290.

[0034] The image input interface 210 conforms to the same standards as the image output interface of the external circuit 110 and receives a digital video signal S1 including input image data IMG1 from the external circuit 110.

[0035] The test image generation unit 220 generates a predetermined test image data IMG2 in test mode. The test image data IMG2 has the same resolution and color depth as the input image data IMG1.

[0036] For example, the test image generation unit 220 may include a pattern generator. The pattern generator generates test image data IMG2 containing a predetermined pattern based on the parameter PRM1 stored in the memory 270. The parameter PRM1 is determined according to the resolution, color depth, etc., of the test image data IMG2.

[0037] Alternatively, the test image data IMG2 itself may be stored in memory 270, and the test image generation unit 220 may load this test image data IMG2. Memory 270 is accessible from the controller 140.

[0038] The input selector SEL1 selects input image data IMG1 in normal mode and test image data IMG2 in test mode.

[0039] The image processing circuit 230 applies predetermined signal processing to the image data output by the input selector SEL1. The image processing can be set according to the parameters PRM2 stored in the memory 270. Parameters PRM2 may include the resolution and color depth of the input image data IMG1, the resolution and color depth of the output image data IMG1p, the type of signal processing, and the parameters used for signal processing.

[0040] In other words, in normal mode, the image processing circuit 230 performs image processing on the input image data IMG1 to generate the output image data IMG1p.

[0041] In test mode, the image processing circuit 230 performs image processing on the test image data IMG2 to generate output image data IMG2p.

[0042] In test mode, the CRC circuit 240 calculates the CRC (Cyclic Redundancy Check) value of the output image data IMG2p output from the image processing circuit 230.

[0043] Figure 2 illustrates the CRC values ​​of the image data IMG. The image data IMG contains multiple pixels PIX, each containing R, G, and B values. The CRC circuit 240 divides the bit sequence corresponding to the R value by a predetermined value (generating polynomial) and outputs the remainders as the R_CRC values. The G_CRC and B_CRC values ​​are generated similarly. R_CRC, G_CRC, and B_CRC values ​​are generated for each pixel.

[0044] The number of bits m in the bit sequence used for CRC can be 32 bits, 16 bits, etc. For example, if the bit sequence for CRC is m bits and the R value, G value, and B value are each n bits, the CRC value can be calculated after converting the n bits to m bits. The conversion process is not particularly limited, but for example, the R value may be left-aligned to the most significant n bits of the m bits, and the least significant (mn) bits of the m bits may be padded with zeros. The same applies to the G value and B value.

[0045] Returning to Figure 1, the dummy image generation unit 250 generates dummy image data IMG3, which is substantially monochromatic, in test mode. For example, dummy image data IMG3 may be entirely black or entirely gray. Being substantially monochromatic means being monochromatic to an extent that is imperceptible to the human eye, and dummy image data IMG3 may have a gradation distribution.

[0046] The output selector SEL2 selects output image data IMG1p in normal mode and dummy image data IMG3 in test mode.

[0047] The image output interface 260 outputs the image data output by the output selector SEL2 to the display device 120. In normal mode, the image output interface 260 outputs the output image data IMG1p to the display device 120, and in test mode, it outputs dummy image data IMG3 to the display device 120.

[0048] The output image data IMG2p that should be obtained when the image processing circuit 230 correctly applies predetermined signal processing to the test image data IMG2 is called the expected output image data IMG2p_EXP. The memory 270 stores the CRC value (referred to as the expected CRC value) CRC_EXP that corresponds to this expected output image data IMG2p_EXP.

[0049] In test mode, the determination unit 280 compares the CRC value calculated by the CRC circuit 240 with the CRC expected value CRC_EXP and determines whether they match or not. If they match, it indicates that the semiconductor integrated circuit 200 is operating normally. Conversely, if they do not match, it indicates that the semiconductor integrated circuit 200 is not operating normally.

[0050] For example, the determination result RESULT of the determination unit 280 is written to the memory 270. The controller 140 may take the lead in reading the determination result RESULT from the memory 270. Alternatively, the semiconductor integrated circuit 200 may take the lead in transmitting the determination result RESULT from the communication circuit 290 to the controller 140. Alternatively, the controller 140 and the semiconductor integrated circuit 200 may be connected by a dedicated interrupt line, and the determination result RESULT may be notified to the controller 140 via this interrupt line.

[0051] The above describes the configuration of System 100. Next, we will explain its operation.

[0052] (System startup) First, the system starts up. When the system starts up, the parameter sets PRM1, PRM2, and the aforementioned CRC expectation value CRC_EXP, which are necessary for the operation of the semiconductor integrated circuit 200, are loaded from the non-volatile memory 130 into the semiconductor integrated circuit 200.

[0053] These loads may be performed by communication between the communication circuit 290 and the controller 140. Specifically, the controller 140 may read the parameter group PRM1, PRM2 and the above-mentioned CRC expectation value CRC_EXP from the non-volatile memory 130 and write them to memory 270.

[0054] Alternatively, the communication circuit 290 may directly access the non-volatile memory 130, read the parameter group PRM1, PRM2 and the above-mentioned CRC expected value CRC_EXP from the non-volatile memory 130, and write them to the memory 270.

[0055] (Test mode) After system 100 is started, the semiconductor integrated circuit 200 switches to test mode.

[0056] Figure 3 is a block diagram of system 100 in test mode. In test mode, the test image generation unit 220 generates test image data IMG2. The test image data IMG2 is supplied to the image processing circuit 230 via the input selector SEL1. The image processing circuit 230 processes the test image data IMG2 based on the parameter PRM2 and generates output image data IMG2p. The CRC circuit 240 calculates the CRC value for the output image data IMG2p. The determination unit 280 compares the CRC value calculated by the CRC circuit 240 with the CRC expected value CRC_EXP stored in memory 270 and generates a determination result RESULT indicating a match or mismatch. If the two match, the processing of the semiconductor integrated circuit 200 is considered normal, and the system proceeds to the next normal mode operation.

[0057] During test mode, the dummy image generation unit 250 generates dummy image data IMG3. The output selector SEL2 selects the dummy image data IMG3. The image output interface 260 outputs the dummy image data IMG3 to the display device 120. This prevents the test image data IMG2 from being displayed on the display device 120.

[0058] Figure 4 illustrates the switching operation of the output selector SEL2. After the test mode ends, the output selector SEL2 switches from dummy image data IMG3 to output image data IMG1p during the blank period Tblank between frames. This suppresses image distortion displayed on the display device 120.

[0059] (Normal mode) Figure 5 is a block diagram of system 100 in normal mode. In normal mode, the test image generation unit 220 is stopped. The input selector SEL1 selects the input image data IMG1 received by the image input interface 210. The image processing circuit 230 processes the input image data IMG1 based on the parameter PRM2 and generates output image data IMG1p. The output image data IMG1p is input to the image output interface 260 via the output selector SEL2. The image output interface 260 transmits the output image data IMG1p to the display device 120.

[0060] The above describes the operation of System 100.

[0061] According to the semiconductor integrated circuit 200 of this embodiment, test image data IMG2 is prepared in advance, and the same processing as in actual operation is performed on it by the image processing circuit 230, and the resulting CRC value of the image data is calculated. Then, by comparing the calculated CRC value with a pre-prepared expected CRC value, it becomes possible to test the functionality of the semiconductor integrated circuit 200 under the same conditions as in actual operation. By comparing CRC values, the amount of data and computational load can be reduced compared to comparing image data with each other.

[0062] (Embodiment 2) Figure 6 is a block diagram of system 300 according to Embodiment 2. System 300 includes an external circuit 310, a display device 320, a non-volatile memory 330, a controller 340, a first IC 400, and a second IC 500.

[0063] The external circuit 310 generates image data IMG1 to be displayed on the display device 320 and transmits a digital video signal S1 containing the image data IMG1 to the first IC 400. The external circuit 310 and the display device 320 are located at a long distance apart, several meters to more than ten meters. The first IC 400 and the second IC 500 are located on this long transmission path and transmit images from the external circuit 310 to the display device 320. The first IC 400 is also called a serializer IC, and the second IC 500 is also called a deserializer IC. Alternatively, the first IC 400 may be called a transmitter IC and the second IC 500 a receiver IC. The second IC 500 outputs the image data received from the first IC 400 to the display device 320.

[0064] The controller 340 controls the entire system 300. In this embodiment, the controller 340 controls the first IC 400 side The non-volatile memory 330 stores a set of parameters that define the operation of the first IC400 and the second IC500, as well as the expected CRC value.

[0065] The first IC 400 includes an image input interface 410, a test image generation unit 420, an input selector SEL1, an encoder 430, a transmitter 440, a memory 470, and a communication circuit 490.

[0066] The image input interface 410 conforms to the same standards as the image output interface of the external circuit 310 and receives a digital video signal S1 including input image data IMG1 from the external circuit 310.

[0067] The test image generation unit 420 generates a predetermined test image data IMG2 in test mode. The test image data IMG2 has the same resolution and color depth as the input image data IMG1.

[0068] For example, the test image generation unit 420 may include a pattern generator. The pattern generator generates test image data IMG2 containing a predetermined pattern based on the parameter PRM1 stored in the memory 470. The parameter PRM1 is determined according to the resolution, color depth, etc., of the test image data IMG2.

[0069] Alternatively, the test image data IMG2 itself may be stored in memory 470, and the test image generation unit 420 may load this test image data IMG2. Memory 470 is accessible from the controller 340.

[0070] The input selector SEL1 selects input image data IMG1 in normal mode and test image data IMG2 in test mode.

[0071] The encoder 430 encodes and performs parallel / serial conversion of the image data output by the input selector SEL1. The operating parameters PRM2 of the encoder 430 are stored in memory 470. Parameters PRM2 may include information such as the resolution and color depth of the input image data IMG1, encoding parameters, and the format of the serial signal.

[0072] In other words, in normal mode, the encoder 430 generates a serial signal corresponding to the input image data IMG1, and in test mode, it generates a serial signal corresponding to the test image data IMG2.

[0073] The transmitter 440 transmits a serial signal to the receiver 510 of the second IC 500.

[0074] The second IC 500 includes a receiver 510, a decoder 520, a CRC circuit 540, a dummy image generation unit 550, an image output interface 560, a memory 570, and a determination unit 580.

[0075] The receiver 510 receives a serial signal from the transmitter 440.

[0076] The decoder 520 converts the serial signal received by the receiver 510 into a parallel signal and decodes it. The operating parameters PRM3 of the decoder 520 are stored in the memory 570. The parameters PRM3 may include information about the resolution and color depth of the input image data IMG1, encoding parameters, and the format of the serial signal.

[0077] In normal mode, the decoder 520 generates output image data IMG1rx corresponding to the input image data IMG1, and in test mode, it generates output image data IMG2rx corresponding to the test image data IMG2.

[0078] In test mode, the CRC circuit 540 calculates the CRC (Cyclic Redundancy Check) value of the output image data IMG2rx output from the decoder 520.

[0079] The dummy image generation unit 550 generates dummy image data IMG3, which is substantially monochromatic, in test mode. For example, dummy image data IMG3 may be entirely black or entirely gray. Being substantially monochromatic means being monochromatic to an extent that is imperceptible to the human eye, and dummy image data IMG3 may have a gradation distribution.

[0080] The output selector SEL2 selects the output image data IMG1rx in normal mode and the dummy image data IMG3 in test mode.

[0081] The image output interface 560 outputs the image data output by the output selector SEL2 to the display device 320. In normal mode, the image output interface 560 outputs the output image data IMG1rx to the display device 320, and in test mode, it outputs dummy image data IMG3 to the display device 320.

[0082] The image data IMG2rx that the second IC500 should obtain when it correctly receives the test image data IMG2 is called the expected output image data IMG2rx_EXP. Memory 570 stores the CRC value (called the expected CRC value) CRC_EXP that corresponds to this expected output image data IMG2rx_EXP.

[0083] In test mode, the determination unit 580 compares the CRC value calculated by the CRC circuit 540 with the expected CRC value CRC_EXP and determines whether they match or not. If they match, it indicates that the system 300 is operating normally. Conversely, if they do not match, it indicates that the system 300 is not operating normally.

[0084] For example, the transmitter 440 and the receiver 510 are capable of bidirectional communication. The determination result RESULT from the determination unit 580 is transmitted from the receiver 510 to the transmitter 440 and stored in the memory 470. The controller 340 may read the determination result RESULT from the memory 470. Alternatively, the first IC 400 may transmit the determination result RESULT from the communication circuit 490 to the controller 340. Alternatively, the controller 340 and the first IC 400 may be connected by a dedicated interrupt line, and the determination result RESULT may be notified to the controller 340 via this interrupt line.

[0085] The above describes the configuration of System 300. Next, we will explain its operation.

[0086] (System startup) First, the system starts up. When the system starts up, the parameter sets PRM1, PRM2, PRM3, and the aforementioned CRC expectation value CRC_EXP, which are necessary for the operation of the first IC400 and the second IC500, are loaded from the non-volatile memory 330 into the first IC400.

[0087] These loads may be performed by communication between the communication circuit 490 and the controller 340. Specifically, the controller 340 may read the parameter group PRM1 to PRM3 and the above-mentioned CRC expectation value CRC_EXP from the non-volatile memory 330 and write them to memory 470.

[0088] Alternatively, the communication circuit 490 may directly access the non-volatile memory 330, read the parameter group PRM1~PRM3 and the CRC expectation value CRC_EXP from the non-volatile memory 330, and write them to memory 470. Parameter PRM3 and the CRC expectation value CRC_EXP are transmitted to the second IC 500 using the transmitter 440 and receiver 510, and loaded into memory 570.

[0089] (Test mode) After system 300 is started, the first IC400 and the second IC500 switch to test mode.

[0090] Figure 7 is a block diagram of the system 300 in test mode. In test mode, the test image generation unit 420 generates test image data IMG2. The test image data IMG2 is supplied to the encoder 430 via the input selector SEL1. The encoder 430 and transmitter 440 convert the test image data IMG2 into a serial signal and transmit it to the second IC 500. The receiver 510 and decoder 520 receive the serial signal and restore output image data IMG2rx, which represents the original test image data IMG2.

[0091] The CRC circuit 540 calculates a CRC value for the output image data IMG2rx. The determination unit 580 compares the CRC value calculated by the CRC circuit 540 with the expected CRC value CRC_EXP stored in the memory 570 and generates a determination result RESULT indicating a match or mismatch. The determination result RESULT is transmitted from the second IC 500 to the first IC 400 via the receiver 510 and transmitter 440, and notified to the controller 340. If both match, the system 300 is considered normal and proceeds to the next normal mode of operation.

[0092] During test mode, the dummy image generation unit 550 generates dummy image data IMG3. The output selector SEL2 selects the dummy image data IMG3. The image output interface 560 outputs the dummy image data IMG3 to the display device 320. This prevents the test image data IMG2 from being displayed on the display device 320.

[0093] (Normal mode) Figure 8 is a block diagram of the system 300 in normal mode. In normal mode, the test image generation unit 220 is stopped. The input selector SEL1 selects the input image data IMG1 received by the image input interface 410. The encoder 430 and transmitter 440 convert the input image data IMG1 into a serial signal and transmit it to the second IC 500. The receiver 510 and decoder 520 receive the serial signal and restore the output image data IMG1rx, which represents the original input image data IMG1.

[0094] The output image data IMG1rx is input to the image output interface 560 via the output selector SEL2. The image output interface 560 transmits the output image data IMG1rx to the display device 320.

[0095] The above describes the operation of system 300.

[0096] According to the system 300 of Embodiment 2, test image data IMG2 is prepared in advance and transmitted from the first IC 400 to the second IC 500. The second IC 500 then restores the test image data IMG2 and calculates the CRC value. By comparing the calculated CRC value with a pre-prepared expected CRC value, it becomes possible to test the functionality of the system 300 under the same conditions as actual operation. By comparing CRC values, the amount of data and computational load can be reduced compared to comparing image data directly.

[0097] Next, a modified example of the system 300 according to Embodiment 2 will be described.

[0098] (Variation 1) Figure 9 is a block diagram of system 300A according to Modification 1. In this Modification 1, the non-volatile memory 330 and controller 340 are located on the second IC 500 side. Therefore, the second IC 500 is provided with a communication circuit 590 for communicating with the controller 340 and / or the non-volatile memory 330.

[0099] When the system starts up, the parameter PRM3 and the expected CRC value CRC_EXP are loaded into memory 570 of the second IC500. The parameters PRM1 and RPM2 are loaded into memory 470 of the first IC400 via the second IC500. Other aspects are the same as in Embodiment 2.

[0100] (Modification 2) Figure 10 is a block diagram of system 300B according to modified example 2. In this modified example 2, the second IC 500 is provided with an image processing unit 530. The image processing unit 530 performs predetermined image processing on the output image data IMG1rx and IMG2rx generated by the decoder 520 to generate output image data IMG1rxp and IMG2rxp. The content of the image processing is not particularly limited, but it may be the same processing as that of the image processing circuit 230 described in Embodiment 1. That is, in addition to the function of a deserializer IC (receiver IC), the second IC 500 may also have functions such as a bridge IC, repeater IC, and scaler IC.

[0101] The CRC circuit 540 calculates the CRC value of the output image data IMG2rxp after processing by the image processing unit 530. The determination unit 580 compares the CRC value of the output image data IMG2rxp with its expected value CRC_EXP.

[0102] The image processing unit 530 may be provided in the second IC 500 in the modified example 1 of Figure 9.

[0103] (Other variations) The method for calculating the CRC value of image data is not limited to those described in the embodiments. For example, for each pixel, the R, G, and B values ​​may be combined or the order of the bits may be rearranged to create one or more bit sequences, and the CRC value (modulo) may be obtained by dividing each bit sequence by a generating polynomial.

[0104] Although this disclosure has been described using specific terminology based on embodiments, embodiments merely illustrate the principles and applications of this disclosure, and many modifications and changes in arrangement are permitted in embodiments without departing from the spirit of the invention as defined in the claims.

[0105] (Note) The technology disclosed herein can be understood in one respect as follows:

[0106] (Item 1) An image input interface that receives a digital video signal from an external circuit and outputs input image data, A test image generation unit that generates predetermined test image data, An input selector that selects the input image data in normal mode and the test image data in test mode, An image processing circuit that applies predetermined signal processing to the image data output by the input selector, In the aforementioned test mode, a CRC circuit calculates the CRC (Cyclic Redundancy Check) value of the output image data output from the image processing circuit, In test mode, a dummy image generation unit generates dummy image data that is essentially a single color, An output selector that selects the output image data in the normal mode and the dummy image data in the test mode, The image output interface outputs the image data output by the output selector to a display device, A memory that stores the CRC expected value, which is the CRC value of the output image data that should be obtained when the image processing circuit correctly applies the predetermined signal processing to the test image data, In the test mode, a determination unit compares the CRC value calculated by the CRC circuit with the expected CRC value, A semiconductor integrated circuit equipped with the following features.

[0107] (Item 2) The CRC circuit is a semiconductor integrated circuit as described in item 1, which calculates the CRC value for each of the R, G, and B values ​​that constitute each pixel of the output image data.

[0108] (Item 3) The CRC circuit is a semiconductor integrated circuit as described in item 2, which left-aligns the R, G, and B values ​​that constitute each pixel of the output image data, generates a bit sequence in which the lower bits are filled with 0, and calculates the CRC value.

[0109] (Item 4) Equipped with an additional communication circuit, The semiconductor integrated circuit according to any one of items 1 to 3, wherein the communication circuit acquires parameters that define the operation of the image processing circuit and acquires the CRC expected value when the semiconductor integrated circuit is started up.

[0110] (Item 5) The test image generation unit is a semiconductor integrated circuit according to any one of items 1 to 4, including a pattern generator.

[0111] (Item 6) The semiconductor integrated circuit is a bridge IC, a repeater IC, or a scaler IC, as described in any of items 1 to 5.

[0112] (Item 7) The semiconductor integrated circuit according to any one of items 1 to 6, wherein the output selector switches from the dummy image data to the output image data during the blank period between frames after the end of the test mode.

[0113] (Item 8) First semiconductor integrated circuit and The second semiconductor integrated circuit, Equipped with, The first semiconductor integrated circuit is An image input interface that receives a digital video signal and outputs input image data, A test image generation unit that generates predetermined test image data, An input selector that selects the input image data in normal mode and the test image data in test mode, An encoder that encodes the image data output by the input selector, A transmitter that transmits a serial signal including the bit sequence output by the encoder to the second semiconductor integrated circuit, Equipped with, The second semiconductor integrated circuit is A receiver that receives the serial signal from the transmitter of the first semiconductor integrated circuit, A decoder that decodes the serial signal received by the receiver into image data, In the aforementioned test mode, a CRC circuit calculates the CRC (Cyclic Redundancy Check) value of the output image data output from the decoder, In test mode, a dummy image generation unit generates dummy image data that is essentially a single color, An output selector that selects the output image data output from the encoder in the normal mode and the dummy image data in the test mode, The image output interface outputs the image data output by the output selector to an image display device, A memory that stores the expected CRC value, which is the CRC value of the output image data, which should be obtained when the receiver correctly receives the serial signal and the decoder correctly decodes the serial signal. In the test mode, a determination unit compares the CRC value calculated by the CRC circuit with the expected CRC value, A system equipped with these features.

[0114] (Item 9) The CRC circuit is the system described in item 8, which calculates the CRC value for each of the R, G, and B values ​​that constitute each pixel of the output image data.

[0115] (Item 10) The CRC circuit generates a bit sequence in which the lower bits are filled with 0 for each of the R, G, and B values ​​that constitute each pixel of the output image data, and calculates the CRC value, as described in item 9.

[0116] (Item 11) The first semiconductor integrated circuit further comprises a communication circuit, The communication circuit, upon startup of the system, acquires parameters that define the operation of the system, and also acquires the CRC expected value. The system according to any one of items 8 to 10, wherein the expected value of the CRC value is supplied to the memory via the encoder and transmitter of the first semiconductor integrated circuit, the receiver and decoder of the second semiconductor integrated circuit.

[0117] (Item 12) The second semiconductor integrated circuit further comprises a communication circuit, The second semiconductor integrated circuit further comprises an encoder and a transmitter, The first semiconductor integrated circuit further comprises a decoder and a receiver, The communication circuit, upon startup of the system, acquires parameters that define the operation of the system, and also acquires the CRC expected value. The system according to any one of items 8 to 10, wherein parameters defining the operation of the system are supplied to the first semiconductor integrated circuit via the encoder and transmitter of the second semiconductor integrated circuit, the receiver and decoder of the first semiconductor integrated circuit.

[0118] (Item 13) The test image generation unit is a system according to any one of items 8 to 12, including a pattern generator. [Explanation of Symbols]

[0119] 100 Systems 110 External circuit 120 Display devices 130 Non-volatile memory 140 controllers 200 Semiconductor Integrated Circuits 210 Image Input Interface 220 Test Image Generation Unit SEL1 Input Selector 230 Image Processing Circuit 240 CRC circuit 250 Dummy Image Generation Unit SEL2 Output Selector 260 Image Output Interface 270 memory 280 Judgment section 290 Communication Circuit IMG1 Input Image Data IMG2 Test Image Data IMG1p, IMG2p Output Image Data IMG3 Dummy image data, 300 Systems 310 External circuit 320 Display Devices 330 Non-volatile memory 340 Controllers 400 1st IC 410 Image Input Interface 420 Test Image Generation Unit SEL1 Input Selector 430 encoders 440 Transmitter 470 memory 490 Communication Circuit 500 2nd IC 510 Receiver 520 Decoder 530 Image Processing Unit 540 CRC circuit 550 Dummy Image Generation Unit SEL2 Output Selector 560 Image Output Interface 570 memory 580 Judgment section 590 Communication Circuit

Claims

1. An image input interface that receives a digital video signal from an external circuit and outputs input image data, A test image generation unit that generates predetermined test image data, An input selector that selects the input image data in normal mode and the test image data in test mode, An image processing circuit that applies predetermined signal processing to the image data output by the input selector, In the aforementioned test mode, a CRC (Cyclic Redundancy Check) circuit calculates the CRC value of the output image data output from the image processing circuit, In test mode, a dummy image generation unit generates dummy image data that is essentially a single color, An output selector that selects the output image data in the normal mode and the dummy image data in the test mode, The image output interface outputs the image data output by the output selector to a display device, A memory that stores the CRC expected value, which is the CRC value of the output image data that should be obtained when the image processing circuit correctly applies the predetermined signal processing to the test image data, In the test mode, a determination unit compares the CRC value calculated by the CRC circuit with the expected CRC value, A semiconductor integrated circuit equipped with the following features.

2. The semiconductor integrated circuit according to claim 1, wherein the CRC circuit calculates the CRC value for each of the R, G, and B values ​​that constitute each pixel of the output image data.

3. The semiconductor integrated circuit according to claim 2, wherein the CRC circuit left-aligns the R, G, and B values ​​that constitute each pixel of the output image data, generates a bit sequence in which the lower bits are filled with 0, and calculates the CRC value.

4. Equipped with an additional communication circuit, The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the communication circuit acquires parameters that define the operation of the image processing circuit and acquires the CRC expected value when the semiconductor integrated circuit is started up.

5. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the test image generation unit includes a pattern generator.

6. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the semiconductor integrated circuit is a bridge IC, a repeater IC, or a scaler IC.

7. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the output selector switches from the dummy image data to the output image data during the blank period between frames after the end of the test mode.

8. First semiconductor integrated circuit and The second semiconductor integrated circuit, Equipped with, The first semiconductor integrated circuit is An image input interface that receives a digital video signal and outputs input image data, A test image generation unit that generates predetermined test image data, An input selector that selects the input image data in normal mode and the test image data in test mode, An encoder that encodes the image data output by the input selector, A transmitter that transmits a serial signal including the bit sequence output by the encoder to the second semiconductor integrated circuit, Equipped with, The second semiconductor integrated circuit is A receiver that receives the serial signal from the transmitter of the first semiconductor integrated circuit, A decoder that decodes the serial signal received by the receiver into image data, In the test mode, a CRC (Cyclic Redundancy Check) circuit calculates the CRC value of the output image data output from the decoder, In test mode, a dummy image generation unit generates dummy image data that is essentially a single color, An output selector that selects the output image data output from the encoder in the normal mode and the dummy image data in the test mode, The image output interface outputs the image data output by the output selector to an image display device, A memory that stores the expected CRC value, which is the CRC value of the output image data, which should be obtained when the receiver correctly receives the serial signal and the decoder correctly decodes the serial signal. In the test mode, a determination unit compares the CRC value calculated by the CRC circuit with the expected CRC value, A system equipped with these features.

9. The system according to claim 8, wherein the CRC circuit calculates the CRC value for each of the R, G, and B values ​​that constitute each pixel of the output image data.

10. The system according to claim 9, wherein the CRC circuit generates a bit sequence in which the lower bits are filled with 0 for each of the R, G, and B values ​​that constitute each pixel of the output image data, and calculates the CRC value.

11. The first semiconductor integrated circuit further comprises a communication circuit, The communication circuit, upon startup of the system, acquires parameters that define the operation of the system, and also acquires the CRC expected value. The system according to any one of claims 8 to 10, wherein the expected value of the CRC value is supplied to the memory via the encoder and transmitter of the first semiconductor integrated circuit, the receiver and decoder of the second semiconductor integrated circuit.

12. The second semiconductor integrated circuit further comprises a communication circuit, The transmitter of the first semiconductor integrated circuit and the receiver of the second semiconductor integrated circuit are capable of bidirectional communication. The communication circuit, upon startup of the system, acquires parameters that define the operation of the system, and also acquires the CRC expected value. The system according to any one of claims 8 to 10, wherein parameters defining the operation of the system are transmitted from the receiver of the second semiconductor integrated circuit to the transmitter of the first semiconductor integrated circuit.

13. The system according to any one of claims 8 to 10, wherein the test image generation unit includes a pattern generator.

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