Indication device

Abstract

To provide a highly reliable display device with low power consumption and suppressed pixel degradation. [Solution] A display device according to one aspect of the present disclosure includes a display panel including a plurality of unit pixels, including a first subpixel that emits light of a first color and a second subpixel that emits light of a second color different from the first color, and a power supply unit that supplies a drive voltage via a first power line connected to the first subpixel and a drive voltage via a second power line connected to the second subpixel, each of the first and second power lines including a grid structure wiring that is electrically isolated from each other, and the power supply unit supplies a first drive voltage via the first power line and a second drive voltage at a different level from the first drive voltage via the second power line.

Description

Technical Field

[0001] This specification relates to a display device.

Background Art

[0002] As information technology develops, the market for display devices, which are the connection medium between users and information, is growing. As a result, the use of display devices such as light-emitting display devices (LEDs), quantum dot display devices (QDDs), and liquid crystal display devices (LCDs) is increasing.

[0003] The aforementioned display device includes a display panel including sub-pixels, a driving unit that outputs a driving signal for driving the display panel, a power supply unit that generates a power supply to be supplied to the display panel or the driving unit, and the like.

[0004] When a driving signal, such as a scan signal or a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixels can display an image by transmitting light or directly emitting light.

[0005] On the other hand, conventionally, a high-potential driving voltage can be supplied from a power source to each sub-pixel that emits red (R), green (G), and blue (B) light via a power line having one grid structure wiring.

Summary of the Invention

Problems to be Solved by the Invention

[0006] One technical problem of the embodiments of this specification is to provide a display device with reduced power consumption.

[0007] One technical problem of the embodiments of this specification is to provide a display device that prevents deterioration of driving transistors provided in each sub-pixel.

[0008] The embodiments described herein address the technical challenge of contributing to ESG (Environmental, Social, and Governance) by improving the reliability and reducing power consumption of display devices. [Means for solving the problem]

[0009] A display device according to one embodiment of this specification includes a display panel having a plurality of unit pixels, including a first subpixel that emits light of a first color and a second subpixel that emits light of a second color different from the first color, and a power supply unit that supplies a drive voltage via a first power line connected to the first subpixel and a drive voltage via a second power line connected to the second subpixel, wherein each of the first and second power lines includes a grid structure wiring that is electrically isolated from each other, and the power supply unit supplies a first drive voltage via the first power line and a second drive voltage at a different level from the first drive voltage via the second power line.

[0010] The grid-structured wiring of the first power line is connected to the first subpixel and may include a plurality of second horizontal wirings arranged horizontally across the display panel and a plurality of second vertical wirings arranged vertically across the display panel.

[0011] Multiple first horizontal and multiple first vertical wires of the first power line are electrically connected to each other, and multiple second horizontal and multiple second vertical wires of the second power line are electrically connected to each other, and each of the multiple first horizontal and multiple first vertical wires is isolated from each of the multiple second horizontal and multiple second vertical wires.

[0012] The first horizontal wiring may be located on a different layer than the first vertical wiring, and the second horizontal wiring may be located on a different layer than the second vertical wiring.

[0013] The first and second vertical traces may be located on the same layer within a unit pixel and may be spaced apart horizontally.

[0014] The first horizontal trace and the second horizontal trace may be located on the same layer within a unit pixel and may be spaced apart vertically.

[0015] The first and second vertical wirings are spaced apart on a first planarization film that covers multiple transistors provided within a unit pixel, and the first and second horizontal wirings may be spaced apart on a second planarization film that covers both the first and second vertical wirings and the first planarization film.

[0016] Each of the multiple unit pixels may have a first contact point where a first horizontal line and a first vertical line intersect each other, and a second contact point where a second horizontal line and a second vertical line intersect each other, both of which are electrically connected.

[0017] The first and second contact points may overlap with the banks that define the emission regions of the first and second subpixels, respectively.

[0018] At the first contact point, the first horizontal and first vertical wirings are electrically connected to each other by passing through the second planarization film, and at the second contact point, the second horizontal and second vertical wirings are electrically connected to each other by passing through the second planarization film.

[0019] The first horizontal trace within each unit pixel is insulated from the second vertical trace at the point where it intersects with the second vertical trace, and the second horizontal trace within each unit pixel may be insulated from the first vertical trace at the point where it intersects with the first vertical trace.

[0020] The first subpixel includes a light-emitting element that emits red light, the second subpixel includes a light-emitting element that emits green light, and the first drive voltage may have a potential at a lower level than the second drive voltage.

[0021] The plurality of unit pixels further includes a third sub-pixel that emits light of a third color different from the first color and the second color. The power supply unit further supplies a third driving voltage having a high-potential driving voltage at a level different from the first driving voltage and the second driving voltage to the light-emitting element of the third sub-pixel via a third power line. The third power line may include a lattice structure wiring electrically separated from the first power line and the second power line.

[0022] The lattice structure wiring of the third power line may be connected to the third sub-pixel and include a plurality of third horizontal wirings arranged in the horizontal direction of the display panel and a plurality of third vertical wirings arranged in the horizontal direction of the display panel.

[0023] The plurality of third horizontal wirings and the plurality of third vertical wirings of the third power line are electrically connected to each other. The plurality of third horizontal wirings may be insulated from the plurality of first and second horizontal wirings, and the plurality of third vertical wirings may be insulated from the plurality of first vertical wirings and the second vertical wirings.

[0024] The third horizontal wiring may be disposed on a layer different from the third vertical wiring within the unit pixel.

[0025] The third horizontal wiring is located on the same layer as the first horizontal wiring and the second horizontal wiring within the unit pixel and may be arranged at a vertical interval.

[0026] The third vertical wiring is located on the same layer as the first vertical wiring and the second vertical wiring within the unit pixel and may be arranged at a horizontal interval.

[0027] The third vertical wiring is located separately from the first vertical wiring and the second vertical wiring on a first planarization film covering a plurality of transistors provided within the unit pixel. The third horizontal wiring may be located separately from the first horizontal wiring and the second horizontal wiring on a second planarization film covering the first vertical wiring, the second vertical wiring, the third vertical wiring, and the first planarization film together.

[0028] [[ID=2,7]] Each of the plurality of unit pixels may further include a third contact point electrically connected to each other at a point where the third horizontal wiring and the third vertical wiring intersect.

[0029] The third contact point may overlap with a bank that defines the light emitting region of the third sub-pixel.

[0030] At the third contact point, the third horizontal wiring and the third vertical wiring may be electrically connected to each other through the second planarization film.

[0031] Within the unit pixel, the third horizontal wiring may be insulated from the first vertical wiring and the second vertical wiring at each point where the third horizontal wiring intersects the first vertical wiring and the second vertical wiring.

[0032] The third sub-pixel includes a light emitting element that emits blue light, and the third driving voltage may have a potential at a level higher than the first driving voltage and the second driving voltage.

Advantages of the Invention

[0033] In the embodiments of the present specification, each of the first power line and the second power line electrically separated from each other is connected to the first sub-pixel and the second sub-pixel that emit lights of different colors from each other, and different first driving voltage and second driving voltage are supplied to each other through the first power line and the second power line, so that the power consumption of the display device can be reduced, and the deterioration of the driving transistors provided in the first sub-pixel and the second sub-pixel can be prevented.

[0034] In the embodiments of the present specification, since each of the first power line and the second power line includes a lattice structure wiring, even if a part of each of the first power line and the second power line is disconnected due to foreign matter or the like, the first driving voltage and the second driving voltage can be supplied to the first sub-pixel and the second sub-pixel, and the display device can be stably driven.

[0035] The examples described herein may reduce the power consumption of display devices and contribute to ESG. [Brief explanation of the drawing]

[0036] [Figure 1] This figure illustrates an example of a display device applicable to the present invention. [Figure 2] This figure illustrates an example of a pixel equivalent circuit applicable to each subpixel in Figure 1. [Figure 3] This figure illustrates a connection structure for a first power line, a second power line, and a third power line having electrically isolated grid-structure wiring according to one embodiment of the present invention. [Figure 4] This diagram illustrates the saturation voltage of the drive transistor electrically connected to the light-emitting element that emits red (R), green (G), or blue (B) light in each subpixel. [Figure 5] Figure 3 illustrates an example of a cross-section of a display device along the CS0-CS0' line, which is a diagonal line with respect to the horizontal and vertical directions. [Figure 6] Figure 3 is a diagram illustrating an example of a cross-section of a display device along the horizontally aligned CS1-CS1' lines. [Figure 7] This figure illustrates an example of a cross-section of a display device along the vertically aligned CS2-CS2' lines in Figure 3. [Modes for carrying out the invention]

[0037] The following describes an embodiment with reference to the drawings.

[0038] The same reference number refers to the same component. Furthermore, some drawings may be exaggerated for the sake of effective explanation of the thickness, proportions, and dimensions of components. The scale of components shown in the drawings is not limited to the scale shown in the drawings, as they may have different scales from reality for the sake of explanation.

[0039] In this specification, when a component (or region, layer, part, etc.) is said to be "on top of," "connected to," or "connected to" another component, it means that it may be directly connected to / connected to the other component, or a third component may be placed between them.

[0040] "and / or" includes both of the one or more combinations defined by the relevant configuration.

[0041] Terms such as "First," "Second," etc., may be used to describe various components, but the components are not limited by these terms. The terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the rights of this embodiment, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes plural expressions unless the context clearly indicates otherwise.

[0042] Terms such as "below," "on the lower side," "up," and "on the upper side" are used to describe the relationships between components shown in the drawing. The terms are relative concepts and are described based on the direction shown in the drawing. For example, unless "right" or "directly" is used, one or more other parts may be positioned between two parts. Spatially relative terms such as "below," "below," "above," and "upper" are used to easily describe the correlation between one element or component and another element or component, as shown in the drawing. Therefore, for example, "below" and "below" relative to the first component may be in the opposite direction to "up" and "upper" relative to the first component.

[0043] Spatially relative terminology should be understood as encompassing not only the directions shown in the drawing, but also the different directions of elements in use or operation. For example, when reversing elements shown in a drawing, an element described as "below" or "beneath" another element may be placed "above" another element. Therefore, the exemplary term "below" can encompass both downward and upward directions.

[0044] Terms such as “includes” or “has” are intended to specify the presence of features, figures, steps, actions, components, parts, or combinations thereof as described in the specification, and should be understood not to preemptively exclude the possibility of the presence or addition of one or more other features or figures, steps, actions, components, parts, or combinations thereof.

[0045] Each feature of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, and various technical interdependencies and drives are possible. Each embodiment can be implemented independently of one another, or in association with one another.

[0046] The display devices described herein are as follows, as seen through the attached drawings and examples.

[0047] Figure 1 is a diagram illustrating an example of a display device applicable to the present invention, and Figure 2 is a diagram illustrating an example of a pixel equivalent circuit applicable to each subpixel of Figure 1.

[0048] As shown in Figure 1, a display device according to one embodiment of the present invention may include a display panel 10, a timing controller 11, a data drive unit 12, a gate drive unit 13, and a power supply unit 20.

[0049] Figure 1 shows an example where the timing controller 11, data drive unit 12, and power supply unit 20 are provided separately. However, unlike Figure 1, the timing controller 11, data drive unit 12, and power supply unit 20 can be integrated, either entirely or partially, within a drive integrated circuit. In Figure 1, the data drive unit 12, gate drive unit 13, and power supply unit 20 may include a panel drive circuit for driving the display panel 10.

[0050] Figure 1 shows an example where the gate drive unit 13 is provided separately from the display panel 10, but the present invention is not limited to this. The gate drive unit 13 can be provided within the non-display area NA of the display panel 10 and can be formed directly on the substrate of the display panel 10 using the GIP (Gate driver In Panel) method.

[0051] The display panel 10 may include a display area AA and a non-display area NA.

[0052] The non-display area (NA) can be an area outside the display area (AA). The non-display area (NA) is also called the edge area or bezel area. The entire or partial non-display area (NA) may be an area visible from the front of the display device, or an area that is curved and not visible from the front of the display device.

[0053] Display area AA may be the area where the image is displayed. Multiple subpixels SP may be arranged in display area AA, and the image can be displayed using multiple subpixels SP. The area where multiple subpixels SP are arranged is display area AA, and the area other than display area AA may be a non-display area NA.

[0054] Multiple subpixels SP arranged in display area AA may emit light of different colors from each other, such as red (R), green (G), or blue (B). However, this is not limited to these. In other embodiments, the multiple subpixels SP may include cyan subpixels, magenta subpixels, and yellow subpixels.

[0055] For example, multiple subpixels SP may include first, second, and third subpixels SP1, SP2, and SP3 that emit light of different colors from each other. The first, second, and third subpixels SP1, SP2, and SP3 may be grouped together for each unit pixel (e.g., UP1, UP2, UP3, and UP4).

[0056] However, the present invention is not limited thereto. The four unit pixels UP1 to UP4 are described as examples, and the present invention is not limited to these unit pixels. Other examples may include more or fewer unit pixels.

[0057] Furthermore, each of the multiple unit pixels may contain multiple subpixels that emit light of different colors, such as two subpixels, three subpixels, or four subpixels. The first to third subpixels SP1 to SP3 described above are illustrative examples only, and the present invention is not limited to these subpixels. Other examples may include more or fewer unit pixels. For example, each of the multiple unit pixels may contain a first subpixel and a second subpixel.

[0058] When defining a group of pixels for color representation as a unit pixel, each unit pixel (e.g., UP1, UP2, UP3, UP4) may include, for example, a first subpixel SP1 emitting red (R) light, a second subpixel SP2 emitting green (G) light, and a third subpixel SP3 emitting blue (B) light. In addition to the first, second, and third subpixels SP1, SP2, and SP3, it may also include a subpixel emitting white (W) light. Therefore, each unit pixel (e.g., UP1, UP2, UP3, UP4) may represent a color that is a mixture of the emitted colors of the first, second, and third subpixels SP1, SP2, and SP3.

[0059] For the sake of explanation, the following example will describe the case where the first subpixel SP1 emits red (R) light, the second subpixel SP2 emits green (G) light, and the third subpixel SP3 emits blue (B) light.

[0060] The non-display area NA may be located in the edge region surrounding the display area AA where the image is displayed. The non-display area NA may contain at least one panel driving circuit for driving multiple subpixels SP.

[0061] The timing controller 11 can supply digital video data (D-DATA) transmitted from a host system (not shown) to the data drive unit 12.

[0062] The timing controller 11 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock signal from the host system, and can generate timing control signals to control the operating timing of the panel drive circuit.

[0063] The timing control signal may include a gate timing control signal GDC for controlling the operation timing of the gate drive unit 13, a data timing control signal DDC for controlling the operation timing of the data drive unit 12, and a power timing control signal PDC for controlling the operation timing of the power supply unit 20.

[0064] The data drive unit 12 is connected to multiple subpixels SP via data lines DL (DL1 to DLm). Based on the digital video data D-DATA input from the timing controller 11, the data drive unit 12 can generate data voltage Vdata, which is an analog signal necessary for driving the multiple subpixels SP, and supply it to the data lines DL.

[0065] The data drive unit 12 samples and latches the digital video data (D-DATA) and data timing control signal (DDC) input from the timing controller 11 to convert them into parallel data, which can then be supplied to multiple subpixels SP via a digital-to-analog converter (DAC) through a data line DL corresponding to the gamma compensation voltage. The analog data voltage Vdata may be analog voltage values ​​with different voltage levels to correspond to the image gradations to be represented by the multiple subpixels SP.

[0066] The data drive unit 12 can output data voltage Vdata to multiple subpixels SP in accordance with a data timing control signal DDC. The data drive unit 12 may consist of multiple source driver integrated circuits. The source driver integrated circuit may include a shift register, a latch, a level shifter, a DAC, and an output buffer. For example, the data drive unit 12 may, but is not limited to, be mounted on the top surface of the display panel 10 in the form of a source driver integrated circuit (IC).

[0067] The gate drive unit 13 generates a scan signal SC based on the gate timing control signal GDC and supplies it to a plurality of subpixels SP via the gate line GL (GL1 to GLn). In some cases, it may also generate light emission control signals EM1 and EM2 based on the gate timing control signal GDC and supply them to a plurality of subpixels SP.

[0068] The power supply unit 20 processes the input power supply according to the power timing control signal PDC to generate a high-potential drive voltage (e.g., EVDD in Figure 2) with a fixed potential, and can supply it to multiple subpixels SP via power lines VDD1, VDD2, and VDD3.

[0069] Furthermore, the power supply unit 20 can process the input power supply in accordance with the power timing control signal PDC to generate a low potential voltage (e.g., EVSS in Figure 2) fixed at a level lower than the high potential drive voltage EVDD, and supply the low potential voltage EVSS to multiple subpixels SP. The high potential drive voltage EVDD and the low potential voltage EVSS can be used as voltages to cause the light-emitting element to emit light. The power supply unit 20 may include one or more circuits that process and supply voltage. As an example, the power supply unit 20 is configured to connect to a power supply.

[0070] On the other hand, the power supply unit 20 provided in the display device of the present invention can supply high-potential drive voltages of different levels to the first, second, and third subpixels SP1, SP2, and SP3, which emit light of different colors from each other, via first, second, and third power lines VDD1, VDD2, and VDD3, which are electrically isolated from each other.

[0071] For this purpose, each of the first, second, and third subpixels SP1, SP2, and SP3 provided in each unit pixel of the display panel 10 is connected to the first, second, and third power lines VDD1, VDD2, and VDD3, respectively. Specifically, in each unit pixel UP1 to UP4, the first subpixel SP1 is connected to the first power line VDD1, the second subpixel SP2 is connected to the second power line VDD2, and the third subpixel SP3 is connected to the third power line VDD3.

[0072] Each of the first, second, and third power lines VDD1, VDD2, and VDD3 may include grid-structured wiring. The grid-structured wiring of the first, second, and third power lines VDD1, VDD2, and VDD3 may be electrically isolated from each other.

[0073] The power supply unit 20 can supply power to the first, second, and third subpixels SP1, SP2, and SP3 (for example, V1, V2, and V3 in Figure 4) via the first, second, and third power lines VDD1, VDD2, and VDD3, respectively, taking into account the saturation voltage of the drive transistor DT provided for each of the first, second, and third subpixels SP1, SP2, and SP3.

[0074] For example, the power supply unit 20 may supply a first drive voltage via a first power line VDD1, a second drive voltage having a different level from the first drive voltage via a second power line VDD2, and a third drive voltage having a different level from the respective levels of the first and second drive voltages via a third power line VDD3.

[0075] As a result, the present invention can prevent the degradation of the drive transistors DT provided in each of the first, second, and third subpixels SP1, SP2, and SP3, and reduce the power consumption of the display device. These will be explained with reference to Figure 3 and subsequent figures.

[0076] At least one of the multiple subpixels SP may include, for example, a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a drive transistor DT, a capacitor Cst, and a light-emitting element OLED, as shown in Figure 2.

[0077] The first electrode of the first switching transistor ST1 is connected to power lines VDD1, VDD2, and VDD3, and a high-potential drive voltage EVDD is applied to it. The second electrode of the first switching transistor ST1 is connected to a drive transistor DT, and a first light emission control signal EM1 may be applied to the gate electrode of the first switching transistor ST1.

[0078] The first switching transistor ST1 can transmit a high-potential drive voltage EVDD applied to the first electrode to the drive transistor DT in accordance with a first light emission control signal EM1 applied to the gate electrode. The first switching transistor ST1 can control the on / off state of the high-potential drive voltage EVDD applied to the corresponding subpixel in response to the first light emission control signal EM1.

[0079] The power lines VDD1, VDD2, and VDD3 connected to the first electrode of the first switching transistor ST1 may be connected to different power lines depending on the color emitted by the corresponding subpixel SP.

[0080] For example, if the pixel equivalent circuit in Figure 2 shows a first subpixel SP1 emitting red R light, the first electrode of the first switching transistor ST1 is connected to the first power supply line VDD1, and a first drive voltage V1 having a first level can be applied as a high-potential drive voltage EVDD.

[0081] Furthermore, if the pixel equivalent circuit in Figure 2 shows a second subpixel SP2 emitting green light G, the first electrode of the first switching transistor ST1 is connected to the second power supply line VDD2, and a second drive voltage V2 having a second level can be applied as a high-potential drive voltage EVDD.

[0082] When the pixel equivalent circuit in Figure 2 shows a third subpixel SP3 emitting blue light B, the first electrode of the first switching transistor ST1 is connected to the third power supply line VDD3, and a third drive voltage V3 having a third level can be applied as a high-potential drive voltage EVDD.

[0083] A high-potential drive voltage EVDD is applied to the first electrode (e.g., drain electrode) of the drive transistor DT from the first switching transistor ST1, and the second electrode (e.g., source electrode) can be electrically connected to the first electrode (e.g., anode electrode) of the light-emitting element OLED via the second switching transistor ST2. The drive transistor DT can control the amount of drive current Ids flowing through the light-emitting element OLED in accordance with the voltage applied to the gate electrode from the first node N1.

[0084] The second switching transistor ST2 is positioned between the drive transistor DT and the light-emitting element OLED. The first electrode of the second switching transistor ST2 is connected to the drive transistor DT, and the second electrode of the second switching transistor ST2 is electrically connected to the light-emitting element OLED. In response to a second light-emitting control signal EM2 applied to the gate electrode of the drive transistor DT, the second switching transistor ST2 can control the on / off state of the drive current Ids applied from the drive transistor DT.

[0085] The first electrode (e.g., drain electrode) of the third switching transistor ST3 is electrically connected to the data line DL, to which the data voltage Vdata is applied, and the second electrode (e.g., source electrode) is electrically connected to the first node N1. The gate electrode of the third switching transistor ST3 is electrically connected to the gate line GL, to which the scan signal SC is applied. In response to the scan signal supplied via the gate line GL, the third switching transistor ST3 transmits the data voltage Vdata supplied via the data line DL to the first node N1.

[0086] Capacitor Cst is electrically connected to the first node N1 and can be charged by the voltage applied to the first node N1.

[0087] In various aspects of this invention, the terms source electrode and drain electrode have been used separately for the sake of explanation. However, the source electrode and drain electrode are interchangeable. A source electrode can be a drain electrode, and a drain electrode can be a source electrode. Furthermore, a source electrode from one aspect of this invention may be a drain electrode from another aspect of this invention, and a drain electrode from one aspect of this invention may be a source electrode from another aspect of this invention.

[0088] The light-emitting OLED can output light corresponding to the drive current Ids. The light-emitting OLED can output light corresponding to one of the following colors: red (R), green (G), blue (B), or white.

[0089] A light-emitting OLED may include an anode electrode, a light-emitting layer disposed on the anode electrode, and a cathode electrode that supplies a common voltage. For example, the light-emitting layer may include one or more of a hole injection layer (HIL), a hole transmission layer (HTL), an electron transmission layer (ETL), and an electron injection layer (EIL), but is not limited to these.

[0090] The light-emitting layer may be configured to emit light of the same color for each pixel, such as white light, or it may be configured to emit light of different colors for each subpixel SP, such as red (R), green (G), or blue (B) light. A low potential voltage (EVSS) may be supplied to the cathode electrodes. For example, the cathode electrodes of the first, second, and third subpixels SP1, SP2, and SP3 may be supplied with a low potential voltage EVSS having the same potential.

[0091] The light-emitting OLED may be a front-emitting diode or a back-emitting diode.

[0092] Although not shown in Figure 2, the subpixel SP may further include a compensation circuit (not shown) for compensating for the threshold voltage of the drive transistor DT, etc. The compensation circuit may include at least one or more transistors connected to the drive transistor DT and may be provided within the subpixel SP.

[0093] The compensation circuit can consist of various structures depending on the configuration, such as 3T1C, which includes three transistors and one capacitor Cst within the subpixel SP, or 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, which include four transistors and two capacitor Cst.

[0094] In Figure 2, the driving transistor DT is shown as an example where it is electrically connected to the light-emitting element OLED via the second switching transistor ST2, but the present invention is not limited to this. For example, unlike in Figure 2, the second switching transistor ST2 may be omitted in some cases, and the driving transistor DT may be electrically connected to the light-emitting element OLED without the need for other transistors.

[0095] Although Figure 2 shows an example where the first switching transistor ST1 is included, the present invention is not limited to this. For example, the drive transistor DT can be electrically connected to a power supply unit 20 that generates a high-level drive voltage EVDD without the need for other transistors.

[0096] On the other hand, each of the first, second, and third power lines VDD1, VDD2, and VDD3 described in Figures 1 and 2 may include grid-structure wiring that is electrically isolated from each other in order to provide a stable supply of the high-potential drive voltage EVDD.

[0097] Figure 3 is a diagram illustrating the connection structure of first, second, and third power lines having electrically isolated grid-structure wiring according to one embodiment of the present invention.

[0098] Figure 3 is a plan view of the K region in Figure 1, magnified. As shown in Figure 3, the display panel 10 may include multiple unit pixels, including the first, second, third, and fourth unit pixels UP1, UP2, UP3, and UP4.

[0099] As shown in Figure 3, the first, second, third, and fourth unit pixels UP1, UP2, UP3, and UP4 may comprise the first, second, and third subpixels SP1, SP2, and SP3. In the following explanation, we will assume that the second, third, and fourth unit pixels also comprise the first, second, and third subpixels SP1, SP2, and SP3 in the same arrangement as the first unit pixel UP1.

[0100] For example, the first subpixel SP1 to the third subpixel SP3 may include a light-emitting OLED that emits red (R), green (G), or blue (B) light. In Figure 3, for example, the first subpixel SP1 may include a light-emitting OLED that emits red (R), the second subpixel SP2 may include a light-emitting OLED that emits green (G), and the third subpixel SP3 may include a light-emitting OLED that emits blue (B).

[0101] The power supply unit 20 can supply first, second, and third drive voltages (e.g., V1, V2, and V3 in Figure 4) having different potential levels to each of the first, second, and third subpixels SP1, SP2, and SP3 provided in the first to fourth unit pixels UP1 to UP4 in Figure 3, respectively, via the first, second, and third power lines VDD1, VDD2, and VDD3, respectively, as high-potential drive voltages EVDD.

[0102] For example, the power supply unit 20 may supply a first level first drive voltage V1 to the first subpixel SP1 of each unit pixel UP1, UP2, UP3, UP4 via the first power line VDD1, supply a second level second drive voltage V2 to the second subpixel SP2 via the second power line VDD2, and supply a third level third drive voltage V3 to the third subpixel SP3 via the third power line VDD3.

[0103] Here, the voltage levels of the first, second, and third drive voltages V1, V2, and V3 can be determined by considering the saturation voltage of the drive transistor DT provided in each of the first, second, and third subpixels SP1, SP2, and SP3. This will be explained later with reference to Figure 4. For example, the power supply unit 20 can supply different levels of the first to third drive voltages V1 to V3 to each of the first to third subpixels SP1 to SP3 via the first to third power lines VDD1 to VDD3.

[0104] The first, second, and third power lines VDD1, VDD2, and VDD3 may each have a grid structure wiring that is electrically isolated from each other, as shown in Figure 3.

[0105] The grid structure wiring of the first power line VDD1 may include a plurality of first horizontal wires Lx1 and a plurality of first vertical wires Ly1 connected to the first subpixel SP1. The grid structure wiring of the second power line VDD2 may include a plurality of second horizontal wires Lx2 and a plurality of second vertical wires Ly2 connected to the second subpixel SP2. The grid structure wiring of the third power line VDD3 may include a plurality of third horizontal wires Lx3 and a plurality of third vertical wires Ly3 connected to the third subpixel SP3. For example, each of the first to third horizontal wires Lx1 to Lx3 may intersect with each of the first to third vertical wires Ly1 to Ly3.

[0106] Here, the first, second, and third horizontal wirings Lx1, Lx2, and Lx3 may be aligned in the horizontal x direction of the display panel 10, and the first, second, and third vertical wirings Ly1, Ly2, and Ly3 may be aligned in the vertical y direction of the display panel 10. Therefore, in each of the first to fourth unit pixels UP1 to UP4, the first, second, and third horizontal wirings Lx1, Lx2, and Lx3 may intersect with the first, second, and third vertical wirings Ly1, Ly2, and Ly3.

[0107] In each of the first to fourth unit pixels UP1 to UP4, the first, second, and third vertical wirings Ly1, Ly2, and Ly3 may be located on the same layer and may be separated in the horizontal direction x.

[0108] In each of the first to fourth unit pixels UP1 to UP4, the first, second, and third horizontal wirings Lx1, Lx2, and Lx3 may be located on the same layer and may be separated in the vertical direction (y).

[0109] In each of the first to fourth unit pixels UP1 to UP4, multiple first horizontal wires Lx1 and multiple first vertical wires Ly1 of the first power line VDD1 are electrically connected to each other, multiple second horizontal wires Lx2 and multiple second vertical wires Ly2 of the second power line VDD2 are electrically connected to each other, and multiple three horizontal wires and multiple third vertical wires Ly3 of the third power line VDD3 can be electrically connected to each other.

[0110] For example, in each of the first to fourth unit pixels UP1 to UP4, in the first subpixel SP1, multiple first horizontal wires Lx1 and multiple first vertical wires Ly1 of the first power line VDD1 are electrically connected to each other; in the second subpixel SP2, multiple second horizontal wires Lx2 and multiple second vertical wires Ly2 of the second power line VDD2 are electrically connected to each other; and in SP3, multiple third horizontal wires Lx3 and multiple third vertical wires Ly3 of the third power line VDD3 are electrically connected.

[0111] For example, each of the first to fourth unit pixels UP1 to UP4 may include a first contact point CP1 that is electrically connected to each other at the point where the first horizontal wiring Lx1 and the first vertical wiring Ly1 intersect, a second contact point CP2 that is electrically connected to each other at the point where the second horizontal wiring Lx2 and the second vertical wiring Ly2 intersect, and a third contact point CP3 that is electrically connected to each other at the point where the third horizontal wiring Lx3 and the third vertical wiring Ly3 intersect.

[0112] At the first contact point CP1, the first horizontal wiring Lx1 and the first vertical wiring Ly1 may be electrically connected in the thickness direction z of the display panel 10; at the second contact point CP2, the second horizontal wiring Lx2 and the second vertical wiring Ly2 may be electrically connected in the thickness direction z of the display panel 10; and at the third contact point CP3, the third horizontal wiring Lx3 and the third vertical wiring Ly3 may be electrically connected in the thickness direction z of the display panel 10. These will be described in detail later with reference to Figures 5 to 7.

[0113] The first, second, and third contact points CP1, CP2, and CP3 are located one per unit pixel, but their positions can be spaced apart without overlapping. For example, the positions of the first to third contact points CP1 to CP3 can be spaced apart so as not to overlap in the horizontal and vertical directions, but are not limited to this.

[0114] For example, in each unit pixel, the first contact point CP1 may be located superimposed on the first subpixel SP1, the second contact point CP2 may be located overlapping with the second subpixel SP2, and the third contact point CP3 may be located overlapping with the third subpixel SP3.

[0115] Multiple first horizontal wirings Lx1 may be insulated from the second and third vertical wirings Ly2 and Ly3, respectively; multiple second horizontal wirings Lx2 may be insulated from the first and third vertical wirings Ly1 and Ly3, respectively; and multiple third horizontal wirings Lx3 may be insulated from the first and second vertical wirings Ly1 and Ly2.

[0116] For example, multiple first horizontal wirings Lx1 may be insulated from second and third vertical wirings Ly2 and Ly3 in the thickness direction z, and multiple second horizontal wirings Lx2 may be insulated from first and third vertical wirings Ly1 and Ly3 in the thickness direction z. Multiple third horizontal wirings Lx3 may, but are not limited to, be insulated from first and second vertical wirings Ly1 and Ly2 in the thickness direction z.

[0117] For example, the first horizontal wiring Lx1 may be insulated from the second and third vertical wirings Ly2 and Ly3 at the points where it intersects with them, separated in the thickness direction z; the second horizontal wiring Lx2 may be insulated from the first and third vertical wirings Ly1 and Ly3 at the points where it intersects with them, separated in the thickness direction z; and the third horizontal wiring Lx3 may be insulated from the first and second vertical wirings Ly1 and Ly2 at the points where it intersects with them, separated in the thickness direction z. This will be explained in detail later with reference to Figures 5 to 7.

[0118] Thus, in one embodiment of the present invention, each of the first, second, and third power lines VDD1, VDD2, and VDD3 includes a grid structure wiring, and each of the grid structure wirings of the first, second, and third power lines VDD1, VDD2, and VDD3 can be electrically isolated from one another.

[0119] For example, a grid-structured wiring including the first to third power lines VDD1 to VDD3 can be electrically isolated from other grid-structured wiring including the first to third power lines VDD1 to VDD3.

[0120] For example, the grid structure wiring of the first power line VDD1 may be electrically isolated from the grid structure wiring of the second power line VDD2 and the grid structure wiring of the third power line VDD3. The grid structure wiring of the second power line VDD2 can be electrically isolated from the grid structure wiring of the first power line VDD1 and the grid structure wiring of the third power line VDD3. The grid structure wiring of the third power line VDD3 can be electrically isolated from the grid structure wiring of the first power line VDD1 and the grid structure wiring of the second power line VDD2.

[0121] A power supply unit 20 according to one embodiment of the present invention can supply first, second, and third drive voltages V1, V2, and V3, which have different potential levels from each other, as a high-potential drive voltage EVDD via first, second, and third power lines VDD1, VDD2, and VDD3, which have electrically isolated grid structure wiring from each other.

[0122] As a result, the present invention can prevent the degradation of the drive transistors DT provided in each of the first, second, and third subpixels SP1, SP2, and SP3, and reduce the power consumption of the display device.

[0123] Figure 4 illustrates the saturation voltage of the drive transistors electrically connected to the light-emitting elements that emit red (R), green (G), or blue (B) light in each subpixel.

[0124] Figure 4(a) shows a comparative example, and Figure 4(b) shows an embodiment of the present invention. In Figures 4(a) and 4(b), the x-axis represents the drain-source voltage Vds of the drive transistor DT provided in the subpixel emitting red (R), green (G), or blue (B) light, and the y-axis represents the drive current Ids of the drive transistor DT.

[0125] In Figures 4(a) and 4(b), R, G, and B are characteristic graphs of Vds and Ids for each drive transistor DT electrically connected to each light-emitting OLED in subpixels emitting red (R), green (G), or blue (B) light, while VSR, VSG, and VSB represent the saturation voltages of the respective drive transistors electrically connected to the light-emitting OLEDs emitting red (R), green (G), or blue (B) light.

[0126] The saturation voltages VSR, VSG, and VSB of the drive transistor DT may vary depending on the brightness, color temperature, width and length of each light-emitting element (OLED) connected to the drive transistor DT, the target current value, and other factors.

[0127] For example, the saturation voltage VSR of the drive transistor DT electrically connected to the red (R) light-emitting element OLED is the lowest, the saturation voltage VSB of the drive transistor DT electrically connected to the blue (B) light-emitting element OLED is the highest, and the saturation voltage VSG of the drive transistor DT electrically connected to the green (G) light-emitting element OLED may have a value between VSR and VSB.

[0128] Thus, when each subpixel SP, which emits different colors under conditions of different saturation voltages, is connected to a single power line, each subpixel SP may be supplied with a high-potential drive voltage EVDD having the same voltage level V0 from the power supply unit 20, as shown in Figure 4(a). For example, each subpixel SP emitting different colors may be supplied with a high-potential drive voltage EVDD with a V0 voltage level higher than the highest saturation voltage VSB, relative to the highest saturation voltage VSB, for stable operation of the display device.

[0129] In such a case, each subpixel SP in each unit pixel will be supplied with a high potential drive voltage EVDD at a V0 voltage level set relative to the highest saturation voltage VSB, which may increase the power consumption of the display device.

[0130] Furthermore, in the case of a drive transistor DT electrically connected to a red (R) or green (G) light-emitting element OLED, the difference between the high-potential drive voltage EVDD at the V0 voltage level and the respective saturation voltages (VSR or VSG) can cause rapid degradation of the drive transistor DT, which can lead to operational errors in the display device.

[0131] However, in the present invention, as explained earlier in Figures 1 to 3, with the first, second, and third power lines VDD1, VDD2, and VDD3, which are electrically isolated from each other, connected to the first, second, and third subpixels SP1, SP2, and SP3, which emit different colors from each other, the power supply unit 20 supplies the first, second, and third drive voltages V1, V2, and V3, which have different voltage levels from each other, as a high-potential drive voltage EVDD via the first, second, and third power lines VDD1, VDD2, and VDD3, as shown in Figure 4(b). This reduces the power consumption of the display device and improves the degradation of the drive transistors DT provided in each subpixel SP.

[0132] For example, as shown in Figure 4(b), the first drive voltage V1 may have a potential at a lower level than the second drive voltage V2, and the third drive voltage V3 may have a potential at a higher level than the first and second drive voltages.

[0133] The first, second, and third drive voltages V1, V2, and V3 can be set relative to the saturation voltages VSR, VSG, and VSB of the drive transistors DT provided in the first, second, and third subpixels SP1, SP2, and SP3, respectively. Specifically, the first drive voltage V1 can be set relative to the saturation voltage VSR of the drive transistor DT of the first subpixel SP1, the second drive voltage V2 can be set relative to the saturation voltage VSG of the drive transistor DT of the second subpixel SP2, and the third drive voltage V3 can be set relative to the saturation voltage VSB of the drive transistor DT of the third subpixel SP3.

[0134] For example, the first drive voltage V1 may be set relative to the saturation voltage VSR of the drive transistor DT for the first subpixel SP1 that emits red (R) light, the second drive voltage V2 may be set relative to the saturation voltage VSG of the drive transistor DT for the second subpixel SP2 that emits green (G) light, and the third drive voltage V3 may be set relative to the saturation voltage VSB of DT.

[0135] For example, as shown in Figure 4(b), the first drive voltage V1 may be set to be greater than or equal to the saturation voltage VSR of the first subpixel SP1 that emits red (R) light, and less than the saturation voltage VSG of the second subpixel SP2 that emits green (G) light; the second drive voltage V2 may be set to be greater than or equal to the saturation voltage VSG of the second subpixel SP2 that emits green (G) light, and less than the saturation voltage VSB of the third subpixel SP3 that emits blue (B) light; and the third drive voltage V3 may be set to be greater than or equal to the saturation voltage VSB of the third subpixel SP3 that emits blue (B) light.

[0136] As a result, the present invention can reduce the power consumption of the display device, minimize the voltage level difference between the saturation voltage and the high-potential drive voltage of the drive transistor DT provided in each subpixel SP, and improve the degradation of the drive transistor.

[0137] Furthermore, as described above in Figure 3, the present invention may have a grid structure wiring in which the first, second, and third power lines VDD1, VDD2, and VDD3 are electrically isolated from each other. As a result, even if a part of the first, second, and third power lines VDD1, VDD2, and VDD3 is broken due to foreign matter or the like, the drive voltage will not be interrupted and will be supplied to subpixels emitting the same color through a bypass path, thereby maintaining the driving stability of the display device.

[0138] In the following section, using the cross-sectional structure of a display device as an example, we will explain the specific interlayer structure of the first, second, and third power lines VDD1, VDD2, and VDD3 shown in Figure 3.

[0139] Figure 5 is a diagram illustrating an example of a cross-section of a display device along the CS0-CS0' line, which is diagonal to the horizontal x and vertical y directions in Figure 3. Figure 6 is a diagram illustrating an example of a cross-section of a display device along the CS1-CS1' line, which is parallel to the horizontal x direction in Figure 3. Figure 7 is a diagram illustrating an example of a cross-section of a display device along the CS2-CS2' line, which is parallel to the vertical y direction in Figure 3.

[0140] Figures 5 to 7 illustrate the cross-section of the fourth unit pixel UP4 in Figure 3, but the first, second, and third unit pixels UP1, UP2, and UP3 in Figure 3 may also have similar cross-sections as shown in Figures 5 to 7.

[0141] The transistors ST1, DT, and ST2 shown in Figures 5 to 7 are examples of transistors located on the path from the power supply line VDD1, VDD2, or VDD3 to the light-emitting element OLED in the pixel equivalent circuit shown in Figure 2.

[0142] The present invention is not limited to the connection structure of the multiple transistors ST1, DT, and ST2 shown in Figures 5 to 7, and the connection structure of the multiple transistors ST1, DT, and ST2 shown in Figures 5 to 7 can be changed. The following explanation will use the connection structure of the multiple transistors shown in Figures 5 to 7 as an example.

[0143] Furthermore, Figures 5 to 7 illustrate the case where the first subpixel SP1 emits red light (R), the second subpixel SP2 emits green light (G), and the third subpixel SP3 emits blue light (B).

[0144] A display device according to one embodiment of the present invention may include, as shown in Figures 5 to 7, a substrate 100, a first buffer layer 110, a first gate insulating film 120, a first interlayer insulating film 130, a second buffer layer 140, a second gate insulating film 150, a second interlayer insulating film 200, a planarization film 300, a bank 500, a light-emitting element OLED, a first switching transistor ST1, a second switching transistor ST2, a drive transistor DT, a first power supply line VDD1, a second power supply line VDD2, and a third power supply line VDD3.

[0145] In Figures 5 to 7, at least one of the first and second switching transistors ST1 and ST2 can be omitted. However, in the following explanation, we will use the case where the first and second switching transistors ST1 and ST2 are provided, as shown in Figures 5 to 7, as an example.

[0146] The substrate 100 is formed from a flexible plastic material and may have flexible properties, and may include a thin, flexible glass material. The substrate 100 may be placed in the display area AA and the non-display area NA of the display panel 10.

[0147] For example, the substrate 100 can be made from any of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin triacetylcellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, or polystyrene (PS), but this is merely an example and not necessarily limited to these.

[0148] The substrate 100 may have a multilayer structure including an insulating material. For example, the substrate 100 may include a polymer material such as polyimide (PI) and an insulating material.

[0149] The first buffer layer 110 may be placed on the display area AA and the non-display area NA on the substrate 100. The first buffer layer 110 is placed on the substrate 100 and can protect structures on the substrate 100 that are vulnerable to moisture permeation from external moisture and flatten the surface of the substrate 100.

[0150] The first buffer layer 110 may contain an insulating material, and may contain inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx), and may have a multilayer structure containing the same material or different materials.

[0151] For example, the first buffer layer 110 may be formed of a single-layer or multi-layer inorganic film. For example, a single-layer inorganic film may be a silicon oxide (SiO) film or a silicon nitride (SiN) film, and a multi-layer inorganic film may consist of one or more silicon oxide (SiO) films, one or more silicon nitride (SiN) films, and one or more amorphous silicon films. However, the disclosure is not limited thereto.

[0152] For example, the first buffer layer 110 may be formed by stacking a multi-buffer layer 110a and an active buffer layer 110b, each containing different insulating materials. The first metal layer BSM of the first switching transistor ST1 is placed between the multi-buffer layer 110a and the active buffer layer 110b. The first active layer ACT1 of the first switching transistor ST1 is placed on the active buffer layer 110b.

[0153] The first gate insulating film 120 may cover the first active layer ACT1 of the first switching transistor ST1 and be disposed on the first buffer layer 110. The first gate insulating film 120 may insulate the first gate electrode G1 of the first switching transistor ST1 from the first active layer ACT1. The first gate insulating film 120 may contain at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy). The first gate electrode G1 of the first switching transistor ST1 and the second metal layer BG2 of the second switching transistor ST2 may be disposed on the first gate insulating film 120.

[0154] The first interlayer insulating film 130 may be placed on the first gate insulating film 120, covering the first gate electrode G1 and the second metal layer BG2. The first interlayer insulating film 130 may completely cover the display area AA of the substrate 100 and may contain insulating material.

[0155] The first interlayer insulating film 130 may contain one or more inorganic films selected from silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy).

[0156] The second buffer layer 140 may be placed on top of the first interlayer insulating film 130. The second buffer layer 140 may contain an insulating material. For example, the second buffer layer 140 may contain an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0157] The second buffer layer 140 may have a multilayer structure. For example, the second buffer layer 140 may include a nitride buffer layer 140a and an oxide buffer layer 140b, each containing different materials. However, the configuration of the second buffer layer 140 is not limited thereto. For example, the nitride buffer layer 140a may be placed on the first interlayer insulating film 130, and the oxide buffer layer 140b may be placed on the nitride buffer layer 140a. The nitride buffer layer 140a may contain silicon nitride (SiNx), and the oxide buffer layer 140b may contain silicon oxide (SiOx). The hydrogen concentration of the nitride buffer layer 140a may be higher than that of the oxide buffer layer.

[0158] A third metal layer BG3 of the drive transistor DT may be placed between the nitride buffer layer 140a and the oxide buffer layer 140b. For example, the oxide buffer layer 140b may be positioned to cover the third metal layer BG3 and the nitride buffer layer 140a of the drive transistor DT.

[0159] The second active layer ACT2 of the second switching transistor ST2 and the third active layer ACT3 of the drive transistor DT may be arranged on the oxide buffer layer 140b.

[0160] The second gate insulating film 150 is placed on the second buffer layer 140, covering the second active layer ACT2, and the second gate electrode G2 of the second switching transistor ST2 and the third gate electrode G3 of the drive transistor DT may be placed on top of the second gate insulating film 150.

[0161] The second gate insulating film 150 can insulate the second gate electrode G2 of the second switching transistor ST2 from the second active layer ACT2, and the third gate electrode G3 of the drive transistor DT from the third active layer ACT3.

[0162] The second gate insulating film 150 may contain at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy). For example, silicon oxide (SiOx) may contain silicon dioxide (SiO2).

[0163] The second interlayer insulating film 200 may be placed on the second gate insulating film 150, covering the second gate electrode G2 of the second switching transistor ST2 and the third gate electrode G3 of the drive transistor DT. The second interlayer insulating film 200 may include an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxide nitride (SiOxNy).

[0164] The first source electrode SD1a and first drain electrode SD1b of the first switching transistor ST1, the second source electrode SD2a and second drain electrode SD2b of the second switching transistor ST2, and the third source electrode SD3a and third drain electrode SD3b of the drive transistor DT may be arranged on top of the second interlayer insulating film 200.

[0165] The first source electrode SD1a and the first drain electrode SD1b of the first switching transistor ST1 can penetrate the first gate insulating film 120, the first interlayer insulating film 130, the second buffer layer 140, the second gate insulating film 150, and the second interlayer insulating film 200 to contact the first active layer ACT1.

[0166] The second source electrode SD2a and second drain electrode SD2b of the second switching transistor ST2, and the third source electrode SD3a and third drain electrode SD3b of the drive transistor DT, can each penetrate the second gate insulating film 150 and the second interlayer insulating film 200 to contact the second active layer ACT2 and the third active layer ACT3.

[0167] For example, the second source electrode SD2a and the second drain electrode SD2b of the second switching transistor ST2 may be placed on the second interlayer insulating film 200, and the second source electrode SD2a and the second drain electrode SD2b may be in contact with the second gate insulating film 150 and the second interlayer insulating film 200.

[0168] For example, the third source electrode SD3a and the third drain electrode SD3b of the drive transistor DT may be placed on the second interlayer insulating film 200. The third source electrode SD3a and the third drain electrode SD3b may penetrate the second gate insulating film 150 and the second interlayer insulating film 200 to contact the third active layer ACT3.

[0169] The planarization film 300 contains an insulating material and can be placed on the second interlayer insulating film 200 while covering the first source electrode SD1a and first drain electrode SD1b of the first switching transistor ST1, the second source electrode SD2a and second drain electrode SD2b of the second switching transistor ST2, and the third source electrode SD3a and third drain electrode SD3b of the drive transistor DT.

[0170] The planarization film 300 can eliminate the steps caused by multiple transistors ST1, ST2, and DT arranged within each subpixel SP1, SP2, and SP3. The upper surface of the planarization film 300 has a flat surface and may contain a material with high fluidity. For example, the planarization film 300 may contain an organic insulating material.

[0171] The planarization film 300 has a multilayer structure in which multiple layers are stacked, for example, the planarization film 300 may include a first planarization film 310, a second planarization film 320, and a third planarization film 330 that are stacked sequentially. However, the present invention is not limited thereto. The planarization film 300 may include more or fewer layers.

[0172] The planarized film 300 may be formed from one or more materials selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, and benzocyclobutene, but the present invention is not limited thereto.

[0173] The first planarization film 310 can eliminate steps caused by the drive circuit, such as the first and second switching transistors ST1 and ST2 and the drive transistor DT. The upper surfaces of the first planarization film 310, the second planarization film 320, and the third planarization film 330 may have a flat surface.

[0174] For this purpose, the first, second, and third planarization films 310, 320, and 330 may contain materials with high fluidity. For example, the first, second, and third planarization films 310, 320, and 330 may contain organic insulating materials, and the first, second, and third planarization films 310, 320, and 330 may contain the same or different materials.

[0175] For example, the first planarization film 310 may be placed on the second interlayer insulating film 200, the second planarization film 320 may be placed on the first planarization film 310, and the third planarization film 330 may be placed on the second planarization film 320.

[0176] Between the first planarization film 310 and the second planarization film 320, the first vertical wiring Ly1 of the first power supply line VDD1, the second vertical wiring Ly2 of the second power supply line VDD2, the third vertical wiring Ly3 of the third power supply line VDD3, and the first, second, and third intermediate electrodes CE1, CE2, and CE3 may be arranged.

[0177] The first, second, and third vertical wirings Ly1, Ly2, Ly3 and the first, second, and third intermediate electrodes CE1, CE2, CE3 may contain conductive materials, such as metals like aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and molybdenum (Mo) and tungsten (W). The first, second, and third vertical wirings Ly1, Ly2, Ly3 and the first, second, and third intermediate electrodes CE1, CE2, CE3 may contain the same conductive material.

[0178] The first, second, and third intermediate electrodes CE1, CE2, and CE3 are connected to the second drain electrode SD2b of the second switching transistor ST2 by penetrating the first planarization film 310 in each of the first, second, and third subpixels SP1, SP2, and SP3, and can be connected to the first electrode E1 (e.g., anode electrode) of the light-emitting element OLED via wiring CL that penetrates the second and third planarization films 320 and 330.

[0179] Each of the first, second, and third vertical wirings Ly1, Ly2, and Ly3 is spaced apart from each other in the horizontal direction x and may extend parallel to the vertical direction y. The first, second, and third vertical wirings Ly1, Ly2, and Ly3 penetrate the first planarization film 310 in each of the first, second, and third subpixels SP1, SP2, and SP3 and are connected to the first source electrode SD1a of the first switching transistor ST1.

[0180] Between the second planarization film 320 and the third planarization film 330, the first horizontal wiring Lx1 of the first power supply line VDD1, the second horizontal wiring Lx2 of the second power supply line VDD2, and the third horizontal wiring Lx3 of the third power supply line VDD3 may be arranged.

[0181] Each of the first, second, and third horizontal wirings Lx1, Lx2, and Lx3 may be spaced apart from each other in the vertical direction y and extend parallel to the horizontal direction x. The first, second, and third horizontal wirings Lx1, Lx2, and Lx3 may be electrically connected to the first, second, and third vertical wirings Ly1, Ly2, and Ly3 by penetrating the second planarization film 320 in each of the first, second, and third subpixels SP1, SP2, and SP3.

[0182] For example, the first horizontal wiring Lx1 and the first vertical wiring Ly1 may be electrically connected, the second horizontal wiring Lx2 and the second vertical wiring Ly2 may be electrically connected to each other, and the third horizontal wiring Lx3 and the third vertical wiring Ly3 may be electrically connected.

[0183] The first, second, and third vertical wirings Ly1, Ly2, and Ly3 may contain conductive materials, such as metals like aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W).

[0184] The first, second, and third vertical wirings Ly1, Ly2, and Ly3 may contain the same conductive material as each other, or they may contain different conductive materials than each other.

[0185] Bank 500 is positioned on the third planarization film 330 and can define the light-emitting regions EA1, EA2, and EA3 of the first, second, and third subpixels SP1, SP2, and SP3, respectively. Between the light-emitting regions EA1, EA2, and EA3, a bank region BA overlapping with bank 500 may be positioned.

[0186] For example, as shown in Figure 5, the bank 500 may define the first light-emitting region EA1 of the first subpixel SP1, the second light-emitting region EA2 of the second subpixel SP2, and the third light-emitting region EA3 of the third subpixel SP3. That is, the bank 500 may distinguish between the first, second, and third light-emitting regions EA1, EA2, and EA3.

[0187] Figure 7 illustrates that one subpixel (e.g., SP1) includes multiple light-emitting regions EA1a, EA1b, and EA1c separated by bank 500; however, this is illustrative and the invention is not necessarily limited thereto. For example, unlike in Figure 7, the first subpixel SP1 may include one light-emitting region not distinguished by bank 500.

[0188] Bank 500 may contain an insulating material, such as an organic insulating material. Bank 500 may contain a different material from the planarization film 300. Bank 500 may cover the edge of the first electrode E1 included in the light-emitting element OLED. The light-emitting layer EL and the second electrode E2 of the light-emitting element OLED may be laminated on a portion of the first electrode E1 exposed by bank 500.

[0189] For example, Bank 500 may include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin. Alternatively, Bank 500 may include inorganic insulating materials such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. Furthermore, Bank 500 may include a black dye to absorb light incident from the outside.

[0190] Each of the first, second, and third light-emitting regions EA1, EA2, and EA3 is equipped with a light-emitting OLED that emits a different color from each other, and the light-emitting OLED may include a first electrode E1, a light-emitting layer EL, and a second electrode E2.

[0191] The first electrode E1 may function as an anode electrode and may contain a conductive material. The first electrode E1 may have high reflectivity. For example, the first electrode E1 may contain metals such as aluminum (Al) and silver (Ag). The first electrode E1 may have a multilayer structure. For example, the first electrode E1 may have a structure in which a reflective electrode made of metal is placed between transparent electrodes made of transparent conductive materials such as ITO or IZO.

[0192] The light-emitting layer (EL) can generate light with a brightness corresponding to the voltage difference between the first electrode E1 and the second electrode E2. For example, the light-emitting layer (EL) may include an Emission Material Layer (EML) containing a light-emitting material. The light-emitting material may include organic materials, inorganic materials, or hybrid materials. For example, the light-emitting layer (EL) may include a light-emitting material layer made of an organic material.

[0193] The light-emitting layer EL may include at least one of a first light-emitting common layer (not shown) located between it and the first electrode E1, and a second light-emitting common layer (not shown) located between it and the second electrode E2. The first light-emitting common layer (not shown) and the second light-emitting common layer (not shown) may each include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0194] The light-emitting layer EL can emit light of one of three colors: red (R), green (G), or blue (B). For example, as shown in Figure 5, the light-emitting layer where the first subpixel SP1 is located may emit red (R) light, the light-emitting layer where the second subpixel SP2 is located may emit green (G) light, and the light-emitting layer where the third subpixel SP3 is located may emit blue (B) light.

[0195] The second electrode E2 functions, for example, as a cathode electrode and may contain a conductive material. The second electrode E2 may contain a different material from the first electrode E1. For example, the second electrode E2 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. The second electrode E2 may have a higher transmittance than the first electrode E1. Therefore, in a display device according to one embodiment of the present invention, light generated by the light-emitting layer EL can be emitted through the second electrode E2.

[0196] For example, the first electrode E1 and the second electrode E2 may each contain metallic materials such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr, and alloys thereof. Alternatively, the first electrode E1 and the second electrode E2 may each contain, but are not limited to, transparent conductive materials such as ITO, indium tin oxide or IZO, or indium zinc oxide.

[0197] The first switching transistor ST1 includes a first metal layer BSM, a first gate electrode G1, a first active layer ACT1, a first source electrode SD1a, and a first drain electrode SD1b, wherein the first active layer ACT1 may include, for example, low-temperature polysilicon (LTPS). The first metal layer BSM may have a light-shielding function that blocks external light flowing into the first active layer ACT1. Although not shown, the first metal layer BSM may, in some cases, be electrically connected to the first gate electrode G1, the first source electrode, the first drain electrode SD1b, or a constant voltage source.

[0198] The second switching transistor ST2 includes a second metal layer BG2, a second gate electrode G2, a second active layer ACT2, a second source electrode SD2a, and a second drain electrode SD2b, where the second active layer ACT2 may include, for example, an oxide semiconductor. The second metal layer BG2 may have a light-shielding function that blocks external light flowing into the second active layer ACT2. Although not shown, in some cases the second metal layer BG2 may be electrically connected to the first gate electrode G1 and function as a bottom gate electrode.

[0199] The drive transistor DT includes a third metal layer BG3, a third gate electrode G3, a third active layer ACT3, a third source electrode SD3a, and a third drain electrode SD3b, where the third active layer ACT3 may include, for example, an oxide semiconductor. The third metal layer BG3 may have a light-shielding function that blocks external light flowing into the third active layer ACT3. Although not shown, the third metal layer BG3 may, in some cases, be electrically connected to either the third source electrode or the third drain electrode SD3b.

[0200] On the other hand, according to an embodiment of the present invention, as described above in Figure 3, the first power supply line VDD1 may include a plurality of first horizontal wirings Lx1 and a plurality of first vertical wirings Ly1, the second power supply line VDD2 may include a plurality of second horizontal wirings Lx2 and a plurality of second vertical wirings Ly2, and the third power supply line VDD3 may include a plurality of third horizontal wirings Lx3 and a plurality of third vertical wirings Ly3.

[0201] As shown in Figures 5-7, within a unit pixel, the first horizontal trace Lx1 of the first power line VDD1 may be located on a different layer from the first vertical trace Ly1, the second horizontal trace Lx2 of the second power line VDD2 may be located on a different layer from the second vertical trace Ly2, and the third horizontal trace Lx3 of the third power line VDD3 may be located on a different layer from the third vertical trace Ly3.

[0202] For example, the first horizontal wiring Lx1 may be electrically connected to the first vertical wiring Ly1 and insulated from the second vertical wiring Ly2 and the third vertical wiring Ly3. The second horizontal wiring Lx2 may be electrically connected to the second vertical wiring Ly2 and insulated from the first vertical wiring Ly1 and the third vertical wiring Ly3. The third horizontal wiring Lx3 may be electrically connected to the third vertical wiring Ly3 and insulated from the first vertical wiring Ly1 and the second vertical wiring Ly2.

[0203] The first, second, and third vertical wirings Ly1, Ly2, and Ly3 are located on the same layer but are spaced apart in the horizontal direction x and may contain the same metallic material. For example, as shown in the figure, the first, second, and third vertical wirings Ly1, Ly2, and Ly3 may be arranged horizontally x apart on the first planarization film 310 that covers a plurality of transistors ST1, ST2, and DT provided within a unit pixel.

[0204] The first, second, and third vertical wirings Ly1, Ly2, and Ly3 are electrically connected to the respective drive transistors DT of the first, second, and third subpixels SP1, SP2, and SP3 located within the unit pixel.

[0205] Specifically, the first vertical wiring Ly1 can be electrically connected to a drive transistor provided in the first subpixel SP1. For example, the first vertical wiring Ly1 is electrically connected to the drive transistor DT via the first switching transistor ST1 of the first subpixel SP1.

[0206] The second vertical wiring Ly2 can be electrically connected to a drive transistor provided in the second subpixel SP2 within a unit pixel. For example, the second vertical wiring Ly2 can be electrically connected to the drive transistor DT via the first switching transistor ST1 of the second subpixel SP2.

[0207] The third vertical wiring Ly3 can be electrically connected to a drive transistor provided in the third subpixel SP3 within a unit pixel. For example, the third vertical wiring Ly3 can be electrically connected to the drive transistor DT via the first switching transistor ST1 of the third subpixel SP3.

[0208] Furthermore, the first, second, and third horizontal wirings Lx1, Lx2, and Lx3 are located on the same layer within a unit pixel but are separated in the vertical direction y, contain the same metal material as each other, and may contain the same or different metal materials as the first, second, and third vertical wirings Ly1, Ly2, and Ly3.

[0209] For example, the first, second, and third horizontal wirings Lx1, Lx2, and Lx3 may be arranged on the second planarization film 320, spaced apart in the vertical direction y.

[0210] The first, second, and third horizontal wirings Lx1, Lx2, and Lx3 are electrically connected to the first, second, and third vertical wirings Ly1, Ly2, and Ly3, respectively, at the first, second, and third contact points CP1, CP2, and CP3, respectively.

[0211] Specifically, the first horizontal wiring Lx1 is electrically connected to the first vertical wiring Ly1 at the first contact point CP1 within a unit pixel. For example, as shown in Figure 7, at the first contact point CP1, the first horizontal wiring Lx1 and the first vertical wiring Ly1 are electrically connected to each other via the first contact point connection electrode CP1e that penetrates the second planarization film 320.

[0212] The second horizontal wiring Lx2 is electrically connected to the second vertical wiring Ly2 at the second contact point CP2 within a unit pixel. For example, as shown in Figure 7, at the second contact point CP2, the second horizontal wiring Lx2 and the second vertical wiring Ly2 are electrically connected to each other via the second contact point connection electrode CP2e that penetrates the second planarization film 320.

[0213] The third horizontal wiring Lx3 is electrically connected to the third vertical wiring Ly3 at the third contact point CP3 within a unit pixel. For example, as shown in Figure 7, at the third contact point CP3, the third horizontal wiring Lx3 and the third vertical wiring Ly3 are electrically connected to each other via the third contact point connection electrode CP3e, which penetrates the second planarization film 320.

[0214] Each of the first, second, and third contact points CP1, CP2, and CP3 may overlap with the bank 500 that defines the light-emitting regions of the first, second, and third subpixels SP1, SP2, and SP3. For example, as shown in Figure 7, the first, second, and third contact point connecting electrodes CP1e, CP2e, and CP3e may be positioned to overlap with the bank region BA. That is, the first, second, and third contact point connecting electrodes CP1e, CP2e, and CP3e may be positioned to overlap the lower part of the bank 500.

[0215] For example, multiple power lines that are not electrically connected to each other may be connected to multiple subpixels, each emitting light of a different color, and multiple drive voltages of different levels may be supplied through the multiple power lines. For example, a power supply may supply a first drive voltage through a first power line and a second drive voltage of a different level from the first drive voltage through a second power line.

[0216] Various examples and embodiments of the present invention are described below. These are illustrative examples and do not limit the scope of the invention.

[0217] In one or more examples, the display device may include a first subpixel configured to emit light of a first color, a second subpixel configured to emit light of a second color different from the first color, and a power supply configured to provide a first drive voltage to a first power line connected to the first subpixel and a second drive voltage to a second power line connected to the second subpixel. The first power line may include a plurality of first power lines (e.g., a first horizontal line and a first vertical line), and the second power line may include a plurality of second power lines (e.g., a second horizontal line and a second vertical line). The plurality of first power lines are connected to each other. The plurality of second power lines may be connected to each other. The plurality of first power lines may be configured not to be electrically connected to the plurality of second power lines. The first drive voltage may have a different level from the level of the second drive voltage.

[0218] In one example, a unit pixel may include a first subpixel and a second subpixel. Each of the first and second subpixels may include a driving transistor and a light-emitting element. Each driving transistor may have a drain electrode and a source electrode. Each light-emitting element may have an anode electrode and a cathode electrode. In one example, the drain electrode may point to the source electrode, and the source electrode may point to the drain electrode. In one example, the anode electrode may point to the cathode electrode, and the cathode electrode may point to the anode electrode. In one example, the period during which a subpixel (e.g., the first or second subpixel) is driven may include an initialization period and an emission period. The emission period may be the period during which the subpixel emits light. The initialization period may be the period during which the subpixel is prepared to emit light. The initialization period may be a period prior to the emission period.

[0219] For example, the first drive voltage may be the voltage with the highest absolute value among the voltages supplied to the first subpixel. The first drive voltage may be the voltage with the highest absolute value among the voltages supplied to the drive transistor of the first subpixel. The first drive voltage may be the voltage with the highest absolute value among the voltages supplied to the drain electrode or source electrode of the drive transistor of the first subpixel. The first drive voltage may be the voltage with the highest absolute value among the voltages supplied to the anode electrode of the light-emitting element of the first subpixel. The first drive voltage may be supplied during the initialization period, the emission period, or both the initialization period and the emission period.

[0220] For example, the second drive voltage may be the voltage with the highest absolute value among the voltages supplied to the second subpixel. The second drive voltage may be the voltage with the highest absolute value among the voltages supplied to the drive transistor of the second subpixel. The second drive voltage may be the voltage with the highest absolute value among the voltages applied to the drain electrode or source electrode of the drive transistor of the second subpixel. The second drive voltage may be the voltage with the highest absolute value among the voltages applied to the anode electrode of the light-emitting element of the second subpixel. The second drive voltage may be applied during the initialization period, the emission period, or both the initialization period and the emission period.

[0221] As an example, a display device may include a plurality of unit pixels, each having a first subpixel and a second subpixel. Each of the first subpixels corresponds to or includes a first subpixel, and each of the second subpixels corresponds to or may include a second subpixel. Thus, a first power line may be connected to the first subpixel, and a second power line may be connected to the second subpixel.

[0222] Thus, in the embodiments described herein, the power consumption of the display device can be reduced and the degradation of the drive transistors DT provided in the first, second, and third subpixels SP1, SP2, SP3 can be prevented by supplying different first, second, and third drive voltages V1, V2, V3 via the first, second, and third power lines VDD1, VDD2, and VDD3, respectively, which are electrically isolated from each other.

[0223] In the embodiments described herein, the first, second, and third power lines VDD1, VDD2, and VDD3 each include a grid structure wiring, so that even if a portion of each of the first, second, and third power lines VDD1, VDD2, and VDD3 is disconnected due to foreign matter, the first, second, and third drive voltages V1, V2, and V3 can be stably supplied to the first, second, and third subpixels SP1, SP2, and SP3, respectively, and the display device can be stably driven.

[0224] As described above, those skilled in the art will understand that various changes and modifications are possible without departing from the technical concept of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0225] 10 Display Panel 11 Timing Controller 12 Data Drive Unit 13 Gate drive unit DL Dataline GL Gate Line

Claims

1. A display panel including multiple unit pixels, including a first subpixel that emits a first color of light and a second subpixel that emits a second color of light different from the first color, A power supply unit that supplies a drive voltage via a first power line connected to the first subpixel and a second power line connected to the second subpixel. Includes, Each of the first power line and the second power line includes a grid structure wiring that is electrically isolated from each other. The power supply unit supplies a first drive voltage via the first power line and a second drive voltage at a different level from the first drive voltage via the second power line. Display device.

2. The grid structure wiring of the first power line is Multiple first horizontal wirings connected to the first subpixel and arranged horizontally on the display panel, Multiple first vertical wirings arranged vertically in the aforementioned display panel and Includes, The grid-structure wiring of the second power line is Multiple second horizontal wirings connected to the second subpixel and arranged horizontally on the display panel, Multiple second vertical wirings arranged vertically in the aforementioned display panel and including, The display device according to claim 1.

3. The plurality of first horizontal wirings and the plurality of first vertical wirings of the first power line are electrically connected to each other. The plurality of second horizontal wirings and the plurality of second vertical wirings of the second power line are electrically connected to each other. Each of the plurality of first horizontal wirings and each of the plurality of first vertical wirings is insulated from each of the plurality of second horizontal wirings and each of the plurality of second vertical wirings. The display device according to claim 2.

4. The first horizontal wiring is located on a different layer from the first vertical wiring. The second horizontal wiring is located on a different layer from the second vertical wiring. The display device according to claim 2.

5. The display device according to claim 2, wherein the first vertical wiring and the second vertical wiring are located on the same layer within the unit pixel and are spaced apart in the horizontal direction.

6. The display device according to claim 2, wherein the first horizontal wiring and the second horizontal wiring are located on the same layer within the unit pixel and are separated in the vertical direction.

7. The first vertical wiring and the second vertical wiring are located spaced apart on the first planarization film that covers a plurality of transistors provided within the unit pixel. The first horizontal wiring and the second horizontal wiring are positioned spaced apart on the second flattening film which covers the first vertical wiring and the second vertical wiring and the first flattening film. The display device according to claim 2.

8. Each of the multiple unit pixels is, A first contact point is electrically connected to the first horizontal wiring and the first vertical wiring at the point where they intersect, A second contact point is electrically connected to the second horizontal wiring and the second vertical wiring at the point where they intersect. The display device according to claim 2, comprising:

9. The display device according to claim 8, wherein each of the first contact point and the second contact point is superimposed on a bank defining the light-emitting regions of the first subpixel and the second subpixel.

10. At the first contact point, the first horizontal wiring and the first vertical wiring are electrically connected to each other by penetrating the second planarization film. At the second contact point, the second horizontal wiring and the second vertical wiring are electrically connected to each other by penetrating the second planarization film. The display device according to claim 8.

11. Within the aforementioned unit pixel, the first horizontal wiring is insulated from the second vertical wiring at the point where it intersects with the second vertical wiring. Within the aforementioned unit pixel, the second horizontal wiring is insulated from the first vertical wiring at the point where it intersects with the first vertical wiring. The display device according to claim 8.

12. The first subpixel includes a light-emitting element that emits red light, and the second subpixel includes a light-emitting element that emits green light. The first drive voltage has a potential at a lower level than the second drive voltage. The display device according to claim 1.

13. The plurality of unit pixels further comprises a third subpixel that emits light of a third color different from the first and second colors, The power supply unit further supplies a third drive voltage having a high potential drive voltage at a different level from the first drive voltage and the second drive voltage to the light-emitting element of the third subpixel via a third power line. The third power line has a grid structure wiring that is electrically separated from the first and second power lines. The display device according to claim 2.

14. The grid-structure wiring of the third power line is Multiple third horizontal wirings connected to the third subpixel and arranged horizontally on the display panel, Multiple third vertical wirings arranged horizontally on the aforementioned display panel and The display device according to claim 13, including the following:

15. The plurality of third horizontal wirings and the plurality of third vertical wirings of the third power line are electrically connected. The plurality of third horizontal wirings are insulated from the plurality of first horizontal wirings and the plurality of second horizontal wirings. The plurality of third vertical wirings are insulated from the plurality of first vertical wirings and the plurality of second vertical wirings. The display device according to claim 14.

16. The third horizontal wiring is, Within the aforementioned unit pixel, it is located on a layer different from the third vertical wiring, Within the unit pixel, it is located on the same layer as the first horizontal wiring and the second horizontal wiring, and is separated in the vertical direction, On the second planarization film that covers the first vertical wiring, the second vertical wiring, the third vertical wiring and the first planarization film, there are, positioned at a distance from the first horizontal wiring and the second horizontal wiring, The display device according to claim 14.

17. The aforementioned third vertical wiring is, Within the aforementioned unit pixel, it is located on the same layer as the first vertical wiring and the second vertical wiring, and is spaced apart in the horizontal direction. On the first planarization film covering the plurality of transistors provided within the unit pixel, positioned apart from the first vertical wiring and the second vertical wiring, The display device according to claim 14.

18. Each of the plurality of unit pixels further comprises a third contact point that is electrically connected to each other at the point where the third horizontal wiring and the third vertical wiring intersect each other. The third contact point is superimposed on the bank that defines the light-emitting region of the third subpixel, At the third contact point, the third horizontal wiring and the third vertical wiring are electrically connected to each other by penetrating the second planarization film. The display device according to claim 14.

19. The display device according to claim 18, wherein within the unit pixel, the third horizontal wiring is insulated from the first vertical wiring and the second vertical wiring at each point where it intersects with the first vertical wiring and the second vertical wiring.

20. The third subpixel includes a light-emitting element that emits blue light. The third drive voltage has a potential level higher than the first drive voltage and the second drive voltage. The display device according to claim 13.

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