Parallel Memory Repair Controller
The parallel memory repair system addresses the inefficiencies of serial memory repair by using a controller with parallel data buses and unique identifiers to simultaneously repair multiple blocks, reducing latency and optimizing memory repair processes.
JP2026116689APending Publication Date: 2026-07-10GOOGLE LLC
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- GOOGLE LLC
- Filing Date
- 2025-11-27
- Publication Date
- 2026-07-10
AI Technical Summary
Technical Problem
Existing memory repair processes in integrated circuits are serial and time-consuming, leading to unnecessary delays during startup and application instantiation due to the sequential repair of memory blocks, which affects user experience.
Method used
A parallel memory repair system utilizing a memory repair controller with parallel data buses and a one-time programmable memory controller to simultaneously repair multiple memory blocks by broadcasting repair data with unique identifiers, allowing independent processing by each block.
Benefits of technology
The system reduces startup latency by enabling parallel memory repair, conserves power, and optimizes OTP memory usage, achieving repair times under 100 microseconds without the need for ordered data storage or compression.
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Smart Images
Figure 2026116689000001_ABST
Abstract
The repair controller 110 and the memory block 150 or subsystem include techniques and architectures for communicating using parallel data transfer protocols. For example, the repair controller includes a one-time programming (OTP) controller / fuse box 118 and memory repair controllers coupled to the respective receiving units / modules 126 / 158 within the individual memory blocks. [Effect] The repair controller includes a transmitting unit / module and functions as a built-in self-healing (BISR) controller.
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