Pre-encoding during link establishment

Abstract

Examples described herein relate to an Ethernet physical layer transceiver (PHY) circuit for use in frame communications with a remote link partner. In some examples, the Ethernet PHY circuit can include a physical medium dependent (PMD) circuit for use in frame communications, a transmitter circuit, and a receiver circuit. In some examples, the PMD circuit performs link training with a partner transmitter and selectively requests the partner transmitter to apply a modulation scheme with precoding during link training based on the magnitude of one or more equalizer coefficient values.

Description

[Technical Field]

[0001] Related Applications This application claims priority under 35 U.S.C. 365(c) to U.S. patent application Ser. No. 18 / 143,034, filed May 3, 2023, which in turn claims priority to and the benefit of U.S. provisional patent application Ser. No. 63 / 433,647, filed December 19, 2022, the entire contents of which are incorporated herein by reference in their entireties. [Background technology]

[0002] Link training is a process used by devices connected to another device through a copper cable, backplane, or other wired or wireless signal transmission medium, whereby the transmitter and receiver communicate with each other to adjust equalizer settings to mitigate frequency-dependent signal attenuation. Link training can provide tuning of finite impulse response (FIR) filters for the channel in an application-specific integrated circuit (ASIC) or other device to achieve a desired bit error rate (BER), eye size, signal-to-noise ratio (SNR), or link error rate (e.g., uncorrectable and correctable forward error correction (FEC) errors, pseudorandom bit sequence (PRBS) errors, physical coding sublayer (PCS) errors, etc.). [Brief explanation of the drawings]

[0003] [Figure 1] 1 shows an example of an equalizer.

[0004] [Figure 2] An example of a training sequence is shown below.

[0005] [Figure 3] 1 illustrates an exemplary process.

[0006] [Figure 4A] An exemplary excerpt from IEEE 802.3-2022 is shown below. [Figure 4B] An exemplary excerpt from IEEE 802.3-2022 is shown below. [Figure 4C] An exemplary excerpt from IEEE 802.3-2022 is shown below. [Figure 4D] An exemplary excerpt from IEEE 802.3-2022 is shown below.

[0007] [Figure 5] An example of potential use of the 800GMII (800Gb / s Media Independent Interface) is given.

[0008] [Figure 6A] 1 illustrates an exemplary system. [Figure 6B] 1 illustrates an exemplary system. [Figure 6C] 1 illustrates an exemplary system.

[0009] [Figure 7] 1 illustrates a system capable of performing link monitoring.

[0010] [Figure 8] Shows network interfaces.

[0011] [Figure 9] 1 illustrates an exemplary computing system.

[0012] [Figure 10] 1 illustrates an exemplary computing system. DETAILED DESCRIPTION OF THE INVENTION

[0013] Precoding encodes a bit stream before transmission and can improve the performance of the equalizer at the receiver. Precoding is a mathematical technique that separates errors into ingress and egress errors. According to IEEE 802.3-2022, Section 136, and similar sections, Ethernet links at data rates of 50 Gbps per lane and higher are required to implement precoding capabilities for Pulse Amplitude Modulation 4-level (PAM-4) modulation on the transmitted bit stream to help reduce the likelihood of error bursts at the receiver due to feedback and sequence-dependent equalizers (e.g., Decision Feedback Equalizers (DFEs), Maximum Likelihood Sequence Estimation (MLSE), or others). Error bursts can result in uncorrectable errors despite the application of forward error correction (FEC). If error bursts are expected, precoding at the transmitter can improve the performance of the equalizer at the receiver. If bursts of errors are not expected (e.g., errors are randomly distributed), precoding at the transmitter may not be desirable because it can result in increased errors when decomposed into ingress and egress errors.

[0014] Some examples provide circuitry and / or processor-executed software in the receiver for determining whether to request precoding during the training phase of link establishment based on measurements made by the receiver based on the received training pattern. Precoding may be requested during the training phase of link establishment and finalized before exiting the training phase. For example, the receiver may determine whether to request the transmitter to apply precoding based on the converged response of decision feedback equalizer (DFE) coefficients in the receiver. If the magnitude of the normalized values ​​of the DFE tap coefficients in the receiver's equalizer is above a predetermined threshold (e.g., 0.5 or other value), the risk of error bursts may be sufficiently high, and the receiver may request that the transmitter apply precoding to training or data signals transmitted. In some examples, the training protocol allows the receiver to request a partner transmitter (e.g., a transmitter transmitting a training signal to the receiver) to allow precoding to be applied to signals transmitted to the receiver. The receiver's request for precoding to the transmitter may be enabled, disabled, or allowed to be automatically determined.

[0015] For example, in addition to or as an alternative to selecting the use of pre-coding, a device may use link training to adjust equalizer settings of at least one serializer / deserializer (SerDes). For example, a transmitter (Tx) may generate training data and transmit the training data to a receiver (Rx). Based on analysis of the training data, the receiver may provide feedback to the transmitter to adjust the transmitter's equalizer settings. For example, the receiver may select to request transmission using PAM-4 and pre-coding, which is applied when the receiver utilizes a DFE, a maximum likelihood sequence estimation (MLSE)-based equalizer, a continuous linear time equalizer (LTE), a feed-forward equalizer (FFE), or other equalizer type. Thus, the receiver may request adjustment of the transmitter equalizer coefficients (e.g., leading, main, or post-cursor coefficients), modulation scheme (e.g., PAM-2 or PAM-4), and pre-coding (e.g., using PAM-4 modulation). For example, a transmitter may apply precoding to the transmitted bitstream using 1 / (1+D) mod 4 precoding, as described in IEEE Std 802.3-2022, Section 135.5.7.2. Receivers may optionally provide the ability to decode precoded data and request precoding during control function link training.

[0016] For links trained to operate at speeds of 50 Gbps per lane or greater, the Ethernet link between two partners may execute a startup protocol using at least the physical medium dependent (PMD) control function based on IEEE Standard 802.3-2022, Section 136.8.11. As part of the startup protocol, the local receiver may request changes to its partner's transmitter's operation to adjust and potentially improve received signal quality. If the receiver requests that its link partner transmitter change its pre-cursor, main cursor, or post-cursor equalization settings, the eye examination process may begin again. In some examples, the receiver examines the signal eye after applying equalization to the signal to determine whether the eye height and / or eye width are within configured parameters. The receiver may decide to terminate link training because the eye is acceptable, or to continue training to further adjust the eye parameters. Factors other than the signal may be analyzed by the receiver to determine whether to continue or terminate link training.

[0017] Because both link partners include a transmitter and a receiver, a link partner can train the other partner's transmitter simultaneously with or after training the transmitter-receiver pair. After the link is trained, the two devices can send data traffic (e.g., non-training signals) with the precoding applied.

[0018] Figure 1 shows an example of a receiver architecture. The signal received from the channel (e.g., signal propagation medium) can be equalized and conditioned by a continuous time linear equalizer (CTLE) and a variable gain amplifier (VGA), sampled by an analog-to-digital converter (ADC), and further equalized using programmable circuitry. A slicer can be used to make a decision (e.g., Data[n]) on the received bits, and the error between the equalized signal and the decision can be calculated (e.g., Error[n] = Equalized Signal[n] - Data[n]).

[0019] The equalizer 102 can include an equalizer such as an FFE and / or a DFE, the output of which can be used to determine ISI. After detecting reflections on the pulse response (based on the aforementioned scan), the PHY link monitor 104 can calculate metrics of residual ISI (unequalized inter-symbol interference (ISI) and reflection-related ISI). Because the physical layer interface (PHY) link monitor 104 is used during mission mode traffic, it can perform ISI detection that operates non-destructively to the normal operation of the link. The link monitor 104 can measure channel ISI caused by insertion loss and reflections. The link monitor 104 can receive a receiver error signal and the detected data stream and determine whether changes in ISI tap values ​​indicate link or channel degradation or poor mating. For example, the link monitor 104 can calculate the projection of the ISI of the nth tap on the error signal by integrating Error[n]*Data[nk] for the nth tap of the ISI. For a series of measurements with n values, different taps of the ISI can be measured, and the system's pulse response can be mapped. The value of n can be negative or positive to estimate leading or trailing ISI taps. A threshold can be set to determine the span of the reflection (the range of n), and tap batches that exceed the threshold can be counted or identified as reflected ISI. Tap batches that do not exceed the threshold can be considered noise. In some examples, the link monitoring circuit 104 can be implemented as a processor or microcontroller running a process, a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or other programmable hardware device.

[0020] The use of precoding can mitigate the possibility of a burst of errors occurring when an incorrect decision (bit error) is made at the receiver regarding a particular bit, and the magnification effects of this error due to the DFE and coefficients. When a sample results in a bit error and this sample is multiplied by a DFE coefficient on a subsequent bit as part of the DFE's echo cancellation function, the application of the coefficient can cause the sampled bit to be evaluated incorrectly (e.g., a "0" is recorded instead of the true value of "1"), leading to another bit error. This bit error can then result in another bit error, and so on, until the coefficient decays.

[0021] Figure 2 shows an example of a PMD control state diagram, reproduced from IEEE 802.3-2022. A transmitter and receiver pair can apply the state diagram operations to change the transmitter equalization coefficients based on predefined initial conditions or by individual coefficient control.

[0022] FIG. 3 illustrates a process that may be utilized by a receiver to determine when to enable precoding of data by a transmitter. This process may be used in conjunction with at least the control state diagram illustrated in FIG. 2. For example, a receiver PMD implemented as one or more of firmware, software, and / or hardware may perform the training process of at least Figure 136-7 of IEEE 802.3-2022. Figure 136-7 of IEEE 802.3-2022 provides exemplary startup operations for a transmitter. However, the examples may apply to earlier or later versions of 802.3-2022, or variations thereof, or other standards. Some examples utilize control function training, in which the receiver may converge its equalizer to the input signal and adjust its DFE coefficients or other parameters. The receiver may request precoding by the transmitter, and the receiver may be retrained based on the monitored absolute value of the DFE coefficients exceeding a programmable threshold.

[0023] This process assumes that automatic precoding determination is enabled. If precoding is permanently enabled or disabled at the beginning of this flow, this process can be completed after the TX EQ setting is reached. During the INITIALIZE phase of Figure 2, the PMD control function link training can be entered. For example, the INITIALIZE phase can refer to the state of the transmitter-receiver pair before the transmitter transmits a training signal. During the SEND_TF phase of Figure 2, the receiver (RX) locks onto the incoming training signal sent by the transmitter. During SEND_TF, initial equalization and identification of control frames for alignment can begin at 302, in accordance with Section 136.8.11 and Figure 136-7 of IEEE Standard 802.3-2022. For example, the SEND_TF phase can refer to the state in which the transmitter transmits a training signal to the receiver.

[0024] During the TRAIN_LOCAL phase of FIG. 2, at 304, the receiver may request the transmission of a training signal encoded using a modulation scheme without precoding (e.g., PAM-4) transmitted to the receiver via one or more lanes. For example, the TRAIN_LOCAL phase may refer to a state in which link training occurs for a specific length of time. An exemplary training signal includes a training signal generated by a pseudorandom binary sequence 13 (PRBS13) polynomial based on a seed value. During TRAIN_LOCAL, at 306, the receiver may adapt to the training signal by performing receiver equalization tap optimization. During TRAIN_LOCAL, the receiver may perform initial equalization and identify at least one control frame for alignment. Examples of exemplary control frames are defined at least in IEEE 802.3-2022, Section 136.8.11.1.

[0025] During TRAIN_LOCAL, at 308, the receiver may determine whether to request the transmitter PMD to adjust one or more equalizer (EQ) settings based on an adaptation scheme. The adaptation scheme may determine whether equalization at the receiver, the transmitter, or the receiver and the transmitter should be performed to improve the quality of the received signal on the lane. An exemplary adaptation scheme includes a least mean square (LMS) error indication to determine how to adjust the transmitter equalizer setting(s) to reduce the slope of the LMS error.

[0026] During TRAIN_LOCAL, based on the receiver determining to request that the transmitter adjust one or more equalizer (EQ) settings, at 310 the receiver can request changes to transmitter coefficients that can utilize table 136-9 (reproduced in FIG. 4B), bits 4-2, to request changes to one or more transmitter FFE coefficients, such as C-1 or C+1. The process can return to 306, where the receiver can adapt to the training signal generated based on the adjusted transmitter coefficient settings.

[0027] During TRAIN_LOCAL, if the receiver does not decide to request the transmitter to adjust one or more equalizer (EQ) settings, a determination may be made at 320 whether to request pre-coding of the training signal or data signal based on the magnitude of the DFE coefficient values. For example, the DFE may include eight taps or another number of taps, and the taps may have associated coefficient values. For example, at 320, a determination may be made as to whether |DFE coefficient| > a threshold, where the DFE coefficients may refer to one or more DFE coefficient values. If the magnitude of one or more DFE coefficient values ​​is greater than the threshold, the current bit may affect the next bit, and an erroneous decision may propagate and affect future bits. A correlation may exist between DFE coefficient values ​​greater than the threshold and the occurrence of error bursts. The threshold may be determined based on operator selection, system simulation, or laboratory characterization and may be based on a hysteresis margin.

[0028] For example, Figure 4D shows an example pulse response at a receiver for channel equalization between two link partners. The contribution of intersymbol interference (ISI) due to the package and connectors is shown in the post-cursor pulse after the cursor. The DFE at the receiver can target and attempt to cancel the energy in the unit intervals (UIs) after the main cursor (sample position). If these coefficients are so large that there is a risk that an erroneous sample could cause a burst of errors by propagating this error through the coefficients applied to subsequent bits, a control frame can be used to request pre-coding during 322, as shown in Figure 4B.

[0029] Section 135.7.2 of IEEE 802.3-2022 (reproduced in Figure 4A) provides a non-limiting example scheme for the precoding to be applied. Precoding data can convert error sequences into ingress and egress errors. If the sequence is one bit long, precoding can lead to a one-bit error creating a two-bit error (ingress and egress). Thus, enabling precoding with randomly interspersed errors can lead to an increased number of errors. Bit error rate feedback from the receiver during training can further qualify whether precoding should be enabled at the receiver. If a known pattern is used during training, forward error correction (FEC) at the receiver can compensate for errors to balance enabling precoding and simply using FEC to correct errors without enabling precoding.

[0030] Referring back to FIG. 3, during TRAIN_LOCAL, at 322, the receiver can request the transmitter to apply precoding. In some cases, precoding can be associated with other signal modulation types, such as PAM-4 or pulse amplitude modulation 6-level (PAM-6). For example, the receiver can request the transmitter to apply PAM-4 with precoding by using bits 9 and 8 (Modulation and Precoding Request (value 11)) of table 136-9 (reproduced in FIG. 4B). FIG. 4C shows an example TX response to a PAM-4 with precoding request, using information in bits 11:10 of table 136-10 to indicate the use of PAM-4 with precoding.

[0031] Based on determining that the magnitude DFE coefficient is not greater than the threshold and that no precoding should be applied by the transmitter, link training can be completed and a local version of receiver ready occurs. During the TRAIN_REMOTE phase of FIG. 2, at 330, the receiver does not request the transmitter to apply precoding to the transmitted training signal. For example, TRAIN_REMOTE can refer to a state in which link training is complete.

[0032] In some examples, the receiver (RX) equalizer (EQ) and / or transmitter (TX) EQ can be re-adapted and another decision on whether to apply precoding can be made during another training phase, which can occur periodically or upon request of the receiver or system administrator.

[0033] 5 shows an example of a potential use of a 400GMII (400 Gb / s media independent interface). The examples are not limited to this scenario. Various examples described herein can utilize a PMD that can determine whether to apply precoding, which can occur during a separate training phase, as described herein.

[0034] 6A is a block diagram illustrating Ethernet port circuitry within a network interface controller 600. The Ethernet port logic includes a medium access control (MAC) module 602, an arbitration sublayer module 604, and a PHY module 606. The PHY module 606 can include a physical medium attachment (PMA) sublayer module 612, a physical medium dependent (PMD) sublayer 610, a forward error correction (FEC) module 614, and a physical coding sublayer (PCS) module 616.

[0035] The auto-negotiation (AN) circuit 608 can perform AN in a manner consistent with Figure 73-1 of IEEE 802.3-2022. For example, the AN circuit 608 can advertise its technology and FEC capabilities to a link partner using message code 2 base and next pages, as described herein. In some examples, the AN circuit 608 can advertise its ability to support an 800 GbE PHY, as described herein.

[0036] The MAC module 620 is configured to transfer data to and from the PHY module 606. The Reconciliation Sublayer (RS) module 618 can provide mapping operations to reconcile signals at the Media Independent Interface (MII) to Media Access Control (MAC)-Physical Signaling Sublayer (PLS) service definitions. The MAC module 620 can be configured to implement aspects of the MAC layer operations, and the RS module 618 can be configured to implement the Reconciliation Sublayer operations.

[0037] The Physical Medium Dependent (PMD) sublayer 610 may be responsible for interfacing with the transmission medium, Medium Dependent Interface (MDI) 622. Some examples described herein for requesting a transmitter to use PAM-4 with precoding may be performed by the PMD 610.

[0038] The physical medium attachment (PMA) sublayer 612 may perform transmission, reception, signal detection, clock recovery, and skew alignment. The PMD 610 and PMA 612 may be configured to transmit and receive serial data through the MDI 622.

[0039] In some examples, the PMD 610 and the PMA 612 may include or use a serializer / deserializer (SerDes). In some examples, link training and retraining may be provided to adjust filter parameters of transmit and / or receive equalizers used by the SerDes. For example, a software SerDes driver executed by a processor in the host or network interface may be used to change the transmit equalizer parameters. In some examples, any combination of hardware, software, and / or firmware may be used to manage and perform link training and / or link retraining.

[0040] In some examples (e.g., for 100GBASE-CR1 or 100GBASE-KR1), the FEC module 614 may decode data passed from the PMD 610 and PMA 612 to the PCS module 616, or encode data passed from the PCS module 616 to the PMD 610 and PMA 612a, 612b. In some examples (e.g., for 200G and 400G modes), the PCS module 616 includes the FEC module 614. Forward error correction codes can improve the reliability of data transmission at higher line speeds.

[0041] In the transmit direction, the MAC module receives data to be transmitted through the host interface 622. The MAC module 620 can receive data to be transmitted through the host interface 622. The MAC module 620 can generate a MAC frame that includes an inter-packet gap (IPG), a preamble, a start of frame delimiter (SFD), padding, and cyclic redundancy check (CRC) bits in addition to the received data before passing the MAC frame to the PHY module 606. The PHY module 606 can encode the MAC frame for reliable serial transmission through the MDI 624.

[0042] In the receive direction, the MAC module 620 can receive MAC frames from the PHY module 606 over the data bus. The MAC module 620 can perform Ethernet frame detection and validation, cyclic redundancy check (CRC) validation, statistical counter updates, CRC stripping, preamble detection and removal, and start of frame delimiter (SFD) detection and removal, and forward the remainder of the MAC frame, including headers for other protocols, to the next layer (e.g., the Internet Protocol (IP) layer) for processing. The PHY module 606 can decode MAC frames received over the MDI 624.

[0043] 6B shows a simplified example of a transmitter-receiver pair between the network interface controller 630 and the device 640. The MDI 635 provides a link between the network interface controller 630 and the device 640 by transferring data in parallel over one or more lanes. The device 640 can be any device, such as another NIC, a switch, a router, a server, a host computing platform, etc. An AN can be implemented using the ANs 632 and 642.

[0044] The network interface controller 630 may include a host receiver 634 and a host transmitter 636 for at least one lane of the electrical link between the network interface controller 630 and the device 640. The device 640 may include a module receiver 646 and a module transmitter 644 for the electrical link between the network interface controller 630 and the device 640.

[0045] For example, the link training controller 638 of the NIC 630 may initiate or manage link establishment, link training, or link retraining operations as described herein. The link training controller 638 may be implemented as one or a combination of a driver, a microcontroller, or other software within a host or network interface.

[0046] The transmitter (Tx) 636 / 644 or receiver (Rx) 634 / 646 can serialize or deserialize signals using a SerDes. When the SerDes is turned on and a signal is received, Rx tuning can be used to improve signal quality. When there is a time limit for performing Rx tuning, the signal should be passed to the PCS layer within the time limit, and if the link is acceptable, the link comes up. If the link does not pass, training can be restarted. In some examples, the Tx 636-Rx 646 and / or the Tx 644-Rx 634 can utilize independent Rx tuning. In some examples, the amount of time to perform equalizer tuning is the same for the Tx 636-Rx 646 and / or the Tx 644-Rx 634.

[0047] According to various examples, the link training controller 638 can perform link training and selectively request the transmitter to use PAM-4 with precoding as described herein.

[0048] Communication between devices can occur using any protocol. For example, an Ethernet frame can be transmitted by the NIC 630 to the device 640. For example, an Ethernet frame can be transmitted by the device 640 to the NIC 630. The Ethernet frame can include one or more of a preamble, a start of frame delimiter (SFD), a destination MAC address, a source MAC address, an Ethertype field, a length field, a frame check sequence (e.g., a cyclic redundancy check (CRC)), and a payload.

[0049] FIG. 6C illustrates an exemplary system for communicatively coupling a network device to another network device. For example, device 650 and device 670 may include network devices such as one or more of a network interface, a switch, a router, a server, a host computing platform, an interconnect, a fabric, a rack, or any computing or communication device. For example, device 670 may be connected to an interface having multiple electrical links (e.g., a backplane or copper cable). The system provides multiple transmit-receive paired lanes that may be used to transmit or receive electrical signals between device 650 and device 670. The lanes may transmit and / or receive signals. The transmitters of the lanes may generate electrical signals for transmission using an equalizer implemented in analog circuitry. The equalizer may have one or more current sources used to generate the signals, whereby the weights of the current sources may be adjusted to change the signal characteristics. The equalizer settings may be modified to change the weights of the current sources. For example, a digital-to-analog converter (DAC) may be used to generate the signal in the digital domain and output the result in analog form.

[0050] According to various examples, transceiver 680 can perform link training and selectively request a transmitter to use PAM-4 with precoding, as described herein. Transceiver 552 can perform operations similar to those of transceiver 680 in conjunction with device 670 to perform link training and selectively request a transmitter to use PAM-4 with precoding, as described herein.

[0051] Various examples may use one or more of the microcontrollers 684-0 through 684-N of the device 670 to initiate and manage link training of transmitter and / or receiver equalizer settings with any of the microcontrollers 656-0 through 656-N of the device 650.

[0052] The transceiver 680 may be used for transmitting and receiving electrical signals between the device 670 and the device 650. The transceiver 680 may provide multiple transmit and receive lanes for electrical signal communication between the device 670 and the device 650. For example, the lanes 682-0 through 682-N may provide transmit and receive circuitry for coupling with the receive and transmit circuitry of the lanes 654-0 through 654-N of the device 650. The lanes 682-0 through 682-N may provide serializer / deserializer (SerDes) formatting of the signals. In some examples, the transceiver 680 may be part of a PMD or a PHY.

[0053] Device 670 may be communicatively coupled to device 650 by interconnect 660. Interconnect 660 may be an electrical signal conductor coupling pins or holes of lanes 682-0 through 682-N of pluggable device 670 to holes or pins of lanes 654-0 through 654-N of device 650. Device 650 may send or receive signals in an electrical format to or from device 670.

[0054] The device 650 may include a transceiver 652 for communication with the device 670. The transceiver 652 may include lanes 654-0 through 654-N, any of which may include receive and transmit circuitry. In some examples, the transceiver 652 may be part of a PMD or PHY. Any of the microcontrollers 656-0 through 656-N may be used to manage the operation of that lane.

[0055] In some examples, a single microcontroller can manage the equalizer settings for one or more lanes. The one or more parameters can cause a receiver or transmitter device in any of lanes 654-0 through 654-N to adjust its equalizer setting for a particular tap, whether to increase or decrease the coefficient value of the equalizer tap. In some examples, the setting of a tap can be adjusted independently from adjusting the setting of another tap.

[0056] In some examples, device 650 can request to change the equalizer settings of any taps of the transmitter equalizer circuit of device 670. Similarly, device 670 can request to change the equalizer settings of any taps of the transmitter equalizer circuit of device 650. Thus, device 670 and device 650 can adjust the transmitter equalizer settings used by the partner device. Additionally, either device 670 or device 650 can adjust the receiver equalizer settings to compensate for channel distortion.

[0057] For example, to initiate an equalizer setting change, any microcontroller 684-0 through 684-N can determine the signal quality of the received signal and determine which transmitter taps of the device 650 to change and whether to increase or decrease the tap setting. For example, the eye opening of the received signal can be measured. The microcontroller can estimate inter-symbol interference (ISI) and select a setting based on which ISI reaches a minimum. The microcontroller can search through available transmitter tap settings and select the setting that leads to the most open eye. The transmitter equalizer setting can be changed periodically, beginning at or after link startup, and can be performed periodically. Similar operations may be performed for the microcontrollers 656-0 through 656-N to adjust the transmit equalizer settings of the device 670.

[0058] Device 670 and / or device 650 may perform packet processing such as one or more of medium access control, any protocol layer processing, security, routing, destination lookup, and the like.

[0059] FIG. 7 illustrates a system capable of performing link training. A host 700 may utilize a network interface device 720 to communicate with a host 760 via a network interface device 770 using a link 750. Optical and / or electrical signal propagation media may provide communication for the link 750. Various examples of the host 700 and the host 760 are described with respect to FIG. 4, and various examples of the network interface device 720 and the network interface device 770 are described with respect to FIG. 5 and / or FIG. 6. Examples described herein may be used in a 5G base station or a cellular communication network.

[0060] The host 700 can use one or more processors to execute port configuration software 706. The port configuration software 706 can be provided by a communications equipment manufacturer to manage the operation of a serializer-deserializer (SerDes) 732 that communicates using one or more links 750. The port configuration 706 can enable the use of one or more ports to establish links 750 between a network interface device 720 and a network interface device 770. The port configuration 706 can manage port and link usage through a stack of APIs and drivers 708 that control a link medium access controller (MAC) (not shown in FIG. 7) and a physical layer interface (PHY) 730.

[0061] During training of the links 750 using the driver and API 708, the port configuration software 706 can configure the operation of the link monitor circuit 740 within the PHY 730 of the network interface device 720 to perform monitoring of one or more of the links 750. In some examples, the link monitor circuit 740 can be implemented as a process running on a processor or microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or other programmable hardware device. The link monitor circuit 740 can monitor the eye height of an analog signal, or a digital conversion of a signal, received by one of the SerDes 732 from a transmission medium (e.g., an electrical or optical cable). The link monitor circuit 740 can perform link training and selectively request the transmitter to use PAM-4 with precoding as described herein.

[0062] Link monitoring is port mode agnostic and can be used for Ethernet (e.g., IEEE 802.3-2018), Common Public Radio Interface (CPRI) (e.g., CPRI Specification v7.0 (2015)), Peripheral Component Interconnect express (PCIe) (e.g., PCI-SIG PCI Express (2015)), or another serial input / output (IO) protocol.

[0063] Note that link monitoring can be utilized on one or both sides of a link. For example, PHY 780 can utilize link monitor 782, which operates in a manner similar to link monitor 740.

[0064] FIG. 8 illustrates an exemplary network interface. Various resources in the network interface can selectively request the transmitter to perform link training and use PAM-4 with precoding as described herein. The transceiver 802 may be capable of receiving and transmitting packets in accordance with an applicable protocol, such as Ethernet as described in IEEE 802.3, although other protocols may be used. The transceiver 802 can receive packets from a network and transmit packets to a network via a network medium (not shown). The transceiver 802 can include a PHY circuit 814 and a medium access control (MAC) circuit 816. The PHY circuit 814 can include encoding and decoding circuitry (not shown) for encoding and decoding data packets in accordance with an applicable physical layer specification or standard.

[0065] In some examples, the PHY 814 can select a PRBS polynomial and / or a seed for use in generating a training signal as described herein. In some examples, the PHY 814 can include a PMD for selecting a PRBS polynomial and / or a seed for training multiple lanes. Various resources within the network interface can perform link establishment, link training, or link retraining according to examples described herein.

[0066] The MAC circuit 816 may be configured to assemble data to be transmitted into packets that include destination and source addresses along with network control information and error detection hash values. The processor 804 may be any combination of processors, cores, graphics processing units (GPUs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), or other programmable hardware devices that allow programming of the network interface 800. For example, the processor 804 may provide identification of resources to use to execute a workload and generation of a bitstream to execute on the selected resources. For example, a "smart network interface" may use the processor 804 to provide packet processing capabilities at the network interface.

[0067] The packet allocator 824 can use time slot allocation or RSS as described herein to provide distribution of received packets for processing by multiple CPUs or cores. When the packet allocator 824 uses RSS, the packet allocator 824 can calculate a hash or make another determination based on the content of the received packet to determine which CPU or core should process the packet.

[0068] Interrupt coalescing 822 can perform interrupt moderation, whereby the network interface interrupt coalescing 822 waits for multiple packets to arrive or for a timeout to expire before generating an interrupt to the host system to process the received packet. Receive segment coalescing (RSC) is performed by the network interface 800, whereby portions of an incoming packet are combined into packet segments. The network interface 800 provides this coalesced packet to the application.

[0069] The direct memory access (DMA) engine 852 can copy packet headers, packet payloads, and / or descriptors directly from host memory to the network interface, or vice versa, rather than copying the packet to an intermediate buffer in the host and then using another copy operation from the intermediate buffer to the destination buffer.

[0070] The memory 810 may be any type of volatile or non-volatile memory device and may store any instructions or queues used to program the network interface 800. The transmit queue 806 may contain data or references to data for transmission by the network interface. The receive queue 808 may contain data or references to data received by the network interface from the network. The descriptor queue 820 may contain descriptors that reference data or packets in the transmit queue 806 or the receive queue 808. The bus interface 812 may provide an interface with a host device (not shown). For example, the bus interface 812 may be compatible with a PCI, PCI Express, PCI-x, Serial ATA, and / or USB-compatible interface (although other interconnect standards may be used).

[0071] In some examples, the network interface and other examples described herein may be used in connection with a base station (e.g., 3G, 4G, 5G, etc.), a macro base station (e.g., in a 5G network), a pico station (e.g., an IEEE 802.11 compatible access point), a nano station (e.g., for point-to-multipoint (PtMP) applications), an on-premises data center, an off-premises data center, an edge network element, a fog network element, and / or a hybrid data center (e.g., a data center that uses virtualization, cloud, and software-defined networking to distribute application workloads across physical data centers and distributed multi-cloud environments).

[0072] FIG. 9 illustrates a system. Components of system 900 (e.g., processor 910, network interface 950, etc.) perform link training and selectively request a transmitter to use PAM-4 with precoding, as described herein. System 900 includes processor 910, which provides processing, operational management, and execution of instructions for system 900. Processor 910 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware that provides processing for system 900, or a combination of processors. Processor 910 controls the overall operation of system 900 and may be or include one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), etc., or a combination of such devices.

[0073] In one example, system 900 includes an interface 912 coupled to processor 910, which may represent a higher speed or high throughput interface for a system component requiring a higher bandwidth connection, such as memory subsystem 920 or graphics interface component 940, or accelerator 942. Interface 912 represents interface circuitry that may be a stand-alone component or integrated onto the processor die.

[0074] The accelerators 942 may be fixed-function or programmable offload engines that may be accessed or used by the processor 910. For example, one of the accelerators 942 may provide a compression (DC) function, a cryptographic service such as public key encryption (PKE), a cipher, a hash / authentication function, decryption, or other function or service. In some examples, additionally or alternatively, one of the accelerators 942 provides a field selection controller function as described herein. In some cases, the accelerator 942 may be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that contains a CPU and provides an electrical interface with the CPU). For example, the accelerator 942 may include a single-core or multi-core processor, a graphics processing unit, a logic execution unit (LES) with a single-level or multi-level cache, a functional unit usable for independently executing programs or threads, an application-specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and a programmable processing element, such as a field-programmable gate array (FPGA) or programmable logic device (PLD). The accelerator 942 may provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or graphics processing units may be made available for use by artificial intelligence (AI) or machine learning (ML) models. For example, the AI ​​models may use or include one or more of reinforcement learning methods, Q-learning methods, deep Q-learning, or asynchronous advantage actor-critic (A3C), combinatorial neural networks, recurrent combinatorial neural networks, or other AI or ML models. Multiple neural networks, processor cores, or graphics processing units may be made available for use by the AI ​​or ML models.

[0075] Memory subsystem 920 represents the main memory of system 900, providing storage for code executed by processor 910 or data values ​​used in executing routines. Memory subsystem 920 may include one or more memory devices 930, such as one or more varieties of random access memory (RAM), such as read-only memory (ROM), flash memory, static random access memory (SRAM), dynamic random access memory (DRAM), or other memory devices, or a combination of such devices. Memory 930 stores and hosts, among other things, an operating system (OS) 932, providing a software platform for the execution of instructions within system 900. Additionally, applications 934 may execute on the OS 932 software platform from memory 930. Applications 934 represent programs having their own operating logic for performing the execution of one or more functions. Processes 936 represent agents or routines that provide auxiliary functionality to OS 932 or one or more applications 934, or a combination. OS 932, applications 934, and processes 936 provide the software logic that provides functionality for system 900. In one example, memory subsystem 920 includes memory controller 922, which is a memory controller that generates and issues commands to memory 930. It will be understood that memory controller 922 can be a physical part of processor 910 or a physical part of interface 912. For example, memory controller 922 can be an integrated memory controller integrated on circuitry with processor 910.

[0076] In some examples, OS 932 may be Linux, Windows, server or personal computer, FreeBSD, Android, MacOS, iOS, VMware vSphere, OpenSUV, RHEL, CentOS, Debian, Ubuntu, or any other operating system. The OS and drivers may run on CPUs sold or designed by Intel, ARM, AMD, Qualcomm, IBM, Texas Instruments, among others.

[0077] In some examples, OS 932 or a driver for network interface 950 can enable or disable network interface 950 to perform link training as described herein and selectively request a transmitter to use PAM-4 with precoding. In some examples, OS 932 or a driver for network interface 950 can enable or disable network interface 950 to indicate support for performing link training as described herein and selectively requesting a transmitter to apply PAM-4 with precoding to transmitted signals. Network interface 950 can instruct OS 932 or a driver function to perform link training as described herein and selectively request a transmitter to use PAM-4 with precoding or other modulation schemes. Network interface 950 can receive configuration and instructions (e.g., from OS 932 or a driver) to perform or not perform link training and selectively request a transmitter to use PAM-4 with precoding or other modulation schemes as described herein.

[0078] Although not specifically shown, it will be understood that system 900 can include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or the like. A bus or other signal line can communicatively or electrically couple components, or can communicatively and electrically couple components. A bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or a combination. A bus can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 bus (Firewire).

[0079] In one example, system 900 includes an interface 914 that can be coupled to interface 912. In one example, interface 914 represents an interface circuit that can include a standalone component and an integrated circuit. In one example, multiple user interface components, peripheral components, or both are coupled to interface 914. Network interface 950 provides system 900 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. In some examples, network interface 950 can refer to one or more of a network interface controller (NIC), a remote direct memory access (RDMA)-capable NIC, a SmartNIC, a router, a switch, a forwarding element, an infrastructure processing unit (IPU), a data processing unit (DPU), or a network connectivity device.

[0080] The network interface 950 may include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a Universal Serial Bus (USB), or other wired or wireless standards-based or proprietary interface. The network interface 950 may transmit data to devices within the same data center or rack or to remote devices, which may include transmitting data stored in memory.

[0081] Some examples of network interface 950 are part of or utilized by an infrastructure processing unit (IPU) or data processing unit (DPU). An xPU can refer to at least an IPU, DPU, GPU, GPGPU, or other processing unit (e.g., accelerator device). An IPU or DPU can include a network interface with one or more programmable pipeline or fixed function processors to perform offloading of operations that might otherwise be performed by a CPU. An IPU or DPU can include one or more memory devices. In some embodiments, an IPU or DPU can perform virtual switch operations, manage storage transactions (e.g., compression, encryption, virtualization), and manage operations running on other IPUs, DPUs, servers, or devices.

[0082] Some examples of network interface 950 may include a programmable packet processing pipeline having one or more successive stages of match-action circuitry, which may be programmed using one or more of Protocol Independent Packet Processor (P4), Software for Open Networking in the Cloud (SONiC), Broadcom® Network Programming Language (NPL), NVIDIA® CUDA®, NVIDIA® DOCA™, Data Plane Development Kit (DPDK), OpenDataPlane (ODP), Infrastructure Programmer Development Kit (IPDK), x86-compatible executable binaries or other executable binaries, or others.

[0083] Some examples of network interface 950 may include PHY circuitry that can perform link training and selectively request the transmitter to use PAM-4 with precoding, as described herein.

[0084] In one example, system 900 includes one or more input / output (I / O) interfaces 960. I / O interface 960 can include one or more interface components (e.g., voice, alphanumeric, haptic / touch, or other interfaces) through which a user interacts with system 900. Peripheral interface 970 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that connect to system 900 in a dependent manner. A dependent connection is one in which system 900 provides a software or hardware platform, or both, on which operations are executed and with which a user interacts.

[0085] In one example, system 900 includes a storage subsystem 980 for non-volatilely storing data. In one example, in certain system implementations, at least certain components of storage 980 can overlap with components of memory subsystem 920. Storage subsystem 980 includes storage device 984, which can be or include any conventional medium for non-volatilely storing large amounts of data, such as one or more magnetic, solid-state, or optical-based disks, or a combination. Storage 984 holds code or instructions and data 986 in a persistent state (e.g., values ​​are retained despite interruption of power to system 900). While storage 984 can be generally considered “memory,” memory 930 is typically an execution or operating memory for providing instructions to processor 910. While storage 984 is non-volatile, memory 930 can include volatile memory (e.g., the value or state of data is indeterminate if power is interrupted to system 900). In one example, storage subsystem 980 includes a controller 982 that interfaces with storage 984. In one example, the controller 982 may be a physical part of the interface 914 or the processor 910 , or may include circuitry or logic in both the processor 910 and the interface 914 .

[0086] Volatile memory is memory whose state (and therefore the data stored therein) is indeterminate if power to the device is interrupted. A non-volatile memory (NVM) device is memory whose state is deterministic even if power to the device is interrupted.

[0087] In one example, system 900 may be implemented using interconnected compute sleds of processors, memory, storage, network interfaces, and other components. High-speed interconnects may be used, such as Ethernet (IEEE 802.3), Remote Direct Memory Access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Quick UDP Internet Connection (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect Express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, Compute Express Link (CXL), HyperTransport, high-speed fabrics, NVLink, Advanced Microcontroller Bus Architecture (AMBA) Interconnect, OpenCAPI, Gen-Z, Infinity Fabric (IF), Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3 GPP 5G, and variants thereof. Data can be copied or stored on virtualized storage nodes or accessed using protocols such as NVMe over Fabrics (NVMe-oF) or NVMe.

[0088] Communication between devices may occur using a network, interconnect, or circuitry that provides chip-to-chip communication, die-to-die communication, packet-based communication, communication through a device interface, fabric-based communication, etc. Die-to-die communication may be consistent with an embedded multi-die interconnect bridge (EMIB).

[0089] 10 illustrates an exemplary system in which an IPU 1000 manages the execution of one or more processes using one or more of a processor 1006, a processor 1010, an accelerator 1020, a memory pool 1030, or servers 1040-0 through 1040-N, where N is an integer greater than or equal to 1. In some examples, the processor 1006 of the IPU 1000 can execute one or more processes, applications, VMs, containers, microservices, etc. that require workload execution by one or more of the processor 1010, the accelerator 1020, the memory pool 1030, and / or the servers 1040-0 through 1040-N. The IPU 1000 can communicate with the processor 1010, the accelerator 1020, the memory pool 1030, and / or the servers 1040-0 through 1040-N using a network interface 1002 or one or more device interfaces. The IPU 1000 may utilize a programmable pipeline 1004 to process packets to be transmitted from or received from the network interface 1002. The IPU 1000 may include PHY circuitry that can perform link training and selectively request the transmitter to use PAM-4 with precoding, as described herein.

[0090] Examples herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers, used in data center and / or server farm environments. Servers used in data centers and server farms include arrayed server configurations, such as rack-based servers or blade servers. These servers are interconnected to communicate via various network provisions. For example, sets of servers may be divided into local area networks (LANs) with appropriate switching and routing capabilities between the LANs to form a private intranet. For example, cloud hosting facilities may typically employ large data centers with many servers. A blade is a separate computing platform configured to perform server-type functions, i.e., a "server on a card." Thus, a blade may include components common to a traditional server, including a main printed circuit board (mainboard) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted on the board.

[0091] In some examples, the network interfaces and other examples described herein may be used in connection with a base station (e.g., 3G, 4G, 5G, etc.), a macro base station (e.g., in a 5G network), a pico station (e.g., an IEEE 802.11 compatible access point), a nano station (e.g., for point-to-multipoint (PtMP) applications), a micro data center, an on-premises data center, an off-premises data center, an edge network element, a fog network element, and / or a hybrid data center (e.g., a data center that uses virtualization, serverless computing systems (e.g., Amazon Web Services (AWS) Lambda), content delivery networks (CDNs), cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

[0092] For example, link establishment, link training, or link retraining may be applied by base stations supporting communications using wired or wireless protocols (e.g., 3GPP® Long Term Evolution (LTE) (4G) or 3GPP® 5G), on-premises data centers, off-premises data centers, edge network elements (computing elements provided physically closer to base stations or network access points than data centers), fog network elements (computing elements provided physically closer to base stations or network access points than data centers but farther from edge networks), and / or hybrid data centers (e.g., data centers using virtualization, cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multicloud environments). The networks or computing elements may be used in a local area network (LAN), a metropolitan area network (MAN), a network with devices connected using fiber optic links, a campus area network (CAN), or a wide area network (WAN).

[0093] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or combinations thereof. The decision of whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computation rate, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints desired for a given implementation. A processor may be a hardware state machine, digital control logic, a central processing unit, or any combination of one or more hardware, firmware, and / or software elements.

[0094] Some examples may be implemented using or as an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium that stores logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or combinations thereof.

[0095] According to some examples, a computer-readable medium may include a non-transitory storage medium for storing or maintaining instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or operations according to the described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, computing device, or system to perform a certain function. The instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0096] One or more aspects of at least one example may be implemented by representative instructions stored on at least one machine-readable medium that represent various logic within a processor, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to produce logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that actually create the logic or processor.

[0097] The appearances of the phrase "one example" or "example" do not necessarily all refer to the same example. Any aspect described herein can be combined with any other aspect described herein or with similar aspects, regardless of whether those aspects are described with respect to the same figure or element. The division, omission, or inclusion of block functions shown in the accompanying drawings does not imply that hardware components, circuits, software, and / or elements for implementing those functions are necessarily divided, omitted, or included in the examples.

[0098] Some examples may be described using the terms "coupled" and "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more elements are not in direct contact with each other, but yet still cooperate or interact with each other.

[0099] The terms "first," "second," and the like, used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "a" and "an" used herein do not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The term "asserted," as used herein with respect to a signal, indicates that the signal is active and may be achieved by applying any logic level, either logic 0 or logic 1, to the signal. The terms "following" or "after" may refer to immediately after or after some other event(s). Alternatively, other sequences of operations may be performed. Furthermore, additional operations may be added or removed depending on the particular application. Any combination of changes may be used, and one of ordinary skill in the art, having the benefit of this disclosure, will recognize numerous variations, modifications, and alternatives thereof.

[0100] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is understood within the context in which it is generally used to indicate that an item, term, etc., can be either X, Y, or Z, or a combination thereof (e.g., X, Y, and / or Z), unless otherwise noted. Thus, such disjunctive language is generally not intended to, and should not, imply that a particular instance requires that at least one of X, at least one of Y, or at least one of Z, respectively, be present. Furthermore, conjunctive language, such as the phrase "at least one of X, Y, and Z," should also be understood to mean X, Y, Z, or a combination thereof, including "X, Y, and / or Z," unless otherwise noted.

[0101] Illustrative examples of the devices, systems, and methods disclosed herein are provided below. Example devices, systems, and methods may include one or more of the examples described below, and combinations thereof. [Example]

[0102] Example 1, including one or more embodiments, includes an apparatus comprising an Ethernet physical layer transceiver (PHY) circuit for use in frame communications with a remote link partner, the Ethernet PHY circuit comprising: a physical medium dependent (PMD) circuit; and a transmitter circuit and a receiver circuit for use in frame communications, the PMD circuit for performing link training with a partner transmitter and selectively requesting, during the link training, the partner transmitter to apply a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values, the modulation scheme comprising pulse amplitude modulation four level (PAM-4) or pulse amplitude modulation six level (PAM-6), and requesting the partner transmitter to apply the modulation scheme with pre-coding during link training includes transmitting a control signal to the partner transmitter.

[0103] Example 2 includes one or more embodiments, wherein the control signal includes a modulation and precoding request.

[0104] Example 3 includes one or more embodiments, wherein the equalizer coefficient values ​​include one or more of: decision feedback equalizer (DFE) leading coefficient values, main coefficient values, or trailing coefficient values; feedforward equalizer (FFE) coefficient values; or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

[0105] Example 4 includes one or more embodiments, wherein the PMD circuitry does not require the partner transmitter to use a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values.

[0106] Example 5 includes one or more embodiments and includes circuitry for applying forward error correction (FEC) to correct errors in a received signal from the partner transmitter.

[0107] Example 6 includes one or more embodiments, including circuitry for requesting an equalizer setting adjustment by the partner transmitter based on the link training.

[0108] Example 7, including one or more embodiments, includes a non-transitory computer-readable medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to execute an operating system (OS) to configure circuitry of a network interface device to enable link training and to selectively request a partner transmitter to use a modulation scheme with pre-coding during the link training based on the magnitude of one or more equalizer coefficient values.

[0109] Example 8 includes one or more of the examples, wherein the modulation scheme includes pulse amplitude modulation four-level (PAM-4) or pulse amplitude modulation six-level (PAM-6).

[0110] Example 9 includes one or more embodiments, wherein requesting the partner transmitter to apply the modulation scheme with precoding during the link training is based on transmitting a control signal to the partner transmitter.

[0111] Example 10 includes one or more embodiments, wherein the control signal includes a modulation and precoding request.

[0112] Example 11 includes one or more embodiments, wherein the equalizer coefficient values ​​include one or more of decision feedback equalizer (DFE) leading coefficient values, main coefficient values, or trailing coefficient values, feedforward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

[0113] Example 12 includes one or more embodiments in which the circuitry does not require the partner transmitter to use a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values.

[0114] Example 13 includes one or more embodiments wherein the OS selectively disables the circuitry of the network interface device from using a modulation scheme that employs precoding during the link training based on the magnitude of one or more equalizer coefficient values.

[0115] Example 14, including one or more embodiments, includes a method including physical medium dependent (PMD) circuitry performing link training with a partner transmitter and selectively requesting the partner transmitter during the link training to apply a modulation scheme using pre-coding based on the magnitude of one or more equalizer coefficient values, wherein the modulation scheme includes pulse amplitude modulation four level (PAM-4) or pulse amplitude modulation six level (PAM-6).

[0116] Example 15 includes one or more embodiments, wherein requesting the partner transmitter to apply the modulation scheme with precoding during the link training is based on transmitting a control signal to the partner transmitter.

[0117] Example 16 includes one or more embodiments in which the control signal includes a modulation and precoding request.

[0118] Example 17 includes one or more embodiments, wherein the equalizer coefficient values ​​include one or more of decision feedback equalizer (DFE) leading coefficient values, main coefficient values, or trailing coefficient values, feedforward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

[0119] Example 18 includes one or more embodiments, including the PMD circuit not requiring the partner transmitter to use a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values.

[0120] Example 19 includes one or more embodiments and includes requesting an equalizer setting adjustment by the partner transmitter based on the link training.

Claims

1. 1. An apparatus comprising an Ethernet physical layer transceiver (PHY) circuit for use in frame communication with a remote link partner, the Ethernet PHY circuit comprising: Physical medium dependent (PMD) circuitry; transmitter and receiver circuits for use in said frame communications; Equipped with the PMD circuitry performs link training with a partner transmitter and selectively requests the partner transmitter to apply a modulation scheme with precoding during the link training based on the magnitude of one or more equalizer coefficient values; The modulation method includes pulse amplitude modulation 4 levels (PAM-4) or pulse amplitude modulation 6 levels (PAM-6), and requesting the partner transmitter to apply the modulation scheme with precoding during the link training includes transmitting a control signal to the partner transmitter. Device.

2. The apparatus of claim 1 , wherein the control signal includes a modulation and precoding request.

3. 2. The apparatus of claim 1, wherein the equalizer coefficient values ​​include one or more of: a decision feedback equalizer (DFE) leading coefficient value, a main coefficient value, or a trailing coefficient value; a feedforward equalizer (FFE) coefficient value; or a maximum likelihood sequence estimation (MLSE) equalizer coefficient value.

4. 10. The apparatus of claim 1, wherein the PMD circuitry does not require the partner transmitter to use a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values.

5. The apparatus of claim 4 , comprising circuitry for applying forward error correction (FEC) to correct errors in a received signal from the partner transmitter.

6. 6. The apparatus of claim 1, further comprising: circuitry for requesting equalizer setting adjustments by the partner transmitter based on the link training.

7. At least one non-transitory computer-readable medium storing instructions that, when executed by one or more processors, cause the one or more processors to: enabling link training to be performed and selectively requesting a partner transmitter to use a modulation scheme with precoding during said link training based on the magnitude of one or more equalizer coefficient values; A network interface device that runs an operating system (OS) to configure the circuitry of the network interface device. Computer-readable medium.

8. 8. The computer-readable medium of claim 7, wherein the modulation scheme comprises Pulse Amplitude Modulation 4-level (PAM-4) or Pulse Amplitude Modulation 6-level (PAM-6).

9. 8. The computer-readable medium of claim 7, wherein requesting the partner transmitter to apply the modulation scheme with precoding during the link training is based on sending a control signal to the partner transmitter.

10. The computer-readable medium of claim 9 , wherein the control signal includes a modulation and precoding request.

11. 8. The computer-readable medium of claim 7, wherein the equalizer coefficient values ​​include one or more of decision feedback equalizer (DFE) leading, main, or trailing coefficient values, feedforward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

12. 8. The computer-readable medium of claim 7, wherein the circuitry does not require the partner transmitter to use a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values.

13. 13. The computer-readable medium of claim 7, wherein the OS selectively disables the circuitry of the network interface device to not use modulation schemes with pre-coding during the link training based on the magnitude of one or more equalizer coefficient values.

14. 1. A method comprising: a physical medium dependent (PMD) circuit performing link training with a partner transmitter and selectively requesting the partner transmitter to apply a modulation scheme with precoding during the link training based on magnitudes of one or more equalizer coefficient values.

15. 15. The method of claim 14, wherein the modulation scheme comprises Pulse Amplitude Modulation 4-level (PAM-4) or Pulse Amplitude Modulation 6-level (PAM-6).

16. 15. The method of claim 14, wherein requesting the partner transmitter to apply the modulation scheme with precoding during the link training is based on transmitting a control signal to the partner transmitter.

17. 17. The method of claim 16, wherein the control signal includes a modulation and precoding request.

18. 15. The method of claim 14, wherein the equalizer coefficient values ​​include one or more of decision feedback equalizer (DFE) leading, main, or trailing coefficient values, feedforward equalizer (FFE) coefficient values, or maximum likelihood sequence estimation (MLSE) equalizer coefficient values.

19. requesting an equalizer setting adjustment by the partner transmitter based on the link training.

15. The method of claim 14.

20. the PMD circuit not requiring the partner transmitter to use a modulation scheme with pre-coding based on the magnitude of one or more equalizer coefficient values.

20. The method of any one of claims 14 to 19.

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