Data processing method and data processing device

Abstract

A data processing method, comprising: performing PCS processing on a first set of k bits to obtain a second set of bits; performing FEC encoding on the second set of bits and a third set of k bits excluding the first set of bits to obtain a fourth set of bits; the fourth set of bits including m0 first bit subsets, each including an F0 bit; and performing a first interleaving process on the fourth set of bits to obtain a fifth set of bits; the fifth set of bits including m0 second bit subsets, each including an F0 bit, an F0 / 2 bit in each of the second bit subsets being from the second bit set, and the other F0 / 2 bits in each of the second bit subsets being from the third set of bits and / or parity bits of the FEC encoding.

Description

[Technical Field]

[0001] This application claims priority to Chinese Patent Application No. 202310206681.6, filed with the State Intellectual Property Office of China on February 25, 2023, entitled "Data Processing Method and Data Processing Device," Chinese Patent Application No. 202310359894.2, filed with the State Intellectual Property Office of China on March 28, 2023, entitled "Data Processing Method and Data Processing Device," Chinese Patent Application No. 202310491179.4, filed with the State Intellectual Property Office of China on April 28, 2023, entitled "Data Processing Method and Data Processing Device," and Chinese Patent Application No. 202311055979.8, filed with the State Intellectual Property Office of China on August 18, 2023, entitled "Data Processing Method and Data Processing Device," all of which are incorporated herein by reference in their entireties.

[0002] The present application relates to the field of communications, and in particular to a data processing method and device. [Background technology]

[0003] With the continued advancement of 5G, cloud computing, big data, artificial intelligence, and other technologies, high-speed optical transport networks are becoming high-capacity, packet-based, and intelligent. Coherent optical communication systems utilize the amplitude, phase, polarization, and frequency of light waves to carry information. To withstand optical signal distortions caused by dispersion, polarization-dependent impairments, noise, nonlinear effects, and other factors during transmission and maintain long-distance transmission, coherent optical communication systems typically require the use of efficient forward error correction (FEC) codes to withstand optical impairments during optical transmission and ensure a sufficiently low bit error rate (BER) during long-distance transmission. For example, the OpenFEC code, commonly referred to as OFEC code, currently used in 400ZR+ and 800ZR, has a 15.3% overhead (OH). When soft-decision decoding is used, performance is approximately 2.0E-2 before correction.

[0004] To improve spectral efficiency, multi-level quadrature amplitude modulation (QAM), such as 16QAM, 32QAM, 64QAM, or even higher-order QAM, is commonly used. Constellation points in a signal constellation diagram corresponding to conventional QAM modulation appear with equal probability. Probabilistic constellation shaping (PCS) technology modifies the occurrence probability of constellation points without changing their positions, so that the constellation points are not uniformly distributed, improving system transmission performance. As a modulation format optimization technology, PCS technology has been widely studied and applied due to its advantages, such as approaching the Shannon limit and being flexible. Existing data processing and transmission methods using OFEC coding primarily use conventional QAM modulation, so they are not applicable to future scenarios where PCS technology is used. This is an issue that needs to be urgently addressed in the future. Summary of the Invention [Means for solving the problem]

[0005] The embodiments of the present application provide a data processing method and a data processing device for using FEC coding in combination with PCS technology for longer transmission distances, which makes the overall data processing operation simpler, less complex, and consumes less power, thus improving overall performance.

[0006] According to a first aspect, an embodiment of the present application provides a data processing method. The data processing method includes the following steps: performing PCS processing on a first bit set among the k bits to obtain a second bit set, where k is an integer greater than 1; performing FEC encoding on the second bit set and a third bit set among the k bits excluding the first bit set to obtain a fourth bit set, where the fourth bit set includes m0 first bit subsets, each of the first bit subsets including an F0 bit, where m0 is an integer greater than 1 and F0 is an even number greater than 1; and performing a first interleaving processing on the fourth bit set to obtain a fifth bit set, where the fifth bit set includes m0 second bit subsets, each of the second bit subsets including an F0 bit, an F0 / 2 bit in each of the second bit subsets is from the second bit set, and other F0 / 2 bits in each of the second bit subsets are from the third bit set and / or parity bits of the FEC encoding.

[0007] In this implementation, FEC coding is used in combination with PCS technology to meet the requirements for longer transmission distances for future urban telecommunications transmission and urban DCI interconnection scenarios. Due to the introduction of PCS processing, during symbol mapping, sign bits that are 0 and 1 must be mapped to a modulation symbol with equal probability, while amplitude bits that are 0 and 1 must be mapped to a modulation symbol with unequal probability. OFEC coding is used as an example of FEC coding. To avoid impact on existing OFEC coding and OFEC interleavers, a new interleaver must be introduced after OFEC coding and before the symbol mapping operation so that PCS-processed bits that are 0 and 1 with unequal probability can be mapped to the amplitude bits of a modulation symbol. In this way, to meet the requirements for future longer transmission distances and improve overall performance, the occurrence probabilities of constellation points are changed while the positions of the constellation points remain unchanged, so that the constellation points are not evenly distributed. Furthermore, it is simple to implement, has low complexity, and consumes little power.

[0008] In some possible implementations where the F0 bits in each of the second bit subsets are distributed into F1 rows and F1 columns, F1 / 2 bits of the F1 bits in each row of the second bit subset are from the second bit set, which includes m0×F0 / 2 bits, and the other F1 / 2 bits of the F1 bits in each row of the second bit subset are from a third bit set and / or parity bits of the FEC coding.

[0009] In some possible implementations, F0=256, F1=16, and the row i2 and column i3 of the second bit subset

number

number

[0010] In some possible implementations, F0=256, a total of m1×256 bits in the m1 first bit subsets in the fourth bit set are from the second bit set, and m0=m1×2.

[0011] In some possible implementations, F0=256, and m0×256 bits in the fourth bit set are distributed into 32 rows and m0×8 columns, and m0×256 bits in the fifth bit set are distributed into 32 rows and m0×8 columns, and m0×8 bits of row r1 in the fifth bit set are from m0×8 bits of row r0 in the fourth bit set, where 0≦r0<32 and 0≦r1<32.

[0012] In some possible implementations, the m0 first bit subsets are distributed across two rows and m1 columns, with the first bit subset in row 0 and column m2 being

number

number

[0013] In some possible implementations, the bit in the m0×8 bits of row r1 of the fifth bit set

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number

number

[0014] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

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[0015] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0016] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0017] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0018] In some possible implementations, the bit in the m0×8 bits of row r1 of the fifth bit set

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number

[0019] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0020] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0021] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0022] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0023] In some possible implementations, the step of performing FEC encoding on the second bit set and a third bit set among the k bits excluding the first bit set to obtain a fourth bit set includes the steps of performing pre-encoding interleaving on the second bit set and the third bit set to obtain a sixth bit set, wherein the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, and the sixth bit set includes m3 third bit subsets, the m3 third bit subsets being distributed in 2 rows and m4 columns, m3 = 2 × m4, m3 is an integer greater than 1 and less than m0, some third bit subsets each include F0 bits, and other third bit subsets each include F2 bits, where F2 is an even number greater than 1 and less than F0; and performing FEC encoding on the sixth bit set to obtain a fourth bit set.

[0024] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 to 5 includes 16 bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, the bits in the third bit subset in column 0, the third bit subset in column 1, the third bit subset in column 4, and the third bit subset in column 5 are from the second bit set, and the bits in the third bit subset in column 2, the third bit subset in column 3, and the third bit subset in column 6 are from the third bit set.

[0025] In some possible implementations, the m0 first bit subsets are distributed across two rows and m1 columns, where m0=16 and m1=8, and the first bit subset B in row 0 and column 0 is 0,0 , the first bit subset B at row 0 and column 1 0,1 , the first bit subset B at row 0 and column 4 0,4 , the first bit subset B at row 0 and column 5 0,5 , the first bit subset B at row 1 and column 0 1,0 , the first bit subset B in row 1 and column 1 1,1 , the first bit subset B in row 1 and column 4 1,4 , and the first bit subset B in row 1 and column 5 1,5 is from the second bit set.

[0026] In some possible implementations, the bit in the 128 bits of row r1 of the fifth bit set

number

number

number

[0027] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

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number

[0028] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

number

number

[0029] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0030] In some possible implementations, the bit in the 128 bits of row r1 of the fifth bit set

number

number

[0031] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0032] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0033] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0034] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0035] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 to 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, an F0 / 2 bit in each third bit subset in columns 0 to 3 is from the second bit set, the other F0 / 2 bits in each third bit subset in columns 0 to 3 are from the third bit set, an F0 bit in each third bit subset in columns 4 and 5 is from the second bit set, and an F2 bit in each third bit subset in column 6 is from the third bit set.

[0036] In some possible implementations, the third bit subset at row i0 and column j0 is

number

number

[0037] In some possible implementations, the m0 first bit subsets are distributed into two rows and m1 columns, m0=16, m1=8, and F0 / 2 bits in each first bit subset in columns 0 to 3 are from the second bit set, the other F0 / 2 bits in each first bit subset in columns 0 to 3 are from the third bit set, F0 bits in each first bit subset in columns 4 and 5 are from the second bit set, and F0 bits in each first bit subset in columns 6 and 7 are from the third bit set and / or parity bits of the FEC coding.

[0038] In some possible implementations, the step of performing a first interleaving process on the fourth set of bits to obtain a fifth set of bits includes performing a first interleaving process on a first subset of bits in columns 4 to 7 of the fourth set of bits to obtain a corresponding second subset of bits in columns 4 to 7 of the fifth set of bits.

[0039] In some possible implementations, the bit in the 128 bits of row r1 of the fifth bit set

number

number

number

[0040] In some possible implementations, when 0≦c1<64, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set, or when 64≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

number

number

number

number

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[0041] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 through 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, F0 / 2 bits in each third bit subset in columns 0 through 4 are from the second bit set, and another F0 / 2 bits in each third bit subset in columns 0 through 4 are from the third bit set, and third bit subset I in row 0 and column 5 0,5 , the third bit subset I at row 1 and column 5 1,5 , the third bit subset I at row 0 and column 6 0,6and a third subset of bits I in row 1 and column 6 1,6 The bits in columns 0 to 7 in are from the second bit set, and the third bit subset I at row 0 and column 6 0,6 and the third bit subset I in row 1 and column 6 1,6 The bits in columns 8 to 14 in are from the third bit set.

[0042] In some possible implementations, the third bit subset at row i0 and column j0 is

number

number

[0043] In some possible implementations, the m0 first bit subsets are distributed into two rows and m1 columns, m0=16, m1=8, F0 / 2 bits in each first bit subset in columns 0 through 4 are from the second bit set, and the other F0 / 2 bits in each first bit subset in columns 0 through 4 are from the third bit set, and the first bit subset B in row 0 and column 5 is 0,5 , the first bit subset B in row 1 and column 5 1,5 , the first bit subset B at row 0 and column 6 0,6 8×8 bits in rows 0 to 7 and columns 0 to 7 in the first bit subset B in row 0 and column 6 0,68×8 bits in rows 8 to 15 and columns 8 to 15 in the first bit subset B in row 1 and column 6 1,6 8×8 bits in rows 0 to 7 and columns 0 to 7 in the 1,6 8×8 bits in rows 8 to 15 and columns 8 to 15 in 0,7 , the first bit subset B in row 1 and column 7 1,7 , the first bit subset B at row 0 and column 6 0,6 8×8 bits in rows 0 to 7 and columns 8 to 15 in the first bit subset B in row 0 and column 6 0,6 8×8 bits in rows 8 to 15 and columns 0 to 7 in the first bit subset B in row 1 and column 6 1,6 8×8 bits in rows 0 to 7 and columns 8 to 15 in the 1,6 The 8x8 bits in rows 8 to 15 and columns 0 to 7 of are from the third bit set and / or parity bits of the FEC coding.

[0044] In some possible implementations, the step of performing a first interleaving process on the fourth set of bits to obtain a fifth set of bits includes performing a first interleaving process on a first subset of bits in columns 5 to 7 of the fourth set of bits to obtain a corresponding second subset of bits in columns 5 to 7 of the fifth set of bits.

[0045] In some possible implementations,

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number

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[0046] In some possible implementations, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set when 0≦c1<80, or bit c1 of the 128 bits of row r1 of the fifth bit set is from bit 80+c0 of the 128 bits of row r0 of the fourth bit set when 80≦c1<128;

number

number

number

number

[0047] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 to 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, an F0 / 2 bit in each third bit subset in columns 0 to 4 is from the second bit set, the other F0 / 2 bits in each third bit subset in columns 0 to 4 are from the third bit set, 9 bits in each row of each third bit subset in column 5 are from the second bit set, the other 7 bits in each row of each third bit subset in column 5 are from the third bit set, and an F2 bit in each third bit subset in column 6 is from the second bit set.

[0048] In some possible implementations, the m0 first bit subsets are distributed into two rows and m1 columns, where m0=16 and m1=8, and F0 / 2 bits in each first bit subset in columns 0 through 4 are from the second bit set, and the other F0 / 2 bits in each first bit subset in columns 0 through 4 are from the third bit set, and 9 bits in each row of each first bit subset in column 5 are from the second bit set, and 10 bits in each first bit subset in column 5 are from the third bit set. The other 7 bits in each row of the first bit subset in column 6 are from the third bit set, the bit in row i1 and column 15-i1 of each first bit subset in column 6 is from the parity bits of the FEC encoding, the remaining bits in each first bit subset in column 6 other than the bit in row i1 and column 15-i1 are from the second bit set, 0≦i1≦15, and the F0 bit in each first bit subset in column 7 is from the parity bits of the FEC encoding.

[0049] In some possible implementations, the step of performing a first interleaving operation on the fourth set of bits to obtain a fifth set of bits includes: 0,5 The second bit subset T in columns C to 15, row 0 and column 5 of 1,5 The second bit subset T in columns C to 15, row 0 and column 6 of 0,6 , the second bit subset T at row 0 and column 7 0,7 , the second bit subset T at row 1 and column 6 1,6 , and a second bit subset T at row 1 and column 6 1,6 To obtain the first bit subset B in row 0 and column 5, 0,5 The first bit subset B in columns C to 15, row 0 and column 5 of 1,5 The first bit subset B in columns C to 15, row 0 and column 6 of 0,6 , the first bit subset B at row 0 and column 7 0,7 , the first bit subset B in row 1 and column 6 1,6, and the first bit subset B at row 1 and column 6 1,6 , where 0≦C≦15.

[0050] In some possible implementations, r0=r1.

[0051] In some possible implementations, the F0 bits in each of the second bit subsets are distributed across F1 rows and F1 columns, and the F1 bits in each row of the second bit subsets are from the two first bit subsets.

[0052] In some possible implementations, the F0 bits in each first bit subset are distributed across F1 rows and F1 columns, F1 / 2 bits among the F1 bits in each row of the second bit subset are from one row of one first bit subset, and the other F1 / 2 bits among the F1 bits in each row of the second bit subset are from one row of another first bit subset.

[0053] In some possible implementations, F0=256, and the m0×256 bits of the fourth bit set are distributed into 32 rows and m0×8 columns, and the m0×256 bits of the fifth bit set are distributed into 32 rows and m0×8 columns, with 32 bits in each column of the fifth bit set coming from the two first bit subsets.

[0054] In some possible implementations, the 256 bits of each first bit subset are distributed into 16 rows and 16 columns, with 16 bits of the 32 bits in each column of the fifth bit subset coming from one column of one first bit subset, and the other 16 bits of the 32 bits in each column of the fifth bit subset coming from one column of another first bit subset.

[0055] In some possible implementations, 16 bits of the 32 bits in each column of the fifth bit set are from column c1%16 of one first bit subset, and the other 16 bits of the 32 bits in each column of the fifth bit set are from column c1%16 of another first bit subset, where 0≦c1<(m0×8).

[0056] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 1,2 and the first bit subset B at row 0 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0057] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0058] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 0 and column 1 0,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T at row 0 and column 3 0,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 0 and column 5 0,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 0 and column 7 0,7 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 1 and column 0 1,0 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, A second subset of bits T in row 1 and column 2 1,2 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5 is from a total of 512 bits, The second bit subset T in row 1 and column 4 1,4 and a second bit subset T at row 1 and column 5 1,5 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 1 and column 6 1,6 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7This is from a total of 512 bits.

[0059] In some possible implementations, the 16 second subset of bits are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0060] In some possible implementations, the 16 second subset of bits are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0061] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 0 and column 1 0,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T at row 0 and column 3 0,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 0 and column 5 0,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 0 and column 7 0,7A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 1 and column 0 1,0 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, A second subset of bits T in row 1 and column 2 1,2 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T in row 1 and column 4 1,4 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 1 and column 6 1,6 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 1,7 This is from a total of 512 bits.

[0062] In some possible implementations, m0=12 or 16.

[0063] In some possible implementations, after the step of performing a first interleaving process on the fourth bit set to obtain a fifth bit set, the method further includes the steps of: performing a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, where each first bit stream includes multiple fifth bit sets and L is an even number greater than 0; performing symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, where t bits are mapped to one dual-polarized symbol by the symbol mapping and polarization distribution, and t is an integer greater than 0; and performing digital signal processing (DSP) framing on the dual-polarized symbol stream.

[0064] In some possible implementations, the amplitude bits in the dual polarization symbols are from the second bit set.

[0065] In some possible implementations, t=8 and the dual polarization symbols are dual polarization DP-16QAM symbols.

[0066] In some possible implementations, the step of performing DSP framing on the dual-polarized symbol stream includes performing framing processing for every 172,032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, wherein the superframe includes 175,104 dual-polarized symbols.

[0067] According to a second aspect, the present application provides a data processing method, which includes the following steps: obtaining first data from a data frame, the first data including bits in r rows and q columns, where r is an integer greater than 0 and q is an integer greater than 0; and performing a cyclic redundancy check (CRC) and / or pad bit insertion on the first data to obtain second data, the second data being obtained by inserting d bits by the CRC. CRC parity bits and / or d PAD pad bits, d CRC is an integer greater than or equal to 0, and d PAD is an integer equal to or greater than 0; and scrambling the second data to obtain third data, wherein the number of bits of the third data is d scr =r×q+d CP and d CP =d CRC +d PAD and acquiring k bits of the third data, where k is an integer greater than 1, and d scr is an integer multiple of k; performing a stochastic constellation shaping PCS process on a first set of bits among the k bits to obtain a second set of bits; and performing FEC encoding on the second set of bits and a third set of bits among the k bits excluding the first set of bits to obtain a fourth set of bits.

[0068] In this implementation, for future urban telecommunication transmission and urban DCI interconnection scenarios, FEC coding is used in combination with PCS technology to meet the requirements of longer transmission distances. With the introduction of PCS processing, the length of information bits that are PCS processed and FEC coded is no longer 3552 but a smaller value. In this case, the number of rows of data obtained from the data frame needs to be redesigned, and the number of CRC checks and pad bits inserted needs to be redesigned so that the overall data processing operation becomes simpler, less complex, and consumes less power.

[0069] In some possible implementations, the step of performing FEC encoding on the second bit set and a third bit set among the k bits excluding the first bit set to obtain a fourth bit set includes the steps of performing pre-encoding interleaving on the second bit set and the third bit set to obtain a sixth bit set, wherein the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, and the sixth bit set includes m3 third bit subsets, the m3 third bit subsets being distributed in 2 rows and m4 columns, m3 = 2 × m4, m3 is an integer greater than 1 and less than m0, some third bit subsets each include F0 bits, and other third bit subsets each include F2 bits, where F2 is an even number greater than 1 and less than F0; and performing FEC encoding on the sixth bit set to obtain a fourth bit set.

[0070] In some possible implementations, the number of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

[0071] In some possible implementations, d scris an integer multiple of 4×k, and q=10280.

[0072] In some possible implementations, the overhead of CRC and / or padding bit insertion is (d CRC +d PAD ) / (r×q), and (d CRC +d PAD ) / (r×q)≦0.001.

[0073] In some possible implementations, r=79, d CP = 328, and k = 3224, r=83, d CP = 32, and k = 3386, r=83, d CP = 536, and k = 3388, r=87, d CP = 72, and k = 2662, r=87, d CP =744, and k=2664, r=87, d CP =3432, and k=2672, r=104, d CP = 704, and k = 3184, r=104, d CP = 3392, and k = 3192, r=105, d CP = 504, and k = 3214, r=105, d CP = 1176, and k = 3216, r=109, d CP = 40, and k = 2668, r=109, d CP = 880, and k = 2670, r=110, d CP = 176, and k = 3366, r=110, d CP =848, and k=3368, r=110, d CP = 3536, and k = 3376, r=111, d CP = 648, and k = 3398, r=131, d CP = 8, and k = 2672, r=131, d CP = 1016, and k = 2674, r=131, d CP = 680, and k = 3208, r=132, d CP = 480, and k = 3232, r=132, d CP = 1320, and k = 3234, r=137, d CP = 320, and k = 3354, r=137, d CP = 1160, and k = 3356, r=138, d CP = 120, and k = 3378, r=138, d CP = 960, and k = 3380, r=152, d CP = 344, and k = 2658, r=152, d CP = 1520, and k = 2660, r=153, d CP = 648, and k = 2676, r=157, d CP = 856, and k = 3204, r=158, d CP = 656, and k = 3224, r=165, d CP = 264, and k = 3366, r=165, d CP = 1272, and k = 3368, r=166, d CP = 64, and k = 3386, r=166, d CP = 1072, and k = 3388, r=174, d CP = 144, and k = 2662, r=174, d CP = 1488, and k = 2664, r=175, d CP= 616, and k = 2678, r=183, d CP = 360, and k = 3200, r=183, d CP = 1536, and k = 3202, r=184, d CP = 664, and k = 3218, r=184, d CP = 1840, and k = 3220, r=185, d CP =968, and k=3236, r=192, d CP =744, and k=3358, r=192, d CP = 1920, and k = 3360, r=193, d CP = 1048, and k = 3376, r=194, d CP = 176, and k = 3392, r=194, d CP = 1352, and k = 3394, r=196, d CP = 616, and k = 2666, r=209, d CP = 536, and k = 3198, r=209, d CP = 1880, and k = 3200, r=210, d CP = 1008, and k = 3214, r=211, d CP = 136, and k = 3228, r=211, d CP = 1480, and k = 3230, r=217, d CP = 280, and k = 2656, r=217, d CP = 1960, and k = 2658, r=218, d CP =80, and k=2668, r=218, d CP = 1760, and k = 2670, r=219, d CP = 1224, and k = 3352, r=220, d CP = 352, and k = 3366, r=220, d CP =1696, and k=3368, r=221, d CP =824, and k=3382, r=221, d CP = 2168, and k = 3384, r=222, d CP = 1296, and k = 3398, r=235, d CP = 376, and k = 3196, r=235, d CP =1888, and k=3198, r=236, d CP = 680, and k = 3210, r=236, d CP = 2192, and k = 3212, r=237, d CP = 984, and k = 3224, r=238, d CP =1288, and k=3238, r=239, d CP = 920, and k = 2660, r=240, d CP =1728, and k=2672, r=247, d CP = 1000, and k = 3360, r=247, d CP = 2512, and k = 3362, r=248, d CP = 1304, and k = 3374, r=249, d CP = 96, and k = 3386, r=249, d CP =1608, and k=3388, r=250, d CP = 400, and k = 3400, r=250, d CP= 1912, and k = 3402, r=261, d CP = 216, and k = 2662, r=261, d CP = 2232, and k = 2664, r=261, d CP = 1560, and k = 3196, r=262, d CP = 16, and k = 2672, r=262, d CP = 2032, and k = 2674, r=262, d CP = 1360, and k = 3208, r=263, d CP = 1160, and k = 3220, r=264, d CP = 960, and k = 3232, r=264, d CP = 2640, and k = 3234, r=274, d CP = 640, and k = 3354, r=274, d CP = 2320, and k = 3356, r=275, d CP = 440, and k = 3366, r=275, d CP = 2120, and k = 3368, r=276, d CP = 240, and k = 3378, r=276, d CP = 1920, and k = 3380, r=277, d CP = 40, and k = 3390, r=277, d CP = 1720, and k = 3392, r=283, d CP = 2032, and k = 2666, r=284, d CP = 488, and k = 2674, r=284, d CP = 2672, and k = 2676, r=287, d CP =896, and k=3194, r=287, d CP = 2744, and k = 3196, r=288, d CP = 1704, and k = 3206, r=289, d CP = 664, and k = 3216, r=289, d CP = 2512, and k = 3218, r=290, d CP = 1472, and k = 3228, r=291, d CP =432, and k=3238, r=291, d CP = 2280, and k = 3240, r=302, d CP = 80, and k = 3360, r=302, d CP =1928, and k=3362, r=303, d CP =888, and k=3372, r=303, d CP = 2736, and k = 3374, r=304, d CP = 688, and k = 2658, r=304, d CP = 3040, and k = 2660, r=304, d CP =1696, and k=3384, r=305, d CP = 2168, and k = 2668, r=305, d CP = 656, and k = 3394, r=305, d CP = 2504, and k = 3396, r=306, d CP = 1296, and k = 2676, r=313, d CP = 1912, and k = 3194, r=314, d CP= 1712, and k = 3204, r=315, d CP = 1512, and k = 3214, r=316, d CP = 1312, and k = 3224, r=317, d CP =1112, and k=3234, r=317, d CP = 3128, and k = 3236, r=326, d CP = 320, and k = 2660, r=326, d CP = 2840, and k = 2662, r=327, d CP = 120, and k = 2668, r=327, d CP = 2640, and k = 2670, r=328, d CP = 2440, and k = 2678, r=329, d CP =728, and k=3356, r=329, d CP = 2744, and k = 3358, r=330, d CP = 528, and k = 3366, r=330, d CP = 2544, and k = 3368, r=331, d CP = 328, and k = 3376, r=331, d CP = 2344, and k = 3378, r=332, d CP = 128, and k = 3386, r=332, d CP = 2144, and k = 3388, r=333, d CP =1944, and k=3398, r=339, d CP =744, and k=3192, r=339, d CP = 2928, and k = 3194, r=340, d CP = 1384, and k = 3202, r=341, d CP = 2024, and k = 3212, r=342, d CP = 480, and k = 3220, r=342, d CP = 2664, and k = 3222, r=343, d CP = 1120, and k = 3230, r=343, d CP = 3304, and k = 3232, r=344, d CP = 1760, and k = 3240, r=348, d CP = 288, and k = 2662, r=348, d CP = 2976, and k = 2664, r=349, d CP = 760, and k = 2670, r=349, d CP =3448, and k=2672, r=350, d CP = 1232, and k = 2678, r=356, d CP = 704, and k = 3352, r=356, d CP = 2888, and k = 3354, r=357, d CP = 1344, and k = 3362, r=357, d CP = 3528, and k = 3364, r=358, d CP = 1984, and k = 3372, r=359, d CP = 440, and k = 3380, r=359, d CP = 2624, and k = 3382, r=360, d CP =1080, and k=3390, r=360, d CP= 3264, and k = 3392, r=361, d CP = 1720, and k = 3400, r=365, d CP = 1592, and k = 3192, r=366, d CP = 720, and k = 3200, r=366, d CP = 3072, and k = 3202, r=367, d CP = 2200, and k = 3210, r=368, d CP =1328, and k=3218, r=368, d CP = 3680, and k = 3220, r=369, d CP = 2304, and k = 2658, r=369, d CP = 456, and k = 3226, r=369, d CP = 2808, and k = 3228, r=370, d CP =592, and k=2664, r=370, d CP =3448, and k=2666, r=370, d CP = 1936, and k = 3236, r=371, d CP = 1736, and k = 2672, r=384, d CP =1488, and k=3358, r=384, d CP = 3840, and k = 3360, r=385, d CP = 616, and k = 3366, r=385, d CP = 2968, and k = 3368, r=386, d CP = 2096, and k = 3376, r=387, d CP = 1224, and k = 3384, r=387, d CP = 3576, and k = 3386, r=388, d CP = 352, and k = 3392, r=388, d CP = 2704, and k = 3394, r=389, d CP =1832, and k=3402, r=391, d CP = 2440, and k = 2660, r=392, d CP = 1232, and k = 2666, r=392, d CP = 2240, and k = 3200, r=393, d CP = 24, and k = 2672, r=393, d CP = 3048, and k = 2674, r=393, d CP = 2040, and k = 3208, r=394, d CP = 1840, and k = 3216, r=395, d CP = 1640, and k = 3224, r=396, d CP = 1440, and k = 3232, r=396, d CP = 3960, and k = 3234, r=397, d CP = 1240, and k = 3240, r=397, d CP = 3760, and k = 3242, r=411, d CP = 960, and k = 3354, r=411, d CP = 3480, and k = 3356, r=412, d CP = 760, and k = 3362, r=412, d CP = 3280, and k = 3364, r=413, dCP = 2912, and k = 2662, r=413, d CP = 560, and k = 3370, r=413, d CP = 3080, and k = 3372, r=414, d CP = 2208, and k = 2668, r=414, d CP = 360, and k = 3378, r=414, d CP = 2880, and k = 3380, r=415, d CP = 1504, and k = 2674, r=415, d CP = 160, and k = 3386, r=415, d CP = 2680, and k = 3388, r=416, d CP = 2480, and k = 3396, r=418, d CP = 1072, and k = 3198, r=418, d CP = 3760, and k = 3200, r=419, d CP = 1544, and k = 3206, r=419, d CP = 4232, and k = 3208, r=420, d CP =2016, and k=3214, r=421, d CP = 2488, and k = 3222, r=422, d CP = 272, and k = 3228, r=422, d CP = 2960, and k = 3230, r=423, d CP =744, and k=3236, r=423, d CP = 3432, and k = 3238, r=434, d CP = 560, and k = 2656, r=434, d CP = 3920, and k = 2658, r=435, d CP = 360, and k = 2662, r=435, d CP = 3720, and k = 2664, r=436, d CP = 160, and k = 2668, r=436, d CP = 3520, and k = 2670, r=437, d CP = 3320, and k = 2676, r=438, d CP = 2448, and k = 3352, r=439, d CP = 232, and k = 3358, r=439, d CP = 2920, and k = 3360, r=440, d CP = 704, and k = 3366, r=440, d CP = 3392, and k = 3368, r=441, d CP = 1176, and k = 3374, r=441, d CP = 3864, and k = 3376, r=442, d CP =1648, and k=3382, r=442, d CP = 4336, and k = 3384, r=443, d CP = 2120, and k = 3390, r=444, d CP = 2424, and k = 3198, r=444, d CP = 2592, and k = 3398, r=445, d CP = 712, and k = 3204, r=445, d CP = 3568, and k = 3206, r=446, dCP = 1856, and k = 3212, r=447, d CP = 144, and k = 3218, r=447, d CP = 3000, and k = 3220, r=448, d CP = 1288, and k = 3226, r=448, d CP = 4144, and k = 3228, r=449, d CP = 2432, and k = 3234, r=456, d CP = 1032, and k = 2658, r=456, d CP = 4560, and k = 2660, r=457, d CP = 1336, and k = 2664, r=458, d CP = 1640, and k = 2670, r=459, d CP = 1944, and k = 2676, r=466, d CP =1888, and k=3356, r=466, d CP = 4744, and k = 3358, r=467, d CP = 176, and k = 3362, r=467, d CP = 3032, and k = 3364, r=468, d CP = 1320, and k = 3370, r=468, d CP = 4176, and k = 3372, r=469, d CP = 2464, and k = 3378, r=470, d CP = 752, and k = 3196, r=470, d CP = 3776, and k = 3198, r=470, d CP=752, and k=3384, r=470, d CP = 3608, and k = 3386, r=471, d CP = 2568, and k = 3204, r=471, d CP =1896, and k=3392, r=471, d CP = 4752, and k = 3394, r=472, d CP = 1360, and k = 3210, r=472, d CP = 4384, and k = 3212, r=472, d CP = 184, and k = 3398, r=472, d CP = 3040, and k = 3400, r=473, d CP = 152, and k = 3216, r=473, d CP = 3176, and k = 3218, r=474, d CP = 1968, and k = 3224, r=475, d CP = 760, and k = 3230, r=475, d CP = 3784, and k = 3232, r=476, d CP = 2576, and k = 3238, r=478, d CP = 1840, and k = 2660, r=479, d CP = 2648, and k = 2666, r=480, d CP = 3456, and k = 2672, r=481, d CP =568, and k=2676, r=481, d CP = 4264, and k = 2678, r=493, d CP = 184, and k = 3352, r=493, d CP = 3208, and k = 3354, r=494, d CP = 2000, and k = 3360, r=494, d CP = 5024, and k = 3362, r=495, d CP =792, and k=3366, r=495, d CP = 3816, and k = 3368, r=496, d CP = 1936, and k = 3196, r=496, d CP = 2608, and k = 3374, r=497, d CP = 1232, and k = 3202, r=497, d CP = 4424, and k = 3204, r=497, d CP = 1400, and k = 3380, r=497, d CP = 4424, and k = 3382, r=498, d CP = 528, and k = 3208, r=498, d CP = 3720, and k = 3210, r=498, d CP = 192, and k = 3386, r=498, d CP = 3216, and k = 3388, r=499, d CP = 1672, and k = 2656, r=499, d CP = 3016, and k = 3216, r=499, d CP = 2008, and k = 3394, r=499, d CP = 5032, and k = 3396, r=500, d CP = 2984, and k = 2662, r=500, d CP= 2312, and k = 3222, r=500, d CP = 800, and k = 3400, r=500, d CP = 3824, and k = 3402, r=501, d CP = 432, and k = 2666, r=501, d CP = 4296, and k = 2668, r=501, d CP =1608, and k=3228, r=501, d CP = 4800, and k = 3230, r=502, d CP = 1744, and k = 2672, r=502, d CP = 904, and k = 3234, r=502, d CP = 4096, and k = 3236, or r=503, d CP = 3056, and k = 2678.

[0074] In some possible implementations, d scr =336×k.

[0075] In some possible implementations, the step of performing a CRC on the first data comprises: performing a CRC-32 check on a total of r×q / p bits in each r / p rows of the first data and adding 32 parity bits; CRC = 32 × p, where r is divisible by p and p is an integer greater than 1, or The first r of the first data F0 ×(p-1)th row in r F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and then add the last r of the first data. F1 Total in rows q×r F1performing a CRC-32 check on the bits and adding 32 parity bits; CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and r F0 >r F1 and

number

[0076] In some possible implementations, q×r F0 =41120.

[0077] In some possible implementations, q=2056.

[0078] In some possible implementations, the step of performing a CRC on the first data includes performing a CRC on the first r F0 ×(p-1)th row in r F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and then add the last r of the first data. F1 Total in rows q×r F1 performing a CRC-32 check on the bits and adding 32 parity bits; CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and integer r F0 is an integer r F1 Bigger,

number

[0079] In some possible implementations, r=435.

[0080] In some possible implementations, p=22 and r F0 = 20, and r F1 =15, and performing a CRC on the first data includes performing a CRC-32 check on a total of 41,120 bits in every 20 rows of the first 420 rows of the first data to add 32 parity bits, and performing a CRC-32 check on a total of 30,840 bits in the last 15 rows of the first data to add 32 parity bits.

[0081] In some possible implementations, d CP = 3432 and k = 2672, or d CP = 744 and k = 2664.

[0082] In some possible implementations, r=546, d CP = 1008, and k = 3344, r=546, d CP = 3696, and k = 3352, r=547, d CP = 1640, and k = 3352, r=547, d CP = 4328, and k = 3360, r=548, d CP = 2272, and k = 3360, r=548, d CP = 4960, and k = 3368, r=549, d CP = 216, and k = 3360, r=549, d CP = 2904, and k = 3368, r=549, d CP = 5592, and k = 3376, r=550, d CP =848, and k=3368, r=550, d CP = 3536, and k = 3376, r=551, d CP = 1480, and k = 3376, r=551, d CP =4168, and k=3384, r=552, d CP = 2112, and k = 3384, r=552, d CP = 4800, and k = 3392, r=553, d CP = 56, and k = 3384, r=553, d CP = 2744, and k = 3392, r=553, d CP = 5432, and k = 3400, r=554, d CP = 688, and k = 3392, r=554, d CP = 3376, and k = 3400, r=555, d CP = 1320, and k = 3400, r=555, d CP = 4008, and k = 3408, r=556, d CP = 1952, and k = 3408, r=556, d CP = 4640, and k = 3416, r=557, d CP = 2584, and k = 3416, r=557, d CP =5272, and k=3424, r=558, d CP = 528, and k = 3416, r=558, d CP = 3216, and k = 3424, r=559, d CP = 1160, and k = 3424, r=559, d CP =3848, and k=3432, r=560, d CP = 1792, and k = 3432, r=560, d CP = 4480, and k = 3440, r=561, dCP = 2424, and k = 3440, r=561, d CP =5112, and k=3448, r=562, d CP = 368, and k = 3440, r=562, d CP = 3056, and k = 3448, or r=562, d CP = 5744, and k = 3456.

[0083] In some possible implementations, r=520, d CP = 704, and k = 3184, r=520, d CP = 3392, and k = 3192, r=520, d CP = 6080, and k = 3200, r=521, d CP = 1336, and k = 3192, r=521, d CP = 4024, and k = 3200, r=522, d CP = 1968, and k = 3200, r=522, d CP = 4656, and k = 3208, r=523, d CP = 2600, and k = 3208, r=523, d CP = 5288, and k = 3216, r=524, d CP = 544, and k = 3208, r=524, d CP = 3232, and k = 3216, r=525, d CP = 1176, and k = 3216, r=525, d CP = 3864, and k = 3224, r=526, d CP =1808, and k=3224, r=526, d CP = 4496, and k = 3232, r=527, d CP = 2440, and k = 3232, r=527, d CP =5128, and k=3240, r=528, d CP = 384, and k = 3232, r=528, d CP = 3072, and k = 3240, r=528, d CP =5760, and k=3248, r=529, d CP = 1016, and k = 3240, r=529, d CP = 3704, and k = 3248, r=530, d CP =1648, and k=3248, r=530, d CP = 4336, and k = 3256, r=531, d CP = 2280, and k = 3256, r=531, d CP =4968, and k=3264, r=532, d CP = 2912, and k = 3264, r=532, d CP = 224, and k = 3256, r=533, d CP =856, and k=3264, r=533, d CP = 3544, and k = 3272, r=534, d CP =1488, and k=3272, r=534, d CP = 4176, and k = 3280, r=535, d CP = 2120, and k = 3280, or r=535, d CP = 4808, and k = 3288.

[0084] In some possible implementations, after the step of performing FEC encoding on the second bit set and the third bit set to obtain a fourth bit set, the method includes the steps of performing a first interleaving operation on the fourth bit set to obtain a fifth bit set, wherein the fifth bit set includes m second bit subsets, each of the second bit subsets including 256 bits, 128 bits in each of the second bit subsets are from the second bit set, and the other 128 bits in each of the second bit subsets are from the third bit set and / or parity bits of the FEC encoding; and The method further includes the steps of: performing a second interleaving process on each of two first bit streams in the bit streams to obtain a total of L / 2 second bit streams, where each first bit stream includes multiple fifth bit sets, and L is an even number greater than 0; performing symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, where t bits are mapped to one dual-polarized symbol by the symbol mapping and polarization distribution, and t is an integer greater than 0; and performing DSP framing on the dual-polarized symbol stream.

[0085] In some possible implementations, the amplitude bits in the dual polarization symbols are from the second bit set.

[0086] In some possible implementations, t=8 and the dual polarization symbols are dual polarization DP-16QAM symbols.

[0087] In some possible implementations, the step of performing DSP framing on the dual-polarized symbol stream includes performing framing processing for every 172,032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, where the superframe includes 175,104 dual-polarized symbols.

[0088] In some possible implementations, the step of obtaining the first data from the data frame includes: Frame F from the data frame to get ×r×q bits Frame acquiring F pieces of first data; Frame is an integer greater than 0, and d scr ×F Frame =336×k×F DSP and F DSP represents the number of DSP superframes, and F DSP DSP superframes are Frame The first data is obtained by processing F DSP is an integer greater than 0, including steps.

[0089] In some possible implementations, F DSP >1 and F DSP A plurality of consecutive symbols in a first DSP superframe of the DSP superframes is a first marker, and F DSP A number of consecutive symbols in each of the DSP superframes except for the first DSP superframe are second markers.

[0090] According to a third aspect, an embodiment of the present application provides a data processing method, which includes the following steps: performing a first PCS process on a first set of bits in a first group of k bits to obtain a second set of bits, where the second set of bits includes m×128 bits, k is an integer greater than 1, and m is an integer greater than 1; performing a first FEC encoding on the second set of bits and a third set of bits in the first group of k bits excluding the first set of bits to obtain a fourth set of bits, where the fourth set of bits the set includes m0 first square blocks, each of the first square blocks including a total of 256 bits distributed in 16 rows and 16 columns; performing a second PCS process on a fifth set of bits in the second group of k bits to obtain a sixth set of bits; and performing a second FEC encoding on the sixth set of bits and a seventh set of bits in the second group of k bits excluding the fifth set of bits to obtain an eighth set of bits, wherein the eighth set of bits is inputting the 21 fourth bit sets and the 21 eighth bit sets into an interleaver buffer, the interleaver buffer including 84 rows and m1 columns, each of the second square blocks including a total of 256 bits, where m0=m1×2, and each of the buffer units is configured to buffer the total of 256 bits in 16 rows and 16 columns; a first square block of 42×m1 input into even rows of an interleaver buffer, and a second square block of 42×m1 input into odd rows of the interleaver buffer, the interleaver buffer including a first buffer subset and a second buffer subset, the first buffer subset including 42×m1 buffer units, the second buffer subset including 42×m1 buffer units, the bits input into the first buffer subset are from the second bit set and the sixth bit set, and the bits input into the second buffer subset arethe third bit set, the seventh bit set, the parity bits of the first FEC encoding, and the parity bits of the second FEC encoding; and performing symbol mapping and polarization distribution for each 8 bits in the interleaver buffer to obtain one dual-polarized DP-16QAM symbol, wherein two amplitude bits among the four bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction are from one column in the first buffer unit of the first buffer subset, and two code bits among the four bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction are from one column in the second buffer unit of the second buffer subset.

[0091] In this implementation, compared to the data processing method described in the first aspect, the data processing method provided in the third aspect of the present application provides a third interleaving process with similar complexity to the second interleaving process of the first aspect. The third interleaving process is implemented by using the interleaver buffer of the third aspect, and the buffer sizes used for the third interleaving process and the second interleaving process are similar or the same. This is equivalent to replacing the first interleaving process and the second interleaving process of the first aspect with the third interleaving process, achieving the same effect as the first aspect. Therefore, PCS-processed bits that become 0 and 1 with unequal probabilities can be mapped to amplitude bits of modulation symbols. To avoid uniform distribution of constellation points, the positions of the constellation points remain unchanged, but the occurrence probabilities of the constellation points are changed, improving overall performance to meet future requirements for longer transmission distances. In addition, the data processing method provided in the third aspect has lower complexity.

[0092] In some possible implementations, four of the eight bits are from one column in a first buffer unit of a first buffer subset, and the other four of the eight bits are from one column in a second buffer unit of a second buffer subset.

[0093] In some possible implementations, the m0 first square blocks are distributed into two rows and m1 columns, and the first square block at row 0 and column m2 and the first square block at row 1 and column m2 are from the second bit set; the m0 second square blocks are distributed into two rows and m1 columns, and the second square block at row 0 and column m2 and the second square block at row 1 and column m2 are from the sixth bit set; and 0≦m2 <m1 / 2である。

[0094] In some possible implementations, m0=16, and the first buffer subset includes a total of 336 buffer units in columns 0, 1, 2, and 3 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 4, 5, 6, and 7 of the interleaver buffer; or m0=12, and the first buffer subset includes a total of 252 buffer units in columns 0, 1, and 2 of the interleaver buffer, and the second buffer subset includes a total of 252 buffer units in columns 3, 4, and 5 of the interleaver buffer.

[0095] In some possible implementations, m0=16 and m1=8, and the m0 first square blocks are distributed into 2 rows and m1 columns, and the first square block at row 0 and column 0, the first square block at row 0 and column 1, the first square block at row 0 and column 4, the first square block at row 0 and column 5, the first square block at row 1 and column 0, the first square block at row 1 and column 1, the first square block at row 1 and column 4, and the first square block at row 1 and column 5 are and the m0 second square blocks are distributed into two rows and m1 columns, with the second square block at row 0 and column 0, the second square block at row 0 and column 1, the second square block at row 0 and column 4, the second square block at row 0 and column 5, the second square block at row 1 and column 0, the second square block at row 1 and column 1, the second square block at row 1 and column 4, and the second square block at row 1 and column 5 being from the sixth bit set.

[0096] In some possible implementations, the first buffer subset includes a total of 336 buffer units in columns 0, 1, 4, and 5 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 2, 3, 6, and 7 of the interleaver buffer.

[0097] According to a fourth aspect, an embodiment of the present application provides a data processing device, the data processing device including: a PCS unit, an FEC encoding unit, and a first interleaving processing unit. The PCS unit is configured to perform PCS processing on a first set of k bits to obtain a second set of bits, where k is an integer greater than 1. The FEC unit is configured to perform FEC encoding on the second set of bits and a third set of k bits excluding the first set of bits to obtain a fourth set of bits, the fourth set of bits including m0 first bit subsets, each of the first bit subsets including F0 bits, where m0 is an integer greater than 1 and F0 is an even number greater than 1. The first interleaving unit is configured to perform a first interleaving process on the fourth bit set to obtain a fifth bit set, the fifth bit set including m0 second bit subsets, each of the second bit subsets including an F0 bit, an F0 / 2 bit in each of the second bit subsets being from the second bit set, and other F0 / 2 bits in each of the second bit subsets being from the third bit set and / or parity bits of the FEC encoding.

[0098] In some possible implementations where the F0 bits in each of the second bit subsets are distributed into F1 rows and F1 columns, F1 / 2 bits of the F1 bits in each row of the second bit subset are from the second bit set, which includes m0×F0 / 2 bits, and the other F1 / 2 bits of the F1 bits in each row of the second bit subset are from a third bit set and / or parity bits of the FEC coding.

[0099] In some possible implementations, F0=256, F1=16, and the row i2 and column i3 of the second bit subset

number

number

[0100] In some possible implementations, F0=256, a total of m1×256 bits in the m1 first bit subsets in the fourth bit set are from the second bit set, and m0=m1×2.

[0101] In some possible implementations, F0=256, and m0×256 bits in the fourth bit set are distributed into 32 rows and m0×8 columns, and m0×256 bits in the fifth bit set are distributed into 32 rows and m0×8 columns, and m0×8 bits in row r1 in the fifth bit set are from m0×8 bits in row r0 in the fourth bit set, where 0≦r0<32 and 0≦r1<32.

[0102] In some possible implementations, the m0 first bit subsets are distributed across two rows and m1 columns, with the first bit subset in row 0 and column m2 being

number

number

[0103] In some possible implementations, the bit in the m0×8 bits of row r1 of the fifth bit set

number

number

number

[0104] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0105] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0106] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0107] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0108] In some possible implementations, the bit in the m0×8 bits of row r1 of the fifth bit set

number

number

[0109] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0110] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0111] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0112] In some possible implementations, bit c1 among the m0×8 bits of row r1 of the fifth bit set is from bit c0 among the m0×8 bits of row r0 of the fourth bit set;

number

number

[0113] In some possible implementations, the data processing apparatus further includes a pre-encoding interleaving unit configured to perform pre-encoding interleaving on the second bit set and the third bit set to obtain a sixth bit set, where a quantity of bits in the sixth bit set is equal to a sum of a quantity of bits in the second bit set and a quantity of bits in the third bit set, the sixth bit set includes m third bit subsets, the m third bit subsets are distributed into 2 rows and m columns, m=2×m, m is an integer greater than 1 and less than m, some third bit subsets each include F bits, and other third bit subsets each include F bits, where F is an even number greater than 1 and less than F, and the FEC unit is configured to perform FEC encoding on the sixth bit set to obtain a fourth bit set.

[0114] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 to 5 includes 16 bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, the bits in the third bit subset in column 0, the third bit subset in column 1, the third bit subset in column 4, and the third bit subset in column 5 are from the second bit set, and the bits in the third bit subset in column 2, the third bit subset in column 3, and the third bit subset in column 6 are from the third bit set.

[0115] In some possible implementations, the m0 first bit subsets are distributed across two rows and m1 columns, where m0=16 and m1=8, and the first bit subset B in row 0 and column 0 is 0,0 , the first bit subset B at row 0 and column 1 0,1 , the first bit subset B at row 0 and column 4 0,4 , the first bit subset B at row 0 and column 5 0,5 , the first bit subset B at row 1 and column 0 1,0 , the first bit subset B in row 1 and column 1 1,1 , the first bit subset B in row 1 and column 4 1,4 , and the first bit subset B in row 1 and column 5 1,5 is from the second bit set.

[0116] In some possible implementations, the bit in the 128 bits of row r1 of the fifth bit set

number

number

number

[0117] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0118] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0119] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0120] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0121] In some possible implementations, the bit in the 128 bits of row r1 of the fifth bit set

number

number

[0122] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0123] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0124] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0125] In some possible implementations, bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set;

number

number

[0126] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 to 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, an F0 / 2 bit in each third bit subset in columns 0 to 3 is from the second bit set, the other F0 / 2 bits in each third bit subset in columns 0 to 3 are from the third bit set, an F0 bit in each third bit subset in columns 4 and 5 is from the second bit set, and an F2 bit in each third bit subset in column 6 is from the third bit set.

[0127] In some possible implementations, the third subset of bits in row i0 and column j0 is

number

number

[0128] In some possible implementations, the m0 first bit subsets are distributed into two rows and m1 columns, m0=16, m1=8, and F0 / 2 bits in each first bit subset in columns 0 to 3 are from the second bit set, the other F0 / 2 bits in each first bit subset in columns 0 to 3 are from the third bit set, F0 bits in each first bit subset in columns 4 and 5 are from the second bit set, and F0 bits in each first bit subset in columns 6 and 7 are from the third bit set and / or parity bits of the FEC coding.

[0129] In some possible implementations, the first interleaving processing unit is specifically configured to perform a first interleaving process on a first subset of bits in columns 4 to 7 of the fourth bit set to obtain a corresponding second subset of bits in columns 4 to 7 of the fifth bit set.

[0130] In some possible implementations, the bit in the 128 bits of row r1 of the fifth bit set

number

number

number

[0131] In some possible implementations, when 0≦c1<64, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set, or when 64≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

number

number

number

number

number

number

number

number

[0132] In some possible implementations, m3=14, m4=7, F0=256, F2=240, each third bit subset in columns 0 through 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, F0 / 2 bits in each third bit subset in columns 0 through 4 are from the second bit set, and the other F0 / 2 bits in each third bit subset in columns 0 through 4 are from the third bit set, and third bit subset I in row 0 and column 5 0,5 , the third bit subset I at row 1 and column 5 1,5, the third bit subset I at row 0 and column 6 0,6 and a third subset of bits I in row 1 and column 6 1,6 The bits in columns 0 to 7 in are from the second bit set, and the third bit subset I at row 0 and column 6 0,6 and the third bit subset I in row 1 and column 6 1,6 The bits in columns 8 to 14 in are from the third bit set.

[0133] In some possible implementations, the third subset of bits in row i0 and column j0 is

number

number

[0134] In some possible implementations, the m0 first bit subsets are distributed into two rows and m1 columns, m0=16, m1=8, F0 / 2 bits in each first bit subset in columns 0 through 4 are from the second bit set, and the other F0 / 2 bits in each first bit subset in columns 0 through 4 are from the third bit set, and the first bit subset B in row 0 and column 5 is 0,5 , the first bit subset B in row 1 and column 5 1,5 , the first bit subset B at row 0 and column 6 0,68×8 bits in rows 0 to 7 and columns 0 to 7 in the first bit subset B in row 0 and column 6 0,6 8×8 bits in rows 8 to 15 and columns 8 to 15 in the first bit subset B in row 1 and column 6 1,6 8×8 bits in rows 0 to 7 and columns 0 to 7 in the 1,6 8×8 bits in rows 8 to 15 and columns 8 to 15 in 0,7 , the first bit subset B in row 1 and column 7 1,7 , the first bit subset B at row 0 and column 6 0,6 8×8 bits in rows 0 to 7 and columns 8 to 15 in the first bit subset B in row 0 and column 6 0,6 8×8 bits in rows 8 to 15 and columns 0 to 7 in the first bit subset B in row 1 and column 6 1,6 8×8 bits in rows 0 to 7 and columns 8 to 15 in the 1,6 The 8x8 bits in rows 8 to 15 and columns 0 to 7 of are from the third bit set and / or parity bits of the FEC coding.

[0135] In some possible implementations, the first interleaving processing unit is specifically configured to perform a first interleaving process on a first subset of bits in columns 5 to 7 of the fourth bit set to obtain a corresponding second subset of bits in columns 5 to 7 of the fifth bit set.

[0136] In some possible implementations,

number

number

number

number

number

number

number

[0137] In some possible implementations, when 0≦c1<80, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set, or when 80≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from 80+c0 of the 128 bits of row r0 of the fourth bit set;

number

number

number

number

[0138] In some possible implementations, m3 = 14, m4 = 7, F0 = 256, F2 = 240, each third bit subset in columns 0 to 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, F0 / 2 bits in each third bit subset in columns 0 to 4 are from the second bit set, the other F0 / 2 bits in each third bit subset in columns 0 to 4 are from the third bit set, 9 bits in each row of each third bit subset in column 5 are from the second bit set, the other 7 bits in each row of each third bit subset in column 5 are from the third bit set, and the F2 bit in each third bit subset in column 6 is from the second bit set.

[0139] In some possible implementations, the m0 first bit subsets are distributed into two rows and m1 columns, m0=16, m1=8, F0 / 2 bits in each first bit subset in columns 0 through 4 are from the second bit set, the other F0 / 2 bits in each first bit subset in columns 0 through 4 are from the third bit set, 9 bits in each row of each first bit subset in column 5 are from the second bit set, and each first bit in column 5 is from the third bit set. The other 7 bits in each row of the subset are from the third bit set, the bit in row i1 and column 15-i1 of each first bit subset in column 6 is from the parity bit of the FEC encoding, the remaining bits other than the bit in row i1 and column 15-i1 of each first bit subset in column 6 are from the second bit set, 0≦i1≦15, and the F0 bit in each first bit subset in column 7 is from the parity bit of the FEC encoding.

[0140] In some possible implementations, the first interleaving unit specifically interleaves the second bit subset T 0,5 The second bit subset T in columns C to 15, row 0 and column 5 of 1,5 The second bit subset T in columns C to 15, row 0 and column 6 of 0,6 , the second bit subset T at row 0 and column 7 0,7 , the second bit subset T at row 1 and column 6 1,6 , and a second bit subset T at row 1 and column 6 1,6 To obtain the first bit subset B in row 0 and column 5, 0,5 The first bit subset B in columns C to 15, row 0 and column 5 of 1,5 The first bit subset B in columns C to 15, row 0 and column 6 of 0,6 , the first bit subset B at row 0 and column 7 0,7 , the first bit subset B in row 1 and column 6 1,6, and the first bit subset B at row 1 and column 6 1,6 , where 0≦C≦15.

[0141] In some possible implementations, r0=r1.

[0142] In some possible implementations, the F0 bits in each of the second bit subsets are distributed across F1 rows and F1 columns, and the F1 bits in each row of the second bit subsets are from the two first bit subsets.

[0143] In some possible implementations, the F0 bits in each first bit subset are distributed across F1 rows and F1 columns, F1 / 2 bits among the F1 bits in each row of the second bit subset are from one row of one first bit subset, and the other F1 / 2 bits among the F1 bits in each row of the second bit subset are from one row of another first bit subset.

[0144] In some possible implementations, F0=256, and the m0×256 bits of the fourth bit set are distributed into 32 rows and m0×8 columns, and the m0×256 bits of the fifth bit set are distributed into 32 rows and m0×8 columns, with 32 bits in each column of the fifth bit set coming from the two first bit subsets.

[0145] In some possible implementations, the 256 bits in each first bit subset are distributed into 16 rows and 16 columns, with 16 bits of the 32 bits in each column of the fifth bit subset coming from one column of one first bit subset, and the other 16 bits of the 32 bits in each column of the fifth bit subset coming from one column of another first bit subset.

[0146] In some possible implementations, 16 bits of the 32 bits in each column of the fifth bit set are from column c1%16 of one first bit subset, and the other 16 bits of the 32 bits in each column of the fifth bit set are from column c1%16 of another first bit subset, where 0≦c1<(m0×8).

[0147] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0148] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0149] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 0 and column 1 0,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T at row 0 and column 3 0,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 0 and column 5 0,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 0 and column 7 0,7 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 1 and column 0 1,0 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, A second subset of bits T in row 1 and column 2 1,2 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5 is from a total of 512 bits, The second bit subset T in row 1 and column 4 1,4 and a second bit subset T at row 1 and column 5 1,5 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 1 and column 6 1,6 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7This is from a total of 512 bits.

[0150] In some possible implementations, the 16 second subset of bits are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0151] In some possible implementations, the 16 second subset of bits are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0152] In some possible implementations, m=16, and the 16 second bit subsets are distributed across 2 rows and 8 columns; The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 0 and column 1 0,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T at row 0 and column 3 0,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 0 and column 5 0,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 0 and column 7 0,7A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 1 and column 0 1,0 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, A second subset of bits T in row 1 and column 2 1,2 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T in row 1 and column 4 1,4 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 1 and column 6 1,6 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0153] In some possible implementations, m0=12 or 16.

[0154] In some possible implementations, the data processing device further includes a second interleaving processing unit, a symbol mapping unit, a polarization distribution unit, and a DSP framing unit, wherein the second interleaving processing unit is configured to perform second interleaving processing on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, each first bit stream including a plurality of fifth bit sets, where L is an even number greater than 0, the symbol mapping unit and polarization distribution unit is configured to perform symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, where t bits are mapped to one dual-polarized symbol by the symbol mapping and polarization distribution, where t is an integer greater than 0, and the DSP framing unit is configured to perform DSP framing on the dual-polarized symbol stream.

[0155] In some possible implementations, the amplitude bits in the dual polarization symbols are from the second bit set.

[0156] In some possible implementations, t=8 and the dual polarization symbols are dual polarization DP-16QAM symbols.

[0157] In some possible implementations, the DSP framing unit is specifically configured to perform framing processing every 172032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, where the superframe includes 175104 dual-polarized symbols.

[0158] According to a fifth aspect, an embodiment of the present application provides a data processing device, the data processing device includes: a first processing unit, a second processing unit, a scrambling unit, a third processing unit, a PCS unit, and an FEC encoding unit, the first processing unit is configured to obtain first data from a data frame, the first data including bits in r rows and q columns, r being an integer greater than 0 and q being an integer greater than 0; the second processing unit is configured to perform a cyclic redundancy check (CRC) and / or pad bit insertion on the first data to obtain second data, the second data including bits inserted by the CRC. CRC parity bits and / or d PAD pad bits, d CRC is an integer greater than or equal to 0, and d PAD is an integer equal to or greater than 0, and the scrambling unit is configured to scramble the second data to obtain third data, and the number of bits of the third data is d scr =r×q+d CP and d CP =d CRC +d PAD and the third processing unit is configured to obtain k bits in the third data, where k is an integer greater than 1; and scr is an integer multiple of k, the PCS unit is configured to perform PCS processing on a first bit set among the k bits to obtain a second bit set, and the FEC unit is configured to perform FEC encoding on the second bit set and a third bit set among the k bits excluding the first bit set to obtain a fourth bit set.

[0159] In some possible implementations, the data processing apparatus further includes a pre-encoding interleaving unit configured to perform pre-encoding interleaving on the second bit set and the third bit set to obtain a sixth bit set, wherein the number of bits in the sixth bit set is equal to the sum of the number of bits in the second bit set and the number of bits in the third bit set, wherein the sixth bit set includes m3 third bit subsets, the m3 third bit subsets being distributed in 2 rows and m4 columns, m3 = 2 × m4, m3 is an integer greater than 1 and less than m0, some third bit subsets each include F0 bits, and other third bit subsets each include F2 bits, wherein F2 is an even number greater than 1 and less than F0, and the FEC unit is configured to perform FEC encoding on the sixth bit set to obtain a fourth bit set.

[0160] In some possible implementations, the number of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

[0161] In some possible implementations, d scr is an integer multiple of 4×k, and q=10280.

[0162] In some possible implementations, the overhead of CRC and / or padding bit insertion is (d CRC +d PAD ) / (r×q), and (d CRC +d PAD ) / (r×q)≦0.001.

[0163] In some possible implementations, r=79, d CP = 328, and k = 3224, r=83, d CP = 32, and k = 3386, r=83, d CP= 536, and k = 3388, r=87, d CP = 72, and k = 2662, r=87, d CP =744, and k=2664, r=87, d CP =3432, and k=2672, r=104, d CP = 704, and k = 3184, r=104, d CP = 3392, and k = 3192, r=105, d CP = 504, and k = 3214, r=105, d CP = 1176, and k = 3216, r=109, d CP = 40, and k = 2668, r=109, d CP = 880, and k = 2670, r=110, d CP = 176, and k = 3366, r=110, d CP =848, and k=3368, r=110, d CP = 3536, and k = 3376, r=111, d CP = 648, and k = 3398, r=131, d CP = 8, and k = 2672, r=131, d CP = 1016, and k = 2674, r=131, d CP = 680, and k = 3208, r=132, d CP = 480, and k = 3232, r=132, d CP = 1320, and k = 3234, r=137, d CP = 320, and k = 3354, r=137, d CP = 1160, and k = 3356, r=138, dCP = 120, and k = 3378, r=138, d CP = 960, and k = 3380, r=152, d CP = 344, and k = 2658, r=152, d CP = 1520, and k = 2660, r=153, d CP = 648, and k = 2676, r=157, d CP = 856, and k = 3204, r=158, d CP = 656, and k = 3224, r=165, d CP = 264, and k = 3366, r=165, d CP = 1272, and k = 3368, r=166, d CP = 64, and k = 3386, r=166, d CP = 1072, and k = 3388, r=174, d CP = 144, and k = 2662, r=174, d CP = 1488, and k = 2664, r=175, d CP = 616, and k = 2678, r=183, d CP = 360, and k = 3200, r=183, d CP = 1536, and k = 3202, r=184, d CP = 664, and k = 3218, r=184, d CP = 1840, and k = 3220, r=185, d CP =968, and k=3236, r=192, d CP =744, and k=3358, r=192, d CP = 1920, and k = 3360, r=193, d CP = 1048, and k = 3376, r=194, d CP = 176, and k = 3392, r=194, d CP = 1352, and k = 3394, r=196, d CP = 616, and k = 2666, r=209, d CP = 536, and k = 3198, r=209, d CP = 1880, and k = 3200, r=210, d CP = 1008, and k = 3214, r=211, d CP = 136, and k = 3228, r=211, d CP = 1480, and k = 3230, r=217, d CP = 280, and k = 2656, r=217, d CP = 1960, and k = 2658, r=218, d CP =80, and k=2668, r=218, d CP = 1760, and k = 2670, r=219, d CP = 1224, and k = 3352, r=220, d CP = 352, and k = 3366, r=220, d CP =1696, and k=3368, r=221, d CP =824, and k=3382, r=221, d CP = 2168, and k = 3384, r=222, d CP = 1296, and k = 3398, r=235, d CP = 376, and k = 3196, r=235, d CP=1888, and k=3198, r=236, d CP = 680, and k = 3210, r=236, d CP = 2192, and k = 3212, r=237, d CP = 984, and k = 3224, r=238, d CP =1288, and k=3238, r=239, d CP = 920, and k = 2660, r=240, d CP =1728, and k=2672, r=247, d CP = 1000, and k = 3360, r=247, d CP = 2512, and k = 3362, r=248, d CP = 1304, and k = 3374, r=249, d CP = 96, and k = 3386, r=249, d CP =1608, and k=3388, r=250, d CP = 400, and k = 3400, r=250, d CP = 1912, and k = 3402, r=261, d CP = 216, and k = 2662, r=261, d CP = 2232, and k = 2664, r=261, d CP = 1560, and k = 3196, r=262, d CP = 16, and k = 2672, r=262, d CP = 2032, and k = 2674, r=262, d CP = 1360, and k = 3208, r=263, d CP = 1160, and k = 3220, r=264, d CP = 960, and k = 3232, r=264, d CP = 2640, and k = 3234, r=274, d CP = 640, and k = 3354, r=274, d CP = 2320, and k = 3356, r=275, d CP = 440, and k = 3366, r=275, d CP = 2120, and k = 3368, r=276, d CP = 240, and k = 3378, r=276, d CP = 1920, and k = 3380, r=277, d CP = 40, and k = 3390, r=277, d CP = 1720, and k = 3392, r=283, d CP = 2032, and k = 2666, r=284, d CP = 488, and k = 2674, r=284, d CP = 2672, and k = 2676, r=287, d CP =896, and k=3194, r=287, d CP = 2744, and k = 3196, r=288, d CP = 1704, and k = 3206, r=289, d CP = 664, and k = 3216, r=289, d CP = 2512, and k = 3218, r=290, d CP = 1472, and k = 3228, r=291, d CP =432, and k=3238, r=291, d CP= 2280, and k = 3240, r=302, d CP = 80, and k = 3360, r=302, d CP =1928, and k=3362, r=303, d CP =888, and k=3372, r=303, d CP = 2736, and k = 3374, r=304, d CP = 688, and k = 2658, r=304, d CP = 3040, and k = 2660, r=304, d CP =1696, and k=3384, r=305, d CP = 2168, and k = 2668, r=305, d CP = 656, and k = 3394, r=305, d CP = 2504, and k = 3396, r=306, d CP = 1296, and k = 2676, r=313, d CP = 1912, and k = 3194, r=314, d CP = 1712, and k = 3204, r=315, d CP = 1512, and k = 3214, r=316, d CP = 1312, and k = 3224, r=317, d CP =1112, and k=3234, r=317, d CP = 3128, and k = 3236, r=326, d CP = 320, and k = 2660, r=326, d CP = 2840, and k = 2662, r=327, d CP = 120, and k = 2668, r=327, d CP = 2640, and k = 2670, r=328, d CP = 2440, and k = 2678, r=329, d CP =728, and k=3356, r=329, d CP = 2744, and k = 3358, r=330, d CP = 528, and k = 3366, r=330, d CP = 2544, and k = 3368, r=331, d CP = 328, and k = 3376, r=331, d CP = 2344, and k = 3378, r=332, d CP = 128, and k = 3386, r=332, d CP = 2144, and k = 3388, r=333, d CP =1944, and k=3398, r=339, d CP =744, and k=3192, r=339, d CP = 2928, and k = 3194, r=340, d CP = 1384, and k = 3202, r=341, d CP = 2024, and k = 3212, r=342, d CP = 480, and k = 3220, r=342, d CP = 2664, and k = 3222, r=343, d CP = 1120, and k = 3230, r=343, d CP = 3304, and k = 3232, r=344, d CP = 1760, and k = 3240, r=348, d CP= 288, and k = 2662, r=348, d CP = 2976, and k = 2664, r=349, d CP = 760, and k = 2670, r=349, d CP =3448, and k=2672, r=350, d CP = 1232, and k = 2678, r=356, d CP = 704, and k = 3352, r=356, d CP = 2888, and k = 3354, r=357, d CP = 1344, and k = 3362, r=357, d CP = 3528, and k = 3364, r=358, d CP = 1984, and k = 3372, r=359, d CP = 440, and k = 3380, r=359, d CP = 2624, and k = 3382, r=360, d CP =1080, and k=3390, r=360, d CP = 3264, and k = 3392, r=361, d CP = 1720, and k = 3400, r=365, d CP = 1592, and k = 3192, r=366, d CP = 720, and k = 3200, r=366, d CP = 3072, and k = 3202, r=367, d CP = 2200, and k = 3210, r=368, d CP =1328, and k=3218, r=368, d CP = 3680, and k = 3220, r=369, d CP = 2304, and k = 2658, r=369, d CP = 456, and k = 3226, r=369, d CP = 2808, and k = 3228, r=370, d CP =592, and k=2664, r=370, d CP =3448, and k=2666, r=370, d CP = 1936, and k = 3236, r=371, d CP = 1736, and k = 2672, r=384, d CP =1488, and k=3358, r=384, d CP = 3840, and k = 3360, r=385, d CP = 616, and k = 3366, r=385, d CP = 2968, and k = 3368, r=386, d CP = 2096, and k = 3376, r=387, d CP = 1224, and k = 3384, r=387, d CP = 3576, and k = 3386, r=388, d CP = 352, and k = 3392, r=388, d CP = 2704, and k = 3394, r=389, d CP =1832, and k=3402, r=391, d CP = 2440, and k = 2660, r=392, d CP = 1232, and k = 2666, r=392, d CP = 2240, and k = 3200, r=393, dCP = 24, and k = 2672, r=393, d CP = 3048, and k = 2674, r=393, d CP = 2040, and k = 3208, r=394, d CP = 1840, and k = 3216, r=395, d CP = 1640, and k = 3224, r=396, d CP = 1440, and k = 3232, r=396, d CP = 3960, and k = 3234, r=397, d CP = 1240, and k = 3240, r=397, d CP = 3760, and k = 3242, r=411, d CP = 960, and k = 3354, r=411, d CP = 3480, and k = 3356, r=412, d CP = 760, and k = 3362, r=412, d CP = 3280, and k = 3364, r=413, d CP = 2912, and k = 2662, r=413, d CP = 560, and k = 3370, r=413, d CP = 3080, and k = 3372, r=414, d CP = 2208, and k = 2668, r=414, d CP = 360, and k = 3378, r=414, d CP = 2880, and k = 3380, r=415, d CP = 1504, and k = 2674, r=415, d CP = 160, and k = 3386, r=415, d CP = 2680, and k = 3388, r=416, d CP = 2480, and k = 3396, r=418, d CP = 1072, and k = 3198, r=418, d CP = 3760, and k = 3200, r=419, d CP = 1544, and k = 3206, r=419, d CP = 4232, and k = 3208, r=420, d CP =2016, and k=3214, r=421, d CP = 2488, and k = 3222, r=422, d CP = 272, and k = 3228, r=422, d CP = 2960, and k = 3230, r=423, d CP =744, and k=3236, r=423, d CP = 3432, and k = 3238, r=434, d CP = 560, and k = 2656, r=434, d CP = 3920, and k = 2658, r=435, d CP = 360, and k = 2662, r=435, d CP = 3720, and k = 2664, r=436, d CP = 160, and k = 2668, r=436, d CP = 3520, and k = 2670, r=437, d CP = 3320, and k = 2676, r=438, d CP = 2448, and k = 3352, r=439, dCP = 232, and k = 3358, r=439, d CP = 2920, and k = 3360, r=440, d CP = 704, and k = 3366, r=440, d CP = 3392, and k = 3368, r=441, d CP = 1176, and k = 3374, r=441, d CP = 3864, and k = 3376, r=442, d CP =1648, and k=3382, r=442, d CP = 4336, and k = 3384, r=443, d CP = 2120, and k = 3390, r=444, d CP = 2424, and k = 3198, r=444, d CP = 2592, and k = 3398, r=445, d CP = 712, and k = 3204, r=445, d CP = 3568, and k = 3206, r=446, d CP = 1856, and k = 3212, r=447, d CP = 144, and k = 3218, r=447, d CP = 3000, and k = 3220, r=448, d CP = 1288, and k = 3226, r=448, d CP = 4144, and k = 3228, r=449, d CP = 2432, and k = 3234, r=456, d CP = 1032, and k = 2658, r=456, d CP= 4560, and k = 2660, r=457, d CP = 1336, and k = 2664, r=458, d CP = 1640, and k = 2670, r=459, d CP = 1944, and k = 2676, r=466, d CP =1888, and k=3356, r=466, d CP = 4744, and k = 3358, r=467, d CP = 176, and k = 3362, r=467, d CP = 3032, and k = 3364, r=468, d CP = 1320, and k = 3370, r=468, d CP = 4176, and k = 3372, r=469, d CP = 2464, and k = 3378, r=470, d CP = 752, and k = 3196, r=470, d CP = 3776, and k = 3198, r=470, d CP =752, and k=3384, r=470, d CP = 3608, and k = 3386, r=471, d CP = 2568, and k = 3204, r=471, d CP =1896, and k=3392, r=471, d CP = 4752, and k = 3394, r=472, d CP = 1360, and k = 3210, r=472, d CP = 4384, and k = 3212, r=472, d CP = 184, and k = 3398, r=472, d CP = 3040, and k = 3400, r=473, d CP = 152, and k = 3216, r=473, d CP = 3176, and k = 3218, r=474, d CP = 1968, and k = 3224, r=475, d CP = 760, and k = 3230, r=475, d CP = 3784, and k = 3232, r=476, d CP = 2576, and k = 3238, r=478, d CP = 1840, and k = 2660, r=479, d CP = 2648, and k = 2666, r=480, d CP = 3456, and k = 2672, r=481, d CP =568, and k=2676, r=481, d CP = 4264, and k = 2678, r=493, d CP = 184, and k = 3352, r=493, d CP = 3208, and k = 3354, r=494, d CP = 2000, and k = 3360, r=494, d CP = 5024, and k = 3362, r=495, d CP =792, and k=3366, r=495, d CP = 3816, and k = 3368, r=496, d CP = 1936, and k = 3196, r=496, d CP = 2608, and k = 3374, r=497, dCP = 1232, and k = 3202, r=497, d CP = 4424, and k = 3204, r=497, d CP = 1400, and k = 3380, r=497, d CP = 4424, and k = 3382, r=498, d CP = 528, and k = 3208, r=498, d CP = 3720, and k = 3210, r=498, d CP = 192, and k = 3386, r=498, d CP = 3216, and k = 3388, r=499, d CP = 1672, and k = 2656, r=499, d CP = 3016, and k = 3216, r=499, d CP = 2008, and k = 3394, r=499, d CP = 5032, and k = 3396, r=500, d CP = 2984, and k = 2662, r=500, d CP = 2312, and k = 3222, r=500, d CP = 800, and k = 3400, r=500, d CP = 3824, and k = 3402, r=501, d CP = 432, and k = 2666, r=501, d CP = 4296, and k = 2668, r=501, d CP =1608, and k=3228, r=501, d CP = 4800, and k = 3230, r=502, d CP= 1744, and k = 2672, r=502, d CP = 904, and k = 3234, r=502, d CP = 4096, and k = 3236, or r=503, d CP = 3056, and k = 2678.

[0164] In some possible implementations, d scr =336×k.

[0165] In some possible implementations, the second data processing unit is specifically configured to perform a CRC-32 check on a total of r×q / p bits in each r / p rows of the first data, and add 32 parity bits; and CRC = 32 × p, r is divisible by p, and p is an integer greater than 1, or the first r of the first data F0 ×(p-1)th row in r F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and then add the last r of the first data. F1 Total in rows q×r F1 configured to perform a CRC-32 check on the bits and add 32 parity bits, CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and r F0 >r F1 and

number

[0166] In some possible implementations, q×r F0 =41120.

[0167] In some possible implementations, q=2056.

[0168] In some possible implementations, the second data processing unit specifically processes the first r F0 ×(p-1)th row in r F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and then add the last r of the first data. F1 Total in rows q×r F1 configured to perform a CRC-32 check on the bits and add 32 parity bits, CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and integer r F0 is an integer r F1 Bigger,

number

[0169] In some possible implementations, r=435.

[0170] In some possible implementations, p=22 and r F0 = 20, and r F1 =15, and the second data processing unit is specifically configured to perform a CRC-32 check on a total of 41,120 bits in every 20 rows of the first 420 rows of the first data to add 32 parity bits, and to perform a CRC-32 check on a total of 30,840 bits in the last 15 rows of the first data to add 32 parity bits.

[0171] In some possible implementations, d CP = 3432 and k = 2672, or d CP = 744 and k = 2664.

[0172] In some possible implementations, r=546, dCP = 1008, and k = 3344, r=546, d CP = 3696, and k = 3352, r=547, d CP = 1640, and k = 3352, r=547, d CP = 4328, and k = 3360, r=548, d CP = 2272, and k = 3360, r=548, d CP = 4960, and k = 3368, r=549, d CP = 216, and k = 3360, r=549, d CP = 2904, and k = 3368, r=549, d CP = 5592, and k = 3376, r=550, d CP =848, and k=3368, r=550, d CP = 3536, and k = 3376, r=551, d CP = 1480, and k = 3376, r=551, d CP =4168, and k=3384, r=552, d CP = 2112, and k = 3384, r=552, d CP = 4800, and k = 3392, r=553, d CP = 56, and k = 3384, r=553, d CP = 2744, and k = 3392, r=553, d CP = 5432, and k = 3400, r=554, d CP = 688, and k = 3392, r=554, d CP = 3376, and k = 3400, r=555, d CP= 1320, and k = 3400, r=555, d CP = 4008, and k = 3408, r=556, d CP = 1952, and k = 3408, r=556, d CP = 4640, and k = 3416, r=557, d CP = 2584, and k = 3416, r=557, d CP =5272, and k=3424, r=558, d CP = 528, and k = 3416, r=558, d CP = 3216, and k = 3424, r=559, d CP = 1160, and k = 3424, r=559, d CP =3848, and k=3432, r=560, d CP = 1792, and k = 3432, r=560, d CP = 4480, and k = 3440, r=561, d CP = 2424, and k = 3440, r=561, d CP =5112, and k=3448, r=562, d CP = 368, and k = 3440, r=562, d CP = 3056, and k = 3448, or r=562, d CP = 5744, and k = 3456.

[0173] In some possible implementations, r=520, d CP = 704, and k = 3184, r=520, d CP = 3392, and k = 3192, r=520, d CP = 6080, and k = 3200, r=521, d CP = 1336, and k = 3192, r=521, d CP = 4024, and k = 3200, r=522, d CP = 1968, and k = 3200, r=522, d CP = 4656, and k = 3208, r=523, d CP = 2600, and k = 3208, r=523, d CP = 5288, and k = 3216, r=524, d CP = 544, and k = 3208, r=524, d CP = 3232, and k = 3216, r=525, d CP = 1176, and k = 3216, r=525, d CP = 3864, and k = 3224, r=526, d CP =1808, and k=3224, r=526, d CP = 4496, and k = 3232, r=527, d CP = 2440, and k = 3232, r=527, d CP =5128, and k=3240, r=528, d CP = 384, and k = 3232, r=528, d CP = 3072, and k = 3240, r=528, d CP =5760, and k=3248, r=529, d CP = 1016, and k = 3240, r=529, d CP = 3704, and k = 3248, r=530, d CP =1648, and k=3248, r=530, d CP= 4336, and k = 3256, r=531, d CP = 2280, and k = 3256, r=531, d CP =4968, and k=3264, r=532, d CP = 2912, and k = 3264, r=532, d CP = 224, and k = 3256, r=533, d CP =856, and k=3264, r=533, d CP = 3544, and k = 3272, r=534, d CP =1488, and k=3272, r=534, d CP = 4176, and k = 3280, r=535, d CP = 2120, and k = 3280, or r=535, d CP = 4808, and k = 3288.

[0174] In some possible implementations, the data processing device further includes a first interleaving unit, a second interleaving unit, a symbol mapping unit, a polarization distribution unit, and a DSP framing unit, wherein the first interleaving unit is configured to perform a first interleaving operation on the fourth bit set to obtain a fifth bit set, the fifth bit set including m0 second bit subsets, each of the second bit subsets including 256 bits, 128 bits in each of the second bit subsets being from the second bit set, and the other 128 bits in each of the second bit subsets being from a third bit set and / or parity bits of FEC encoding, and the second interleaving unit is configured to perform a first interleaving operation on the fourth bit set to obtain a fifth bit set, the fifth bit set including m0 second bit subsets, each of the second bit subsets including 256 bits, 128 bits in each of the second bit subsets being from the second bit set, and the other 128 bits in each of the second bit subsets being from a third bit set and / or parity bits of FEC encoding, The unit is configured to perform a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, each first bit stream including a plurality of fifth bit sets, where L is an even number greater than 0; the symbol mapping unit and polarization distribution unit is configured to perform symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, where t bits are mapped to one dual-polarized symbol by the symbol mapping and polarization distribution, where t is an integer greater than 0; and the DSP framing unit is configured to perform DSP framing on the dual-polarized symbol stream.

[0175] In some possible implementations, the amplitude bits in the dual polarization symbols are from the second bit set.

[0176] In some possible implementations, t=8 and the dual polarization symbols are dual polarization DP-16QAM symbols.

[0177] In some possible implementations, the DSP framing unit is specifically configured to perform framing processing every 172032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, where the superframe includes 175104 dual-polarized symbols.

[0178] In some possible implementations, the first processing unit specifically includes: Frame F from the data frame to get ×r×q bits Frame configured to acquire first data, F Frame is an integer greater than 0, and d scr ×F Frame =336×k×F DSP and F DSP represents the number of DSP superframes, and F DSP DSP superframes are Frame The first data is obtained by processing F DSP is an integer greater than 0.

[0179] In some possible implementations, F DSP >1 and F DSP A plurality of consecutive symbols in a first DSP superframe of the DSP superframes is a first marker, and F DSP A number of consecutive symbols in each of the DSP superframes except for the first DSP superframe are second markers.

[0180] According to a sixth aspect, an embodiment of the present application provides a data processing device, the data processing device includes: a first PCS unit, a first FEC encoding unit, a second PCS unit, a second FEC unit, an interleaving processing unit, a symbol mapping unit, and a polarization distribution unit, the first PCS unit is configured to perform a first PCS processing on a first set of bits in a first group of k bits to obtain a second set of bits, the second set of bits including m0×128 bits, k is an integer greater than 1, and m0 is an integer greater than 1; the first FEC encoding unit is configured to perform first forward error correction FEC encoding on the second set of bits and a third set of bits in the first group of k bits excluding the first set of bits to obtain a fourth set of bits, the fourth set of bits including m0 first square blocks, each of the first square blocks including a total of 256 bits distributed in 16 rows and 16 columns; and the second PCS unit performs second PCS processing on a fifth set of bits in the second group of k bits, the second FEC encoding unit is configured to obtain a sixth bit set, the second FEC encoding unit is configured to perform second FEC encoding on the sixth bit set and a seventh bit set in the second group of k bits excluding the fifth bit set to obtain an eighth bit set, the eighth bit set includes m0 second square blocks, each of the second square blocks includes a total of 256 bits distributed in 16 rows and 16 columns, and the interleave processing unit is configured to interleave 21 of the fourth bit set and 21 of the eighth bit set. into an interleaver buffer, the interleaver buffer including a total of 84×m1 buffer units distributed into 84 rows and m1 columns, where m0=m1×2, each of the buffer units configured to buffer a total of 256 bits in 16 rows and 16 columns, 42×m1 first square blocks being input into the even rows of the interleaver buffer and 42×m1 second square blocks being input into the odd rows of the interleaver buffer,The signal processing unit includes a first buffer subset and a second buffer subset, the first buffer subset including 42×m1 buffer units, the second buffer subset including 42×m1 buffer units, bits input to the first buffer subset are from a second bit set and a sixth bit set, bits input to the second buffer subset are from a third bit set, a seventh bit set, parity bits of a first FEC encoding, and parity bits of a second FEC encoding, and the symbol mapping unit and the polarization distribution unit are , configured to perform symbol mapping and polarization distribution for every 8 bits in the interleaver buffer to obtain one dual-polarized DP-16QAM symbol, wherein two amplitude bits among the four bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction are from one column in the first buffer unit of the first buffer subset, and two code bits among the four bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction are from one column in the second buffer unit of the second buffer subset.

[0181] In some possible implementations, four of the eight bits are from one column in a first buffer unit of a first buffer subset, and the other four of the eight bits are from one column in a second buffer unit of a second buffer subset.

[0182] In some possible implementations, the m0 first square blocks are distributed into two rows and m1 columns, and the first square block at row 0 and column m2 and the first square block at row 1 and column m2 are from the second bit set; the m0 second square blocks are distributed into two rows and m1 columns, and the second square block at row 0 and column m2 and the second square block at row 1 and column m2 are from the sixth bit set; and 0≦m2 <m1 / 2である。

[0183] In some possible implementations, m0=16, and the first buffer subset includes a total of 336 buffer units in columns 0, 1, 2, and 3 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 4, 5, 6, and 7 of the interleaver buffer; or m0=12, and the first buffer subset includes a total of 252 buffer units in columns 0, 1, and 2 of the interleaver buffer, and the second buffer subset includes a total of 252 buffer units in columns 3, 4, and 5 of the interleaver buffer.

[0184] In some possible implementations, m0=16 and m1=8, and the m0 first square blocks are distributed into 2 rows and m1 columns, and the first square block at row 0 and column 0, the first square block at row 0 and column 1, the first square block at row 0 and column 4, the first square block at row 0 and column 5, the first square block at row 1 and column 0, the first square block at row 1 and column 1, the first square block at row 1 and column 4, and the first square block at row 1 and column 5 are and the m0 second square blocks are distributed into two rows and m1 columns, with the second square block at row 0 and column 0, the second square block at row 0 and column 1, the second square block at row 0 and column 4, the second square block at row 0 and column 5, the second square block at row 1 and column 0, the second square block at row 1 and column 1, the second square block at row 1 and column 4, and the second square block at row 1 and column 5 being from the sixth bit set.

[0185] In some possible implementations, the first buffer subset includes a total of 336 buffer units in columns 0, 1, 4, and 5 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 2, 3, 6, and 7 of the interleaver buffer. [Brief explanation of the drawings]

[0186] [Figure 1] 1 is a diagram of a communication system to which an embodiment of the present application may be applied; [Figure 2] FIG. 1 is a diagram of the structure of a data frame. [Figure 3] FIG. 2 is a diagram of a first data processing embodiment of an embodiment of the present application. [Figure 4] FIG. 10 is a diagram of a second data processing embodiment of an embodiment of the present application. [Figure 5] FIG. 1 is a diagram of an embodiment of PCS and OFEC encoding of an embodiment of the present application. [Figure 6] FIG. 10 is a diagram of a fourth bit set according to an embodiment of the present application. [Figure 7] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. [Figure 8] FIG. 10 is a diagram of a fifth bit set according to an embodiment of the present application. [Figure 9(a)] FIG. 2 is a diagram of a second bit subset according to an embodiment of the present application. [Figure 9(b)] FIG. 10 is another diagram of a second bit subset according to an embodiment of the present application. [Figure 10] FIG. 2 is a diagram of a first implementation of a first interleaving process according to an embodiment of the present application. [Figure 11(a)] FIG. 2 is a diagram of a distribution of multiple first bit subsets according to an embodiment of the present application. [Figure 11(b)] FIG. 10 is another distribution diagram of a plurality of first bit subsets according to an embodiment of the present application. [Figure 11(c)] FIG. 10 is another distribution diagram of a plurality of first bit subsets according to an embodiment of the present application. [Figure 11(d)] FIG. 10 is another distribution diagram of a plurality of first bit subsets according to an embodiment of the present application. [Figure 11(e)] FIG. 10 is another distribution diagram of a plurality of first bit subsets according to an embodiment of the present application. [Figure 12]FIG. 2 is a diagram of a second implementation of the first interleaving process according to an embodiment of the present application. [Figure 13] FIG. 10 is a diagram of a third implementation of the first interleaving process according to an embodiment of the present application. [Figure 14] FIG. 2 is a diagram of intra-block interleaving according to an embodiment of the present application; [Figure 15] FIG. 2 is a diagram of inter-block interleaving according to an embodiment of the present application. [Figure 16] FIG. 10 is another diagram of intra-block interleaving according to an embodiment of the present application. [Figure 17(a)] FIG. 2 is a diagram of an implementation of performing a CRC on a data frame according to an embodiment of the present application. [Figure 17(b)] FIG. 10 is a diagram of another implementation of performing a CRC on a data frame according to an embodiment of the present application. [Figure 17(c)] FIG. 10 is a diagram of another implementation of performing a CRC on a data frame according to an embodiment of the present application. [Figure 18] FIG. 10 is a diagram of a third data processing embodiment of an embodiment of the present application. [Figure 19] FIG. 2 is a diagram of interleaver buffer distribution according to an embodiment of the present application; [Figure 20] FIG. 10 is another diagram of an interleaver buffer distribution according to an embodiment of the present application. [Figure 21] FIG. 10 is a diagram of another embodiment of PCS and FEC encoding according to an embodiment of the present application. [Figure 22] FIG. 10 is a diagram of a sixth bit set according to an embodiment of the present application. [Figure 23(a)] FIG. 10 is a diagram of a first distribution of a sixth set of bits according to an embodiment of the present application. [Figure 23(b)] FIG. 10 is a diagram of a second distribution of the sixth bit set according to an embodiment of the present application. [Figure 23(c)] FIG. 10 is a diagram of a third distribution of the sixth bit set according to an embodiment of the present application. [Figure 23(d)] FIG. 10 is a diagram of a fourth distribution of a sixth bit set according to an embodiment of the present application. [Figure 24(a)]FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 24(b)] FIG. 10 is another diagram of the third bit subset according to an embodiment of the present application. [Figure 25] 1 is a diagram of a first structure of a data processing device according to an embodiment of the present application; [Figure 26] FIG. 2 is a diagram of a second structure of a data processing device according to an embodiment of the present application; [Figure 27] FIG. 2 is a diagram of a third structure of a data processing device according to an embodiment of the present application; [Figure 28] FIG. 10 is a diagram of a fourth structure of a data processing device according to an embodiment of the present application. [Figure 29(a)] FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 29(b)] FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 29(c)] FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 29(d)] FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 29(e)] FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 29(f)] FIG. 10 is a diagram of a third bit subset according to an embodiment of the present application. [Figure 30(a)] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. [Figure 30(b)] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. [Figure 30(c)] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. [Figure 30(d)] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. [Figure 30(e)] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. [Figure 30(f)] FIG. 2 is a diagram of a first bit subset according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0187] The embodiments of the present application provide a data processing method and a data processing device that use FEC encoding in combination with PCS technology to meet the requirements of longer transmission distances, thereby making the overall data processing operation simpler, less complex, and consuming less power, thereby improving overall performance.

[0188] It should be noted that in the specification, claims, and aforementioned accompanying drawings of this application, the terms "first" and "second" are intended to distinguish between similar objects and do not limit a particular order or sequence. The foregoing terms are interchangeable where appropriate, and thus it should be understood that the embodiments described herein may be performed in orders other than those described in the present application. In addition, the terms "comprise," "have," and all other variations thereof are intended to include a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those explicitly listed steps or units and may include other steps or units not explicitly listed or inherent to the process, method, product, or device.

[0189] FIG. 1 is a diagram of a communication system to which an embodiment of the present application is applied. As shown in FIG. 1, in a transmitter, a source provides a data stream to be transmitted, and a transmitter data processor receives the data stream. The transmitter data processor first performs data processing, including encoding, interleaving, modulation, and DSP framing, on the data stream to obtain a symbol data stream, and then sends the symbol data stream to a transmitter signal processor for signal processing, where the processed symbol data stream is transmitted to a receiver device via a channel. After receiving a signal with distortion due to noise or other impairments on the channel, the receiver device transmits the signal to the receiver signal processor for dispersion compensation, synchronization, phase recovery, and other operations. The signal is then transmitted to the receiver data processor for demodulation, deinterleaving, and decoding to restore the original data for transmission to a destination.

[0190] Regarding some operation symbols in the formulas in the embodiments of the present application,

number

number

number

[0191] It should be noted that the bit sets and bit subsets in the specification and claims of this application are merely concepts introduced for ease of explanation. In actual applications, the data stream is the whole, and there is no case of division, and each bit set and each bit subset may be regarded as one or more bits in the data stream. It should be understood that the bit sets and bit subsets may alternatively be presented in the form of a matrix, an array, etc. This is not particularly limited in this specification.

[0192] FIG. 2 is a diagram of the structure of a data frame. As shown in FIG. 2, a data frame includes multiple rows of bits, each row including q bits, for example, q=10280. It should be understood that the specific type of data frame is not limited in this application. In an example, an 800ZR frame, a FlexO-8 frame, or a FlexO-8e frame includes 512 rows, each including 10280 bits. In another example, a FlexO-6 frame or a FlexO-6e frame includes 384 rows, each including 10280 bits. In some specific applications, the integer q is an integer multiple of 257. Typically, q is 10280, 8224, 4112, 2056, etc.

[0193] It should be noted that the data processing method provided in this application may be divided into three parts, denoted as "first data processing," "second data processing," and "third data processing." In a possible implementation, the first data processing may be performed before the second data processing. In another possible implementation, the first data processing may be performed before the third data processing. In the following, the "first data processing," "second data processing," and "third data processing" will be described separately in detail.

[0194] 3 is a diagram of an embodiment of the first data processing of the present application. As shown in FIG. 3, the first data processing includes a Cyclic Redundancy Check (CRC), pad insertion, and scrambling. In practical applications, at least one of CRC and pad insertion may be performed. In particular, the first data is obtained from a data frame, and the first data includes r rows and q columns of bits, where r is an integer greater than 0 and q is an integer greater than 0. In the following, for ease of distinction between r0, r1, etc., we will uniformly use r to represent the r rows included in the first data. Frame is used.

[0195] Using q=10280 as an example, the total d in =10280×r Frame The bits are obtained, and a CRC and / or pad bit insertion is performed on the first data to obtain the second data. CRC CRC parity bits are added in the CRC operation, and d PAD pad bits are inserted in a pad insertion operation. Further, the second data is scrambled to obtain third data, and the number of bits of the third data is d scr =10280×r Frame +d CRC +d PAD scrambled bits, and d CRC is an integer greater than or equal to 0, and d PAD is an integer greater than or equal to 0, and dCP =d CRC +d PAD In this case, the overhead associated with CRC checking and padding is

number

[0196] In the example, d PAD = 0, the pad bits are CRC checked 10280 × r Frame +d CRC In another example, to implement a shorter delay and lower complexity, the CRC check is bypassed and replaced by pad bits. In this case, d CRC =0.

[0197] Note that in some specific application scenarios, CRC-32 is used for the CRC check. In this case, d CRC = 32 × p, where p is an integer greater than 1, and r is an integer Frame is exactly divisible by p. More specifically, the r obtained from the data frame Frame For row data, CRC-32 uses r to add 32 parity bits. Frame / p Total of 10280 × r per line Frame / p bits, and the CRC-32 is CRC = 32 × p CRC parity bits.

[0198] Note that in some other specific application scenarios, CRC-32 is used for the CRC check. In this case, d CRC = 32 × p, where p is an integer greater than 1, and r is an integer Frame is not divisible by p. F0 ×(p-1)+r F1 =r Frame where integer r F0is an integer r F1 Greater than. In some specific implementations, integer

number

[0199] FIG. 4 is a diagram of a second data processing embodiment of the present application. As shown in FIG. 4, a plurality of bits are obtained from the third data output by the first data processing and sent to L PCS and FEC encoding in a round-robin manner, where L is an even number greater than 0. Using FIG. 4 as an example, L=4. For ease of explanation, the following uses an example in which k bits are input to each PCS and FEC encoding, where k is an integer greater than 1. In other words, in each PCS and FEC encoding, processing is performed by using k bits as a group. In practical applications, 2×k bits, 4×k bits, etc. may alternatively be input to each PCS and FEC encoding. This is not particularly limited in this specification. In particular, PCS and FEC encoding are first performed separately for every k bits, and then a first interleaving process is performed separately to obtain L first bit streams. The FEC encoding may in particular be OFEC encoding. Then, a second interleaving process is performed on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams. The second interleaving process may be OFEC interleaving, in particular. Hereinafter, OFEC interleaving is used as an example to describe the second interleaving process. Next, symbol mapping and polarization distribution are performed on the L / 2 second bit streams to obtain one dual-polarized symbol stream. For example, t bits are mapped to one dual-polarized symbol by symbol mapping and polarization distribution, where t is an integer greater than 0. For example, when t=8, the dual-polarized symbol is a dual-polarized DP-16QAM symbol. Furthermore, digital signal processing (DSP) framing is performed on the dual-polarized symbol stream.For example, DSP framing is performed every 172032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, and the superframe contains 175104 dual-polarized symbols.

[0200] It should be noted that the second data processing may alternatively include six PCS and OFEC encoding. In this case, the corresponding second data processing includes six first interleaving processes and three second interleaving processes. The output of each PCS and OFEC encoding is sent to one first interleaving process, the outputs of each of the two first interleaving processes are sent to one second interleaving process, and the outputs of the three second interleaving processes are sent to symbol mapping for symbol modulation and mapping. It should further be noted that the second data processing may alternatively include eight PCS and OFEC encoding. In this case, the corresponding second data processing includes eight first interleaving processes and four second interleaving processes. The output of each PCS and OFEC coding is sent to one first interleaving process, the outputs of every two first interleaving processes are sent to one second interleaving process, and the outputs of the four second interleaving processes are sent to symbol mapping for symbol modulation and mapping.

[0201] Each operation of the second data processing will be described in detail below.

[0202] (1) PCS and FEC coding FIG. 5 is a diagram of an embodiment of PCS and FEC encoding of an embodiment of the present application. As shown in FIG. 5, a lane of k input bits is used as an example for explanation. PCS processing is performed on a first bit set among the k bits to obtain a second bit set. OFEC encoding is performed on the second bit set and a third bit set among the k bits excluding the first bit set to obtain a fourth bit set. The fourth bit set includes m first bit subsets, each of which includes F bits, where m is an integer greater than 1 and F is an even number greater than 1. For example, m may be 12 or 16, and F may be 256. Note that the number of bits in the second bit set is m × F / 2, and the number of bits in the fourth bit set is m × F. Note that the amplitude bits in the dual polarization symbol are from the second bit set. For ease of explanation, F0=256 is used as an example in the following description.

[0203] In a possible implementation, m=16, the number of bits in the first bit set is k−1504, the number of bits in the second bit set is 2048, the number of bits in the third bit set is 1504, and the number of bits in the fourth bit set is 4096. In other words, k−1504 bits are sent to PCS processing to obtain 2048 bits, which are then combined with the remaining 1504 bits of k that are not sent to PCS processing, resulting in a total of 2048+1504=3552 bits that are sent to OFEC encoding for encoding with the addition of 544 OFEC parity bits to obtain a total of 4096 OFEC coded bits. In this case, the coding overhead for OFEC coding is 4096 / 3552−1=15.3%.

[0204] In another possible implementation, m=12, the number of bits in the first bit set is k−992, the number of bits in the second bit set is 1536, the number of bits in the third bit set is 992, and the number of bits in the fourth bit set is 3072. In other words, k−992 bits are sent for PCS processing to obtain 1536 bits, which are combined with the remaining 992 bits of k that are not sent for PCS processing, resulting in a total of 1536+992=2528 bits sent to FEC encoding for encoding that adds 544 FEC parity bits to obtain a total of 3072 FEC coded bits. In this case, the coding overhead of FEC coding is 3072 / 2528−1=21.5%. The particular FEC code may be an FEC code with 21.5% OH obtained by shortening an OFEC code with 15.3% OH, in some scenarios the shortened OFEC code is also referred to as the OFEC code for short.

[0205] The number d of bits of the third data output by the first data processing scr Note that d is an integer multiple of L × k. In this case, d scr After the bits are output by the first data processing, d scr The processing on the bits may be completed by performing the second data processing one or more times, and no further processing such as buffering needs to be performed, which simplifies the specific hardware implementation of the overall data processing and reduces power consumption.

[0206] When m0=16, the number of input bits corresponding to the PCS processing, k PCS Note that =k-1504 is an integer multiple of 2, 4, 8, or 16. The number of output bits corresponding to the PCS process is considered to be 2048 bits. Generally, in the PCS process, the input k LUT The bit is LUTThe number of output bits in the PCS process is n. LUT cannot be made too small, otherwise the performance of the entire PCS process will be deteriorated. The number of output bits of the PCS process, n LUT cannot be too large. Otherwise, the number of output bits of the PCS process, n LUT is not conducive to hardware implementation. In some specific hardware implementations, n LUT is 128, 256, 512, or 1024. LUT = 128, in PCS processing, the LUT mapping is LUT = k to output 128 bits LUT = (k - 1504) / 16 input bits each time, and after the LUT mapping is performed 16 times in a row, that is, after the LUT mapping is performed for a total of k - 1504 bits, the corresponding 2048 bits are output. In some specific applications, the lookup table LUT processing may be implemented by including multiple lookup sub-tables, and the number of input bits of the lookup sub-tables may be different, and the number of output bits of the lookup sub-tables may also be different. In this application, the specific implementation of the lookup table is not limited.

[0207] n LUT = 256, in PCS processing, the LUT mapping is LUT = k to output 256 bits LUT = (k-1504) / 8 input bits each time, and after the LUT mapping is performed eight times in succession, that is, after the LUT mapping is performed for a total of k-1504 bits, the corresponding 2048 bits are output. LUT = 512, in PCS processing, the LUT mapping is LUT = k to output 128 bits LUT= (k-1504) / 4 input bits each time, and after the LUT mapping is performed four times in succession, that is, after the LUT mapping is performed for a total of k-1504 bits, the corresponding 2048 bits are output. LUT = 1024, in PCS processing, the LUT mapping is LUT = k to output 1024 bits LUT = (k-1504) / 2 input bits each time, and after the LUT mapping is performed twice consecutively, that is, after the LUT mapping is performed for a total of k-1504 bits, the corresponding 2048 bits are output. Therefore, when m0=16, the number k-1504 of input bits corresponding to the PCS processing is an integer multiple of 2, 4, 8, or 16 to facilitate hardware implementation or achieve better performance.

[0208] When m0=12, the number of input bits corresponding to the PCS processing, k PCS Note that =k-992 is an integer multiple of 2, 3, 4, 6, 8, 12, or 16. The number of output bits corresponding to the PCS process is considered to be 1536 bits. Generally, in PCS processing, the input k LUT The bit is LUT The number of output bits in the PCS process is n. LUT cannot be made too small, otherwise the performance of the entire PCS process will be deteriorated. The number of output bits of the PCS process, n LUT cannot be too large. Otherwise, the number of output bits of the PCS process, n LUT is not conducive to hardware implementation. In some specific hardware implementations, n LUT is 96, 128, 192, 256, 384, 512, or 768. LUT = 96, in PCS processing, the LUT mapping is LUT = k to output 96 bits LUT= (k-992) / 16 input bits each time, and after the LUT mapping is performed 16 times in succession, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. LUT = 128, in PCS processing, the LUT mapping is LUT = k to output 128 bits LUT = (k-992) / 12 input bits each time, and after the LUT mapping is performed 12 times in succession, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. LUT = 192, in PCS processing, the LUT mapping is LUT = k to output 192 bits LUT = (k-992) / 8 input bits each time, and after the LUT mapping is performed eight times in succession, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. LUT = 256, in PCS processing, the LUT mapping is LUT = k to output 256 bits LUT = (k-992) / 6 input bits each time, and after the LUT mapping is performed six times in succession, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. LUT = 384, in PCS processing, the LUT mapping is LUT = 384 bits to output k LUT = (k-992) / 4 input bits each time, and after the LUT mapping is performed four times in succession, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. LUT = 512, in PCS processing, the LUT mapping is LUT = k to output 512 bits LUT= (k-992) / 3 input bits each time, and after the LUT mapping is performed three times in succession, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. LUT = 768, in PCS processing, the LUT mapping is LUT = 768 bits to output k LUT = (k-992) / 2 input bits each time, and after the LUT mapping is performed twice consecutively, that is, after the LUT mapping is performed for a total of k-992 bits, the corresponding 1536 bits are output. Therefore, when m0=12, in order to facilitate hardware implementation or to implement better performance, the quantity k-992 of input bits corresponding to the PCS processing is an integer multiple of 2, 3, 4, 6, 8, 12, or 16.

[0209] FIG. 6 is a diagram of a fourth bit set according to an embodiment of the present application. As shown in FIG. 6, in some application scenarios, the m0 first bit subsets of the fourth bit set may be particularly presented in the form of square blocks. A square block may also be referred to as a block for short, and each first bit subset may be referred to as a square block B. For example, as shown in FIG. 6, m0=16 square blocks B are distributed into two rows and eight columns. The block in row i0 and column j0 includes 256 bits of 4096 OFEC coded bits, where 0≦i0<2 and 0≦j0<8. As another example, m0=12 square blocks B are distributed into two rows and six columns. The block in row i0 and column j0 includes 256 bits of 3072 FEC coded bits, where 0≦i0<2 and 0≦j0<6. Furthermore, the 256 bits of each square block B may be distributed into F1 rows and F1 columns, where F1=16 is used as an example below for ease of explanation.

number

[0210] In a particular scenario, it should be understood that the square block B with 2 rows and m1 columns, also called the output block of FEC encoding, has m0 = 2 × m1. The square block B with 2 rows and m1 columns may be considered as a bit matrix with 32 rows and m0 × 8 columns, and it should be further understood that it contains 32 rows, with each row containing m0 × 8 bits. In this case, the bit at row r0 and column c0 of the bit matrix corresponds to the bit at row i1 and column j1 of the square block [Number] such that i1 = r0 % 16, j1 = c0 % 16, 0 ≤ r0 < 32, 0 ≤ c0 < m0 × 8, 0 ≤ i0 < 2, 0 ≤ j0 < 8, 0 ≤ i1 < 16, and 0 ≤ j1 < 16. In this application, in some cases, 1 row represents 8 square blocks, in some cases, 1 row represents a total of 16 bits in one row of the square block, and in some cases, 1 row represents a total of m0 × 8 bits in one row of a set containing m0 square blocks. Specific cases may be distinguished based on the understanding of the context. [Number] , [Number] , i1 = r0 % 16, j1 = c0 % 16, 0 ≤ r0 < 32, 0 ≤ c0 < m0 × 8, 0 ≤ i0 < 2, 0 ≤ j0 < 8, 0 ≤ i1 < 16, and 0 ≤ j1 < 16. In this application, in some cases, 1 row represents 8 square blocks, in some cases, 1 row represents a total of 16 bits in one row of the square block, and in some cases, 1 row represents a total of m0 × 8 bits in one row of a set containing m0 square blocks. Specific cases may be distinguished based on the understanding of the context.

[0211] In some specific applications, as shown in FIG. 6, the block at row i0 and column j0 (0 ≤ i0 < 2 and 0 ≤ j0 < 8) [Number] includes bits from bit 512 × j0 + 256 × i0 to bit 512 × j0 + 256 × i0 + 255 of the fourth bit set. For example, the block B at row i0 = 0 and column j0 = 0 0,0 includes bits from bit 0 to bit 255 of the fourth bit set. As another example, the block B at row i0 = 1 and column j0 = 7 1,7includes bits 3840 through 4095 of the fourth bit set.

[0212] 7 is a diagram of a first bit subset according to an embodiment of the present application. As shown in FIG. 7, each square block includes a total of 256 bits in 16 rows and 16 columns, and a bit in row i1 and column j1 (0≦i1<16 and 0≦j1<16) of the square block corresponds to bit 16×i1+j1 among the 256 bits. For example, a bit in row i1=1 and column j1=0 of the square block corresponds to bit 16 among the 256 bits. As another example, a bit in row i1=2 and column j1=3 of the square block corresponds to bit 35 among the 256 bits.

[0213] More specifically, the square block in row i0 and column j0 (0≦i0<2 and 0≦j0<8)

number

number

[0214] (2) First interleave process A first interleaving process is performed on the fourth bit set obtained by the PCS process and the FEC encoding to obtain a fifth bit set. In particular, in the first interleaving process, the bit sequence of the fourth bit set is permuted. The fifth bit set includes m second bit subsets, each of which includes 256 bits. It should be understood that, as shown in FIG. 4, each first bit stream sent to the second interleaving process may include multiple fifth bit sets.

[0215] FIG. 8 is a diagram of a fifth bit set according to an embodiment of the present application. As shown in FIG. 8, m0=16 is used as an example. Similar to the 16 first bit subsets of the fourth bit set, the 16 second bit subsets of the fifth bit set may also be presented in the form of square blocks. Each second bit subset may be referred to as a square block T, and the 256 bits of each square block T are distributed into 16 rows and 16 columns. For example, the 16 square blocks T are distributed into 2 rows and 8 columns. The block at row i0 and column j0 includes 256 bits of the 4096 bits obtained by the first interleaving process, where 0≦i0<2 and 0≦j0<8. For ease of explanation,

number

number

number

Number

[0216] Note that each 128 bits in each of the second bit subsets are from the second bit set, and the other 128 bits in each of the second bit subsets are from the third bit set and / or the parity bits of the OFEC encoding. In the example, the first interleaving process is performed after OFEC encoding is executed on the 2048 bits obtained by the PCS process, and the 2048 bits are distributed to 16 square blocks T, and 128 bits in each square block T containing 256 bits are distributed.

[0217] In some specific applications, 8 bits out of 16 bits in each row of the second bit subset are from the second bit set, and the other 8 bits out of 16 bits in each row of the second bit subset are from the third bit set and / or the parity bits of the OFEC encoding.

[0218] FIG. 9(a) is a diagram of the second bit subset according to an embodiment of the present application. As shown in FIG. 9(a), in a possible implementation, the row i2 and column of the second bit subset

Number

[0219] Note that a total of m1×256 bits of the m1 first bit subsets of the fourth bit set are from the second bit set, with m0=2×m1. See Figure 6. m0=16 and m1=8 are used as an example. Eight square blocks B out of a total of 16 square blocks B in two rows and eight columns are from the 2048 bits of the second bit set. Furthermore, bits 0 to 2047 out of the 4096 bits of the fourth bit set are from the 2048 bits of the second bit set.

[0220] In a possible implementation, the m0×256 bits of the fourth bit set are distributed into 32 rows and m0×8 columns, the m0×256 bits of the fifth bit set are distributed into 32 rows and m0×8 columns, and the m0×8 bits of row r1 of the fifth bit set are from the m0×8 bits of row r0 of the fourth bit set, where 0≦r0<32 and 0≦r1<32.

[0221] 10 is a diagram of a first implementation of the first interleaving process according to an embodiment of the present application. As shown in FIG. 10, the 4096 bits of the fourth bit set (including 16 square blocks B) are distributed into 32 rows and 128 columns, and the 4096 bits of the fifth bit set (including 16 square blocks T) are distributed into 32 rows and 128 columns. The 128 bits of row r1 of the fifth bit set are from the 128 bits of row r0 of the fourth bit set. More specifically, when r1%4=0, bits 2, 3, 6, 7, 10, 11, 14, 15, ..., 114, 115, 118, 119, 122, 123, 126, and 127 of the 128 bits of row r1 of the fifth bit set, i.e., a total of 64 bits, are from the 128 bits of row r0 of the fourth bit set and obtained by the PCS process. When r1%4=1, bits 0, 3, 4, 7, 8, 11, 12, 15, ..., 112, 115, 116, 119, 120, 123, 124, and 127 of the 128 bits of row r1 of the fifth bit set, i.e., a total of 64 bits, are from the 128 bits of row r0 of the fourth bit set and obtained by the PCS process. When r1%4=2, bits 0, 1, 4, 5, 8, 9, 12, 13, ..., 112, 113, 116, 117, 120, 121, 124, and 125 of the 128 bits of row r1 of the fifth bit set, i.e., a total of 64 bits, are from the 128 bits of row r0 of the fourth bit set and obtained by the PCS process. When r1%4=3, bits 1, 2, 5, 6, 9, 10, 13, 14, ..., 113, 114, 117, 118, 121, 122, 125, and 126 of the 128 bits of row r1 of the fifth bit set, i.e., a total of 64 bits, are from the 128 bits of row r0 of the fourth bit set and obtained by the PCS process.

[0222] In the example, the m0 first bit subsets are distributed across two rows and m1 columns, and the first bit subset in row 0 and column m2 is

number

number

[0223] 11(a) is a diagram of the distribution of multiple first bit subsets according to an embodiment of the present application. As shown in FIG. 11(a), m0=16 is used as an example. 8 square blocks B with a shaded background 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 is from the 2048 bits of the second bit set, and is the 8 square blocks B that do not have a shaded background. 0,4 , B 0,5 , B 0,6 , B 0,7 , B 1,4 , B 1,5 , B 1,6 , and B 1,7 are 1504 bits and 544 OFEC parity bits for which no PCS processing is performed. The 16 square blocks B are considered as a group, and the first 64 bits of the 128 bits in row r0 are 64 bits of the 2048 bits in the second bit set, where 0≦r0<32.

[0224] Using FIG. 11(a) as an example, the specific interleaving rule for the first interleaving process is as follows:

number

number

[0225] Example 1: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0226] Example 2: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0227] Example 3: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0228] Example 4: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0229] Using FIG. 11(a) as an example, another specific interleaving rule for the first interleaving process is as follows:

number

number

[0230] Example 5: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0231] Example 6: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0232] Example 7: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0233] Example 8: Bit c1 in the m0×8 bits of row r1 of the fifth bit set is from bit c0 in the m0×8 bits of row r0 of the fourth bit set,

number

number

[0234] Figure 11(a) is used as an example. In a possible implementation, the following conditions are met: The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 51,5 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0235] Figure 11(a) is used as an example. In another possible implementation, the following conditions are met: The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0.0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B in row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0236] Figure 11(a) is used as an example. In yet another possible implementation, the following conditions are met: The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 0 and column 1 0,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 4 0,4 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T at row 0 and column 3 0,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 5 0,5 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 0 and column 5 0,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 2. 0,2and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 0 and column 7 0,7 A total of 512 bits are allocated to the first bit subset B in row 0 and column 3. 0,3 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 1 and column 0 1,0 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 4 1,4 is from a total of 512 bits, A second subset of bits T in row 1 and column 2 1,2 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 5 1,5 is from a total of 512 bits, The second bit subset T in row 1 and column 4 1,4 and a second bit subset T at row 1 and column 5 1,5 The total 512 bits are the first bit subset B in row 1 and column 2. 1,2 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 1 and column 6 1,6 and a second bit subset T at row 1 and column 7 1,7 The total 512 bits are the first bit subset B in row 1 and column 3. 1,3 and the first bit subset B in row 1 and column 7 1,7This is from a total of 512 bits.

[0237] 11(b) is another diagram of the distribution of multiple first bit subsets according to an embodiment of the present application. As shown in FIG. 11(b), m0=16 is used as an example. 8 square blocks B with a shaded background 0,0 , B 0,1 , B 0,4 , B 0,5 , B 1,0 , B 1,1 , B 1,4 , and B 1,5 is from the 2048 bits of the second bit set, and is the 8 square blocks B that do not have a shaded background. 0,2 , B 0,3 , B 0,6 , B 0,7 , B 1,2 , B 1,3 , B 1,6 , and B 1,7 are 1504 bits and 544 OFEC parity bits for which no PCS processing is performed. Considering 16 square blocks B as a group, bits 0 to 31 and bits 64 to 95 of row r0 are 64 bits of the 2048 bits of the second bit set, where 0≦r0<32.

[0238] Using FIG. 11(b) as an example, the specific interleaving rule for the first interleaving process is as follows:

number

number

[0239] Example 9: Bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set,

number

number

[0240] Example 10: Bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set,

number

number

[0241] Example 11: Bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set,

number

number

[0242] Example 12: Bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set,

number

number

[0243] Using FIG. 11(b) as an example, the specific interleaving rule for the first interleaving process is as follows:

number

number

[0244] Example 13: Bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set,

number

number

[0245] Example 14: Bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set,

number

number

[0246] Example 15: Bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set,

number

number

[0247] Example 16: Bit c1 of the 128 bits in row r1 of the fifth bit set is from bit c0 of the 128 bits in row r0 of the fourth bit set,

number

number

[0248] Figure 11(b) is used as an example. In a possible implementation, the following conditions are met: The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0249] Figure 11(b) is used as an example. In another possible implementation, the following conditions are met: The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 1 and column 0 1,0 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, A second subset of bits T at row 0 and column 1 0,1 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T in row 1 and column 2 1,2 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 3 0,3 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5 and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 1 and column 4 1,4 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, The second bit subset T at row 0 and column 5 0,5 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 1 and column 6 1,6 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6is from a total of 512 bits, The second bit subset T at row 0 and column 7 0,7 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0250] Figure 11(b) is used as an example. In yet another possible implementation, the following conditions are met: The second bit subset T at row 0 and column 0 0,0 and a second bit subset T at row 0 and column 1 0,1 A total of 512 bits are allocated to the first bit subset B in row 0 and column 0. 0,0 and the first bit subset B at row 0 and column 2 0,2 is from a total of 512 bits, The second bit subset T at row 0 and column 2 0,2 and a second bit subset T at row 0 and column 3 0,3 A total of 512 bits are allocated to the first bit subset B in row 0 and column 1. 0,1 and the first bit subset B at row 0 and column 3 0,3 is from a total of 512 bits, The second bit subset T at row 0 and column 4 0,4 and a second bit subset T at row 0 and column 5 0,5 A total of 512 bits are allocated to the first bit subset B in row 0 and column 4. 0,4 and the first bit subset B at row 0 and column 6 0,6 is from a total of 512 bits, The second bit subset T at row 0 and column 6 0,6 and a second bit subset T at row 0 and column 7 0,7 A total of 512 bits are allocated to the first bit subset B in row 0 and column 5. 0,5and the first bit subset B at row 0 and column 7 0,7 is from a total of 512 bits, The second bit subset T at row 1 and column 0 1,0 and a second bit subset T at row 1 and column 1 1,1 A total of 512 bits are allocated to the first bit subset B in row 1 and column 0. 1,0 and the first bit subset B in row 1 and column 2 1,2 is from a total of 512 bits, A second subset of bits T in row 1 and column 2 1,2 and a second bit subset T at row 1 and column 3 1,3 A total of 512 bits are allocated to the first bit subset B in row 1 and column 1. 1,1 and the first bit subset B in row 1 and column 3 1,3 is from a total of 512 bits, The second bit subset T in row 1 and column 4 1,4 and a second bit subset T at row 1 and column 5 1,5 A total of 512 bits are allocated to the first bit subset B in row 1 and column 4. 1,4 and the first bit subset B in row 1 and column 6 1,6 is from a total of 512 bits, The second bit subset T at row 1 and column 6 1,6 and a second bit subset T at row 1 and column 7 1,7 A total of 512 bits are allocated to the first bit subset B in row 1 and column 5. 1,5 and the first bit subset B in row 1 and column 7 1,7 This is from a total of 512 bits.

[0251] As shown in Figure 11(b), eight square blocks B 0,0 , B 0,1 , B 0,4 , B 0,5 , B 1,0 , B 1,1 , B 1,4 , and B1,5 Note that, in Figure 5, the positions of the 2048 bits of the second bit set in the codeword for FEC encoding are discontinuous, as shown in Figure 11(b). In this case, before the second and third bit sets are sent to FEC encoding, a pre-encoding interleaving process is further performed to scramble the sequence of the 3552 bits before encoding, so that the sequence is as follows: first 1024 consecutive bits from the second bit set, then 1024 consecutive bits from the third bit set, then 1024 consecutive bits from the second bit set, and finally 480 consecutive bits from the third bit set.

[0252] It should be noted that the pre-encoding interleaving process is optional, but the first interleaving process is mandatory. For example, as shown in Figure 11(a), the pre-encoding interleaving process is not performed on the second and third bit sets, but the coded fourth bit set still needs to be sent to the first interleaving process. For example, as shown in Figure 11(b), the pre-encoding interleaving process is performed on the second and third bit sets, and the coded fourth bit set needs to be sent to the first interleaving process to disrupt the sequence.

[0253] It should be noted that in some specific applications, the pre-encoding interleaving process is performed on the second bit set and the third bit set, and the encoded fourth bit set is also sent to the first interleaving process to disrupt the sequence. When some first bit subsets of the encoded fourth bit set satisfy the pattern shown in FIG. 9(a) or 9(b), the first interleaving process may be performed only on the remaining first bit subsets that do not satisfy the pattern shown in FIG. 9(a) or 9(b) to disrupt the sequence, so that all second bit subsets of the fifth bit set obtained by the first interleaving process on the encoded fourth bit set satisfy the pattern shown in FIG. 9(a) or 9(b). In other words, the first interleaving process may be performed on some bits of the fourth bit set. This is not particularly limited in this specification. Optionally, in some scenarios, if some first bit subsets of the encoded fourth bit set satisfy the pattern shown in Figure 9(a) or Figure 9(b), the first interleaving process may still be performed on all first bit subsets if all second bit subsets of the fifth bit set obtained by the first interleaving process satisfy the pattern shown in Figure 9(a) or Figure 9(b).

[0254] Below, we provide some implementation solutions of pre-encoding interleaving and corresponding first interleaving.

[0255] 21 is a diagram of another embodiment of PCS and FEC encoding according to an embodiment of the present application. As shown in FIG. 21, pre-encoding interleaving is performed on the second bit set and the third bit set to obtain a sixth bit set, and then FEC encoding is performed on the sixth bit set to obtain a fourth bit set, where the sixth bit set includes m third bit subsets, and the m third bit subsets are distributed into two rows and m columns. m=2×m, where m is an integer greater than 1 and less than m. Each third bit subset of some third bit subsets includes an F bit, and each third bit subset of other third bit subsets includes an F bit, where F is an even number greater than 1 and less than F.

[0256] It should be understood that the above "the sixth bit set includes m3 third bit subsets, and the m3 third bit subsets are distributed into two rows and m4 columns" is merely a concept introduced for ease of explanation. In actual applications, the sixth bit set is the whole, there is no "two rows and m4 columns" distribution, and each third bit subset may be regarded as a plurality of bits in the sixth bit set.

[0257] 22 is a diagram of a sixth bit set according to an embodiment of the present application. In an example, the sixth bit set includes m3=14 third bit subsets. In some application scenarios, the m3 third bit subsets of the sixth bit set may be particularly presented in the form of square blocks. A square block may also be referred to as a block for short, and each third bit subset may be referred to as a square block I. For example, as shown in FIG. 22, the m3=14 square blocks I are distributed into 2 rows and 7 columns. For ease of explanation,

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Number

[0258] In some specific scenarios, the square block I of 2 rows and m4 columns, which is also called the input block of FEC encoding, it should be understood that m3 = 2 × m4. The square block I of 2 rows and m4 columns may be considered as a bit matrix of 32 rows and m3 × 8 - 1 columns, and it should be further understood that it contains 32 rows and each row contains m3 × 8 - 1 bits. In this case, the bit at row r0 and column c0 of the bit matrix corresponds to the bit at row i1 and column j1 in the square block

Number

Number

Number

[0259] In some specific applications, as shown in FIG. 22, a block in row i0 and column j0 (0≦i0<2 and 0≦j0<6)

number

[0260] 23(a) is a diagram of a first distribution of the sixth bit set according to an embodiment of the present application. As shown in FIG. 23(a), m2=14 is used as an example. The square block I of the sixth bit set 0,0 , I 0,1 , I 0,4 , I 0,5 , I 1,0 , I 1,1 , I 1,4 , and I 1,5 The total 2048 bits of square block I are from the second set of bits. 0,2 , I 0,3 , I 0,6 , I 1,2 , I 1,3 , and I 0,6All bits of are from the third bit set. Then, the fourth bit set is obtained by FEC encoding on the sixth bit set. The corresponding distribution of the fourth bit set is shown in FIG. 11(b). In this case, the fifth bit set may be obtained through first interleaving by any of the solutions from Examples 9 to 12, and any second bit subset of the fifth bit set is shown in FIG. 9(a). Alternatively, the fifth bit set may be obtained through first interleaving by any of the solutions from Examples 13 to 16, and any second bit subset of the fifth bit set is shown in FIG. 9(b).

[0261] 23(b) is a diagram of a second distribution of the sixth bit set according to an embodiment of the present application. As shown in FIG. 23(b), m2=14 is used as an example. The square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I 0,3 , I 1,0 , I 1,1 , I 1,2 , and I 1,3 Half of the bits (128 bits) of each of the square blocks I are from the second bit set, and the other half of the bits (128 bits) are from the third bit set, on which no PCS processing is performed. 0,4 , I 0,5 , I 1,4 , and I 1,5 All bits of square block I are from the second bit set. 0,6 and I 1,6 is from the third bit set where no PCS processing is performed.

[0262] 24(a) is a diagram of a third bit subset according to an embodiment of the present application. FIG. 24(b) is another diagram of a third bit subset according to an embodiment of the present application. Based on the sixth bit set shown in FIG. 23(b), further, square block I 0,0 , I 0,1 , I0,2 , I 0,3 , I 1,0 , I 1,1 , I 1,2 , and I 1,3 satisfies the pattern shown in Figure 24(a), in other words, the square block

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[0263] 11(c) is another diagram of a distribution of a plurality of first bit subsets according to an embodiment of the present application. The fourth bit set is obtained by FEC encoding on the sixth bit set shown in FIG. 23(b), and the corresponding distribution of the fourth bit set is shown in FIG. 11(c). In particular, the square block B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 Half of the bits (128 bits) of each of the square blocks B are from the second bit set, and the other half of the bits (128 bits) are from the third bit set on which no PCS processing is performed. 0,4 , B 0,5 , B 1,4 , and B 1,5 All bits of square block B are from the second bit set. 0,6 , B 0,7 , B 1,6 , and B 1,7 are from the third set of bits and / or OFEC parity bits for which no PCS processing is performed. Additionally, the square block B of the fourth set of bits 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 The bit arrangement method of is shown in Figure 9(a) or Figure 9(b). In particular, the square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I 0,3 , I 1,0 , I 1,1 , I 1,2 , and I 1,3 24(a), the square block B of the fourth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B1,2 , and B 1,3 is shown in Figure 9(a). The square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I 0,3 , I 1,0 , I 1,1 , I 1,2 , and I 1,3 When the square block B of the fourth bit set is shown in FIG. 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 , is shown in Figure 9(b). In this case, the first interleaving is performed on the square block T 0,4 , T 0,5 , T 0,6 , T 0,7 , T 1,4 , T 1,5 , T 1,6 , and T 1,7 To obtain the fourth bit set, a total of eight square blocks, namely B 0,4 , B 0,5 , B 0,6 , B 0,7 , B 1,4 , B 1,5 , B 1,6 , and B 1,7 should only be executed for B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 is the square block B of the fifth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 are output in the original sequence to obtain

[0264] Figure 11(c) is used as an example, and the square block B of the fourth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 is shown in Figure 9(a). The specific interleaving rule of the first interleaving process is as follows: bits 0 to 63 among the 128 bits of row r1 of the fifth bit set (comprising m0 square blocks T) correspond one-to-one to bits 0 to 63 of row r0 of the fourth bit set. Furthermore, bits 0 to 63 among the 128 bits of row r1 of the fifth bit set correspond one-to-one to bits 0 to 63 of row r0 of the fourth bit set.

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[0265] Example 17: When 0≦c1<64, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set. When 64≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set.

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[0266] Example 18: When 0≦c1<64, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set, or when 64≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set.

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[0267] Example 19: When 0≦c1<64, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set, or when 64≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set.

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[0268] Example 20: When 0≦c1<64, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c1 of the 128 bits of row r0 of the fourth bit set, or when 64≦c1<128, bit c1 of the 128 bits of row r1 of the fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set.

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[0269] 23(c) is a diagram of a third distribution of the sixth bit set according to an embodiment of the present application. As shown in FIG. 23(c), the square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I 0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I 1,3 , and I 1,4 Half of the bits (128 bits) of each of the square blocks I are from the second bit set, and the other half of the bits (128 bits) are from the third bit set, on which no PCS processing is performed. 0,5 , Square Block I 1,5 , Square Block I 0,6 Columns 0 to 7 of the square block I 1,6 All bits in columns 0 to 7 of square block I are from the second bit set. 0,6 Columns 8 to 14 and Square Block I 1,6 The bits in columns 8 to 14 of square block I are from a third set of bits for which no PCS processing is performed. 0,0 , I0,1 , I 0,2 , I 0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I 1,3 , and I 1,4 satisfies the pattern shown in Figure 24(a), in other words, the square block

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[0270] 11(d) is another diagram of a distribution of a plurality of first bit subsets according to an embodiment of the present application. The fourth bit set is obtained by FEC encoding on the sixth bit set shown in FIG. 23(c), and the corresponding distribution of the fourth bit set is shown in FIG. 11(d). In particular, the square block B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 Half of the bits (128 bits) of each of the square blocks B are from the second bit set, and the other half of the bits (128 bits) are from the third bit set on which no PCS processing is performed. 0,5 , square block B 1,5 , square block B 0,6 , and square block B 1,6 All bits in the shaded part of square block B are from the second bit set. 0,6 and square block B 0,6 The unshaded bits of the square block B 0,7 and square block B 1,7 All bits of the square block B of the fourth bit set are from the third bit set and / or OFEC parity bits, for which no PCS processing is performed. 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 The arrangement of the bits from the second bit set and the bits from the third bit set for which no PCS processing is performed is shown in Figure 9(a) or 9(b). In particular, the square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I 1,3 , and I 1,4 24(a), the square block B of the fourth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 is shown in Figure 9(a). The square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I 0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I 1,3 , and I 1,4 When the square block of the fourth bit set is shown in FIG. 24(b), 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 , is shown in Figure 9(b). In this case, the first interleaving is performed on the square block T 0,5 , T 0,6 , T 0,7 , T 1,5 , T 1,6 , and T 1,7 To obtain the fourth bit set, we use a total of six square blocks, namely, B 0,5 , B 0,6 , B 0,7 , B 1,5 , B 1,6 , and B 1,7 should only be executed for B 0,0 , B 0,1 , B 0,2 , B 0,3 , B0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 is the square block T of the fifth bit set 0,0 , T 0,1 , T 0,2 , B 0,3 , T 0,4 , T 1,0 , T 1,1 , T 1,2 , T 1,3 , and T 1,4 are output in the original sequence to obtain

[0271] Figure 11(d) is used as an example, and the square block B of the fourth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 is shown in Figure 9(a). The specific interleaving rule of the first interleaving process is as follows: bits 0 to 79 of the 128 bits of row r1 of the fifth bit set (containing m0 square blocks T) correspond one-to-one to bits 0 to 79 of row r0 of the fourth bit set (containing m0 square blocks B).

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[0272] Example 21: When 0≦c1<80, bit c1 in the 128 bits of row r1 of the fifth bit set is from bit c1 in the 128 bits of row r0 of the fourth bit set, or when 80≦c1<128, bit c1 in the 128 bits of row r1 of the fifth bit set is from bit 80+c0 in the 128 bits of row r0 of the fourth bit set.

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[0273] Example 22: When 0≦c1<80, bit c1 in the 128 bits of row r1 of the fifth bit set is from bit c1 in the 128 bits of row r0 of the fourth bit set, or when 80≦c1<128, bit c1 in the 128 bits of row r1 of the fifth bit set is from bit 80+c0 in the 128 bits of row r0 of the fourth bit set.

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[0274] 23(d) is a diagram of a fourth distribution of the sixth bit set according to an embodiment of the present application. As shown in FIG. 23(d), the square block I of the sixth bit set 0,0 , I 0,1 , I 0,2 , I 0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I 1,3 , and I 1,4 Half of the bits (128 bits) of each of the square blocks I are from the second bit set, and the other half of the bits (128 bits) are from the third bit set, on which no PCS processing is performed. 0,5 and I 1,5 Nine bits in each row of square block I are from the second set of bits that have been PCS processed, and the other seven bits in each row are from the third set of bits that have not been PCS processed. 0,6 and I 1,6 All bits of are from the PCS processed second set of bits.

[0275] 11(e) is another diagram of a distribution of a plurality of first bit subsets according to an embodiment of the present application. The fourth bit set is obtained by FEC encoding on the sixth bit set shown in FIG. 23(d), and the corresponding distribution of the fourth bit set is shown in FIG. 11(e). In particular, the square block B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1, B 1,2 , B 1,3 , and B 1,4 Half of the bits (128 bits) of each of the square blocks B are from the second bit set, and the other half of the bits (128 bits) are from the third bit set on which no PCS processing is performed. 0,5 and B 1,5 Nine bits in each row of square block B are from the second set of bits that have been PCS processed, and the other seven bits in each row are from the third set of bits that have not been PCS processed. 0,6 and B 1,6 The bits in each row i1 and column 15-i1 of the square block B are from the OFEC parity bits, in other words, 0,6 and B 1,6 The bits on the diagonal line from the bottom left to the top right of square block B are from OFEC parity bits, and the remaining bits are from the second set of PCS processed bits. 0,7 and B 1,7 All bits of are from the OFEC parity bits.

[0276] Furthermore, the square block B of the fourth bit set shown in FIG. 11(e) 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 The arrangement of bits from the second bit set and bits from the third bit set in the square block B shown in FIG. 0,5 and B 1,5 The arrangement of bits from the second bit set and bits from the third bit set in each of columns 0 to C-1 is shown in columns 0 to C-1 of Figure 9(a) or columns 0 to C-1 of Figure 9(b). In this case, the first interleaving is performed by interleaving the T 0,5Columns C to 15, and T 0,6 , T 0,7 , and T 1,5 Columns C to 15, and T 1,6 and T 1,7 Set the fourth bit to B 0,5 Columns C to 15, and B 0,6 , B 0,7 , and B 1,5 Columns C to 15, and B 1,6 and B 1,7 where 0≦C≦15. In the following, some specific first interleaving solutions are described.

[0277] In a possible implementation, based on the sixth bit set shown in FIG. 23(d), the square block I 0,0 , I 0,1 , I 0,2 , I 0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I 1,3 , I 1,4 24(a), the square block B of the fourth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 is shown in Figure 9(a). The square block I of the sixth bit set 0,5 and I 1,5 29(a), the square block B of the fourth bit set 0,5 and B 1,5is shown in Figure 30(a). The four shaded areas indicated in Figure 29(a) are all 4x4 square blocks, and three bits in each row of each 4x4 square block are from the second bit set that has been PCS processed, and the remaining one bit in each row is from the third bit set for which no PCS processing is performed. The shaded areas indicated in Figure 30(a) are 16 rows and four columns from column 12 to column 15 of the 16 rows and four columns of the square block, and three bits in each row of each 16 rows and four columns are from the second bit set that has been PCS processed, and the remaining one bit in each row is from the third bit set for which no PCS processing is performed.

[0278] Furthermore, the sixth bit set square block I 0,5 and I 1,5 29(b), 29(c), 29(d), or 29(e), the square block B of the fourth bit set 0,5 and B 1,5 corresponds to the square blocks shown in Figure 30(b), Figure 30(c), Figure 30(d), or Figure 30(e), respectively.

[0279] In the above case, the first interleave is the T 0,5 Columns 12 to 15 of T 0,6 , T 0,7 , and T 1,5 Columns 12 to 15 of the 1,6 and T 1,7 Set the fourth bit to B 0,5 Columns 12 to 15, B 0,6 , B 0,7 , and B 1,5 Columns 12 to 15 of B 1,6 and B 1,7 However, the fourth bit set B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B1,4 is the fifth bit set T 0,0 , T 0,1 , T 0,2 , T 0,3 , T 0,4 , T 1,0 , T 1,1 , T 1,2 , T 1,3 , and T 1,4 The square block B of the fourth bit set is output in the original sequence to obtain 0,5 Columns 0 to 11 and square block B 1,5 Columns 0 to 11 of the square block T 0,5 Columns 0 to 11 and square block T 1,5 The square blocks of the fifth bit set obtained through the first interleaving are shown in FIG. 9(a), in other words, the row i2 and column i3 of each square block of the fifth bit set are output in the original sequence to obtain columns 0 to 11 of the fifth bit set.

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[0280] In another possible implementation, based on the sixth bit set shown in FIG. 23(d), the square block I 0,0 , I 0,1 , I 0,2 , I 0,3 , I 0,4 , I 1,0 , I 1,1 , I 1,2 , I1,3 , and I 1,4 24(b), the square block B of the fourth bit set 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 is shown in Figure 9(b). The square block I of the sixth bit set 0,5 and I 1,5 29(f), the square block B of the fourth bit set 0,5 and B 1,5 is shown in Figure 30(f). In this case, the first interleave is T 0,5 Columns 14 and 15 of T 0,6 , T 0,7 , and T 1,5 Columns 14 and 15 of the 1,6 and T 1,7 Set the fourth bit to B 0,5 Columns 14 and 15 of B 0,6 , B 0,7 , and B 1,5 Columns 14 and 15 of, and B 1,6 and B 1,7 However, the fourth bit set B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 0,4 , B 1,0 , B 1,1 , B 1,2 , B 1,3 , and B 1,4 is the square block T of the fifth bit set 0,0 , T 0,1 , T 0,2 , T 0,3 , T 0,4 , T 1,0 , T 1,1 , T 1,2 , T 1,3 , and T 1,4The square block B of the fourth bit set is output in the original sequence to obtain 0,5 Columns 0 to 13 and square block B 1,5 Columns 0 to 13 of the square block T 0,5 Columns 0 to 13 and square block T 1,5 9B. Each square block of the fifth bit set obtained through the first interleaving is shown in FIG. 9B. In other words, the bits in row i2 and column (j2×2−i2%2+1) of each square block of the fifth bit set are from the second bit set, where 0≦i2<16 and 0≦j2<8. In this case, the specific corresponding interleaving rule of the first interleaving is as follows: bits 94 to 127 of the 128 bits in row r1 of the fifth bit set including m0 square blocks T are from bits 94 to 127 of row r0 of the fourth bit set including m0 square blocks B. Furthermore, there are multiple specific interleaving rules of the first interleaving, which will not be listed one by one in this specification.

[0281] Note that in some specific scenarios, r0=r1 may be satisfied.

[0282] 12 is a diagram of a second implementation of the first interleaving process according to an embodiment of the present application. As shown in FIG. 12, in a possible implementation, 16 bits in each row of the second bit subset are from two first bit subsets. Furthermore, 8 bits of the 16 bits in each row of the second bit subset are from one row in one of the first bit subsets, and the other 8 bits of the 16 bits in each row of the second bit subset are from one row in the other one of the first bit subsets.

[0283] 13 is a diagram of a third implementation of the first interleaving process according to an embodiment of the present application. As shown in FIG. 13, in a possible implementation, the m0×256 bits of the fourth bit set are distributed into 32 rows and m0×8 columns, and the m0×256 bits of the fifth bit set are distributed into 32 rows and m0×8 columns, with 32 bits in each column of the fifth bit set coming from two first bit subsets. More specifically, 16 bits of the 32 bits in each column of the fifth bit set come from one column of one of the first bit subsets, and the other 16 bits of the 32 bits in each column of the fifth bit set come from one column of the other one of the first bit subsets. Furthermore, 16 bits of the 32 bits in each column of the fifth bit set are from column c1%16 of one of the first bit subsets, and the other 16 bits of the 32 bits in each column of the fifth bit set are from column c1%16 of the other one of the first bit subsets, where 0≦c1<(m0×8).

[0284] (3) Second interleave processing In particular, the use of OFEC interleaving for the second interleaving process is used as an example: the OFEC interleaver receives the bits output by the two first interleaver processors and performs "intra-block interleaving" and "inter-block interleaving."

[0285] FIG. 14 is a diagram of intra-block interleaving according to an embodiment of the present application. As shown in FIG. 14, the OFEC interleaver first performs "intra-block interleaving" on each received block. Specifically, to obtain an output block with 16 rows and 16 columns, it performs interleaving on each input block with 16 rows and 16 columns to scramble the sequence according to the interleaving rule shown in FIG. 14. In FIG. 14, the element in row i1 and column j1 (0≦i1<16 and 0≦j1<16) is (a, b), indicating that the bit in row i1 and column j1 of the output block obtained through "intra-block interleaving" comes from the bit in row a and column b of the input block. For example, in FIG. 14, the element in row 1 and column 0 is (14, 15), indicating that the bit in row 1 and column 0 of the output block obtained through "intra-block interleaving" comes from the bit in row 14 and column 15 of the input block.

[0286] "Inter-block interleaving" is performed on the "intra-block interleaved" bits to improve the overall anti-burst performance. The operation of inter-block interleaving is described below.

[0287] 15 is a diagram of inter-block interleaving according to an embodiment of the present application. As shown in FIG. 15, the inter-block interleaving includes an interleaver buffer M with 84 rows and 8 columns, where each row includes 8 blocks and each block includes a total of 256 bits in 16 rows and 16 columns. The size of the interleaver buffer of the inter-block interleaving is 84×8×256=172032 bits, corresponding to 172032 / 4096=42 output blocks of the first interleaver processors, where 21 output blocks are from one output block of the first interleaver processors and are in the even rows of the interleaver buffer M, and the other 21 output blocks are from another output block of the first interleaver processors and are in the odd rows of the interleaver buffer M. In this specification, the output blocks of each first interleaver processor are a set of 2 rows and 8 columns of blocks, totaling 4096 bits. The interleaver buffer M for block interleaving may be divided into four sets. As shown in FIG. 15, set 0 includes a total of 21×16×128=43008 bits in blocks in rows 0, 2, 4, ..., and 40 of interleaver buffer M; set 1 includes a total of 43008 bits in blocks in rows 1, 3, 5, ..., and 41 of interleaver buffer M; set 2 includes a total of 43008 bits in blocks in rows 42, 44, 46, ..., and 82 of interleaver buffer M; and set 3 includes a total of 43008 bits in blocks in rows 43, 45, 47, ..., and 83 of interleaver buffer M.

[0288] The bits of each column are read from each set in a round-robin manner by using 8 bits as the granularity in the interleaver buffer M, and after all the bits of each column are read, the bits of the next column are read. First, the first 8 bits of the group are read from top to bottom in set 0, then the first 8 bits are read from top to bottom in each of sets 1, 2, and 3. A total of 32 bits are read in a cycle. Then, in the next cycle, the next group of 8 bits are read from top to bottom in each of sets 0, 1, 2, and 3. A total of 32 bits are read. After a total of 42 cycles, 1344 bits of the current column are read. The specific operations for reading the bits of each column from each set are as follows: First, 8 bits (bit rows 0 to 7 of the block) are read out sequentially from top to bottom in the block of row 0 of the interleaver buffer M; In the block of row 1 of the interleaver buffer M, 8 bits are read out sequentially from top to bottom (bit rows 0 to 7 of the block); In the block of row 42 of the interleaver buffer M, eight bits are read out sequentially from top to bottom (bit rows 0 to 7 of the block); In the block of row 43 of the interleaver buffer M, eight bits are read out sequentially from top to bottom (bit rows 0 to 7 of the block); In the block of row 0 of the interleaver buffer M, 8 bits are read out sequentially from top to bottom (bit rows 8 to 15 of the block); In the block of row 1 of the interleaver buffer M, 8 bits are read out sequentially from top to bottom (bit rows 8 to 15 of the block); In the block of row 42 of the interleaver buffer M, eight bits are read out sequentially from top to bottom (bit rows 8 to 15 of the block); In the block of row 43 of the interleaver buffer M, eight bits are read out sequentially from top to bottom (bit rows 8 to 15 of the block); Then, the 8 bits in the block of row 2 of the interleaver buffer M are read out sequentially from top to bottom (bit rows 0 to 7 of the block); ..., until a total of 1344 bits in the current bit stream of the interleaver buffer M have been completely read out.

[0289] (4) Symbol mapping and polarization distribution The bit data output through OFEC interleaving is sent to symbol mapping and polarization distribution to obtain dual-polarized symbols. As shown in Figure 4, two OFEC interleavers, OFEC interleaver 0 and OFEC interleaver 1, send bits to symbol mapping in a round-robin manner by using 8 bits as a group. When dual-polarized 16QAM modulation (DP-16QAM) is used, 8 bits (b0, b1, b2, b3, b4, b5, b6, b7) are mapped to one DP-16QAM symbol in the symbol mapping and polarization distribution. A first symbol mapping scheme is considered as follows: (b0, b2) is mapped to the I in-phase component of the X polarization of the DP-16QAM symbol, denoted as XI; (b4, b6) is mapped to the Q quadrature-phase component of the X polarization of the DP-16QAM symbol, denoted as XQ; (b1, b3) is mapped to the I in-phase component of the Y polarization of the DP-16QAM symbol, denoted as YI; and (b5, b7) is mapped to the Q quadrature-phase component of the Y polarization of the DP-16QAM symbol, denoted as YQ. For each signaling dimension XI / XQ / YI / YQ, two bits are mapped to the corresponding symbol amplitude in the following mapping scheme: (0,0) → -3, (0,1) → -1, (1,1) → +1, (1,0) → +3

[0290] In this case, of the 8 bits (b0, b1, b2, b3, b4, b5, b6, b7), b0 and b4 are two sign bits in 16QAM in the X polarization direction, b2 and b6 are two amplitude bits in 16QAM in the X polarization direction, b1 and b5 are two sign bits in 16QAM in the Y polarization direction, and b3 and b7 are two amplitude bits in 16QAM in the Y polarization direction.

[0291] Any block containing 256 bits of the set T of square blocks with 2 rows and 8 columns output by the first interleaving process shown in Figure 9(a)

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[0292] 16 is another diagram of intra-block interleaving according to an embodiment of the present application.

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[0293] Because "inter-block interleaving" does not disturb the bit sequence within a block, after "inter-block interleaving" of OFEC interleaving, the 16 bits in row 2, row 3, row 6, row 7, row 10, row 11, row 14, or row 15 of any output block with 16 rows and 16 columns are all 16 bits among the 2048 third bits obtained by PCS processing. Furthermore, by using the first symbol mapping and polarization distribution, the positions of the constellation points may remain unchanged, but the occurrence probabilities of the constellation points may be changed so that the constellation points are not evenly distributed, in order to implement PCS and improve the transmission performance of the system.

[0294] It should be noted that in some specific embodiments, in the symbol mapping and polarization distribution, each 8 bits (b0, b1, b2, b3, b4, b5, b6, b7) is mapped to one DP-16QAM symbol. The following second symbol mapping scheme is considered: (b0, b1) is mapped to the in-phase component of the X polarization of the DP-16QAM symbol, denoted as XI; (b2, b3) is mapped to the quadrature-phase component of the X polarization of the DP-16QAM symbol, denoted as XQ; (b4, b5) is mapped to the in-phase component of the Y polarization of the DP-16QAM symbol, denoted as YI; and (b6, b7) is mapped to the quadrature-phase component of the Y polarization of the DP-16QAM symbol, denoted as YQ. In each signaling dimension XI / XQ / YI / YQ, two bits are mapped to the corresponding symbol amplitude in the following mapping manner: (0,0) → -3, (0,1) → -1, (1,1) → +1, (1,0) → +3

[0295] In this case, b0 and b2 of the 8 bits (b0, b1, b2, b3, b4, b5, b6, b7) are two sign bits in 16QAM in the X polarization direction, b1 and b3 are two amplitude bits in 16QAM in the X polarization direction, b4 and b6 are two sign bits in 16QAM in the Y polarization direction, and b5 and b7 are two amplitude bits in 16QAM in the Y polarization direction.

[0296] Any block containing 256 bits of the set T of square blocks with 2 rows and 8 columns output by the first interleaving process shown in Figure 9(b)

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[0297] (5) DSP Framing The DSP framing is performed by inserting FAW, TS, RES, and PS separately into the X-polarized and Y-polarized symbols of the dual-polarized symbol stream obtained by symbol mapping and polarization distribution to obtain a dual-polarized symbol stream to be transmitted.

[0298] In a typical DSP framing, 172032 dual-polarized symbols are framed to obtain 175104 dual-polarized symbols, also called a superframe, and the overhead of a superframe is:

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[0299] It should be noted that in some specific applications, the above statements "the bit data output through OFEC interleaving is sent to symbol mapping and polarization distribution to obtain dual-polarized symbols" and "DSP framing is performed by separately inserting FAW, TS, RES, and PS into the X-polarized symbols and Y-polarized symbols of the dual-polarized symbol stream obtained by symbol mapping and polarization distribution to obtain a dual-polarized symbol stream to be transmitted" may be equivalent to the following operations: First, the bit data output through OFEC interleaving is inserted into a bit sequence corresponding to the FAW frame alignment word symbol, TS training symbol, RES reserved symbol, and PS pilot symbol before modulation and mapping, and then symbol mapping and polarization distribution are performed to obtain the same dual-polarized symbol stream to be transmitted. These specific operations will not be described in detail in this application.

[0300] The data frame rate is W bit Gbit / s, in the first data processing, CRC check and / or pad bit insertion is performed on r rows of data taken from the data frame, and then scrambling is performed by 10280×r Frame + d CRC+PAD is performed to obtain scrambled bits, and the corresponding scrambling rate is W × (10280 × r Frame + d CP ) / (10280×r Frame ) Gbit / s. PCS and OFEC coding, first interleaving, OFEC interleaving, 16QAM symbol mapping and polarization distribution, and

number

[0301] [Table 1]

[0302] Typical low power consumption components in the industry have a maximum baud rate of approximately 131 Gbaud. baud Tables 2 and 3 show the number of data lines, r, the total number of bits for CRC check and padding, d, and the total number of bits for padding. CP , the number of input bits for PCS processing and OFEC encoding k, the number of input bits for PCS processing k PCS , overhead OH corresponding to CRC check and pad bit insertion CP Table 2 shows the combination of multiple parameters obtained from the data frame each time, including the baud rate when using the data frame types FlexO-6e, FlexO-6, FlexO-8e, and FlexO-8, and the corresponding baud rate when using the data frame types FlexO-6e, FlexO-6, FlexO-8e, and FlexO-8. ... CP We show all parameter combinations for which the overhead is less than or equal to 0.1% and therefore does not affect the overall system transmission efficiency.

[0303] The number of scrambled bits output by the first data processing, d scr =10280×r Frame +d CP is an integer multiple of 4 × k, so the specific hardware implementation of the entire data processing is simple and consumes little power. PCS = k - 1504 is an integer multiple of 2, so the PCS processing is convenient for hardware implementation and has excellent performance. scr / k × 4096 OFEC coded bits are output by the first data processing. scr is obtained by performing PCS processing and OFEC encoding on the scrambled bits, scr / k×4096 is an integer multiple of the total size of the two OFEC interleavers, 172032×2=344064, and therefore the specific hardware implementation of the entire data processing is simple and consumes little power.

[0304] A given parameter combination in one row of Table 2 or Table 3 below, i.e., r Frame , d CP Note that for , and k, some of the baud rates corresponding to data frame types FlexO-6e, FlexO-6, FlexO-8e, and FlexO-8 may be higher than 132 Gbaud, indicating that the parameter combination is not applicable to the data frame type and is shown in the table with a dark background color. For a given parameter combination in one row of Table 2 below, i.e., r Frame , d CP Note that for , and k, some of the baud rates corresponding to data frame types FlexO-6e, FlexO-6, FlexO-8e, and FlexO-8 may be lower than 110 Gbaud, indicating that the parameter combinations are also not applicable to the data frame types and are shown in the table with a darker background color. For example, the parameter combination {r Frame =79, d CPFor {k=328, and k=3224}, the baud rates when the data frame types FlexO-6e, FlexO-6, FlexO-8e, and FlexO-8 are used are 97.6 Gbaud, 103.5 Gbaud, 130.2 Gbaud, and 136.7 Gbaud, respectively. When the data frame types FlexO-6e and FlexO-6 are used, a baud rate lower than 110 Gbaud indicates that the parameter combination is not applicable to the data frame types FlexO-6e and FlexO-6, as indicated by a darker background color in the table. When the data frame type FlexO-8 is used, a baud rate higher than 132 Gbaud indicates that the parameter combination is not applicable to the data frame type FlexO-8, as indicated by a darker background color in the table. When the data frame type FlexO-8e is used, a baud rate higher than 110 Gbaud but lower than 132 Gbaud indicates that the parameter combination is applicable to the data frame type FlexO-8e. As another example, the parameter combination {r Frame =87, d CP =72, and k=2662}, the baud rates when the data frame types FlexO-6e, FlexO-6, FlexO-8e, and FlexO-8 are used are 118.2 Gbaud, 124.1 Gbaud, 157.6 Gbaud, and 165.5 Gbaud, respectively. When the data frame types FlexO-8e and FlexO-8 are used, a baud rate higher than 132 Gbaud indicates that the parameter combination is not applicable to the data frame types FlexO-8e and FlexO-8, which is shown with a dark background color in the table. When the data frame types FlexO-6e and FlexO-6 are used, a baud rate higher than 110 Gbaud and lower than 132 Gbaud indicates that the parameter combination is applicable to the data frame types FlexO-6e and FlexO-6.

[0305] [Table 2A] [Table 2B] [Table 2C]

[0306] [Table 3A] [Table 3B] [Table 3C] [Table 3D] [Table 3E] [Table 3F] [Table 3G] [Table 3H]

[0307] d scr = 336 × k, then d scr After the PCS processing, OFEC encoding, and first interleaving on the scrambled bits,

number

[0308] From the above description of the first and second data processing, it can be seen that FEC coding is used in combination with PCS technology to meet the requirements for longer transmission distances for future urban telecommunication transmission and urban DCI interconnection scenarios. Due to the introduction of PCS processing, during symbol mapping, sign bits that are 0 and 1 must be mapped to a modulation symbol with equal probability, while amplitude bits that are 0 and 1 must be mapped to a modulation symbol with unequal probability. OFEC coding is used as an example of FEC coding. To avoid impact on existing OFEC coding and OFEC interleavers, a new interleaver needs to be introduced after OFEC coding and before the symbol mapping operation so that PCS-processed bits that are 0 and 1 with unequal probability can be mapped to amplitude bits of modulation symbols. In this way, to meet the requirements for longer transmission distances in the future, the occurrence probabilities of constellation points are changed while the positions of the constellation points remain unchanged, so that the constellation points are not evenly distributed, thereby improving overall performance. In addition, with the introduction of PCS processing, the length of information bits on which PCS processing and FEC encoding are performed is no longer 3552 but a smaller value. In this case, the number of rows of data obtained from the data frame needs to be redesigned, and the number of CRC checks and pad bits inserted needs to be redesigned so that the overall data processing operation becomes simpler, less complex, and consumes less power.

[0309] In the following, some specific embodiments will be described in relation to the first and second data processing described above.

[0310] Embodiment 1 Considering the data frame rate of 800G, one data frame contains 512 rows, and each row contains 10280 bits. Frame =110, d CP=848, and k=3368} are considered. In the first data processing, r Frame = 110 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 1130800 bits. p = 22 is considered.

[0311] 17(a) is a diagram of an implementation of performing a CRC on a data frame according to an embodiment of the present application. As shown in FIG. 17(a), the CRC-32 check is first performed by:

number

number

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[0312] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L = 4 PCS and OFEC encoding in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, in the PCS and OFEC encoding, k = 3368 input bits are sent to L = 4 PCS and OFEC encoding in a round-robin manner. PCS =k-1504=1864 bits are sent to the PCS process to get 2048 bits. k=3368 bits is k PCS=k-1504=18 Contains 64 bits and 1504 bits.

[0313] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 256 bits LUT = 233 input bits each time, and after LUT mapping is performed 8 times in succession, i.e., after LUT mapping is performed for a total of k - 1504 = 1864 bits, the corresponding 2048 bits are output.

[0314] The 2048 bits and 1504 bits output by the PCS processing, i.e., a total of 2048 + 1504 = 3552 bits, are sent to OFEC encoding for encoding to insert 544 OFEC parity bits, to obtain a total of 4096 OFEC coded bits, i.e., the fourth bit set. The 4096 bits are represented by using the set of blocks shown in Figure 11(a), and the PCS processed 2048 bits are divided into eight square blocks B shown in Figure 11(a). 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 Corresponds to.

[0315] A first interleaving operation is performed on the fourth bit set (4096 bits) to obtain an interleaved fifth bit set, where bit c1 of the 128 bits of row r1 of the interleaved fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

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[0316] Here, r0 = r1. All square blocks of the interleaved fifth bit set obtained by the first interleaving process

number

number

[0317] Obtained by the first interleaving process

number

[0318] If the rate of a given data frame is Wbit Gbit / s, the corresponding baud rate is W baud =W bit ×(10280×r Frame +d CP ) / (10280×r Frame ) × (4096 / k) × (57 / 56) / 8 Gbaud. The baud rates corresponding to the data frame types FlexO-8e and FlexO-8 are 124.7 Gbaud and 130.9 Gbaud, respectively.

[0319] Embodiment 2 Considering the data frame rate of 600G, one data frame contains 384 rows, and each row contains 10280 bits. Frame =87, d CP = 744, and k = 2664} are considered. In the first data processing, r = 87 rows of data are retrieved from the data frame, and a total of d in =10280×r Frame = 894360 bits. p = 3 is considered. CRC-32 check is done first.

number

number

number

[0320] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L = 4 PCS and OFEC encoding in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, in the PCS and OFEC encoding, k bits out of k = 2664 input bits are sent to L = 4 PCS and OFEC encoding in a round-robin manner. PCS =k-1504=1160 bits are sent to PCS processing to obtain 2048 bits. k=2664 bits is k PCS =k-1504=Contains 1160 bits and 1504 bits.

[0321] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 256 bits LUT = 145 input bits each time, and after LUT mapping is performed 8 times in succession, i.e., after LUT mapping is performed for a total of k - 1504 = 1160 bits, the corresponding 2048 bits are output.

[0322] The 2048 bits and 1504 bits output by the PCS processing, totaling 2048 + 1504 = 3552 bits, are sent to OFEC encoding for encoding to insert 544 OFEC parity bits, to obtain a total of 4096 OFEC coded bits, i.e., the fourth bit set. The 4096 bits are represented by using the set of blocks shown in Figure 11(a), and the PCS processed 2048 bits are divided into eight square blocks B shown in Figure 11(a). 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 Corresponds to.

[0323] A first interleaving operation is performed on the fourth bit set to obtain an interleaved fifth bit set, where bit c1 of the 128 bits of row r1 of the interleaved fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

number

number

[0324] Here, r0 = r1. Any block of the fifth set of bits obtained by the first interleaving process

number

number

[0325] Obtained by the first interleaving process

number

[0326] If the rate of a given data frame is W bit Gbit / s, the corresponding baud rate is W baud =W bit ×(10280×r Frame +d CP ) / (10280×r Frame ) × (4096 / k) × (57 / 56) / 8 Gbaud. The baud rates corresponding to the data frame types FlexO-6e and FlexO-6 are 118.2 Gbaud and 124.1 Gbaud, respectively.

[0327] Embodiment 3 Considering the data frame rate of 600G, one data frame contains 384 rows, and each row contains 10280 bits. Frame =105, d CP = 504, and k = 3214} are considered. In the first data processing, r Frame = 105 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 1079400 bits. p = 15 is considered. CRC-32 check is done first.

number

number

number

[0328] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L=4 PCS and OFEC encoding in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, in the PCS and OFEC encoding, k bits out of k=3214 input bits are sent to L=4 PCS and OFEC encoding in a round-robin manner. PCS =k-1504=1710 bits are sent to PCS processing to obtain 2048 bits. k=3214 bits are PCS =k-1504=1710 bits and 1504 bits.

[0329] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 1024 bits LUT = 855 input bits each time, and after the LUT mapping is performed twice consecutively, i.e., after the LUT mapping is performed for a total of k - 1504 = 1710 bits, the corresponding 2048 bits are output.

[0330] The 2048 bits and 1504 bits output by the PCS processing, totaling 2048 + 1504 = 3552 bits, are sent to OFEC encoding for encoding to insert 544 OFEC parity bits, to obtain a total of 4096 OFEC coded bits, i.e., the fourth bit set. The 4096 bits are represented by using the set of blocks shown in Figure 11(b), and the PCS processed 2048 bits are divided into eight square blocks B shown in Figure 11(b). 0,0 , B 0,1 , B 0,4 , B 0,5 , B 1,0 , B 1,1 , B 1,4 , and B 1,5 Corresponds to.

[0331] A first interleaving operation is performed on the fourth bit set to obtain an interleaved fifth bit set, where bit c1 of the 128 bits of row r1 of the interleaved fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

number

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[0332] Here, r0 = r1. Any block in the set of interleaved blocks obtained by the first interleaving process

number

number

[0333] Obtained by the first interleaving process

number

[0334] If the rate of a given data frame is W bit Gbit / s, the corresponding baud rate is W baud =W bit ×(10280×r Frame +d CP ) / (10280×r Frame ) × (4096 / k) × (57 / 56) / 8 Gbaud. The baud rate corresponding to the data frame type FlexO-6e is 130.6 Gbaud.

[0335] Embodiment 4 Considering the data frame rate of 600G, one data frame contains 384 rows, and each row contains 10280 bits. Frame =261, d CP =2232, and k=2664} are considered. In the first data processing, r Frame = 261 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 2683080 bits. p = 29 is considered. CRC-32 check is done first.

number

number

number

[0336] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L = 4 PCS and OFEC encoding in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, in the PCS and OFEC encoding, k bits out of k = 2664 input bits are sent to L = 4 PCS and OFEC encoding in a round-robin manner. PCS =k-1504=1160 bits are sent to PCS processing to obtain 2048 bits. k=2664 bits is k PCS=k-1504=Contains 1160 bits and 1504 bits.

[0337] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 512 bits LUT = 290 input bits each time, and after the LUT mapping is performed four times in succession, i.e., after the LUT mapping is performed for a total of k - 1504 = 1160 bits, the corresponding 2048 bits are output. In some other specific embodiments, a LUT lookup table is used in the PCS processing, and the LUT mapping is performed for the corresponding n LUT = k to output 256 bits LUT = 145 input bits each time, and after LUT mapping has been performed eight consecutive times, i.e., after LUT mapping has been performed for a total of k - 1504 = 1160 bits, the corresponding 2048 bits are output.

[0338] The 2048 bits and 1504 bits output by the PCS processing, totaling 2048 + 1504 = 3552 bits, are sent to OFEC encoding for encoding to insert 544 OFEC parity bits, to obtain a total of 4096 OFEC coded bits, i.e., the fourth bit set. The 4096 bits are represented by using the set of blocks shown in Figure 11(b), and the PCS processed 2048 bits are divided into eight square blocks B shown in Figure 11(b). 0,0 , B 0,1 , B 0,4 , B 0,5 , B 1,0 , B 1,1 , B 1,4 , and B 1,5 Corresponds to.

[0339] A first interleaving operation is performed on the fourth bit set to obtain an interleaved fifth bit set, where bit c1 of the 128 bits of row r1 of the interleaved fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

number

number

[0340] Here, r0 = r1. Any block in the set of interleaved blocks obtained by the first interleaving process

number

number

[0341] Obtained by the first interleaving process

number

[0342] d scr ≠ 336 × k, and d scr ×F Frame =336×k×F DSP is considered, F Frame =1 and F DSP = 3, and F DSP superframes are F Frame = d output by one first data processing scr ×F Frame = 4128768 bits, F DSP Note that a total of F = 3 superframes may be used as a combination. The RES reserved symbols inserted in each superframe are used by the receiver to Frame = d output by one first data processing scr ×F Frame = 4128768 bits to identify the boundary. DSP= 3 superframes can be specified.

[0343] The specific implementation of the RES reserved symbols inserted in each superframe is as follows: DSP Note that for F = 3 superframes, 22 consecutive RES reserved symbols in superframe 0 are a specific first marker sequence (sometimes also referred to as first marker symbols), and 22 consecutive RES reserved symbols in superframe 1 and superframe 2 are a specific second marker sequence (sometimes also referred to as second marker symbols), where the first marker sequence is different from the second marker sequence. After performing DSP superframe alignment, the receiver can derive F by identifying the first marker sequence and the second marker sequence. DSP = 3 superframe combination boundary. The first marker and the second marker are F DSP Superframe alignment signal (F DSP The RES reserved symbols remaining after the first or second marker is deleted may also be referred to as fixed stuff (FS). In some specific implementations, the specific values ​​of the first marker sequence and the second marker sequence are shown in Table 4, and the 16QAM symbols of the two polarization directions corresponding to the first marker sequence and the second marker sequence may be obtained by 16QAM symbol mapping to the sequences.

[0344] [Table 4]

[0345] If the rate of a given data frame is W bit Gbit / s, the corresponding baud rate is W baud =W bit×(10280×r Frame + d CP ) / (10280×r Frame ) × (4096 / k) × (57 / 56) / 8 Gbaud. The baud rate corresponding to the data frame type FlexO-6e is 118.203 Gbaud. The baud rate corresponding to the data frame type FlexO-6 is 124.102 Gbaud.

[0346] In some specific scenarios, a superframe containing 172032 dual-polarized symbols is also called a multi-frame, and an F containing 172032 × 3 dual-polarized symbols is also called a multi-frame. DSP Note that =3 multiframes are also called one superframe.

[0347] Embodiment 5 Considering the data frame rate of 800G, one data frame contains 512 rows, and each row contains 10280 bits. Frame =261, d CP = 1560, and k = 3196} are considered. In the first data processing, r Frame = 261 rows of data are retrieved from the data frame, totaling d in =10280×r Frame =2683080 bits are obtained.

[0348] p=29 is considered. The CRC-32 check is performed first.

number

number

number

[0349] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L = 4 PCS and OFEC encoding in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, in the PCS and OFEC encoding, k = 3196 input bits are sent to L = 4 PCS and OFEC encoding in a round-robin manner. PCS =k-1504=1692 bits are sent to PCS processing to obtain 2048 bits. k=3196 bits is k PCS =k-1504=Contains 1692 bits and 1504 bits.

[0350] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 512 bits LUT = 423 input bits each time, and after LUT mapping is performed four times in succession, i.e., after LUT mapping is performed for a total of k - 1504 = 1692 bits, the corresponding 2048 bits are output.

[0351] The 2048 bits and 1504 bits output by the PCS processing, totaling 2048 + 1504 = 3552 bits, are sent to OFEC encoding for encoding to insert 544 OFEC parity bits, to obtain a total of 4096 OFEC coded bits, i.e., the fourth bit set. The 4096 bits are represented by using the set of blocks shown in Figure 11(a), and the PCS processed 2048 bits are divided into eight square blocks B shown in Figure 11(a). 0,0 , B 0,1 , B 0,2 , B0,3 , B 1,0 , B 1,1 , B 1,2 , and B 1,3 Corresponds to.

[0352] A first interleaving operation is performed on the fourth bit set (4096 bits) to obtain an interleaved fifth bit set, where bit c1 of the 128 bits of row r1 of the interleaved fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

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[0353] Here, r0 = r1. Any square block of the fifth set of interleaved bits obtained by the first interleaving process

number

number

[0354] Obtained by the first interleaving process

number

[0355] d scr ≠ 336 × k, and d scr ×F Frame =336×k×F DSP is considered, F Frame = 2 and F DSP Note that =5. In other words, F Frame = d output by the first data processing twice scr ×F Frame = 5369280 bits correspond to 860160 dual-polarized symbols. To obtain one superframe containing 175104 dual-polarized symbols, DSP framing is performed for each of the 172032 dual-polarized symbols in the 860160 = 172032 × 5 dual-polarized symbols. Specifically, FAW frame alignment word symbols, TS training symbols, RES reserved symbols, and PS pilot symbols are inserted into the X and Y polarization symbols. A total of five superframes are obtained and then transmitted. Typically, a superframe contains 74 RES reserved symbols.

[0356] F DSP = 5 superframes are F Frame = d output by the first data processing twice scr ×F Frame = 5369280 bits, F DSP= 5 superframes are used as a combination. The RES reserved symbols inserted in each superframe are used by the receiver to Frame = d output by the first two data processing scr ×F Frame = 5369280 bits to identify the boundary. DSP = 5 superframes can be specified.

[0357] The specific implementation of the RES reserved symbols inserted in each superframe is as follows: DSP Note that for F = 5 superframes, 22 consecutive RES reserved symbols in superframe 0 are a specific first marker sequence, and 22 consecutive RES reserved symbols in superframe 1 and superframe 4 are a specific second marker sequence, where the first marker sequence is different from the second marker sequence. After performing DSP superframe alignment, the receiver can derive F by identifying the first marker sequence and the second marker sequence. DSP The boundaries of the combinations of F = 5 superframes may be obtained. The specific implementation of "RES reserved symbols inserted in each superframe" is as follows: DSP For F = 5 superframes, 22 consecutive RES reserved symbols in superframe 0 and superframe 1 are a specific first marker sequence (sometimes referred to as first marker symbols), and 22 consecutive RES reserved symbols in superframe 2 through superframe 4 are a specific second marker sequence (sometimes referred to as second marker symbols), where the first marker sequence is different from the second marker sequence. After performing DSP superframe alignment, the receiver can determine F by identifying the first marker sequence and the second marker sequence. DSP The first marker and the second marker may be used to obtain the boundary of a combination of F = 5 superframes.DSP Superframe alignment marker (F DSP The RES reserved symbols remaining after the first or second marker is removed are also referred to as fixed stuff (FS). In some specific implementations, the specific values ​​of the first marker symbol and the second marker symbol are shown in Table 5.

[0358] [Table 5]

[0359] If the rate of a given data frame is W bit Gbit / s, the corresponding baud rate is W baud =W bit ×(10280×r Frame +d CP ) / (10280×r Frame ) × (4096 / k) × (57 / 56) / 8 Gbaud. The baud rate corresponding to the data frame type FlexO-8e is 131.337 Gbaud.

[0360] In some specific scenarios, a superframe containing 175104 dual-polarized symbols is also called a multi-frame, and an F containing 175104 × 5 dual-polarized symbols is also called a multi-frame. DSP Note that =5 multiframes are also called one superframe.

[0361] Embodiment 6 Considering a data frame with a rate of 600G, each row of one data frame contains q bits. Frame The row data is retrieved from the data frame and the total d in =q×r Frame d) obtain the first data bits, and then CRC and / or pad bit insertion is performed on the first data to obtain the second data bits. CRCCRC parity bits are added in the CRC operation, and d PAD Pad bits are inserted in the pad insertion operation. Furthermore, the second data is scrambled to obtain third data, and the number of bits of the third data is d scr =q×r Frame +d CP scrambled bits, and d CP =d CRC +d PAD PCS and OFEC encoding, first interleaving, OFEC interleaving, and 16QAM symbol mapping and polarization distribution are performed on the scrambled bit data to obtain 172032 dual-polarized symbols, resulting in overhead.

number

[0362] The baud rate for data processing is W baud = W bit ×(q×r Frame +d CP ) / (q×r Frame )×(4096 / k)×(57 / 56) / 8 Gbaud, and W bit is a specific bit rate value corresponding to a 600G data frame. In this embodiment, in a 600G rate scenario where PCS is used, the corresponding baud rate W baud is the same as the baud rate of the existing 800G ZR baud rate scenario, and Equation 2 is as follows:

number

number

[0363] In other words, Equation 3 is:

number

number

[0364] In this embodiment, d in =q×r Frame = 894360 bits of first data are obtained from the data frame by the first data processing, and the first data is stored in the data frame.

number

number

[0365] The overhead for CRC checking and padding is

number

[0366] In PCS processing, input k LUT The bit is LUTThe number of output bits in the PCS process is n. LUT cannot be made too small, otherwise the performance of the entire PCS process will be deteriorated. The number of output bits of the PCS process, n LUT cannot be too large. Otherwise, the number of output bits of the PCS process, n LUT is not conducive to hardware implementation. LUT = 128 or 256. LUT When n = 128, in the PCS processing, after the LUT mapping is performed 2048 / 128 = 16 times consecutively, that is, after the LUT mapping is performed for a total of k-1504 bits (first bit set), the corresponding 2048 bits (corresponding to the second bit set) are output, and the integer k-1504 is an integer multiple of 16. LUT = 256, in PCS processing, after LUT mapping is performed 2048 / 256 = 8 times in succession, i.e., after LUT mapping is performed on a total of k-1504 bits (first bit set), corresponding 2048 bits (corresponding to the second bit set) are output, and the integer k-1504 is an integer multiple of 8. Therefore, the integer k-1504 is an integer multiple of 8.

[0367] Overhead is

number

[0368] Parameter combination of serial number 1 in Table 6 {r Frame=87, d CP =744, and k=2664} is used, the number of bits n output using the lookup table in the PCS process is LUT The minimum value of is 256, and the overhead of CRC and PAD is OH CP Note that the parameter combination {r Frame =87, d CP =3432, and k=2672} is used, the number of bits n output using the lookup table in the PCS process LUT The minimum value of is 128, and the overhead of CRC and PAD is OH CP = 0.384%. For the combination of the two parameters, the specific implementation complexity of the lookup table for PCS processing corresponding to serial number 1 is high, but the overhead of CRC and PAD, OH CP is small, and the specific implementation complexity of the PCS lookup table corresponding to serial number 2 is low, but the overhead of CRC and PAD, OH CP The combination of parameters in Serial No. 1 or Serial No. 2 may be selected based on the specific application scenario of the implementation.

[0369] [Table 6]

[0370] Parameter combination of serial number 2 in Table 6 {r Frame =87, d CP Note that for {p = 3432, and k = 2672}, the parameter p = 29 is selected. Correspondingly, in the first data processing, r Frame = 87 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 894360 bits. CRC-32 check is performed first.

number

number

[0371] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L=4 PCS and OFEC encoding in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, in the PCS and OFEC encoding, k bits out of k=2672 input bits are sent to L=4 PCS and OFEC encoding in a round-robin manner. PCS =k-1504=1168 bits are sent to the PCS process to get 2048 bits. k=2672 bits are sent to the PCS process. PCS =k-1504=1168 bits and the remaining 1504 bits.

[0372] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 128 bits LUT = 73 input bits each time, and after LUT mapping has been performed 16 times in succession, i.e., after LUT mapping has been performed for a total of k - 1504 = 1168 bits, the corresponding 2048 bits are output.

[0373] The 2048 bits and 1504 bits output by the PCS processing, totaling 2048 + 1504 = 3552 bits, are sent to OFEC encoding for encoding to insert 544 OFEC parity bits, to obtain a total of 4096 OFEC coded bits, i.e., the fourth bit set. The 4096 bits are represented by using the set of blocks shown in Figure 11(b), and the PCS processed 2048 bits are divided into eight square blocks B shown in Figure 11(b). 0,0 , B 0,1 , B 0,4 , B 0,5 , B 1,0 , B 1,1 , B 1,4 , and B 1,5 Corresponds to.

[0374] The positions of the 2048 bits of the second bit set in the codeword for FEC encoding are non-contiguous. In this case, a pre-encoding interleaving process is further performed to scramble the sequence so that when the second and third bit sets are sent to FEC encoding, the sequence of 3552 bits before encoding is as follows: first 1024 consecutive bits from the second bit set, then 1024 consecutive bits from the third bit set, then 1024 consecutive bits from the second bit set, and finally 480 consecutive bits from the third bit set.

[0375] A first interleaving operation is performed on the fourth bit set to obtain an interleaved fifth bit set, where bit c1 of the 128 bits of row r1 of the interleaved fifth bit set is from bit c0 of the 128 bits of row r0 of the fourth bit set;

number

number

[0376] Here, r0 = r1. Any block in the set of interleaved blocks obtained by the first interleaving process

number

number

[0377] Obtained by the first interleaving process

number

[0378] If the rate of a given data frame is W bitGbit / s, the corresponding baud rate is W baud =W bit ×(10280×r Frame +d CP ) / (10280×r Frame ) × (4096 / k) × (57 / 56) / 8 Gbaud. The baud rate corresponding to the data frame type FlexO-6e is 118.203 Gbaud, which is the same as the baud rate of 800ZR.

[0379] Embodiment 7 17(b) is a diagram of another implementation of performing CRC on a data frame according to an embodiment of the present application. Frame =87, d CP =3432, and k=2672} are considered, and the parameter p=18 is selected. Refer to FIG. 17(b) for understanding. Correspondingly, in the first data processing, r Frame = 87 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 894360 bits to get integer

number

[0380] Embodiment 8 17(c) is a diagram of another implementation of performing CRC on a data frame according to an embodiment of the present application. Frame =87, d CP =3432, and k=2672} are considered, and the parameter p=22 is selected. For understanding, refer to FIG. 17(c). Correspondingly, in the first data processing, r Frame = 87 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 894360 bits to get integer

number

[0381] Note that in the above scenario, each row of the data frame is considered to contain q=10280 bits. In some other possible scenarios, each row of the data frame contains q=2056 bits. In the example, the parameter combination {q=2056, r Frame =435, d CP =3432, and k=2672} is considered, and the parameter p=22 is selected. In this case, in the first data processing, r Frame = 435 rows of data are retrieved from the data frame, totaling d in =q×r Frame = 894360 bits to get integer

number

[0382] Parameter combination of serial number 1 in Table 6 {r Frame =87, d CP = 744, and k = 2664} applies to a scenario where each row of the data frame contains q = 10280 bits. For a scenario where each row of the data frame contains q = 2056 bits, the parameter combination {q = 2056, r Frame =435, d CP =744, and k=2664} is considered, and the parameter p=22 is selected. In this case, in the first data processing, r Frame = 435 rows of data are retrieved from the data frame, totaling d in =q×r Frame = 894360 bits to get integer

number

[0383] The behavior of CRC-32 is Frame = the first r of 435 rows of data F0 ×(p-1)=r in 420 rows F0 = Total q × r for each of the 20 rows F0 Note that in the scenario where the CRC-32 operation is performed on r = 41120 bits, the CRC-32 operation of the existing 800G ZR may be directly used as the CRC-32 encoding and detection operation, the difference being that in the existing 800G ZR, the CRC-32 operation is performed on a total of 4 × 10280 = 41120 bits in 4 rows and 10280 columns. Frame = the last r of 435 rows of data F1 = Total q × r in 15 rows F1 It should be understood that in a scenario performed on =30840 bits, the CRC-32 encoding and detection operations may still use similar operations of the 800G ZR CRC-32, but with a different quantity of input bits.

[0384] Embodiment 9 Considering a data frame with a rate of 800G, each row of one data frame contains q=10280 bits. Frame The row data is retrieved from the data frame and the total d in =q×rFrame d) obtain the first data bits, and then CRC and / or pad bit insertion is performed on the first data to obtain the second data bits. CRC CRC parity bits are added in the CRC operation, and d PAD Pad bits are inserted in the pad insertion operation. Furthermore, the second data is scrambled to obtain third data, and the number of bits of the third data is d scr =q×r Frame +d CP scrambled bits, and d CP =d CRC +d PAD PCS and OFEC encoding, first interleaving, OFEC interleaving, and 16QAM symbol mapping and polarization distribution are performed on the scrambled bit data to obtain 172032 dual-polarized symbols, resulting in overhead.

number

[0385] The baud rate for data processing is

number

number

[0386] When k=3360, d scr =336×k=1128960.

number

number

[0387] When k=3368, d scr =336×k=1131648.

number

number

[0388] When k=3376, d scr =336×k=1134336.

number

number

[0389] Thus, typical values ​​of the integer k may be 3368 or 3376. Corresponding typical parameter combinations are shown in Table 7.

[0390] Parameter combination of serial number 1 in Table 7 {r Frame =110, d CP = 848, and k = 3368} is used, the number of bits n output using the lookup table in the PCS process is LUT The minimum value of is 256, and the overhead of CRC and PAD is OH CP Note that the parameter combination {r Frame =110, d CP =3536, and k=3376} is used, the number of bits n output using the lookup table in the PCS process LUT The minimum value of is 128, and the overhead of CRC and PAD is OH CP Note that for the two parameter combinations, the specific implementation complexity of the PCS lookup table corresponding to serial number 1 is high, but the overhead of CRC and PAD, OH CP is small, and the specific implementation complexity of the PCS lookup table corresponding to serial number 2 is low, but the overhead of CRC and PAD, OH CP The combination of parameters in Serial No. 1 or Serial No. 2 may be selected based on the specific application scenario of the implementation.

[0391] [Table 7]

[0392] Parameter combination of serial number 1 in Table 7 {r Frame =110, d CP Note that the parameter p=22 is selected for {r = 848, and k = 3368}. For a specific implementation, please refer to embodiment 1. The parameter combination {r Frame =110, d CP =3536, and k=3376}, parameter p=22 is selected. Correspondingly, in the first data processing, r Frame = 110 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 1130800 bits. CRC-32 check is performed first.

number

number

[0393] Embodiment 10 Based on embodiment 9, a FlexO-8e data frame is considered, and the bit rate of a FlexO-8 data frame is about W bit ≒804.9795Gbit / s, and the baud rate W baud is approximately 131 GBaud.

number

[0394] When k=3184, d scr =336×k=1069824.

number

number

[0395] When k=3192, d scr =336×k=1072512.

number

number

[0396] When k=3200, d scr =336×k=1075200.

number

[0397] When k=3208, d scr =336×k=1077888.

number

[0398] When k=3216, d scr =336×k=1080576.

number

number

[0399] Thus, typical values ​​of the integer k may be 3184, 3192, or 3216. Corresponding typical parameter combinations are shown in Table 8.

[0400] [Table 8]

[0401] Parameter combination of serial number 1 in Table 8 {r Frame =104, d CP= 704, and k = 3184} is used, the number of bits n output using the lookup table in the PCS process is LUT The minimum value of is 128, and the overhead of CRC and PAD is OH CP Note that r = 0.066%. The parameter p = 13 may be selected. Correspondingly, in the first data processing, r Frame = 104 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 1069120 bits. CRC-32 check is performed first.

number

number

[0402] Parameter combination of serial number 2 in Table 8 {r Frame =104, d CP =3392, and k =3192} is used, the number of bits n output using a lookup table in the PCS process LUT The minimum value of is 256. The complexity of a particular implementation of the PCS lookup table is high, as is the overhead of CRC and PAD. CP is large. Therefore, the parameter combination with serial number 1 is preferentially selected at a baud rate of 131.842 GBaud.

[0403] Parameter combination of serial number 3 in Table 8 {r Frame=105, d CP = 1176, and k = 3216} is used, the number of bits n output using the lookup table in the PCS process is LUT The minimum value of is 128, and the overhead of CRC and PAD is OH CP =0.109%. The corresponding specific implementation of the PCS lookup table has low complexity. Furthermore, the parameter p=21 is selected. Correspondingly, in the first data processing, r Frame = 105 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 1079400 bits. CRC-32 check is performed first.

number

number

[0404] Embodiment 11 Considering the data frame rate of 800G, one data frame contains 512 rows, and each row contains 10280 bits. Frame =110, d CP =848, and k=3368} are considered. In the first data processing, r Frame = 110 rows of data are retrieved from the data frame, totaling d in =10280×r Frame = 1130800 bits. p = 22 is considered.

[0405] 17(a) is a diagram of an implementation of performing a CRC on a data frame according to an embodiment of the present application. As shown in FIG. 17(a), the CRC-32 check is first performed by:

number

number

number

[0406] As shown in Figure 4, in the second data processing, a plurality of bits obtained from the bit data stream output by the first data processing are sent to L=4 PCSs and OFEC encoders in a round-robin manner for PCS processing and OFEC encoding. As shown in Figure 5, k bits among k=3368 input bits are sent to L=4 PCSs and OFEC encoders in a round-robin manner. PCS =k-1504=1864 bits are sent to PCS processing to get 2048 bits. k=3368 bits are 1504 bits that do not undergo PCS processing and k PCS =k-1504=1864 bits.

[0407] In PCS processing, a LUT lookup table is used, and the LUT mapping is LUT = k to output 256 bits LUT= 233 input bits each time, and after LUT mapping is performed 8 times in succession, i.e., after LUT mapping is performed for a total of k - 1504 = 1864 bits, the corresponding 2048 bits are output.

[0408] The 2048 bits output by the PCS processing and the 1504 bits on which the PCS processing is not performed, totaling 2048 + 1504 = 3552 bits, are sent to pre-coding interleaving to obtain a sixth bit set, which includes 3552 bits. The sixth bit set is represented by using the set of blocks shown in Figure 23(b), where square block I 0,0 , I 0,1 , I 0,2 , I 0,3 , I 1,0 , I 1,1 , I 1,2 , and I 1,3 For each row i1 and column

number

number

[0409] The first interleaving process is the square block T 0,4 , T 0,5 , T 0,6 , T 0,7 , T 1,4 , T 1,5 , T 1,6 , and T 1,7 Set the fourth bit to get the square block B 0,4 , B 0,5 , B 0,6 , B 0,7 , B 1,4 , B 1,5 , B 1,6 , and B 1,7 is performed on the square block B 0,0 , B 0,1 , B 0,2 , B 0,3 , B 1,0 , B 1,...

Claims

1. 1. A data processing method comprising: performing a stochastic constellation shaping PCS process on a first set of k bits to obtain a second set of bits, where k is an integer greater than 1; performing forward error correction FEC encoding on the second set of bits and a third set of bits among the k bits excluding the first set of bits to obtain a fourth set of bits, wherein the fourth set of bits is m 0 first bit subsets, each of the first bit subsets being F 0 Contains m bits, 0 is an integer greater than 1, and F 0 is an even number greater than 1, and performing a first interleaving operation on the fourth set of bits to obtain a fifth set of bits, the fifth set of bits being m 0 second bit subsets, each of the second bit subsets being F 0 F in each of said second subsets of bits 0 / 2 bits are from the second bit set, and the other F in each of the second bit subsets 0 2 bits are from the third bit set and / or parity bits of the FEC coding; A method comprising:

2. The fifth set of bits is m 0 ×F 0 bits, each of the second subsets of bits comprising F 0 The method of claim 1 , wherein the first bit comprises consecutive bits.

3. The method of claim 1 , wherein each of the second subsets of bits is presented as a square block.

4. F in each of the second bit subsets 0 Bit is F 1 Row and F 1 F in each row of each of the second bit subsets 1 F out of bits 1 / 2 bits are from the second set of bits, and the second set of bits is 0 ×F 0 / 2 bits, and the F in each row of each of the second bit subsets 1 Other F bits 1 4. The method of claim 1, wherein the / 2 bits are from the third bit set and / or the parity bits of the FEC encoding.

5. F 0 = 256, and F 1 5. The method of claim 4, wherein: =16.

6. F 0 = 256, and F 1 =16, and each row i of the second bit subset 2 AND column [Equation 1] are from the second bit set, and 0≦i 2 < 16 and 0 ≤ j 2 <8 or Each row i of the second bit subset 2 and column (j 2 ×2-i 2 %2+1) are from the second bit set, and 0≦i 2 < 16 and 0 ≤ j 2 <8, [Equation 2] 6. The method of claim 4, wherein a represents performing a floor operation on a, and b%c represents b modulo c.

7. F 0 = 256, and F 1 =16, and the bits in each of the second bit subsets are: the bits in row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; the bits in row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; the bits in row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; the bits in row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set; the bits in row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; the bits in row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; the bits in row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; the bits in row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set; the bits in row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; the bits in row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; the bits in row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; the bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set; the bits in row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of each of the second bit subsets are from the second bit set; the bits in row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of each of the second bit subsets are from the second bit set; the bits in row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of each of the second bit subsets are from the second bit set; and 6. The method of claim 4, wherein the bits in row 15 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of each of the second bit subsets are from the second bit set.

8. F 0 = 256, and m in the fourth bit set 1 The sum of m in the first bit subsets 1 × 256 bits are from the second bit set, and m 0 =m 1 8. The method of claim 1, wherein the number of times is 2.

9. F 0 = 256, and m in the fourth bit set 0 ×256 bits, 32 rows and m 0 ×8 columns, and m 0 ×256 bits, 32 rows and m 0 ×8 columns, and row r in the fifth bit set 1 m in 0 ×8 bits are assigned to row r in the fourth bit set. 0 m in 0 × 8 bits, and 0 ≤ r 0 < 32 and 0 ≤ r 1 9. The method of any one of claims 1 to 8, wherein the β-amino acid residue is <32.

10. performing FEC encoding on the second set of bits and a third set of bits among the k bits excluding the first set of bits to obtain a fourth set of bits; performing a pre-encoding interleaving process on the second bit set and the third bit set to obtain a sixth bit set, wherein a quantity of bits in the sixth bit set is equal to a sum of a quantity of bits in the second bit set and a quantity of bits in the third bit set, and the sixth bit set is m 3 m third bit subsets, 3 The third bit subsets have two rows and m 4 distributed across columns, m 3 =2×m 4 and m 3 is greater than 1 and m 0 are integers smaller than F, and some third bit subsets are 0 Each of the other third subsets of bits contains F 2 Contains the F bit 2 is greater than 1 and F 0 a step that is a smaller even number; performing FEC encoding on the sixth set of bits to obtain the fourth set of bits; 10. The method of any one of claims 1 to 9, comprising:

11. m 3 = 14, and m 4 = 7, and F 0 = 256, and F 2 =240, each third bit subset in columns 0 to 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, and F 0 / 2 bits are from the second bit set, and the other F in each third bit subset in columns 0 to 4 0 1 / 2 bits are from the third bit set, 9 bits in each row of each third bit subset in column 5 are from the second bit set, the other 7 bits in each row of each third bit subset in column 5 are from the third bit set, and F in each third bit subset in column 6 2 The method of claim 10, wherein the bits are from the second set of bits.

12. r 0 =r 1 12. The method according to any one of claims 9 to 11, wherein

13. m 0 13. The method of any one of claims 1 to 12, wherein = 12 or 16.

14. After the step of performing an interleaving process on the fourth set of bits to obtain a fifth set of bits, the method further comprises: performing a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, where each first bit stream includes a plurality of fifth bit sets, and L is an even number greater than 0; performing symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, wherein the symbol mapping and polarization distribution map t bits to one dual-polarized symbol, where t is an integer greater than 0; performing digital signal processing (DSP) framing on the dual polarization symbol stream; 14. The method of any one of claims 1 to 13, further comprising:

15. 15. The method of claim 14, wherein amplitude bits in the dual polarization symbols are from the second bit set.

16. 16. The method of claim 15, wherein t=8 and the dual-polarized symbols are dual-polarized DP-16QAM symbols.

17. performing DSP framing on the dual polarization symbol stream; 17. The method of claim 16, comprising: performing framing processing every 172032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, wherein the superframe includes 175104 dual-polarized symbols.

18. 18. The method of claim 1, wherein the quantity of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

19. 1. A data processing method comprising: obtaining first data from a data frame, the first data comprising bits in r rows and q columns, where r is an integer greater than 0 and q is an integer greater than 0; performing a cyclic redundancy check (CRC) and / or pad bit insertion on the first data to obtain second data, wherein the second data is obtained by inserting d CRC parity bits and / or d PAD pad bits, d CRC is an integer greater than or equal to 0, and d PAD is an integer greater than or equal to 0; scrambling the second data to obtain third data, wherein the number of bits of the third data is d scr =r×q+d CP and d CP =d CRC +d PAD Steps obtaining k bits of the third data, where k is an integer greater than 1, and d scr is an integer multiple of k, and performing a stochastic constellation shaping PCS process on a first set of the k bits to obtain a second set of bits; performing forward error correction (FEC) encoding on the second set of bits and a third set of bits among the k bits excluding the first set of bits to obtain a fourth set of bits; A method comprising:

20. The fourth bit set is m 0 number of first bit subsets, each of which is F 0 Contains m bits, 0 is an integer greater than 1, and F 0 is an even number greater than 1, and the step of performing FEC encoding on the second set of bits and a third set of bits among the k bits excluding the first set of bits to obtain a fourth set of bits comprises: performing a pre-encoding interleaving process on the second bit set and the third bit set to obtain a sixth bit set, wherein a quantity of bits in the sixth bit set is equal to a sum of a quantity of bits in the second bit set and a quantity of bits in the third bit set, and the sixth bit set is m 3 m third bit subsets, 3 The third bit subsets have two rows and m 4 distributed across columns, m 3 =2×m 4 and m 3 is greater than 1 and m 0 are integers smaller than F, and some third bit subsets are 0 Each of the other third subsets of bits contains F 2 Contains the F bit 2 is greater than 1 and F 0 a step that is a smaller even number; performing FEC encoding on the sixth set of bits to obtain the fourth set of bits; 20. The method of claim 19, comprising:

21. 21. The method of claim 19 or 20, wherein the quantity of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set includes 2048 bits, the third bit set includes 1504 bits, and the fourth bit set includes 4096 bits.

22. d scr 22. The method of claim 19, wherein k is an integer multiple of 4×k and q=10280.

23. r=79, d CP = 328, and k = 3224, r=83, d CP = 32, and k = 3386, r=83, d CP = 536, and k = 3388, r=87, d CP = 72, and k = 2662, r=87, d CP =744, and k=2664, r=87, d CP =3432, and k=2672, r=104, d CP = 704, and k = 3184, r=104, d CP = 3392, and k = 3192, r=105, d CP = 504, and k = 3214, r=105, d CP = 1176, and k = 3216, r=109, d CP = 40, and k = 2668, r=109, d CP = 880, and k = 2670, r=110, d CP = 176, and k = 3366, r=110, d CP =848, and k=3368, r=110, d CP = 3536, and k = 3376, r=111, d CP = 648, and k = 3398, r=131, d CP = 8, and k = 2672, r=131, d CP = 1016, and k = 2674, r=131, d CP = 680, and k = 3208, r=132, d CP = 480, and k = 3232, r=132, d CP = 1320, and k = 3234, r=137, d CP = 320, and k = 3354, r=137, d CP = 1160, and k = 3356, r=138, d CP = 120, and k = 3378, r=138, d CP = 960, and k = 3380, r=152, d CP = 344, and k = 2658, r=152, d CP = 1520, and k = 2660, r=153, d CP = 648, and k = 2676, r=157, d CP = 856, and k = 3204, r=158, d CP = 656, and k = 3224, r=165, d CP = 264, and k = 3366, r=165, d CP = 1272, and k = 3368, r=166, d CP = 64, and k = 3386, r=166, d CP = 1072, and k = 3388, r=174, d CP = 144, and k = 2662, r=174, d CP = 1488, and k = 2664, r=175, d CP = 616, and k = 2678, r=183, d CP = 360, and k = 3200, r=183, d CP = 1536, and k = 3202, r=184, d CP = 664, and k = 3218, r=184, d CP = 1840, and k = 3220, r=185, d CP =968, and k=3236, r=192, d CP =744, and k=3358, r=192, d CP = 1920, and k = 3360, r=193, d CP = 1048, and k = 3376, r=194, d CP = 176, and k = 3392, r=194, d CP = 1352, and k = 3394, r=196, d CP = 616, and k = 2666, r=209, d CP = 536, and k = 3198, r=209, d CP = 1880, and k = 3200, r=210, d CP = 1008, and k = 3214, r=211, d CP = 136, and k = 3228, r=211, d CP = 1480, and k = 3230, r=217, d CP = 280, and k = 2656, r=217, d CP = 1960, and k = 2658, r=218, d CP =80, and k=2668, r=218, d CP = 1760, and k = 2670, r=219, d CP = 1224, and k = 3352, r=220, d CP = 352, and k = 3366, r=220, d CP =1696, and k=3368, r=221, d CP =824, and k=3382, r=221, d CP = 2168, and k = 3384, r=222, d CP = 1296, and k = 3398, r=235, d CP = 376, and k = 3196, r=235, d CP =1888, and k=3198, r=236, d CP = 680, and k = 3210, r=236, d CP = 2192, and k = 3212, r=237, d CP = 984, and k = 3224, r=238, d CP =1288, and k=3238, r=239, d CP = 920, and k = 2660, r=240, d CP =1728, and k=2672, r=247, d CP = 1000, and k = 3360, r=247, d CP = 2512, and k = 3362, r=248, d CP = 1304, and k = 3374, r=249, d CP = 96, and k = 3386, r=249, d CP =1608, and k=3388, r=250, d CP = 400, and k = 3400, r=250, d CP = 1912, and k = 3402, r=261, d CP = 216, and k = 2662, r=261, d CP = 2232, and k = 2664, r=261, d CP = 1560, and k = 3196, r=262, d CP = 16, and k = 2672, r=262, d CP = 2032, and k = 2674, r=262, d CP = 1360, and k = 3208, r=263, d CP = 1160, and k = 3220, r=264, d CP = 960, and k = 3232, r=264, d CP = 2640, and k = 3234, r=274, d CP = 640, and k = 3354, r=274, d CP = 2320, and k = 3356, r=275, d CP = 440, and k = 3366, r=275, d CP = 2120, and k = 3368, r=276, d CP = 240, and k = 3378, r=276, d CP = 1920, and k = 3380, r=277, d CP = 40, and k = 3390, r=277, d CP = 1720, and k = 3392, r=283, d CP = 2032, and k = 2666, r=284, d CP = 488, and k = 2674, r=284, d CP = 2672, and k = 2676, r=287, d CP =896, and k=3194, r=287, d CP = 2744, and k = 3196, r=288, d CP = 1704, and k = 3206, r=289, d CP = 664, and k = 3216, r=289, d CP = 2512, and k = 3218, r=290, d CP = 1472, and k = 3228, r=291, d CP =432, and k=3238, r=291, d CP = 2280, and k = 3240, r=302, d CP = 80, and k = 3360, r=302, d CP =1928, and k=3362, r=303, d CP =888, and k=3372, r=303, d CP = 2736, and k = 3374, r=304, d CP = 688, and k = 2658, r=304, d CP = 3040, and k = 2660, r=304, d CP =1696, and k=3384, r=305, d CP = 2168, and k = 2668, r=305, d CP = 656, and k = 3394, r=305, d CP = 2504, and k = 3396, r=306, d CP = 1296, and k = 2676, r=313, d CP = 1912, and k = 3194, r=314, d CP = 1712, and k = 3204, r=315, d CP = 1512, and k = 3214, r=316, d CP = 1312, and k = 3224, r=317, d CP =1112, and k=3234, r=317, d CP = 3128, and k = 3236, r=326, d CP = 320, and k = 2660, r=326, d CP = 2840, and k = 2662, r=327, d CP = 120, and k = 2668, r=327, d CP = 2640, and k = 2670, r=328, d CP = 2440, and k = 2678, r=329, d CP =728, and k=3356, r=329, d CP = 2744, and k = 3358, r=330, d CP = 528, and k = 3366, r=330, d CP = 2544, and k = 3368, r=331, d CP = 328, and k = 3376, r=331, d CP = 2344, and k = 3378, r=332, d CP = 128, and k = 3386, r=332, d CP = 2144, and k = 3388, r=333, d CP =1944, and k=3398, r=339, d CP =744, and k=3192, r=339, d CP = 2928, and k = 3194, r=340, d CP = 1384, and k = 3202, r=341, d CP = 2024, and k = 3212, r=342, d CP = 480, and k = 3220, r=342, d CP = 2664, and k = 3222, r=343, d CP = 1120, and k = 3230, r=343, d CP = 3304, and k = 3232, r=344, d CP = 1760, and k = 3240, r=348, d CP = 288, and k = 2662, r=348, d CP = 2976, and k = 2664, r=349, d CP = 760, and k = 2670, r=349, d CP =3448, and k=2672, r=350, d CP = 1232, and k = 2678, r=356, d CP = 704, and k = 3352, r=356, d CP = 2888, and k = 3354, r=357, d CP = 1344, and k = 3362, r=357, d CP = 3528, and k = 3364, r=358, d CP = 1984, and k = 3372, r=359, d CP = 440, and k = 3380, r=359, d CP = 2624, and k = 3382, r=360, d CP =1080, and k=3390, r=360, d CP = 3264, and k = 3392, r=361, d CP = 1720, and k = 3400, r=365, d CP = 1592, and k = 3192, r=366, d CP = 720, and k = 3200, r=366, d CP = 3072, and k = 3202, r=367, d CP = 2200, and k = 3210, r=368, d CP =1328, and k=3218, r=368, d CP = 3680, and k = 3220, r=369, d CP = 2304, and k = 2658, r=369, d CP = 456, and k = 3226, r=369, d CP = 2808, and k = 3228, r=370, d CP =592, and k=2664, r=370, d CP =3448, and k=2666, r=370, d CP = 1936, and k = 3236, r=371, d CP = 1736, and k = 2672, r=384, d CP =1488, and k=3358, r=384, d CP = 3840, and k = 3360, r=385, d CP = 616, and k = 3366, r=385, d CP = 2968, and k = 3368, r=386, d CP = 2096, and k = 3376, r=387, d CP = 1224, and k = 3384, r=387, d CP = 3576, and k = 3386, r=388, d CP = 352, and k = 3392, r=388, d CP = 2704, and k = 3394, r=389, d CP = 1832, and k = 3402, r=391, d CP = 2440, and k = 2660, r=392, d CP = 1232, and k = 2666, r=392, d CP = 2240, and k = 3200, r=393, d CP = 24, and k = 2672, r=393, d CP = 3048, and k = 2674, r=393, d CP = 2040, and k = 3208, r=394, d CP = 1840, and k = 3216, r=395, d CP = 1640, and k = 3224, r=396, d CP = 1440, and k = 3232, r=396, d CP = 3960, and k = 3234, r=397, d CP = 1240, and k = 3240, r=397, d CP = 3760, and k = 3242, r=411, d CP = 960, and k = 3354, r=411, d CP = 3480, and k = 3356, r=412, d CP = 760, and k = 3362, r=412, d CP = 3280, and k = 3364, r=413, d CP = 2912, and k = 2662, r=413, d CP = 560, and k = 3370, r=413, d CP = 3080, and k = 3372, r=414, d CP = 2208, and k = 2668, r=414, d CP = 360, and k = 3378, r=414, d CP = 2880, and k = 3380, r=415, d CP = 1504, and k = 2674, r=415, d CP = 160, and k = 3386, r=415, d CP = 2680, and k = 3388, r=416, d CP = 2480, and k = 3396, r=418, d CP = 1072, and k = 3198, r=418, d CP = 3760, and k = 3200, r=419, d CP = 1544, and k = 3206, r=419, d CP = 4232, and k = 3208, r=420, d CP =2016, and k=3214, r=421, d CP = 2488, and k = 3222, r=422, d CP = 272, and k = 3228, r=422, d CP = 2960, and k = 3230, r=423, d CP =744, and k=3236, r=423, d CP = 3432, and k = 3238, r=434, d CP = 560, and k = 2656, r=434, d CP = 3920, and k = 2658, r=435, d CP = 360, and k = 2662, r=435, d CP = 3720, and k = 2664, r=436, d CP = 160, and k = 2668, r=436, d CP = 3520, and k = 2670, r=437, d CP = 3320, and k = 2676, r=438, d CP = 2448, and k = 3352, r=439, d CP = 232, and k = 3358, r=439, d CP = 2920, and k = 3360, r=440, d CP = 704, and k = 3366, r=440, d CP = 3392, and k = 3368, r=441, d CP = 1176, and k = 3374, r=441, d CP = 3864, and k = 3376, r=442, d CP =1648, and k=3382, r=442, d CP = 4336, and k = 3384, r=443, d CP = 2120, and k = 3390, r=444, d CP = 2424, and k = 3198, r=444, d CP = 2592, and k = 3398, r=445, d CP = 712, and k = 3204, r=445, d CP = 3568, and k = 3206, r=446, d CP = 1856, and k = 3212, r=447, d CP = 144, and k = 3218, r=447, d CP = 3000, and k = 3220, r=448, d CP =1288, and k=3226, r=448, d CP = 4144, and k = 3228, r=449, d CP = 2432, and k = 3234, r=456, d CP = 1032, and k = 2658, r=456, d CP = 4560, and k = 2660, r=457, d CP = 1336, and k = 2664, r=458, d CP = 1640, and k = 2670, r=459, d CP = 1944, and k = 2676, r=466, d CP =1888, and k=3356, r=466, d CP = 4744, and k = 3358, r=467, d CP = 176, and k = 3362, r=467, d CP = 3032, and k = 3364, r=468, d CP = 1320, and k = 3370, r=468, d CP = 4176, and k = 3372, r=469, d CP = 2464, and k = 3378, r=470, d CP = 752, and k = 3196, r=470, d CP = 3776, and k = 3198, r=470, d CP =752, and k=3384, r=470, d CP = 3608, and k = 3386, r=471, d CP = 2568, and k = 3204, r=471, d CP =1896, and k=3392, r=471, d CP = 4752, and k = 3394, r=472, d CP = 1360, and k = 3210, r=472, d CP = 4384, and k = 3212, r=472, d CP = 184, and k = 3398, r=472, d CP = 3040, and k = 3400, r=473, d CP = 152, and k = 3216, r=473, d CP = 3176, and k = 3218, r=474, d CP = 1968, and k = 3224, r=475, d CP = 760, and k = 3230, r=475, d CP = 3784, and k = 3232, r=476, d CP = 2576, and k = 3238, r=478, d CP = 1840, and k = 2660, r=479, d CP = 2648, and k = 2666, r=480, d CP = 3456, and k = 2672, r=481, d CP =568, and k=2676, r=481, d CP = 4264, and k = 2678, r=493, d CP = 184, and k = 3352, r=493, d CP = 3208, and k = 3354, r=494, d CP = 2000, and k = 3360, r=494, d CP = 5024, and k = 3362, r=495, d CP =792, and k=3366, r=495, d CP = 3816, and k = 3368, r=496, d CP = 1936, and k = 3196, r=496, d CP = 2608, and k = 3374, r=497, d CP = 1232, and k = 3202, r=497, d CP = 4424, and k = 3204, r=497, d CP = 1400, and k = 3380, r=497, d CP = 4424, and k = 3382, r=498, d CP = 528, and k = 3208, r=498, d CP = 3720, and k = 3210, r=498, d CP = 192, and k = 3386, r=498, d CP = 3216, and k = 3388, r=499, d CP = 1672, and k = 2656, r=499, d CP = 3016, and k = 3216, r=499, d CP = 2008, and k = 3394, r=499, d CP = 5032, and k = 3396, r=500, d CP = 2984, and k = 2662, r=500, d CP = 2312, and k = 3222, r=500, d CP = 800, and k = 3400, r=500, d CP = 3824, and k = 3402, r=501, d CP = 432, and k = 2666, r=501, d CP = 4296, and k = 2668, r=501, d CP =1608, and k=3228, r=501, d CP = 4800, and k = 3230, r=502, d CP = 1744, and k = 2672, r=502, d CP = 904, and k = 3234, r=502, d CP = 4096, and k = 3236, or r=503, d CP 23. The method of any one of claims 19 to 22, wherein k = 3056, and k = 2678.

24. d scr 24. The method of any one of claims 19 to 23, wherein k = 336 × k.

25. performing a CRC on the first data; performing a CRC-32 check on a total of r×q / p bits in each r / p rows of the first data and adding 32 parity bits; CRC = 32 × p, where r is divisible by p and p is an integer greater than 1, or The first r of the first data F0 ×r in (p-1) rows F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and add the last r of the first data. F1 Total in rows q×r F1 performing a CRC-32 check on the bits and adding 32 parity bits; CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and integer r F0 is an integer r F1 Bigger, Step 25. The method of any one of claims 19 to 24, comprising:

26. 26. The method of any one of claims 19 to 25, wherein q=2056.

27. performing a CRC on the first data; The first r of the first data F0 ×r in (p-1) rows F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and add the last r of the first data. F1 Total in rows q×r F1 performing a CRC-32 check on the bits and adding 32 parity bits; CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and integer r F0 is an integer r F1 Bigger, Step 27. The method of claim 26, comprising:

28. 28. The method of claim 26 or 27, wherein r=435.

29. p=22 and r F0 = 20, and r F1 =15, and performing a CRC on the first data, 29. The method of claim 28, comprising performing a CRC-32 check on a total of 41,120 bits in every 20 rows of the first 420 rows of the first data to add 32 parity bits, and performing a CRC-32 check on a total of 30,840 bits in the last 15 rows of the first data to add 32 parity bits.

30. d CP = 3432 and k = 2672, or d CP 30. The method of claim 28 or 29, wherein k=744 and k=2664.

31. r=546, d CP = 1008, and k = 3344, r=546, d CP = 3696, and k = 3352, r=547, d CP = 1640, and k = 3352, r=547, d CP = 4328, and k = 3360, r=548, d CP = 2272, and k = 3360, r=548, d CP = 4960, and k = 3368, r=549, d CP = 216, and k = 3360, r=549, d CP = 2904, and k = 3368, r=549, d CP = 5592, and k = 3376, r=550, d CP =848, and k=3368, r=550, d CP = 3536, and k = 3376, r=551, d CP = 1480, and k = 3376, r=551, d CP =4168, and k=3384, r=552, d CP = 2112, and k = 3384, r=552, d CP = 4800, and k = 3392, r=553, d CP = 56, and k = 3384, r=553, d CP = 2744, and k = 3392, r=553, d CP = 5432, and k = 3400, r=554, d CP = 688, and k = 3392, r=554, d CP = 3376, and k = 3400, r=555, d CP = 1320, and k = 3400, r=555, d CP = 4008, and k = 3408, r=556, d CP = 1952, and k = 3408, r=556, d CP = 4640, and k = 3416, r=557, d CP = 2584, and k = 3416, r=557, d CP =5272, and k=3424, r=558, d CP = 528, and k = 3416, r=558, d CP = 3216, and k = 3424, r=559, d CP = 1160, and k = 3424, r=559, d CP =3848, and k=3432, r=560, d CP =1792, and k=3432, r=560, d CP = 4480, and k = 3440, r=561, d CP = 2424, and k = 3440, r=561, d CP =5112, and k=3448, r=562, d CP = 368, and k = 3440, r=562, d CP = 3056, and k = 3448, or r=562, d CP 28. The method of claim 26 or 27, wherein k=5744, and k=3456.

32. r=520, d CP = 704, and k = 3184, r=520, d CP = 3392, and k = 3192, r=520, d CP = 6080, and k = 3200, r=521, d CP = 1336, and k = 3192, r=521, d CP = 4024, and k = 3200, r=522, d CP = 1968, and k = 3200, r=522, d CP = 4656, and k = 3208, r=523, d CP = 2600, and k = 3208, r=523, d CP =5288, and k=3216, r=524, d CP = 544, and k = 3208, r=524, d CP = 3232, and k = 3216, r=525, d CP = 1176, and k = 3216, r=525, d CP = 3864, and k = 3224, r=526, d CP =1808, and k=3224, r=526, d CP = 4496, and k = 3232, r=527, d CP = 2440, and k = 3232, r=527, d CP =5128, and k=3240, r=528, d CP = 384, and k = 3232, r=528, d CP = 3072, and k = 3240, r=528, d CP =5760, and k=3248, r=529, d CP = 1016, and k = 3240, r=529, d CP = 3704, and k = 3248, r=530, d CP =1648, and k=3248, r=530, d CP = 4336, and k = 3256, r=531, d CP = 2280, and k = 3256, r=531, d CP =4968, and k=3264, r=532, d CP = 2912, and k = 3264, r=532, d CP = 224, and k = 3256, r=533, d CP =856, and k=3264, r=533, d CP = 3544, and k = 3272, r=534, d CP =1488, and k=3272, r=534, d CP = 4176, and k = 3280, r=535, d CP = 2120, and k = 3280, or r=535, d CP 28. The method of claim 26 or 27, wherein k=4808, and k=3288.

33. The fourth bit set is m 0 m first bit subsets, 0 is an integer greater than 1, and after the step of performing FEC encoding on the second set of bits and the third set of bits to obtain a fourth set of bits, the method further comprises: performing a first interleaving operation on the fourth set of bits to obtain a fifth set of bits, the fifth set of bits being m 0 33. The method of claim 19, further comprising: comprising second bit subsets, each of the second bit subsets comprising 256 bits, 128 bits in each of the second bit subsets being from the second bit set, and the other 128 bits in each of the second bit subsets being from the third bit set and / or parity bits of the FEC coding.

34. 34. The method of claim 33, wherein each of the second bit subsets comprises 256 consecutive bits.

35. 34. The method of claim 33, wherein each of the second subsets of bits is presented as a block.

36. The 256 bits in the second bit subset are distributed into 16 rows and 16 columns, and the bits in the second bit subset are arranged as follows: the bits at row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits at row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits at row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; and 36. The method of claim 33, wherein one or more of the following conditions are satisfied: the bits at row 15 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set.

37. m in the fourth bit set 0 ×256 bits, 32 rows and m 0 ×8 columns, and m 0 ×256 bits, 32 rows and m 0 ×8 columns, and row r in the fifth bit set 1 m in 0 ×8 bits are assigned to row r in the fourth bit set. 0 m in 0 × 8 bits, and 0 ≤ r 0 < 32 and 0 ≤ r 1 37. The method of any one of claims 33 to 36, wherein <32.

38. r 0 =r 1 38. The method of claim 37, wherein:

39. The fourth bit set is m 0 m first bit subsets, 0 39. The method of any one of claims 19 to 38, wherein = 12 or 16.

40. After the step of performing a first interleaving operation on the fourth set of bits to obtain a fifth set of bits, the method further comprises: performing a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, where each first bit stream includes a plurality of fifth bit sets, and L is an even number greater than 0; performing symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, wherein the symbol mapping and polarization distribution map t bits to one dual-polarized symbol, where t is an integer greater than 0; performing digital signal processing (DSP) framing on the dual polarization symbol stream; 40. The method of any one of claims 33 to 39, further comprising:

41. 41. The method of claim 40, wherein amplitude bits in the dual polarization symbols are from the second bit set.

42. 42. The method of claim 41, wherein t=8 and the dual-polarized symbols are dual-polarized DP-16QAM symbols.

43. performing DSP framing on the dual polarization symbol stream, 43. The method of claim 42, comprising: performing framing processing every 172032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, wherein the superframe includes 175104 dual-polarized symbols.

44. said step of obtaining first data from a data frame comprises: F Frame to obtain F ×r ×q bits from the data frame. Frame A step of acquiring F first data Frame is an integer greater than 0, d scr ×F Frame =336×k×F DSP and F DSP represents the number of DSP superframes, and F DSP DSP superframes are Frame The first data is obtained by processing F DSP 44. The method of claim 43, comprising the step of:

45. F DSP >1, and F DSP A plurality of consecutive symbols in a first DSP superframe of the DSP superframes is a first marker, and the F DSP superframes excluding the first DSP superframe are DSP 45. The method of claim 44, wherein a plurality of consecutive symbols in each of the DSP superframes is a second marker.

46. 1. A data processing method comprising: performing a first stochastic constellation shaping PCS process on a first set of bits in a first group of k bits to obtain a second set of bits, the second set of bits being m 0 × 128 bits, k is an integer greater than 1, and m 0 is an integer greater than 1; performing a first forward error correction (FEC) encoding on the second set of bits and a third set of bits in the first group of k bits excluding the first set of bits to obtain a fourth set of bits, wherein the fourth set of bits is m 0 first square blocks, each of said first square blocks comprising a total of 256 bits distributed in 16 rows and 16 columns; performing a second PCS process on a fifth set of bits in the second group of k bits to obtain a sixth set of bits; performing a second FEC encoding on the sixth set of bits and a seventh set of bits in the second group of k bits excluding the fifth set of bits to obtain an eighth set of bits, wherein the eighth set of bits is m 0 second square blocks, each of said second square blocks comprising a total of 256 bits distributed in 16 rows and 16 columns; inputting the 21 fourth sets of bits and the 21 eighth sets of bits into an interleaver buffer, the interleaver buffer having 84 rows and m 1 Total of 84 × m distributed among columns 1 Contains m buffer units 0 =m 1 x2, each of the buffer units configured to buffer a total of 256 bits in 16 rows and 16 columns, and 42 x m 1 The first square blocks are input to the even rows of the interleaver buffer, and 42×m 1 number of second square blocks are input to odd rows of the interleaver buffer, the interleaver buffer including a first buffer subset and a second buffer subset, the first buffer subset being 42×m 1 buffer units, and the second buffer subset comprises 42×m 1 buffer units, wherein bits input to the first buffer subset are from the second bit set and the sixth bit set, and bits input to the second buffer subset are from the third bit set, the seventh bit set, parity bits of the first FEC encoding, and parity bits of the second FEC encoding; performing symbol mapping and polarization distribution for every 8 bits in the interleaver buffer to obtain one dual-polarized DP-16QAM symbol, wherein two amplitude bits among four bits corresponding to a 16QAM symbol of the DP-16QAM symbol in a target polarization direction are from one column in a first buffer unit of the first buffer subset, and two code bits among the four bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction are from one column in a second buffer unit of the second buffer subset; A method comprising:

47. 47. The method of claim 46, wherein four of the eight bits are from one column of the first buffer units of the first buffer subset and the other four of the eight bits are from one column of the second buffer units of the second buffer subset.

48. m 0 The first square blocks are arranged in two rows and m 1 distributed across columns, row 0 and column m 2 The first square block in row 1 and column m 2 the first square block in m is from the second bit set, 0 The second square blocks are arranged in two rows and m 1 distributed across columns, row 0 and column m 2 The second square block in and row 1 and column m 2 the second square block in is from the sixth bit set, and 0≦m 2 <m 1 48. The method of claim 46 or 47, wherein the β-amino acid is β-amino acid / 2.

49. m 0 =16, and the first buffer subset includes a total of 336 buffer units in columns 0, 1, 2, and 3 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 4, 5, 6, and 7 of the interleaver buffer; or m 0 49. The method of claim 48, wherein: =12, the first buffer subset includes a total of 252 buffer units in columns 0, 1, and 2 of the interleaver buffer, and the second buffer subset includes a total of 252 buffer units in columns 3, 4, and 5 of the interleaver buffer.

50. m 0 = 16, and m 1 = 8, m 0 The first square blocks are arranged in two rows and m 1 distributed into columns, wherein the first square block at row 0, column 0, the first square block at row 0, column 1, the first square block at row 0, column 4, the first square block at row 0, column 5, the first square block at row 1, column 0, the first square block at row 1, column 1, the first square block at row 1, column 4, and the first square block at row 1, column 5 are from the second bit set; m 0 The second square blocks are arranged in two rows and m 1 48. A method as claimed in claim 46 or 47, wherein the second square block at row 0 and column 0, the second square block at row 0 and column 1, the second square block at row 0 and column 4, the second square block at row 0 and column 5, the second square block at row 1 and column 0, the second square block at row 1 and column 1, the second square block at row 1 and column 4, and the second square block at row 1 and column 5 are from the sixth bit set.

51. 51. The method of claim 50, wherein the first buffer subset includes a total of 336 buffer units in columns 0, 1, 4, and 5 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 2, 3, 6, and 7 of the interleaver buffer.

52. 1. A data processing apparatus, comprising: a stochastic constellation shaping PCS unit; a forward error correction FEC encoding unit; and a first interleaving unit, the PCS unit is configured to perform a probabilistic PCS process on a first set of k bits to obtain a second set of bits, where k is an integer greater than 1; The FEC unit is configured to perform FEC encoding on the second bit set and a third bit set among the k bits excluding the first bit set to obtain a fourth bit set, and the fourth bit set is m 0 first bit subsets, each of the first bit subsets being F 0 Contains m bits, 0 is an integer greater than 1, and F 0 is an even number greater than 1, The first interleaving unit is configured to perform a first interleaving process on the fourth set of bits to obtain a fifth set of bits, and the fifth set of bits is m 0 second bit subsets, each of the second bit subsets being F 0 F in each of said second subsets of bits 0 / 2 bits are from the second bit set, and the other F in each of the second bit subsets 0 2 bits are from said third set of bits and / or parity bits of said FEC coding.

53. The fifth set of bits is m 0 ×F 0 bits, each of the second subsets of bits comprising F 0 53. A data processing apparatus as claimed in claim 52, comprising consecutive bits.

54. 53. A data processing apparatus as claimed in claim 52, wherein each of said second subsets of bits is presented as a block.

55. F in each of the second bit subsets 0 Bit is F 1 Row and F 1 F in each row of the second bit subset 1 F out of bits 1 / 2 bits are from the second set of bits, and the second set of bits is 0 ×F 0 / 2 bits, and the F 1 Other F bits 1 55. A data processing apparatus as claimed in any one of claims 52 to 54, wherein / 2 bits are from the third set of bits and / or the parity bits of the FEC encoding.

56. F 0 = 256, and F 1 56. The data processing device of claim 55, wherein: =16.

57. F 0 = 256, and F 1 =16, and row i of the second bit subset 2 AND column [Equation 3] are from the second bit set, and 0≦i 2 < 16 and 0 ≤ j 2 <8 or Row i of the second bit subset 2 and column (j 2 ×2-i 2 %2+1) are from the second bit set, and 0≦i 2 < 16 and 0 ≤ j 2 <8, [Equation 4] 57. A data processing apparatus according to claim 55 or 56, wherein: denotes performing a floor operation on a, and b%c denotes b modulo c.

58. F 0 = 256, and F 1 =16 and the bits in the second subset of bits are: the bits at row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits at row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits at row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; and 57. A data processing apparatus as claimed in claim 55 or 56, wherein one or more of the following are satisfied: the bits at row 15 and columns 1, 2, 5, 6, 9, 10, 13 and 14 of the second bit subset are from the second bit set.

59. F 0 = 256, and m in the fourth bit set 1 The sum of m in the first bit subsets 1 × 256 bits are from the second bit set, and m 0 =m 1 59. A data processing device according to any one of claims 52 to 58, wherein the number of inputs is 2.

60. F 0 = 256, and m in the fourth bit set 0 ×256 bits, 32 rows and m 0 ×8 columns, and m 0 ×256 bits, 32 rows and m 0 ×8 columns, and row r in the fifth bit set 1 m in 0 ×8 bits are assigned to row r in the fourth bit set. 0 m in 0 × 8 bits, and 0 ≤ r 0 < 32 and 0 ≤ r 1 60. A data processing device according to any one of claims 52 to 59, wherein <32

61. the data processing apparatus further comprises a pre-encoding interleaving unit; The pre-encoding interleaving unit is configured to perform a pre-encoding interleaving process on the second bit set and the third bit set to obtain a sixth bit set, wherein a quantity of bits in the sixth bit set is equal to a sum of a quantity of bits in the second bit set and a quantity of bits in the third bit set, and the sixth bit set is m 3 m third bit subsets, 3 The third bit subsets have two rows and m 4 distributed across columns, m 3 =2×m 4 and m 3 is greater than 1 and m 0 are integers smaller than F, and some third bit subsets are 0 Each of the other third subsets of bits contains F 2 Contains the F bit 2 is greater than 1 and F 0 is a smaller even number, 61. A data processing apparatus according to any one of claims 52 to 60, wherein the FEC unit is configured to perform FEC encoding on the sixth set of bits to obtain the fourth set of bits.

62. m 3 = 14, and m 4 = 7, and F 0 = 256, and F 2 =240, each third bit subset in columns 0 to 5 includes bits in 16 rows and 16 columns, each third bit subset in column 6 includes bits in 16 rows and 15 columns, and F 0 / 2 bits are from the second bit set, and the other F in each third bit subset in columns 0 to 4 0 1 / 2 bits are from the third bit set, 9 bits in each row of each third bit subset in column 5 are from the second bit set, the other 7 bits in each row of each third bit subset in column 5 are from the third bit set, and F in each third bit subset in column 6 2 62. A data processing apparatus as claimed in claim 61, wherein the bits are from said second set of bits.

63. r 0 =r 1 63. A data processing device according to any one of claims 60 to 62, wherein:

64. m 0 64. A data processing device according to any one of claims 52 to 63, wherein =12 or 16.

65. the data processing device further includes a second interleaving unit, a symbol mapping unit, a polarization distribution unit, and a digital signal processing DSP framing unit; the second interleaving unit is configured to perform second interleaving on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, each first bit stream including a plurality of fifth bit sets, where L is an even number greater than 0; the symbol mapping unit and the polarization distribution unit are configured to perform symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, wherein t bits are mapped to one dual-polarized symbol by the symbol mapping and the polarization distribution, where t is an integer greater than 0; 65. A data processing apparatus according to any one of claims 52 to 64, wherein said DSP framing unit is configured to perform DSP framing on said dual polarized symbol stream.

66. 66. A data processing apparatus as claimed in claim 65, wherein amplitude bits in said dual polarization symbols are from said second bit set.

67. 67. The data processing apparatus of claim 66, wherein t=8 and the dual-polarized symbols are dual-polarized DP-16QAM symbols.

68. 68. The data processing device of claim 67, wherein the DSP framing unit is specifically configured to perform framing processing every 172,032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, and the superframe includes 175,104 dual-polarized symbols.

69. 69. A data processing apparatus according to any one of claims 52 to 68, wherein the quantity of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set comprises 2048 bits, the third bit set comprises 1504 bits, and the fourth bit set comprises 4096 bits.

70. 1. A data processing apparatus, comprising: a first processing unit, a second processing unit, a scrambling unit, a third processing unit, a stochastic constellation shaping PCS unit, and a forward error correction FEC encoding unit, the first processing unit is configured to obtain first data from a data frame, the first data including bits in r rows and q columns, r being an integer greater than 0, and q being an integer greater than 0; The second processing unit is configured to perform a cyclic redundancy check (CRC) and / or pad bit insertion on the first data to obtain second data, and the second data is obtained by inserting a cyclic redundancy check (CRC) and / or pad bit insertion. CRC parity bits and / or d PAD pad bits, d CRC is an integer greater than or equal to 0, and d PAD is an integer greater than or equal to 0, The scrambling unit is configured to scramble the second data to obtain third data, and the number of bits of the third data is d scr =r×q+d CP and d CP =d CRC +d PAD and the third processing unit is configured to obtain k bits in the third data, where k is an integer greater than 1; and scr is an integer multiple of k, the PCS unit is configured to perform PCS processing on a first set of bits among the k bits to obtain a second set of bits; the FEC unit is configured to perform FEC encoding on the second set of bits and a third set of bits among the k bits excluding the first set of bits to obtain a fourth set of bits.

71. The fourth bit set is m 0 first bit subsets, each of the first bit subsets being F 0 Contains m bits, 0 is an integer greater than 1, and F 0 is an even number greater than 1, and the data processing apparatus further includes a pre-encoding interleaving unit, wherein the pre-encoding interleaving unit is configured to perform a pre-encoding interleaving process on the second bit set and the third bit set to obtain a sixth bit set, a quantity of bits in the sixth bit set equal to a sum of a quantity of bits in the second bit set and a quantity of bits in the third bit set, and the sixth bit set is m 3 m third bit subsets, 3 The third bit subsets have two rows and m 4 distributed across columns, m 3 =2×m 4 and m 3 is greater than 1 and m 0 are integers smaller than F, and some third bit subsets are 0 Each of the other third subsets of bits contains F 2 Contains the F bit 2 is greater than 1 and F 0 is a smaller even number, 71. The data processing apparatus of claim 70, wherein the FEC unit is configured to perform the FEC encoding on the sixth set of bits to obtain the fourth set of bits.

72. 72. A data processing apparatus as claimed in claim 70 or 71, wherein the quantity of bits in the first bit set is an integer multiple of 2, 4, 8, or 16, the second bit set comprises 2048 bits, the third bit set comprises 1504 bits, and the fourth bit set comprises 4096 bits.

73. d scr 73. A data processing apparatus according to any one of claims 70 to 72, wherein is an integer multiple of 4 × k and q = 10280.

74. r=79, d CP = 328, and k = 3224, r=83, d CP = 32, and k = 3386, r=83, d CP = 536, and k = 3388, r=87, d CP = 72, and k = 2662, r=87, d CP =744, and k=2664, r=87, d CP =3432, and k=2672, r=104, d CP = 704, and k = 3184, r=104, d CP = 3392, and k = 3192, r=105, d CP = 504, and k = 3214, r=105, d CP = 1176, and k = 3216, r=109, d CP = 40, and k = 2668, r=109, d CP = 880, and k = 2670, r=110, d CP = 176, and k = 3366, r=110, d CP =848, and k=3368, r=110, d CP = 3536, and k = 3376, r=111, d CP = 648, and k = 3398, r=131, d CP = 8, and k = 2672, r=131, d CP = 1016, and k = 2674, r=131, d CP = 680, and k = 3208, r=132, d CP = 480, and k = 3232, r=132, d CP = 1320, and k = 3234, r=137, d CP = 320, and k = 3354, r=137, d CP = 1160, and k = 3356, r=138, d CP = 120, and k = 3378, r=138, d CP = 960, and k = 3380, r=152, d CP = 344, and k = 2658, r=152, d CP = 1520, and k = 2660, r=153, d CP = 648, and k = 2676, r=157, d CP = 856, and k = 3204, r=158, d CP = 656, and k = 3224, r=165, d CP = 264, and k = 3366, r=165, d CP = 1272, and k = 3368, r=166, d CP = 64, and k = 3386, r=166, d CP = 1072, and k = 3388, r=174, d CP = 144, and k = 2662, r=174, d CP = 1488, and k = 2664, r=175, d CP = 616, and k = 2678, r=183, d CP = 360, and k = 3200, r=183, d CP = 1536, and k = 3202, r=184, d CP = 664, and k = 3218, r=184, d CP = 1840, and k = 3220, r=185, d CP =968, and k=3236, r=192, d CP =744, and k=3358, r=192, d CP = 1920, and k = 3360, r=193, d CP = 1048, and k = 3376, r=194, d CP = 176, and k = 3392, r=194, d CP = 1352, and k = 3394, r=196, d CP = 616, and k = 2666, r=209, d CP = 536, and k = 3198, r=209, d CP = 1880, and k = 3200, r=210, d CP = 1008, and k = 3214, r=211, d CP = 136, and k = 3228, r=211, d CP = 1480, and k = 3230, r=217, d CP = 280, and k = 2656, r=217, d CP = 1960, and k = 2658, r=218, d CP =80, and k=2668, r=218, d CP = 1760, and k = 2670, r=219, d CP = 1224, and k = 3352, r=220, d CP = 352, and k = 3366, r=220, d CP =1696, and k=3368, r=221, d CP =824, and k=3382, r=221, d CP = 2168, and k = 3384, r=222, d CP = 1296, and k = 3398, r=235, d CP = 376, and k = 3196, r=235, d CP =1888, and k=3198, r=236, d CP = 680, and k = 3210, r=236, d CP = 2192, and k = 3212, r=237, d CP = 984, and k = 3224, r=238, d CP =1288, and k=3238, r=239, d CP = 920, and k = 2660, r=240, d CP =1728, and k=2672, r=247, d CP = 1000, and k = 3360, r=247, d CP = 2512, and k = 3362, r=248, d CP = 1304, and k = 3374, r=249, d CP = 96, and k = 3386, r=249, d CP =1608, and k=3388, r=250, d CP = 400, and k = 3400, r=250, d CP = 1912, and k = 3402, r=261, d CP = 216, and k = 2662, r=261, d CP = 2232, and k = 2664, r=261, d CP = 1560, and k = 3196, r=262, d CP = 16, and k = 2672, r=262, d CP = 2032, and k = 2674, r=262, d CP = 1360, and k = 3208, r=263, d CP = 1160, and k = 3220, r=264, d CP = 960, and k = 3232, r=264, d CP = 2640, and k = 3234, r=274, d CP = 640, and k = 3354, r=274, d CP = 2320, and k = 3356, r=275, d CP = 440, and k = 3366, r=275, d CP = 2120, and k = 3368, r=276, d CP = 240, and k = 3378, r=276, d CP = 1920, and k = 3380, r=277, d CP = 40, and k = 3390, r=277, d CP = 1720, and k = 3392, r=283, d CP = 2032, and k = 2666, r=284, d CP = 488, and k = 2674, r=284, d CP = 2672, and k = 2676, r=287, d CP =896, and k=3194, r=287, d CP = 2744, and k = 3196, r=288, d CP = 1704, and k = 3206, r=289, d CP = 664, and k = 3216, r=289, d CP = 2512, and k = 3218, r=290, d CP = 1472, and k = 3228, r=291, d CP =432, and k=3238, r=291, d CP = 2280, and k = 3240, r=302, d CP = 80, and k = 3360, r=302, d CP =1928, and k=3362, r=303, d CP =888, and k=3372, r=303, d CP = 2736, and k = 3374, r=304, d CP = 688, and k = 2658, r=304, d CP = 3040, and k = 2660, r=304, d CP =1696, and k=3384, r=305, d CP = 2168, and k = 2668, r=305, d CP = 656, and k = 3394, r=305, d CP = 2504, and k = 3396, r=306, d CP = 1296, and k = 2676, r=313, d CP = 1912, and k = 3194, r=314, d CP = 1712, and k = 3204, r=315, d CP = 1512, and k = 3214, r=316, d CP = 1312, and k = 3224, r=317, d CP =1112, and k=3234, r=317, d CP = 3128, and k = 3236, r=326, d CP = 320, and k = 2660, r=326, d CP = 2840, and k = 2662, r=327, d CP = 120, and k = 2668, r=327, d CP = 2640, and k = 2670, r=328, d CP = 2440, and k = 2678, r=329, d CP =728, and k=3356, r=329, d CP = 2744, and k = 3358, r=330, d CP = 528, and k = 3366, r=330, d CP = 2544, and k = 3368, r=331, d CP = 328, and k = 3376, r=331, d CP = 2344, and k = 3378, r=332, d CP = 128, and k = 3386, r=332, d CP = 2144, and k = 3388, r=333, d CP =1944, and k=3398, r=339, d CP =744, and k=3192, r=339, d CP = 2928, and k = 3194, r=340, d CP = 1384, and k = 3202, r=341, d CP = 2024, and k = 3212, r=342, d CP = 480, and k = 3220, r=342, d CP = 2664, and k = 3222, r=343, d CP = 1120, and k = 3230, r=343, d CP = 3304, and k = 3232, r=344, d CP = 1760, and k = 3240, r=348, d CP = 288, and k = 2662, r=348, d CP = 2976, and k = 2664, r=349, d CP = 760, and k = 2670, r=349, d CP =3448, and k=2672, r=350, d CP = 1232, and k = 2678, r=356, d CP = 704, and k = 3352, r=356, d CP = 2888, and k = 3354, r=357, d CP = 1344, and k = 3362, r=357, d CP = 3528, and k = 3364, r=358, d CP = 1984, and k = 3372, r=359, d CP = 440, and k = 3380, r=359, d CP = 2624, and k = 3382, r=360, d CP =1080, and k=3390, r=360, d CP = 3264, and k = 3392, r=361, d CP = 1720, and k = 3400, r=365, d CP = 1592, and k = 3192, r=366, d CP = 720, and k = 3200, r=366, d CP = 3072, and k = 3202, r=367, d CP = 2200, and k = 3210, r=368, d CP =1328, and k=3218, r=368, d CP = 3680, and k = 3220, r=369, d CP = 2304, and k = 2658, r=369, d CP = 456, and k = 3226, r=369, d CP = 2808, and k = 3228, r=370, d CP =592, and k=2664, r=370, d CP =3448, and k=2666, r=370, d CP = 1936, and k = 3236, r=371, d CP = 1736, and k = 2672, r=384, d CP =1488, and k=3358, r=384, d CP = 3840, and k = 3360, r=385, d CP = 616, and k = 3366, r=385, d CP = 2968, and k = 3368, r=386, d CP = 2096, and k = 3376, r=387, d CP = 1224, and k = 3384, r=387, d CP = 3576, and k = 3386, r=388, d CP = 352, and k = 3392, r=388, d CP = 2704, and k = 3394, r=389, d CP = 1832, and k = 3402, r=391, d CP = 2440, and k = 2660, r=392, d CP = 1232, and k = 2666, r=392, d CP = 2240, and k = 3200, r=393, d CP = 24, and k = 2672, r=393, d CP = 3048, and k = 2674, r=393, d CP = 2040, and k = 3208, r=394, d CP = 1840, and k = 3216, r=395, d CP = 1640, and k = 3224, r=396, d CP = 1440, and k = 3232, r=396, d CP = 3960, and k = 3234, r=397, d CP = 1240, and k = 3240, r=397, d CP = 3760, and k = 3242, r=411, d CP = 960, and k = 3354, r=411, d CP = 3480, and k = 3356, r=412, d CP = 760, and k = 3362, r=412, d CP = 3280, and k = 3364, r=413, d CP = 2912, and k = 2662, r=413, d CP = 560, and k = 3370, r=413, d CP = 3080, and k = 3372, r=414, d CP = 2208, and k = 2668, r=414, d CP = 360, and k = 3378, r=414, d CP = 2880, and k = 3380, r=415, d CP = 1504, and k = 2674, r=415, d CP = 160, and k = 3386, r=415, d CP = 2680, and k = 3388, r=416, d CP = 2480, and k = 3396, r=418, d CP = 1072, and k = 3198, r=418, d CP = 3760, and k = 3200, r=419, d CP = 1544, and k = 3206, r=419, d CP = 4232, and k = 3208, r=420, d CP =2016, and k=3214, r=421, d CP = 2488, and k = 3222, r=422, d CP = 272, and k = 3228, r=422, d CP = 2960, and k = 3230, r=423, d CP =744, and k=3236, r=423, d CP = 3432, and k = 3238, r=434, d CP = 560, and k = 2656, r=434, d CP = 3920, and k = 2658, r=435, d CP = 360, and k = 2662, r=435, d CP = 3720, and k = 2664, r=436, d CP = 160, and k = 2668, r=436, d CP = 3520, and k = 2670, r=437, d CP = 3320, and k = 2676, r=438, d CP = 2448, and k = 3352, r=439, d CP = 232, and k = 3358, r=439, d CP = 2920, and k = 3360, r=440, d CP = 704, and k = 3366, r=440, d CP = 3392, and k = 3368, r=441, d CP = 1176, and k = 3374, r=441, d CP = 3864, and k = 3376, r=442, d CP =1648, and k=3382, r=442, d CP = 4336, and k = 3384, r=443, d CP = 2120, and k = 3390, r=444, d CP = 2424, and k = 3198, r=444, d CP = 2592, and k = 3398, r=445, d CP = 712, and k = 3204, r=445, d CP = 3568, and k = 3206, r=446, d CP = 1856, and k = 3212, r=447, d CP = 144, and k = 3218, r=447, d CP = 3000, and k = 3220, r=448, d CP =1288, and k=3226, r=448, d CP = 4144, and k = 3228, r=449, d CP = 2432, and k = 3234, r=456, d CP = 1032, and k = 2658, r=456, d CP = 4560, and k = 2660, r=457, d CP = 1336, and k = 2664, r=458, d CP = 1640, and k = 2670, r=459, d CP = 1944, and k = 2676, r=466, d CP =1888, and k=3356, r=466, d CP = 4744, and k = 3358, r=467, d CP = 176, and k = 3362, r=467, d CP = 3032, and k = 3364, r=468, d CP = 1320, and k = 3370, r=468, d CP = 4176, and k = 3372, r=469, d CP = 2464, and k = 3378, r=470, d CP = 752, and k = 3196, r=470, d CP = 3776, and k = 3198, r=470, d CP =752, and k=3384, r=470, d CP = 3608, and k = 3386, r=471, d CP = 2568, and k = 3204, r=471, d CP =1896, and k=3392, r=471, d CP = 4752, and k = 3394, r=472, d CP = 1360, and k = 3210, r=472, d CP = 4384, and k = 3212, r=472, d CP = 184, and k = 3398, r=472, d CP = 3040, and k = 3400, r=473, d CP = 152, and k = 3216, r=473, d CP = 3176, and k = 3218, r=474, d CP = 1968, and k = 3224, r=475, d CP = 760, and k = 3230, r=475, d CP = 3784, and k = 3232, r=476, d CP = 2576, and k = 3238, r=478, d CP = 1840, and k = 2660, r=479, d CP = 2648, and k = 2666, r=480, d CP = 3456, and k = 2672, r=481, d CP =568, and k=2676, r=481, d CP = 4264, and k = 2678, r=493, d CP = 184, and k = 3352, r=493, d CP = 3208, and k = 3354, r=494, d CP = 2000, and k = 3360, r=494, d CP = 5024, and k = 3362, r=495, d CP =792, and k=3366, r=495, d CP = 3816, and k = 3368, r=496, d CP = 1936, and k = 3196, r=496, d CP = 2608, and k = 3374, r=497, d CP = 1232, and k = 3202, r=497, d CP = 4424, and k = 3204, r=497, d CP = 1400, and k = 3380, r=497, d CP = 4424, and k = 3382, r=498, d CP = 528, and k = 3208, r=498, d CP = 3720, and k = 3210, r=498, d CP = 192, and k = 3386, r=498, d CP = 3216, and k = 3388, r=499, d CP = 1672, and k = 2656, r=499, d CP = 3016, and k = 3216, r=499, d CP = 2008, and k = 3394, r=499, d CP = 5032, and k = 3396, r=500, d CP = 2984, and k = 2662, r=500, d CP = 2312, and k = 3222, r=500, d CP = 800, and k = 3400, r=500, d CP = 3824, and k = 3402, r=501, d CP = 432, and k = 2666, r=501, d CP = 4296, and k = 2668, r=501, d CP =1608, and k=3228, r=501, d CP = 4800, and k = 3230, r=502, d CP = 1744, and k = 2672, r=502, d CP = 904, and k = 3234, r=502, d CP = 4096, and k = 3236, or r=503, d CP 74. A data processing apparatus according to any one of claims 70 to 73, wherein n=3056, and k=2678.

75. d scr 75. A data processing apparatus according to any one of claims 70 to 74, wherein k = 336 × k.

76. Specifically, the second data processing unit: configured to perform a CRC-32 check on a total of r×q / p bits in each r / p rows of the first data and add 32 parity bits; and d CRC = 32 × p, r is divisible by p, and p is an integer greater than 1, or The first r of the first data F0 ×r in (p-1) rows F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and add the last r of the first data. F1 Total in rows q×r F1 configured to perform a CRC-32 check on the bits and add 32 parity bits, CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and integer r F0 is an integer r F1 76. A data processing device according to any one of claims 70 to 75, wherein the data processing device is larger than the one claimed in claim 70.

77. 77. A data processing apparatus according to any one of claims 70 to 76, wherein q=2056.

78. Specifically, the second data processing unit: The first r of the first data F0 ×r in (p-1) rows F0 Total of q×r in each row F0 Perform a CRC-32 check on the bits, add 32 parity bits, and add the last r of the first data. F1 Total in rows q×r F1 configured to perform a CRC-32 check on the bits and add 32 parity bits, CRC = 32 × p, r is not divisible by p, p is an integer greater than 1, and r F0 ×(p-1)+r F1 = r, and integer r F0 is an integer r F1 78. A data processing apparatus according to claim 77, wherein the data processing apparatus is larger than the first data processing apparatus.

79. 79. A data processing device according to claim 77 or 78, wherein r=435.

80. p=22 and r F0 = 20, and r F1 =15, and the second data processing unit specifically:

80. The data processing apparatus of claim 79, configured to perform a CRC-32 check on a total of 41,120 bits in every 20 rows of the first 420 rows of the first data to add 32 parity bits, and to perform a CRC-32 check on a total of 30,840 bits in the last 15 rows of the first data to add 32 parity bits.

81. d CP = 3432 and k = 2672, or d CP 81. A data processing device according to claim 79 or 80, wherein k=744 and k=2664.

82. r=546, d CP = 1008, and k = 3344, r=546, d CP = 3696, and k = 3352, r=547, d CP = 1640, and k = 3352, r=547, d CP = 4328, and k = 3360, r=548, d CP = 2272, and k = 3360, r=548, d CP = 4960, and k = 3368, r=549, d CP = 216, and k = 3360, r=549, d CP = 2904, and k = 3368, r=549, d CP = 5592, and k = 3376, r=550, d CP =848, and k=3368, r=550, d CP = 3536, and k = 3376, r=551, d CP = 1480, and k = 3376, r=551, d CP =4168, and k=3384, r=552, d CP = 2112, and k = 3384, r=552, d CP = 4800, and k = 3392, r=553, d CP = 56, and k = 3384, r=553, d CP = 2744, and k = 3392, r=553, d CP = 5432, and k = 3400, r=554, d CP = 688, and k = 3392, r=554, d CP = 3376, and k = 3400, r=555, d CP = 1320, and k = 3400, r=555, d CP = 4008, and k = 3408, r=556, d CP = 1952, and k = 3408, r=556, d CP = 4640, and k = 3416, r=557, d CP = 2584, and k = 3416, r=557, d CP =5272, and k=3424, r=558, d CP = 528, and k = 3416, r=558, d CP = 3216, and k = 3424, r=559, d CP = 1160, and k = 3424, r=559, d CP =3848, and k=3432, r=560, d CP =1792, and k=3432, r=560, d CP = 4480, and k = 3440, r=561, d CP = 2424, and k = 3440, r=561, d CP =5112, and k=3448, r=562, d CP = 368, and k = 3440, r=562, d CP = 3056, and k = 3448, or r=562, d CP 79. A data processing device according to claim 77 or 78, wherein n=5744 and k=3456.

83. r=520, d CP = 704, and k = 3184, r=520, d CP = 3392, and k = 3192, r=520, d CP = 6080, and k = 3200, r=521, d CP = 1336, and k = 3192, r=521, d CP = 4024, and k = 3200, r=522, d CP = 1968, and k = 3200, r=522, d CP = 4656, and k = 3208, r=523, d CP = 2600, and k = 3208, r=523, d CP =5288, and k=3216, r=524, d CP = 544, and k = 3208, r=524, d CP = 3232, and k = 3216, r=525, d CP = 1176, and k = 3216, r=525, d CP = 3864, and k = 3224, r=526, d CP =1808, and k=3224, r=526, d CP = 4496, and k = 3232, r=527, d CP = 2440, and k = 3232, r=527, d CP =5128, and k=3240, r=528, d CP = 384, and k = 3232, r=528, d CP = 3072, and k = 3240, r=528, d CP =5760, and k=3248, r=529, d CP = 1016, and k = 3240, r=529, d CP = 3704, and k = 3248, r=530, d CP =1648, and k=3248, r=530, d CP = 4336, and k = 3256, r=531, d CP = 2280, and k = 3256, r=531, d CP =4968, and k=3264, r=532, d CP = 2912, and k = 3264, r=532, d CP = 224, and k = 3256, r=533, d CP =856, and k=3264, r=533, d CP = 3544, and k = 3272, r=534, d CP =1488, and k=3272, r=534, d CP = 4176, and k = 3280, r=535, d CP = 2120, and k = 3280, or r=535, d CP 79. A data processing device according to claim 77 or 78, wherein k=4808 and k=3288.

84. The fourth bit set is m 0 m first bit subsets, 0 is an integer greater than 1, and the data processing device further includes a first interleaving unit; The first interleaving unit is configured to perform a first interleaving process on the fourth set of bits to obtain a fifth set of bits, and the fifth set of bits is m 0 84. A data processing apparatus according to any one of claims 70 to 83, comprising second bit subsets, each of the second bit subsets comprising 256 bits, 128 bits in each of the second bit subsets being from the second bit set, and the other 128 bits in each of the second bit subsets being from the third bit set and / or parity bits of the FEC coding.

85. 85. A data processing apparatus as claimed in claim 84, wherein each of said second subsets of bits comprises 256 consecutive bits.

86. 85. A data processing apparatus as claimed in claim 84, wherein each of said second subsets of bits is presented as a block.

87. The 256 bits in the second bit subset are distributed into 16 rows and 16 columns, and the bits in the second bit subset are arranged as follows: the bits at row 0 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 1 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 2 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits at row 3 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 4 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 5 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 6 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits at row 7 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 8 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 9 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 10 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; the bits in row 11 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set; the bits at row 12 and columns 2, 3, 6, 7, 10, 11, 14, and 15 of the second bit subset are from the second bit set; the bits at row 13 and columns 0, 3, 4, 7, 8, 11, 12, and 15 of the second bit subset are from the second bit set; the bits at row 14 and columns 0, 1, 4, 5, 8, 9, 12, and 13 of the second bit subset are from the second bit set; and 87. A data processing apparatus according to any one of claims 84 to 86, wherein one or more of the following are satisfied: the bits in row 15 and columns 1, 2, 5, 6, 9, 10, 13, and 14 of the second bit subset are from the second bit set.

88. m in the fourth bit set 0 ×256 bits, 32 rows and m 0 ×8 columns, and m 0 ×256 bits, 32 rows and m 0 ×8 columns, and row r in the fifth bit set 1 m in 0 ×8 bits are assigned to row r in the fourth bit set. 0 m in 0 × 8 bits, and 0 ≤ r 0 < 32 and 0 ≤ r 1 88. A data processing device according to any one of claims 84 to 87, wherein <32.

89. r 0 =r 1 89. The data processing device of claim 88, wherein:

90. The fourth bit set is m 0 m first bit subsets, 0 90. A data processing device according to any one of claims 70 to 89, wherein =12 or 16.

91. the data processing device further includes a second interleaving unit, a symbol mapping unit, a polarization distribution unit, and a digital signal processing DSP framing unit; the second interleaving unit is configured to perform a second interleaving process on every two first bit streams among the L first bit streams to obtain a total of L / 2 second bit streams, where each first bit stream includes a plurality of fifth bit sets, and L is an even number greater than 0; the symbol mapping unit and the polarization distribution unit are configured to perform symbol mapping and polarization distribution on the L / 2 second bit streams to obtain one dual-polarized symbol stream, wherein t bits are mapped to one dual-polarized symbol by the symbol mapping and the polarization distribution, where t is an integer greater than 0; 91. A data processing apparatus according to any one of claims 84 to 90, wherein said DSP framing unit is configured to perform DSP framing on said dual polarized symbol stream.

92. 92. The data processing apparatus of claim 91, wherein amplitude bits in said dual polarization symbols are from said second bit set.

93. 93. The data processing apparatus of claim 92, wherein t=8 and the dual-polarized symbols are dual-polarized DP-16QAM symbols.

94. 94. The data processing device of claim 93, wherein the DSP framing unit is specifically configured to perform framing processing every 172,032 dual-polarized DP-16QAM symbols to obtain one DSP superframe, and the superframe includes 175,104 dual-polarized symbols.

95. The first processing unit specifically comprises: Frame to obtain F ×r ×q bits from the data frame. Frame configured to acquire first data, F Frame is an integer greater than 0, d scr ×F Frame =336×k×F DSP and F DSP represents the number of DSP superframes, and F DSP DSP superframes are Frame The first data is obtained by processing F DSP 95. The data processing apparatus of claim 94, wherein is an integer greater than zero.

96. F DSP >1, and F DSP A plurality of consecutive symbols in a first DSP superframe of the DSP superframes is a first marker, and the F DSP superframes excluding the first DSP superframe are DSP 96. The data processing apparatus of claim 95, wherein a plurality of consecutive symbols in each of the DSP superframes is a second marker.

97. 1. A data processing apparatus, comprising: a first stochastic constellation shaping PCS unit, a first forward error correction FEC encoding unit, a second PCS unit, a second FEC unit, an interleaving unit, a symbol mapping unit, and a polarization distribution unit; The first PCS unit is configured to perform a first PCS process on a first set of bits in a first group of k bits to obtain a second set of bits, the second set of bits being m 0 × 128 bits, k is an integer greater than 1, and m 0 is an integer greater than 1, The first FEC encoding unit is configured to perform a first forward error correction FEC encoding on the second set of bits and a third set of bits in the first group of k bits excluding the first set of bits to obtain a fourth set of bits, and the fourth set of bits is m 0 first square blocks, each of said first square blocks including a total of 256 bits distributed in 16 rows and 16 columns; the second PCS unit is configured to perform a second PCS process on a fifth set of bits in the second group of k bits to obtain a sixth set of bits; The second FEC encoding unit is configured to perform second FEC encoding on the sixth bit set and a seventh bit set in the second group of k bits excluding the fifth bit set to obtain an eighth bit set, and the eighth bit set is m 0 second square blocks, each of said second square blocks containing a total of 256 bits distributed in 16 rows and 16 columns; The interleave processing unit is configured to input 21 fourth sets of bits and 21 eighth sets of bits to an interleaver buffer, the interleaver buffer having 84 rows and m 1 Total of 84 × m distributed among columns 1 Contains m buffer units 0 =m 1 x2, each of the buffer units configured to buffer a total of 256 bits in 16 rows and 16 columns, and 42 x m 1 The first square blocks are input to the even rows of the interleaver buffer, and 42×m 1 number of second square blocks are input to odd rows of the interleaver buffer, the interleaver buffer including a first buffer subset and a second buffer subset, the first buffer subset being 42×m 1 buffer units, and the second buffer subset comprises 42×m 1 buffer units, wherein bits input to the first buffer subset are from the second bit set and the sixth bit set, and bits input to the second buffer subset are from the third bit set, the seventh bit set, parity bits of the first FEC encoding, and parity bits of the second FEC encoding; the symbol mapping unit and the polarization distribution unit are configured to perform symbol mapping and polarization distribution for every 8 bits in the interleaver buffer to obtain one dual-polarized DP-16QAM symbol, wherein two amplitude bits among four bits corresponding to a 16QAM symbol of the DP-16QAM symbol in a target polarization direction are from one column in a first buffer unit of the first buffer subset, and two code bits among four bits corresponding to the 16QAM symbol of the DP-16QAM symbol in the target polarization direction are from one column in a second buffer unit of the second buffer subset.

98. 98. The data processing apparatus of claim 97, wherein four of the eight bits are from one column of the first buffer units of the first buffer subset, and the other four of the eight bits are from one column of the second buffer units of the second buffer subset.

99. m 0 The first square blocks are arranged in two rows and m 1 distributed across columns, row 0 and column m 2 The first square block in row 1 and column m 2 the first square block in m is from the second bit set, 0 The second square blocks are arranged in two rows and m 1 distributed across columns, row 0 and column m 2 The second square block in and row 1 and column m 2 the second square block in is from the sixth bit set, and 0≦m 2 <m 1 99. A data processing device according to claim 97 or 98, wherein:

100. m 0 =16, and the first buffer subset includes a total of 336 buffer units in columns 0, 1, 2, and 3 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 4, 5, 6, and 7 of the interleaver buffer; or m 0 100. The data processing apparatus of claim 99, wherein: =12, the first buffer subset includes a total of 252 buffer units in columns 0, 1, and 2 of the interleaver buffer, and the second buffer subset includes a total of 252 buffer units in columns 3, 4, and 5 of the interleaver buffer.

101. m 0 = 16, and m 1 = 8, m 0 The first square blocks are arranged in two rows and m 1 distributed into columns, wherein the first square block at row 0, column 0, the first square block at row 0, column 1, the first square block at row 0, column 4, the first square block at row 0, column 5, the first square block at row 1, column 0, the first square block at row 1, column 1, the first square block at row 1, column 4, and the first square block at row 1, column 5 are from the second bit set; m 0 The second square blocks are arranged in two rows and m 1 99. A data processing device as claimed in claim 97 or 98, wherein the second square block at row 0 and column 0, the second square block at row 0 and column 1, the second square block at row 0 and column 4, the second square block at row 0 and column 5, the second square block at row 1 and column 0, the second square block at row 1 and column 1, the second square block at row 1 and column 4 and the second square block at row 1 and column 5 are from the sixth bit set.

102. 102. The data processing apparatus of claim 101, wherein the first buffer subset includes a total of 336 buffer units in columns 0, 1, 4, and 5 of the interleaver buffer, and the second buffer subset includes a total of 336 buffer units in columns 2, 3, 6, and 7 of the interleaver buffer.

103. 52. A data processing apparatus comprising a processor and a transceiver, wherein said processor is configured to perform the method of any one of claims 1 to 51, and said transceiver is configured to perform data transmission and reception operations.

104. 52. A communication system comprising a transmitter data processing device and a receiver data processing device, wherein the transmitter data processing device is configured to perform a method according to any one of claims 1 to 51, and wherein the transmitter data processing device is configured to transmit a data stream to the receiver data processing device.

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