NON-CASCADING MIMO CHANNEL EXTENDER FOR RADAR CHIP

Abstract

The receive extender in the integrated circuit may include N phase adjustment circuits that adjust the phases of N receive signals from the N receive antennas and an N:1 demultiplexer that coherently combines the N receive signals into one output signal that is provided to the transceiver chip. Furthermore, the transmit extender in the integrated circuit may include a 1:M multiplexer that coherently separates the transmit signal from the transceiver chip into M transmit signals, where N and M are non-zero integers that may be different, and M phase adjustment circuits that adjust the phases of the M transmit signals that are provided to the M transmit antennas. Note that the integrated circuit may be coupled to a second integrated circuit that phase-shifts the output and transmit signals based at least in part on an oscillator signal. Furthermore, control signals between the integrated circuit and the second integrated circuit may be synchronized.

Description

[Technical Field]

[0001] The present disclosure relates to techniques for increasing the number of transmitters and receivers in a multiple-input multiple-output (MIMO) radar system using extender chips. [Background technology]

[0002] To provide improved safety and convenience for transportation, many automobile manufacturers are equipping their vehicles with additional sensors and / or features. For example, autonomous vehicles typically include a wide variety of sensors, such as acoustic and / or electromagnetic sensors, that monitor the surrounding environment to detect other vehicles, people, animals, or obstacles. However, many of these sensors (e.g., MIMO radar systems), which may include multiple transmitters and receivers, are still prohibitively expensive. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Co-owned Patent Application No. US16 / 660,370 Summary of the Invention [Means for solving the problem]

[0004] The above-identified shortcomings may be addressed, at least in part, by a MIMO radar system with a channel extender that further increases the number of receive and / or transmit antennas that can be supported by a given radar transceiver. One exemplary radar system includes a radar transceiver that generates a transmit signal and downconverts at least one receive signal, and a receive-side extender that couples to a set of receive antennas to obtain a set of input signals and adjustably phase-shifts each of the input signals to generate a set of phase-shifted signals, and that couples to the radar transceiver to provide at least one receive signal, the at least one receive signal being a sum of the phase-shifted signals.

[0005] An exemplary receive extender includes a set of phase shifters, each of which applies an adjustable phase shift to a respective input signal, a power combiner that combines the outputs of the phase shifters to form a receive signal, and an internal memory that stores a different sequence of phase shift adjustments for each of the phase shifters. The receive extender may further include an external interface that controls the timing for providing the different sequences from the memory to the phase shifters.

[0006] An exemplary transmit-side extender includes a power splitter that splits each transmit signal into multiple signal copies, a set of multiple phase shifters that each apply an adjustable phase shift to one of the multiple signal copies, a set of power amplifiers that each derive one of the multiple output signals from an output of a corresponding one of the multiple phase shifters, and an internal memory that stores a different sequence of phase shift adjustments for each of the multiple phase shifters. The transmit-side extender may further include an external interface that controls the timing for providing the different sequences from the memory to the multiple phase shifters.

[0007] An exemplary radar detection method includes generating a chirp waveform, deriving a transmit signal from the chirp waveform, obtaining a set of multiple input signals from a set of multiple receive antennas, applying an adjustable phase shift to each of the multiple input signals to provide multiple phase-shifted input signals, summing the multiple phase-shifted input signals to form a receive signal, combining the receive signal with the chirp waveform to obtain a downconverted receive signal, deriving a set of digital input signals from the downconverted receive signals, and processing the set of digital input signals to determine reflected energy as a function of range or traveltime.

[0008] Exemplary systems, extenders, and methods may be employed, individually or jointly, with one or more of the following optional features in any suitable combination: 1. The transmit signal includes a sequence of chirps. 2. The receive extender adjusts the phase shifts of the multiple input signals once per chirp. 3. The adjusted phase shifts impart progressive phase shifts to the multiple input signals for beam steering. 4. The adjusted phase shifts perform code division multiplexing of the multiple input signals. 5. The radar transceiver processes at least one downconverted receive signal to obtain a demultiplexed set of digital input signals. 6. The receive extender adjusts the phase shifts of the multiple input signals multiple times in each chirp. 7. The adjusted phase shifts impart different frequency shifts, different frequency sweep rates, or different coding modulations to the multiple input signals. 8. One or more transmit extenders each coupled to the radar transceiver to obtain a respective transmit signal and each coupled to a respective set of multiple transmit antennas to provide a set of multiple output signals, each of the multiple output signals having an adjustable phase shift. 9. The transmit extenders adjust the phase shifts of the multiple output signals once per chirp. 10. The adjusted phase shifts impart progressive phase shifts to the multiple output signals for beam steering. 11. The adjusted phase shifts impart quadrature coded modulation to the multiple output signals. 12. The radar transceiver processes at least one downconverted receive signal to obtain a demultiplexed set of digital input signals for each of the transmit antennas. 13. The transmit extenders adjust the phase shifts of the multiple output signals multiple times in each chirp. 14. The adjusted phase shifts impart different frequency shifts, different frequency sweep rates, or different coded modulation to the multiple output signals. 15. Each transmitting extender includes a power splitter that splits a respective transmit signal into multiple signal copies, a set of multiple phase shifters that each apply an adjustable phase shift to one of the multiple signal copies, and a set of power amplifiers that each derive one of the multiple output signals from the output of a corresponding one of the multiple phase shifters.16. Each of the receive extenders includes a set of multiple phase shifters, each applying an adjustable phase shift to one of the multiple input signals, and a power combiner that combines the outputs of the multiple phase shifters to form a respective receive signal. 17. Each extender includes an internal memory for storing a different sequence of phase shift adjustments for each of the multiple input signals. 18. Each extender includes an external interface that controls the timing for providing the different sequences from the memory to the multiple phase shifters. 19. The radar transceiver provides a clock signal to each of the extenders and controls the timing for providing the sequences of phase shift adjustments from the internal memory to the multiple phase shifters. 20. The obtaining, applying, and summing are performed by a receive extender coupled to the radar transceiver, which performs the combining, deriving, and processing.

[0009] An embodiment of an integrated circuit including a receive extender is described. The integrated circuit includes: N receive (or input) contacts coupled to N receive antennas, where N is a non-zero integer; N phase adjustment circuits coupled to the N receive contacts, where a given phase adjustment circuit among the N phase adjustment circuits is coupled to a given receive contact of the N receive contacts; an N:1 demultiplexer coupled to the N phase adjustment circuits; an amplifier coupled to the N:1 demultiplexer; an output contact coupled to the amplifier; and a control circuit for controlling the N phase adjustment circuits. The integrated circuit is further coupled to a second integrated circuit, which performs phase and / or frequency shifting of the output signal based at least in part on an oscillator signal. During operation, the integrated circuit receives N receive signals at the N receive contacts. After phase adjusting the N receive signals using the N phase adjustment circuits, the integrated circuit combines the N receive signals using the N:1 demultiplexer. The integrated circuit then amplifies the combined received signal using an amplifier, and an output signal is provided by the amplifier on an output contact to a second integrated circuit. Further, the control signals between the control circuit and a second control circuit on the second integrated circuit are synchronized, and the oscillator signals between the integrated circuit and the second integrated circuit are not synchronized.

[0010] Note that the N received signals may be coherently combined (eg, by maintaining the relative phase of the N received signals when combining).

[0011] Additionally, the N phase adjustment circuits may apply different phase adjustments to the N received signals.

[0012] Furthermore, the configuration of the integrated circuit and the second integrated circuit may differ from the cascaded configuration.

[0013] Additionally, the integrated circuit may be different from the second integrated circuit.

[0014] In some embodiments, the N phase-shift adjustment circuits are implemented in the analog domain.

[0015] Note that the second integrated circuit may perform analog-to-digital conversion (ADC) and signal processing.

[0016] Additionally, the integrated circuit may increase the number of receive antennas coupled to the second integrated circuit.

[0017] Furthermore, the frequency shift can be from a frequency band at RF to a second frequency band lower than the first frequency band, for example, the second frequency band can be an intermediate frequency band above DC or baseband.

[0018] In addition, the second integrated circuit may include a transceiver chip.

[0019] Another embodiment provides a third integrated circuit including a transmit extender. The third integrated circuit includes input contacts, a 1:M multiplexer coupled to the input contacts, where M is a non-zero integer, M phase adjustment circuits coupled to the 1:M multiplexer, M power amplifiers coupled to the M phase adjustment circuits, where a given one of the M power amplifiers is coupled to a given one of the M phase adjustment circuits, M output (or transmit) contacts coupled to the M power amplifiers and the M transmit antennas, where a given one of the M output contacts is coupled to a given power amplifier, and a third control circuit that controls the M phase adjustment circuits. The integrated circuit is further coupled to a second integrated circuit, where the second integrated circuit performs phase and / or frequency shifting of the transmit signal based at least in part on an oscillator signal. During operation, the third integrated circuit receives a transmit signal on the input contact from the second integrated circuit. The third integrated circuit then separates the transmit signal into M transmit signals using a 1:M multiplexer. Further, the third integrated circuit phase-adjusts the M transmit signals using M phase adjustment circuits. Next, the third integrated circuit amplifies the M transmit signals using M power amplifiers and outputs the M transmit signals on M output contacts. Further, the control signals between the third control circuit and the second control circuit on the second integrated circuit are synchronized, and the oscillator signals between the second integrated circuit and the third integrated circuit are not synchronized.

[0020] It should be noted that the M transmit signals may be coherently separated (eg, by maintaining the phase of the transmit signals of the M transmit signals when separating).

[0021] Additionally, the M phase adjustment circuits may apply different phase adjustments to the M transmit signals.

[0022] Furthermore, the configuration of the second integrated circuit and the third integrated circuit may differ from the cascaded configuration.

[0023] In addition, the third integrated circuit may be different from the second integrated circuit.

[0024] In some embodiments, the M phase-shift adjustment circuits are implemented in the analog domain.

[0025] Additionally, the second integrated circuit may perform the ADC and signal processing.

[0026] Furthermore, N may be different from M.

[0027] Additionally, the third integrated circuit may increase the number of transmission channels output by the second integrated circuit.

[0028] Additionally, the frequency shift can be from a frequency band at RF to a second frequency band lower than the first frequency band, for example, an intermediate frequency band above DC or baseband.

[0029] In some embodiments, the second integrated circuit may include a transceiver chip.

[0030] Another embodiment provides a fourth integrated circuit including a receive extender and a transmit extender.

[0031] Another embodiment provides a system including a second integrated circuit and one or more of the integrated circuit, the third integrated circuit, and / or the fourth integrated circuit.

[0032] Another embodiment provides a method for enhancing an integrated circuit, the method including at least some of the operations performed by an integrated circuit, a second integrated circuit, a third integrated circuit, and / or a fourth integrated circuit.

[0033] This Summary is presented for the purposes of illustrating some exemplary embodiments to aid in a basic understanding of some aspects of the subject matter described herein. Accordingly, it will be understood that the features described above are examples and should not be construed in any way as narrowing the scope or spirit of the subject matter described herein. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following Detailed Description, Figures, and Claims. [Brief explanation of the drawings]

[0034] [Figure 1] 1 is a diagram illustrating an example of a vehicle equipped with a radar sensor according to some embodiments of the present disclosure. [Figure 2] FIG. 1 is a block diagram illustrating an example of a driver assistance system according to some embodiments of the present disclosure. [Figure 3] FIG. 1 is a block diagram illustrating an example of a radar system according to some embodiments of the present disclosure. [Figure 4] FIG. 1 is a block diagram illustrating an example of a radar system according to some embodiments of the present disclosure. [Figure 5] FIG. 1 is a block diagram illustrating an example of a radar transceiver chip according to some embodiments of the present disclosure. [Figure 6] FIG. 1 is a block diagram illustrating an example of a radar system having an extender chip according to some embodiments of the present disclosure. [Figure 7] FIG. 1 is a block diagram illustrating an example of an input extender chip according to some embodiments of the present disclosure. [Figure 8] FIG. 1 is a block diagram illustrating an example of an output extender chip according to some embodiments of the present disclosure. [Figure 9A] FIG. 1 is a block diagram illustrating an example of a data cube representing an acquired set of radar measurements and a transformed set of radar measurements according to some embodiments of the present disclosure. [Figure 9B]FIG. 1 is a block diagram illustrating an example of a data cube representing an acquired set of radar measurements and a transformed set of radar measurements according to some embodiments of the present disclosure. [Figure 10] 1 is a flow diagram of an example data flow in a radar system according to some embodiments of the present disclosure. [Figure 11] 1 is a flow chart illustrating an example of a method for radar detection according to some embodiments of the present disclosure. [Figure 12] FIG. 1 is a block diagram illustrating an example of a cascaded chip according to some embodiments of the present disclosure. [Figure 13] FIG. 1 is a block diagram illustrating an example of a radar chip and an extender chip according to some embodiments of the present disclosure. [Figure 14] FIG. 1 is a block diagram illustrating an example of a radar chip and a transmit channel extender chip according to some embodiments of the present disclosure. [Figure 15] FIG. 1 is a block diagram illustrating an example of a radar chip and a receive channel extender chip according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0035] It should be noted that like reference numbers refer to corresponding parts throughout the drawings. Additionally, multiple instances of the same part are designated by a common prefix separated from the instance number by a dash.

[0036] An integrated circuit including a receive extender is described. The integrated circuit may include N receive contacts coupled to N receive antennas, where N is a non-zero integer; N phase adjustment circuits coupled to the N receive contacts, where a given phase adjustment circuit among the N phase adjustment circuits is coupled to a given receive contact of the N receive contacts; an N:1 demultiplexer coupled to the N phase adjustment circuits; an amplifier coupled to the N:1 demultiplexer; an output contact coupled to the amplifier; and a control circuit for controlling the N phase adjustment circuits. Furthermore, the integrated circuit may be coupled to a second integrated circuit, which performs phase and / or frequency shifting of the output signal based at least in part on an oscillator signal. During operation, the integrated circuit may receive N receive signals on the N receive contacts. After phase adjusting the N receive signals using the N phase adjustment circuits, the integrated circuit may combine the N receive signals using the N:1 demultiplexer. The integrated circuit may then amplify the combined received signal using an amplifier, and an output signal may be provided by the amplifier on an output contact to the second integrated circuit. Further, the control signals between the control circuit and a second control circuit on the second integrated circuit may be synchronized, and the oscillator signals may not be synchronized between the integrated circuit and the second integrated circuit.

[0037] Further, a third integrated circuit including a transmit extender is described. The third integrated circuit may include input contacts, a 1:M multiplexer coupled to the input contacts, where M is a non-zero integer, M phase adjustment circuits coupled to the 1:M multiplexer, M power amplifiers coupled to the M phase adjustment circuits, where a given one of the M power amplifiers is coupled to a given one of the M phase adjustment circuits, M output contacts coupled to the M power amplifiers and the M transmit antennas, where a given one of the M output contacts is coupled to a given power amplifier, and a third control circuit that controls the M phase adjustment circuits. Further, the integrated circuit may be coupled to a second integrated circuit, where the second integrated circuit performs phase and / or frequency shifting of the transmit signal based at least in part on an oscillator signal. During operation, the third integrated circuit may receive a transmit signal on the input contact from the second integrated circuit. The third integrated circuit may then separate the transmit signal into M transmit signals using a 1:M multiplexer. Further, the third integrated circuit may phase adjust the M transmit signals using M phase adjustment circuits. The third integrated circuit may then amplify the M transmit signals using M power amplifiers and output the M transmit signals on M output contacts. Further, the control signals between the third control circuit and a second control circuit on the second integrated circuit may be synchronized, and the oscillator signals may not be synchronized between the second integrated circuit and the third integrated circuit.

[0038] Additionally, a fourth integrated circuit is described that includes a receive extender and a transmit extender.

[0039] These circuit techniques may reduce the cost and complexity of a MIMO radar system including the integrated circuit, the second integrated circuit, the third integrated circuit, and / or the fourth integrated circuit by implementing receive extenders and / or transmit extenders. For example, the integrated circuit, the third integrated circuit, and / or the fourth integrated circuit may be smaller and / or consume less power than the second integrated circuit. Furthermore, these circuit techniques may improve the performance of the MIMO radar system. In particular, the integrated circuit and / or the fourth integrated circuit may increase the number of receive antennas coupled to the second integrated circuit, and the third integrated circuit and / or the fourth integrated circuit may increase the number of transmit channels output by the second integrated circuit. As a result, the circuit techniques may enable the use of MIMO and various applications, such as automotive applications.

[0040] In the following description, a vehicle may include an automobile, a sport utility vehicle, a truck, a motorcycle, a train, an aircraft, a boat, or other type of transportation vehicle, however, in the following description, an automobile is used as an illustrative example of a vehicle.

[0041] Furthermore, in the following description, the vehicle may use one or more types of sensors to perform measurements related to objects in the surrounding environment. While a wide variety of types of sensors may be used, in the following description, a radar sensor is used as an illustrative example. The radar sensor may perform measurements using at least one of various modes of operation (such as pulsed wave or continuous wave) and may involve the use of one or more types of modulation (such as amplitude, frequency, and / or phase modulation). In some embodiments, a frequency-modulated continuous wave (FMCW) radar is used. Furthermore, the transmitted and received radar signals (e.g., having a carrier frequency within a radar frequency band, such as between 3 MHz and 100 GHz) may be generated and / or processed in the analog and / or digital domains.

[0042] Furthermore, in the following discussion, the terms "about" or "substantially" mean that a value is expected to be close to the stated value. However, there may be small variations that prevent values ​​from being stated precisely. As a result, expected variations, such as a 10% difference, are reasonable variations that may occur and are known to be acceptable with respect to stated or ideal goals for one or more embodiments of the present disclosure. In addition, terms such as "first," "second," "next," "last," "previous," "after," and other similar terms are used for ease of description and reference only and are not intended to be limitations on any configuration of elements or sequence of operations with respect to various embodiments of the present disclosure. It should be noted that the use of "coupled," "connected," or any other term is not intended to limit such interaction and signal transmission between two or more devices, systems, components, or anything else to a direct interaction; indirect coupling and connection may also occur.

[0043] Next, we will describe embodiments of the circuit technology. FIG. 1 presents a diagram illustrating an example of a vehicle 110 equipped with an array of radar antennas, including an antenna 112 for short-range sensing (e.g., for parking assistance), an antenna 114 for medium-range sensing (e.g., for monitoring traffic congestion and cut-in events), and an antenna 116 for long-range sensing (e.g., for adaptive cruise control and collision warning), each of which may be located behind the front bumper cover. An antenna 118 for short-range sensing (e.g., for backup assist) and an antenna 120 for medium-range sensing (e.g., for rear collision warning) may be located behind the back bumper cover. Additionally, an antenna 122 for short-range sensing (e.g., for blind spot monitoring and side obstacle detection) may be located behind the car fender. Each antenna and each set of antennas may be grouped into one or more arrays. Furthermore, each array may be controlled by a radar array controller 205 (FIG. 2). In some embodiments, a given set of antennas may perform MIMO radar sensing. The type, number, and configuration of sensors in sensor arrangements for vehicles with driver assistance and autonomous driving functions vary. The vehicle may employ sensor arrangements to detect and measure distance / direction to objects within various detection zones, allowing the vehicle to navigate while avoiding other vehicles and obstacles. While the preceding description illustrates vehicle 110 with radar sensors, in other embodiments, vehicle 110 may include additional types of sensors, such as LiDAR, ultrasonic sensors, cameras, etc.

[0044] FIG. 2 presents a block diagram illustrating an example of a driver assistance system. The driver assistance system may include an electronic control unit (ECU) 210 at the center of a star topology, coupled to various sensors 212 and a radar array controller 214. However, other topologies may include serial, parallel, and hierarchical (tree) topologies. The radar array controller 214 may couple a radio frequency (RF) front end (e.g., in antenna 114) to transmit and receive antennas to transmit electromagnetic waves, receive reflections, and determine the spatial relationship of the vehicle to its surroundings. Additionally, the radar array controller 214 may couple to a carrier signal generator. In some embodiments, the radar array controller 214 may control the timing and sequence of operation of multiple carrier signal generators.

[0045] To provide automated parking assistance, ECU 210 may be coupled to a set of actuators, such as a turn signal actuator 216, a steering actuator 218, a braking actuator 220, and / or a throttle actuator 222. Additionally, ECU 210 may be coupled to an interactive user interface 224 for accepting user input and displaying various measurements and system status.

[0046] Using the user interface 224, sensors, and actuators, the ECU 210 may provide automatic parking, park assist, lane change assist, obstacle and blind spot detection, autonomous driving, and / or other desirable features. During operation of the vehicle 110 (FIG. 1), sensor measurements may be obtained by the ECU 210 and used by the ECU 210 to determine the status of the vehicle 110. Furthermore, the ECU 210 may act based on the status and input information to activate signaling and control transducers to coordinate and maintain the operation of the vehicle 110. For example, operations that may be provided by the ECU 210 include driver assistance functions such as automatic parking, lane following, automatic braking, and automated driving.

[0047] Furthermore, to obtain measurements, ECU 210 may employ a MIMO radar system. Radar systems operate by emitting electromagnetic waves that propagate outward from a transmitting antenna, which then reflects the waves toward a receiving antenna. A reflector may be any moderately reflective object in the path of the emitted electromagnetic wave. By measuring the propagation time of the electromagnetic wave from the transmitting antenna to the reflector and back to the receiving antenna, the radar system can determine the distance to the reflector. Additionally, by measuring the Doppler shift of the electromagnetic wave, the radar system can determine the speed of the reflector relative to vehicle 110 (FIG. 1). When multiple transmitting or receiving antennas are used, or when multiple measurements are taken at different locations, the radar system can determine the direction to the reflector and thereby track the location of the reflector relative to vehicle 110 (FIG. 1). With more advanced processing, multiple reflectors may be tracked. In some embodiments, the radar system may employ array processing to "scan" a directional beam of electromagnetic waves and build a circumferential image of the environment around vehicle 110 (FIG. 1). In general, pulsed and / or continuous wave implementations of radar systems may be implemented.

[0048] FIG. 3 presents a block diagram illustrating one example of a radar system 310 having a MIMO configuration in which J transmitters are collectively coupled to M transmit antennas 312 to (e.g., simultaneously) transmit transmit signals 316, where J and M are nonzero integers. The M possible transmit signals 316 may reflect from one or more reflectors or targets 314 and be received as receive signals 318 via N receive antennas 320 coupled to P receivers, where N and P are nonzero integers. Each receiver may extract the amplitude and phase or propagation delay associated with each of the M transmit signals 316, thereby enabling the system to obtain N·M spatially diverse measurements (although only J·P of the measurements may be obtained simultaneously). Note that each of the measurements may indicate the range to multiple targets and, when combined in various ways, may further indicate the direction and / or velocity of each target. The processing requirements associated with each receiver extracting the J measurements may be reduced through the use of time-division multiplexing and / or orthogonal coding. Furthermore, available antennas can be systematically multiplexed to available transmitters and receivers to collect a complete set of measurements for radar imaging.

[0049] FIG. 4 presents a block diagram illustrating an example of a radar transceiver circuit 410 (e.g., in the radar system 310 of FIG. 3). In some embodiments, the radar transceiver circuit 410 is implemented as an integrated circuit in a packaged chip. The radar transceiver circuit 410 may include a carrier signal (chirp) generator 412 that converts a local oscillator (LO) signal into an FMCW signal (e.g., a signal) including a series of linearly swept frequency chirps, a phase shifter 414 (and, more generally, an encoder circuit, which may implement Doppler code multiplexing), an amplifier 416, and / or a transmit antenna 312 that can transmit a signal 316 based at least in part on the output of the carrier signal generator 412. Additionally, the radar transceiver circuit 410 may include a receive antenna 320, a low-noise amplifier (LNA) 418, and / or a mixer 420 (which, in some embodiments, may implement Doppler code multiplexing). A mixer 420 may mix the received signal 318 detected by the receive antenna 312 with the signal from the carrier signal generator 412. Additionally, a low-noise amplifier 418 may be used to amplify the received signal 318 detected by the receive antenna 320. In some embodiments, the radar transceiver circuit 410 may include a sensitivity time controller and equalizer (not shown), a wideband (BB) filter 422, an ADC 424, and / or a processor 426 (e.g., the ECU 210 and / or the radar array controller 214 of FIG. 2 ) to perform further processing (such as a Fourier transform) of the received signal. In some embodiments, the processor 426 and the low-noise amplifier 418 may be coupled for bidirectional communication.

[0050] Additionally, in some embodiments, the carrier signal generator 412 may be coupled to the radar array controller 214 (FIG. 2). The carrier signal generator 412 may include a chirp generator for generating an FMCW signal. The chip rate of the carrier signal generator 412 may be controlled by the radar array controller 214 (FIG. 2). In some embodiments, the carrier signal generator 412 may be deactivated by the radar array controller 214 (FIG. 2) to provide an unmodulated carrier signal. Furthermore, the carrier signal generator 412 may be implemented as a local oscillator (LO) signal generator, a fractional-N phase-locked loop (PLL) with a ΣΔ controller, or a direct digital synthesis generator.

[0051] Further, the carrier signal generator 412 may be coupled to the transmit antenna 312 via a phase shifter 414 and an amplifier 416. The carrier signal generator 412 may be coupled to the receive antenna 312 through a mixer 420 and a low-noise amplifier 418. In addition, the carrier signal generator 412 may generate a transmit signal (e.g., a chirp signal). The amplifier 416 may receive the transmit signal from the carrier signal generator 412, and a transmit signal 316 corresponding to the transmit signal from the carrier signal generator 412 may be transmitted using the transmit antenna 312.

[0052] In some embodiments, the radar transmitter may include a phase rotator, a binary phase modulator, a variable gain amplifier, a switch, a power amplifier driver, a power amplifier, and / or a digital signal processor (DSP). Additionally, in some embodiments, the radar transmitter may include a digital controller. This digital controller may be included in the DSP or may be a separate component. Furthermore, the phase rotator may be used for digital phase modulation. Additionally, the radar transmitter may use a wave modulation power amplifier in a digital envelope modulation technique.

[0053] FIG. 5 presents a block diagram illustrating an example of a radar transceiver chip 502 or “RF front-end” chip for use in a MIMO radar system. The transceiver chip 502 may include a chirp generator 404 that converts an LO signal into an FMCW signal, such as a signal including a series of linearly swept frequency chirps. Additionally, a power splitter 506 may split off a portion of the FMCW signal power and provide copies of the FMCW signal to a downconversion mixer 507. Additionally, the remainder of the FMCW signal may pass through a set of phase shifters 508 that a controller 509 may use to phase-shift the FMCW signal independently for each of the RF outputs.

[0054] In some embodiments, phase shifting can be used in various ways to provide coherent beam steering or channel separation, for example, to enable virtual beam steering. Channel separation can be provided using quadrature coded phase modulation, which uses a different code pattern for each channel. Alternatively, or in addition, phase shifting can provide channel separation through the use of different frequency shifts, different frequency sweep rates, and / or spreading codes (e.g., Barker codes, maximum length sequence codes, etc.). Phase modulation can be 1-bit (e.g., binary phase shift keying), 2-bit (e.g., quadrature phase shift keying), or higher order modulation (N-bit). The power amplifier 510 can receive the phase-shifted FMCW signal and drive three transmit signals (Tx0 to Tx2) at its output terminals. While the radar transceiver chip is illustrated with three transmit signals, other embodiments may have more or fewer transmit signals. The transmit signals can be fed to transmit antennas or to a transmit extender chip, which increases the number of transmit antennas driven from the transceiver chip 502, as described further below.

[0055] The transceiver chip 502 may include contacts for acquiring four receive signals (Rx0 to Rx3) from the receive antennas or from a receive extender chip that, as described further below, increases the number of receive antennas supported by the transceiver chip 502. The downconversion mixer 507 may multiply the receive signal by a copy of the FMCW signal and convert the receive signal to near-baseband frequencies passed through a low-pass filter 512. Additionally, the gain control amplifier 514 may adaptively adjust the signal amplitude to optimize use of the dynamic range of the ADC 516. Additionally, the ADC 516 may digitize the receive signal for processing by the controller 509. The controller 509 may be a programmable digital signal processor with high-speed memory (e.g., SRAM) and a serial peripheral interface (SPI), thereby enabling communication with other chips in the MIMO radar system.

[0056] At signal frequencies used in automotive radar (e.g., 80 GHz), it may be preferable to keep antenna feed lines short to minimize attenuation and electromagnetic interference. However, due to the relationship between the physical size of the transceiver chip and the pitch of the antenna array, it may become difficult to keep antenna feed lines acceptably short after the array size exceeds about seven or eight antennas. When employing additional chips (such as extender chips) each supporting a small number of antennas (e.g., three or four), the extender chips may be positioned near the corresponding antennas to minimize feed line length, and inter-chip communication may be protected, at least in part, through the use of amplifiers and additional shielding.

[0057] FIG. 6 presents a block diagram illustrating an example of a radar system with extender chips. The extender chips may increase the number of transmitter and receiver antennas supported by a given transceiver chip 502. In particular, each of four receive signal contacts may be coupled to a given receiver extender chip 602A through 602D. Each receiver extender chip may receive input signals from a corresponding set of receive antennas 604A through 604D, apply an adjustable phase shift to them, and combine the phase-shifted signals to provide a receive signal to the transceiver chip 502. In FIG. 6, each receiver extender chip may combine four input signals to form a receive signal. However, in other embodiments, the number of input signals may be greater or less.

[0058] Furthermore, each of the three transmit signal contacts of the transceiver chip 502 may be coupled to a given transmit extender chip 606A through 606C. Each of the transmit extender chips may convert the transmit signal into multiple output signals to a corresponding set of transmit antennas 608A through 608C, and may use controllable phase shifters to phase-shift or frequency-shift each of the transmit signals by a desired amount and / or modulate each output signal with a desired channel code. In FIG. 6, each of the transmit extender chips may convert the transmit signal into three output signals. However, in other embodiments, the number of output signals may be greater or less.

[0059] The transceiver chip 502 may be coupled to each of the extender chips by digital control signal lines 610, which may include an SPI bus. The signal lines 610 may allow the transceiver chip 502 to program the extender chips with desired phase shifts and / or channel codes, and may allow the transceiver chip 502 to control the timing of any transitions in phase shifts.

[0060] Although not shown in FIG. 6 , extender chips may be employed in a hierarchical manner. For example, rather than coupling the inputs of receive extender chip 602A to antenna 604A, each of those inputs may instead be coupled to an additional, given receive extender chip, thereby increasing the number of antennas multiplexed onto the Rx0 channel of the transceiver chip 502 from 4 to 16. This may be repeated for each of receive extender chips 602B through 602D, thereby increasing the total number of receive antennas from 16 to 64. Note that transmit extender chips 606A through 606C may similarly be coupled to a second level of transmit extender chips, thereby increasing the number of supported transmit antennas from 9 to 27. Additional hierarchical layers may be added, for example, until limited by the processing power of the transceiver chip 502.

[0061] FIG. 7 presents a block diagram illustrating an example of an input or receive extender chip 602. This receive extender chip may have three input contacts for receive antenna signals (RF_IN1 through RF_IN3). Each input signal may be coupled to one of multiple controllable phase shifters 702, and a power combiner 704 may sum the phase shifter outputs to provide a composite receive signal to a low-noise amplifier 706. The LNA 706 may drive the composite receive signal to a downstream chip, such as the transceiver 502, via an output contact RF_OUT. Note that the receive extender chip 602 may include an on-chip controller 710 (or control circuitry) for controlling the phase shifters 702 using a given sequence of adjustable phase shifts from an on-chip memory 708. The timing of the phase shift adjustments may vary, but some embodiments may apply a fixed phase shift to each chirp and switch to the next phase shift for the next chirp. This approach may avoid widening the bandwidth of the composite received signal, but may require the use of multi-chirp measurements to separate the contributions of various antennas, which could potentially affect the time or rate resolution of the measurement. Alternatively, or in addition, the phase shift adjustment may be performed multiple times per chirp, resulting in different frequency shifts, different frequency sweep rates, and / or code modulations to spread the input signal energy over a larger spectrum. Although the transceiver chip 502 may need to increase its binarization rate, multi-chirp measurements may be avoided. In some embodiments, the timing of the phase shift adjustments may be coordinated by the transceiver chip 502 to the extender chip via the SPI bus 712 or via another shared clock signal line.

[0062] In some embodiments, the vehicle electronics may preferably include circuitry for verifying proper operation. Consequently, the receiving extender chip 602 may include an optional power supply voltage monitor 714 to detect under- and over-voltage conditions and may also include an optional test input (RF_INJECT) through which a test signal may be coupled to the antenna input contacts. When the test signal is applied, the transceiver chip 502 may verify that the test signal can be detected from each of the antenna inputs.

[0063] FIG. 8 presents a block diagram illustrating one example of an output or transmitting extender chip 606. This transmitting extender chip may have an input contact that accepts a transmit signal (RF_IN). A power splitter may split the transmit signal into multiple copies, one for each of multiple controllable phase shifters 804. The output of each phase shifter 804 may be coupled to a given transmit signal contact by a corresponding power amplifier 806. Note that the transmit signal contact may be suitable for connecting to a transmit antenna. The transmitting extender chip 606 may include an on-chip controller 810 (or control circuitry) that controls the phase shifters 804 using a given sequence of phase shift adjustments from an on-chip memory 808. As with the receiving extender, in some embodiments, the timing of the phase shift adjustments may be adjusted by the transceiver chip 502 via an SPI bus 812 or via another shared clock signal line. Furthermore, to avoid bandwidth expansion, the transmitter code symbols (phase shifts) for each chirp can remain fixed, e.g., switching only between chirps. Alternatively, or in addition, phase shifters can be used to impart different frequency shifts, different frequency sweep rates, and / or different spreading codes to the output signal.

[0064] Similar to the receiving extender, the transmitting extender may include circuitry for verifying proper operation. For example, an optional power supply voltage monitor 814 may detect under- or overvoltage conditions that could potentially affect component operation. Additionally, an optional phase difference detector 816 may be included to compare the phase between adjacent phase shifters 804, and an optional power detector 818 may be included to monitor the output of the power amplifier 806 for proper operation. As described in commonly owned patent application US 16 / 660,370, entitled "Radar Array Phase Shifter Verification," filed October 22, 2019, inventors Tom Heller et al., operation of the phase shifters may be periodically verified by incrementing through each possible combination of phase shifter settings and verifying that the phase difference detector 816 measures the expected phase difference. Note that the extender chip may notify the transceiver chip 602 of detected faults via the SPI bus.

[0065] 9A and 9B present block diagrams illustrating example data cubes representing an acquired set of radar measurements and a transformed set of radar measurements, respectively. In particular, FIG. 9A illustrates a data cube representing a portion of digital signal measurements that may be collected by the transceiver chip 502. Typically, each chirp may be considered a measurement cycle. However, using code multiplexing, a measurement cycle may span multiple chirps. In a measurement cycle, the RF receiver front end may digitize and separate the downconverted received signal from a selected receive antenna, thereby providing a time sequence of digitized received signal samples. Due to the chirp modulation, signal energy reflected by a target may arrive at the receive antenna with a frequency offset that depends on the round-trip travel time (and therefore the range to the target). A fast Fourier transform (FFT) of the time sequence collected in a given cycle may isolate the energy associated with each frequency offset, thereby forming a function of reflected energy versus target range. This operation, sometimes referred to as a "range FFT," may be performed for each transmit / receive antenna pair in each measurement cycle. The range FFT may yield a peak for each target having a given range.

[0066] Note that target motion relative to the antenna array can impart a Doppler shift to the reflected signal energy. The Doppler shift can be proportional to the relative velocity. The Doppler shift is typically small relative to the frequency offset due to range, but can be observable as a change in the phase of the associated frequency coefficient in subsequent measurement cycles. (Recall that FFT coefficients are complex-valued and have both magnitude and phase.) Applying the FFT to corresponding frequency coefficients over successive measurement cycles can isolate the energy associated with each relative velocity, thereby forming a function of reflected energy versus target velocity. This operation, sometimes referred to as a "velocity FFT," can be performed for each range and each transmit / receive antenna pair. The resulting two-dimensional data array can contain a "peak" for each target having a given range and relative velocity.

[0067] Furthermore, reflected energy from a given target may arrive at individual receive antennas in an antenna array with a phase that depends on the direction of arrival of the reflected energy (this is sometimes referred to as the "angle of approach"). By applying the FFT to the corresponding frequency coefficients associated with a series of uniformly spaced antennas, the energy associated with each angle of incidence can be isolated, thereby forming a function of reflected energy versus angle of approach (AoA). This operation, sometimes referred to as the "AoA FFT," can be performed for each range and velocity using a given transmit antenna.

[0068] Thus, binarized signal measurements arranged into a measurement data cube with three dimensions representing functions of time, measurement cycle, and antenna position (as shown in FIG. 9A) can be converted into a target data cube with three dimensions representing functions of range, velocity, and AoA (as shown in FIG. 8B). Because these operations (channel separation, range FFT, velocity FFT, and AoA FFT) are linear, they can be performed in any order. Furthermore, the FFT operations are independent (meaning, for example, that the range FFT for a given antenna and cycle may be independent from the range FFTs for other antennas and other cycles, and that the velocity FFT for a given range and antenna may be independent from the velocity FFTs for other ranges and antennas), thereby allowing the FFT processing to be parallelized (if desired).

[0069] Another desirable processing operation is separating signal energy from noise energy. A wide variety of suitable noise suppression or target detection techniques can be used. One technique (including many variations) is constant false alarm rate (CFAR) detection. CFAR detection may employ detection threshold adaptation based at least in part on measured energy values ​​within a sliding window near or surrounding the measurement being evaluated (sometimes referred to as the "cell under test"). CFAR techniques and their variations offer various trade-offs between performance and computational complexity by using different statistical approaches to derive the detection threshold from measurements within the sliding window. Note that CFAR detection is a nonlinear technique because measurements below the threshold can be zeroed or ignored, but its position in the processing sequence can nevertheless be modified, since zeroing out frequency coefficients generally cannot prevent a subsequent FFT from utilizing the associated phase / frequency information of an energy peak representing a target.

[0070] 10 presents a flow diagram of an exemplary data flow 1000 in a radar system, which may be performed by the transceiver chip 502 or may be split between the transceiver chip 502 and the ECU 210. In particular, the binarized received signal x k Once Θ is obtained, the controller 509 may optionally use phase shift adjustments applied in the transceiver chip 502, either the transmitting extender, and / or either the receiving extender to demultiplex the receive antenna signals and separate the contributions from each transmit antenna, thereby separating the channels corresponding to each transmit-receive antenna pair. (This channel separation may not be required if phase shifts are used for beam steering.) Additionally, the controller 509 may, for example, perform a range FFT 1002 for each channel as the signal is acquired and store the resulting frequency coefficients as range data in the frame buffer 1004. The frame buffer 1004 accumulates range data from multiple measurement cycles, so that the controller 509 may then perform a velocity FFT 1006 to generate target range and velocity data for each channel, as previously described.

[0071] The CFAR detector 1008 may operate on the target range and velocity data to remove noise energy below an adaptive threshold. Additionally, the CFAR detector 1008 may zero out values ​​below the threshold, leaving only values ​​at or above the threshold that represent the range and velocity of potential targets (radar energy reflectors). In some embodiments, the CFAR detection process may compress the amount of data by omitting at least some of the values ​​below the threshold and / or by employing more advanced data compression techniques to reduce buffer size and / or bus bandwidth requirements. Additionally, the controller 509 and / or ECU 210 may perform an AoA FFT 1010 to determine the relative direction associated with the potential target and may analyze any peaks in the amount of data to detect and track 1012 the target's relative position and velocity with respect to the vehicle.

[0072] FIG. 11 presents a flow chart illustrating an example of a method 1100 for radar detection according to some embodiments of the present disclosure, which may be performed by a MIMO radar system with an extender. In particular, the chirp generator 504 may generate a chirp signal having an interval in which the signal frequency rises linearly from a start frequency to an end frequency (Operation 1102). The chirp signal may be an up-chirp, a down-chirp, or even a triangular up-down chirp signal. Furthermore, the chirp signal may be split into multiple transmit signals. The transceiver chip 502 may then optionally apply adjustable phase shifts to the different transmit signals (Operation 1104), for example, to perform phase shifting, beamforming, orthogonal code modulation, and / or frequency shifting. Furthermore, the MIMO system may use a transmitting extender chip to split each of the transmit signals into multiple output signals (Operation 1106), which may be further phase shifted with different sequences of phase shift adjustments before being provided to the transmit antennas.

[0073] Next, the input signals from the receive antennas may optionally be phase shifted (Operation 1108) to perform phase shifting, beam steering, orthogonal coding, and / or frequency shifting, and the phase-shifted signals may be combined to form a receive signal for binarization. Furthermore, controller 509 may optionally separate signals from each transmit-receive antenna pair using the phase-shift sequences (Operation 1110). Additionally, controller 509 and / or ECU 210 may transform the signals (Operation 1112) to extract energy peaks indicative of targets, which may then be used to detect and track targets relative to the vehicle (Operation 1114). ECU 210 may evaluate whether the target requires action, such as a driver warning or automatic braking and autopilot to avoid a collision (Operation 1116), and may act accordingly if necessary.

[0074] In some embodiments of method 1100, there may be additional or fewer operations. Furthermore, the order of the operations may be changed and / or two or more operations may be combined into a single operation. Although the operations in method 1100 are described in a sequential manner for purposes of explanation, at least some of these operations may be implemented in a parallel or pipelined manner. Alternatively, at least some of these operations may be performed asynchronously.

[0075] It should be noted that combining input signals from multiple receive antennas using a receive extender may enable the transceiver to support additional receive antennas. Furthermore, splitting the transmit signal inversely using a transmit extender may enable the transceiver to support additional transmit antennas. Furthermore, the phase modulator may enable the transceiver to distinguish the contributions of individual transmit and receive antennas. In some embodiments, the phase modulator may be implemented as a binary phase shift keying (BPSK) modulator, a quadrature phase shift keying (QPSK) modulator, and / or a higher order phase shift keying modulator.

[0076] As previously described, MIMO radar employs multiple transmit and receive radio channels to enhance its capabilities. For example, increasing the number of channels can increase radar range and angular resolution. However, radar RF front-end chips typically have a finite capacity to host channels within the same die due to tradeoffs such as RF interconnect loss (toward the antenna) and die area constraints, complexity, and cost. These issues can be addressed by connecting multiple chips in a cascaded configuration (e.g., star topology), but often require synchronization of signals (such as LO, clock, and control signals).

[0077] FIG. 12 presents a block diagram illustrating cascaded chips. In particular, a single radar chip (or transceiver chip) with four receivers and three transmitters is used as a master with two slave radar chips in a cascaded configuration with 12 receivers and 9 transmitters. Note that the master and slave chips in FIG. 12 are identical. Furthermore, the master and slave chips in FIG. 12 are synchronized and coordinated, which increases overhead and adds redundant or unnecessary components.

[0078] In contrast, in the disclosed circuit technology, an extender chip can be used to extend the number of transmit and receive channels available to a single radar chip. This is shown in FIG. 13, which presents a block diagram illustrating an example of a radar chip (or transceiver chip) and an extender chip. The configuration in FIG. 13 increases the number of antennas (e.g., patch antennas) on the receiving side and increases the number of physical channels on the transmitting side. Note that this configuration is equivalent to a radar chip with 16 receivers and 9 transmitters. Furthermore, instead of cascading radar chips using LO synchronization (which may involve tens of gigahertz communication over a printed circuit board), only the digital control signals can be synchronized (which may involve hundreds of megahertz communication over a printed circuit board). As a result, the extender in the disclosed circuit technology is smaller, less expensive, and easier to integrate into a MIMO radar system.

[0079] In some embodiments, losses on the RF traces from the chip to the antenna array (which may be unavoidable in the embodiments shown in FIGS. 12-13) may be compensated for by amplifiers operating within the extender chip. Additionally, signal processing to separate channels may use MIMO for transmit and previously described MIMO techniques for receive. Furthermore, phase coding may enable beam steering, simultaneous channel operation (such as simultaneous receive) and / or interference mitigation (as opposed to on / off switching, which may require time division multiplexing).

[0080] Note that the extender chip may not be a perfect replica of the radar chip. Instead, the extender chip may be simpler than the radar chip. For example, a given extender may have a smaller area, include fewer components, and use fewer control signals. Furthermore, the extender chip may increase the number of channels carrying "independent" information (as opposed to increasing the number of antennas per channel, which may only result in increased channel gain).

[0081] While FIG. 13 illustrates an extender chip including a multiplexer, in other embodiments, at least the multiplexer from the transmit extender chip may be mounted on the radar chip. However, in some embodiments, the demultiplexer from the receive extender chip may be mounted on the radar chip. Furthermore, while FIG. 13 illustrates separate transmit extender chips and receive extender chips, in some embodiments, the transmit extender chip and receive extender chip may be included in a single extender chip. As a result, in some embodiments, there may be fewer combined transmit / receive extender chips instead of the seven chips shown in FIG. 13. Note that the multiplexing in the transmit extender chip and / or the demultiplexing in the receive extender chip may be performed coherently. Furthermore, note that the receive extender chip may not perform frequency shifting. Instead, frequency shifting or mixing may be performed by the radar chip.

[0082] In some embodiments, these circuit techniques provide a transmit channel extender chip (sometimes referred to as a "transmit extender chip"). In particular, the transmit channel extender chip may include two signal domains: an RF path and a digital path. The RF path may include a 1:N power splitter, N phase shifters, and / or N power amplifiers. Furthermore, the digital path may include an SPI data interface, an SRAM for storing phase profiles, and / or a controller.

[0083] 8, when connecting the transmit channel extender chip to the radar chip, RF_IN may be coupled to a power amplifier output (e.g., Tx0) of the radar chip. Additionally, each RF_OUT of the transmit channel extender chip may be coupled to an antenna element.

[0084] During operation of the transmit channel extender chip, upon power-up, the user can load the initial phase settings, power amplifier bias, and channel on / off status via the SPI data interface. Additionally, a table of phase profiles can be loaded into SRAM. Then, during radar operation, for each chirp, the transmit channel extender chip can point to a subsequent row in the lookup table, and each extender channel can receive a different phase setting to separate each transmit signal. Note that the power amplifier gain can be selected to compensate for RF trace losses on the printed circuit board containing the radar chip and one or more transmit channel extender chips, as well as losses associated with the one or more transmit channel extender chips. Figure 14 presents a block diagram illustrating an example of a radar chip and a transmit channel extender chip.

[0085] In some embodiments, these circuit techniques provide a receive channel extender chip (sometimes referred to as a "receive extender chip"). In particular, the receive channel extender chip may include two signal domains: an RF path and a digital path. The RF path may include N phase shifters, a 1:N power combiner, and / or a low-noise amplifier. Furthermore, the digital path may include an SPI data interface, an SRAM for storing phase profiles, and / or a controller.

[0086] 7, when connecting the receive channel extender chip to the radar chip, each RF_in may be coupled to an antenna element, and each RF_OUT of the receive channel extender chip may be coupled to an RF input of the radar chip.

[0087] During operation of the receive channel extender chip, upon power-up, the user can load the initial phase settings, low-noise amplifier bias, and channel on / off status via the SPI data interface. Additionally, a table of phase profiles can be loaded into SRAM. Then, during radar operation, for each chirp, the receive channel extender chip can point to a subsequent row in the lookup table, and each extender channel can receive a different phase setting to separate each received signal. Note that the low-noise amplifier gain can be selected to compensate for RF trace losses on the printed circuit board containing the radar chip and one or more receive channel extender chips, as well as losses associated with the one or more receive channel extender chips. Figure 15 presents a block diagram illustrating an example of a radar chip and receive channel extender chip.

[0088] Furthermore, note that combining the received signals within the receive extender chip may occur after analog phase shifting, as shown in Figure 7. However, in some embodiments, this may be implemented in a digital signal processor after analog-to-digital conversion within the radar chip. In these embodiments, different phase encoding (e.g., allowing received signals for different channels to be separated) may be used in the receive extender chip. This encoding may occur after input to the receive extender and before analog-to-digital conversion.

[0089] As previously described, safety components may be included in the extender chip when used in automotive applications. For example, as shown in FIG. 8, a given transmit channel extender chip may include N power detectors (PDs) 818 at the power amplifier outputs and / or N−1 phase detectors (Φ) 816 between adjacent power amplifiers. Additionally, as shown in FIG. 7, a given receive channel extender chip may include an RF inject port and N couplers at the input ports. In some embodiments, a given receive channel extender chip may include a voltage monitor 714 for the power supply, and / or a given transmit channel extender chip may include a voltage monitor 814 for the power supply.

[0090] In some embodiments, the transmit channel extender chip and / or the receive channel extender chip may include fewer or additional components, the location of one or more components may be changed, two or more components may be combined into a single component, and / or a single component may be split into two or more components.

[0091] The disclosed circuit techniques can increase the size scalability of RF radar chips while keeping costs low. Furthermore, these circuit techniques can improve performance. For example, positioning the gain stage close to the antenna arrangement can compensate for losses in printed circuit board traces, which can increase the signal-to-noise ratio. Furthermore, in some embodiments, extender chips can be used in a cascaded configuration to further enhance channel extension. Note that the receive channel extender chip and / or the transmit channel extender chip can be implemented in CMOS technology for cost-effectiveness. In some embodiments, the extender chip can be compatible with existing radar chips, including radar chips from multiple different vendors or manufacturers.

[0092] The disclosed integrated circuits and circuit techniques can be (or can be included in) any electronic device or system. For example, the electronic device can include a mobile phone or smartphone, a tablet computer, a laptop computer, a notebook computer, a personal or desktop computer, a netbook computer, a media player device, an e-book device, a MiFi® device, a smart watch, a wearable computing device, a portable computing device, a consumer electronic device, an access point, a router, a switch, communications equipment, test equipment, a vehicle, a watercraft, an aircraft, an automobile, a truck, a bus, a motorcycle, manufacturing equipment, agricultural equipment, construction equipment, or another type of electronic device.

[0093] Although particular components are used to describe embodiments of an integrated circuit and / or an integrated circuit containing an integrated circuit, in alternative embodiments, different components and / or subsystems may be present within the integrated circuit and / or the integrated circuit containing an integrated circuit. Thus, embodiments of an integrated circuit and / or an integrated circuit containing an integrated circuit may include fewer components, additional components, or different components, two or more components may be combined into a single component, a single component may be separated into two or more components, one or more positions of one or more components may be changed, and / or there may be different types of components.

[0094] Furthermore, the circuits and components in embodiments of integrated circuits and / or integrated circuits comprising integrated circuits may be implemented using any combination of analog and / or digital circuits, including bipolar, PMOS, and / or NMOS gates or transistors. Furthermore, signals in these embodiments may include digital signals having more or less discrete values ​​and / or analog signals having continuous values. Additionally, components and circuits may be single-ended or differential, and power supplies may be unipolar or bipolar. It should be noted that electrical couplings or connections in the previously described embodiments may be direct or indirect. In the previously described embodiments, a single line corresponding to a route may refer to one or more single lines or routes.

[0095] As previously mentioned, at least an integrated circuit may implement some or all of the functionality of the circuit technology. The integrated circuit may include hardware and / or software mechanisms used to implement the functionality associated with the circuit technology. However, in other embodiments, the disclosed circuit technology may be implemented, at least in part, using discrete components.

[0096] In some embodiments, the output of a process for designing an integrated circuit, or a portion of an integrated circuit, including one or more of the circuits described herein may be a computer-readable medium, such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing a circuit that may be physically instantiated in the integrated circuit or as part of the integrated circuit. Although various formats may be used for such encoding, these data structures are commonly described in Caltech Intermediate Format (CIF), Calma GDS II Stream Format (GDSII), Electronic Design Interchange Format (EDIF), Open Access (OA), or Open Artwork System Interchange Standard (OASIS). One skilled in the art of integrated circuit design can develop such a data structure from a wiring diagram and corresponding description of the type detailed above and encode the data structure on a computer-readable medium. One skilled in the art of integrated circuit fabrication can use such encoded data to fabricate an integrated circuit including one or more of the circuits described herein.

[0097] Although some of the operations in the previously described embodiments have been implemented in hardware or software, in general, the operations in the previously described embodiments may be implemented in a wide variety of configurations and architectures. Thus, some or all of the operations in the previously described embodiments may be performed in hardware, software, or both. For example, at least some of the operations in the circuitry may be implemented using program instructions executed by a processor or in firmware within an integrated circuit.

[0098] Furthermore, although example values ​​are provided in the foregoing description, other embodiments may use different values, and as a result, the values ​​provided are not intended to be limiting.

[0099] In the preceding description, we refer to "some embodiments." Note that "some embodiments" describes a subset of all possible embodiments, but does not always specify the same subset of embodiments.

[0100] The preceding description is intended to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Moreover, the foregoing descriptions of embodiments of the present disclosure have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Accordingly, many modifications and variations will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit or scope of the present disclosure. Additionally, the description of the embodiments set forth above is not intended to limit the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. [Explanation of symbols]

[0101] 110 vehicles 112 Antenna 114 Antenna 116 Antenna 118 Antenna 120 Antenna 122 Antenna 205 Radar Array Controller 210 Electronic Control Unit (ECU) 212 Sensors 214 Radar Array Controller 216 Turn signal actuator 218 Steering Actuator 220 Braking Actuator 222 Throttle Actuator 224 Interactive User Interface 310 Radar System 312 Transmitting Antenna 314 Reflector or Target 316 Transmitted Signal 318 Received Signal 320 receiving antenna 404 Chirp Generator 410 Radar Transceiver Circuit 412 Carrier Signal (Chirp) Generator 414 Phase shifter 416 Amplifier 418 Low Noise Amplifier (LNA) 420 Mixer 422 Broadband (BB) filter 424 ADC 426 processor 502 transceiver chip 506 Power Splitter 507 Down Conversion Mixer 508 Phase Shifter 509 Controller 512 Low-pass filter 514 Gain Control Amplifier 516 ADC 602 Input or Receiver Extender Chip 602A to 602D Receiver Extender Chips 604A to 604D receiving antennas 606 Output or Transmitting Extender Chip 606A to 606C Transmitting Extender Chips 610 Digital control signal line 702 Phase shifter 704 Power Combiner 706 Low Noise Amplifier 708 On-Chip Memory 712 SPI bus 714 Power Supply Voltage Monitor 804 Controllable Phase Shifter 806 Power Amplifier 808 On-Chip Memory 810 On-chip Controller 812 SPI bus 814 Power Supply Voltage Monitor 816 Phase difference detector 816 Phase detector (ΦD) 818 Power Detector (PD) 1002 Range FFT 1004 Frame Buffer 1006 Velocity FFT 1008 CFAR detector 1010 AoA FFT 1102 Operation 1104 Operation 1106 operation 1108 operation 1110 operation 1112 operation 1114 operation 1116 operation

Claims

1. 1. An integrated circuit comprising: a receiving extender; Transmit Extender and Equipped with The receiving extender N receive contacts configured to couple to N receive antennas and to receive N receive signals associated with the N receive antennas, where N is a non-zero integer; N phase adjustment circuits coupled to the N receiving contacts and configured to adjust the phases of the N received signals; an N:1 demultiplexer coupled to the N phase adjustment circuits and configured to combine the N received signals into an output signal; an output contact coupled to the N:1 demultiplexer and configured to provide the output signal to a second integrated circuit; Equipped with The transmitting extender an input contact configured to receive a transmit signal associated with the second integrated circuit, the second integrated circuit configured to perform a phase shift of the output signal, the transmit signal, or both based at least in part on an oscillator signal; a 1:M multiplexer coupled to the input contacts and configured to separate the transmit signal into M transmit signals, where M is a non-zero integer; M phase adjustment circuits coupled to the 1:M multiplexer and configured to adjust the phases of the M transmit signals; M transmit contacts coupled to the M phase adjustment circuits and coupled to M transmit antennas and configured to provide the M transmit signals to the M transmit antennas, wherein control signals for the N phase adjustment circuits, the M phase adjustment circuits, or both are synchronized between the integrated circuit and the second integrated circuit, and the oscillator signal is not synchronized between the integrated circuit and the second integrated circuit; 1. An integrated circuit comprising:

2. The integrated circuit of claim 1 , wherein the N:1 demultiplexer is configured to coherently combine the N received signals.

3. The integrated circuit of claim 1 , wherein the 1:M multiplexer is configured to coherently separate the M transmit signals.

4. The integrated circuit of claim 1 , wherein N and M are different.

5. The integrated circuit of claim 1 , wherein the N phase adjustment circuits are configured to apply different phase adjustments to the N received signals.

6. The integrated circuit of claim 1 , wherein the M phase adjustment circuits are configured to apply different phase adjustments to the M transmit signals.

7. The integrated circuit of claim 1 , wherein the configuration of the integrated circuit and the second integrated circuit is different from a cascaded configuration.

8. The integrated circuit of claim 1 , wherein the integrated circuit is different from the second integrated circuit.

9. The integrated circuit of claim 1 , wherein the second integrated circuit comprises a transceiver chip.

10. 1. A system comprising:

1. An integrated circuit comprising: a receiving extender; Transmit Extender and Equipped with The receiving extender N receive contacts configured to couple to N receive antennas and to receive N receive signals associated with the N receive antennas, where N is a non-zero integer; N phase adjustment circuits coupled to the N receiving contacts and configured to adjust the phases of the N received signals; an N:1 demultiplexer coupled to the N phase adjustment circuits and configured to combine the N received signals into an output signal; an output contact coupled to the N:1 demultiplexer and configured to provide the output signal to a second integrated circuit; Equipped with The transmitting extender an input contact configured to receive a transmission signal associated with the second integrated circuit; a 1:M multiplexer coupled to the input contacts and configured to separate the transmit signal into M transmit signals, where M is a non-zero integer; M phase adjustment circuits coupled to the 1:M multiplexer and configured to adjust the phases of the M transmit signals; M transmit contacts coupled to the M phase adjustment circuits and coupled to M transmit antennas, the M transmit signals being configured to provide the M transmit antennas; an integrated circuit comprising: a second integrated circuit coupled to the integrated circuit, the second integrated circuit configured to perform a phase shift of the output signal, the transmit signal, or both, based at least in part on an oscillator signal; Equipped with a control signal for the N phase adjustment circuits, the M phase adjustment circuits, or both, being synchronized between the integrated circuit and the second integrated circuit, and the oscillator signal not being synchronized between the integrated circuit and the second integrated circuit.

11. The system of claim 10 , wherein the N:1 demultiplexer is configured to coherently combine the N received signals.

12. The system of claim 10 , wherein the 1:M multiplexer is configured to coherently separate the M transmit signals.

13. The system of claim 10 , wherein N and M are different.

14. The system of claim 10 , wherein the N phase adjustment circuits are configured to apply different phase adjustments to the N received signals.

15. The system of claim 10 , wherein the M phase adjustment circuits are configured to apply different phase adjustments to the M transmit signals.

16. The system of claim 10 , wherein the configuration of the integrated circuit and the second integrated circuit is different from a cascaded configuration.

17. The system of claim 10 , wherein the integrated circuit is different from the second integrated circuit.

18. The system of claim 10 , wherein the second integrated circuit includes a transceiver chip.

19. 1. A method for enhancing a second integrated circuit, comprising: The integrated circuit receiver extender receiving N received signals from N receive antennas, where N is a non-zero integer; adjusting the phases of the N received signals using N phase adjustment circuits; combining the N received signals into one output signal using an N:1 demultiplexer; providing the output signal to the second integrated circuit; or A transmit extender in the integrated circuit receiving a transmit signal associated with the second integrated circuit, the second integrated circuit performing a phase shift of the output signal, the transmit signal, or both based at least in part on an oscillator signal; Separating the transmit signal into M transmit signals using a 1:M multiplexer, where M is a non-zero integer; adjusting the phases of the M transmit signals using M phase adjustment circuits; providing the M transmit signals to M transmit antennas; synchronizing control signals for the N phase adjustment circuits, the M phase adjustment circuits, or both between the integrated circuit and the second integrated circuit; not synchronizing the oscillator signal between the integrated circuit and the second integrated circuit. A method comprising:

20. 20. The method of claim 19, wherein the step of combining the N received signals or the step of separating the M transmitted signals is performed coherently.

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