Hierarchical store queue

Abstract

A method, system, and apparatus, including a computer program encoded on a computer storage medium, on a processor using a hierarchical store queue. In one aspect, the system includes a processor configured to receive a load instruction having an address corresponding to an entry in the hierarchical store queue. The processor performs a store-to-load forwarding process for the load instruction, including performing a hierarchical search to find the entry in the hierarchical store queue, where performing the hierarchical search includes searching for the entry in a first partition of the hierarchical store queue before searching a second partition of the hierarchical store queue. The processor reads the value of the entry from the hierarchical store queue for the load instruction.

Description

[Technical Field]

[0001] This specification relates to techniques for performing memory operations using hierarchical store queues. [Background technology]

[0002] In modern computing, loads from and stores to memory are performance-critical memory operations in a processor. A store queue in a Load Store Unit (LSU) within a processor tracks in-flight store entries within a processing window to ensure the correctness of data written to memory by a store instruction in the presence of out-of-order (OOO) execution. The store queue in the LSU can ensure the correctness of data when a store instruction requires data to be read from memory. A conventional technique for optimizing for reading data from memory is to perform a store-to-load forwarding (STLF) process. STLF ensures that data is forwarded from a store instruction within the window to a load instruction within the processor, rather than writing data to memory with a store instruction and then reading the same data back with a load instruction.

[0003] As the processing window size increases, the processor can increase the size of the store queue to accommodate more entries in order to track outstanding store entries. However, a larger store queue size can increase the latency of executing an STLF because the processor must read more store queue entries. On the other hand, a smaller store queue allows for faster performance of the STLF, but a smaller store queue can incur a performance loss due to more blocking of store instructions when the store queue is full. Summary of the Invention

[0004] This specification describes a system for executing memory operations using a hierarchical store queue with multiple partitions, which can significantly improve the performance of STLFs for large processor windows. Using a hierarchical store queue, the system can speed up the search for a store instruction by first searching the first partition of the store queue, where the store instruction is more likely to be found. If the store instruction is not in the first partition, the system can search other partitions of the store queue. The hierarchical structuring method disclosed herein can achieve increased efficiency in processors by improving the performance of the STLF.

[0005] Particular embodiments of the subject matter described herein can be implemented to realize one or more of the following advantages.

[0006] The described methods and systems improve the performance of store queues included in processors, for example, store queues having a large number of instructions associated with large processing window sizes. For example, the described methods and systems enable more efficient execution of STLFs by dividing the store queue into two partitions. The system executes the STLFs at a relatively faster rate in the first partition than in the second partition. By executing the STLFs more quickly in the first partition, the system improves the overall efficiency of the store queue by discovering store instructions at a faster rate and reduces latency in writing data to memory.

[0007] Additionally, if the system searches and finds the data to be transferred in the first partition, the system can save power by refraining from searching for the data in the second partition.

[0008] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram of an exemplary system. [Figure 2] 1 is an exemplary diagram of a logically partitioned hierarchical store queue structure. [Figure 3] 1 is an exemplary diagram of a physically partitioned hierarchical store queue structure. [Figure 4] 1 is a flow diagram of an exemplary process for executing memory operations on a processor using a hierarchical store queue. DETAILED DESCRIPTION OF THE INVENTION

[0010] Like reference numbers and designations in the various drawings refer to like elements.

[0011] 1 illustrates an example of an exemplary system 100. System 100 is an example of a system in which the systems, components, and techniques described below may be implemented.

[0012] System 100 includes a processor 102 coupled to a main memory 118, such as a cache, a random-access memory (RAM), or a read-only memory (ROM). Processor 102 can execute STLF processes using a load store unit (LSU), as described above. Processor 102 includes a load store unit (LSU) 106 and main execution logic 104.

[0013] LSU 106 communicates with main execution logic 104 to send and receive data. For example, communications 120 between LSU 106 and main execution logic 104 may include store instructions, load instructions, stored values, etc. Processor 102 communicates with main memory 118 to send and receive data. For example, communications 120 between processor 102 and main memory 118 may include memory addresses, stored values, etc.

[0014] The LSU 106 includes a load reservation station 108 and a store queue 110 .

[0015] The store queue 110 may include a content-addressable memory (CAM) structure that holds in-flight store instructions capable of supporting concurrent retrieval. The store queue 110 is associated with at least one tail pointer that points to the entry most recently added to the store queue 110 by the processor 102. The processor 102 obtains the most recently added entry from the load reservation station 108. Additionally, the store queue 110 is associated with at least one head pointer that points to the oldest entry in the store queue 110 (e.g., the entry most recently added by the processor). Conventionally, the processor 102 retires entries (e.g., retired stores 114) from the store queue 110 in a first-in-first-out (FIFO) manner. The processor 102 may retire entries (e.g., the oldest entry) at the head pointer. In some examples, the processor 102 retires entries to a store-gather buffer, as described in further detail with reference to FIG. 3.

[0016] Regardless of the implementation, a load reservation station 108 in an LSU 106 can receive a communication 116 from the main execution logic to extract or read data. The load reservation station 108 sends a load instruction 112 for the data to a store queue 110. The load instruction 112 includes an address corresponding to an entry in the store queue 110 associated with the data.

[0017] In some implementations, processor 102 may use store queue 110 to execute an STLF for one or more entries of load instruction 112. Store queue 110 tracks pending store instructions within a processing window. When a subsequent load instruction is executed, processor 102 may check the pending store instructions in store queue 110 to determine whether the data to be loaded is present in store queue 110. If the data is present in the pending store instruction, processor 102 may execute the STLF by retrieving the data from the pending store instruction in store queue 110 rather than from main memory 118. Processor 102 may transfer data from the pending store instruction to load instruction 112 instead of writing the data to main memory 118 and reading the same data back with load instruction 112, thereby improving the efficiency of store queue 110.

[0018] In this example, processor 102 executes the STLF process for load instruction 112 by performing a hierarchical search of store queue 110 (e.g., a hierarchical store queue). In this case, hierarchical store queue 110 is divided into a first partition and a second partition. Processor 102 first searches the first partition for entries included in load instruction 112 before searching the second partition of hierarchical store queue 110. The first partition may be smaller than the second partition, and the first partition contains the most recently stored entries that are likely to be required by load instruction 112. Thus, processor 102 may execute the STLF more efficiently, thereby reducing the latency of executing the STLF across the hierarchical store queue.

[0019] In some implementations, store queue 110 is logically divided into two partitions using head and tail pointers for store queue 110, along with a third pointer that points to the first entry to retrieve in the first partition, as described in more detail with reference to FIG.

[0020] Alternatively, in other embodiments, the hierarchical store queue 110 is physically divided into two partitions, each partition being a separate store queue device, each associated with a head pointer and a tail pointer associated with storing and retiring entries in the hierarchical store queue 110, as described in more detail with reference to FIG.

[0021] 2 is an exemplary diagram of a logically partitioned hierarchical store queue structure. For convenience, diagram 200 is described as being executed by a processor. For example, a processor, such as processor 102 of FIG. 1, suitably configured in accordance with this specification, may execute diagram 200.

[0022] A conventional store queue has been implemented as a monolithic circular queue associated with a store queue tail pointer and a store queue head pointer. The offset between the store queue tail pointer 208 and the store queue head pointer 204 indicates the region of the store queue 202 that has active entries. The location of the store queue head pointer 204 points to the oldest entry in the processor, and the location of the store queue tail pointer 208 points to the most recently added entry in the processor (e.g., the newest entry).

[0023] In this example, store queue 202 is a monolithic circular queue that is logically divided into a first partition and a second partition by a third pointer (e.g., store queue STLF pointer 206). The first partition spans the range from store queue tail pointer 208 to store queue STLF pointer 206, and the second partition spans the range from store queue STLF pointer 206 to store queue head pointer 204. Store queue STLF pointer 206 points to the first entry to search for in the first partition when the processor executes an STLF. The first partition is smaller than the second partition.

[0024] The store queue STLF pointer 206 is positioned at an offset from the store queue tail pointer 208, where the offset is the STLF window 210. The STLF window 210 can be configured globally for the processor, in which case the offset between the STLF pointer 206 and the store queue tail pointer 208 is a fixed value for the processor, and the STLF window 210 applies to each load instruction and each active entry for executing the STLF. Alternatively, the STLF window can be local to each load instruction, in which case the processor can set a relatively small offset, resulting in a smaller STLF window 210 and increasing the efficiency of executing STLFs in the first partition.

[0025] The processor executes an STLF by searching for an active entry in the STLF window 210, starting from an entry in the store queue STLF pointer 206. The first partition is smaller than the second partition, which improves the efficiency of executing an STLF across the first partition and the store queue 202. Thus, the first partition supports relatively faster STLF performance compared to the second partition (e.g., the second partition supports a slower STLF). The processor performs a hierarchical search by determining whether the entry from the load instruction is located in the first partition. If not, and only then, does the processor search the second partition instead, starting from the location indicated by the head pointer.

[0026] For example, store queue 202 may have a store queue size of 128 entries and a maximum STLF window size of 64. If store queue STLF pointer 206 is at entry at index 100 (e.g., the 100th entry in the store queue), the processor determines that the youngest entry (e.g., the most recently added entry) is at entry at index 100. The processor determines that the current STLF window 210 spans a particular number of entries (e.g., 36 entries) by calculating the difference between the number of entries and the maximum STLF window size (e.g., 100-64). Because the first partition contains a relatively smaller number of entries (e.g., 36 entries) than the second partition (e.g., 64 entries), the processor may execute the STLF more efficiently in the first partition.

[0027] This technique retires stored entries in a first-in, first-out (FIFO) manner. A processor may receive a store instruction that includes a new entry, and the processor stores the new entry in the store queue 202. Thus, when the processor stores the new entry, the store queue tail pointer 208 shifts within the circular queue to point to the most recent entry. As the store queue tail pointer 208 shifts, the store queue STLF pointer 206 also shifts to maintain the maximum STLF window size. The store queue head pointer 204 also shifts within the circular queue so that the STLF window 210 contains active entries (e.g., not retired entries).

[0028] To maintain the maximum STLF window size, the processor retires entries from the store queue 202 to the store gather buffer. The processor first retires the oldest entry from the store queue 202, which is pointed to by the store queue head pointer 204. Once the processor retires the oldest entry from the store queue 202, the processor can write a new entry from a store instruction in the hierarchical store queue.

[0029] 3 is an exemplary diagram of a physically partitioned hierarchical store queue structure. For convenience, diagram 300 is described as being executed by a processor. For example, a processor, such as processor 102 of FIG. 1, suitably configured in accordance with this specification, may execute diagram 300.

[0030] The load store unit (LSU) 302 includes a load reservation station 304 , a store queue 306 , and a store gather buffer 322 .

[0031] In this embodiment, the store queue 202 is physically divided into separate hierarchical store queue devices, a first store queue 308 and a second store queue 310. The store queue devices are unequal in size, with the first store queue 308 being smaller than the second store queue 310. The first store queue 308 includes a first store queue tail pointer 314 and a first store queue head pointer 316, and the second store queue 310 includes a second store queue tail pointer 318 and a second store queue head pointer 320. The first store queue tail pointer 314 and the second store queue tail pointer 318 each point to the newest entry in each partition. The first store queue head pointer 316 and the second store queue head pointer 320 each point to the oldest entry in each partition.

[0032] In this case, the processor receives a load instruction that includes an entry. The processor performs a hierarchical search for the data associated with the entry by searching the first store queue 308. If the processor finds the entry in the first store queue 308, the processor can execute the STLF relatively quickly due to the first store queue 308's smaller size and relatively small amount of entries. If the processor determines that the value is not in the first store queue 308, the processor searches the second store queue 310. The processor executes the STLF one cycle later in the second store queue 310 than in the first store queue 308 to reduce the STLF timing pressure associated with the larger size of the second store queue 310 and the larger amount of entries in the second store queue 310.

[0033] In this embodiment, the processor references pointers in the first store queue 308 and the second store queue 310 to retire entries based on their location. The processor receives a store instruction and stores a value 326 in the store queue 306. The store queue 306 receives the value 326 from the load reservation station 304. The processor determines whether to retire an older entry in the store queue 306 by determining whether the first store queue 308 is full (e.g., contains a limited amount of entries for the first store queue 308).

[0034] If the first store queue 308 is not full, the processor writes a value 326 to the store queue 306. If the first store queue 308 is full, the processor drains (e.g., moves) the entry 312 to the second store queue 310. The entry 312 is the oldest entry in the first store queue 308, which is indicated by the first store queue head pointer 316. In some cases, the processor drains the entry 312 in the first store queue 308 when the processor commits the entry.

[0035] If the second store queue is full, the processor may move retired entries 324 from the second store queue 310 to the store gather buffer 322. In some cases, when the processor commits the retired entries 324, the processor drains the retired entries 324 in the second store queue 310.

[0036] The processor writes the value 326 to the first store queue 308 at the first store queue tail pointer 314. By writing the value 326 to the first store queue 308, the processor is more likely to use the most recently added entry to transfer the data, allowing the processor to execute the STLF more efficiently.

[0037] For example, store queue 306 may have a store queue size of 128 entries. First store queue 308 may contain 32 entries, and second store queue 310 may contain 96 entries. Because first store queue 308 contains a relatively smaller number of entries (e.g., 32 entries) than second store queue 310 (e.g., 96 entries), the processor may more efficiently execute STLFs in first store queue 308. Furthermore, first store queue 308 contains the youngest entries that are more likely to be used in an STLF, further improving the efficiency of store queue 306.

[0038] 4 is a flow diagram of an exemplary process for performing a back-end victimization process. For convenience, process 400 is described as being performed by a processor. For example, a processor, such as processor 102 of FIG. 1, may be suitably configured in accordance with this specification to perform process 400.

[0039] In some cases, the processor may receive a load instruction having an address corresponding to an entry in the hierarchical store queue (402). For example, referring to Figure 2, the processor receives a load instruction for an entry having an address in the store queue and a corresponding value located in an LSU. Referring to Figure 3, the processor receives a load instruction having an address and value corresponding to an entry located in a load reservation station of the LSU. In this case, the load reservation station sends the value to the store queue for the processor to execute the STLF.

[0040] The processor performs a hierarchical search for the load instruction to find an entry in the store queue (404). The processor searches the hierarchical store queue to determine whether the data requested by the load instruction is present in the store queue. The processor searches the first partition of the store queue before searching the second partition of the store queue.

[0041] In one example, referring to Figure 2, the store queue is logically divided into a first partition and a second partition. In another example, referring to Figure 3, the store is physically divided into two separate store queue devices, where the first store queue device is the first partition and the second store queue device is the second partition. In either case, the first partition is relatively smaller than the second partition, and the processor must search fewer entries in the first partition than in the second partition, allowing the processor to execute the STLF relatively faster in the first partition than in the second partition.

[0042] The processor reads the value of the entry from the hierarchical store queue for the load instruction (406). If the processor finds the entry in one of the partitions, the processor can execute the STLF by transferring the value of the entry from the first partition or the second partition of the hierarchical store queue to the pending load instruction; for example, the processor can transfer the data from the active entry in the store queue instead of writing the data out to main memory.

[0043] This specification uses the term "configured" in the context of systems and computer program components. When one or more computer systems are configured to perform a particular operation or action, it means that the system has installed thereon software, firmware, hardware, or a combination thereof that, when running, causes the system to perform the operation or action. When one or more computer programs are configured to perform a particular operation or action, it means that the one or more programs contain instructions that, when executed by a data processing device, cause the device to perform the operation or action.

[0044] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, such as the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can also be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a tangible, non-transitory storage medium for execution by or to control the operation of a data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random-access or serial-access memory device, or one or more combinations thereof. Alternatively, or in addition, the program instructions can be encoded into an artificially generated transmitted signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver apparatus for execution by a data processing apparatus.

[0045] The term "data processing apparatus" refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or multiple computers. An apparatus may be or further include special-purpose logic circuitry, such as an FPGA (Field Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit). An apparatus optionally includes, in addition to hardware, code that creates an execution environment for a computer program (e.g., code comprising processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof).

[0046] A computer program, which may be called or described as a program, software, software application, app, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted, declarative or procedural, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in part of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple cooperating files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to be executed on one computer or to be executed on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communications network.

[0047] The term "engine" is used broadly herein to refer to a software-based system, subsystem, or process that is programmed to perform one or more specific functions. Typically, an engine is implemented as one or more software modules or components and installed on one or more computers in one or more locations. In some cases, one or more computers are dedicated to a particular engine, and in other cases, multiple engines may be installed and run on the same computer or computers.

[0048] The processes and logic flows described herein may be implemented by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be implemented by special purpose logic circuitry, such as an FPGA or an ASIC, or a combination of special purpose logic circuitry and one or more programmed computers.

[0049] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from a read-only memory or a random-access memory, or both. The essential components of a computer are a central processing unit for executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory may be supplemented by, or incorporated in, special-purpose logic circuitry. Typically, a computer also includes, or is operatively coupled to receive data from, or transfer data to, one or more mass storage devices for storing data, such as, for example, magnetic, magneto-optical, or optical disks. However, a computer need not include such devices. Additionally, computers can be embedded in other devices, such as mobile phones, personal digital assistants (PDAs), mobile audio or video players, game consoles, Global Positioning System (GPS) receivers, or portable storage devices, such as Universal Serial Bus (USB) flash drives, to name just a few.

[0050] Computer-readable media suitable for storing computer program instructions and data include, by way of example, all types of non-volatile memory, media, and memory devices, such as semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0051] To provide for user interaction, embodiments of the subject matter described herein can be implemented in a computer having a display device, such as a CRT (Cathode Ray Tube) or LCD (Liquid Crystal Display) monitor, for displaying information to the user, and a keyboard and pointing device, such as a mouse or trackball, through which the user can provide input to the computer. Other types of devices can also be used to interact with the user. For example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input from the user can be received in any form, including acoustic, speech, or tactile input. Furthermore, a computer can interact with a user by sending documents to and receiving documents from a device used by the user, for example, by sending a web page to a web browser on the user's device in response to a request received from the web browser. A computer may also interact with a user by sending text messages or other forms of messages to a personal device (e.g., a smartphone running a messaging application) and then receiving a reply message from the user.

[0052] A data processing device for implementing machine learning models may also include dedicated hardware accelerator units, for example for handling the common and computationally intensive part of machine learning training or production, i.e., inference, workloads.

[0053] The machine learning model can be implemented and deployed using a machine learning framework, for example, the TensorFlow framework.

[0054] Embodiments of the subject matter described herein can be implemented in a computing system that includes back-end components such as, for example, a data server, or includes middleware components such as, for example, an application server, or includes front-end components such as a client computer having a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described herein, or includes any combination of one or more such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communications network. Examples of communications networks include a local area network (LAN) or a wide area network (WAN), e.g., the Internet.

[0055] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. In some embodiments, a server sends data (e.g., HTML pages) to a user device, for example, to display the data to and receive user input from a user interacting with the device acting as a client. Data generated at the user device (e.g., results of user interaction) can be received from the device by the server.

[0056] In addition to the above embodiments, the following embodiments are also innovative.

[0057] Embodiment 1 is a method executed in a processor using a hierarchical store queue, comprising:

[0058] receiving a load instruction having an address corresponding to an entry in the hierarchical store queue;

[0059] performing a hierarchical search to locate the entry in the hierarchical store queue, wherein performing the hierarchical search includes searching a first partition of the hierarchical store queue for the entry before searching a second partition of the hierarchical store queue;

[0060] The method further includes reading the value of the entry from the hierarchical store queue of the load instruction.

[0061] Embodiment 2 is the method of embodiment 1, wherein the first partition is smaller than the second partition.

[0062] A third embodiment is the method according to any one of the first and second embodiments, wherein performing the hierarchical search includes performing a store-to-load forwarding process for the load instruction.

[0063] Embodiment 4 is a method according to any one of embodiments 1 to 33, wherein the hierarchical store queue is a logically partitioned circular queue using a pointer indicating a first entry to search for in the first partition.

[0064] Embodiment 5 is a method of embodiment 4, wherein the pointer to the first entry in the first partition is positioned offset from a tail pointer representing the entry most recently added to the hierarchical store queue.

[0065] Embodiment 6 is the method of embodiment 5, wherein performing the hierarchical search comprises:

[0066] determining that the entry is not located in the first partition;

[0067] and in response, retrieving the second partition from a location indicated by a head pointer, the head pointer representing the oldest entry in the hierarchical store queue.

[0068] Embodiment 7 is the method of embodiment 6, wherein the first partition extends from the tail pointer to the pointer to the first entry, and the second partition extends from the pointer to the first entry to the head pointer.

[0069] Example 8 is the method of example 5, in which the offset is a store-to-load window of the store-to-load forwarding process.

[0070] Example 9 is the method of Example 8, wherein the size of the store-to-load window is global to the processor and local to the load instruction of the store-to-load forwarding process.

[0071] Example 10 is the method of example 6, further including receiving a store instruction to store a value in the hierarchical store queue; determining to retire an entry from the hierarchical store queue to a store gather buffer; and retiring the entry to the store gather buffer on a first-in, first-out basis, the entry being the oldest entry indicated by the head pointer, and the method further including writing the value from the store instruction to the hierarchical store queue.

[0072] An eleventh embodiment is the method of any one of the first to thirty-third embodiments, wherein the hierarchical store queue is physically partitioned using separate hierarchical store queue devices.

[0073] Example 12 is the method of example 11, wherein performing the hierarchical search includes determining that the entry is not located in the first partition, and in response, searching for a second device that implements the second partition.

[0074] Embodiment 13 is the method of embodiment 12, wherein the first partition extends from a first tail pointer to a first head pointer, the second partition extends from a second tail pointer to a second head pointer, the first tail pointer and the second tail pointer point to the newest entry in the respective partition, and the first head pointer and the second head pointer point to the oldest entry in the respective partition.

[0075]

[0033] Embodiment 14 is the method of embodiment 11, wherein performing the store-to-load forwarding process in the second partition is at least one cycle slower than performing the store-to-load forwarding process in the first partition.

[0076] Embodiment 15 is the method of embodiment 11, further including receiving a store instruction to store a value in the hierarchical store queue; determining whether to retire an entry in the hierarchical store queue to a store gather buffer by determining whether the first partition and the second partition are full; and writing the value of the store instruction to the first partition or the second partition based on determining whether the first partition and the second partition are full.

[0077] A sixteenth embodiment is a system including a processor having a hierarchical store queue, the processor being configured to execute the method according to any one of the first to fifteenth embodiments.

[0078] A seventeenth embodiment is one or more storage media storing instructions that, when executed by a data processing device, cause the data processing device to perform the method according to any one of the first to fifteenth embodiments.

[0079] While the specification contains many specific implementation details, these should not be construed as limiting the scope of any invention or the scope of patentable subject matter, but rather as descriptions of features that may be unique to particular embodiments of a particular invention. Certain features described herein as separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented in multiple embodiments, either separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0080] Similarly, while operations are illustrated in the figures and described in the claims in a particular order, this should not be understood as requiring that such operations be performed in the particular order or sequential order shown, or that all of the operations shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the program components and systems described may generally be integrated into a single software product or packaged into multiple software products.

[0081] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims may be performed in a different order and still produce desirable results. By way of example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. 1. A method implemented in a processor using a hierarchical store queue, comprising: receiving a load instruction having an address corresponding to an entry in the hierarchical store queue; performing a hierarchical search to locate the entry in the hierarchical store queue, wherein performing the hierarchical search includes searching a first partition of the hierarchical store queue for the entry before searching a second partition of the hierarchical store queue, the method further comprising: reading a value of the entry from the hierarchical store queue of the load instruction.

2. The method of claim 1 , wherein the first partition is smaller than the second partition.

3. The method of any one of claims 1 to 2, further comprising performing a store-to-load forwarding process on the load instruction.

4. 4. The method of claim 1, wherein the hierarchical store queue is a logically partitioned circular queue using a pointer to a first entry to search for in the first partition.

5. 5. The method of claim 4, wherein the pointer to the first entry in the first partition is located offset from a tail pointer representing the most recently added entry to the hierarchical store queue.

6. performing the hierarchical search determining that the entry is not located in the first partition; and in response, retrieving the second partition from a location indicated by a head pointer, the head pointer representing the oldest entry in the hierarchical store queue.

7. 7. The method of claim 6, wherein the first partition extends from the tail pointer to the pointer to the first entry, and the second partition extends from the pointer to the first entry to the head pointer.

8. 6. The method of claim 5, wherein the offset is a store-to-load window of the store-to-load forwarding process.

9. 9. The method of claim 8, wherein the size of the store-to-load window is global to the processor and local to the load instruction of the store-to-load forwarding process.

10. The method comprises: receiving a store instruction to store a value in the hierarchical store queue; determining to retire an entry from the hierarchical store queue to a store gather buffer; retiring the entry to the store gather buffer on a first-in, first-out basis, the entry being the oldest entry indicated by the head pointer, the method further comprising:

7. The method of claim 6, further comprising writing the value from the store instruction to the hierarchical store queue.

11. The method of any one of claims 1 to 3, wherein the hierarchical store queue is physically partitioned using separate hierarchical store queue devices.

12. performing the hierarchical search determining that the entry is not located in the first partition; In response thereto, searching for a second device that implements the second partition; and The method of claim 11 , comprising:

13. 13. The method of claim 12, wherein the first partition spans from a first tail pointer to a first head pointer, the second partition spans from a second tail pointer to a second head pointer, the first tail pointer and the second tail pointer point to the newest entry in the respective partition, and the first head pointer and the second head pointer point to the oldest entry in the respective partition.

14. 12. The method of claim 11, wherein performing the store-to-load forwarding process in the second partition is at least one cycle slower than performing the store-to-load forwarding process in the first partition.

15. receiving a store instruction to store a value in the hierarchical store queue; determining whether to retire an entry in the hierarchical store queue to a store gather buffer by determining whether the first partition and the second partition are full; writing the value of the store instruction to the first partition or the second partition based on determining whether the first partition and the second partition are full; The method of claim 11 further comprising:

16. A system including a processor having a hierarchical store queue, said processor configured to perform the method of any one of claims 1 to 15.

17. One or more storage media storing instructions that, when executed by a data processing apparatus, cause said data processing apparatus to carry out the method of any one of claims 1 to 15.

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