Display panel and its display control method, display device

Abstract

This application provides a display panel, a display control method therefor, and a display device belonging to the field of display technology. A plurality of first drive units (031) included in a first drive circuit (03) in the display panel can output gate drive signals based on ON signals provided from a coupled first ON line. A plurality of second drive units (041) included in a second drive circuit (04) can output gate drive signals based on ON signals provided from a coupled second ON line. A first gating unit (032) can control the conduction interruption between a corresponding first drive unit (031) and some pixels based on an enable signal provided from a coupled first enable line. A second gating unit (042) can control the conduction interruption between a corresponding second drive unit (041) and some other pixels based on an enable signal provided from a coupled second enable line. In this way, by flexibly setting the enable signal and ON signal, flexible refresh for pixels in different areas of the display area can be achieved, and the refresh rate for different areas can be made different, that is, section frequency conversion can be achieved, thereby reducing power consumption.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel, its display control method, and a display device.

Background Art

[0002] Low temperature polycrystalline oxide (LTPO) display products are attracting increasing attention in the market because they can achieve low-frequency display and save display power consumption.

[0003] In related technologies, an LTPO display product generally includes a substrate, a plurality of rows of pixels located on the substrate (each row further includes a plurality of columns of pixels), and a gate driver on array (GOA) circuit for driving the emission of the plurality of pixels. Here, the GOA circuit includes a plurality of cascaded GOA units, and the plurality of GOA units are correspondingly coupled one-to-one to the plurality of rows of pixels on the substrate via a plurality of gate lines, and are used to transmit a gate drive signal to the plurality of rows of pixels one row at a time so as to realize progressive scan refresh and light up the plurality of rows of pixels one row at a time.

[0004] However, due to the limitations in the connection and layout between the GOA circuit and the pixels, currently, only full-screen refresh (i.e., the refresh rates in different regions of the full screen are the same) can be performed, and split-screen refresh for different regions cannot be performed, the flexibility of refresh is poor, and the operating power consumption of the display product is large.

Summary of the Invention

[0005] A display panel, its display control method, and a display device are provided. The technical solutions are as follows.

[0006] According to one aspect, a display panel is provided, and the display panel A substrate having a display area and a peripheral area that at least partially encloses the display area, Multiple pixels arranged in an array in the aforementioned display area, The first drive circuit located in the peripheral region, The second drive circuit located in the aforementioned peripheral region, Includes, The first drive circuit includes a plurality of cascaded first drive units and a plurality of first gating units that correspond one-to-one with the plurality of first drive units, The second drive circuit includes a plurality of cascaded second drive units and a plurality of second gating units that correspond one-to-one with the plurality of second drive units, At least one first drive unit and at least one second drive unit are located on opposite sides of the pixels in the row direction of the substrate, each first gating unit and its corresponding first drive unit are located on the same side of the substrate, and each second gating unit and its corresponding second drive unit are located on the same side of the substrate. Each first drive unit is coupled to a subset of pixels in at least one row via a corresponding first gating unit, the first gating unit is further coupled to a first enable line and is used to control the conduction interruption between the first drive unit and the subset of pixels based on a first enable signal provided from the first enable line, and the plurality of first drive units are further coupled to a first on line and is used to output a first gate drive signal based on a first on signal provided from the first on line. Each second drive unit is coupled to some of the other pixels of the at least one row of pixels via a corresponding second gating unit, the second gating unit is further coupled to a second enable line and is used to control the conduction interruption between the second drive unit and the other some pixels based on a second enable signal provided from the second enable line, and the plurality of second drive units are further coupled to a second on line and is used to output a second gate drive signal based on a second on signal provided from the second on line.

[0007] As one option, the plurality of first drive units are all located on the first side of the two sides, and the plurality of second drive units are all located on the second side of the two sides.

[0008] As one option, some of the multiple first drive units are located on the first side of the two sides, and the remaining first drive units are located on the second side of the two sides. Some of the plurality of second drive units are located on the first side of the two sides, and the remaining second drive units are located on the second side of the two sides.

[0009] As one option, each first drive unit is coupled to a portion of the pixels in a row via a corresponding first gating unit. Of the plurality of first drive units, each first drive unit coupled to a pixel in an even row is located on the first side, and each first drive unit coupled to a pixel in an odd row is located on the second side.

[0010] As one option, each second drive unit is coupled to some of the other pixels in a row of pixels via a corresponding second gating unit. Of the plurality of second drive units, each second drive unit coupled to pixels in even rows is located on the first side, and each second drive unit coupled to pixels in odd rows is located on the second side.

[0011] As one option, the first drive units and second drive units located on the first side are arranged sequentially in the pixel row direction, one first drive unit followed by one second drive unit. Each first drive unit and each second drive unit located on the second side are arranged sequentially in the pixel row direction, in the order of one second drive unit followed by one first drive unit.

[0012] As one option, each first drive unit is coupled to a first drive line via a corresponding first gating unit, the first drive line is coupled to some of the pixels, each second drive unit is coupled to a second drive line via a corresponding second gating unit, the second drive line is coupled to some of the other pixels, and the plurality of first drive units are cascaded via the first drive line, and the plurality of second drive units are cascaded via the second drive line.

[0013] As one option, if the plurality of first drive units are all located on the first side of the two sides, and the plurality of second drive units are all located on the second side of the two sides, then the first drive line and the second drive line are independent of each other.

[0014] As one option, a case in which some of the plurality of first drive units are located on the first side of the two sides, the remaining first drive units other than the plurality of first drive units are located on the second side of the two sides, some of the plurality of second drive units are located on the first side of the two sides, and the remaining second drive units other than the plurality of second drive units are located on the second side of the two sides, In addition to being coupled to a pixel, the first drive line further penetrates the display area and cascades a first drive unit located on the first side and a first drive unit located on the second side. In addition to being coupled to the pixels, the second drive line further penetrates the display area and cascades the second drive unit located on the first side and the second drive unit located on the second side. Furthermore, the first drive line and the second drive line, which are joined to pixels in the same row, overlap within the display area.

[0015] As one option, the first drive line has a portion for coupling to a pixel and a portion for cascading to a first drive unit located in different layers, the second drive line has a portion for coupling to a pixel and a portion for cascading to a second drive unit located in different layers, and the portion where the first drive line and the second drive line overlap is located in different layers.

[0016] As one option, the pixel includes a gate metal layer, an insulating layer, and a source-drain metal layer located on one side of the substrate and sequentially stacked. Here, the first drive line has a portion for coupling to a pixel located in the same layer as the gate metal layer, a portion for cascading to a first drive unit located in the same layer as the source-drain metal layer, and the portion for coupling to a pixel and the portion for cascading to a first drive unit are through-connected via a via penetrating the insulating layer. The second drive line has a portion for coupling to a pixel located in the same layer as the gate metal layer, and a portion for cascading to a second drive unit located in the same layer as the source-drain metal layer. The portion for coupling to a pixel and the portion for cascading to a second drive unit are through-connected via vias penetrating the insulating layer.

[0017] As one option, the aforementioned substrate is A left display area and a right display area arranged in the row direction of pixels from the pixels in the first column to the pixels in the last column, and An upper display area and a lower display area arranged in the column direction of pixels from the pixels in the first row to the pixels in the last row, and including The left display area includes the part of the pixels, and the right display area includes the other part of the pixels, Both the upper display area and the lower display area each include at least one row of pixels.

[0018] As one option, the refresh rate of the upper display area is greater than or equal to the refresh rate of the lower display area.

[0019] As one option, the left display area and the right display area have the same area and the same number of pixels included, and / or the upper display area and the lower display area have the same area and the same number of pixels included.

[0020] As one option, each of the gating units located on the same side of the substrate among the plurality of first gating units and the plurality of second gating units shares the same enable line.

[0021] As one option, the first gating unit includes a first gating switch element, and the second gating unit includes a second gating switch element, The gate of the first gating switch element is coupled to the first enable line, the first pole of the first gating switch element is coupled to the corresponding first driving unit, and the second pole of the first gating switch element is coupled to the part of the pixels, The gate of the second gating switch element is coupled to the second enable line, the first pole of the second gating switch element is coupled to the corresponding second driving unit, and the second pole of the second gating switch element is coupled to the other part of the pixels.

[0022] As one option, each first driving unit is coupled to a part of pixels of at least one row that are close to the corresponding first gating unit through the corresponding first gating unit, and each second driving unit is coupled to another part of pixels of at least one row that are close to the corresponding second gating unit through the corresponding second gating unit. Each pixel among the part of pixels is adjacent to each other, and each pixel among the other part of pixels is adjacent to each other.

[0023] As one option, the display panel includes a low temperature poly-silicon oxide (LTPO) display panel.

[0024] According to another aspect, a display control method is provided and is used to control the display panel in the above aspect. The method includes: Determining the refresh needs of different regions in the display area of the substrate. The different regions include a left region and a right region arranged in the row direction of pixels, and / or an upper region and a lower region arranged in the column direction of pixels. The refresh needs are used to indicate whether a refresh is required and the refresh frequency. In response to a frame synchronization signal and based on the refresh needs, a first enable signal is transmitted to a first enable line coupled to the plurality of first gating units, and a second enable signal is transmitted to a second enable line coupled to the plurality of second gating units, wherein the first enable signal of a first potential is used to instruct the first gating unit to control the corresponding first drive unit to conduct with some of the coupled pixels, the first enable signal of a second potential is used to instruct the first gating unit to control the coupling between the corresponding first drive unit and some of the coupled pixels, the second enable signal of a first potential is used to instruct the second gating unit to control the corresponding second drive unit to conduct with some of the coupled pixels, and the second enable signal of a second potential is used to instruct the second gating unit to control the coupling between the corresponding second drive unit and some of the coupled pixels, In response to a frame synchronization signal, a first ON signal is transmitted to a first ON line coupled to the plurality of first drive units, and a second ON signal is transmitted to a second ON line coupled to the plurality of second drive units, wherein the first ON signal is used to instruct the plurality of first drive units to output a first gate drive signal, and the second ON signal is used to instruct the plurality of second drive units to output a second gate drive signal. Includes, Here, when the first gating unit controls the first drive unit to make electrical contact with some of the pixels to be coupled, the first drive unit transmits the first gate drive signal to some of the pixels. When the second gating unit controls the second drive unit to make electrical contact with some other pixels to be coupled, the second drive unit transmits the second gate drive signal to some other pixels.

[0025] In another embodiment, a display device is provided, the display device comprising a drive chip and the display panel in the above embodiment, The drive chip is coupled to a signal line to which the circuit in the display panel is coupled, and is used to provide a signal to the signal line. [Brief explanation of the drawing]

[0026] To more clearly explain the technical concept in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. The drawings in the following description are only a few embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained based on these drawings without any creative work.

[0027] [Figure 1] This is a schematic diagram of the structure of the display panel provided in the embodiment of the present application. [Figure 2] This is a schematic diagram of the structure of another display panel provided in the embodiments of the present application. [Figure 3] Based on Figure 1, this is a schematic diagram of the structure of another display panel provided in the embodiment of the present application. [Figure 4] Figure 2 is a schematic diagram of the structure of another display panel provided in the embodiment of the present application. [Figure 5] This is a schematic diagram of the pixel film layer structure provided in the embodiment of the present application. [Figure 6] Figure 4 is a schematic diagram of a partial structure of the display panel provided in the embodiment of the present application. [Figure 7] This is a schematic diagram of the display area division of the substrate provided in the embodiment of the present application. [Figure 8] This is a schematic diagram of the circuit structure of the drive unit and gating unit provided in the embodiment of the present application. [Figure 9] This is a schematic diagram of the structure of the pixel circuit provided in the embodiment of the present application. [Figure 10] This is a flowchart of the display control method provided in the embodiment of the present application. [Figure 11]This is a signal timing chart provided in an embodiment of the present application, based on the structure shown in Figure 1. [Figure 12] This is a signal timing chart provided in an embodiment of the present application, based on the structure shown in Figure 2. [Figure 13] This is a schematic diagram of the structure of the display device provided in the embodiment of the present application. [Modes for carrying out the invention]

[0028] To further clarify the purpose, technical proposal, and advantages of this application, embodiments of this application will be described in more detail below, accompanied by drawings.

[0029] The transistors used in all embodiments of this application may be thin-film transistors, field-effect transistors, or other components with the same characteristics, and depending on their role in the circuit, the transistors used in the embodiments of this application are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of this application, the source is referred to as the first pole and the drain as the second pole. According to the form in the drawings, the intermediate terminal of the transistor is defined as the control pole and can also be called the gate, the signal input terminal is the source and the signal output terminal is the drain. The switching transistors used in the embodiments of this application may include either P-type switching transistors or N-type switching transistors, where the P-type switching transistor conducts when the gate is at a low level and is blocked when the gate is at a high level, and the N-type switching transistor conducts when the gate is at a high level and is blocked when the gate is at a low level. The multiple signals in each embodiment of this application each have corresponding first and second potentials. The first and second potentials merely indicate that the potential of the signal has two state variables, and do not indicate that the first or second potential has a specific numerical value in the entire text.

[0030] As consumers pursue the ultimate power consumption of display products, LTPO display panels have been designed. Due to the special properties of the material, low-frequency display is possible, achieving a minimum of 1 Hz, thus reducing power consumption and meeting users' needs for low power consumption. Of course, this is not the only example; currently, many manufacturers are proposing further partition frequency conversion designs based on low-frequency display. Here, partition frequency conversion means that the display area of ​​a single display panel can be divided into multiple areas, and different refresh rates can be set for each area. In this way, it is possible to update only a portion of the refresh area and retain the portion that does not need refreshing, resulting in smarter refreshing and thus saving power consumption. However, current partition frequency conversion designs can only control the minimum refresh area to the entire row, that is, they can only divide the display area into multiple areas using pixel rows as units, and each area contains at least one row of pixels, and partition refresh is performed on each area above and below that contains at least one row of pixels.

[0031] Based on this, the embodiment of the present application proposes a partition frequency conversion design that can realize both vertical and horizontal partitions (i.e., dividing the area with pixel rows as units) with the aim of further reducing the refresh area and achieving greater power saving and smarter design.

[0032] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. As shown in Figure 1, the display panel includes a substrate 01, a plurality of pixels 02 arranged in an array, a first drive circuit 03, and a second drive circuit 04.

[0033] The substrate 01 has a display area A1 and a peripheral area B1 that at least partially encloses the display area A1. Referring to Figure 1, in the substrate 01 shown therein, the peripheral area B1 partially encloses the display area A1 and is located on both the left and right sides of the display area A1. Of course, in some other embodiments, the peripheral area B1 may also be located above and / or below the display area A1. Alternatively, the peripheral area B1 may enclose the display area A1, i.e., the display area A1 is surrounded by the GOA area. The embodiments of the present application are not limited to the positional relationship between the peripheral area B1 and the display area A1.

[0034] These multiple pixels 02 are located in the display area A1. Here, array arrangement can mean that the multiple pixels 02 are arranged according to the pixel row direction X1 and pixel column direction Y1 as shown in Figure 1, that is, the display panel can include multiple matrix pixels as shown in Figure 1.

[0035] The first drive circuit 03 is located in the peripheral region B1 and includes a plurality of cascaded first drive units 031 and a plurality of first gating units 032 that correspond one-to-one with the plurality of first drive units 031.

[0036] The second drive circuit 04 is located in the peripheral region B1. The second drive circuit 04 includes a plurality of cascaded second drive units 041 and a plurality of second gating units 042 that correspond one-to-one with the plurality of second drive units 041.

[0037] Furthermore, referring to Figure 1, with the first drive circuit 03 as an example, the statement that multiple first drive units 031 correspond one-to-one with multiple first gating units 032 means that each first drive unit 031 corresponds to one first gating unit 032, and different first drive units 031 correspond to different first gating units 032. Also, the statement that multiple first drive units 031 are cascaded means that two (also called two-stage) first drive units 031 are coupled to each other, and the later first drive unit 031 operates by being driven by the earlier first drive unit 031. Here, the two first drive units 031 coupled to each other may or may not be adjacent, as shown in Figure 1. The related explanation of the second drive circuit 04 is the same, so a detailed explanation of the embodiment of this application is omitted.

[0038] Based on the above combination, and continuing to refer to Figure 1, at least one first drive unit 031 and at least one second drive unit 041 described in the embodiments of the present application can each be located on either side of the pixel row X1 of the substrate 01. That is, as shown in Figure 1, there are one or more first GOA units 031 and second GOA units 041 located on the left and right sides of the display area A1, respectively. Furthermore, each first gating unit 032 and its corresponding first drive unit 031 can be located on the same side of the substrate 01, and each second gating unit 042 and its corresponding second drive unit 041 can be located on the same side of the substrate 01.

[0039] Here, each first drive unit 031 is coupled to a portion of the pixels 02 of at least one row of pixels 02 via a corresponding first gating unit 032. Each first gating unit 032 is further coupled to a first enable line GE1 and is used to control the conduction interruption between the first drive unit 031 and the portion of pixels 02 based on a first enable signal provided from the first enable line GE1. Multiple first drive units 031 are further coupled to a first on line STV1 and are used to output a first gate drive signal based on a first on signal provided from the first on line STV1.

[0040] For example, each first drive unit 031 shown in Figure 1 is coupled to a portion of the pixels 02 in a row via a corresponding first gating unit 032. The first gating unit 032 can also be controlled to conduct to the coupled portion of pixels 02 when the potential of the first enable signal provided from the first enable line GE1 is a first potential, thereby allowing the first gate drive signal output by the first drive unit 031 to be further transmitted to this portion of pixels 02, enabling a refresh scan for this portion of pixels 02 and driving the emission of light from this portion of pixels 02. Alternatively, the first gating unit 032 can be controlled to disconnect the coupling between the first drive unit 031 and the coupled portion of pixels 02 when the potential of the first enable signal provided from the first enable line GE1 is a second potential, thereby preventing the first gate drive signal output by the first drive unit 031 from being transmitted to this portion of pixels 02. In other words, the first gating unit 032 can effectively control whether or not the first gate drive signal output from the first drive unit 031 enters the pixel 02, based on the potential of the first enable signal.

[0041] As one option, in the embodiment of the present application, the first potential may be an active potential, the second potential may be an inactive potential, and the first potential may be higher than the second potential. Of course, in some other embodiments, the first potential may be lower than the second potential.

[0042] Each second drive unit 041 is coupled to a portion of the other pixels 02 of at least one row of pixels 02 via a corresponding second gating unit 042. Each second gating unit 042 is further coupled to a second enable line GE2 and is used to control the conduction interruption between the second drive unit 041 and the other portion of pixels 02 based on a second enable signal provided from the second enable line GE2. Multiple second drive units 041 are further coupled to a second on line STV2 and are used to output a second gate drive signal based on a second on signal provided from the second on line STV2.

[0043] For example, each second drive unit 041 shown in Figure 1 is coupled to some of the other pixels 02 of a row of pixels 02 via a corresponding second gating unit 042. The second gating unit 042 can be controlled to conduct to the other pixels 02 to be coupled when the potential of the second enable signal provided from the second enable line GE2 is a first potential, thereby allowing the second gate drive signal output by the second drive unit 041 to be further transmitted to these other pixels 02, enabling a refresh scan for these other pixels 02 and driving the emission of light in these other pixels 02. Alternatively, the second gating unit 042 can be controlled to disconnect the coupling between the second drive unit 041 and the other pixels 02 to be coupled when the potential of the second enable signal provided from the second enable line GE2 is a second potential, thereby preventing the second gate drive signal output by the second drive unit 041 from being transmitted to these other pixels 02. In other words, the second gating unit 042 can effectively control whether or not the second gate drive signal output from the second drive unit 041 enters the pixel 02, based on the potential of the second enable signal.

[0044] That is, in the display panel described in the embodiment of the present invention, for each row of pixels 02, some (may be one or more) of the pixels 02 can be coupled to a corresponding first drive unit 031 via a first gating unit 032, and the other portion of pixels 02 can be coupled to a corresponding second drive unit 041 via a second gating unit 042. In other words, multiple pixels 02 located in the same row are divided into two parts in the row direction X1 of the pixels, each of which can be coupled to a different drive unit and receive a different gate drive signal. Furthermore, the first gating unit 032 can control the conduction interruption between the first drive unit 031 and some of the pixels 02 in this row based on the first enable signal it receives. The second gating unit 042 can control the conduction interruption between the second drive unit 041 and the other portion of the pixels 02 in this row based on the second enable signal it receives. In other words, the first gating unit 032 and the second gating unit 042 can control the conduction interruption between the corresponding drive unit and the pixel 02 based on different enable signals provided from different enable lines. Furthermore, the first drive unit 031 can output a first gate drive signal based on a received first ON signal, and the second drive unit 041 can output a second gate drive signal based on a received second ON signal. In other words, the first drive unit 031 and the second drive unit 041 can output gate drive signals based on different ON signals provided from different ON lines. In this way, by flexibly setting the ON signals and enable signals and matching them to the coupling relationship, flexible smart refresh can be achieved for different region pixels 02 in the top, bottom, left, and right areas of the display area A1, and different refresh rates can be provided for the refresh of different areas, thereby achieving the purpose of frequency division design and achieving the purpose of greater power saving.Furthermore, by arranging the first drive unit 031 and the second drive unit 041 on the left and right sides of the display area A1, respectively, it is possible to facilitate the design of a narrow bezel for the display device and to lay the foundation for a full-screen design.

[0045] Since both the first drive unit 031 and the second drive unit 041 are used to output gate drive signals, in the embodiment of this application, the first drive unit 031 and the second drive unit 041 may also be referred to as the GOA unit described in the above embodiment, and accordingly, the first drive circuit 03 including the first drive unit 031 and the second drive circuit 04 including the second drive unit 041 may be referred to as the GOA circuit.

[0046] Based on the above, an embodiment of the present application provides a display panel. The display panel includes a substrate including a display area and a peripheral area, a plurality of pixels located in the display area, and a first drive circuit and a second drive circuit located in the peripheral area. Here, the first drive circuit includes a plurality of first drive units and a plurality of first gating units that correspond one-to-one. The second drive circuit includes a plurality of second drive units and a plurality of second gating units that correspond one-to-one. The plurality of first drive units are cascaded and coupled to a first on line and further coupled to some of the pixels of a row via a corresponding first gating unit. The plurality of second drive units are cascaded and coupled to a second on line and further coupled to some of the pixels of this row via a corresponding second gating unit. The first gating unit is further coupled to a first enable line. The second gating unit is further coupled to a second enable line. Multiple first drive units can output a first gate drive signal based on a first ON signal provided from a first ON line. Multiple second drive units can output a second gate drive signal based on a second ON signal provided from a second ON line. A first gating unit can control the conduction interruption between a corresponding first drive unit and some pixels based on a first enable signal provided from a first enable line. A second gating unit can control the conduction interruption between a corresponding second drive unit and some other pixels based on a second enable signal provided from a second enable line. In this way, by flexibly setting the enable and ON signals, flexible refresh can be achieved for pixels in different areas of the display region (top, bottom, left, and right), and different refresh rates can be set for different regions, i.e., section frequency conversion can be achieved, thereby reducing power consumption and achieving the goal of smart power saving.

[0047] As one option, as continuing to refer to Figure 1, in the embodiment of the present application, each first drive unit 031 can be coupled to a portion of pixels 02 of at least one row of pixels 02 that are close to the first gating unit 032 via a corresponding first gating unit 032. Also, each second drive unit 041 can be coupled to other portions of pixels 02 of at least one row of pixels 02 that are close to the second gating unit 042 via a corresponding second gating unit 042. Furthermore, each pixel 02 of the portion of pixels 02 can be adjacent to each other, and each pixel 02 of the other portion of pixels 02 can be adjacent to each other. In this way, multiple pixels 02 located in the same row can be divided into two parts, left and right, in the row direction X1 of the pixels, thereby realizing a left-right frequency division design. In addition, layout and wiring can be facilitated and manufacturing costs can be reduced.

[0048] As one option, as continuing to refer to Figure 1, in a plurality of first drive units 031, the first first drive unit 031 coupled to the first row of pixels 02 from top to bottom in the pixel column direction Y1 is coupled to the first on-line STV1, and each of the remaining first drive units 031 other than the first first drive unit 031 can be sequentially coupled to the adjacent preceding first drive unit 031. Similarly, in a plurality of second drive units 041, the first second drive unit 041 coupled to the first row of pixels 02 from top to bottom in the pixel column direction Y1 may be coupled to the second on-line STV2, and each of the remaining second drive units 041 other than the first second drive unit 041 can be sequentially coupled to the adjacent preceding second drive unit 041. In this way, wiring can be made easier, layout can be simplified, and manufacturing costs can be reduced.

[0049] As one of the options, the selectable embodiments are as follows:

[0050] As shown in Figure 1, the multiple first drive units 031 included in the first drive circuit 03 can all be located on the first side of the two sides. The multiple second drive units 041 included in the second drive circuit 04 can all be located on the second side of the two sides. That is, on both sides in the row direction X1 of the pixels, one side can include multiple cascaded first drive units 031, and the other side can include multiple cascaded second drive units 041.

[0051] As one option, referring to Figure 1, the first side described in the embodiment of the present application can point to the left side of display area A1, and the second side can point to the right side of display area A1. Based on this, in accordance with the coupling configuration in Figure 1, a plurality of first drive units 031 located on the left side of display area A1 can drive pixels in the left half of display area A1. A plurality of second drive units 041 located on the right side of display area A1 can drive pixels in the right half of display area A1. By realizing drive on both the left and right sides, the basis for frequency division design is established. Of course, in some other embodiments, the first side can also point to the right side of display area A1, and accordingly, the second side can point to the left side of display area A1.

[0052] However, test results show that this selectable embodiment, as shown in Figure 1, is prone to process variability or load differences. For this reason, other layout configurations are provided for the embodiments of the present application.

[0053] As an alternative, other possible embodiments are as follows:

[0054] Referring to the schematic diagram of the structure of another display panel shown in Figure 2, some (one or more) of the multiple first drive units 031 can be located on the first side of both sides (for example, the left side), and the remaining first drive units 031 other than some can be located on the second side of both sides (for example, the right side). Similarly, some (one or more) of the multiple second drive units 041 can be located on the first side of both sides, and the remaining second drive units 041 other than some can be located on the second side of both sides.

[0055] Compared to the selectable embodiment shown in Figure 1, the other selectable embodiment can similarly achieve left and right-sided driving, and can transmit both the first gate drive signal and the second gate drive signal across the entire row, thus reducing the likelihood of a split screen phenomenon between the left and right sides, rather than a simple physical left and right division.

[0056] As an option, and continuing to refer to Figure 2, each first drive unit 031 can be coupled to some of the pixels 02 of a row of pixels 02 via a corresponding first gating unit 032. Based on this, each first drive unit 031 coupled to pixels 02 of even rows (i.e., the second, fourth, sixth, etc.) can be located on the first side, and each first drive unit 031 coupled to pixels 02 of odd rows (i.e., the first, third, fifth, etc.) can be located on the second side.

[0057] As one option, as continuing to refer to Figure 2, each second drive unit 041 can be coupled to some of the other pixels 02 of a row of pixels 02 via a corresponding second gating unit 042. Based on this, of the multiple second drive units 041, each second drive unit 041 coupled to pixels 02 in even rows can be located on the first side, and each second drive unit 041 coupled to pixels 02 in odd rows can be located on the second side.

[0058] That is, each first drive unit 031 connected to an odd-numbered row of pixels 02 and each first drive unit 031 connected to an even-numbered row of pixels 02 can be alternately arranged on both the left and right sides in the row direction X1 of the pixels. Also, each second drive unit 041 connected to an odd-numbered row of pixels 02 and each second drive unit 041 connected to an even-numbered row of pixels 02 can be alternately arranged on both sides in the row direction. Furthermore, each first drive unit 031 connected to an odd-numbered row of pixels 02 and each second drive unit 041 connected to an even-numbered row of pixels 02 can be located on the same side (for example, the left side), and each first drive unit 031 connected to an even-numbered row of pixels 02 and each second drive unit 041 connected to an odd-numbered row of pixels 02 can be located on the same side (for example, the right side).

[0059] Accordingly, based on this, and continuing to refer to Figure 2, each first drive unit 031 and each second drive unit 041 located on the first side can be arranged sequentially in the pixel column direction Y1, in the order of one first drive unit 031 followed by one second drive unit 041. Each first drive unit 031 and each second drive unit 041 located on the second side can be arranged sequentially in the pixel column direction Y1, in the order of one second drive unit 041 followed by one first drive unit 031. In this way, the layout of the panel can be facilitated and the wiring can be simplified, thereby saving manufacturing costs.

[0060] Of course, in some other embodiments, each first drive unit 031 coupled to the same set of pixels 02 in multiple adjacent rows may be positioned on the same side, and each first drive unit 031 coupled to adjacent sets may be positioned on both the left and right sides, respectively. The layout of the second drive units 041 is similar. In other words, the layout is not limited to that shown in Figure 2, based on the fact that some drive units are located on the first side and some drive units are located on the second side when installing multiple first drive units 031 and multiple second drive units 041.

[0061] As one option, as shown in Figures 1 and 2 above, each gating unit located on the same side of the substrate 01 among the multiple first gating units 032 and the multiple second gating units 042 can share the same enable wire. That is, they are connected to the same enable wire. In this way, wiring can be further simplified and costs can be saved.

[0062] As one option, for example, if GOA1 labels the first drive unit 031, MS1 labels the first gating unit 032, GOA2 labels the second drive unit 041, and MS2 labels the second gating unit 042, Figure 3 shows a schematic diagram of another display panel structure based on the structure shown in Figure 1, and Figure 4 shows a schematic diagram of yet another display panel structure based on the structure shown in Figure 2. Furthermore, both Figures 3 and 4 schematically show 10 first drive units GOA1-1 to GOA1-10 and the corresponding 10 first gating units MS1-1 to MS1-10, and both also schematically show 10 second drive units GOA2-1 to GOA2-10 and the corresponding 10 second gating units MS2-1 to MS2-10.

[0063] Here, as shown in Figures 3 and 4, each first drive unit 031 (e.g., GOA1-1) is coupled to a first drive line G1 via a corresponding first gating unit 032 (e.g., MS1-1), and the first drive line G1 can be coupled to some pixels 02. Each second drive unit 041 (e.g., GOA2-1) is coupled to a second drive line G2 via a corresponding second gating unit 042 (e.g., MS2-1), and the second drive line G2 can be coupled to other some pixels 02. Furthermore, multiple first drive units 031 can be cascaded via the first drive line G1. Multiple second drive units 041 can be cascaded via the second drive line G2. Accordingly, each first drive unit 031 can transmit a first gate drive signal and a cascading signal via the first drive line G1. Similarly, each second drive unit 041 can transmit a second gate drive signal via the second drive line G2 and also transmit a cascade connection signal.

[0064] Furthermore, the following are selectable embodiments.

[0065] Referring to Figure 3, if multiple first drive units 031 are all located on the first side of both sides, and multiple second drive units 041 are all located on the second side of both sides, then the first drive line G1 and the second drive line G2 can be independent of each other. That is, they are not connected to each other. In other words, pixels 02 located in the same row can be coupled to two drive units via two drive lines.

[0066] Other selectable embodiments are as follows:

[0067] Referring to Figure 4, of the multiple first drive units 031, some first drive units 031 are located on the first side of the two sides, and the remaining first drive units 031 are located on the second side of the two sides. If, of the multiple second drive units 041, some second drive units 041 are located on the first side of the two sides, and the remaining second drive units 041 are located on the second side of the two sides, then the first drive line G1 can not only be coupled to the pixel 02, but also penetrate the display area A1 and cascade the first drive units 031 located on the first side and the first drive units 031 located on the second side. The second drive line G2 can not only be coupled to the pixel 02, but also penetrate the display area A1 and cascade the second drive units 041 located on the first side and the second drive units 041 located on the second side. Furthermore, the first drive line G1 and the second drive line G2, which are connected to pixel 02 in the same row, may overlap in the display area A1.

[0068] As one option, the first drive line G1 can have its portion G11 for coupling to pixel 02 and its portion G12 for cascading to the first drive unit 031 located in different layers. The second drive line G2 can have its portion G21 for coupling to pixel 02 and its portion G22 for cascading to the second drive unit 041 located in different layers. Furthermore, the portion of the first drive line G1 and the second drive line Gate that overlaps (see overlap region C1) can be located in different layers.

[0069] As one option, first referring to Figure 5, the pixel 02 described in the embodiment of the present application may be located on one side of the substrate 01 and may include a gate metal layer GATE, an insulating layer J1, and a source-drain metal layer SD that are sequentially stacked.

[0070] For example, the gate metal layer GATE, insulating layer J1, and source-drain metal layer SD shown in Figure 5 can be sequentially stacked along the direction away from the substrate 01. Furthermore, the pixel 02 may further include a buffer layer BUFFER and an active layer ACT located between the substrate 01 and the gate metal layer GATE, and sequentially stacked along the direction away from the substrate 01. Based on Figure 5, refer to the schematic diagram of the partial structure of the display panel shown in Figure 6.

[0071] In the first drive line G1, the portion G11 for coupling to the pixel 02 can be located in the same layer as the gate metal layer GATE, and the portion G12 for cascading to the first drive unit 031 can be located in the same layer as the source-drain metal layer SD. Furthermore, the portion G11 for coupling to the pixel 02 and the portion G12 for cascading to the first drive unit 031 can be through-connected vias (not shown) penetrating the insulating layer J1.

[0072] Furthermore, in the second drive line G2, the portion G21 for coupling to the pixel 02 can be located in the same layer as the gate metal layer GATE, and the portion G22 for cascading to the second drive unit 041 can be located in the same layer as the source-drain metal layer SD. In addition, the portion G21 for coupling to the pixel 02 and the portion G22 for cascading to the second drive unit 041 can be through-connected vias (not shown) penetrating the insulating layer J1.

[0073] In the overlapping region C1, the portion where the first drive line G1 and the second drive line G2 overlap can be located in the same layer as the gate metal layer GATE, and the other can be located in the same layer as the source-drain metal layer SD.

[0074] That is, based on the layout of Figure 2, the spanlines in the left and right regions of display area A1 can be selected from the gate metal layer GATE and the source / drain metal layer SD. In some embodiments, a pixel may include sequentially stacked source / drain metal layers SD1 and SD2. Accordingly, the spanlines here can also be selected from the source / drain metal layer SD1 and / or the source / drain metal layer SD2. For example, as described in the embodiments above, the spanlines coupled to pixel 02 can be selected from the gate metal layer GATE, and the spanlines not coupled to pixel 02 can be selected from the source / drain metal layer SD1.

[0075] Furthermore, "located in the same layer" can refer to a layer structure formed by using the same film deposition process to create a film layer for a specific pattern, and then patterning the film layer using the same masking plate in a primary patterning process. Depending on the specific pattern, the primary patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and formed by the same primary patterning process. In this way, manufacturing processes and costs can be saved, and manufacturing efficiency can be improved.

[0076] As one option, as continuing to refer to Figure 5, the row of pixels 02 described in the embodiment of the present application may include a red (R) pixel 02, a green (G) pixel 02, and a blue (B) pixel. Of course, in some other embodiments, it may also include pixels of other colors (e.g., white pixels).

[0077] As an alternative, and continuing to refer to Figure 5, in the pixel column direction Y1, the pixels 02 of the multiple columns described in the embodiment of this application may be coupled one-to-one with multiple data lines S1 and used to receive data signals transmitted from the data lines S1. Each pixel 02 can emit light based on the received gate drive signal and data signal.

[0078] As one option, referring to the schematic diagram of the substrate 01 shown in Figures 3 and 4, and Figure 7, the substrate 01 described in the embodiment of the present application may include a left display area A11 and a right display area A12 arranged along the row direction X1 of pixels from the first row of pixels 02 to the last row of pixels 02, the left display area A11 may include some of the pixels 02 of a row of pixels 02, and the right display area A12 may include other some of the pixels 02 of a row of pixels 02. Here, as described in the above embodiment, some of the pixels 02 here refers to pixels 02 of a row of pixels 02 that are coupled to the first drive unit 031, and other some of the pixels 02 refer to pixels 02 of a row of pixels 02 that are coupled to the second drive unit 041. That is, the first drive unit 031 is coupled to a plurality of pixels 02 in the left display area A11 and can drive the emission of light from the pixels 02 in the left display area A11. The second drive unit 041 is coupled to multiple pixels 02 in the right display area A12 and can drive the light emission of the pixels 02 in the right display area A12. In this way, a left-right frequency division design can be realized.

[0079] Furthermore, as described in the above embodiment and continuing to refer to Figure 7, the substrate 01 is divided into a left display area A11 and a right display area A12, and may further include an upper display area and a lower display area arranged along the pixel column direction Y1 from the first row of pixels 02 to the last row of pixels 02, and both the upper display area and the lower display area include at least one row of pixels 02. Exemplarily, in Figure 7, the upper display area divided into the left display area A11 is labeled as A11-1, and the lower display area is labeled as A11-2. The upper display area divided into the right display area A12 is labeled as A12-1, and the lower display area is labeled as A12-2.

[0080] As one option, based on the layouts shown in Figures 2 and 4, and considering reliable cascaded transmission between the first drive unit 031 and the second drive unit 041, the embodiment of the present invention can also make the refresh rate (frames rate, FR) of the upper display area greater than the refresh rate of the lower display area.

[0081] For example, in Figure 7, in the left display area A11, the refresh rate FR1 of the upper display area A11-1 may be equal to or greater than the refresh rate FR3 of the lower display area A11-2, and in the right display area A12, the refresh rate FR2 of the upper display area A12-1 may be equal to or greater than the refresh rate FR4 of the lower display area A12-2.

[0082] Of course, in the left display area A11 and the right display area A12, the refresh rate FR1 of the upper display area A11-1 and the refresh rate FR2 of the upper display area A12-1 may be unrelated in size. Similarly, the refresh rate FR3 of the lower display area A11-2 and the refresh rate FR4 of the lower display area A12-2 may be unrelated in size.

[0083] As one option, in the embodiment of the present application, as shown in Figure 7, the left display area A11 and the right display area A12 may have the same area and the same number of pixels 02 they contain. And / or, the upper display area (A11-1 and A12-1) and the lower display area (A11-2 and A12-2) may have the same area and the same number of pixels 02 they contain. That is, in the case of frequency division drive, the left and right frequency division areas may be the same, and / or the upper and lower frequency division areas may be the same. In this way, uniform frequency division drive can be achieved and a good display effect can be ensured.

[0084] Of course, in some other embodiments, the left and right frequency division areas may differ depending on the needs of different users. For example, the area of ​​the left display area A11 may be 2 / 3 of the total area of ​​the display area A1, and accordingly, the area of ​​the right display area A12 may be 1 / 3 of the total area of ​​the display area A1. That is, a 2 / 3 frequency division on the left and a 1 / 3 frequency division on the right can be installed. Also, the upper and lower frequency division areas may differ. Of course, the upper and lower frequency division refresh rates may also differ. For example, the refresh rate of the upper display area may be 120Hz, and the refresh rate of the lower display area may be 30Hz.

[0085] As one option, Figure 8 is a schematic diagram of a circuit provided in an embodiment of the present application. Referring to Figure 8, the first gating unit 032 described in an embodiment of the present application may include a first gating switch element MS-T1. The second gating unit 042 includes a second gating switch element MS-T2.

[0086] The gate of the first gating switch element MS-T1 can be coupled to the first enable line GE1, the first pole of the first gating switch element MS-T1 can be coupled to the corresponding first drive unit 031, and the second pole of the first gating switch element MS-T1 can be coupled to some pixels 02. The first gating switch element MS-T1 can be turned on when the potential of the first enable signal provided from the first enable line GE1 is at a first potential, thereby connecting the first drive unit 031 to the pixels 02 and causing the first drive unit 031 to transmit the first gate drive signal to the pixels 02. Furthermore, the first gating switch element MS-T1 can be turned off when the potential of the first enable signal provided from the first enable line GE1 is at a second potential, thereby disconnecting the first drive unit 031 from the pixels 02.

[0087] The gate of the second gating switch element MS-T2 can be coupled to the second enable line GE2, the first pole of the second gating switch element MS-T2 can be coupled to the corresponding second drive unit 041, and the second pole of the second gating switch element MS-T2 can be coupled to some other pixels 02. The second gating switch element MS-T2 can be turned on when the potential of the second enable signal provided from the second enable line GE2 is at a first potential, thereby connecting the second drive unit 041 to the pixel 02, and used to transmit the second gate drive signal to the pixel 02 to the second drive unit 041. Furthermore, the second gating switch element MS-T2 can be turned off when the potential of the second enable signal provided from the second enable line GE2 is at a second potential, thereby disconnecting the second drive unit 041 from the pixel 02.

[0088] As one option, the display panel described in the embodiments of the present application may include the LTPO display panel described in the above embodiments. Exemplarily, using an LTPO display panel as an example, Figure 9 shows a schematic diagram of the structure of the pixels it includes. As shown in Figure 9, pixel 02 may include a pixel circuit 021 and a light-emitting element L1. The pixel circuit 021 may also be an 8T1C structure, that is, including eight transistors T1 to T8 and one capacitor C1.

[0089] Here, the gate of transistor T1 can be coupled to the reset terminal N-Reset, the first pole of transistor T1 can be coupled to the first initial terminal Vinit1, and the second pole of transistor T1 can be coupled to node N3. Transistor T1 can be turned on when the potential of the reset signal provided from the reset terminal N-Reset is at a first potential, thereby conducting the first initial terminal Vinit1 to node N3, and transmitting the first initial signal provided from the first initial terminal Vinit1 to node N3, thereby achieving a reset for node N3. Furthermore, transistor T1 can be turned off when the potential of the reset signal provided from the reset terminal N-Reset is at a second potential, thereby disconnecting the coupling between the first initial terminal Vinit1 and node N3.

[0090] The gate of transistor T2 can be coupled to the gate signal terminal Gate_N, the first pole of transistor T2 can be coupled to node N3, and the second pole of transistor T2 can be coupled to node N1. Transistor T2 can be turned on when the potential of the gate drive signal provided from the gate signal terminal Gate_N is at a first potential, and used to conduct node N1 to node N3. Transistor T2 can also be turned off when the potential of the gate drive signal provided from the gate signal terminal Gate_N is at a second potential, and used to disconnect the coupling between node N1 and node N3.

[0091] The gate of transistor T3 can be coupled to node N1, the first pole of transistor T3 can be coupled to node N2, and the second pole of transistor T3 can be coupled to node N3. Transistor T3 can be used to transmit a light-emitting drive signal to node N3 based on the potentials of node N1 and node N2. Transistor T3 can also be called a drive transistor.

[0092] The gate of transistor T4 can be coupled to the gate signal terminal Gate_P, the first pole of transistor T4 can be coupled to the data signal terminal Vdata, and the second pole of transistor T4 can be coupled to node N2. Transistor T4 can be turned on when the potential of the gate drive signal provided from the gate signal terminal Gate_P is at the first potential, thereby connecting the data signal terminal Vdata to node N2, and used to transmit the data signal provided from the data signal terminal Vdata to node N2. Based on the fact that both transistors T2 and T3 are conducting, the data signal transmitted to node N2 can be further written to node N1 via transistors T3 and T2. Furthermore, transistor T4 can be turned off when the potential of the gate drive signal provided from the gate signal terminal Gate_P is at the second potential, thereby disconnecting the data signal terminal Vdata from node N2.

[0093] The gate of transistor T5 can be coupled to the light emission control terminal EM, the first pole of transistor T5 can be coupled to the drive power supply terminal VDD, and the second pole of transistor T5 can be coupled to node N2. Transistor T5 can be turned on when the potential of the light emission control signal provided from the light emission control terminal EM is at a first potential, thereby connecting the drive power supply terminal VDD to node N2, and used to transmit the drive power supply signal provided from the drive power supply terminal VDD to node N2. Transistor T5 can also be turned off when the potential of the light emission control signal provided from the light emission control terminal EM is at a second potential, thereby disconnecting the drive power supply terminal VDD from node N2.

[0094] The gate of transistor T6 can be coupled to the light emission control terminal EM, the first pole of transistor T6 can be coupled to node N3, and the second pole of transistor T6 can be coupled to the first pole of the light-emitting element L1. Transistor T6 can be turned on when the potential of the light emission control signal provided from the light emission control terminal EM is at a first potential, thereby connecting node N3 to the first pole of the light-emitting element L1, and used to transmit a signal (e.g., a light emission drive signal) transmitted to node N3 to the first pole of the light-emitting element L1. Transistor T6 can also be turned off when the potential of the light emission control signal provided from the light emission control terminal EM is at a second potential, thereby disconnecting node N3 from the first pole of the light-emitting element L1. The second pole of the light-emitting element L1 can also be coupled to the pull-down power supply terminal VSS, and the light-emitting element L1 can emit light due to the voltage difference between the signal received by its first pole and the pull-down power supply signal provided from the pull-down power supply terminal VSS coupled to its second pole.

[0095] As one option, one of the first and second poles of the light-emitting element L1 may be an anode, and the other may be a cathode. For example, see 9, where the first pole is an anode and the second pole is a cathode.

[0096] The gate of transistor T7 can be coupled to the reset terminal P-Reset, the first pole of transistor T7 can be coupled to the second initial terminal Vinit2, and the second pole of transistor T7 can be coupled to the first pole of the light-emitting element L1. Transistor T7 can be turned on when the potential of the reset signal provided from the reset terminal P-Reset is at a first potential, thereby conducting the second initial terminal Vinit2 to the first pole of the light-emitting element L1, and transmitting the second initial signal provided from the second initial terminal Vinit2 to the first pole of the light-emitting element L1, thereby achieving a reset of the first pole of the light-emitting element L1. Furthermore, transistor T7 can be turned off when the potential of the reset signal provided from the reset terminal P-Reset is at a second potential, thereby disconnecting the coupling between the second initial terminal Vinit2 and the first pole of the light-emitting element L1.

[0097] The gate of transistor T8 can be coupled to the reset terminal H-Reset, the first pole of transistor T8 can be coupled to the third initial terminal Vinit3, and the second pole of transistor T8 can be coupled to node N2. Transistor T8 can be turned on when the potential of the reset signal provided from the reset terminal H-Reset is at the first potential, thereby conducting the third initial terminal Vinit3 to node N2, and transmitting the third initial signal provided from the third initial terminal Vinit3 to node N2, thereby achieving a reset for node N2. Transistor T8 can also be turned off when the potential of the reset signal provided from the reset terminal H-Reset is at the second potential, thereby disconnecting the coupling between the third initial terminal Vinit3 and node N2.

[0098] One end of capacitor C1 can be coupled to node N1, and the other end of capacitor C1 can be coupled to the drive power terminal VDD. Capacitor C1 can be used to store the potential of node N1 based on the drive power signal provided from the drive power terminal VDD.

[0099] Furthermore, the transistor T2 coupled to the gate signal terminal Gate_N may be an N-type transistor made of oxide material, and the transistor T4 coupled to the gate signal terminal Gate_P may be a P-type transistor made of low-temperature polysilicon (LTPS). In this way, the display panel is called an LTPO panel. Note that the transistor material here can refer to the material of the active layer contained in the transistor.

[0100] Furthermore, in accordance with Figures 3 and 4 above, the first drive line G1 and the second drive line G2 can both be coupled to the gate signal terminal Gate_N in the pixel 02, which is coupled to the transistor T2 included in the pixel circuit 021. Accordingly, the first on-line STV1 and the second on-line STV2 can both be labeled as NSTV. Here, N represents an N-type transistor, and accordingly, it represents an embodiment in which the first potential is high potential and the second potential is low potential. Of course, in some embodiments, it is not limited to being coupled to the gate signal terminal Gate_N. For example, the first drive line G1 and the second drive line G2 can also be coupled to the gate signal terminal Gate_P in the pixel circuit 02, which is coupled to the transistor T4. That is, the first drive unit 031 and the second drive unit 041 may act only on transistor T2, or they may act in common on transistors T2 and T4. The data line S1 can both be coupled to the data signal terminal Vdata in the pixel 02, which is coupled to the transistor T4 included in the pixel circuit 021.

[0101] Note that the pixel circuit 021 is not limited to the 8T1C structure shown in Figure 9. For example, in some other embodiments, the pixel circuit 021 does not need to include transistor T8 and has a 7T1C structure.

[0102] Based on the above, an embodiment of the present application provides a display panel. The display panel includes a substrate including a display area and a peripheral area, a plurality of pixels located in the display area, and a first drive circuit and a second drive circuit located in the peripheral area. Here, the first drive circuit includes a plurality of first drive units and a plurality of first gating units that correspond one-to-one. The second drive circuit includes a plurality of second drive units and a plurality of second gating units that correspond one-to-one. The plurality of first drive units are cascaded and coupled to a first on line and further coupled to some of the pixels of a row via a corresponding first gating unit. The plurality of second drive units are cascaded and coupled to a second on line and further coupled to some of the pixels of this row via a corresponding second gating unit. The first gating unit is further coupled to a first enable line. The second gating unit is further coupled to a second enable line. Multiple first drive units can output a first gate drive signal based on a first ON signal provided from a first ON line. Multiple second drive units can output a second gate drive signal based on a second ON signal provided from a second ON line. A first gating unit can control the conduction interruption between a corresponding first drive unit and some pixels based on a first enable signal provided from a first enable line. A second gating unit can control the conduction interruption between a corresponding second drive unit and some other pixels based on a second enable signal provided from a second enable line. In this way, by flexibly setting the enable and ON signals, flexible refresh can be achieved for pixels in different areas of the display region (top, bottom, left, and right), and different refresh rates can be set for different regions, i.e., section frequency conversion can be achieved, thereby reducing power consumption and achieving the goal of smart power saving.

[0103] Figure 10 is a method flowchart of a display control method provided in an embodiment of the present application, which can be used to control a display panel as described in the above embodiment. As shown in Figure 10, the method includes the following steps.

[0104] Step 1001: Determine the refresh needs of different areas within the display area of ​​the substrate.

[0105] Here, in the embodiment of the present application, the different regions may include a left region and a right region located in the row direction X1 of the pixels, and / or an upper region and a lower region located in the pixel column direction Y1, and refresh needs may be used to indicate whether a refresh is necessary and the refresh frequency. Exemplaryly, as shown in Figure 7, the left region may refer to the left display region A11, and the right region may refer to the right display region A12. Furthermore, the upper region may refer to the upper display regions A11-1 and A12-1, and the lower region may refer to the lower display regions A11-2 and A12-2.

[0106] As one option, the display control method described in the embodiment of this application can be applied to a driver chip (also called a driver integrated circuit (DIC)) included in the display device.

[0107] Here, the DIC can be coupled to the host-side access point (AP). The DIC can directly determine the refresh needs, that is, it can determine the left / right refresh area positions and the top / bottom refresh area positions of the display area, or the DIC can receive data signals from the AP and determine the refresh needs by comparing the received data signals in real time with the data signals of the previous frame.

[0108] Step 1002: In response to the frame synchronization signal and based on the refresh needs, a first enable signal is transmitted to a first enable line coupled to a plurality of first gating units, and a second enable signal is transmitted to a second enable line coupled to a plurality of second gating units.

[0109] Here, a first enable signal of a first potential can be used to instruct a first gating unit to control the corresponding first drive unit to conduct with some of the pixels to be coupled, and a first enable signal of a second potential can be used to instruct a first gating unit to control the corresponding first drive unit to disconnect the coupling between some of the pixels to be coupled.

[0110] Similarly, a second enable signal of the first potential can be used to instruct a second gating unit to control the corresponding second drive unit to conduct with some of the other pixels being coupled, and a second enable signal of the second potential can be used to instruct a second gating unit to control the corresponding second drive unit to disconnect the coupling with some of the other pixels being coupled.

[0111] As an option, after determining the refresh needs, the DIC can further generate a first enable signal and a second enable signal based on the refresh needs in response to the frame synchronization signal Vsync, and output them to the first enable line GE1 and the second enable line GE2, respectively. The frame synchronization signal Vsync is used to indicate turning on the scanning of one frame.

[0112] Step 1003: In response to the frame synchronization signal, a first ON signal is transmitted to a first ON line coupled to a plurality of first drive units, and a second ON signal is transmitted to a second ON line coupled to a plurality of second drive units.

[0113] Here, the first ON signal can be used to instruct multiple first drive units to output a first gate drive signal, and the second ON signal can be used to instruct multiple second drive units to output a second gate drive signal.

[0114] As an alternative, the DIC can also respond to the frame synchronization signal Vsync by generating a first ON signal and a second ON signal, which can then be transmitted to the first ON line STV1 and the second ON line STV2, respectively.

[0115] In the embodiment of the present invention, when the first gating unit controls the first drive unit to make electrical contact with some of the pixels to be coupled, the first drive unit can drive some of the pixels to emit light by transmitting a first gate drive signal to them. When the second gating unit controls the second drive unit to make electrical contact with other some of the pixels to be coupled, the second drive unit can drive some of the other pixels to emit light by transmitting a second gate drive signal to them.

[0116] As one option, using the structure shown in Figures 1 and 3 as an example, where the first potential is high potential and the second potential is low potential, Figure 11 shows a timing chart, and Figure 12 shows another timing chart, based on the structure shown in Figures 2 and 4. As shown in Figures 11 and 12, after the arrival of the frame synchronization signal Vsync, it is possible to start lowering / raising the first enable signal provided by the first enable line GE1 on any one line, and to start lowering / raising the second enable signal provided by the second enable line GE2 on any one line.

[0117] Here, when the first enable signal is raised (i.e., the potential of the first enable signal becomes high), the first gating unit 032 controls the first drive unit 031 to conduct to a portion of the pixels 02 to be coupled, based on the high potential of the first enable signal, thereby allowing the first drive unit 031 to transmit the first gate drive signal to this portion of pixels 02, and thereby enabling a refresh scan for this portion of pixels 02. When the first enable signal is lowered (i.e., the potential of the first enable signal becomes low), the first gating unit 032 controls the connection between the first drive unit 031 and the portion of the pixels 02 to be coupled, based on the high potential of the first enable signal, thereby preventing the first drive unit 031 from transmitting the first gate drive signal to this portion of pixels 02, and thus a refresh scan is not performed on this portion of pixels 02, and this portion of pixels 02 can be held in the state of the most recent frame.

[0118] Similarly, with respect to the second enable signal, when the second enable signal is raised (i.e., the potential of the second enable signal becomes high), the second gating unit 042 controls the second drive unit 041 to conduct to some of the other pixels 02 that are coupled, based on the high potential second enable signal, thereby allowing the second drive unit 041 to transmit the first gate drive signal to these other pixels 02, thereby enabling a refresh scan for these other pixels 02. When the second enable signal is lowered (i.e., the potential of the second enable signal becomes low), the second gating unit 042 controls the second drive unit 041 to disconnect from some of the other pixels 02 that are coupled, based on the high potential second enable signal, thereby preventing the second drive unit 041 from transmitting the first gate drive signal to these other pixels 02. As a result, a refresh scan is not performed on these other pixels 02, and these other pixels 02 can be retained in the state of the most recent frame.

[0119] This means that by flexibly setting the first and second enable signals, smart refresh can be achieved for different area positions in the display area—top, bottom, left, and right—and frequency division drive can be realized.

[0120] Based on the above, an embodiment of the present invention provides a display control method. In this method, a plurality of first drive units can output a first gate drive signal based on a first ON signal provided from a first ON line. A plurality of second drive units can output a second gate drive signal based on a second ON signal provided from a second ON line. A first gating unit can control the conduction blocking between a corresponding first drive unit and some pixels based on a first enable signal provided from a first enable line. A second gating unit can control the conduction blocking between a corresponding second drive unit and some other pixels based on a second enable signal provided from a second enable line. In this way, by flexibly setting the enable signal and ON signal, flexible refresh can be achieved for pixels in different areas of the display area, such as the top, bottom, left, and right, and the refresh rate can be made different for different areas, that is, section frequency conversion can be achieved, thereby reducing power consumption and achieving the objective of smart power saving.

[0121] Figure 13 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. As shown in Figure 13, the display device includes a drive chip DIC and a display panel 00 which is described in the embodiment as described above.

[0122] Here, the drive chip DIC is coupled to a signal line connected to the circuit in the display panel 00 and is used to provide a signal to the signal line.

[0123] For example, the drive chip DIC can be coupled to a first on-line STV1 coupled to a first drive unit 031 included in the first drive circuit 03 in the display panel 00, to a first enable line GE1 coupled to a first gating unit 032 included in the first drive circuit 03, to a second on-line STV2 coupled to a second drive unit 041 included in the second drive circuit 04, and to a second enable line GE2 coupled to a second gating unit 042 included in the second drive circuit 04. The drive chip DIC is used to provide a first on-signal to the first on-line STV1, a second on-signal to the second on-line STV2, a first enable signal to the first enable line GE1, and a second enable signal to the second enable line GE2.

[0124] As one option, the display device described in the embodiments of this application may be any product or component having a display function, such as a mobile phone (for example, a foldable mobile phone capable of realizing a left and right split screen), a tablet, a flexible display device, a television, or a display. Taking the case where the display device is a mobile phone as an example, the solution described in the embodiments of this application can realize a left and right split screen design when the mobile phone is rotated, and has high driving flexibility.

[0125] Furthermore, the terminology used in the embodiments of this Application is used to describe the embodiments of this Application and is not intended to limit this Application. Unless otherwise defined, the technical or scientific terms used in the embodiments of this Application shall have the ordinary meanings that would be understood by those skilled in the art in which this Application pertains.

[0126] For example, in the embodiments of this application, the terms “first” and “second” are used solely to describe the purpose and should not be understood as indicating or implying relative importance. The term “plural” refers to two or more unless otherwise specified.

[0127] Similarly, words like "one" or "one" do not indicate a limit on quantity, but rather indicate the existence of at least one.

[0128] "Connection" or "bonding" refers to an electrical connection. "And / or" indicates that there can be three possible relationships; for example, A and / or B can indicate three cases: A exists alone, A and B exist together, and B exists alone. The letter " / " generally indicates that the related objects before and after it have an "or" relationship.

[0129] Similar words such as "include" or "inclusive" mean that the elements or objects that appear before "include" or "inclusive" cover the elements or objects and their equivalents listed after "include" or "inclusive," without excluding other elements or objects.

[0130] Terms such as "up," "down," "left," and "right" are used solely to indicate relative positions, and if the absolute position of the object being described changes, the relative positional relationships may also change accordingly.

[0131] The foregoing are merely selectable embodiments of the present application and are not intended to limit it. Any modifications, equivalent substitutions, improvements, etc., made in the spirit and principles of the present application should all be included within the scope of protection. [Explanation of Symbols]

[0132] 01 Substrate BUFFER Buffer layer G1 First drive line J1 Insulating layer SD Source Drain Metal Layer ACT active layer GATE Gate Metal Layer

Claims

1. A substrate having a display area and a peripheral area that at least partially encloses the display area, Multiple pixels arranged in an array in the aforementioned display area, The first drive circuit located in the peripheral region, The second drive circuit located in the aforementioned peripheral region, Includes, The first drive circuit includes a plurality of first drive units connected in cascade, and a plurality of first gating units that correspond one-to-one with the plurality of first drive units, The second drive circuit includes a plurality of cascaded second drive units and a plurality of second gating units that correspond one-to-one with the plurality of second drive units, At least one first drive unit and at least one second drive unit are located on opposite sides of the pixels in the row direction of the substrate, each first gating unit and its corresponding first drive unit are located on the same side of the substrate, and each second gating unit and its corresponding second drive unit are located on the same side of the substrate. Each first drive unit is coupled to a portion of the pixels of at least one row via a corresponding first gating unit, the first gating unit is further coupled to a first enable line and is used to control the conduction interruption between the first drive unit and the portion of the pixels based on a first enable signal provided from the first enable line, and the plurality of first drive units are further coupled to a first on line and is used to output a first gate drive signal based on a first on signal provided from the first on line, Each second drive unit is coupled to some of the other pixels of the at least one row of pixels via a corresponding second gating unit, the second gating unit is further coupled to a second enable line and is used to control the conduction interruption between the second drive unit and the other some pixels based on a second enable signal provided from the second enable line, and the plurality of second drive units are further coupled to a second on line and is used to output a second gate drive signal based on a second on signal provided from the second on line. Display panel.

2. Each of the plurality of first drive units is located on the first side of the two sides, and each of the plurality of second drive units is located on the second side of the two sides. The display panel according to claim 1.

3. Some of the plurality of first drive units are located on the first side of the two sides, and the remaining first drive units are located on the second side of the two sides. Some of the plurality of second drive units are located on the first side of the two sides, and the remaining second drive units are located on the second side of the two sides. The display panel according to claim 1.

4. Each first drive unit is coupled to a portion of the pixels in a row via a corresponding first gating unit. Of the plurality of first drive units, each first drive unit coupled to a pixel in an even row is located on the first side, and each first drive unit coupled to a pixel in an odd row is located on the second side. The display panel according to claim 3.

5. Each second drive unit is coupled to some of the other pixels of a row of pixels via a corresponding second gating unit. Of the plurality of second drive units, each second drive unit coupled to pixels in even rows is located on the first side, and each second drive unit coupled to pixels in odd rows is located on the second side. The display panel according to claim 3 or 4.

6. Each first drive unit and each second drive unit located on the first side are arranged sequentially in the pixel row direction, in the order of one first drive unit followed by one second drive unit. Each first drive unit and each second drive unit located on the second side are arranged sequentially in the pixel row direction, in the order of one second drive unit followed by one first drive unit. The display panel according to claim 5.

7. Each first drive unit is coupled to a first drive line via a corresponding first gating unit, the first drive line is coupled to some of the pixels, each second drive unit is coupled to a second drive line via a corresponding second gating unit, the second drive line is coupled to some of the other pixels, and the plurality of first drive units are cascaded via the first drive line, and the plurality of second drive units are cascaded via the second drive line. The display panel according to any one of claims 1 to 4.

8. When the plurality of first drive units are all located on the first side of the two sides, and the plurality of second drive units are all located on the second side of the two sides, the first drive line and the second drive line are independent of each other. The display panel according to claim 7.

9. If some of the plurality of first drive units are located on the first side of the two sides, and the remaining first drive units other than the plurality of first drive units are located on the second side of the two sides, and some of the plurality of second drive units are located on the first side of the two sides, and the remaining second drive units other than the plurality of second drive units are located on the second side of the two sides, In addition to being coupled to the pixels, the first drive line further penetrates the display area and cascades the first drive unit located on the first side and the first drive unit located on the second side. In addition to being coupled to the pixels, the second drive line further penetrates the display area and cascades the second drive unit located on the first side and the second drive unit located on the second side. Furthermore, the first drive line and the second drive line, which are joined to pixels in the same row, have an overlap in the display area. The display panel according to claim 7.

10. The first drive line has a portion for coupling to a pixel and a portion for cascading to a first drive unit located in different layers, and the second drive line has a portion for coupling to a pixel and a portion for cascading to a second drive unit located in different layers, and the portion where the first drive line and the second drive line overlap is located in different layers. The display panel according to claim 9.

11. The aforementioned pixel is located on one side of the substrate and includes a gate metal layer, an insulating layer, and a source-drain metal layer that are sequentially stacked. The first drive line has a portion for coupling to a pixel located in the same layer as the gate metal layer, and a portion for cascading to a first drive unit located in the same layer as the source-drain metal layer, and the portion for coupling to a pixel and the portion for cascading to a first drive unit are through-connected via vias penetrating the insulating layer. The second drive line has a portion for coupling to a pixel located in the same layer as the gate metal layer, and a portion for cascading to a second drive unit located in the same layer as the source-drain metal layer, and the portion for coupling to a pixel and the portion for cascading to a second drive unit are through-connected via a via penetrating the insulating layer. The display panel according to claim 10.

12. The aforementioned substrate is The left and right display regions are arranged in the row direction of the pixels, from the first row of pixels to the last row of pixels, An upper display area and a lower display area are arranged in the direction of the pixel column, from the first row of pixels to the last row of pixels, Includes, The left display area includes some of the pixels, the right display area includes some of the other pixels, and both the upper display area and the lower display area each include at least one row of pixels. The display panel according to any one of claims 1 to 4.

13. The refresh rate of the upper display area is equal to or greater than the refresh rate of the lower display area. The display panel according to claim 12.

14. The left display area and the right display area have the same area, and / or the same number of pixels they contain, The upper display area and the lower display area have the same area and the same number of pixels. The display panel according to claim 12.

15. Of the plurality of first gating units and the plurality of second gating units, each gating unit located on the same side of the substrate shares the same enable wire. The display panel according to any one of claims 1 to 4.

16. The first gating unit includes a first gating switch element, and the second gating unit includes a second gating switch element. The gate of the first gating switch element is coupled to the first enable line, the first pole of the first gating switch element is coupled to the corresponding first drive unit, and the second pole of the first gating switch element is coupled to some of the pixels. The gate of the second gating switch element is coupled to the second enable line, the first pole of the second gating switch element is coupled to the corresponding second drive unit, and the second pole of the second gating switch element is coupled to some of the other pixels. The display panel according to any one of claims 1 to 4.

17. Each first drive unit is coupled to a portion of pixels in at least one row of pixels that are close to the first gating unit via a corresponding first gating unit, and each second drive unit is coupled to another portion of pixels in at least one row of pixels that are close to the second gating unit via a corresponding second gating unit, and each of the pixels in the portion of pixels is adjacent to one another, and each of the pixels in the other portion of pixels is adjacent to one another, The display panel according to any one of claims 1 to 4.

18. The display panel includes a low-temperature polysilicon oxide (LTPO) display panel. The display panel according to any one of claims 1 to 4.

19. A display control method used to control a display panel according to any one of claims 1 to 4, The refresh needs of different regions within the display area of ​​the substrate are determined, and these different regions include left and right regions arranged in the row direction of pixels, and / or upper and lower regions arranged in the column direction of pixels, and these refresh needs are used to indicate whether a refresh is necessary and the refresh frequency. In response to a frame synchronization signal and based on the refresh needs, a first enable signal is transmitted to a first enable line coupled to the plurality of first gating units, and a second enable signal is transmitted to a second enable line coupled to the plurality of second gating units, wherein the first enable signal of a first potential is used to instruct the first gating unit to control the corresponding first drive unit to conduct with some of the coupled pixels, the first enable signal of a second potential is used to instruct the first gating unit to control the coupling between the corresponding first drive unit and some of the coupled pixels, the second enable signal of a first potential is used to instruct the second gating unit to control the corresponding second drive unit to conduct with some of the coupled pixels, and the second enable signal of a second potential is used to instruct the second gating unit to control the coupling between the corresponding second drive unit and some of the coupled pixels, In response to a frame synchronization signal, a first ON signal is transmitted to a first ON line coupled to the plurality of first drive units, and a second ON signal is transmitted to a second ON line coupled to the plurality of second drive units, the first ON signal is used to instruct the plurality of first drive units to output a first gate drive signal, and the second ON signal is used to instruct the plurality of second drive units to output a second gate drive signal. Includes, When the first gating unit controls the first drive unit to make electrical contact with some of the pixels to be coupled, the first drive unit transmits the first gate drive signal to some of the pixels. When the second gating unit controls the second drive unit to make electrical contact with some other pixels to be coupled, the second drive unit transmits the second gate drive signal to some other pixels. Display control method.

20. The system includes a drive chip and a display panel according to any one of claims 1 to 4, The drive chip is coupled to a signal line to which the circuit in the display panel is coupled, and is used to provide a signal to the signal line. Display device.

Images