Display driver circuit and display device

Abstract

This application provides a display drive circuit and a display device, the display drive circuit including a plurality of frequency division control lines and a plurality of gate drive circuits connected in cascade, the plurality of frequency division control lines transmitting frequency division control signals to the plurality of gate drive circuits, each gate drive circuit including a plurality of first output modules, the plurality of first output modules output a plurality of first gate control signals having a phase difference.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display driving circuit and a display device.

[0002] This application claims the priority of a Chinese patent application with the application number 202410405954.4 filed with the Chinese Patent Office on April 3, 2024, and all the contents of the said application are incorporated herein by reference.

Background Art

[0003] By controlling the display panel to have different refresh rates corresponding to different display areas, the design of area division and frequency division can be realized, thereby reducing power consumption. However, the number of transistors included in the gate driving circuit used by the display panel to realize the design of area division and frequency division is large, and the gate driving unit including the gate driving circuits of multiple stages occupies a relatively large bezel space of the display panel during layout design, which is disadvantageous for realizing the narrow bezel design of the display panel.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of this application provide a display driving circuit and a display device, which can reduce the layout space occupied by a gate driving unit including gate driving circuits of multiple stages.

Means for Solving the Problems

[0005] Embodiments of this application provide a display driving circuit, which includes a gate driving unit. The gate driving unit includes a plurality of frequency division control lines and a plurality of gate driving circuits connected in cascade. The plurality of frequency division control lines are arranged to transmit frequency division control signals to the plurality of gate driving circuits. Each gate driving circuit includes a node control module, a plurality of first output modules, and at least one first frequency division module.

[0006] A node control module is electrically connected to the first and second nodes of the gate drive circuit of the current stage, and is configured to control the signals transmitted to the first and second nodes based on a corresponding first clock signal and a start signal. Each first output module is electrically connected to the first and second nodes, and is configured to output a first gate control signal based on a corresponding second clock signal, a frequency division control signal, and signals from the first and second nodes. At least one first frequency division module is electrically connected to the first node, the second node, and at least one first output module, and is configured to control the signal transmission between the first node and the corresponding first output module based on a frequency division control signal and signals from the second node. Here, a plurality of first output modules are configured to output a plurality of first gate control signals having a phase difference.

[0007] This application provides a display device which includes any of the above-described display driving circuits and display panels. The display panel is electrically connected to the display driving circuit and includes a plurality of subpixels, each subpixel including a light-emitting element, a driving transistor, and a data transistor. The driving transistor is arranged to generate a driving current for driving the light-emitting element to emit light, and the data transistor is arranged to transmit a data signal to the control terminal of the driving transistor. Here, first gate control signals output from a plurality of first output modules in the same gate driving circuit are electrically connected to the control terminals of data transistors in a plurality of adjacent rows of subpixels, and each first gate control signal is electrically connected to the control terminal of a data transistor in at least one row of subpixels. [Brief explanation of the drawing]

[0008] [Figure 1] This is a principle block diagram showing the display drive circuit provided by the embodiment of the present application.

[0009] [Figure 2] This is a principle block diagram showing a gate drive circuit provided by an embodiment of the present application.

[0010] [Figure 3A] This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention. [Figure 3B] This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention. [Figure 3C] This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention. [Figure 3D] This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention. [Figure 3E] This is a schematic diagram showing the connection between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention.

[0011] [Figure 4] This is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present invention.

[0012] [Figure 5A] This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application. [Figure 5B] This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application. [Figure 5C] This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application. [Figure 5D] This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application. [Figure 5E] This is a timing diagram corresponding to the gate drive circuit provided by the embodiment of the present application.

[0013] [Figure 6]It is a schematic diagram showing a display device provided by an embodiment of the present application.

[0014] [Figure 7] It is a schematic diagram showing the configuration of a pixel driving circuit provided by an embodiment of the present application.

[0015] [Figure 8] It is a timing diagram corresponding to the pixel driving circuit provided by an embodiment of the present application.

[0016] [Figure 9] It is a schematic diagram showing the display principle of a high-frequency image and a low-frequency image provided by an embodiment of the present application.

Embodiments for Carrying Out the Invention

[0017] In order to make the object, technical solution and effect of the present application clearer and more definite, the present application will be further described in detail below with reference to the drawings and by way of examples. It should be understood that the specific embodiments described in this specification are only for the purpose of explaining the present application and are not intended to limit the present application.

[0018] This application provides a display drive circuit and a display device, the display drive circuit including a plurality of frequency division control lines and a plurality of gate drive circuits cascaded together, the plurality of frequency division control lines transmitting frequency division control signals to the plurality of gate drive circuits, each gate drive circuit including a node control module, a plurality of first output modules and at least one first frequency division module, the node control module controlling signals transmitted to the first and second nodes of the gate drive circuit of the current stage based on a corresponding first clock signal and a start signal, the first frequency division module controlling signal transmission between the first node and at least one first output module based on a frequency division control signal and the signal of the second node, each first output module outputting a first gate control signal based on a corresponding second clock signal, a frequency division control signal, and the signals of the first and second nodes, and the plurality of first output modules output a plurality of first gate control signals having a phase difference. By arranging each gate drive circuit to simultaneously include multiple first output modules, and the multiple first output modules to output multiple first gate control signals with a phase difference, the number of gate drive circuits included in the gate drive unit is reduced, and consequently, the layout space occupied by the gate drive unit is reduced.

[0019] Specifically, Figure 1 is a principle block diagram showing a display driving circuit provided by an embodiment of the present application. The present application provides a display driving circuit which includes a gate driving unit GM, which includes a plurality of frequency division control lines FL and a plurality of gate driving circuits GA cascaded together, the plurality of frequency division control lines FL transmitting a frequency division control signal FD to the plurality of gate driving circuits GA, and the plurality of gate driving circuits GA output a plurality of first gate control signals Pscan.

[0020] Figure 2 is a principle block diagram showing a gate drive circuit provided by an embodiment of the present invention. Each gate drive circuit GA includes a node control module 10, a plurality of first output modules 20, and at least one first frequency division module 30.

[0021] The node control module 10 is electrically connected to the first node K1 and the second node K2 of the gate drive circuit GA of the current stage, and the node control module 10 is configured to control the signals transmitted to the first node K1 and the second node K2 based on the corresponding first clock signal XCK and start signal STV.

[0022] Each first output module 20 is electrically connected to the first node K1 and the second node K2, and each first output module 20 is configured to output a first gate control signal Pscan based on the corresponding second clock signal CK, frequency division control signal FD, and signals from the first node K1 and the second node K2. Here, IN1 and INX both indicate input terminals on which the first output module 20 receives the second clock signal CK.

[0023] The first frequency division module 30 is electrically connected to the first node K1, the second node K2, and at least one first output module 20. The first frequency division module 30 is configured to control signal transmission between the first node K1 and the corresponding first output module 20 based on the frequency division control signal FD and the signal from the second node K2. Here, the multiple first output modules 20 are configured to output multiple first gate control signals Pscan having a phase difference.

[0024] By arranging each gate drive circuit GA to simultaneously include multiple first output modules 20, and the multiple first output modules 20 to output multiple first gate control signals Pscan having a phase difference, the number of gate drive circuits GA included in the gate drive unit GM is reduced, and consequently, the layout space occupied by the gate drive unit GM is reduced.

[0025] Optionally, each gate drive circuit GA includes X first output modules 20, and the phase difference of the first clock signal XCK corresponding to two adjacent stage gate drive circuit GAs is XH (as shown in Figures 5A to 5E below), so that each of the X first output modules 20 of each stage gate drive circuit GA can control the level of the first gate control signal Pscan within its corresponding effective level output period. That is, taking the gate drive circuit GA of the current stage and the gate drive circuit GA of the previous stage cascaded to the current stage gate drive circuit GA as an example, after the X first output modules 20 of the gate drive circuit GA of the previous stage cascaded to the current stage gate drive circuit GA have all output their corresponding first gate control signal Pscan, the X first output modules 20 of the gate drive circuit GA of the current stage finally begin to output their corresponding first gate control signal Pscan. Here, X ≥ 2 and H is the unit time length.

[0026] Optionally, each gate drive circuit GA is electrically connected to N clock lines, and these N clock lines transmit the corresponding first clock signal XCK and second clock signal CK to one gate drive circuit GA, where N = X + 1.

[0027] Optionally, the gate driver circuit GA includes two first output modules 20 (i.e., X=2), and the gate driver circuit GA is electrically connected to three clock lines (i.e., N=3), one of the three clock lines transmitting the corresponding first clock signal XCK to the gate driver circuit GA, and the other two of the three clock lines transmitting the corresponding second clock signal CK to the gate driver circuit GA.

[0028] Optionally, in order to make the phase difference of the first gate control signals Pscan output from multiple first output modules 20 in the same gate drive circuit GA the same, the phase difference between the second clock signal CK received by one first output module 20 and the first clock signal XCK corresponding to the gate drive circuit GA can be made equal to the minimum phase difference of the multiple second clock signals CK, while the phase difference between the second clock signal CK received by the other first output modules 20 and the first clock signal XCK corresponding to the gate drive circuit GA can be made greater than the minimum phase difference.

[0029] For example, if the gate drive circuit GA includes two first output modules 20 and the gate drive circuit GA corresponds to one first clock signal XCK and two second clock signals CK, then the phase difference between the two second clock signals CK is 1H (i.e., the minimum phase difference is 1H), and the phase difference between the second clock signal CK and the first clock signal XCK corresponding to one first output module 20 is also equal to 1H, while the phase difference between the second clock signal CK and the first clock signal XCK corresponding to the other first output module 20 is equal to 2H.

[0030] For example, if the gate drive circuit GA includes three first output modules 20 and the gate drive circuit GA corresponds to one first clock signal XCK and three second clock signals CK (i.e., the first sub-signal, the second sub-signal, and the third sub-signal), then the phase difference between the first sub-signal and the second sub-signal is 1H, the phase difference between the second sub-signal and the third sub-signal is 1H, and the phase difference between the third sub-signal and the first sub-signal is 2H. That is, the minimum phase difference of the multiple second clock signals CK is 1H, and the phase difference between the second clock signal CK and the first clock signal XCK corresponding to one first output module 20 is also equal to 1H, while the phase differences between the second clock signal CK and the first clock signal XCK corresponding to the other two first output modules 20 are 2H and 3H, respectively.

[0031] Optionally, a second clock signal CK received by one of the multiple first output modules 20 of the gate drive circuit GA has a phase difference equal to XH with the first clock signal XCK corresponding to the gate drive circuit GA, so that the phase difference of the first gate control signals Pscan of adjacent stages output from two adjacent gate drive circuit GAs matches the phase difference of the first gate control signals Pscan of adjacent stages output from the same gate drive circuit GA.

[0032] Optionally, the phase difference range between the second clock signal CK and the first clock signal XCK, received in relation to multiple first output modules 20, is xH to ​​XH. Here, x represents the minimum phase difference described above, and x > 0.

[0033] Optionally, the multi-stage gate drive circuit GA reduces the power consumption of the display drive circuit by transmitting clock signals via multiple clock lines as the corresponding first clock signal XCK and second clock signal CK.

[0034] Optionally, in the same gate drive circuit GA, the phase difference of the first gate control signal Pscan output from two first output modules 20 is RH, which corresponds to the phase difference interval of the first clock signal XCK applied to two adjacent gate drive circuits GA, and controls the X first output modules 20 in the same gate drive circuit GA to all output the first gate control signal Pscan. Here, 1 ≤ R <Xである。

[0035] For example, if the gate drive circuit GA includes two first output modules 20, the phase difference between the first gate control signals Pscan output from the two first output modules 20 is 1H.

[0036] For example, if the gate drive circuit GA includes three first output modules 20, and each of the three first output modules includes a first sub-output module, a second sub-output module, and a third sub-output module, then the phase difference of the first gate control signal Pscan output from the first sub-output module 201 and the second sub-output module 202 is 1H, the phase difference of the first gate control signal Pscan output from the second sub-output module 202 and the third sub-output module is 1H, and the phase difference of the first gate control signal Pscan output from the first sub-output module 201 and the third sub-output module is 2H.

[0037] Figures 3A to 3E are schematic diagrams showing the connections between the gate drive circuits and clock lines of multiple stages provided by the embodiment of the present invention. Here, IN1 to IN3 represent input terminals to which one first output module 20 receives the corresponding second clock signal CK, and XIN represents an input terminal to which the gate drive circuit GA receives the corresponding first clock signal XCK.

[0038] Optionally, each gate drive circuit GA includes X first output modules 20, and the gate drive circuits GA of multiple stages are electrically connected to Y clock lines, which transmit corresponding first clock signals XCK and second clock signals CK to the gate drive circuits GA of multiple stages, thereby causing the gate drive circuits GA to share the clock signals provided by the Y clock lines to control the output of multiple first gate control signals Pscan, where X≧2 and Y>X.

[0039] Optionally, by setting Y=2X, multiple gate drive circuits GA are combined with Y clock lines, thereby ensuring that the first gate control signal Pscan output from the gate drive circuits GA of multiple stages have the same phase difference sequentially.

[0040] When multiple clock lines are multiplexed to transmit corresponding first clock signals XCK and second clock signals CK to gate drive circuits GA at multiple stages, it is necessary to simultaneously provide both the first and second clock signals XCK and CK to the corresponding gate drive circuit GA for a given clock line, while for another clock line only the second clock signal CK is provided to the corresponding gate drive circuit GA. As a result, the loads corresponding to the multiple clock lines do not match, which may lead to differences in the output waveforms of the multiple clock signals. This can affect the uniformity of the quality of the first gate control signal Pscan output from the gate drive circuits GA at multiple stages.

[0041] To ensure that the first gate control signal Pscan output from the gate drive circuit GA of multiple stages has relatively good uniformity, the clock line may be independently configured to provide the first clock signal XCK to the gate drive circuit GA of multiple stages.

[0042] That is, each gate drive circuit GA includes X first output modules 20, and the gate drive circuits GA of multiple stages are electrically connected to multiple clock lines. Of the multiple clock lines, Z clock lines transmit the corresponding first clock signal XCK to the gate drive circuits GA of multiple stages, and Y clock lines transmit the corresponding second clock signal CK to the gate drive circuits GA of multiple stages. Here, X≧2, Z≧2, and Y>X.

[0043] Optionally, Z=2, so that the gate drive circuit GA for multiple stages shares the clock signal transmitted by two clock lines to form the corresponding first clock signal XCK.

[0044] Next, referring to Figure 3A, we will describe a design in which the corresponding first clock signal XCK and second clock signal CK are transmitted to the gate drive circuit GA of multiple stages using Y clock lines.

[0045] For example, each gate drive circuit GA can output two first output modules 20 (i.e., X=2) by including two first gate control signals Pscan. Accordingly, the Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Here, the first clock line CKL1 transmits the corresponding second clock signal CK to one first output module 20 in the gate drive circuit GA(2k+1) of the second k+1 stage, the second clock line CKL2 transmits the corresponding second clock signal CK to the other first output module 20 in the gate drive circuit GA(2k+1) of the second k+1 stage, the third clock line CKL3 transmits the corresponding second clock signal CK to one first output module 20 in the gate drive circuit GA(2k+2) of the second k+2 stage, and the fourth clock line CKL4 transmits the corresponding second clock signal CK to the other first output module 20 in the gate drive circuit GA(2k+2) of the second k+2 stage, so that the phase difference between the two first gate control signals Pscan output from each gate drive circuit GA is the same. Here, k≧0.

[0046] Continuing to refer to Figure 3A, the third clock line CKL3 transmits the corresponding first clock signal XCK to the gate drive circuit GA(2k+1) of the second k+1 stage, and the first clock line CKL1 transmits the corresponding first clock signal XCK to the gate drive circuit GA(2k+2) of the second k+2 stage. As a result, the phase difference between the first clock signals XCK corresponding to the gate drive circuits GA of two adjacent stages is XH, and consequently, the X first output modules 20 in each gate drive circuit GA can all efficiently output the first gate control signal Pscan.

[0047] Next, referring to Figure 3B, a design is described in which the corresponding first clock signal XCK is transmitted to the gate drive circuits GA of multiple stages using Z clock lines. Optionally, the Z clock lines include a fifth clock line CKL5 and a sixth clock line CKL6. Here, the fifth clock line CKL5 transmits the corresponding first clock signal XCK to the gate drive circuit GA(2k+1) of the 2k+1 stage, and the sixth clock line CKL6 transmits the corresponding first clock signal XCK to the gate drive circuit GA(2k+2) of the 2k+2 stage. As a result, the gate drive circuits GA of odd stages use the signal transmitted by the fifth clock line CKL5 to form the first clock signal XCK, and the gate drive circuits GA of even stages use the signal transmitted by the sixth clock line CKL6 to form the first clock signal XCK. Consequently, the loads corresponding to the Z clock lines and Y clock lines are close together, and the quality of the first gate control signal Pscan output from the gate drive circuits GA of multiple stages is matched.

[0048] The inventor performed a simulation verification of the design configuration shown in Figure 3B, and the simulation results showed that providing the first clock signal XCK to the gate drive circuit GA of multiple stages using independent clock lines reduces the load deviation to less than 10% and ensures that the quality of the first gate control signal Pscan output from the gate drive circuit GA of multiple stages is consistent.

[0049] For example, Figures 3C to 3E show a design in which, when each gate drive circuit GA includes three corresponding first output modules 20 (for example, the three first output modules 20 include a first sub-output module, a second sub-output module, and a third sub-output module), the corresponding first clock signal XCK and second clock signal CK are transmitted to the gate drive circuits GA of multiple stages using Y clock lines. That is, the Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a seventh clock line CKL7, and an eighth clock line CKL8.

[0050] Continuing with Figure 3C, the first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage, the second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage, and the third clock line CKL3 transmits the corresponding second clock signal CK to the third sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage. The fourth clock line CKL4 transmits the corresponding second clock signal CK to the first sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage, the seventh clock line CKL7 transmits the corresponding second clock signal CK to the second sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage, and the eighth clock line CKL8 transmits the corresponding second clock signal CK to the third sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage.

[0051] Continuing to refer to Figure 3D, the seventh clock line CKL7 transmits the corresponding second clock signal CK to the first sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage, the eighth clock line CKL8 transmits the corresponding second clock signal CK to the second sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage, and the first clock line CKL1 transmits the corresponding second clock signal CK to the third sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage. The second clock line CKL2 transmits the corresponding second clock signal CK to the first sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage; the third clock line CKL3 transmits the corresponding second clock signal CK to the second sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage; and the fourth clock line CKL4 transmits the corresponding second clock signal CK to the third sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage.

[0052] Continuing with Figure 3E, the eighth clock line CKL8 transmits the corresponding second clock signal CK to the first sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage, the first clock line CKL1 transmits the corresponding second clock signal CK to the second sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage, and the second clock line CKL2 transmits the corresponding second clock signal CK to the third sub-output module in the gate drive circuit GA(2k+1) of the second k+1 stage. The third clock line CKL3 transmits the corresponding second clock signal CK to the first sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage; the fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage; and the seventh clock line CKL7 transmits the corresponding second clock signal CK to the third sub-output module in the gate drive circuit GA(2k+2) of the second k+2 stage.

[0053] Here, the period of the clock signal transmitted by the Y clock lines is EH (as shown in Figures 5A to 5E described later), E=2X, and the phase difference between two adjacent clock signal lines of the Y clock lines is equal. Using the design shown in Figures 3C to 3D, the phase difference between the first gate control signals Pscan output from the first sub-output module and the second sub-output module of the same gate drive circuit GA is equal to the phase difference between the first gate control signals Pscan output from the second sub-output module and the third sub-output module. Furthermore, the phase difference between the first gate control signals Pscan output by the first sub-output module of adjacent two-stage gate drive circuit GA is equal to XH, the phase difference between the first gate control signals Pscan output by the second sub-output module of adjacent two-stage gate drive circuit GA is equal to XH, and the phase difference between the first gate control signals Pscan output by the third sub-output module of adjacent two-stage gate drive circuit GA is equal to XH.

[0054] For example, the period of the clock signals transmitted by Y clock lines is FH, the phase difference between the clock signal transmitted by the first clock line CKL1 and the clock signal transmitted by the second clock line CKL2 is 1H, the phase difference between the clock signal transmitted by the second clock line CKL2 and the clock signal transmitted by the third clock line CKL3 is 1H, the phase difference between the clock signal transmitted by the third clock line CKL3 and the clock signal transmitted by the fourth clock line CKL4 is 1H, and the phase difference between the clock signal transmitted by the fourth clock line CKL4 and the clock signal transmitted by the seventh clock line CKL7 is The phase difference between the clock signal transmitted by the 7th clock line CKL7 and the clock signal transmitted by the 8th clock line CKL8 is 1H, and the phase difference between the clock signal transmitted by the 8th clock line CKL8 and the clock signal transmitted by the 1st clock line CKL1 is 1H. By using the design shown in Figures 3C to 3D, the phase difference between the first gate control signals Pscan output from the 1st sub-output module and the 2nd sub-output module in the same gate drive circuit GA can be set to 1H, and the phase difference between the first gate control signals Pscan output from the 2nd sub-output module and the 3rd sub-output module can be set to 1H. Furthermore, the phase difference between the first gate control signals Pscan output from the 1st sub-output module in adjacent two-stage gate drive circuits GA is equal to 3H, the phase difference between the first gate control signals Pscan output from the 2nd sub-output module in adjacent two-stage gate drive circuits GA is equal to 3H, and the phase difference between the first gate control signals Pscan output from the 3rd sub-output module in adjacent two-stage gate drive circuits GA is equal to 3H.

[0055] Optionally, each gate drive circuit GA includes three corresponding first output modules 20, and if Y clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, a fourth clock line CKL4, a seventh clock line CKL7, and an eighth clock line CKL8, then the fourth clock line CKL4 transmits the corresponding first clock signal XCK to the gate drive circuit GA(2k+1) of the second k+1 stage, and the first clock line CKL1 transmits the corresponding first clock signal XCK to the gate drive circuit GA(2k+2) of the second k+2 stage, thereby enabling each of the X first output modules 20 in the gate drive circuit GA of each stage to efficiently output the first gate control signal Pscan.

[0056] Optionally, if each gate driver circuit GA includes three corresponding first output modules 20, the fifth clock line CKL5 transmits the corresponding first clock signal XCK to the second k+1 stage gate driver circuit GA(2k+1), and the sixth clock line CKL6 transmits the corresponding first clock signal XCK to the second k+2 stage gate driver circuit GA(2k+2), thereby ensuring that the loads corresponding to multiple clock lines are close together and that the quality of multiple first gate control signals Pscan is consistent.

[0057] Optionally, when multiple gate drive circuits GA multiplex clock signals provided by multiple clock lines, if the period of the clock signal provided by each clock line is EH, then the number X of first output modules 20 included in each gate drive circuit GA is less than E, and thereafter, each first output module 20 in each gate drive circuit GA can effectively output the first gate control signal Pscan. Here, E ≥ 2.

[0058] Optionally, the upper limit of the number of first output modules 20 included in each gate drive circuit GA is E-1, such that each first output module 20 in the same gate drive circuit GA effectively outputs the first gate control signal Pscan. That is, a gate drive circuit GA can contain 2 to E-1 (i.e., X = 2 to E-1) first output modules 20.

[0059] Figure 4 is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present application. In Figure 4, only an example is shown in which a one-stage gate drive circuit GA includes two first output modules 20, and it is not intended to limit the number of first output modules 20 included in the gate drive circuit GA to two. Here, in Figure 4, p≧1 and q≧1.

[0060] Continuing with Figure 4, each first output module 20 includes a first output transistor To1, a second output transistor To2, and a first capacitor C1.

[0061] The control terminal of the first output transistor To1 is electrically connected to the corresponding first frequency division module 30, the input terminal of the first output transistor To1 is configured to receive the corresponding second clock signal CK, and the output terminal of the first output transistor To1 is electrically connected to the first output terminal Pout, which outputs the first gate control signal Pscan of the gate drive circuit GA of the current stage.

[0062] The control terminal of the second output transistor To2 is electrically connected to the second node K2, the input terminal of the second output transistor To2 is electrically connected to the first power supply terminal PVGH, and the output terminal of the first output transistor To1 is electrically connected to the corresponding first output terminal Pout.

[0063] The first terminal of the first capacitor C1 is electrically connected to the control terminal of the first output transistor To1, and the second terminal of the first capacitor C1 is electrically connected to the corresponding first output terminal Pout.

[0064] Continuing with Figure 4, at least one first output module 20 includes a first switching transistor Ts1, the control terminal of the first switching transistor Ts1 is electrically connected to the second node K2 of the gate drive circuit GA of the previous stage, the input terminal of the first switching transistor Ts1 is electrically connected to the corresponding first frequency division module 30, and the output terminal of the first switching transistor Ts1 is electrically connected to the control terminal of the corresponding first output transistor To1.

[0065] Optionally, the switching control signal SC received by the control terminal of the 11th transistor T11 in the first-stage gate drive circuit GA(1) to the second-stage gate drive circuit GA(2) corresponds to the low-level signal VGL, and the control terminal of the 11th transistor T11 in each stage gate drive circuit GA located after the second-stage gate drive circuit GA(2) is electrically connected to the second node K2 of the preceding two stages' gate drive circuits GA (for example, as shown in Figures 3A to 3E, the control terminal of the 11th transistor T11 in the p-th stage gate drive circuit GA(p) is electrically connected to the second node K2(p-2) of the p-2 stage gate drive circuit GA(p-2)).

[0066] Optionally, in the same gate drive circuit GA, the switching control signals SC corresponding to multiple first switching transistors Ts1 may be the same, thereby reducing the complexity of the control.

[0067] Optionally, in the same gate drive circuit GA, the switching control signals SC corresponding to multiple first switching transistors Ts1 may be different, thereby allowing the timing at which each first output module 20 outputs the first gate control signal Pscan in the same gate drive circuit GA to be controlled independently.

[0068] Optionally, in order to ensure that the first gate control signals Pscan output from multiple first output modules 20 in the same gate drive circuit GA have similar characteristics, the design parameters for the first output transistor To1 (e.g., aspect ratio and dimensions of the transistor channel) of multiple first output modules 20 in the same gate drive circuit GA are made the same, the design parameters for the second output transistor To2 of multiple first output modules 20 in the same gate drive circuit GA are made the same, the design parameters for the first capacitor C1 (e.g., dimensions and capacitance) of multiple first output modules 20 in the same gate drive circuit GA are made the same, and the design parameters for the first switching transistor Ts1 of multiple first output modules 20 in the same gate drive circuit GA are made the same.

[0069] Referring to Figure 2, at least one gate drive circuit GA includes a first control module 40, which is configured to control signal transmission between a first power supply terminal PVGH and at least one first output module 20 based on the corresponding first clock signal XCK and the potential of a second node K2.

[0070] Continuing with Figure 4, the first control module 40 includes a second switching transistor Ts2 and a third switching transistor Ts3.

[0071] The control terminal of the second switching transistor Ts2 receives the corresponding first clock signal XCK, and the input terminal of the second switching transistor Ts2 is electrically connected to the input terminal of at least one first switching transistor Ts1.

[0072] The control terminal of the third switching transistor Ts3 is electrically connected to the second node K2, the input terminal of the third switching transistor Ts3 is electrically connected to the first power supply terminal PVGH, and the output terminal of the third switching transistor Ts3 is electrically connected to the output terminal of the second switching transistor Ts2.

[0073] Continuing with Figure 4, the first frequency division module 30 includes a first frequency division transistor Tf1, a second frequency division transistor Tf2, and a second capacitor C2.

[0074] The control terminal of the first frequency division transistor Tf1 is electrically connected to the second node K2 of the gate drive circuit of the current stage, and the input terminal of the first frequency division transistor Tf1 is electrically connected to the corresponding frequency division control line FL.

[0075] The control terminal of the second frequency division transistor Tf2 is electrically connected to the output terminal of the first frequency division transistor Tf1, the input terminal of the second frequency division transistor Tf2 is electrically connected to the first node K1, and the output terminal of the second frequency division transistor Tf2 is electrically connected to the corresponding first output module 20.

[0076] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the second frequency division transistor Tf2, and the second terminal of the second capacitor C2 is electrically connected to the output terminal of the second frequency division transistor Tf2.

[0077] Multiple frequency division control lines FL include a first frequency division control line FL1, and the input terminals of the first frequency division transistor Tf1 in multiple gate drive circuits GA are electrically connected to the first frequency division control line FL1, thereby reducing the number of frequency division control lines FL used by the gate drive unit GM.

[0078] Optionally, one first frequency division module 30 is provided for each first output module 20 so that each first output module 20 controls the level of the first gate control signal Pscan output by the corresponding first frequency division module 30. Accordingly, different frequency division control signals are used for each first output module 20 so that the levels of the first gate control signal Pscan output from each first output module 20 in the same gate drive circuit GA can be controlled independently.

[0079] For example, the gate drive circuit GA includes two first output modules 20 and two first frequency division modules 30. The two first output modules 20 include a first sub-output module 201 and a second sub-output module 202, and the two first frequency division modules 30 include a first sub-frequency division module and a second sub-frequency division module. Here, the first sub-frequency division module is configured to control the level of the first gate control signal Pscan output from the first sub-output module 201, and the second sub-frequency division module is configured to control the level of the first gate control signal Pscan output from the second sub-output module 202. As a result, the first sub-frequency division modules in the multi-stage gate drive circuit GA can be connected to one frequency division control line FL, and the second sub-frequency division modules in the multi-stage gate drive circuit GA can be connected to another frequency division control line FL.

[0080] To further reduce the layout space occupied by the display drive circuit, the same gate drive circuit GA can output a second gate control signal Nscan in addition to multiple first gate control signals Pscan with phase differences, thereby expanding the application range of the gate drive unit GM.

[0081] Referring again to Figure 2, each gate drive circuit GA further includes a second output module 50 and a second frequency division module 60.

[0082] The second output module 50 is electrically connected to the first node K1, and the second output module 50 is configured to output a second gate control signal Nscan based on the corresponding frequency division control signal and the signal from the first node K1.

[0083] The second frequency division module 60 is electrically connected to the first node K1, the second node K2, and the second output module 50, and the second frequency division module 60 is configured to control signal transmission between the first node K1 and the second output module 50 based on the corresponding frequency division control signal and the signal from the second node K2.

[0084] Optionally, referring to Figure 4, the second frequency division module 60 includes a third frequency division transistor Tf3, a fourth frequency division transistor Tf4, and a third capacitor C3.

[0085] The control terminal of the third frequency division transistor Tf3 is electrically connected to the second node K2, and the input terminal of the third frequency division transistor Tf3 is electrically connected to the corresponding frequency division control line FL.

[0086] The control terminal of the fourth frequency division transistor Tf4 is electrically connected to the output terminal of the third frequency division transistor Tf3, the input terminal of the fourth frequency division transistor Tf4 is electrically connected to the first node K1, and the output terminal of the fourth frequency division transistor Tf4 is electrically connected to the corresponding second output module 50.

[0087] The first terminal of the third capacitor C3 is electrically connected to the control terminal of the fourth frequency division transistor Tf4, and the second terminal of the third capacitor C3 is electrically connected to the output terminal of the fourth frequency division transistor Tf4.

[0088] Optionally, in order to reduce the number of frequency division control lines FL used by the gate drive unit GM and to achieve independent control of the level states of the first gate control signal Pscan and the second gate control signal Nscan output from the gate drive unit GM, the first frequency division module 30 and the second frequency division module 60 in the same gate drive circuit GA provide corresponding frequency division control signals using different frequency division control lines FL.

[0089] In other words, the multiple frequency division control lines FL include a second frequency division control line FL2, and the input terminals of the third frequency division transistor Tf3 in the multiple gate drive circuits GA are electrically connected to the second frequency division control line FL2.

[0090] Continuing to refer to Figure 4, the second output module 50 includes a third output transistor To3 and a fourth output transistor To4.

[0091] The control terminal of the third output transistor To3 is electrically connected to the output terminal of the fourth frequency division transistor Tf4, the input terminal of the third output transistor To3 is electrically connected to the second power supply terminal NVGH, and the output terminal of the third output transistor To3 is electrically connected to the second output terminal Nout, which outputs the second gate control signal Nscan of the gate drive circuit GA of the current stage.

[0092] The control terminal of the fourth output transistor To4 is electrically connected to the first node K1, the input terminal of the fourth output transistor To4 is electrically connected to the third power supply terminal NVGL, and the output terminal of the fourth output transistor To4 is electrically connected to the second output terminal Nout.

[0093] Optionally, continuing with reference to Figure 2, at least one gate drive circuit GA includes a second control module 70, which is configured to control signal transmission between the first power supply terminal PVGH and the second output module 50 based on the corresponding first clock signal XCK and the potential of the second node K2.

[0094] Optionally, referring to Figure 4, the second control module 70 includes a fourth switching transistor Ts4 and a fifth switching transistor Ts5.

[0095] The control terminal of the fourth switching transistor Ts4 receives the corresponding first clock signal XCK, and the input terminal of the fourth switching transistor Ts4 is electrically connected to the input terminal of the third output transistor To3.

[0096] The control terminal of the fifth switching transistor Ts5 is electrically connected to the second node K2, the input terminal of the fifth switching transistor Ts5 is electrically connected to the first power supply terminal PVGH, and the output terminal of the fifth switching transistor Ts5 is electrically connected to the output terminal of the fourth switching transistor Ts4.

[0097] Continuing to refer to Figure 4, the node control module 10 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0098] The control terminal of the first transistor T1 is configured to receive the corresponding start signal STV, and the input terminal of the first transistor T1 is electrically connected to the third power supply terminal NVGL or the fourth power supply terminal PVGL.

[0099] The control terminal of the second transistor T2 is electrically connected to the first control terminal of the first transistor T1, the input terminal of the second transistor T2 is electrically connected to the first power supply terminal PVGH, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1.

[0100] The control terminal of the third transistor T3 is positioned to receive the corresponding first clock signal XCK, the input terminal of the third transistor T3 is electrically connected to the output terminal of the first transistor T1, and the output terminal of the third transistor T3 is electrically connected to the first node K1.

[0101] The control terminal of the fourth transistor T4 is electrically connected to the first node K1, the input terminal of the fourth transistor T4 is electrically connected to the fourth power supply terminal PVGL, and the output terminal of the fourth transistor T4 is electrically connected to the second node K2.

[0102] The control terminal of the fifth transistor T5 is electrically connected to the first node K1, the input terminal of the fifth transistor T5 is electrically connected to the first power supply terminal PVGH, and the output terminal of the fifth transistor T5 is electrically connected to the second node K2.

[0103] The control terminal of the sixth transistor T6 is electrically connected to the second node K2, the input terminal of the sixth transistor T6 is electrically connected to the third power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node K1.

[0104] Optionally, as shown in Figures 3A to 3E, the first stage gate drive circuit GA(1) among the multiple gate drive circuits GA uses the initial signal stv as the start signal STV, and is configured to control the signal transmitted to the first node K1 based on the corresponding first clock signal XCK and the initial signal stv.

[0105] Optionally, the nth-th stage gate drive circuit GA(n) among multiple gate drive circuits GA(n) is configured to use the nth-th stage second gate control signal Nscan(nA), output from the nA-th stage gate drive circuit GA(nA), as its start signal STV. Thereafter, the nth-th stage gate drive circuit GA(n) is configured to control the signal transmitted to the first node K1 of the nth-th stage gate drive circuit GA(n) based on the corresponding first clock signal XCK and the nA-th stage second gate control signal Nscan(nA), output from the nA-th stage gate drive circuit GA(nA). Here, n>1 and A≧1.

[0106] Optionally, to reduce the load corresponding to the second output terminal Nout of the gate drive circuit GA, the nth-stage gate drive circuit GA(n) among the multiple gate drive circuits GA controls the signal transmitted to the first node K1 of the nth-stage gate drive circuit GA(n) based on the corresponding first clock signal XCK and the potential of the second node K2 of the nA-stage gate drive circuit GA(nA). As shown in Figure 4, the p-th-stage gate drive circuit GA(n) controls the signal transmitted to the first node K1 of the p-th-stage gate drive circuit GA(p) based on the corresponding first clock signal XCK and the potential of the second node K2(p-1) of the p-1-stage gate drive circuit GA(p-1).

[0107] Optionally, referring to Figure 4, the node control module 10 includes a seventh transistor T7 and an eighth transistor T8.

[0108] The control terminal of the seventh transistor T7 is configured to receive the corresponding first clock signal XCK, and the output terminal of the seventh transistor T7 is electrically connected to the first node K1.

[0109] The control terminal of the 8th transistor T8 is electrically connected to the 2nd node K2, the input terminal of the 8th transistor T8 is electrically connected to the 1st power supply terminal PVGH, and the output terminal of the 8th transistor T8 is electrically connected to the input terminal of the 7th transistor T7.

[0110] Optionally, continuing to refer to Figure 4, at least one gate drive circuit GA further includes a reset module 80, which is electrically connected to a first node K1, and is configured to control signal transmission between a first power terminal PVGH and the first node K1 based on a reset control signal Ctl.

[0111] Optionally, the reset module includes a reset transistor Tre, the control terminal of the reset transistor Tre is configured to receive a reset control signal Ctl, the input terminal of the reset transistor Tre is electrically connected to the first power supply terminal PVGH, and the output terminal of the reset transistor Tre is electrically connected to the first node K1.

[0112] Optionally, if the gate drive unit GM is used in the display device, the reset module 80 is configured to be activated when the display device is started and / or during the blank interval period.

[0113] To make it easier to understand, each transistor included in the gate drive circuit GA may be either a P-type transistor or an N-type transistor. The semiconductor material of each transistor included in the gate drive circuit GA may be either a silicon semiconductor or an oxide semiconductor.

[0114] Optionally, in some embodiments, at least one of the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the second switching transistor Ts2, the fourth switching transistor Ts4, and the fourth output transistor To4 has correspondingly only one or two control terminals.

[0115] Optionally, in some embodiments, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the second switching transistor Ts2, the fourth switching transistor Ts4, and the fourth output transistor To4 are N-type transistors, while the other transistors are P-type transistors.

[0116] Optionally, in some embodiments, the voltage corresponding to the fourth power terminal PVGL is lower than the voltage corresponding to the first power terminal PVGH, and the voltage of the third power terminal NVGL is lower than the voltage corresponding to the second power terminal NVGH.

[0117] Figures 5A to 5E are timing diagrams corresponding to the gate drive circuit GA provided by the embodiment of the present application. The second transistor T2, third transistor T3, fifth transistor T5, eighth transistor T8, first switching transistor Ts1, third switching transistor Ts3, fifth switching transistor Ts5, first frequency division transistors Tf1 to fourth frequency division transistors Tf4, and first output transistors To1 to third output transistors To3 are P-type transistors, and the first transistor T1, fourth transistor T4, sixth transistor T6, seventh transistor T7, second switching transistor Ts2, fourth switching transistor Ts4, and fourth output transistor To4 are N-type transistors. The multi-stage gate drive circuit GA includes two first output modules 20, and the two first output modules 20 are connected to one first frequency division module. 30 is shared, and the two first output modules 20 include a first sub-output module 201 and a second sub-output module 202. A third clock line CKL3 transmits the corresponding second clock signal CK to the first sub-output module 201 in the p-th stage gate drive circuit GA(p). A fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module 202 in the p-th stage gate drive circuit GA(p). A first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module 201 in the p+1-th stage gate drive circuit GA(p+1). A second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module 202 in the p+1-th stage gate drive circuit GA(p+1). The first clock line CKL1 or the sixth clock line CKL6 transmits the corresponding first clock signal XCK to the p-th stage gate drive circuit GA(p), the third clock line CKL3 or the fifth clock line CKL5 transmits the corresponding first clock signal XCK to the p+1-th stage gate drive circuit GA(p+1), and the operating principle of the gate drive unit GM will be explained using the design shown in Figure 3A or Figure 3B as an example, where the gate drive circuits GA of multiple stages use the design shown.Here, the second output module 50 of the p-th stage gate drive circuit GA outputs the second gate control signal Nscan(p) of the p-th stage, the first sub-output module 201 of the p-th stage gate drive circuit GA outputs the first gate control signal Pscan(q) of the q-th stage, and the second sub-output module 202 of the p-th stage gate drive circuit GA outputs the first gate control signal Pscan(q+1) of the q+1-th stage, where p≧1 and q=2p-1.

[0118] Continuing with reference to Figures 3A-3B, 4, and 5A, in the first stage t1, the first clock signal CK1 transmitted by the first clock line CKL1 and the sixth clock signal CK6 transmitted by the sixth clock line CKL6 are at a low level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a high level, the third clock signal CK3 transmitted by the third clock line CKL3 and the fifth clock signal CK5 transmitted by the fifth clock line CKL5 are at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage and the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a high level. The first frequency division control signal FD1 transmitted by the first frequency division control line FL1 and the second frequency division control signal FD2 transmitted by the second frequency division control line FL2 are at a low level.

[0119] In the p-stage gate drive circuit GA(p), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the third output transistor To3, the second frequency division transistor Tf2, and the fourth frequency division transistor Tf4 are turned on, while the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The second gate control signal Nscan(p) of the p-stage, the first gate control signal Pscan(q) of the q-stage, and the first gate control signal Pscan(q+1) of the q+1-stage have high levels.

[0120] In the p+1 stage gate drive circuit GA(p+1), the first transistor T1 is turned on, the third transistor T3 is turned off, the second gate control signal Nscan(p+1) of the p+1 stage remains at a low level, and the first gate control signal Pscan(q+2) of the q+2 stage and the first gate control signal Pscan(q+3) of the q+3 stage remain at a high level. In the p+2 stage gate drive circuit GA(p+2), the second transistor T2 is turned on, the third transistor T3 is turned off, the second gate control signal Nscan(p+2) of the p+2 stage remains at a low level, and the first gate control signal Pscan(q+4) of the q+4 stage and the first gate control signal Pscan(q+5) of the q+5 stage remain at a high level. The second gate control signals Nscan(p+2) in the p+3 stage to Nscan(p+6) in the p+6 stage remain at a low level, while the first gate control signals Pscan(q+6) in the q+6 stage to Pscan(q+13) in the q+13 stage remain at a high level.

[0121] In the second stage t2, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a low level, and the fourth clock signal CK4 is at a high level. The second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a high level. The first frequency division control signal FD1 and the second frequency division control signal FD2 are at a low level.

[0122] In the p-stage gate drive circuit GA(p), the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the third output transistor To3, the second frequency division transistor Tf2, the fourth frequency division transistor Tf4, the second switching transistor Ts2, and the fourth switching transistor Ts4 are turned on, while the second transistor T2, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the first switching transistor Ts1, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The second gate control signal Nscan(p) of the p-stage, the first gate control signal Pscan(q) of the q-stage, and the first gate control signal Pscan(q+1) of the q+1-stage have high levels.

[0123] In the second stage t2, the gate drive circuit GA(p+1) of the p+1 stage performs an operation similar to that performed by the gate drive circuit GA(p) of the p stage in the first stage t1. Similarly, the gate drive circuit GA(p+2) of the p+2 stage performs an operation similar to that performed by the gate drive circuit GA(p+1) of the p+1 stage in the first stage t1 in the second stage t2. In the same way, the gate drive circuits GA(p+3) to GA(p+6) of the p+3 stage perform the operation that was performed in the second stage t2.

[0124] In the third stage t3, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a low level, and the fourth clock signal CK4 is at a high level. The second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level. The first frequency division control signal FD1 and the second frequency division control signal FD2 are at a low level.

[0125] In the p-stage gate drive circuit GA(p), the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first switching transistor Ts1, the second switching transistor Ts2, the fourth switching transistor Ts4, the second frequency division transistor Tf2, the fourth frequency division transistor Tf4, the third output transistor To3, and the first output transistor To1 are turned on, while the first transistor T1, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth output transistor To4, and the second output transistor To2 are turned off. The second gate control signal Nscan(p) of the p-stage and the first gate control signal Pscan(q+1) of the q+1 stage have a high level, and the first gate control signal Pscan(q) of the q-stage have a low level.

[0126] In the p+1 stage gate drive circuit GA(p+1), the first transistor T1, the third transistor T3, and the first switching transistor Ts1 are turned on. As a result, the first output transistor To1 and the third output transistor To3 are turned on, and the second gate control signal Nscan(p+1) of the p+1 stage, the first gate control signal Pscan(q+2) of the q+2 stage, and the first gate control signal Pscan(q+3) of the q+3 stage remain at a high level.

[0127] In the third stage t3, the p+2 stage gate drive circuit GA(p+2) performs an operation similar to that performed by the p stage gate drive circuit GA(p) in the second stage t2. Similarly, in the third stage t3, the p+3 stage gate drive circuit GA(p+3) performs an operation similar to that performed by the p+1 stage gate drive circuit GA(p+1) in the second stage t2. In the same way, the gate drive circuits GA(p+3) through p+6 stages perform the operation that was performed in the second stage t2.

[0128] In the fourth stage t4, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a high level, the fourth clock signal CK4 is at a low level, the second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level, and the first frequency division control signal FD1 and the second frequency division control signal FD2 are at a low level.

[0129] In the p-stage gate drive circuit GA(p), the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the first switching transistor Ts1, the second switching transistor Ts2, the fourth switching transistor Ts4, the second frequency division transistor Tf2, the fourth frequency division transistor Tf4, the third output transistor To3, and the first output transistor To1 are turned on, while the first transistor T1, the third transistor T3, the fourth transistor T4, the eighth transistor T8, the third switching transistor Ts3, the fifth switching transistor Ts5, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth output transistor To4, and the second output transistor To2 are turned off. The second gate control signal Nscan(p) of the p-stage and the first gate control signal Pscan(q) of the q-stage have a high level, and the first gate control signal Pscan(q+1) of the q+1-stage have a low level.

[0130] In the p+1 stage gate drive circuit GA(p+1), the second transistor T2 and the third transistor T3 are turned off, the first output transistor To1 and the third output transistor To3 are turned on, and the second gate control signal Nscan(p+1) of the p+1 stage, the first gate control signal Pscan(q+2) of the q+2 stage, and the first gate control signal Pscan(q+3) of the q+3 stage remain at a high level.

[0131] In the p+2 stage gate drive circuit GA(p+2) and the p+3 stage gate drive circuit GA(p+3), the second transistor T2, the third transistor T3, and the first output transistor To1 are turned off, and the third output transistor To3 is turned on, so that the second gate control signal Nscan(p+2) in the p+2 stage to the second gate control signal Nscan(p+3) in the p+3 stage, and the first gate control signal Pscan(q+4) in the q+4 stage to the first gate control signal Pscan(q+7) in the q+7 stage remain at a high level.

[0132] In the gate drive circuits GA(p+2) of the p+4th stage to GA(p+3) of the p+6th stage, the third transistor T3 is turned off, the second output transistor To2 and the fourth output transistor To4 are turned on, and the second gate control signals Nscan(p+4) of the p+4th stage to Nscan(p+6) of the p+6th stage, and the first gate control signals Pscan(q+8) of the q+8th stage to Pscan(q+13) of the q+13th stage remain at a high level.

[0133] In the fifth stage t5, the first clock signal CK1 and the sixth clock signal CK6 are at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a high level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level, and the first frequency division control signal FD1 and the second frequency division control signal FD2 are at a low level.

[0134] In the p-stage gate drive circuit GA(p), the second transistor T2, third transistor T3, fourth transistor T4, eighth transistor T8, first switching transistor Ts1, third switching transistor Ts3, fifth switching transistor Ts5, second output transistor To2, fourth output transistor To4, and first to fourth frequency division transistors Tf1 to Tf4 are turned on. The first transistor T1, fifth transistor T5, sixth transistor T6, seventh transistor T7, second switching transistor Ts2, fourth switching transistor Ts4, first output transistor To1, and third output transistor To3 are turned off. The second gate control signal Nscan(p) of the p-stage has a low level, and the first gate control signal Pscan(q) of the q-stage and the first gate control signal Pscan(q+1) of the q+1-stage have high levels.

[0135] The gate drive circuit GA(p+1) in the (p+1)th stage performs an operation similar to that of the gate drive circuit GA(p) in the (p)th stage in the (3)th stage in the (3)th stage in the (5)th stage in the (5)th stage in the (5)th stage in the (5)th stage in the (5)th stage in the (5)th stage in the (6)th stage in the (1)th stage in the (5

[0136] In the sixth stage t6, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 and the fifth clock signal CK5 are at a high level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) of the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) of the p-2 stage are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0137] In the p-stage gate drive circuit GA(p), the third transistor T3 is turned off, the second gate control signal Nscan(p) of the p-stage is at a low level, and the first gate control signal Pscan(q) of the q-stage and the first gate control signal Pscan(q+1) of the q+1-stage are at a high level.

[0138] In the sixth stage t6, the gate drive circuit GA(p+1) of the p+1 stage performs an operation similar to that performed by the gate drive circuit GA(p) of the p stage in the fourth stage t4. In the sixth stage t6, the gate drive circuit GA(p+2) of the p+2 stage performs an operation similar to that performed by the gate drive circuit GA(p+1) of the p+1 stage in the fourth stage. In the sixth stage t6, the gate drive circuit GA(p+3) of the p+3 stage performs an operation similar to that performed by the gate drive circuit GA(p+2) of the p+2 stage in the fourth stage t4. In the sixth stage t6, the gate drive circuit GA(p+4) of the p+3 stage performs an operation similar to that performed by the gate drive circuit GA(p+3) of the p+3 stage in the fourth stage t4.

[0139] In the p+5 stage gate drive circuit GA(p+5), the first transistor T1, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the second switching transistor Ts2, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the third switching transistor Ts3, the second output transistor To2, the fourth output transistor To4, the first frequency division transistor Tf1, the third frequency division transistor Tf3, and the fourth frequency division transistor Tf4 are turned on. The second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the first switching transistor Ts1, the second frequency division transistor Tf2, the first output transistor To1, and the third output transistor To3 are turned off. The second gate control signal Nscan(p+5) of the p+5 stage has a low level, and the first gate control signal Pscan(q+10) of the q+10 stage and the first gate control signal Pscan(q+11) of the q+11 stage have high levels.

[0140] In the p+6th stage gate drive circuit GA(p+6), the second transistor T2, the second output transistor To2, and the fourth output transistor To4 are turned on, while the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The second gate control signal Nscan(p+6) of the p+6th stage has a low level, and the first gate control signal Pscan(q+12) of the q+12th stage and the first gate control signal Pscan(q+13) of the q+13th stage have high levels.

[0141] In the seventh stage t7, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a low level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0142] In the p-stage gate drive circuit GA(p), the third transistor T3 is turned off, the second gate control signal Nscan(p) of the p-stage is at a low level, and the first gate control signal Pscan(q) of the q-stage and the first gate control signal Pscan(q+1) of the q+1-stage are at a high level.

[0143] In the seventh stage t7, the p+1 stage gate drive circuit GA(p+1) performs an operation similar to that performed by the p stage gate drive circuit GA(p) in the fifth stage t5. In the seventh stage t7, the p+2 stage gate drive circuit GA(p+2) performs an operation similar to that performed by the p+1 stage gate drive circuit GA(p+1) in the fifth stage t5. In the fifth stage t5, the p+3 stage gate drive circuit GA(p+3) performs an operation similar to that performed by the p+2 stage gate drive circuit GA(p+2) in the fifth stage t5. In the seventh stage t7, the p+4 stage gate drive circuit GA(p+4) performs an operation similar to that performed by the p+3 stage gate drive circuit GA(p+3) in the fifth stage t5.

[0144] In the p+5 stage gate drive circuit GA(p+5), the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the fourth frequency division transistor Tf4, and the third output transistor To3 are turned on, while the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the first frequency division transistors Tf1 to the third frequency division transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off. The second gate control signal Nscan(p+5) of the p+5 stage, the first gate control signal Pscan(q+10) of the q+10 stage, and the first gate control signal Pscan(q+11) of the q+11 stage have high levels.

[0145] In the p+6th stage gate drive circuit GA(p+6), the first transistor T1, the second output transistor To2, and the fourth output transistor To4 are turned on, while the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The second gate control signal Nscan(p+6) of the p+6th stage has a low level, and the first gate control signal Pscan(q+12) of the q+12th stage and the first gate control signal Pscan(q+13) of the q+13th stage have high levels.

[0146] In the eighth stage t8, the first clock signal CK1 and the sixth clock signal CK6 are at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a high level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0147] The second gate control signals Nscan(p) in the p-th stage to Nscan(p+4) in the p+4th stage have a low level, and the first gate control signals Pscan(q+1) in the q+1st stage to Pscan(q+9) in the q+9th stage have a high level.

[0148] In the p+5 stage gate drive circuit GA(p+5), the second transistor T2, fifth transistor T5, sixth transistor T6, seventh transistor T7, first switching transistor Ts1, second switching transistor Ts2, fourth switching transistor Ts4, and third output transistor To3 are turned on, while the first transistor T1, third transistor T3, fourth transistor T4, eighth transistor T8, third switching transistor Ts3, fifth switching transistor Ts5, first frequency division transistors Tf1 to fourth frequency division transistors Tf4, fourth output transistor To4, first output transistor To1, and second output transistor To2 are turned off. The second gate control signal Nscan(p+5) in the p+5 stage, and the first gate control signals Pscan(q+10) in the q+10 stage to the first gate control signals Pscan(q+11) in the q+11 stage have high levels.

[0149] In the p+6th stage gate drive circuit GA(p+6), the first transistor T1 is turned on, the third transistor T3 is turned off, and the second gate control signal Nscan(p+6) of the p+6th stage, the first gate control signal Pscan(q+12) of the q+12th stage, and the first gate control signal Pscan(q+13) of the q+13th stage are at a high level.

[0150] In the ninth stage t9, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 and the fifth clock signal CK5 are at a high level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0151] The second gate control signals Nscan(p) in stage p to Nscan(p+4) in stage p+4 have a high level, and the first gate control signals Pscan(q+1) in stage q+1 to Pscan(q+9) in stage q+9 also have a high level.

[0152] The operation performed by the gate drive circuit GA(p+5) in the p+5th stage at the 9th stage t9 is similar to the operation performed at the 8th stage t8, with the second gate control signal Nscan(p+5) of the p+5th stage being at a low level, and the first gate control signals Pscan(q+10) of the q+10th stage to the first gate control signals Pscan(q+11) of the q+11th stage being at a high level. The operation performed by the gate drive circuit GA(p+6) in the p+6th stage at the 9th stage t9 is similar to the operation performed at the 8th stage t8, with the second gate control signal Nscan(p+6) of the p+6th stage, the first gate control signal Pscan(q+12) of the q+12th stage, and the first gate control signal Pscan(q+13) of the q+13th stage being at a high level.

[0153] Therefore, as can be seen from the analysis of Figure 5A, by controlling the change of the first frequency division control signal FD1 from a low-level active state to a high-level inactive state, the output of the first gate control signal Pscan by multiple gate drive circuits GA can be changed from outputting a first gate control signal Pscan with a low level to outputting a first gate control signal Pscan without a low level. Thus, by controlling the level state of the first frequency division control signal FD1, the level state of multiple first gate control signals Pscan can be controlled, thereby controlling whether or not the first gate control signals Pscan output from multiple gate drive circuits GA have active pulses. By adjusting the timing of the level change of the first frequency division control signal FD1, it is possible to control the first gate control signals Pscan of multiple stages so that they do not have active pulses from the time they correspond to different stages.

[0154] Similarly, the operating principles for multiple gate drive circuits GA can be obtained when the first frequency division control signal FD1 changes from a high level to a low level.

[0155] Continuing with reference to Figures 3A-3B, 4, and 5B, when the second frequency division control signal FD2 has a low level and the first frequency division control signal FD1 has a low level, the operating principle of the gate drive circuits GA(p) of the p-th stage to the gate drive circuits GA(p+6) of the p+6th stage, corresponding to the first stage t1 to the fifth stage t5, can be explained by referring to the explanation corresponding to the first stage t1 to the fifth stage t5 in Figure 5A. Therefore, the change in the second frequency division control signal FD2 from a low level to a high level will be explained starting from the sixth stage t6 in Figure 5B.

[0156] In the sixth stage t6, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 and the fifth clock signal CK5 are at a high level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) of the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) of the p-2 stage are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0157] The second gate control signal Nscan(p) of the p-stage has a low level, and the first gate control signal Pscan(q) of the q-stage and the first gate control signal Pscan(q+1) of the q+1-stage have high levels.

[0158] In the gate drive circuits GA(p+1) of the p+1 stage to the gate drive circuits GA(p+4) of the p+4 stage, the second frequency division transistor Tf2, the fourth frequency division transistor Tf4, and the third output transistor To3 are turned on, and the second gate control signals Nscan(p+1) of the p+1 stage to the second gate control signals Nscan(p+4) of the p+4 stage have a high level, the first gate control signal Pscan(p+2) of the q+2 stage, and the first gate control signals Pscan(p+4) of the q+4 stage to the first gate control signal Pscan(p+13) of the p+13 stage have a high level, and the first gate control signal Pscan(p+3) of the q+3 stage have a low level.

[0159] In the p+5 stage gate drive circuit GA(p+5), the first transistor T1, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the second switching transistor Ts2, the fourth switching transistor Ts4, the fifth switching transistor Ts5, the third switching transistor Ts3, the second output transistor To2, the fourth output transistor To4, and the first to third frequency division transistors Tf1 to Tf3 are turned on. The second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the first switching transistor Ts1, the fourth frequency division transistor Tf4, the first output transistor To1, and the third output transistor To3 are turned off. The second gate control signal Nscan(p+5) of the p+5 stage has a low level, and the first gate control signal Pscan(q+10) of the q+10 stage and the first gate control signal Pscan(q+11) of the q+11 stage have high levels.

[0160] In the p+6th stage gate drive circuit GA(p+6), the second transistor T2, the second output transistor To2, and the fourth output transistor To4 are turned on, while the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The second gate control signal Nscan(p+6) of the p+6th stage has a low level, and the first gate control signal Pscan(q+12) of the q+12th stage and the first gate control signal Pscan(q+13) of the q+13th stage have high levels.

[0161] In the seventh stage t7, the first clock signal CK1 and the sixth clock signal CK6 are at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 and the fifth clock signal CK5 are at a low level, the fourth clock signal CK4 is at a high level, the second node K2(p-1) of the gate drive circuit GA(p-1) in the p-1 stage to the second node K2(p-2) of the gate drive circuit GA(p-2) in the p-2 stage are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0162] The second gate control signals Nscan(p) in stage p to Nscan(p+1) in stage p+1 have a low level, the first gate control signals Pscan(q) in stage q to Pscan(q+3) in stage q+3 have a high level, the first gate control signals Pscan(p+5) in stage q+5 to Pscan(p+13) in stage p+13 have a high level, and the first gate control signal Pscan(p+4) in stage q+4 has a low level.

[0163] In the p+5 stage gate drive circuit GA(p+5), the first transistor T1, third transistor T3, fifth transistor T5, sixth transistor T6, and second frequency division transistor Tf2 are turned on, while the second transistor T2, fourth transistor T4, seventh transistor T7, eighth transistor T8, first switching transistor Ts1, second switching transistor Ts2, third switching transistor Ts3, fourth switching transistor Ts4, fifth switching transistor Ts5, first frequency division transistor Tf1, third frequency division transistor Tf3, fourth frequency division transistor Tf4, third output transistor To3, fourth output transistor To4, first output transistor To1, and second output transistor To2 are turned off. The second gate control signal Nscan(p+5) of the p+5 stage has a low level, and the first gate control signal Pscan(q+10) of the q+10 stage and the first gate control signal Pscan(q+11) of the q+11 stage have high levels.

[0164] In the p+6th stage gate drive circuit GA(p+6), the second transistor T2, the second output transistor To2, and the fourth output transistor To4 are turned on, while the third transistor T3, the first output transistor To1, and the third output transistor To3 are turned off. The second gate control signal Nscan(p+6) of the p+6th stage has a low level, and the first gate control signal Pscan(q+12) of the q+12th stage and the first gate control signal Pscan(q+13) of the q+13th stage have high levels.

[0165] Therefore, as can be seen from the analysis of Figure 5B, by controlling the change of the second frequency division control signal FD2 from a low-level active state to a high-level inactive state, the output of the second gate control signal Nscan by multiple gate drive circuits GA can be changed from outputting a second gate control signal Nscan with a low level to outputting a second gate control signal Nscan without a low level. Thus, by controlling the level state of the second frequency division control signal FD2, the level state of multiple second gate control signals Nscan can be controlled, thereby controlling whether or not the second gate control signals Nscan output from multiple gate drive circuits GA have active pulses. By adjusting the timing of the level change of the second frequency division control signal FD2, it is possible to control the second gate control signals Nscan of multiple stages so that they do not have active pulses from the time they correspond to different stages.

[0166] Similarly, the operating principles for multiple gate drive circuits GA can be obtained when the second frequency division control signal FD2 changes from a high level to a low level.

[0167] Similarly, referring to the analysis of Figures 5A to 5B, if the gate drive circuit GA includes three first output modules 20 and uses the corresponding design shown in Figure 3C, the timings of the multiple first gate control signals Pscan and second gate control signals Nscan are obtained as shown in Figure 5C. Here, CK7 is the clock signal transmitted by the seventh clock line CKL7, and CK8 is the clock signal transmitted by the eighth clock line CKL8.

[0168] Similarly, referring to the analysis of Figures 5A to 5B, if the gate drive circuit GA includes three first output modules 20 and uses the corresponding design shown in Figure 3D, the timings of the multiple first gate control signals Pscan and second gate control signals Nscan are obtained as shown in Figure 5D.

[0169] Similarly, referring to the analysis of Figures 5A to 5B, if the gate drive circuit GA includes three first output modules 20 and uses the corresponding design shown in Figure 3E, the timings of the multiple first gate control signals Pscan and second gate control signals Nscan are obtained as shown in Figure 5E.

[0170] To make it easier to understand, in the same gate drive circuit GA, when multiple first output modules 20 are controlled using multiple first frequency division control signals FD1, the multiple first frequency division control signals FD1 can be independent of each other in terms of the timing of the change from low level to high level, thereby enabling independent control of whether or not the first gate control signal Pscan output from each first output module 20 has an effective level.

[0171] To make it easier to understand, the timing of the level change of the second frequency division control signal FD2 and the timing of the level change of the first frequency division control signal FD1 may be the same or different.

[0172] To make it easier to understand, by adjusting the timing of the level changes of the second frequency division control signal FD2 and the first frequency division control signal FD1, the display panel using the gate drive unit GM can achieve frequency division control at different positions.

[0173] Figure 6 is a schematic diagram showing a display device provided by an embodiment of the present application. The present application further provides a display device, which may be a mobile device such as a mobile phone, a notebook computer, or a wearable device, or it may be a television, a desktop computer, or the like.

[0174] As shown in Figure 6, the display device includes one of the display driver circuits Ddc and a display panel DP as described above.

[0175] The display panel DP is electrically connected to the display driver circuit Ddc, and the display panel DP includes multiple sub-pixels Spi, which are used to realize the display function of the display panel DP.

[0176] The gate drive unit GM of the display drive circuit Ddc is used to control the display panel DP by providing multiple first gate control signals Pscan to the display panel DP to realize the display.

[0177] Figure 7 is a schematic diagram showing the configuration of a pixel driving circuit provided by an embodiment of the present application. Each sub-pixel Spi includes a light-emitting element and a pixel driving circuit for driving the light-emitting element to emit light, the pixel driving circuit including a driving transistor Tdr and a data transistor Tda.

[0178] Optionally, the light-emitting element Di includes light-emitting diodes. Optionally, the light-emitting element Di includes organic light-emitting diodes, sub-millimeter light-emitting diodes, micro-light-emitting diodes, etc.

[0179] The drive transistor Tdr and the light-emitting element Di are electrically connected between the first voltage terminal Vdd and the second voltage terminal Vss, and the drive transistor Tdr is positioned to generate a drive current to drive the light-emitting element Di to emit light.

[0180] Optionally, the input terminal of the drive transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the drive transistor Tdr is electrically connected to the anode of the light-emitting element Di, and the cathode of the light-emitting element Di is electrically connected to the second voltage terminal Vss, with the voltage supplied by the first voltage terminal Vdd being greater than the voltage supplied by the second voltage terminal Vss.

[0181] The data transistor Tda is positioned to transmit data signals to the control terminal of the drive transistor Tdr. Here, the input terminal of the data transistor Tda is positioned to receive data signals transmitted by the corresponding electrically connected data line DL, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the drive transistor Tdr.

[0182] Here, multiple first output modules 20 in the same gate drive circuit GA are electrically connected to the control terminals of data transistors Tda in multiple adjacent rows of sub-pixels Spi, and each first output module 20 is electrically connected to the control terminal of data transistor Tda in at least one row of sub-pixels Spi. Multiple first gate control signals Pscan control the ON state of the data transistors Tda of the multiple sub-pixels Spi, thereby controlling the refresh rate for the display data of the multiple sub-pixels Spi, which is advantageous for the display panel DP to realize a domain division / frequency division design.

[0183] Optionally, each first output module 20 is electrically connected to the control terminal of the data transistor Tda in one row of subpixels Spi, and the same gate drive circuit GA includes X first output modules 20, and the X first output modules 20 in the same gate drive circuit GA are electrically connected to the control terminals of the data transistor Tda in adjacent X rows of subpixels Spi, thereby causing the data transistors Tda in multiple adjacent rows of subpixels Spi to be sequentially turned on or off based on multiple first gate control signals Pscan having corresponding phase differences, and when it is necessary to refresh the display data, the data signal refresh operation can be sequentially realized by controlling the multiple adjacent rows of subpixels Spi.

[0184] For example, each gate drive circuit GA includes two first output modules 20, and the two first output modules 20 in the same gate drive circuit GA are electrically connected to the control terminals of the data transistors Tda in two adjacent rows of subpixels Spi.

[0185] Furthermore, for example, each gate drive circuit GA includes three first output modules 20, and the three first output modules 20 in the same gate drive circuit GA are electrically connected to the control terminals of the data transistors Tda in three adjacent rows of subpixels Spi.

[0186] Optionally, when the same gate drive circuit GA includes X first output modules 20, and each first output module 20 is electrically connected to the control terminal of the data transistor Tda in one row of sub-pixels Spi, the gate drive circuit GA of the K stage is correspondingly electrically connected to the control terminal of the data transistor Tda in rows L to L+(X-1), thereby enabling display driving using sequential scanning technology when multiple sub-pixels Spi are driven using the gate drive unit GM. Here, K≧1 and L=XK-(X-1).

[0187] For example, the K-stage gate drive circuit GA includes two first output modules 20, each of which includes a first sub-output module 201 and a second sub-output module 202. The first sub-output module 201 is electrically connected to the control terminal of the data transistor Tda in the L-th row sub-pixel Spi, and the second sub-output module 202 is electrically connected to the control terminal of the data transistor Tda in the L+1-th row sub-pixel Spi. Thus, the first sub-output module 201 in the K-stage gate drive circuit GA provides a first gate control signal Pscan to the control terminal of the data transistor Tda in the L-th row sub-pixel Spi, and the second sub-output module 202 in the K-stage gate drive circuit GA provides a first gate control signal Pscan to the control terminal of the data transistor Tda in the L+1-th row sub-pixel Spi. Here, K≧1, L=2K-1, L is odd, and the L-th row sub-pixel Spi is adjacent to the L+1-th row sub-pixel Spi.

[0188] Furthermore, for example, the gate drive circuit GA of the K-th stage includes three first output modules 20, the three first output modules 20 include a first sub-output module 201, a second sub-output module 202, and a third sub-output module, the first sub-output module 201 is electrically connected to the control terminal of the data transistor Tda in the sub-pixel Spi of the L-th row, the second sub-output module 202 is electrically connected to the control terminal of the data transistor Tda in the sub-pixel Spi of the L+1-th row, and the third sub-output module is electrically connected to the control terminal of the data transistor Tda in the sub-pixel Spi of the L+2-th row, and so As a result, the first sub-output module 201 in the K-stage gate drive circuit GA provides a first gate control signal Pscan to the control terminal of the data transistor Tda in the L-row sub-pixel Spi, the second sub-output module 202 in the K-stage gate drive circuit GA provides a first gate control signal Pscan to the control terminal of the data transistor Tda in the L+1-row sub-pixel Spi, and the third sub-output module in the K-stage gate drive circuit GA provides a first gate control signal Pscan to the control terminal of the data transistor Tda in the L+2-row sub-pixel Spi. Here, K≧1 and L=3K-2, and the L+1-row sub-pixel Spi is simultaneously adjacent to the L-row sub-pixel Spi and the L+2-row sub-pixel Spi.

[0189] To make it clearer, in some embodiments, each first output module 20 may be electrically connected to the control terminal of the data transistor Tda in a multi-row sub-pixel Spi.

[0190] Optionally, the display panel DP includes multiple first scan lines SL1 and a source drive chip. The control terminal of the data transistor Tda in multiple sub-pixels Spi receives the required first gate control signal Pscan via the corresponding first scan line SL1, and the source drive chip is connected to multiple data lines DL and outputs multiple data signals.

[0191] Continuing with Figure 7, at least one sub-pixel Spi includes a compensation transistor Tc, the input terminal of the compensation transistor Tc is electrically connected to the output terminal of the drive transistor Tdr, the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the drive transistor Tdr, and the control terminal of the compensation transistor Tc is positioned to receive the first scan signal Scan1.

[0192] Optionally, the display panel DP includes multiple second scan lines SL2, and the control terminals of the compensation transistor Tc in multiple sub-pixels Spi receive the required first scan signal Scan1 via the corresponding second scan line SL2.

[0193] In some embodiments, the gate drive circuit GA can output a second gate control signal Nscan in addition to a plurality of first gate control signals Pscan. By controlling the second output module 50 in each gate drive circuit GA, the second gate control signal Nscan can be output to the compensation transistor Tc in multiple sub-pixels Spi in multiple adjacent rows, thereby reducing the number of gate drive units GM required for matching the sub-pixels Spi. That is, the operating state of the compensation transistor Tc is controlled as the first scan signal Scan1 using the second gate control signal Nscan output from the gate drive circuit GA.

[0194] Optionally, if the gate drive circuit GA includes X first output modules 20, the second output module 50 in the gate drive circuit GA outputs a second gate control signal Nscan to the compensation transistor Tc of multiple sub-pixels Spi in X adjacent rows, matching the number of rows of sub-pixels Spi driven by the second gate control signal Nscan output from the same gate drive circuit GA with the number of rows of sub-pixels Spi driven by the first gate control signal Pscan.

[0195] Optionally, if the second output module 50 of the gate drive circuit GA outputs a second gate control signal Nscan to the compensation transistor Tc of multiple sub-pixels Spi in multiple adjacent rows, the first gate control signal Pscan and the second gate control signal Nscan received by the same sub-pixel Spi are output from the same gate drive circuit GA. As a result, the data transistor Tda and the compensation transistor Tc in the same sub-pixel Spi have a common on-period, the data signal is transmitted to the control terminal of the drive transistor Tdr, and a refresh operation is performed on the display data of the sub-pixel Spi.

[0196] Optionally, if the same gate drive circuit GA includes X first output modules 20, the gate drive circuit GA of the K-th stage is electrically connected to the control terminal of the compensation transistor Tc in the corresponding L-th to L+(X-1)-th row subpixels Spi, so that the data transistor Tda and compensation transistor Tc in each subpixel Spi have a common on-period. Here, K≧1 and L=XK-(X-1).

[0197] Continuing with Figure 7, at least one subpixel Spi includes a reset transistor Tr, the input terminal of the reset transistor Tr is electrically connected to the reset line VLr, the output terminal of the reset transistor Tr is electrically connected to the control terminal of the drive transistor Tdr, and the control terminal of the reset transistor Tr is positioned to receive the second scan signal Scan2.

[0198] Optionally, the display panel DP includes multiple third scan lines SL3, and the control terminals of the reset transistors Tr in multiple sub-pixels Spi receive the second scan signal Scan2 required by the corresponding third scan line SL3.

[0199] In some embodiments, when the gate drive circuit GA simultaneously outputs multiple first gate control signals Pscan and second gate control signals Nscan, the second output module 50 of each gate drive circuit GA outputs the second gate control signal Nscan to the control terminal of the reset transistor Tr in multiple sub-pixels Spi in multiple adjacent rows, thereby reducing the number of gate drive units GM required for matching the sub-pixels Spi. That is, the operating state of the reset transistor Tr is controlled as a second scan signal Scan2 using the second gate control signal Nscan output from the gate drive circuit GA.

[0200] Optionally, if the same gate drive circuit GA includes X first output modules 20, the gate drive circuit GA of the K-2 stage is electrically connected to the control terminal of the reset transistor Tr in the corresponding L row to L+(X-1) row subpixels Spi, thereby giving each subpixel Spi data transistor Tda and reset transistor Tr independent ON periods.

[0201] To make it easier to understand, in a display device, if only one gate drive unit GM is provided that simultaneously outputs multiple first gate control signals Pscan and second gate control signals Nscan, the multiple second gate control signals Nscan may independently control the compensation transistor Tc in multiple sub-pixels Spi, independently control the reset transistor Tr in multiple sub-pixels Spi, or simultaneously control the compensation transistor Tc and the reset transistor Tr in multiple sub-pixels Spi.

[0202] Optionally, if multiple second gate control signals Nscan simultaneously control the compensation transistor Tc and reset transistor Tr in multiple sub-pixels Spi, the second gate control signals Nscan corresponding to the compensation transistor Tc and reset transistor Tr in the same sub-pixel Spi can be provided by gate drive circuits GA with different numbers of stages. For details on this configuration, please refer to the relevant design; a detailed explanation is omitted here.

[0203] Therefore, each gate drive circuit GA can output a second gate control signal Nscan to the control terminal of the compensation transistor Tc or reset transistor Tr in multiple subpixels Spi in multiple adjacent rows.

[0204] Optionally, the second gate control signal Nscan output from the gate drive circuits GA of multiple stages in the same gate drive unit GM can be output to transistors of the same functional type (i.e., the second gate control signals Nscan output from the gate drive circuits GA of multiple stages in the same gate drive unit GM can all be output to the compensation transistor Tc, or all to the reset transistor Tr).

[0205] Optionally, in some embodiments, two gate drive units GM that simultaneously output multiple first gate control signals Pscan and second gate control signals Nscan are arranged, and the reset transistor Tr and the compensation transistor Tc are controlled using the second gate control signals Nscan output by the two gate drive units GM, respectively. On the other hand, the compensation transistor Tc can be controlled using the second gate control signal Nscan output by either the two gate drive units GM or one of the two gate drive units GM.

[0206] For example, the display driver circuit Ddc includes two gate driver units GM, and the two gate driver units GM include a first gate driver unit and a second gate driver unit. Here, the control terminal of the compensation transistor Tc in multiple sub-pixels Spi receives a second gate control signal Nscan output from the multiple gate driver circuits GA in the first gate driver unit, and the control terminal of the reset transistor Tr in multiple sub-pixels Spi receives a second gate control signal Nscan output from the multiple gate driver circuits GA in the second gate driver unit. The control terminal of the data transistor Tda in multiple sub-pixels Spi receives a first gate control signal Pscan output from the multiple gate driver circuits GA in the first gate driver unit, and / or receives a first gate control signal Pscan output from the multiple gate driver circuits GA in the second gate driver unit.

[0207] Optionally, the compensating transistor Tc and reset transistor Tr are silicon transistors or oxide transistors, and the compensating transistor Tc and reset transistor Tr are P-type transistors or N-type transistors. Optionally, to reduce leakage from the control terminal of the driving transistor Tdr to the output terminal of the driving transistor Tdr and the reset line VLr, the compensating transistor Tc and reset transistor Tr are oxide transistors. To fit existing process architectures, the compensating transistor Tc and reset transistor Tr are N-type transistors. For clarity, the active layer of an oxide transistor contains indium gallium zinc oxide, etc.

[0208] Continuing with Figure 7, at least one subpixel Spi further includes a first initial transistor Ti1, a first light emission control transistor Te1, a second light emission control transistor Te2, and a first storage capacitor Cst1.

[0209] The input terminal of the first initial transistor Ti1 is positioned to receive the first initial signal transmitted by the first initial line VL1, the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light-emitting element Di, and the control terminal of the first initial transistor Ti1 is positioned to receive the third scanning signal Scan3.

[0210] The input terminal of the first light emission control transistor Te1 is electrically connected to the first voltage terminal Vdd, and the output terminal of the first light emission control transistor Te1 is electrically connected to the input terminal of the drive transistor Tdr.

[0211] The input terminal of the second light emission control transistor Te2 is electrically connected to the output terminal of the drive transistor Tdr, and the output terminal of the second light emission control transistor Te2 is electrically connected to the anode electrode of the light-emitting element Di.

[0212] The first terminal of the first storage capacitor Cst1 is electrically connected to the first voltage terminal Vdd, and the second terminal of the first storage capacitor Cst1 is electrically connected to the control terminal of the drive transistor Tdr.

[0213] Optionally, the multiple scan lines include multiple fourth scan lines SL4 and multiple light emission control lines EML, the multiple fourth scan lines SL4 being electrically connected to the control terminals of the first initial transistor Ti1 in multiple sub-pixels Spi, the multiple light emission control lines EML being electrically connected to the control terminals of the first light emission control transistor Te1 and the second light emission control transistor Te2 in multiple sub-pixels Spi, and the control terminals of the first initial transistor Ti1 in multiple sub-pixels Spi receiving the required third scan signal Scan3 via the corresponding fourth scan line SL4.

[0214] Optionally, in some embodiments, the sub-pixel Spi further includes a second storage capacitor Cst2, the first terminal of which is electrically connected to the control terminal of the data transistor Tda, and the second terminal of which is electrically connected to the control terminal of the drive transistor Tdr.

[0215] Optionally, in some embodiments, to improve the threshold voltage shift of the drive transistor Tdr due to the switching of the display frequency, the sub-pixel Spi further includes a second initial transistor Ti2, the input terminal of the second initial transistor Ti2 is arranged to receive the second initial signal transmitted by the second initial line VL2, and the output terminal of the second initial transistor Ti2 is electrically connected to the input terminal of the drive transistor Tdr. Optionally, multiple fourth scan lines SL4 are electrically connected to the control terminals of the second initial transistor Ti2 in multiple sub-pixel Spi.

[0216] Figure 8 is a timing diagram corresponding to the pixel driving circuit provided by the embodiment of the present application. The operating principle of the pixel driving circuit will be explained using the example that the compensation transistor Tc and reset transistor Tr are N-type transistors, and the driving transistor Tdr, data transistor Tda, first light emission control transistor Te1, second light emission control transistor Te2, first initial transistor Ti1, and second initial transistor Ti2 are P-type transistors.

[0217] In the first reset stage Si1, the light emission control signal EM transmitted by the light emission control line EML and the first gate control signal Pscan received by the data transistor Tda are at a high level, the second scan signal Scan2 received by the reset transistor Tr and the first scan signal Scan1 received by the compensation transistor Tc are at a low level, and the third scan signal Scan3 is at a low level. The first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light-emitting element Di, realizing a potential reset of the anode of the light-emitting element Di. The second initial signal transmitted from the second initial line VL2 is transmitted to the input and output terminals of the drive transistor Tdr, realizing a potential reset of the input and output terminals of the drive transistor Tdr.

[0218] In the second reset stage Si2, the second scan signal Scan2, the light emission control signal EM, the first gate control signal Pscan, and the third scan signal Scan3 are at high levels, while the first scan signal Scan1 is at a low level. When the reset transistor Tr is turned on, the reset signal Vr is transmitted to the gate of the drive transistor Tdr, thereby achieving a potential reset of the control terminal of the drive transistor Tdr.

[0219] During the data writing phase Sw, the first scan signal Scan1, the light emission control signal EM, and the third scan signal Scan3 are at high levels, while the second scan signal Scan2 and the first gate control signal Pscan are at low levels. When the data transistor Tda and the compensation transistor Tc are turned on, the data signal is transmitted to the control terminal of the drive transistor Tdr.

[0220] Here, a step may be further included between the second reset stage Si2 and the data writing stage Sw to control whether the reset transistor Tr and the compensation transistor Tc are turned on simultaneously, thereby enabling the reset signal Vr to be transmitted to the output and input terminals of the drive transistor Tdr, and realizing a potential reset of the output and input terminals of the drive transistor Tdr.

[0221] In the third reset stage Si3, the light emission control signal EM and the first gate control signal Pscan are at a high level, while the second scan signal Scan2, the first scan signal Scan1, and the third scan signal Scan3 are at a low level. The first initial signal is transmitted to the anode of the light-emitting element Di, and the second initial signal is transmitted to the input and output terminals of the drive transistor Tdr.

[0222] In the light emission stage Sd, the first gate control signal Pscan and the third scan signal Scan3 are at a high level, and the light emission control signal EM, the second scan signal Scan2, and the first scan signal Scan1 are at a low level. When the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned on, the drive transistor Tdr generates a drive current to drive the corresponding light-emitting element Di to emit light.

[0223] In the fourth reset stage Si4 and the fifth reset stage Si5, the light emission control signal EM and the first gate control signal Pscan are at a high level, while the second scan signal Scan2, the first scan signal Scan1, and the third scan signal Scan3 are at a low level. The first initial signal is transmitted to the anode of the light-emitting element Di, and the second initial signal is transmitted to the input and output terminals of the drive transistor Tdr.

[0224] Here, the write frame WF includes a first reset stage Si1, a second reset stage Si2, a data write stage Sw, a third reset stage Si3, and an emission stage Sd, while the hold frame HF includes a fourth reset stage Si4, a fifth reset stage Si5, and an emission stage Sd.

[0225] Figure 9 is a schematic diagram illustrating the display principle of high-frequency and low-frequency images provided by the embodiment of the present application. The write frame WF and hold frame HF will be described using the example of the display panel DP displaying a single static screen.

[0226] When the display panel DP displays at a high frequency (e.g., 120Hz), the display panel DP needs to perform a refresh operation of the display data 120 times per second, meaning that the screen contains 120 frames per second, and each frame's display requires a refresh of the display data (i.e., the sub-pixel Spi matches the timing of the write frame WF shown in Figure 8 for each frame). When the display panel DP displays at a low frequency (e.g., 1Hz), the display panel DP also contains 120 frames per second, but only the first frame's screen requires a refresh of the display data (i.e., the sub-pixel Spi matches the timing of the write frame WF shown in Figure 8 only for the first frame's screen), and the 119 consecutive frames after the first frame F1 all retain the data signal of the first frame's screen and do not perform a refresh operation of the display data (i.e., the sub-pixel Spi matches the timing of the hold frame HF shown in Figure 8 for the 119 consecutive frames after the first frame F1). Here, the frame in which the display data is refreshed may be designated as the write frame WF, and the frame in which the display data is not refreshed may be designated as the hold frame HF. In this case, in the write frame WF, the first scan signal Scan1 corresponding to the compensation transistor Tc, the second scan signal Scan2 corresponding to the reset transistor Tr, and the first gate control signal Pscan corresponding to the data transistor Tda must all have an active level so that the original data signal stored in the control terminal of the drive transistor Tdr is overwritten by the newly written data signal. This ensures that the sub-pixel Spi is displayed again in the write frame WF by the newly written data signal. On the other hand, in the hold frame HF, the second scan signal Scan2 corresponding to the compensation transistor Tc and reset transistor Tr in some sub-pixel Spi is kept at an inactive level, turning off the compensation transistor Tc and reset transistor Tr, and thus no new data signal is stored in the control terminal of the drive transistor Tdr.In the hold frame HF, the first gate control signal Pscan corresponding to the data transistor Tda can maintain the same frequency as the write frame WF. Alternatively, in the hold frame HF, the first gate control signal Pscan corresponding to the data transistor Tda maintains an invalid level, thereby the frequency of the first gate control signal Pscan corresponding to the data transistor Tda in the hold frame HF is lower than the frequency in the write frame WF.

[0227] Optionally, in some embodiments, in the holding frame HF, the data transistor Tda is turned on based on the corresponding first gate control signal Pscan, and the data transistor Tda performs a potential reset to the input terminal of the drive transistor Tdr using a signal transmitted by the data line DL to which it is electrically connected.

[0228] Optionally, in some embodiments, in the holding frame HF, the data transistor Tda is kept off based on the corresponding first gate control signal Pscan, and the second initial transistor Ti2 has an on period based on the corresponding third scan signal Scan3, thereby performing a potential reset to the input terminal of the drive transistor Tdr using the second initial signal transmitted by the second initial line VL2 to which the second initial transistor Ti2 is electrically connected.

[0229] Using a matching design as an example, in which each gate drive circuit GA includes two first output modules 20, the principle that enables the display panel DP using the display drive circuit Ddc to display using frequency division will be explained in conjunction with the analysis in Figures 5A to 5B and Figure 8.

[0230] In the first frame F1 of one display cycle, new data signals are written to the control terminals of the drive transistors Tdr in multiple sub-pixels Spi. The first frequency division control signal FD1 and the second frequency division control signal FD2 maintain their active levels, controlling that all of the multiple rows of sub-pixels Spi in the display panel DP go through the writing frame WF stage shown in Figure 8. Here, one display cycle may include one frame or multiple frames. If one display cycle includes one frame, that frame is the writing frame WF corresponding to the multi-line sub-pixels Spi. If one display cycle includes multiple frames, the first frame F1 is the writing frame WF corresponding to the multiple rows of sub-pixels Spi.

[0231] In the second frame F2 of one display cycle, if the sub-pixels Spi of the first row to the sub-L-1 row of the display panel DP are displayed at a high frequency, and the sub-pixels Spi of the L row and subsequent rows are displayed at a low frequency, then the second scan signal Scan2, the first scan signal Scan1, and the first gate control signal Pscan used in correspondence with the sub-pixels Spi of the first row to the sub-L-1 row must all have valid pulses, and as a result, the sub-pixels Spi of the first row to the sub-pixels Spi of the L row all go through the write frame WF stage shown in Figure 8. On the other hand, the second scan signal Scan2, the first scan signal Scan1, and the first gate control signal Pscan used in correspondence with the sub-pixels Spi of the L row and subsequent rows do not need to have valid pulses, and as a result, the sub-pixels Spi of the L row and subsequent rows all go through the hold frame HF stage shown in Figure 8. Here, the second frame, F2, is positioned after the first frame, F1.

[0232] Therefore, for the sub-pixels Spi in the first row to the sub-pixels Spi in the (L-1)th row, the second frame F2 is still the write frame WF. On the other hand, for the sub-pixels Spi in the (L)th row and subsequent rows of sub-pixels Spi, the second frame F2 is the hold frame HF. Therefore, corresponding to the second frame F2, the control terminal of the drive transistor Tdr in the sub-pixels Spi in the first row to the sub-pixels Spi in the (L-1)th row has data signal writing, while the control terminal of the drive transistor Tdr in the sub-pixels Spi in the (L)th row and subsequent rows of sub-pixels Spi does not have data signal writing. The refresh rates corresponding to the sub-pixels Spi in the first row to the sub-pixels Spi in the (L-1)th row and the sub-pixels Spi in the (L)th row and subsequent rows of sub-pixels Spi are different, thereby enabling the display panel DP to display using frequency division.

[0233] Similarly, if the gate drive circuit includes three or more first output modules 20, it enables the design of a function that controls the display panel and displays it in frequency division.

[0234] Furthermore, when a gate drive unit transmits the corresponding first clock signal XCK and second clock signal CK to the gate drive circuits GA of multiple stages using Y clock lines, the corresponding loads on the multiple clock lines are not uniform, resulting in differences in the display on the display panel using the gate drive unit. For example, if the display panel uses the design corresponding to the gate drive unit shown in Figure 3A, the display effect of odd-numbered rows and even-numbered rows on the display panel will differ.

[0235] On the other hand, when using Z clock lines out of multiple clock lines to transmit the corresponding first clock signal XCK to the gate drive circuit GA of multiple stages, and using Y clock lines out of multiple clock lines to transmit the corresponding second clock signal CK to the gate drive circuit GA of multiple stages, the loads corresponding to the Z clock lines and the Y clock lines can be brought closer together, resulting in smaller display differences in the display panel using this gate drive unit design. For example, using the design corresponding to the gate drive unit shown in Figure 3B results in smaller display differences between odd and even rows on the display panel compared to using the design corresponding to the gate drive unit shown in Figure 3A, which is advantageous for improving display quality.

[0236] Furthermore, the aforementioned H (i.e., unit time length) can correspond to the row period time length.

[0237] Each gate drive circuit included in the gate drive unit is provided with multiple first output modules, and multiple first gate control signals with phase differences output from multiple first output modules in the same gate drive circuit can be used in the display device, thereby realizing a frequency-division display design on the display panel. Therefore, when the display device uses any one of the above-described display drive circuits, it is advantageous to reduce the layout space occupied by the gate drive unit and reduce the bezel width of the display panel, thereby easily realizing a narrow bezel design for the display panel and advantageous to reduce driving power consumption. A display device using the display drive circuit of the present invention can further compress the bezel dimensions of the display panel to about 100 microns. Compared with a display device using a display drive circuit having one first output module and one second output module, a display device using the display drive circuit of the present invention can compress the bezel dimensions of the display panel to about 60 microns.

[0238] In this specification, the principles and embodiments of the present application have been described using specific examples, but the descriptions of the above-mentioned embodiments are intended solely to aid in understanding the method and core idea of ​​the present application. Furthermore, those skilled in the art will know that there are variations in specific embodiments and scope of application based on the idea of ​​the present application. In summary, it should be understood that the description in this specification is not intended to limit the present application. [Explanation of Symbols]

[0239] 10: Node control module 20: First output module 30: First frequency division module 40: First control module 50: Second output module 60: Second frequency division module 70: Second control module 80: Reset Module 201: First sub-output module 202: Second sub-output module

Claims

1. The gate drive unit includes a plurality of frequency division control lines and a plurality of gate drive circuits connected in cascade, the plurality of frequency division control lines are arranged to transmit frequency division control signals to the plurality of gate drive circuits, and each of the gate drive circuits is A node control module is electrically connected to the first and second nodes of the gate drive circuit of the current stage and is arranged to control the signals transmitted to the first and second nodes based on the corresponding first clock signal and start signal. A first output module comprising a plurality of first output modules, each of which is electrically connected to a first node and a second node, and each first output module is arranged to output a first gate control signal based on a corresponding second clock signal, the frequency division control signal, and signals from the first node and the second node, The system includes the first node, the second node, and at least one first frequency division module electrically connected to at least one first output module, and arranged to control signal transmission between the first node and the corresponding first output module based on the frequency division control signal and the signal of the second node, Here, the multiple first output modules are arranged to output a plurality of first gate control signals having a phase difference. Display driver circuit.

2. Each gate drive circuit includes X first output modules, and the phase difference of the first clock signal corresponding to two adjacent stages of the gate drive circuit is XH, where X ≥ 2 and H is the unit time length. The display drive circuit according to claim 1.

3. The gate drive circuits of the multiple stages are electrically connected to Y clock lines, and the Y clock lines transmit the corresponding first clock signal and second clock signal to the gate drive circuits of the multiple stages, where Y = 2X. The display drive circuit according to claim 2.

4. The gate drive circuits of the multiple stages are electrically connected to multiple clock lines, and Z of the multiple clock lines transmit the corresponding first clock signal to the gate drive circuits of the multiple stages, and Y of the multiple clock lines transmit the corresponding second clock signal to the gate drive circuits of the multiple stages, where Z = 2 and Y = 2X. The display drive circuit according to claim 1.

5. Each gate drive circuit includes two first output modules, and the Y clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line. Here, the first clock line transmits the corresponding second clock signal to one of the first output modules in the gate drive circuit of the second k+1 stage, the second clock line transmits the corresponding second clock signal to the other first output module in the gate drive circuit of the second k+1 stage, the third clock line transmits the corresponding second clock signal to one of the first output modules in the gate drive circuit of the second k+2 stage, and the fourth clock line transmits the corresponding second clock signal to the other first output module in the gate drive circuit of the second k+2 stage, where k ≥ 0. A display drive circuit according to any one of claims 3 to 4.

6. The third clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+1 stage, and the first clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+2 stage. The display drive circuit according to claim 5.

7. The Z clock lines include a fifth clock line and a sixth clock line. Here, the fifth clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+1 stage, and the sixth clock line transmits the corresponding first clock signal to the gate drive circuit of the second k+2 stage. The display drive circuit according to claim 5.

8. Each of the first output modules is: A first output transistor wherein the control terminal of the first output transistor is electrically connected to the corresponding first frequency division module, the input terminal of the first output transistor is arranged to receive the corresponding second clock signal, and the output terminal of the first output transistor is electrically connected to the first output terminal of the gate drive circuit of the current stage that outputs the first gate control signal, A second output transistor, wherein the control terminal of the second output transistor is electrically connected to the second node, the input terminal of the second output transistor is electrically connected to the first power supply terminal, and the output terminal of the first output transistor is electrically connected to the first output terminal, A first capacitor, the first terminal of which is electrically connected to the control terminal of the first output transistor, and the second terminal of which is electrically connected to the first output terminal, The display drive circuit according to claim 1.

9. At least one of the first output modules includes a first switching transistor, the control terminal of the first switching transistor being electrically connected to the second node of the gate drive circuit of the previous stage, the input terminal of the first switching transistor being electrically connected to the corresponding first frequency division module, and the output terminal of the first switching transistor being electrically connected to the control terminal of the first output transistor. The display drive circuit according to claim 8.

10. At least one of the gate drive circuits is A second switching transistor wherein the control terminal of the second switching transistor receives the corresponding first clock signal, and the input terminal of the second switching transistor is electrically connected to at least one input terminal of the first switching transistor, A third switching transistor, wherein the control terminal of the third switching transistor is electrically connected to the second node, the input terminal of the third switching transistor is electrically connected to the first power supply terminal, and the output terminal of the third switching transistor is electrically connected to the output terminal of the second switching transistor, The display drive circuit according to claim 9.

11. The multiple frequency division control lines include a first frequency division control line, and the first frequency division module is A first frequency division transistor, wherein the control terminal of the first frequency division transistor is electrically connected to the second node, A second frequency division transistor wherein the control terminal of the second frequency division transistor is electrically connected to the output terminal of the first frequency division transistor, the input terminal of the second frequency division transistor is electrically connected to the first node, and the output terminal of the second frequency division transistor is electrically connected to the corresponding first output module, A second capacitor, wherein the first terminal of the second capacitor is electrically connected to the control terminal of the second frequency division transistor, and the second terminal of the second capacitor is electrically connected to the output terminal of the second frequency division transistor, Here, the input terminals of the first frequency division transistors in the multiple gate drive circuits are electrically connected to the first frequency division control line. The display drive circuit according to claim 1.

12. At least one of the gate drive circuits is A second output module is electrically connected to the first node and is configured to output a corresponding frequency division control signal and a second gate control signal based on the signal of the first node, The first node, the second node, and the second output module are further comprising a second frequency division module electrically connected to the second output module and arranged to control signal transmission between the first node and the second output module based on the corresponding frequency division control signal and the signal of the second node, The display drive circuit according to claim 1.

13. The multiple frequency division control lines include a second frequency division control line, and the second frequency division module is A third frequency division transistor, wherein the control terminal of the third frequency division transistor is electrically connected to the second node, A fourth frequency division transistor, wherein the control terminal of the fourth frequency division transistor is electrically connected to the output terminal of the third frequency division transistor, the input terminal of the fourth frequency division transistor is electrically connected to the first node, and the output terminal of the fourth frequency division transistor is electrically connected to the corresponding second output module, A third capacitor, wherein the first terminal of the third capacitor is electrically connected to the control terminal of the fourth frequency division transistor, and the second terminal of the third capacitor is electrically connected to the output terminal of the fourth frequency division transistor, Here, the input terminals of the third frequency division transistors in the multiple gate drive circuits are electrically connected to the second frequency division control line. The display drive circuit according to claim 12.

14. The second output module is, A third output transistor wherein the control terminal of the third output transistor is electrically connected to the output terminal of the fourth frequency division transistor, the input terminal of the third output transistor is electrically connected to the second power supply terminal, and the output terminal of the third output transistor is electrically connected to the second output terminal of the gate drive circuit of the current stage that outputs the second gate control signal, A fourth output transistor, wherein the control terminal of the fourth output transistor is electrically connected to the first node, the input terminal of the fourth output transistor is electrically connected to the third power supply terminal, and the output terminal of the fourth output transistor is electrically connected to the second output terminal, The display drive circuit according to claim 13.

15. At least one of the gate drive circuits is A fourth switching transistor wherein the control terminal of the fourth switching transistor receives the corresponding first clock signal, and the input terminal of the fourth switching transistor is electrically connected to the input terminal of the third output transistor, A fifth switching transistor, wherein the control terminal of the fifth switching transistor is electrically connected to the second node, the input terminal of the fifth switching transistor is electrically connected to the first power supply terminal, and the output terminal of the fifth switching transistor is electrically connected to the output terminal of the fourth switching transistor, The display drive circuit according to claim 14.

16. The node control module is A first transistor wherein the control terminal of the first transistor is arranged to receive the corresponding start signal, and the input terminal of the first transistor is electrically connected to a third power supply terminal or a fourth power supply terminal. A second transistor wherein the control terminal of the second transistor is electrically connected to the first control terminal of the first transistor, the input terminal of the second transistor is electrically connected to the first power supply terminal, and the output terminal of the second transistor is electrically connected to the output terminal of the first transistor, A third transistor wherein the control terminal of the third transistor is arranged to receive the corresponding first clock signal, the input terminal of the third transistor is electrically connected to the output terminal of the first transistor, and the output terminal of the third transistor is electrically connected to the first node, A fourth transistor wherein the control terminal of the fourth transistor is electrically connected to the first node, the input terminal of the fourth transistor is electrically connected to the fourth power supply terminal, and the output terminal of the fourth transistor is electrically connected to the second node, A fifth transistor wherein the control terminal of the fifth transistor is electrically connected to the first node, the input terminal of the fifth transistor is electrically connected to the first power supply terminal, and the output terminal of the fifth transistor is electrically connected to the second node, A sixth transistor, wherein the control terminal of the sixth transistor is electrically connected to the second node, the input terminal of the sixth transistor is electrically connected to the third power supply terminal, and the output terminal of the sixth transistor is electrically connected to the first node, The display drive circuit according to claim 1.

17. The node control module is A seventh transistor wherein the control terminal of the seventh transistor is arranged to receive the corresponding first clock signal, and the output terminal of the seventh transistor is electrically connected to the first node, The eighth transistor includes an eighth transistor whose control terminal is electrically connected to the second node, whose input terminal is electrically connected to the first power supply terminal, and whose output terminal is electrically connected to the input terminal of the seventh transistor. The display drive circuit according to claim 16.

18. A display drive circuit according to any one of claims 1 to 17, A display panel is electrically connected to the display driving circuit and includes a plurality of subpixels, each subpixel including a light-emitting element, a driving transistor, and a data transistor, wherein the driving transistor is arranged to generate a driving current for driving the light-emitting element to emit light, and the data transistor is arranged to transmit a data signal to the control terminal of the driving transistor, Here, the multiple first output modules in the same gate drive circuit are electrically connected to the control terminals of the data transistors in multiple adjacent rows of subpixels, and each first gate control signal is electrically connected to the control terminal of the data transistor in at least one row of subpixels. Display device.

19. Each of the first output modules is electrically connected to the control terminal of the data transistor in one row of the subpixels, and each of the gate drive circuits includes two of the first output modules, and the two first output modules in the same gate drive circuit are electrically connected to the control terminals of the data transistors in two adjacent rows of the subpixels. The display device according to claim 18.

20. At least one of the subpixels includes a compensation transistor and a reset transistor, wherein the input terminal of the compensation transistor is electrically connected to the output terminal of the drive transistor, the output terminal of the compensation transistor is electrically connected to the control terminal of the drive transistor, the input terminal of the reset transistor is electrically connected to a reset line, and the output terminal of the reset transistor is electrically connected to the control terminal of the drive transistor. Here, each gate drive circuit outputs a second gate control signal to the control terminal of the compensation transistor or reset transistor in multiple subpixels in multiple adjacent rows. The display device according to claim 18.

21. The display drive circuit includes two gate drive units, and the two gate drive units include a first gate drive unit and a second gate drive unit. Here, the control terminals of the compensation transistors in the plurality of subpixels receive the second gate control signals output from the plurality of gate drive circuits in the first gate drive unit, the control terminals of the reset transistors in the plurality of subpixels receive the second gate control signals output from the plurality of gate drive circuits in the second gate drive unit, the control terminals of the data transistors in the plurality of subpixels receive the first gate control signals output from the plurality of gate drive circuits in the first gate drive unit, and / or receive the first gate control signals output from the plurality of gate drive circuits in the second gate drive unit. The display device according to claim 20.

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