Indication device

Abstract

The present invention provides a display device in which the control terminals of compensation transistors in multiple subpixels are electrically connected to the first output terminals of first gate drive circuits of multiple stages, the control terminals of reset transistors in multiple subpixels are electrically connected to the first output terminals of second gate drive circuits of multiple stages, and in the same subpixel, the frequency of the second gate control signal received by the reset transistor and the frequency of the first gate control signal received by the compensation transistor are the same.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to display devices.

[0002] This application claims the priority of a Chinese patent application with the application number 202410404491.X filed with the Chinese Patent Office on April 3, 2024, and all the contents of this application are incorporated herein by reference.

Background Art

[0003] In a pixel driving circuit, a compensation transistor and a reset transistor electrically connected to the control terminal of a driving transistor are usually controlled using gate control signals output from different stages of a gate driving circuit in the same gate driving unit, and the reset transistor is turned on before the compensation transistor, so that a reset signal can be applied to the control terminal of the driving transistor to realize the potential reset of the control terminal of the driving transistor. However, when the display panel is displayed using different display frequencies corresponding to different display areas, some sub-pixels corresponding to the frequency-divided positions in the display panel may cause display abnormality problems in the sub-pixels because the gate control signal used for the compensation transistor is at a low frequency while the gate control signal used for the reset transistor is still at a high frequency.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of this application provide a display device, which can improve the problem of display abnormality occurring in some sub-pixels corresponding to the frequency-divided positions in the display panel.

Means for Solving the Problems

[0005] Embodiments of the present application provide a display device comprising a display panel and a gate drive module. The display panel comprises a plurality of subpixels, at least one of which comprises a light-emitting element, a drive transistor, a compensation transistor, and a reset transistor, wherein the drive transistor is arranged to generate a drive current to drive the light-emitting element to emit light, the output terminal of the reset transistor and the output terminal of the compensation transistor are electrically connected to the control terminal of the drive transistor, the input terminal of the compensation transistor is electrically connected to the output terminal of the drive transistor, and the input terminal of the reset transistor is arranged to receive a reset signal. The gate drive module is electrically connected to the display panel and comprises a plurality of frequency division control lines for transmitting frequency division control signals, a first gate drive unit, and a second gate drive unit. The plurality of frequency division control signals include a first frequency division control signal and a second frequency division control signal. The first gate drive unit includes a plurality of cascaded first gate drive circuits, and the second gate drive unit includes a plurality of cascaded second gate drive circuits. The first gate drive circuits are configured to control the level of the generated first gate control signal based on the first frequency division control signal, and the second gate drive circuits are configured to control the level of the generated second gate control signal based on the second frequency division control signal. Here, both the first and second gate drive circuits include a first output terminal. The control terminals of the compensation transistors in the plurality of subpixels are electrically connected to the first output terminals of the first gate drive circuits in the plurality of stages to receive the plurality of first gate control signals. The control terminals of the reset transistors in the plurality of subpixels are electrically connected to the first output terminals of the second gate drive circuits in the plurality of stages to receive the plurality of second gate control signals. In the same subpixel, the frequency of the second gate control signal received by the reset transistor is the same as the frequency of the first gate control signal received by the compensation transistor. [Brief explanation of the drawing]

[0006] [Figure 1A] This is a schematic diagram showing the configuration of the display device provided by the embodiment of the present application. [Figure 1B] This is a schematic diagram showing the configuration of the display device provided by the embodiment of the present application.

[0007] [Figure 2A] This is a schematic diagram showing the configuration of subpixels provided by the embodiment of the present application. [Figure 2B] This is a schematic diagram showing the configuration of subpixels provided by the embodiment of the present application.

[0008] [Figure 3] This is a schematic diagram showing the connection between subpixels and gate drive modules provided by related technologies.

[0009] [Figure 4A] This is a timing diagram corresponding to subpixels provided by related technologies. [Figure 4B] This is a timing diagram corresponding to subpixels provided by related technologies.

[0010] [Figure 5A] This is a schematic diagram showing the configuration of the first gate drive unit and the second gate drive unit provided by the embodiment of the present application. [Figure 5B] This is a schematic diagram showing the configuration of the first gate drive unit and the second gate drive unit provided by the embodiment of the present application.

[0011] [Figure 6A] This is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present invention. [Figure 6B] This is a schematic diagram showing the configuration of a gate drive circuit provided by an embodiment of the present invention.

[0012] [Figure 7]It is a schematic diagram showing the display principle of a high-frequency image and a low-frequency image provided by an embodiment of the present application.

[0013] [Figure 8A] It is a timing diagram of a first gate control signal and a second gate control signal provided by an embodiment of the present application. [Figure 8B] It is a timing diagram of a first gate control signal and a second gate control signal provided by an embodiment of the present application. [Figure 8C] It is a timing diagram of a first gate control signal and a second gate control signal provided by an embodiment of the present application. [Figure 8D] It is a timing diagram of a first gate control signal and a second gate control signal provided by an embodiment of the present application.

[0014] [Figure 9] It is a timing diagram of a write frame and a hold frame corresponding to a sub-pixel provided by an embodiment of the present application.

Modes for Carrying Out the Invention

[0015] In order to make the object, technical solution and effects of the present application clearer and more definite, the present application will be further described in detail below with reference to the drawings and by way of examples. It should be understood that the specific examples described in this specification are only for the purpose of explaining the present application and are not intended to limit the present application.

[0016] This application provides a display device. The first gate driving unit includes a plurality of first gate driving circuits connected in cascade. The second gate driving unit includes a plurality of second gate driving circuits connected in cascade. The first gate driving circuit controls the level of the generated first gate control signal based on the first frequency division control signal. The second gate driving circuit controls the level of the generated second gate control signal based on the second frequency division control signal. The control terminals of the compensation transistors in the plurality of sub-pixels are electrically connected corresponding to the first output terminals that output the first gate control signals of the first gate driving circuits of the plurality of stages. The control terminals of the reset transistors in the plurality of sub-pixels are electrically connected corresponding to the first output terminals that output the second gate control signals of the second gate driving circuits of the plurality of stages. Thereby, the reset transistor and the compensation transistor are no longer controlled by the gate control signal generated by the same gate driving unit, and the compensation transistor and the reset transistor are controlled by the gate control signals generated by different gate driving units. As a result, the reset transistor in one sub-pixel and the compensation transistor in another sub-pixel no longer have a synchronous operation state under the control of the same gate control signal, and the operation states of the reset transistors and the compensation transistors in different sub-pixels are made independent. As a result, in the same sub-pixel in cooperation with the first frequency division control signal and the second frequency division control signal, the frequency of the second gate control signal received by the reset transistor is made the same as the frequency of the first gate control signal received by the compensation transistor, so as to improve the problem that display abnormalities occur in some sub-pixels corresponding to the frequency division positions in the display panel.

[0017] Specifically, FIGS. 1A to 1B are schematic diagrams showing the configuration of a display device provided by an embodiment of the present application. This application provides a display device, and the display device includes a display panel DP and a gate driving module GM, and the gate driving module GM is electrically connected to the display panel DP.

[0018] Optionally, the display panel DP includes a self-illuminating display panel.

[0019] The display panel DP includes multiple sub-pixels Spi, and the gate drive module GM is electrically connected to the multiple sub-pixels Spi, working together with the multiple sub-pixels Spi to realize the display function on the display panel DP.

[0020] Optionally, the display panel DP includes multiple scan lines, and the gate drive module GM is electrically connected to multiple subpixels Spi by multiple scan lines.

[0021] Figures 2A and 2B are schematic diagrams showing the configuration of a subpixel Spi provided by an embodiment of the present invention. At least one subpixel Spi includes a light-emitting element Di, a drive transistor Tdr, a compensation transistor Tc, and a reset transistor Tr.

[0022] Optionally, the light-emitting element Di includes light-emitting diodes. Optionally, the light-emitting element Di may include organic light-emitting diodes, sub-millimeter light-emitting diodes, micro-light-emitting diodes, etc.

[0023] The drive transistor Tdr and the light-emitting element Di are electrically connected between the first voltage terminal Vdd and the second voltage terminal Vss, and the drive transistor Tdr is positioned to generate a drive current to drive the drive light-emitting element Di to emit light.

[0024] Optionally, the input terminal of the drive transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the drive transistor Tdr is electrically connected to the anode of the light-emitting element Di, and the cathode of the light-emitting element Di is electrically connected to the second voltage terminal Vss, with the voltage supplied by the first voltage terminal Vdd being greater than the voltage supplied by the second voltage terminal Vss.

[0025] The input terminal of the reset transistor Tr is positioned to receive the reset signal transmitted by the reset line VLr, and the output terminal of the reset transistor Tr is electrically connected to the control terminal of the drive transistor Tdr.

[0026] The input terminal of the compensation transistor Tc is electrically connected to the output terminal of the drive transistor Tdr, and the output terminal of the compensation transistor Tc is electrically connected to the control terminal of the drive transistor Tdr.

[0027] Optionally, the compensation transistor Tc and reset transistor Tr may be silicon transistors or oxide transistors, and may be P-type transistors or N-type transistors. Optionally, to reduce leakage from the control terminal of the drive transistor Tdr to the output terminal of the drive transistor Tdr and the reset line VLr, the compensation transistor Tc and reset transistor Tr are oxide transistors. To fit existing process architectures, the compensation transistor Tc and reset transistor Tr are N-type transistors.

[0028] To make it easier to understand, the active layer of an oxide transistor contains indium gallium zinc oxide, etc.

[0029] Optionally, the multiple scan lines include multiple first scan lines GL1 and multiple second scan lines GL2, with the control terminals of the compensation transistors Tc in multiple sub-pixels Spi electrically connected to the multiple first scan lines GL1, and the control terminals of the reset transistors Tr in multiple sub-pixels Spi electrically connected to the multiple second scan lines GL2.

[0030] Continuing with reference to Figures 1A-1B and 2A-2B, the display panel DP includes multiple data lines DL, and at least one sub-pixel Spi further includes a data transistor Tda, the input terminal of which the data transistor Tda is arranged to receive data signals transmitted by the data line DL to which it is electrically connected, and the output terminal of the data transistor Tda is electrically connected to the input terminal of the drive transistor Tdr.

[0031] Optionally, the multiple scan lines include multiple third scan lines GL3, and the control terminals of the data transistor Tda in multiple sub-pixels Spi are electrically connected to the multiple third scan lines GL3. The display device includes a source drive chip SDC, which is connected to multiple data lines DL and outputs multiple data signals.

[0032] Continuing with reference to Figures 2A and 2B, at least one subpixel Spi further includes a first initial transistor Ti1, a first light emission control transistor Te1, a second light emission control transistor Te2, and a first storage capacitor Cst1.

[0033] The input terminal of the first initial transistor Ti1 is positioned to receive the first initial signal transmitted by the first primary line VL1, and the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light-emitting element Di.

[0034] The input terminal of the first light emission control transistor Te1 is electrically connected to the first voltage terminal Vdd, and the output terminal of the first light emission control transistor Te1 is electrically connected to the input terminal of the drive transistor Tdr.

[0035] The input terminal of the second light emission control transistor Te2 is electrically connected to the output terminal of the drive transistor Tdr, and the output terminal of the second light emission control transistor Te2 is electrically connected to the anode of the light-emitting element Di.

[0036] The first terminal of the first storage capacitor Cst1 is electrically connected to the first voltage terminal Vdd, and the second terminal of the first storage capacitor Cst1 is electrically connected to the control terminal of the drive transistor Tdr.

[0037] Optionally, multiple scan lines include multiple fourth scan lines GL4 and multiple light emission control lines EL, the multiple fourth scan lines GL4 being electrically connected to the control terminals of the first initial transistor Ti1 in multiple sub-pixels Spi, and the multiple light emission control lines EL being electrically connected to the control terminals of the first light emission control transistor Te1 and the second light emission control transistor Te2 in multiple sub-pixels Spi.

[0038] Optionally, referring to Figure 2B, the sub-pixel Spi further includes a second storage capacitor Cst2, the first terminal of which is electrically connected to the control terminal of the data transistor Tda, and the second terminal of which is electrically connected to the control terminal of the drive transistor Tdr.

[0039] Optionally, to improve the threshold voltage shift of the drive transistor Tdr due to the switching of the display frequency, the sub-pixel Spi further includes a second initial transistor Ti2, the input terminal of the second initial transistor Ti2 is positioned to receive the second initial signal transmitted by the second primary line VL2, and the output terminal of the second initial transistor Ti2 is electrically connected to the input terminal of the drive transistor Tdr, as shown in Figure 2B.

[0040] Optionally, multiple fourth scan lines GL4 are electrically connected to the control terminals of the second initial transistor Ti2 in multiple subpixels Spi.

[0041] Figure 3 is a schematic diagram showing the connection between a subpixel and a gate drive module provided by the related technology. In the related technology, the gate drive module GM includes a first subgate drive unit gm1, a second subgate drive unit gm2, and a third subgate drive unit gm3, wherein the first subgate drive unit gm1 includes a plurality of cascaded first subgate drive circuits ga1, the second subgate drive unit gm2 includes a plurality of cascaded second subgate drive circuits ga2, and the third subgate drive unit gm3 includes a plurality of cascaded third subgate drive circuits ga3. The plurality of first subgate drive circuits ga1 are arranged to provide gate control signals to reset transistors Tr and compensation transistors Tc in a plurality of subpixels Spi, the plurality of second subgate drive circuits ga2 are arranged to provide gate control signals to second initial transistors Ti2 in a plurality of subpixels Spi, and the plurality of third subgate drive circuits ga3 are arranged to provide light emission control signals to first light emission control transistors Te1 and second light emission control transistors Te2 in a plurality of subpixels Spi. The data transistor Tda may be controlled by a gate control signal output from the first subgate drive unit gm1, or by a gate control signal output from another gate drive unit. The first initial transistor Ti1 may share a gate control signal provided by the same gate drive unit as the data transistor Tda, or a third subgate drive unit gm3 may provide the corresponding gate control signal. Here, in the same subpixel Spi, the gate control signal received by the control terminal of the compensation transistor Tc and the gate control signal received by the control terminal of the reset transistor Tr are generated by first sub-drive circuits of different stages. For example, in a display panel DP, the gate control signal received by the control terminal of the reset transistor Tr in the nth row of subpixels Spi is generated by the first sub-gate drive circuit of the (n-2)th stage, and the gate control signal received by the control terminal of the compensation transistor Tc in the nth row of subpixels Spi is generated by the first sub-gate drive circuit of the nth stage.The first subgate drive unit GM1 adopts a design configuration that drives from both sides.

[0042] Figures 4A and 4B are timing diagrams corresponding to subpixels provided by the relevant technology. Here, Pscan is the gate control signal received by the control terminals of the first initial transistor Ti1 and the second initial transistor Ti2, Pscan_T2 is the gate control signal received by the control terminal of the data transistor Tda, Nscan_T3 is the gate control signal received by the control terminal of the compensation transistor Tc, Nscan_T4 is the gate control signal received by the control terminal of the reset transistor Tr, and EM is the gate control signal received by the control terminals of the first light emission control transistor Te1 and the second light emission control transistor Te2.

[0043] Here, when the sub-pixel Spi is displayed using the timing diagram shown in Figure 4A, the gate control signals corresponding to the reset transistor Tr and the compensation transistor Tc have two effective pulses. Therefore, the display panel DP cannot achieve region division and frequency division display when using the timing shown in Figure 4A. When a sub-pixel Spi is displayed using the timing diagram shown in Figure 4B, even if the gate control signals corresponding to the reset transistor Tr and the compensation transistor Tc have one effective pulse, in the same sub-pixel Spi, the gate control signal received by the control terminal of the compensation transistor Tc and the gate control signal received by the control terminal of the reset transistor Tr are provided by the first sub-gate drive circuit ga1 of different stages, and the reset transistor Tr is turned on before the compensation transistor Tc. As a result, in some rows corresponding to the position of the frequency division in the display panel DP, the reset transistor Tr in the sub-pixel Spi is turned on based on the corresponding gate control signal, causing the potential of the control terminal of the drive transistor Tdr to be reset, while the compensation transistor Tc remains off because the corresponding gate control signal is at a low frequency. Consequently, no new data information is stored in the sub-pixel Spi, the original data signal is not held at the control terminal of the drive transistor Tdr, and as a result, a display abnormality occurs in the sub-pixel Spi.

[0044] The present invention provides a display device that enables region division and frequency division display on a display panel DP, and improves the problem of display abnormalities occurring in some rows of subpixels Spi corresponding to the frequency division positions on the display panel DP.

[0045] Continuing with Figures 1A and 1B, the gate drive module GM includes multiple frequency division control lines FL, a first gate drive unit GM1, and a second gate drive unit GM2.

[0046] Multiple frequency division control lines FL transmit multiple frequency division control signals, each of which includes a first frequency division control signal NF1 and a second frequency division control signal NF2.

[0047] The first gate drive unit GM1 includes a plurality of cascaded first gate drive circuits GA1, which are arranged to control the level of a first gate control signal Nscan1 generated based on a first frequency division control signal NF1.

[0048] The second gate drive unit GM2 includes a plurality of cascaded second gate drive circuits GA2, which are arranged to control the level of a second gate control signal Nscan2 generated based on a second frequency division control signal NF2.

[0049] Here, both the first gate drive circuit GA1 and the second gate drive circuit GA2 include a first output terminal O1. The first output terminal O1 of the first gate drive circuit GA1 outputs a first gate control signal Nscan1, and the first output terminal O1 of the second gate drive circuit GA2 outputs a second gate control signal Nscan2.

[0050] Optionally, the first output terminal O1 of multiple first gate drive circuits GA1 is electrically connected to multiple sub-pixels Spi by multiple first scan lines GL1, and the first output terminal O1 of multiple second gate drive circuits GA2 is electrically connected to multiple sub-pixels Spi by multiple second scan lines GL2.

[0051] Continuing with reference to Figures 1A-1B and 2A-2B, the control terminals of the compensation transistors Tc in multiple sub-pixels Spi are electrically connected to the first output terminals O1 of the first gate drive circuits GA1 of multiple stages, and the control terminals of the reset transistors Tr in multiple sub-pixels Spi are electrically connected to the first output terminals O1 of the second gate drive circuits GA2 of multiple stages. As a result, the reset transistors Tr and compensation transistors Tc are no longer controlled by the same gate control signal generated by the same gate drive unit, and are instead controlled by gate control signals generated by different gate drive units. Consequently, the reset transistor Tr in one sub-pixel Spi and the compensation transistor Tc in another sub-pixel Spi will no longer be in a synchronous operation state controlled by the same gate control signal, and the operating states of the reset transistors Tr and compensation transistors Tc in different sub-pixels Spi will be independent. Furthermore, since the first gate drive circuit GA1 can implement level control of the first gate control signal Nscan1 based on the first frequency division control signal NF1, and the second gate drive circuit GA2 can implement level control of the second gate control signal Nscan2 based on the second frequency division control signal NF2, the first frequency division control signal NF1 and the second frequency division control signal NF2 ensure that in the same sub-pixel Spi, the frequency of the second gate control signal Nscan2 received by the reset transistor Tr and the frequency of the first gate control signal Nscan1 received by the compensation transistor Tc are the same. As a result, in the same sub-pixel Spi, the on frequencies of the reset transistor Tr and the compensation transistor Tc are the same, and consequently, some sub-pixel Spi corresponding to the frequency division position in the display panel DP will have a problem of display abnormalities in the sub-pixel Spi because the gate control signal used for the reset transistor Tr is still at a high frequency when the gate control signal used for the compensation transistor Tc is at a low frequency.

[0052] Optionally, referring to Figures 1A and 1B, the display panel DP includes a display area AA and a first non-display area DA1 and a second non-display area DA2 located on opposite sides of the display area AA. Here, multiple subpixels Spi are located in the display area AA, the first gate drive unit GM1 is located in the first non-display area DA1, and the second gate drive unit GM2 is located in the second non-display area DA2. By having the first gate drive unit GM1 and the second gate drive unit GM2 located in the first non-display area DA1 and the second display area DA2, respectively, the bezel size of the display panel DP can be reduced.

[0053] Accordingly, the control terminals of the compensation transistors Tc in multiple sub-pixels Spi are electrically connected to the first output terminals O1 of the first gate drive circuits GA1 of multiple stages, and the control terminals of the reset transistors Tr in multiple sub-pixels Spi are electrically connected to the first output terminals O1 of the second gate drive circuits GA2 of multiple stages. This enables a one-sided drive design for the compensation transistors Tc in multiple sub-pixels Spi, and a one-sided drive design for the reset transistors Tr in multiple sub-pixels Spi. In other words, the first gate drive circuits GA1 of multiple stages are electrically connected to the control terminals of the compensation transistors Tc in multiple sub-pixels Spi in a one-sided drive manner, and the second gate drive circuits GA2 of multiple stages are electrically connected to the control terminals of the reset transistors Tr in multiple sub-pixels Spi in a one-sided drive manner. This is advantageous in reducing the bezel size of the display panel DP.

[0054] Optionally, to reduce power consumption and decrease the bezel size of the display panel DP, a single gate drive circuit may be configured to output multiple gate control signals simultaneously. Accordingly, the multiple gate control signals output from a single gate drive circuit may be used to control the on-states of different transistors in the same sub-pixel Spi.

[0055] For example, the first gate drive circuit GA1 includes a second output terminal O2, and the second output terminal O2 of the first gate drive circuit GA1 outputs a third gate control signal Pscan1. Here, the control terminals of the data transistors Tda in multiple sub-pixels Spi are electrically connected to the second output terminals O2 of multiple first gate drive circuits GA1, so that the data transistors Tda in multiple sub-pixels Spi are controlled by the third gate control signal Pscan1 output from multiple first gate drive circuits GA1.

[0056] For example, the second gate drive circuit GA2 includes a second output terminal O2, and the second output terminal O2 of the second gate drive circuit GA2 outputs a fourth gate control signal Pscan2. Here, the control terminals of the data transistors Tda in multiple sub-pixels Spi are electrically connected to the second output terminals O2 of multiple second gate drive circuits GA2, so that the data transistors Tda in multiple sub-pixels Spi are controlled by the fourth gate control signal Pscan2 output from the multiple second gate drive circuits GA2.

[0057] For example, both the first gate drive circuit GA1 and the second gate drive circuit GA2 include a second output terminal O2, with the second output terminal O2 of the first gate drive circuit GA1 outputting a third gate control signal Pscan1, and the second output terminal O2 of the second gate drive circuit GA2 outputting a fourth gate control signal Pscan2. Meanwhile, the control terminals of the data transistors Tda in multiple sub-pixels Spi are electrically connected to the second output terminals O2 of multiple first gate drive circuits GA1 and / or the second output terminals O2 of multiple second gate drive circuits GA2.

[0058] That is, in one sub-pixel Spi, the control terminal of the data transistor Tda may be electrically connected to the second output terminal O2 of the corresponding first gate drive circuit GA1, or to the second output terminal O2 of the corresponding second gate drive circuit GA2, or to the second output terminal O2 of the corresponding first gate drive circuit GA1 and the second output terminal O2 of the corresponding second gate drive circuit GA2. Therefore, in one sub-pixel Spi, if the control terminal of the data transistor Tda is electrically connected to the second output terminal O2 of the corresponding first gate drive circuit GA1, or to the second output terminal O2 of the corresponding second gate drive circuit GA2, a one-sided drive design is formed. In one sub-pixel Spi, if the control terminal of the data transistor Tda is electrically connected to the second output terminal O2 of the corresponding first gate drive circuit GA1 and the second output terminal O2 of the corresponding second gate drive circuit GA2, a two-sided drive design is formed. Optionally, the second output terminal O2 of multiple first gate drive circuits GA1 are electrically connected to multiple sub-pixels Spi by multiple third scan lines GL3. The second output terminal O2 of multiple second gate drive circuits GA2 is electrically connected to multiple subpixels Spi by multiple third scan lines GL3.

[0059] Figures 5A to 5B are schematic diagrams showing the configurations of the first gate drive unit and the second gate drive unit provided by the embodiment of the present application. Figures 6A to 6B are schematic diagrams showing the configuration of the gate drive circuit provided by the embodiment of the present application. Here, the circuit configuration of at least one of the first gate drive circuit GA1 and the second gate drive circuit GA2 is shown in Figures 6A to 6B. In Figures 6A to 6B, O21 and O22 both indicate the second output terminal, and Cka and CKb both indicate the second clock signal.

[0060] At least one of the first gate drive circuit GA1 and the second gate drive circuit GA2 includes a node control module 10, a first frequency division control module 20, and a first output module 30.

[0061] The node control module 10 is electrically connected to the first node K1 of the gate drive circuit of the current stage, and the node control module 10 is configured to control the signals of the first node K1 based on the corresponding start signal STV and first clock signal XCK.

[0062] Optionally, referring to Figures 5A to 5B, in the multiple first gate drive circuits GA1, the first stage first gate drive circuit GA1(1) uses the first initial signal stv1 as the start signal STV, and controls the signal at the first node K1 of the first stage first gate drive circuit GA1(1) based on the corresponding first clock signal XCK and the first initial signal stv1. In the multiple second gate drive circuits GA2, the first stage second gate drive circuit GA2(1) uses the second initial signal stv2 as the start signal STV, and controls the signal at the first node K1 of the first stage second gate drive circuit GA2(1) based on the corresponding first clock signal XCK and the second initial signal stv2.

[0063] Optionally, in a plurality of first gate drive circuits GA1, the first gate drive circuit GA1(M) of the M stage uses the first gate control signal Nscan1(MA) output from the first gate drive circuit GA1(MA) of the MA stage as a start signal STV, and controls the signal at the first node K1 of the first gate drive circuit GA1(M) of the M stage based on the corresponding first clock signal XCK and the first gate control signal Nscan1(MA) output from the first gate drive circuit GA1(MA) of the MA stage. Here, M>1 and A≧1. In a plurality of second gate drive circuits GA2, the Nth-th stage second gate drive circuit GA2(N) uses the Nscan2(NB) second gate control signal for the NB stage, output from the NB-th stage second gate drive circuit GA2(NB), as a start signal STV, and causes the Nth-th stage second gate drive circuit GA2(N) to control the signal at the first node K1 of the Nth-th stage second gate drive circuit GA2(N) based on the corresponding first clock signal XCK and the Nscan2(NB) second gate control signal for the NB stage, output from the NB-th stage second gate drive circuit GA2(NB). Here, N>1 and B≧1.

[0064] For example, the first gate control signal Nscan1(1) of the first stage, output from the first output terminal O1 of the first gate drive circuit GA1(1) of the first stage, is used as a start signal STV by the first gate drive circuit GA1 of the second stage. Similarly, a cascaded configuration of multiple second gate drive circuits GA2 can be further obtained.

[0065] Furthermore, in gate drive circuits of multiple stages, the gate drive circuit of the preceding M stage is called a virtual gate drive circuit (for example, the gate drive circuit enclosed by a dotted line in the gate drive unit in Figures 1A and 1B), and it provides a start signal STV corresponding to the gate drive circuits that are cascaded thereafter.

[0066] Optionally, referring to Figures 6A to 6B, the configuration of the node control module 10 will be described using one of the first gate drive circuits GA1(p) and the second gate drive circuit GA2(p) of the p-th stage as an example. Here, if Figures 6A to 6B correspond to the first gate drive circuit GA1(p) of the p-th stage, O1(p-1) indicates the first output terminal of the first gate drive circuit GA1(p-1) of the p-1th stage. If Figures 6A to 6B correspond to the second gate drive circuit GA2(p) of the p-th stage, O1(p-1) indicates the first output terminal of the second gate drive circuit GA2(p-1) of the p-1th stage. Here, p≧1. If p=1, then O1(p-1) corresponds to the first initial signal stv1 or the second initial signal stv2.

[0067] As shown in Figures 6A to 6B, the node control module 10 includes a first transistor T1, a second transistor T2, and a third transistor T3.

[0068] The first and second control terminals of the first transistor T1 are arranged to receive the corresponding start signal STV, and the input terminal of the first transistor T1 is electrically connected to the first power supply terminal PVGL.

[0069] The control terminal of the second transistor T2 is electrically connected to the first control terminal of the first transistor T1, the input terminal of the second transistor T2 is electrically connected to the second power supply terminal PVGH, and the output terminal of the second transistor T2 is electrically connected to the output terminal of the first transistor T1.

[0070] The control terminal of the third transistor T3 is positioned to receive the corresponding first clock signal XCK, the input terminal of the third transistor T3 is electrically connected to the output terminal of the first transistor T1, and the output terminal of the third transistor T3 is electrically connected to the first node K1.

[0071] Optionally, the node control module 10 is further electrically connected to the third node K3 of the gate drive circuit of the current stage, and the node control module 10 is configured to control the electrical connection between the second power supply terminal PVGH or the third power supply terminal NVGL and the first node K1 based on the potential of the third node K3.

[0072] Optionally, the node control module 10 includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0073] The first and second control terminals of the fourth transistor T4 are arranged to receive the corresponding first clock signal XCK, and the output terminal of the fourth transistor T4 is electrically connected to the first node K1. The control terminals of the fifth transistor T5 and the first and second control terminals of the sixth transistor T6 are electrically connected to the third node K3, the input terminal of the fifth transistor T5 is electrically connected to the second power supply terminal PVGH, the output terminal of the fifth transistor T5 is electrically connected to the input terminal of the fourth transistor T4, the input terminal of the sixth transistor T6 is electrically connected to the third power supply terminal NVGL, and the output terminal of the sixth transistor T6 is electrically connected to the first node K1.

[0074] Continuing with reference to Figures 6A to 6B, the node control module 10 is configured to control signal transmission between the first power terminal PVGL or the second power terminal PVGH and the third node K3 based on the signal from the first node K1.

[0075] Optionally, the node control module 10 further includes a seventh transistor T7 and an eighth transistor T8.

[0076] The first and second control terminals of the seventh transistor T7 are electrically connected to the first node K1, the input terminal of the seventh transistor T7 is electrically connected to the first power supply terminal PVGL, the output terminal of the seventh transistor T7 is electrically connected to the third node K3, the control terminal of the eighth transistor T8 is electrically connected to the first node K1, the input terminal of the eighth transistor T8 is electrically connected to the second power supply terminal PVGH, and the output terminal of the eighth transistor T8 is electrically connected to the third node K3.

[0077] Continuing with reference to Figures 6A to 6B, the first frequency division control module 20 is electrically connected to the first node K1, the second node K2, and the third node K3 of the gate drive circuit of the current stage, and the first frequency division control module 20 is configured to control signal transmission between the first node K1 and the second node K2 based on the signal from the third node K3 and the corresponding frequency division control signal.

[0078] Optionally, the first frequency division control module 20 includes a first frequency division transistor Tf1, a second frequency division transistor Tf2, and a first capacitor C1.

[0079] The control terminal of the first frequency division transistor Tf1 is electrically connected to the third node K3 of the gate drive circuit of the current stage, and the input terminal of the first frequency division transistor Tf1 is positioned to receive the corresponding frequency division control signal (i.e., the input terminal of the first frequency division transistor Tf1 in the first gate drive circuit GA1 is positioned to receive the first frequency division control signal NF1, and the input terminal of the first frequency division transistor Tf1 in the second gate drive circuit GA2 is positioned to receive the second frequency division control signal NF2).

[0080] The control terminal of the second frequency division transistor Tf2 is electrically connected to the output terminal of the first frequency division transistor Tf1, the input terminal of the second frequency division transistor Tf2 is electrically connected to the first node K1, and the output terminal of the second frequency division transistor Tf2 is electrically connected to the second node K2.

[0081] The first terminal of the first capacitor C1 is electrically connected to the control terminal of the second frequency division transistor Tf2, and the second terminal of the first capacitor C1 is electrically connected to the second node K2.

[0082] Continuing with Figures 6A to 6B, the first output module 30 is electrically connected to the first node K1, the second node K2, and the first output terminal O1. The first output module 30 is configured to control the gate control signal output from the first output terminal O1 based on the signals from the first node K1 and the second node K2.

[0083] Optionally, the first output module 30 includes a first output transistor To1 and a second output transistor To2.

[0084] The first and second control terminals of the first output transistor To1 are electrically connected to the first node K1, and the input terminal of the first output transistor To1 is electrically connected to the third power supply terminal NVGL.

[0085] The control terminal of the second output transistor To2 is electrically connected to the second node K2, the input terminal of the second output transistor To2 is electrically connected to the fourth power supply terminal NVGH, and the output terminal of the second output transistor To2 and the output terminal of the first output transistor To1 are electrically connected to the first output terminal O1 of the gate drive circuit of the current stage.

[0086] Optionally, one first frequency division control signal NF1 is provided for each first gate drive circuit GA1 to achieve level control for the first gate control signal Nscan1 output from each first gate drive circuit GA1. Similarly, one second frequency division control signal NF2 is provided for each second gate drive circuit GA2 to achieve level control for the second gate control signal Nscan2 output from each second gate drive circuit GA2.

[0087] Optionally, to reduce the number of frequency division control signals used in the display device, the same frequency division control signal is shared among the first frequency division control modules 20 in multiple cascaded first gate drive circuits GA1 to achieve level control for multiple first gate control signals Nscan1. Similarly, the same frequency division control signal is shared among the first frequency division control modules 20 in multiple cascaded second gate drive circuits GA2 to achieve level control for multiple second gate control signals Nscan2.

[0088] In order to enable the display panel DP to display using frequency division, the on-times of the compensation transistor Tc and the reset transistor Tr are different within the same sub-pixel Spi. Consequently, the frequency division control signal used to control the first frequency division control module 20 in multiple cascaded second gate drive circuits GA2 is different from the frequency division control signal used to control the first frequency division control module 20 in multiple cascaded first gate drive circuits GA1.

[0089] Specifically, referring to Figures 5A to 5B, the multiple frequency division control lines FL include a first frequency division control line FL1 and a second frequency division control line FL2, with the first frequency division control line FL1 transmitting the first frequency division control signal NF1 and the second frequency division control line FL2 transmitting the second frequency division control signal NF2. The first frequency division control module 20 in the first gate drive circuit GA1 of multiple stages is electrically connected to the first frequency division control line FL1, and the first frequency division control module 20 in the second gate drive circuit GA2 of multiple stages is electrically connected to the second frequency division control line FL2, thereby reducing the number of frequency division control signals used in the display device and making the operating states of the compensation transistor Tc and reset transistor Tr in the multiple sub-pixels Spi independent.

[0090] Optionally, referring further to Figures 6A and 6B, at least one gate drive circuit further includes a first control module 40, which is electrically connected to a third node K3 of the current stage gate drive circuit and a second node K2 of the current stage gate drive circuit GDC, and the first control module 40 is configured to control signal transmission between a second power supply terminal PVGH and a second node K2 based on the corresponding first clock signal XCK and the potential of the third node K3.

[0091] Optionally, the first control module 40 includes a ninth transistor T9 and a tenth transistor T10.

[0092] The first and second control terminals of the ninth transistor T9 are arranged to receive the corresponding first clock signal XCK, and the output terminal of the ninth transistor T9 is electrically connected to the second node K2.

[0093] The control terminal of the 10th transistor T10 is electrically connected to the 3rd node K3 of the gate drive circuit of the current stage, the input terminal of the 10th transistor T10 is electrically connected to the 2nd power supply terminal PVGH, and the output terminal of the 10th transistor T10 is electrically connected to the input terminal of the 9th transistor T9.

[0094] Since the gate control signal received by the control terminal of the data transistor Tda can be provided by at least one of the first gate drive unit GM1 and the second gate drive unit GM2, at least one of the first gate drive circuit GA1 included in the first gate drive unit GM1 and the second gate drive circuit GA2 included in the second gate drive unit GM2 may further include a second output module 50, thereby providing the necessary gate control signal to the data transistor Tda in the corresponding subpixel Spi via the second output module 50.

[0095] The second output module 50 is electrically connected to the first node K1, the third node K3, and the second output terminal O2 of the gate drive circuit of the current stage. The second output module 50 is configured to control the gate control signal output from the second output terminal O2 based on the signals from the first node K1 and the third node K3, and the corresponding second clock signal CK. Referring further to Figures 6A and 6B, the second output module 50 includes a third output transistor To3, a fourth output transistor To4, and a second capacitor C2.

[0096] The control terminal of the third output transistor To3 is electrically connected to the first node K1, and the input terminal of the third output transistor To3 is positioned to receive the corresponding second clock signal CK.

[0097] The control terminal of the fourth output transistor To4 is electrically connected to the third node K3, the input terminal of the fourth output transistor To4 is electrically connected to the second power supply terminal PVGH, and the output terminal of the fourth output transistor To4 and the output terminal of the third output transistor To3 are electrically connected to the second output terminal O2 of the gate drive circuit GDC of the current stage.

[0098] The first terminal of the second capacitor C2 is electrically connected to the control terminal of the third output transistor To3, and the second terminal of the second capacitor C2 is electrically connected to the second output terminal O2 of the gate drive circuit GDC of the current stage.

[0099] Optionally, the first gate drive circuit GA1 includes X second output modules 50 and X second output terminals O2, where each second output module 50 is electrically connected to one second output terminal O2, and X ≥ 1.

[0100] That is, as shown in Figure 6A, one first gate drive circuit GA1 includes one second output module 50 such that one first gate drive circuit GA1 simultaneously outputs one first gate control signal Nscan1 and one third gate control signal Pscan1.

[0101] Optionally, to reduce the bezel size of the display panel DP, as shown in Figure 6B, one first gate drive circuit GA1 includes multiple second output modules 50 such that one first gate drive circuit GA1 simultaneously outputs one first gate control signal Nscan1 and multiple third gate control signals Pscan1.

[0102] Optionally, in order to improve the utilization rate of multiple second output modules 50 in the first gate drive circuit GA1, if the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X > 1), the X second output modules 50 in the same first gate drive circuit GA1 are arranged to output multiple third gate control signals Pscan1 with a phase difference, so that the data transistor Tda driven by the multiple third gate control signals Pscan1 output from the same first gate drive circuit GA1 can be turned on within different time periods, thereby reducing the power consumption of the display device.

[0103] Similarly, the second gate drive circuit GA2 includes X second output modules 50 and X second output terminals O2, where each second output module 50 is electrically connected to one second output terminal O2, where X ≥ 1.

[0104] That is, as shown in Figure 6A, one second gate drive circuit GA2 includes one second output module 50 such that one second gate drive circuit GA2 simultaneously outputs one second gate control signal Nscan2 and one fourth gate control signal Pscan2.

[0105] Optionally, to reduce the bezel size of the display panel DP, as shown in Figure 6B, one second gate drive circuit GA2 includes multiple second output modules 50 such that one second gate drive circuit GA2 simultaneously outputs one second gate control signal Nscan2 and multiple fourth gate control signals Pscan2.

[0106] Optionally, in order to improve the utilization rate of multiple second output modules 50 in the second gate drive circuit GA2, if the second gate drive circuit GA2 includes multiple second output modules 50 (i.e., X > 1), the X second output modules 50 in the same second gate drive circuit GA2 are arranged to output multiple fourth gate control signals Pscan2 with a phase difference, so that the data transistor Tda driven by the multiple fourth gate control signals Pscan2 output from the same second gate drive circuit GA2 can be turned on within different time periods, thereby reducing the power consumption of the display device.

[0107] Optionally, each second output terminal O2 is electrically connected to the control terminal of the data transistor Tda in at least one row of sub-pixels Spi, thereby allowing each third gate control signal Pscan1 output from the first gate drive circuit GA1, or each fourth gate control signal Pscan2 output from the second gate drive circuit GA2, to drive the data transistor Tda in at least one row of sub-pixels Spi.

[0108] Optionally, the phase difference of the first clock signals corresponding to the adjacent two-stage first gate drive circuits GA1 and the phase difference of the first clock signals corresponding to the adjacent two-stage second gate drive circuits GA2 is XH, so that multiple rows of subpixels Spi are driven sequentially at the same time interval by corresponding gate control signals. Here, H is the unit time length of the display.

[0109] Optionally, H may be set to the corresponding time length of the row period.

[0110] Optionally, each third gate control signal Pscan1 output from the first gate drive circuit GA1 and / or each fourth gate control signal Pscan2 output from the second gate drive circuit GA2 can drive the data transistor Tda in one row of sub-pixels Spi, and the control terminals of the data transistor Tda in the L to L+X-1 rows of sub-pixels Spi are electrically connected to the X second output terminals O2 in the first gate drive circuit GA1 of the K stage and / or the X second output terminals O2 in the second gate drive circuit GA2 of the K stage, where K≧1 and L=XK-(X-1). For example, the first gate drive circuit GA1 and the second gate drive circuit GA2 each include one second output module 50 (i.e., X=1), and at least one of the second output terminal O2 of the first gate drive circuit GA1(K) in the K stage and the second output terminal O2 of the second gate drive circuit GA2(K) in the K stage is electrically connected to the control terminal of the data transistor Tda in the L row (i.e., the K row) subpixel Spi, so that the data transistor Tda in multiple subpixels Spi can be matched with the gate control signals used for the compensation transistor Tc and the reset transistor Tr, thereby performing the transmission of data signals.

[0111] For example, both the first gate drive circuit GA1 and the second gate drive circuit GA2 each have two second output modules 50 (i.e., X=2), and at least one of the second output terminal O2 of the first gate drive circuit GA1(K) in the K stage and the second output terminal O2 of the second gate drive circuit GA2(K) in the K stage is electrically connected to the control terminal of the data transistor Tda in the L row (i.e., the 2K-1 row) to the L+1 row (i.e., the 2K row) sub-pixels Spi, and performs the transmission operation of gate control signals and data signals used for the matching compensation transistor Tc and reset transistor Tr of the data transistor Tda in multiple sub-pixels Spi.

[0112] Optionally, depending on the number of second output modules 50 of the gate drive unit, the compensation transistor Tc and reset transistor Tr are controlled to use gate control signals for different stages, thereby enabling the refresh of the display data of the sub-pixel Spi.

[0113] For example, continuing to refer to Figure 1A, the first gate drive circuit GA1 and the second gate drive circuit GA2 each include one second output module 50 (i.e., X=1), the control terminal of the compensation transistor Tc in the sub-pixel Spi of the L row is electrically connected to the first output terminal O1 of the first gate drive circuit GA1 in the K+A stage, and the control terminal of the reset transistor Tr in the sub-pixel Spi of the L row is electrically connected to the first output terminal O1 of the second gate drive circuit GA2 in the KB stage. Here, A≧1 and B≧1.

[0114] Furthermore, the first gate drive circuit GA1(K+A) in the K+A stage is the first gate drive circuit GA1 that is cascaded from the first gate drive circuit GA1(K) of the K stage onwards, and whose stage difference with the first gate drive circuit GA1(K) of the K stage is A. The second gate drive circuit GA2(KB) in the KB stage is the second gate drive circuit GA2 that is cascaded before the second gate drive circuit GA2(K) of the K stage, and whose stage difference with the second gate drive circuit GA2(K) of the K stage is B. Therefore, when K=1, the second gate drive circuit GA2(KB) in the KB stage is the second gate drive circuit GA2 that is cascaded before the second gate drive circuit GA2(1) of the first stage, and whose stage difference with the second gate drive circuit GA2(1) of the first stage is B. Therefore, the second gate drive circuit GA2 in the first stage of the second gate drive circuit GA2 does not necessarily have to be the same as the second gate drive circuit GA2(1) in the first stage.

[0115] Optionally, A=1 and B=3. That is, the control terminal of the compensation transistor Tc in the sub-pixel Spi of the Kth row is electrically connected to the first output terminal O1 of the first gate drive circuit GA1(K+1) of the K+1 stage, and the control terminal of the reset transistor Tr in the sub-pixel Spi of the Kth row is electrically connected to the first output terminal O1 of the second gate drive circuit GA2(K-3) of the K-3 stage. As a result, the display panel DP can control multiple sub-pixels Spi using the gate control signals received by the compensation transistor Tc and the reset transistor Tr to realize region division and frequency division display.

[0116] On the other hand, if the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X≧2), the control terminal of the compensation transistor Tc in the sub-pixel Spi of the L row to the L+X-1 row is electrically connected to the first output terminal O1 of the first gate drive circuit GA1 of the K+C stage. Here, C≧0.

[0117] For example, continuing to refer to Figure 1B, the first gate drive circuit GA1 includes two second output modules 50, and the control terminal of the compensation transistor Tc in the subpixel Spi of the L row (i.e., corresponding to row 2K-1) to the L+X-1 row (i.e., corresponding to row 2K) is electrically connected to the first output terminal O1 of the first gate drive circuit GA1 of the K stage (i.e., C=0).

[0118] Furthermore, for example, the first gate drive circuit GA includes three second output modules 50, and the control terminals of the compensation transistors Tc in the sub-pixels Spi of the L row (i.e., corresponding to row 3K-2) to the L+X-1 row (i.e., corresponding to row 3K) are electrically connected to the first output terminal O1 of the first gate drive circuit GA1 of the K stage.

[0119] The control terminal of the compensation transistor Tc in the sub-pixel Spi of the L row is electrically connected to the first output terminal O1 of the first gate drive circuit GA1 of the K+A stage, and the control terminal of the reset transistor Tr in the sub-pixel Spi of the L row is electrically connected to the first output terminal O1 of the second gate drive circuit GA2 of the KB stage. Here, A≧1 and B≧1.

[0120] On the other hand, if the second gate drive circuit GA2 includes multiple second output modules 50 (i.e., X≧2), the control terminal of the reset transistor Tr in the L-th row subpixel Spi is electrically connected to the first output terminal O1 of the second gate drive circuit GA2 in the KD stage. Here, D≧0.

[0121] For example, continuing to refer to Figure 1B, the second gate drive circuit GA2 includes two second output modules 50, and the control terminal of the compensation transistor Tc in the subpixel Spi of the L row (i.e., corresponding to row 2K-1) to the L+X-1 row (i.e., corresponding to row 2K) is electrically connected to the first output terminal O1 of the second gate drive circuit GA2 of the K-2 stage (i.e., D=2).

[0122] Furthermore, for example, the second gate drive circuit GA2 includes three second output modules 50, and the control terminal of the reset transistor Tr in the sub-pixel Spi of the L row (i.e., corresponding to row 3K-2) to the L+X-1 row (i.e., corresponding to row 3K) is electrically connected to the first output terminal O1 of the second gate drive circuit GA2 of the K-2 stage.

[0123] Optionally, to further reduce the power consumption of the display device, the first gate drive circuit GA1 and / or the second gate drive circuit GA2, which include a second output module 50, further include a second frequency division control module 60 to provide frequency control for the gate control signal output from the second output terminal O2 of the gate drive circuit.

[0124] The second frequency division control module 60 is electrically connected to the node control module 10 by the first node K1 and the third node K3 of the gate drive circuit of the current stage, and is electrically connected to the second output module 50 by the fourth node K4 of the gate drive circuit of the current stage. The second frequency division control module 60 is configured to control signal transmission between the first node K1 and the fourth node K4 based on the corresponding frequency division control signals, and controls the electrical connection between the second output module 50 and the first node K1. On the other hand, the second output module 50 is configured to control the gate control signal output from the second output terminal O2 based on the signals from the third node K3 and the fourth node K4, and the corresponding second clock signal CK.

[0125] Optionally, referring to Figures 6A to 6B, the second frequency division control module 60 includes a third frequency division transistor Tf3, a fourth frequency division transistor Tf4, and a third capacitor C3.

[0126] The control terminal of the third frequency division transistor Tf3 is electrically connected to the third node K3 of the gate drive circuit of the current stage, and the input terminal of the third frequency division transistor Tf3 is positioned to receive the corresponding frequency division control signal.

[0127] The control terminal of the fourth frequency division transistor Tf4 is electrically connected to the output terminal of the third frequency division transistor Tf3, the input terminal of the fourth frequency division transistor Tf4 is electrically connected to the first node K1, and the output terminal of the fourth frequency division transistor Tf4 is electrically connected to the fourth node K4.

[0128] The first terminal of the third capacitor C3 is electrically connected to the control terminal of the fourth frequency division transistor Tf4, and the second terminal of the third capacitor C3 is electrically connected to the fourth node K4.

[0129] Optionally, one frequency division control signal is provided for each second frequency division control module 60 to control the frequency of the gate control signal output from the second output terminal O2 of the corresponding gate drive circuit.

[0130] Optionally, to reduce the number of frequency division control signals used in the display device, the same frequency division control signal is shared among the second frequency division control modules 60 in multiple cascaded first gate drive circuits GA1, enabling level control for multiple third gate control signals Pscan1 using a single frequency division control signal. Similarly, the same frequency division control signal is shared among the second frequency division control modules 60 in multiple cascaded second gate drive circuits GA2, enabling level control for multiple fourth gate control signals Pscan2 using a single frequency division control signal. Optionally, if the first gate drive circuit GA1 includes one second output module 50, the first gate drive circuit GA1 may also include one second frequency division control module 60, and the second frequency division control modules 60 in multiple cascaded first gate drive circuits GA1 share the same frequency division control signal to reduce the number of frequency division control signals used in the display device.

[0131] Optionally, if the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X ≥ 2), the first gate drive circuit GA1 may include at least one second frequency division control module 60. That is, the first gate drive circuit GA1 includes one second frequency division control module 60 to control the level of the third gate control signal Pscan output from the multiple second output modules 50. The first gate drive circuit GA1 may include multiple second frequency division control modules 60 to control the level of the third gate control signal Pscan output from the multiple second output modules 50, thereby achieving independent control of the level states of multiple third gate control signals Pscan.

[0132] Optionally, if the first gate drive circuit GA1 is equipped with multiple second frequency division control modules 60, each second frequency division control module 60 is configured to control the level of a third gate control signal Pscan output from a corresponding second output module 50 based on its corresponding frequency division control signal.

[0133] Optionally, if the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X≧2) and the first gate drive circuit GA1 includes one second frequency division control module 60, the second frequency division control modules 60 of multiple cascaded first gate drive circuits GA1 share the same frequency division control signal. For example, the second frequency division control modules 60 in multiple stage first gate drive circuits GA1 are electrically connected to a third frequency division control line FL3 to reduce the number of frequency division control signals used in the display device.

[0134] Optionally, if the first gate drive circuit GA1 includes multiple second output modules 50 (i.e., X≧2) and the first gate drive circuit GA1 includes multiple second frequency division control modules 60, the frequency division control signals used for the multiple second frequency division control modules 60 included in the same first gate drive circuit GA1 may be different.

[0135] For example, each first gate drive circuit GA1 includes two second output modules 50 and two second frequency division control modules 60, where the two second output modules 50 include a first sub-output module and a second sub-output module, and the two second frequency division control modules 60 include a first sub-frequency division control module and a second sub-frequency division control module, where the first sub-frequency division control module is configured to control the level of a third gate control signal Pscan output from the first sub-output module based on one frequency division control signal, and the second sub-frequency division control module is configured to control the level of a third gate control signal Pscan output from the second sub-output module based on another frequency division control signal. Here, the second output terminal corresponding to the first sub-output module may be O21 in Figure 6B, and the second output terminal corresponding to the second sub-output module may be O22 in Figure 6B. The second clock signal input terminal corresponding to the first sub-output module may be CKa in Figure 6B, and the second clock signal input terminal corresponding to the second sub-output module may be CKb in Figure 6B.

[0136] Optionally, the first sub-frequency division control modules in multiple cascaded first gate drive circuits GA1 share the same frequency division control signal, and the second sub-frequency division control modules in multiple cascaded first gate drive circuits GA1 share the same frequency division control signal, thereby reducing the number of frequency division control signals used in the display device.

[0137] Similarly, if the second gate drive circuit GA2 includes X second output modules 50, the number of second frequency division control modules 60 corresponding to the second gate drive circuit GA2 and the configuration of the appropriate frequency division control signals can be obtained.

[0138] When a sub-pixel Spi needs to refresh the display data, the data transistor Tda needs to be turned on so that the data signal is transmitted to the control terminal of the drive transistor Tdr. Therefore, the gate control signal corresponding to the data transistor Tda also needs to have an effective level for a specific period (for example, the data writing stage described later). Accordingly, the frequency division control signal used to control the first frequency division control module 20 and the frequency division control signal used to control the second frequency division control module 60 may be different so that the levels of the gate control signal output from the first output terminal O1 and the levels of the gate control signal output from the second output terminal O2 can be controlled independently in the same gate drive circuit.

[0139] Accordingly, referring to Figures 5A to 5B, the multiple frequency division control lines FL include a third frequency division control line FL3, the third frequency division control line FL3 transmits the third frequency division control signal PF1, each first gate drive circuit GA1 includes one second frequency division control module 60, and the second frequency division control module 60 in the first gate drive circuit GA1 of multiple stages is electrically connected to the third frequency division control line FL3, thereby reducing the number of frequency division control signals used in the display device and making the operating states of the data transistor Tda and compensation transistor Tc in multiple sub-pixels Spi independent.

[0140] Accordingly, multiple frequency division control lines FL include a fourth frequency division control line FL4, which transmits the fourth frequency division control signal PF2, and each second gate drive circuit GA2 includes one second frequency division control module 60. The second frequency division control modules 60 in the second gate drive circuits GA2 of multiple stages are electrically connected to the fourth frequency division control line FL4, thereby reducing the number of frequency division control signals used in the display device and making the operating states of the data transistor Tda and reset transistor Tr in multiple sub-pixels Spi independent.

[0141] Accordingly, the multiple frequency division control lines FL include a third frequency division control line FL3 and a fourth frequency division control line FL4, the second frequency division control module in the first gate drive circuit GA1 of multiple stages is electrically connected to the third frequency division control line FL3, and the second frequency division control module in the second gate drive circuit GA2 of multiple stages is electrically connected to the fourth frequency division control line FL4, thereby reducing the number of frequency division control signals used in the display device and making the operating states of the data transistor Tda, compensation transistor Tc, and reset transistor Tr in multiple sub-pixels Spi independent.

[0142] Optionally, when the gate control signals received by the control terminal of the data transistor Tda are simultaneously supplied by the first gate drive unit GM1 and the second gate drive unit GM2, in order to stabilize the operating state of the data transistor Tda by keeping the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda the same, the frequency division control line corresponding to the second frequency division control module in the first gate drive unit GM1 is electrically connected to the frequency division control line corresponding to the second frequency division control module in the second gate drive unit GM2, thereby enabling the second frequency division control module in the first gate drive unit GM1 and the second frequency division control module in the second gate drive unit GM2 to use the same frequency division control signal.

[0143] In other words, the control terminals of the data transistors Tda in multiple sub-pixels Spi in the same row are electrically connected to the second output terminals O2 of multiple first gate drive circuits GA1 and the second output terminals O2 of multiple second gate drive circuits GA2. Here, the third frequency division control line FL3 is electrically connected to the fourth frequency division control line FL4, so that the third gate control signal Pscan1 and the fourth gate control signal Pscan2, which are correspondingly received by the data transistors Tda in the sub-pixels Spi, remain the same, thereby stabilizing the operating state of the data transistors Tda in the sub-pixels Spi and reducing the number of frequency division control signals used.

[0144] To make it easier to understand, if each first gate drive circuit GA1 includes multiple second frequency division control modules 60, the multiple frequency division control lines FL may include frequency division control lines connected to the remaining second frequency division control modules 60, in addition to the third frequency division control line FL3 connected to one second frequency division control module 60. For example, each first gate drive circuit GA1 may include two second frequency division control modules 60, and the multiple frequency division control lines FL may include a fifth frequency division control line, with one second frequency division control module 60 in each stage of the first gate drive circuit GA1 being electrically connected to the third frequency division control line FL3, and the other second frequency division control module 60 in each stage of the first gate drive circuit GA1 being electrically connected to the fifth frequency division control line, thereby making the operating states of the two second frequency division control modules 60 in each first gate drive circuit GA1 independent.

[0145] Similarly, if each first gate drive circuit GA1 includes multiple second frequency division control modules 60, the multiple frequency division control lines FL may include frequency division control lines connected to the remaining second frequency division control modules 60, in addition to the fourth frequency division control line FL4 connected to one second frequency division control module 60. For example, each second gate drive circuit GA2 includes two second frequency division control modules 60, and the multiple frequency division control lines FL may include a sixth frequency division control line, where one second frequency division control module 60 in each stage of the second gate drive circuit GA2 is electrically connected to the fourth frequency division control line FL4, and the other second frequency division control module 60 in each stage of the second gate drive circuit GA2 is electrically connected to the sixth frequency division control line, thereby making the operating states of the two second frequency division control modules 60 in each second gate drive circuit GA2 independent.

[0146] Accordingly, if the gate control signals received by the control terminal of the data transistor Tda are simultaneously supplied by the first gate drive unit GM1 and the second gate drive unit GM2, and both the first gate drive circuit GA1 and the second gate drive circuit GA2 include multiple second frequency division control modules 60, the frequency division control signals used in the second frequency division control modules, corresponding to the third gate control signals Pscan1 and the fourth gate control signals Pscan2 received by the control terminal of the data transistor Tda in multiple sub-pixels Spi of the same row, remain the same. For example, if the frequency division control signals used in the second frequency division control module, which correspond to the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the control terminals of the data transistor Tda in multiple subpixels Spi in the same row, are signals transmitted by the fifth frequency division control line and the sixth frequency division control line, the electrical connection of the fifth frequency division control line and the sixth frequency division control line is controlled to keep the third gate control signal Pscan1 and the fourth gate control signal Pscan2, respectively, received by the data transistor Tda, the same, thereby stabilizing the operating state of the data transistor Tda.

[0147] The first gate drive circuit GA1(1) of the first stage included in the first gate drive unit GM1 uses the first initial signal stv1 as the start signal STV, and the second gate drive circuit GA2(1) of the first stage included in the second gate drive unit GM2 uses the second initial signal stv2 as the start signal STV. The phase difference between the first initial signal and the second initial signal is the same as the phase difference between the first gate drive circuit GA1 of each stage in the first gate drive unit GM1 and the second gate drive circuit GA2 of the same stage in the second gate drive unit GM2. Therefore, when the control terminal of the data transistor Tda simultaneously receives the third gate control signal Pscan1 and the fourth gate control signal Pscan2, the change time from the active level to the inactive level corresponding to the first initial signal stv1 and the second initial signal stv2 is kept the same, so that the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda in one sub-pixel Spi remain the same, thereby stabilizing the operating state of the data transistor Tda.

[0148] That is, in the first gate drive circuit GA1 of the multi-stage first gate drive circuit GA1(1), the start signal STV corresponding to the first stage first gate drive circuit GA1(1) (for example, the first initial signal stv1 described above) changes from an active level to an inactive level at the first time, and in the second gate drive circuit GA2 of the multi-stage second gate drive circuit GA2 (for example, the second initial signal stv2 described above) changes from an active level to an inactive level at the first time. Here, the first time is shown as ta in Figure 8A, which will be described later.

[0149] To make it easier to understand, if the transistor is an N-type transistor, then having an effective level in the signal received by the control terminal of this transistor means that the signal received by the control terminal of this transistor is at a high level, and having an ineffective level in the signal received by the control terminal of this transistor means that the signal received by the control terminal of this transistor is at a low level. If the transistor is a P-type transistor, then having an effective level in the signal received by the control terminal of this transistor means that the signal received by the control terminal of this transistor is at a low level, and having an ineffective level in the signal received by the control terminal of this transistor means that the signal received by the control terminal of this transistor is at a high level.

[0150] Optionally, the pulse widths of the effective levels of the first initial signal stv1 and the second initial signal stv2 may be the same or different.

[0151] Optionally, in some embodiments, in one subpixel Spi, after the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the second gate control signal Nscan2 corresponding to the reset transistor Tr are reduced to a low frequency, the gate control signal corresponding to the data transistor Tda (i.e., the third gate control signal Pscan1 and / or the fourth gate control signal Pscan2) may remain at a high frequency or be reduced to a low frequency.

[0152] For example, taking the case where the display panel DP realizes the display of a single static screen, we will explain this in conjunction with the schematic diagram of the display principle of high-frequency and low-frequency images provided by the embodiment of the present invention shown in Figure 7. When the display panel DP displays at a high frequency (e.g., 120 Hz), the display panel DP needs to perform a display data refresh operation 120 times per second, that is, the screen contains 120 frames per second, and each frame's display involves a display data refresh. When the display panel DP displays at a low frequency (e.g., 1 Hz), the display panel DP also contains 120 frames per second, but only the first frame's screen undergoes a display data refresh. The 119 consecutive frames from the first frame F1 onward all retain the data signal of the first frame's screen and do not perform a display data refresh operation. Here, the frame in which the display data is refreshed may be designated as the write frame WF, and the frame in which the display data is not refreshed may be designated as the hold frame HF. In this way, in the write frame WF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc, the second gate control signal Nscan2 corresponding to the reset transistor Tr, and the gate control signal corresponding to the data transistor Tda all need to have an active level so that the original data signal stored at the control terminal of the drive transistor Tdr is overwritten by the newly written data signal. This ensures that the sub-pixel Spi is displayed again in the write frame WF by the newly written data signal. On the other hand, in the hold frame HF, the first gate control signal Nscan1 corresponding to the compensation transistor Tc and the second gate control signal Nscan2 corresponding to the reset transistor Tr for some sub-pixel Spi maintain an inactive level, turning off the compensation transistor Tc and the reset transistor Tr, and thus preventing new data signals from being stored at the control terminal of the drive transistor Tdr. In the hold frame HF, the gate control signal corresponding to the data transistor Tda can maintain the same frequency as in the write frame WF.Alternatively, in the hold frame HF, the gate control signal corresponding to the data transistor Tda is kept at an invalid level, and as a result, the frequency of the gate control signal corresponding to the data transistor Tda in the hold frame HF is lower than the frequency in the write frame WF.

[0153] Optionally, in some embodiments, in the holding frame HF, the data transistor Tda is turned on based on the corresponding gate control signal, and the data transistor Tda is electrically connected to the input terminal of the drive transistor Tdr, using the signal transmitted by the data line DL to which it corresponds to perform a potential reset.

[0154] Optionally, in some embodiments, in the holding frame HF, the data transistor Tda is kept off based on the corresponding gate control signal, and the second initial transistor Ti2 has an on period based on the gate control signal transmitted by the corresponding fourth scan line GL4, thereby performing a potential reset to the input terminal of the drive transistor Tdr using the second initial signal transmitted by the second initial line VL2 to which the second initial transistor Ti2 is electrically connected.

[0155] Optionally, continuing with reference to Figures 6A and 6B, at least one gate drive circuit GDC further includes a switching module 70, which is electrically connected between the second frequency division control module 60 and the fourth node K4, and the switching module 70 is configured to control the electrical connection between the second frequency division control module 60 and the fourth node K4 based on the corresponding switching control signal SC.

[0156] Optionally, the switching module 70 includes an 11th transistor T11, the control terminal of the 11th transistor T11 is configured to receive a switching control signal SC, the input terminal of the 11th transistor T11 is electrically connected to the output terminal of the 4th frequency division transistor Tf4, and the output terminal of the 11th transistor T11 is electrically connected to the 4th node.

[0157] Optionally, the control terminal of the 11th transistor T11 in the K-stage's first gate drive circuit GA1(K) is configured to receive the KE-stage's first gate control signal Nscan1(KE) output from the KE-stage's first gate drive circuit GA1(KE), and the KE-stage's first gate control signal Nscan1(KE) output from the KE-stage's first gate drive circuit GA1(KE) is used as the switching control signal SC received by the control terminal of the 11th transistor T11 in the K-stage's first gate drive circuit GA1(K). Here, E≧1.

[0158] Optionally, the switching control signal SC received by the control terminal of the 11th transistor T11 in the first gate drive circuit GA1(1) of the first stage to the first gate drive circuit GA1(2) of the second stage is correspondingly a low-level signal VGL, and the control terminal of the 11th transistor T11 in the gate drive circuit of each stage from the first gate drive circuit GA1(2) of the second stage onward is arranged to receive the first gate control signal Nscan1 output from the first gate drive circuit GA1 two stages prior (for example, as shown in Figures 5A to 5B, the control terminal of the 11th transistor T11 in the first gate drive circuit GA1(3) of the third stage is arranged to receive the first gate control signal Nscan1(1) of the first stage output from the first gate drive circuit GA1(1) of the first stage). Similarly, the switching control signal SC corresponding to the second gate drive circuit GA2 of each stage in the second gate drive unit GM2 can be obtained.

[0159] Optionally, the control terminal of the 11th transistor T11 is electrically connected to the third node K3 of the gate drive circuit one stage prior, and the potential of the third node K3 of the gate drive circuit one stage prior is used as a switching control signal SC to control the operating state of the 11th transistor T11 and reduce the load at the first output terminal O1 of the gate drive circuit. For example, the control terminal of the 11th transistor T11 in the first gate drive circuit GA1(K) of the K stage is electrically connected to the third node K3 of the first gate drive circuit GA1(KE) of the KE stage, and the potential of the third node K3 of the first gate drive circuit GA1(KE) of the KE stage is used as the switching control signal SC received by the control terminal of the 11th transistor T11 in the first gate drive circuit GA1(K) of the K stage.

[0160] Optionally, referring further to Figures 6A and 6B, at least one gate drive circuit further includes a second control module 80, which is electrically connected to the third node K3 of the current stage gate drive circuit GDC and to the switching module 70, and the second control module 80 is configured to control signal transmission between the second power supply terminal PVGH and the switching module 70 based on the corresponding first clock signal XCK and the potential of the third node K3.

[0161] Optionally, the second control module 80 includes a 12th transistor T12 and a 13th transistor T13.

[0162] The first and second control terminals of the 12th transistor T12 are arranged to receive the corresponding first clock signal XCK, and the output terminal of the 12th transistor T12 is electrically connected to the input terminal of the 11th transistor T11.

[0163] The control terminal of the 13th transistor T13 is electrically connected to the third node K3 of the gate drive circuit GDC of the current stage, the input terminal of the 13th transistor T13 is electrically connected to the second power supply terminal PVGH, and the output terminal of the 13th transistor T13 is electrically connected to the input terminal of the 12th transistor T12.

[0164] Optionally, referring again to Figures 6A and 6B, at least one gate drive circuit GDC further includes an initialization module 90, which is electrically connected to a first node K1, and is configured to control signal transmission between a second power supply terminal PVGH and the first node K1 based on an initialization control signal Ctl.

[0165] Optionally, the initialization module 90 includes an initialization transistor Tre, the control terminal of which is configured to receive an initialization control signal Ctl, the input terminal of which is electrically connected to the second power supply terminal PVGH, and the output terminal of which is electrically connected to the first node K1.

[0166] Optionally, the initialization module 90 is configured to be activated when the display device is started and / or during blank intervals.

[0167] Optionally, in some embodiments, the voltage corresponding to the first power terminal PVGL is lower than the voltage corresponding to the second power terminal PVGH, and the voltage corresponding to the third power terminal NVGL is lower than the voltage corresponding to the fourth power terminal NVGH.

[0168] Optionally, in some embodiments, at least one of the first transistor T1, fourth transistor T4, sixth transistor T6, seventh transistor T7, ninth transistor T9, twelfth transistor T12, and first output transistor To1 may have only one corresponding control terminal.

[0169] To make it easier to understand, each transistor included in the gate drive circuit (GDC) may be either a P-type transistor or an N-type transistor. The semiconductor material of each transistor included in the gate drive circuit (GDC) may be either a silicon semiconductor or an oxide semiconductor.

[0170] Optionally, the clock signals transmitted by multiple clock signal lines are multiplexed to form first and second clock signals corresponding to multiple gate drive circuits connected in cascade, thereby reducing the power consumption of the display device and decreasing the bezel size of the display panel DP.

[0171] Optionally, multiple first gate drive circuits GA1 included in the first gate drive unit GM1 share a clock signal transmitted by F clock lines to form the corresponding first and second clock signals. Here, F may be 2, 4, 6, 8, etc. For example, referring to Figure 5A, we will explain the case where F is 4 as an example. The multiple clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Here, if the first gate drive circuit GA1 includes one second output module 50, the first clock signal XCK corresponding to the first gate drive circuit GA1(4m+1) of the 4m+1 stage is the signal transmitted by the corresponding second clock line CKL2, and the second clock signal CK corresponding to the first gate drive circuit GA1(4m+1) of the 4m+1 stage is the signal transmitted by the corresponding first clock line CKL1. The first clock signal XCK corresponding to the first gate drive circuit GA1(4m+2) of the 4m+2 stage is transmitted by the corresponding third clock line CKL3, and the second clock signal CK corresponding to the first gate drive circuit GA1(4m+2) of the 4m+2 stage is transmitted by the corresponding second clock line CKL2. The first clock signal XCK corresponding to the first gate drive circuit GA1(4m+3) of the 4m+3 stage is transmitted by the corresponding fourth clock line CKL4, and the second clock signal CK corresponding to the first gate drive circuit GA1(4m+3) of the 4m+3 stage is transmitted by the corresponding third clock line CKL3. The first clock signal XCK, corresponding to the first gate drive circuit GA1(4m+4) of the 4m+4 stage, is transmitted by the corresponding first clock line CKL1, and the second clock signal CK, corresponding to the first gate drive circuit GA1(4m+4) of the 4m+4 stage, is transmitted by the corresponding fourth clock line CKL4. m≧0.

[0172] Optionally, if each first gate drive circuit GA1 includes multiple second output modules 50 (X≧2), the multiple first gate drive circuits GA1 included in the first gate drive unit GM1 share a clock signal transmitted by F clock lines to form a corresponding second clock signal CK. Here, F=2X.

[0173] For example, referring to Figure 5B, let us consider a case where each first gate drive circuit GA1 includes two second output modules 50 (X=2), and multiple first gate drive circuits GA1 included in the first gate drive unit GM1 share a clock signal transmitted by four clock lines to form the corresponding second clock signal CK. The multiple clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4. Here, the first clock line CKL1 transmits the corresponding second clock signal CK to one second output module 50 in the second k+1 stage first gate drive circuit GA1(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to the other second output module 50 in the second k+1 stage first gate drive circuit GA1(2k+1). The third clock line CKL3 transmits the corresponding second clock signal CK to one second output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage, and the fourth clock line CKL4 transmits the corresponding second clock signal CK to another second output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage, where k≧0.

[0174] Similarly, if each first gate drive circuit GA1 includes three second output modules 50 (X=3), the multiple first gate drive circuits GA1 included in the first gate drive unit GM1 may share a clock signal transmitted by six clock lines to form a corresponding second clock signal CK.

[0175] For example, let's consider a case where the three second output modules in the first gate drive circuit GA1 include a first sub-output module, a second sub-output module, and a third sub-output module, and the multiple clock lines further include a fifth clock line CKL5 and a sixth clock line CKL6.

[0176] The first clock line CKL1 transmits the corresponding second clock signal CK to the first sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage; the second clock line CKL2 transmits the corresponding second clock signal CK to the second sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage; and the third clock line CKL3 transmits the corresponding second clock signal CK to the third sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage. The fourth clock line CKL4 transmits the corresponding second clock signal CK to the first sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage; the fifth clock line CKL5 transmits the corresponding second clock signal CK to the second sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage; and the sixth clock line CKL6 transmits the corresponding second clock signal CK to the third sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage.

[0177] Alternatively, the fifth clock line CKL5 transmits the corresponding second clock signal CK to the first sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage, the sixth clock line CKL6 transmits the corresponding second clock signal CK to the second sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage, and the first clock line CKL1 transmits the corresponding second clock signal CK to the third sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage. The second clock line CKL2 transmits the corresponding second clock signal CK to the first sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage; the third clock line CKL3 transmits the corresponding second clock signal CK to the second sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage; and the fourth clock line CKL4 transmits the corresponding second clock signal CK to the third sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage.

[0178] Alternatively, the sixth clock line CKL6 transmits the corresponding second clock signal CK to the first sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage, the first clock line CKL1 transmits the corresponding second clock signal CK to the second sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage, and the second clock line CKL2 transmits the corresponding second clock signal CK to the third sub-output module in the first gate drive circuit GA1(2k+1) of the second k+1 stage. The third clock line CKL3 transmits the corresponding second clock signal CK to the first sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage; the fourth clock line CKL4 transmits the corresponding second clock signal CK to the second sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage; and the fifth clock line CKL5 transmits the corresponding second clock signal CK to the third sub-output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage.

[0179] Furthermore, the phase difference between the clock signal transmitted by the first clock line CKL1 and the clock signal transmitted by the second clock line CKL2 is φ1, the phase difference between the clock signal transmitted by the second clock line CKL2 and the clock signal transmitted by the third clock line CKL3 is φ2, the phase difference between the clock signal transmitted by the third clock line CKL3 and the clock signal transmitted by the fourth clock line CKL4 is φ3, the phase difference between the clock signal transmitted by the fourth clock line CKL4 and the clock signal transmitted by the fifth clock line CKL5 is φ4, the phase difference between the clock signal transmitted by the fifth clock line CKL5 and the clock signal transmitted by the sixth clock line CKL6 is φ5, and the phase difference between the clock signal transmitted by the sixth clock line CKL6 and the clock signal transmitted by the sixth clock line CKL6 is φ6. Here, φ1=φ2=φ3=φ4=φ5=φ6.

[0180] Optionally, if each first gate drive circuit GA1 includes multiple second output modules 50 (X≧2), the multiple first gate drive circuits GA1 included in the first gate drive unit GM1 share a clock signal transmitted by multiple clock lines out of the F clock lines to form a corresponding first clock signal XCK.

[0181] For example, referring to Figure 5B, let us consider the case where each first gate drive circuit GA1 includes two second output modules 50 (X=2), and multiple first gate drive circuits GA1 included in the first gate drive unit GM1 share a clock signal transmitted by four clock lines. The third clock line CKL1 transmits the corresponding first clock signal XCK to the first gate drive circuit GA1(2k+1) of the second k+1 stage, and the first clock line transmits the corresponding first clock signal XCK to the first gate drive circuit GA1(2k+2) of the second k+2 stage.

[0182] For example, consider a case where each first gate drive circuit GA1 includes three second output modules 50, and each of the three second output modules 50 includes a first sub-output module, a second sub-output module, and a third sub-output module. The fourth clock line CKL4 transmits the corresponding first clock signal XCK to the first gate drive circuit GA1(2k+1) of the second k+1 stage, and the first clock line CKL1 transmits the corresponding first clock signal XCK to the first gate drive circuit GA1(2k+2) of the second k+2 stage.

[0183] Optionally, if each first gate drive circuit GA1 includes multiple second output modules 50 (X≧2), multiple clock lines are independently installed to provide the corresponding first clock signal XCK to the first gate drive circuits GA1 of multiple stages. As a result, some of the F clock lines will not simultaneously provide the corresponding first clock signal XCK and second clock signal CK to the first gate drive circuits GA1 of multiple stages. This brings the loads corresponding to the multiple clock lines closer together, and consequently improves the quality of the third gate control signal Pscan1 output from the first gate drive circuits GA1 of multiple stages.

[0184] Similarly, based on a design principle similar to the case where the phase difference of the first clock signal XCK corresponding to two adjacent first gate drive circuits GA1 is XH, the phase difference of the third gate control signals output from the first sub-output module in two adjacent first gate drive circuits GA1 is XH, and the phase difference of the third gate control signals output from the second sub-output module in two adjacent first gate drive circuits GA1 is XH, a matching connection relationship between multiple first gate drive circuits GA1 and multiple clock lines can be obtained when each first gate drive circuit GA1 includes more second output modules 50.

[0185] Optionally, multiple first gate drive circuits GA1 included in the second gate drive unit GM2 may share the clock signal transmitted by the G-strip clock line to form the corresponding first clock signal XCK and second clock signal CK. Here, G may be 2, 4, 6, 8, etc.

[0186] Optionally, the number of clock lines corresponding to the first gate drive unit GM1 may be the same as, or different from, the number of clock lines corresponding to the second gate drive unit GM2.

[0187] To make it easier to understand, by referring to the matching connection relationships between the multiple stage first gate drive circuits GA1 and multiple clock lines, we can obtain the matching connection relationships between the multiple stage second gate drive circuits GA2 and multiple clock lines.

[0188] Optionally, the first gate drive unit GM1 may or may not share multiple clock lines with the second gate drive unit GM2.

[0189] Optionally, the first gate drive unit GM1 shares multiple clock lines with the second gate drive unit GM2. This can result in situations where the clock lines used by the first gate drive unit GM1 and the second gate drive unit GM2 are different, or where the change rates of the clock signals used by the first gate drive unit GM1 and the second gate drive unit GM2 do not match. In such cases, the matching relationship between the gate control signals generated by the first gate drive unit GM1 and the gate control signals generated by the second gate drive unit does not correspond, or the matching timing does not match. Sharing multiple clock lines between the first gate drive unit GM1 and the second gate drive unit GM2 is advantageous in improving the synergistic effect between the two units and reducing power consumption by reducing the number of clock lines used.

[0190] Furthermore, when the gate control signal received by the control terminal of the data transistor Tda is supplied simultaneously by the first gate drive unit GM1 and the second gate drive unit GM2, the sharing of multiple clock lines between the first gate drive unit GM1 and the second gate drive unit GM2 is advantageous in keeping the third gate control signal Pscan1 and the fourth gate control signal Pscan2, which are correspondingly received by the data transistor Tda in the subpixel Spi, the same, thereby improving the operational stability of the data transistor Tda.

[0191] For example, referring to Figure 5A, we will explain the connection relationship between the first gate drive unit GM1 and the second gate drive unit GM2 and multiple clock lines, taking as an example the case where both the first gate drive circuit GA1 and the second gate drive unit GA2 include one second output module 50, and the first gate drive unit GM1 and the second gate drive unit GM2 share four clock lines. The first clock signal XCK corresponding to the first gate drive circuit GA1(4m+1) and the second gate drive circuit GA2(4m+1) of the 4m+1 stage is a signal transmitted by the corresponding second clock line CKL2, and the second clock signal CK corresponding to the first gate drive circuit GA1(4m+1) and the second gate drive circuit GA2(4m+1) of the 4m+1 stage is a signal transmitted by the corresponding first clock line CKL1. The first clock signal XCK, corresponding to the first gate drive circuit GA1(4m+2) and the second gate drive circuit GA2(4m+2) of the 4m+2 stage, is transmitted by the corresponding third clock line CKL3, and the second clock signal CK, corresponding to the first gate drive circuit GA1(4m+2) and the second gate drive circuit GA2(4m+2) of the 4m+2 stage, is transmitted by the corresponding second clock line CKL2. The first clock signal XCK, corresponding to the first gate drive circuit GA1(4m+3) and the second gate drive circuit GA2(4m+3) of the 4m+3 stage, is transmitted by the corresponding fourth clock line CKL4, and the second clock signal CK, corresponding to the first gate drive circuit GA1(4m+3) and the second gate drive circuit GA2(4m+3) of the 4m+3 stage, is transmitted by the corresponding third clock line CKL3.The first clock signal XCK, corresponding to the first gate drive circuit GA1(4m+4) and the second gate drive circuit GA2(4m+4) of the 4m+4 stage, is transmitted by the corresponding first clock line CKL1, and the second clock signal CK, corresponding to the first gate drive circuit GA1(4m+4) and the second gate drive circuit GA2(4m+4) of the 4m+4 stage, is transmitted by the fourth clock line CKL4. Here, m≧0.

[0192] For example, continuing to refer to Figure 5B, if we take the case where the first gate drive circuit GA1 and the second gate drive unit GA2 each include two second output modules 50, and the first gate drive unit GM1 and the second gate drive unit GM2 share four clock lines, then the first clock line CKL1 transmits the corresponding second clock signal CK to one second output module in the second k+1 stage first gate drive circuit GA1(2k+1) and one second output module in the second k+1 stage second gate drive circuit GA2(2k+1), and the second clock line CKL2 transmits the corresponding second clock signal CK to the other second output module in the second k+1 stage first gate drive circuit GA1(2k+1) and the other second output module in the second k+1 stage second gate drive circuit GA2(2k+1). The third clock line CKL3 transmits the corresponding second clock signal CK to one second output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage, and to one second output module in the second gate drive circuit GA2(2k+2) of the second k+2 stage. The fourth clock line CKL4 transmits the corresponding second clock signal CK to another second output module in the first gate drive circuit GA1(2k+2) of the second k+2 stage, and to another second output module in the second gate drive circuit GA2(2k+2) of the second k+2 stage.

[0193] Accordingly, optionally, the third clock line CKL1 transmits the corresponding first clock signal XCK to the first gate drive circuit GA1(2k+1) of the second k+1 stage and the second gate drive circuit GA2(2k+1) of the second k+1 stage, and the first clock line transmits the corresponding first clock signal XCK to the first gate drive circuit GA1(2k+2) of the second k+2 stage and the second gate drive circuit GA2(2k+2) of the second k+2 stage.

[0194] Similarly, when both the first gate drive unit GM1 and the second gate drive unit GM2 contain more second output modules, the first gate drive unit GM1 and the second gate drive unit GM2 can obtain connection relationships with multiple clock lines.

[0195] The circuit configurations of the first gate drive circuit GA1 and the second gate drive circuit GA2 may be the same or different. For example, in some embodiments, both the first gate drive circuit GA1 and the second gate drive circuit GA2 may use the circuit configurations shown in Figures 6A to 6B. In other embodiments, one of the first gate drive circuit GA1 and the second gate drive circuit GA2 may use the circuit configuration shown in Figures 6A to 6B, while the other of the first gate drive circuit GA1 and the second gate drive circuit GA2 may use a circuit configuration that can realize frequency division control in related technologies.

[0196] By controlling the level state of the first frequency division control signal NF1, the level state of the first gate control signal Nscan1 output from the first gate drive circuit GA1 of multiple stages can be controlled. Similarly, by controlling the level state of the frequency division control signal corresponding to the second frequency division module in the first gate drive circuit GA1, the level state of the third gate control signal Pscan1 output from the first gate drive circuit GA1 of multiple stages can be controlled. Similarly, by controlling the level state of the second frequency division control signal NF2, the level state of the second gate control signal Nscan2 output from the second gate drive circuit GA2 of multiple stages can be controlled. Similarly, by controlling the level state corresponding to the second frequency division module in the second gate drive circuit GA2, the level state of the fourth gate control signal Pscan2 output from the second gate drive circuit GA2 of multiple stages can be controlled.

[0197] Figures 8A to 8D are timing diagrams of the first and second gate control signals provided by embodiments of the present application. Of these, Figures 8A to 8B are timing diagrams showing the case where each gate drive circuit includes one second output module, and Figures 8C to 8D are timing diagrams showing the case where each gate drive circuit includes two second output modules. Nscan in Figures 8C to 8D may indicate the first gate control signal or the second gate control signal, and Pscan in Figures 8C to 8D may indicate the third gate control signal or the fourth gate control signal.

[0198] The second transistor T2, third transistor T3, fifth transistor T5, eighth transistor T8, tenth transistor T10, eleventh transistor T11, thirteenth transistor T13, first frequency division transistors Tf1 to fourth frequency division transistors Tf4, second output transistors To2 to fourth output transistors To4 are P-type transistors, the first transistor T1, fourth transistor T4, sixth transistor T6, seventh transistor T7, ninth transistor T9, twelfth transistor T12, and first output transistor To1 are N-type transistors, the first gate drive circuit GA1 of the first stage uses the first initial signal stv1 as a start signal, the second gate drive circuit GA2 of the first stage uses the second initial signal stv2 as a start signal, and the first gate drive circuit GA1(p) of the p-1 stage uses the first output terminal O1 of the first gate drive circuit GA1(p-1) of the p-1 stage. The operating principles of the first gate drive unit GM1 and the second gate drive unit GM2 will be explained using the following example: the first gate control signal Nscan1(p-1) is the start signal STV, the second gate drive circuit GA2(p) of the p-th stage uses the second gate control signal Nscan2(p-1) output from the first output terminal O1 of the second gate drive circuit GA2(p-1) of the p-1st stage as the start signal STV, the switching control signal SC corresponding to the first gate drive circuit GA1(p) of the p-th stage is the first gate control signal Nscan1(p-2) of the p-2nd stage output from the first gate drive circuit GA1(p-2), and the switching control signal SC corresponding to the second gate drive circuit GA2(p) of the p-2nd stage is the second gate control signal Nscan2(p-2) of the p-2nd stage output from the second gate drive circuit GA2(p-2). Here, p>1. Correspondingly, in Figures 8A and 8B, the first clock signal XCK corresponding to the first gate drive circuit GA1(p) of the p-th stage and the second gate drive circuit GA2(p) of the p-th stage are provided by the second clock line CKL2, and the corresponding second clock signal CK is provided by the first clock line CKL1.Correspondingly in Figures 8C to 8D, the first clock signal XCK corresponding to the first gate drive circuit GA1(p) of the p-th stage and the second gate drive circuit GA2(p) of the p-th stage is provided by the first clock line CKL1, the corresponding second clock signal CK is provided by the third clock line CKL3 and the fourth clock line CKL4, and each gate drive circuit corresponding to Figures 8C to 8D includes one second frequency division control module.

[0199] Continuing with reference to Figures 5A, 6A, and 8A-8B, we will explain as an example the case in which the first frequency division control signal NF1 and the second frequency division control signal NF2 correspond to each other and change from a low-level state to a high-level state.

[0200] In the first stage t1, the first clock signal CK1 transmitted by the first clock line CKL1 is at a high level, the second clock signal CK2 transmitted by the second clock line CKL2 is at a low level, the third clock signal CK3 transmitted by the third clock line CKL3 is at a high level, and the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is at a high level. The first gate control signals Nscan1(p-1) of the p-1 stage to the first gate control signals Nscan1(p-2) of the p-2 stage, and the second gate control signals Nscan2(p-1) of the p-1 stage to the second gate control signals Nscan2(p-2) of the p-2 stage are at a low level. The first frequency division control signal NF1, the second frequency division control signal NF2, the third frequency division control signal PF1, and the fourth frequency division control signal PF2 are at a low level.

[0201] In a first gate drive circuit GA1 and a second gate drive circuit GA2 (for example, the first gate drive circuit GA1(p) of the p-th stage and the second gate drive circuit GA2(p) of the p-th stage, etc.), the first clock signal XCK is provided by the second clock line CKL2, and the second clock signal CK is provided by the first clock line CKL1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor The transistor T13, the first to fourth frequency division transistors Tf1 to Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off, the third power supply terminal NVGL is electrically connected to the first output terminal O1, and the second power supply terminal PVGH is electrically connected to the second output terminal O2.

[0202] In the first gate drive circuit GA1 and the second gate drive circuit GA2 (for example, the first gate drive circuit GA1(p+1) of the p+1 stage to the first gate drive circuit GA1(p+3) of the p+3 stage, and the second gate drive circuit GA2(p+1) of the p+1 stage to the second gate drive circuit GA2(p+3) of the p+3 stage, etc.), the third transistor T3 is turned off. Consequently, the first gate control signal Nscan1 output from the first gate drive circuit GA1 and the second gate control signal Nscan2 output from the second gate drive circuit GA2, both of which are output from the first gate drive circuit GA1 and p+1 respectively, are kept at a low level, while the third gate control signal Pscan1 and the fourth gate control signal Pscan2 are kept at a high level.

[0203] In the second stage t2, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first gate control signals Nscan1(p-1) of the p-1 stage to the first gate control signals Nscan1(p-2) of the p-2 stage are at a high level, the second gate control signals Nscan2(p-1) of the p-1 stage to the second gate control signals Nscan2(p-2) of the p-2 stage are at a low level, and the first frequency division control signals NF1 to the fourth frequency division control signals PF2 are at a low level.

[0204] In the first gate drive circuit GA1(p) of the p-th stage, the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the second output transistor To2 are turned on, the second frequency division transistor Tf2 and the fourth frequency division transistor Tf4 remain on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the first output transistor To1, the third output transistor To3, and the fourth output transistor To4 are turned off. The fourth power supply terminal NVGH is electrically connected to the first output terminal O1, the first gate control signal Nscan1(p) of the p-th stage has a high level, and the third gate control signal Pscan1(p) of the p-th stage maintains a high level.

[0205] In the second gate drive circuit GA2(p) of the p-th stage, the second stage t2 performs an operation similar to that of the first stage t1. The first gate control signals Nscan1(p+1) of the p+1-th stage to the first gate control signals Nscan1(p+11) of the p+11-th stage, and the second gate control signals Nscan2(p) of the p-th stage to the second gate control signals Nscan2(p+11) of the p+11-th stage maintain a low level, while the third gate control signals Pscan1(p+1) of the p+1-th stage to the third gate control signals Pscan1(p+11) of the p+11-th stage, and the fourth gate control signals Pscan2(p) of the p-th stage to the fourth gate control signals Pscan2(p+11) of the p+11-th stage maintain a high level.

[0206] In the third stage t3, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a low level, and the fourth clock signal CK4 is at a high level. The first gate control signals Nscan1(p-1) of the p-1 stage to the first gate control signals Nscan1(p-2) of the p-2 stage are at a high level, the second gate control signals Nscan2(p-1) of the p-1 stage to the second gate control signals Nscan2 of the p-2 stage are at a low level, and the first frequency division control signals NF1 to the fourth frequency division control signals PF2 are at a low level.

[0207] The first gate control signal Nscan1(p) and the third gate control signal Pscan1(p) of the p-stage maintain a high level.

[0208] In the second gate drive circuit GA2(p) of the p-th stage, the third transistor T3 is turned off. The second gate control signals Nscan2(p) of the p-th stage to the second gate control signals Nscan2(p+11) of the p+11th stage are held at a low level, and the fourth gate control signals Pscan2(p) of the p-th stage to the fourth gate control signals Pscan2(p+11) of the p+11th stage are held at a high level.

[0209] In the third stage t3, the first gate drive circuit GA1(p+1) and the second gate drive circuit GA2(p+1) of the p+1 stage perform operations similar to those performed by the first gate drive circuit GA1(p) and the second gate drive circuit GA2(p) of the p stage in the second stage t2. In the third stage t3, the first gate drive circuit GA1(p+2) and the second gate drive circuit GA2(p+2) of the p+2 stage perform operations similar to those performed by the first gate drive circuit GA1(p+1) and the second gate drive circuit GA2(p+1) of the p+1 stage in the second stage t2. Similarly, the operation performed by the first gate drive circuit GA1(p+3) in the p+3 stage to the first gate drive circuit GA1(p+11) in the p+11 stage, and the second gate drive circuit GA2(p+3) in the p+3 stage to the second gate drive circuit GA2(p+11) in the p+11 stage is obtained in the third stage t3.

[0210] In the fourth stage t4, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first gate control signals Nscan1(p-1) of the p-1 stage to the first gate control signals Nscan1(p-2) of the p-2 stage are at a high level, the second gate control signals Nscan2(p-1) of the p-1 stage to the second gate control signals Nscan2 of the p-2 stage are at a high level, and the first frequency division control signal NF1, the second frequency division control signal NF2, the third frequency division control signal PF1, and the fourth frequency division control signal PF2 are at a low level.

[0211] The first gate control signal Nscan1(p) of stage p and the third gate control signal Pscan1(p) of stage p maintain a high level. Additionally, the first gate control signals Nscan1(p+1) of stage p+1 to Nscan1(p+4) of stage p+4, and the third gate control signals Pscan1(p+1) of stage p+1 to Pscan1(p+11) of stage p+11 maintain a high level, while the first gate control signals Nscan1(p+5) of stage p+5 to Nscan1(p+11) of stage p+11 maintain a low level.

[0212] The second gate drive circuit GA2(p) in the p-th stage performs an operation similar to that performed by the first gate drive circuit GA1(p) in the p-th stage in the second stage t2, with the second gate control signal Nscan2(p) in the p-th stage being at a high level and the fourth gate control signal Pscan2(p) in the p-th stage being at a high level. The second gate control signals Nscan2(p+1) in the p+1-th stage to the second gate control signals Nscan2(p+11) in the p+11-th stage maintain a low level, while the fourth gate control signals Pscan2(p) in the p-th stage to the fourth gate control signals Pscan2(p+11) in the p+11-th stage maintain a high level.

[0213] In the fifth stage t5, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first gate control signals Nscan1(p-1) of the p-1 stage to the first gate control signals Nscan1(p-2) of the p-2 stage, and the second gate control signals Nscan2(p-1) of the p-1 stage to the second gate control signals Nscan2 of the p-2 stage are at a low level. The first frequency division control signals NF1 to the fourth frequency division control signals PF2 are at a low level.

[0214] In the first gate drive circuit GA1(p) of the p-stage and the second gate drive circuit GA2(p) of the p-stage, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, the twelfth transistor T12, the second frequency division transistor Tf2, the fourth frequency division transistor Tf4, the second output transistor To2, and the third output transistor To3 are turned on, while the first transistor T1, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the thirteenth transistor T13, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the first output transistor To1, and the fourth output transistor To4 are turned off. The first gate control signal Nscan1(p) and the second gate control signal Nscan2(p) of the p-stage have high levels, while the third gate control signal Pscan1(p) and the fourth gate control signal Pscan2(p) of the p-stage have low levels.

[0215] The first gate control signals Nscan1(p+1) in the p+1 stage to the first gate control signals Nscan1(p+7) in the p+7 stage, and the third gate control signals Pscan1(p+2) in the p+2 stage to the third gate control signals Pscan1(p+11) in the p+11 stage have high levels, while the first gate control signals Nscan1(p+8) in the p+8 stage to the first gate control signals Nscan1(p+11) in the p+11 stage have low levels. The second gate control signals Nscan2(p+1) in the p+1 stage to the second gate control signals Nscan2(p+3) in the p+3 stage, and the fourth gate control signals Pscan2(p+2) in the p+2 stage to the fourth gate control signals Pscan2(p+11) in the p+11 stage have high levels, while the third gate control signals Nscan2(p+4) in the p+4 stage to the third gate control signals Nscan2(p+11) in the p+11 stage have low levels.

[0216] In the sixth stage t6, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a low level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first gate control signals Nscan1(p-1) of the p-1 stage to the first gate control signals Nscan1(p-2) of the p-2 stage, and the second gate control signals Nscan2(p-1) of the p-1 stage to the second gate control signals Nscan2 of the p-2 stage are at a low level. The first frequency division control signals NF1 to the fourth frequency division control signals PF2 are at a low level.

[0217] In the first gate drive circuit GA1(p) and the second gate drive circuit GA2(p) of the p-stage, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, the tenth transistor T10, the eleventh transistor T11, the thirteenth transistor T13, the first frequency division transistors Tf1 to the fourth frequency division transistors Tf4, the first output transistor To1, and the fourth output transistor To4 are turned on, while the first transistor T1, the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, the second output transistor To2, and the third output transistor To3 are turned off. The first gate control signal Nscan1(p) and the second gate control signal Nscan2(p) of the p-stage have a low level, and the third gate control signal Pscan1(p) and the fourth gate control signal Pscan2(p) of the p-stage have a high level.

[0218] The first gate drive circuit GA1(p+1) and the second gate drive circuit GA2(p+1) of the p+1 stage perform operations similar to those performed by the first gate drive circuit GA1(p) and the second gate drive circuit GA2(p) of the p stage in the 6th stage t6, respectively, in the 5th stage t5. The first gate drive circuit GA1(p+2) and the second gate drive circuit GA2(p+2) of the p+2 stage perform operations similar to those performed by the first gate drive circuit GA1(p+1) and the second gate drive circuit GA2(p+2) of the p+1 stage in the 6th stage t6, respectively, in the 5th stage t5. Similarly, the operation performed by the first gate drive circuit GA1(p+3) in the p+3 stage to the first gate drive circuit GA1(p+11) in the p+11 stage, and the second gate drive circuit GA2(p+3) in the p+3 stage to the second gate drive circuit GA2(p+11) in the p+11 stage is obtained in the 6th stage t6.

[0219] In the seventh stage t7, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a low level, and the fourth clock signal CK4 is at a high level. The first frequency division control signals NF1 to the fourth frequency division control signals PF2 are at a low level.

[0220] The first gate control signals Nscan1(p) in stage p to stage p+1, and Nscan1(p+10) in stage p+10 to stage p+11, have low levels, while the first gate control signals Nscan1(p+2) in stage p+2 to stage p+9, have high levels. The third gate control signal Pscan1(p+2) in stage p+2 has a low level, while the third gate control signals Pscan1(p) in stage p to stage p+1, and Pscan1(p+3) in stage p+3 to stage p+11, have high levels.

[0221] The second gate control signals Nscan2(p) in stage p to the second gate control signal Nscan2(p+1) in stage p+1, and the second gate control signals Nscan2(p+6) in stage p+6 to the second gate control signal Nscan2(p+11) in stage p+11 have low levels, while the second gate control signals Nscan2(p+2) in stage p+2 to the second gate control signal Nscan2(p+5) in stage p+5 have high levels. The fourth gate control signal Pscan2(p+2) in stage p+2 has a low level, while the fourth gate control signals Pscan2(p) in stage p to the fourth gate control signal Pscan2(p+1) in stage p+1, and the fourth gate control signals Pscan2(p+3) in stage p+3 to the fourth gate control signal Pscan2(p+11) in stage p+11 have high levels.

[0222] In the eighth stage t8, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a low level. The first frequency division control signal NF1 is at a high level, and the second to fourth frequency division control signals NF2 to PF2 are at low levels.

[0223] The first gate drive circuit GA1(p) in the p-th stage maintains the same state as in the seventh stage t7 at the eighth stage t8. The first gate drive circuit GA1(p+1) in the p+1-th stage performs an operation similar to the operation performed by the first gate drive circuit GA1(p) in the p-th stage at the seventh stage t7 at the eighth stage t8. The first gate drive circuit GA1(p+2) in the p+2-th stage performs an operation similar to the operation performed by the first gate drive circuit GA1(p+1) in the p+1-th stage at the seventh stage t7 at the eighth stage t8, and similarly, the first gate drive circuits GA1(p+4) to p+9 perform the operation performed by the first gate drive circuits GA1(p+9) in the p+4-th stage to the p+9-th stage. In the p+10th stage, the first gate drive circuit GA1(p+10) performs an operation similar to that of the first gate drive circuit GA1(p) in the p-th stage in the second stage t2, and the first gate control signal Nscan1(p+10) and the third gate control signal Pscan1(p+10) of the p+10th stage are at a high level.

[0224] In the first gate drive circuit GA1(p+11) of the p+11th stage, the first transistor T1, the fourth transistor T4, the ninth transistor T9, the twelfth transistor T12, the first frequency division transistor Tf1, the third frequency division transistor Tf3, and the fourth frequency division transistor Tf4 are turned on, while the second transistor T2, the third transistor T3, the eleventh transistor T11, and the second frequency division transistor Tf2 are turned off. Consequently, the first gate control signal Nscan1(p+11) of the p+11th stage has a low level, and the third gate control signal Pscan1(p+11) of the p+11th stage has a high level.

[0225] In the first gate drive circuit GA1 of the p+11th stage, from GA1(p+11) onward, the first frequency division transistor Tf1, the third frequency division transistor Tf3, and the fourth frequency division transistor Tf4 are turned on, and the second frequency division transistor Tf2 is turned off.

[0226] The second gate control signals Nscan2(p) in stage p to the second gate control signals Nscan2(p+2) in stage p+2, and the second gate control signals Nscan2(p+7) in stage p+7 to the second gate control signals Nscan2(p+11) in stage p+11 have low levels, while the second gate control signals Nscan2(p+3) in stage p+3 to the second gate control signals Nscan2(p+6) in stage p+6 have high levels. The fourth gate control signal Pscan2(p+3) in stage p+3 has a low level, while the fourth gate control signals Pscan2(p) in stage p to the fourth gate control signals Pscan2(p+2) in stage p+2, and the fourth gate control signals Pscan2(p+4) in stage p+4 to the fourth gate control signals Pscan2(p+11) in stage p+11 have high levels.

[0227] In the ninth stage t9, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first frequency division control signal NF1 is at a high level, and the second to fourth frequency division control signals NF2 to PF2 are at low levels.

[0228] The first gate control signals Nscan1(p) in stage p to the first gate control signal Nscan1(p+3) in stage p+3 have a low level, and the first gate control signals Nscan1(p+4) in stage p+4 to the first gate control signal Nscan1(p+10) in stage p+10 have a high level. The third gate control signal Pscan1(p+4) in stage p+4 has a low level, and the third gate control signals Pscan1(p) in stage p to the third gate control signal Pscan1(p+3) in stage p+3, and the third gate control signals Pscan1(p+5) in stage p+5 to the third gate control signal Pscan1(p+11) in stage p+11 have a high level.

[0229] In the first gate drive circuit GA1(p+11) of the p+11th stage, the first transistor T1, the third transistor T3, the sixth transistor T6, the eighth transistor T8, and the fourth frequency division transistor Tf4 are turned on, while the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the first to third frequency division transistors Tf1 to Tf3, and the first to fourth output transistors To1 to To4 are turned off, causing the first gate control signal Nscan1(p+11) of the p+11th stage to maintain a low level and the third gate control signal Pscan1(p+11) of the p+11th stage to maintain a high level.

[0230] The second gate control signals Nscan2(p) in stage p to stage p+3, and Nscan2(p+8) in stage p+8 to stage p+11, have low levels, while the second gate control signals Nscan2(p+4) in stage p+4 to stage p+7, have high levels. The fourth gate control signal Pscan2(p+4) in stage p+4 has a low level, while the fourth gate control signals Pscan2(p) in stage p to stage p+3, and Pscan2(p+5) in stage p+5 to stage p+11, have high levels.

[0231] In the 10th stage t10, the first clock signal CK1 is at a high level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a low level. The first frequency division control signal NF1 and the second frequency division control signal NF2 are at a high level, and the third frequency division control signal PF1 and the fourth frequency division control signal PF2 are at a low level.

[0232] The first gate control signals Nscan1(p) in stage p to stage p+6, Nscan1(p+6) in stage p+11, and subsequent first gate control signals Nscan1 have a low level, while the first gate control signals Nscan1(p+7) in stage p+7 to stage p+10 have a high level. The third gate control signal Pscan1(p+7) in stage p+7 has a low level, while the third gate control signals Pscan1(p) in stage p to stage p+6, and the third gate control signals Pscan1(p+8) in stage p+8 to stage p+1 have a high level.

[0233] The second gate control signals Nscan2(p) in stage p to stage p+6, Nscan2(p+6) in stage p+11, and subsequent second gate control signals Nscan2 have a low level, while the second gate control signals Nscan2(p+7) in stage p+7 to stage p+10 have a high level. The fourth gate control signal Pscan2(p+7) in stage p+7 has a low level, while the fourth gate control signals Pscan2(p) in stage p to stage p+6, and the fourth gate control signals Pscan2(p+8) in stage p+8 to stage p+11 have a high level.

[0234] In the 11th stage t11, the first clock signal CK1 is at a low level, the second clock signal CK2 is at a high level, the third clock signal CK3 is at a high level, and the fourth clock signal CK4 is at a high level. The first frequency division control signal NF1 and the second frequency division control signal NF2 are at a high level, and the third frequency division control signal PF1 and the fourth frequency division control signal PF2 are at a low level.

[0235] The first gate control signals Nscan1(p) in stage p to stage p+7, Nscan1(p+7) in stage p+11, and subsequent first gate control signals Nscan1 have a low level, while the first gate control signals Nscan1(p+8) in stage p+8 to stage p+10 have a high level. The third gate control signal Pscan1(p+8) in stage p+8 has a low level, while the third gate control signals Pscan1(p) in stage p to stage p+7, and the third gate control signals Pscan1(p+9) in stage p+9 to stage p+11 have a high level.

[0236] The second gate control signals Nscan2(p) in stage p to stage p+7, Nscan2(p+7) in stage p+11, and subsequent second gate control signals Nscan2 have a low level, while the second gate control signals Nscan2(p+8) in stage p+8 to stage p+10 have a high level. The fourth gate control signal Pscan2(p+8) in stage p+8 has a low level, while the fourth gate control signals Pscan2(p) in stage p to stage p+7, and the fourth gate control signals Pscan2(p+9) in stage p+9 to stage p+11 have a high level. In other words, the second gate drive circuit GA2(p+11) of the p+11th stage performs an operation similar to that performed by the first gate drive circuit GA1(p+11) of the p+11th stage in the 9th stage t9, at the 11th stage t11.

[0237] Next, the first gate drive circuit GA1(p+10) and the second gate drive circuit GA2(p+10) of the p+10 stage, based on the corresponding first and second clock signals, cause the first gate control signal Nscan1(p+10) and the second gate control signal Nscan2(p+10) of the p+10 stage to recover to a low level, and the third gate control signal Pscan1(p+10) and the fourth gate control signal Pscan2(p+10) of the p+10 stage to output a low level and then recover to a high level.

[0238] Therefore, by controlling the first frequency division control signal NF1, the level of the first gate control signal Nscan1 output from multiple first gate drive circuits GA1 can be controlled, and by controlling the second frequency division control signal NF2, the level of the second gate control signal Nscan2 output from multiple second gate drive circuits GA2 can be controlled. By controlling the change time from the effective level to the invalid level of the first frequency division control signal NF1 and the second frequency division control signal NF2, the first gate control signal Nscan1 and the second gate control signal Nscan2 are prevented from having an effective level output corresponding to the same stage.

[0239] Similarly, the level of the third gate control signal Pscan1 output from multiple first gate drive circuits GA1 can be controlled by controlling the third frequency division control signal PF1, and the level of the fourth gate control signal Pscan2 output from multiple second gate drive circuits GA2 can be controlled by controlling the fourth frequency division control signal PF2. By controlling the change time from the effective level to the invalid level of the third frequency division control signal PF1 and the fourth frequency division signal, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 are prevented from having an effective level output corresponding to the same stage. Accordingly, the timing diagrams corresponding to the change from the effective level to the invalid level of the third frequency division control signal PF1 or the fourth frequency division control signal PF2 of the first gate drive unit GM1 and the second gate drive unit GM2 are shown in Figure 8B, and the operating principle corresponding to the change from the effective level to the invalid level of the third frequency division control signal PF1 or the fourth frequency division control signal PF2 of the first gate drive unit GM1 and the second gate drive unit GM2 can be similarly obtained by referring to the operating principle from the effective level to the invalid level of the first frequency division control signal NF1 and the second frequency division control signal NF2.

[0240] For example, corresponding to Figure 8B, if the 12th stage t12 corresponds to the time before the third frequency division control signal PF1 changes from the active level to the inactive level, then the first gate control signal Nscan1(p+9) for the p+9th stage, output from the first gate drive circuit GA1(p+9) for the p+9th stage, has a high level, and the first gate control signal Nscan1(p+10) for the p+10th stage, output from the first gate drive circuit GA1(p+10) for the p+10th stage, has a low level. When the 13th stage t13 corresponds to the time after the 3rd frequency division control signal PF1 or the 4th frequency division control signal PF2 changes from an active level to an inactive level, in the 1st gate drive circuit GA1(p+11) of the p+11th stage, the 1st transistor T1, the 4th transistor T4, the 9th transistor T9, the 12th transistor T12, and the 1st to 3rd frequency division transistors Tf1 to Tf3 are turned on, while the 2nd transistor T2, the 3rd transistor T3, the 11th transistor T11, and the 4th frequency division transistor Tf4 are turned off. The turning off of the 4th frequency division transistor Tf4 in the 1st gate drive circuit GA1(p+11) of the p+11th stage causes the 3rd gate control signal Pscan1(p+11) of the p+11th stage to remain at a high level during the period when the 2nd clock signal corresponding to the 1st gate drive circuit GA1(p+11) of the p+11th stage is at a low level.

[0241] Similarly, the operating principle of the second gate drive unit GM2 when the fourth frequency division control signal PF2 changes from an active level to an inactive level can be obtained.

[0242] Similarly, the operating principle can be obtained when the first gate drive unit GM1 and the second gate drive unit GM2 change from an inactive level to an active level based on the corresponding frequency division control signal, but the explanation is omitted here.

[0243] By referring to the analysis in Figures 8A to 8B, the operating principle of the first gate drive unit GM1 or the second gate drive unit GM2 can be obtained when the first gate drive circuit GA1 or the second gate drive circuit GA2 includes two second output modules 50 and one second frequency division control module 60, and this explanation is omitted here. Accordingly, timing diagrams for the multiple gate control signals output from the first gate drive unit or the second gate drive unit are shown in Figures 8C to 8D.

[0244] Continuing with reference to Figures 1A and 1B, in some embodiments, the gate drive module GM further includes a third gate drive unit GM3 and a fourth gate drive unit GM4. The third gate drive unit GM3 includes a plurality of cascaded third gate drive circuits GA3, which are arranged to generate a plurality of fifth gate control signals Pscan and output them to the control terminals of a first initial transistor Ti1 and a second initial transistor Ti2 in a plurality of sub-pixels Spi. The fourth gate drive unit GM4 includes a plurality of cascaded fourth gate drive circuits GA4, which are arranged to generate a plurality of light emission control signals EM and output them to the control terminals of a first light emission control transistor Te1 and a second light emission control transistor Te2 in a plurality of sub-pixels Spi. Optionally, the plurality of third gate drive circuits GA3 are electrically connected to a plurality of fourth scan lines GL4, and the plurality of fourth gate drive circuits GA4 are electrically connected to a plurality of light emission control lines EL.

[0245] Optionally, each third gate drive circuit GA3 can drive a first initial transistor Ti1 and a second initial transistor Ti2 in at least one row of subpixels Spi, and each fourth gate drive circuit GA4 can drive a first light emission control transistor Te1 and a second light emission control transistor Te2 in at least one row of subpixels Spi.

[0246] Optionally, the third gate drive circuit GA3 and the fourth gate drive circuit GA4 may use the same or different circuit configurations, and the circuit configurations used by the third gate drive circuit GA3 and the fourth gate drive circuit GA4 may be referenced from the design of related technologies.

[0247] Figure 9 is a timing diagram of the write frame and hold frame corresponding to the subpixel provided by the embodiment of the present application. The operating principle of the pixel driving circuit will be explained using the case where the compensation transistor Tc and reset transistor Tr are N-type transistors, and the drive transistor Tdr, data transistor Tda, first light emission control transistor Te1, second light emission control transistor Te2, first initial transistor Ti1, and second initial transistor Ti2 are P-type transistors as an example.

[0248] In the first reset stage Si1, the light emission control signal EM transmitted by the light emission control line EL and the gate control signal received by the data transistor Tda (i.e., at least one of the third gate control signal Pscan1 and the fourth gate control signal Pscan2) are at a high level, the gate control signal received by the reset transistor Tr (i.e., the first gate control signal Nscan1) and the gate control signal received by the compensation transistor Tc (i.e., the second gate control signal Nscan2) are at a low level, and the fifth gate control signal Pscan transmitted by the fourth scan line GL4 is at a low level. The first initial signal transmitted by the first primary line VL1 is transmitted to the anode of the light-emitting element Di, realizing a potential reset of the anode of the light-emitting element Di. The second initial signal transmitted by the second primary line VL2 is transmitted to the input and output terminals of the drive transistor Tdr, realizing a potential reset of the input and output terminals of the drive transistor Tdr.

[0249] In the second reset stage Si2, the first gate control signal Nscan1, the light emission control signal EM, the third gate control signals Pscan1 and Pscan2 received by the data transistor Tda, and the fifth gate control signal Pscan are all at a high level, while the second gate control signal Nscan2 is at a low level. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the drive transistor Tdr, thereby resetting the potential of the control terminal of the drive transistor Tdr.

[0250] During the data writing phase Sw, the second gate control signal Nscan2, the light emission control signal EM, and the fifth gate control signal Pscan are at high levels, while the first gate control signal Nscan1, the third gate control signal Pscan1 received by the data transistor Tda, and the fourth gate control signal Pscan2 are at low levels. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the drive transistor Tdr.

[0251] Here, between the second reset stage Si2 and the data writing stage Sw, there is further a stage in which the reset transistor Tr and the compensation transistor Tc are controlled and turned on simultaneously, thereby transmitting the reset signal Vr to the output and input terminals of the drive transistor Tdr, thereby achieving a potential reset of the output and input terminals of the drive transistor Tdr.

[0252] In the third reset stage Si3, the light emission control signal EM, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda are at a high level, the first gate control signal Nscan1, the second gate control signal Nscan2, and the fifth gate control signal Pscan are at a low level, the first initial signal is transmitted to the anode of the light-emitting element Di, and the second initial signal is transmitted to the input and output terminals of the drive transistor Tdr.

[0253] In the light emission stage Sd, the third gate control signal Pscan1, the fourth gate control signal Pscan2, and the fifth gate control signal Pscan, received by the data transistor Tda, are at a high level, the light emission control signal EM, the first gate control signal Nscan1, and the second gate control signal Nscan2 are at a low level, the first light emission control transistor Te1 and the second light emission control transistor Te2 are turned on, and the drive transistor Tdr generates a drive current to drive the corresponding light-emitting element Di to emit light.

[0254] In the fourth reset stage Si4 and the fifth reset stage Si5, the light emission control signal EM, the third gate control signal Pscan1 and the fourth gate control signal Pscan2 received by the data transistor Tda are at a high level, the first gate control signal Nscan1, the second gate control signal Nscan2, and the fifth gate control signal Pscan are at a low level, the first initial signal is transmitted to the anode of the light-emitting element Di, and the second initial signal is transmitted to the input and output terminals of the drive transistor Tdr.

[0255] Here, the write frame WF includes a first reset stage Si1, a second reset stage Si2, a data write stage Sw, a third reset stage Si3, and an emission stage Sd, while the hold frame HF includes a fourth reset stage Si4, a fifth reset stage Si5, and an emission stage Sd.

[0256] In conjunction with the analysis of Figures 1A, 6A, 8A-8B, and 9, the principle of realizing frequency division on the display panel DP using the first gate drive unit GM1 and the second gate drive unit GM2 will be explained, using as an example the case where the control terminal of the compensation transistor Tc in the sub-pixel Spi of the L row is electrically connected to the first output terminal O1 of the first gate drive circuit GA1(K+1) of the K+1 stage, the control terminal of the reset transistor Tr in the sub-pixel Spi of the L row is electrically connected to the first output terminal O1 of the second gate drive circuit GA2(K-3) of the K-3 stage, the control terminal of the data transistor Tda in the sub-pixel Spi of the L row is electrically connected to the second output terminal O2 of the first gate drive circuit GA1(K) of the K stage and the second output terminal O2 of the second gate drive circuit GA2(K) of the K stage, and the gate drive circuit of the K stage uses the gate control signal output from the first output terminal O1 of the gate drive circuit of the K-1 stage as the control signal.

[0257] In the first frame F1 of one display cycle, new data signals are written to the control terminals of the drive transistors Tdr in multiple sub-pixels Spi. The first frequency division control signal NF1 and the fourth frequency division control signal PF2 maintain their active levels, controlling that all of the multiple rows of sub-pixels Spi in the display panel DP go through the writing frame WF stage shown in Figure 9. Here, one display cycle may include one frame or multiple frames. If one display cycle includes one frame, that frame is the writing frame WF corresponding to the multi-line sub-pixel Spi. If one display cycle includes multiple frames, the first frame F1 is the writing frame WF corresponding to the multiple rows of sub-pixels Spi.

[0258] In the second frame F2 of one display cycle, if the subpixels Spi of the first row to the Lth row of the display panel DP are displayed at a high frequency, and the subpixels Spi of the L+1th row and subsequent rows are displayed at a low frequency, then the first gate control signal Nscan1, the second gate control signal Nscan2, the third gate control signal Pscan1, and the fourth gate control signal Pscan2 used in correspondence with the subpixels Spi of the first row to the Lth row must all have active pulses, and as a result, the subpixels Spi of the first row to the Lth row all go through the write frame WF stage shown in Figure 9. On the other hand, the first gate control signal Nscan1, the second gate control signal Nscan2, the third gate control signal Pscan1, and the fourth gate control signal Pscan2, which are used in response to the sub-pixel Spi of the L row and the sub-pixel Spi of subsequent rows, do not need to have valid pulses. As a result, the sub-pixel Spi of the L row and the sub-pixel Spi of subsequent rows all go through the holding frame HF stage shown in Figure 9. Here, the second frame F2 is located after the first frame F1.

[0259] For example, taking the sub-pixel Spi of the L-1 row and the sub-pixel Spi of the n row as examples, the first gate control signal Nscan1 used for the sub-pixel Spi of the L-1 row is the first gate control signal Nscan1(K) of the K stage, the second gate control signal Nscan2 used for the sub-pixel Spi of the L-1 row is the second gate control signal Nscan2(K-4) of the K-4 stage, and the third gate control signal Pscan1 and the fourth gate control signal Pscan2 used for the sub-pixel Spi of the L-1 row are the third gate control signal Pscan1(K-1) and the fourth gate control signal Pscan2(K-1) of the K-1 stage, respectively. The timing of the first gate control signal Nscan1(K) in the K-stage in the second frame F2 corresponds to the form of the first gate control signal Nscan1 in the write frame WF in Figure 9, the timing of the second gate control signal Nscan2(K-4) in the K-4 stage in the second frame F2 corresponds to the form of the second gate control signal Nscan2 in the write frame WF in Figure 9, and the timing of the third gate control signal Pscan1(K-1) in the K-1 stage and the fourth gate control signal Pscan2(K-2) in the K-1 stage in the second frame F2 corresponds to the forms of the third gate control signal Pscan1 and the fourth gate control signal Pscan2 in the write frame WF in Figure 9.

[0260] On the other hand, the first gate control signal Nscan1 used for the sub-pixel Spi of the L row is the first gate control signal Nscan1(K+1) of the K+1 stage, the second gate control signal Nscan2 used for the sub-pixel Spi of the L row is the second gate control signal Nscan2(K-3) of the K-3 stage, and the third gate control signal Pscan1 and the fourth gate control signal Pscan2 used for the sub-pixel Spi of the L row are the third gate control signal Pscan1(K) of the K stage and the fourth gate control signal Pscan2(K) of the K stage. The timing of the first gate control signal Nscan1(K+1) of the K+1 stage in the second frame F2 corresponds to the form of the first gate control signal Nscan1 in the hold frame HF in Figure 9, the timing of the second gate control signal Nscan2(K-3) of the K-3 stage in the second frame F2 corresponds to the form of the second gate control signal Nscan2 in the hold frame HF in Figure 9, and the timing of the third gate control signal Pscan1(K) of the K stage and the fourth gate control signal Pscan2(K) of the K stage in the second frame F2 corresponds to the forms of the third gate control signal Pscan1 and the fourth gate control signal Pscan2 in the hold frame HF in Figure 9. Therefore, for the sub-pixel Spi of the L-1 row, the second frame F2 is still the write frame WF. On the other hand, for the sub-pixel Spi of the L row, the second frame F2 is the hold frame HF. In the second frame F2, the control terminal of the drive transistor Tdr in the L-1 row sub-pixel Spi has data signal writing capabilities, while the control terminal of the drive transistor Tdr in the L row sub-pixel Spi does not have data signal writing capabilities. The L-1 row sub-pixel Spi and the L row sub-pixel Spi have different corresponding refresh rates in the second frame F2, thereby enabling the display panel DP to perform frequency division display.

[0261] Optionally, in some embodiments, if one sub-pixel Spi corresponds to low-frequency display, the compensation transistor Tc, reset transistor Tr, and data transistor Tda are all reduced to low frequencies, i.e., the compensation transistor Tc, reset transistor Tr, and data transistor Tda are controlled to remain in the off state during the hold frame HF. Accordingly, since the sub-pixel Spi of the L-1st row uses the first gate control signal Nscan1(K) of the Kth stage, and the sub-pixel Spi of the Kth row uses the third gate control signal Pscan1(K) of the Kth stage and the fourth gate control signal Pscan2(K) of the Kth stage, the first gate control signal Nscan1(K) output from the first gate drive circuit GA1(K) of the Kth stage must satisfy the need for the sub-pixel Spi of the L-1st row to achieve high-frequency display, the third gate control signal Pscan1(K) output from the first gate drive circuit GA1(K) of the Kth stage must satisfy the need for the sub-pixel Spi of the Lth row to achieve low-frequency display, and the fourth gate control signal Pscan2(K) output from the second gate drive circuit GA2(K) of the Kth stage must satisfy the need for the sub-pixel Spi of the Lth row to achieve low-frequency display. Therefore, the first gate drive circuit GA1(K) of the K-stage needs to output a first gate control signal Nscan1(K) that simultaneously satisfies high-frequency needs, and also needs to output a third gate control signal Pscan1(K) that satisfies low-frequency needs. For this reason, within at least one frame after the first frame HF1 in one display cycle, the frequency of the first gate control signal Nscan1 output from at least one of the first gate drive circuits GA1 is greater than the frequency of the third gate control signal Pscan1.Similarly, the second gate drive circuits GA2(K-3) in the K-3rd stage to the second gate drive circuit GA2(K-1) in the K-1st stage need to output the fourth gate control signals Pscan2(K-3) in the K-3rd stage to the fourth gate control signals Pscan2(K-1) in the K-1st stage to simultaneously satisfy high-frequency needs, and also need to output the second gate control signals Nscan2(K-3) in the K-3rd stage to the second gate control signals Nscan2(K-1) in the K-1st stage to satisfy low-frequency needs. Therefore, within one display cycle, in at least one frame after the first frame HF1, the frequency of the second gate control signal Nscan2 output from at least one of the second gate drive circuits GA2 is smaller than the frequency of the fourth gate control signal Pscan2. In other words, when corresponding to the same gate drive circuit, there is a need to output gate control signals with different frequencies. Therefore, the matching design of the first gate drive unit GM1, the second gate drive unit GM2, the frequency division control signal, and the sub-pixel Spi provided by this application can satisfy the above-mentioned needs.

[0262] Similarly, if the sub-pixels Spi of the first row to the sub-pixels Spi of the Lth row of the display panel DP are displayed at a low frequency, and the sub-pixels Spi of the L+1th row and subsequent rows of sub-pixels Spi are displayed at a high frequency, the first gate drive circuit GA1(K) of the Kth stage must output a first gate control signal Nscan1(K) that simultaneously satisfies the low frequency needs, and also must output a third gate control signal Pscan1(K) that simultaneously satisfies the high frequency needs. Therefore, in one display cycle, within at least one frame from the first frame HF1 onward, the frequency of the first gate control signal Nscan1 output from at least one of the first gate drive circuits GA1(K) is smaller than the frequency of the third gate control signal Pscan1. Similarly, the second gate drive circuits GA2(K-3) in the K-3rd stage to the second gate drive circuit GA2(K-1) in the K-1st stage need to output the fourth gate control signals Pscan2(K-3) in the K-3rd stage to the fourth gate control signals Pscan2(K-1) in the K-1st stage, which simultaneously satisfy low-frequency needs, and also need to output the second gate control signals Nscan2(K-3) in the K-3rd stage to the second gate control signals Nscan2(n-1) in the K-1st stage, which simultaneously satisfy high-frequency needs. Therefore, within at least one frame after the first frame HF1 in one display cycle, the frequency of the second gate control signal Nscan2 output from at least one of the second gate drive circuits GA2 is greater than the frequency of the fourth gate control signal Pscan2. In other words, when corresponding to the same gate drive circuit, there is a need to output gate control signals with different frequencies.

[0263] Similarly, there is still a need for a single gate drive circuit to output gate control signals with different frequencies corresponding to the same gate drive circuit, in order to accommodate designs that include multiple second output modules. For example, in conjunction with the analysis in Figures 1B, 6B, 8C-8D, and 9, the control terminal of the compensation transistor Tc in the sub-pixel Spi of the L row to the L+X-1 row is electrically connected to the first output terminal O1 of the first gate drive circuit GA1(K) of the K stage, the control terminal of the reset transistor Tr in the sub-pixel Spi of the L row to the L+X-1 row is electrically connected to the first output terminal O1 of the second gate drive circuit GA2(K-2) of the K-2 stage, and the data transistor T in the sub-pixel Spi of the L row The case where the control terminal of da is electrically connected to one second output terminal O2 of the first gate drive circuit GA1(K) of the Kth stage and one second output terminal O2 of the second gate drive circuit GA2(K) of the Kth stage, and the control terminal of the data transistor Tda in the sub-pixel Spi of the L+X-1 row is electrically connected to another second output terminal O2 of the first gate drive circuit GA1(K) of the Kth stage and another second output terminal O2 of the second gate drive circuit GA2(K) of the Kth stage will be explained as an example.

[0264] In the second frame F2 of one display cycle, when the sub-pixels Spi of the first row to the sub-pixels Spi of the tenth row of the display panel DP are displayed at a high frequency, and the sub-pixels Spi of the eleventh row and subsequent rows of sub-pixels Spi are displayed at a low frequency, the first gate drive circuit GA1(6) of the sixth stage needs to output a first gate control signal Nscan1(6) that simultaneously satisfies the high frequency needs, and also needs to output the third gate control signals Pscan1(11) of the eleventh stage to the third gate control signals Pscan1(12) of the twelfth stage, which simultaneously satisfies the high frequency needs. The second gate drive circuit GA2(5) of the fifth stage needs to output the fourth gate control signals Pscan2(9) of the ninth stage to the fourth gate control signals Pscan2(10) of the tenth stage, which simultaneously satisfies the high frequency needs, and also needs to output the second gate control signal Nscan2(5) of the fifth stage, which simultaneously satisfies the low frequency needs. In other words, when the same gate drive circuit corresponds to including multiple second output modules, the gate drive circuit needs to output gate control signals having different frequencies. Therefore, the matching design of the first gate drive unit GM1, the second gate drive unit GM2, the frequency division control signal, and the sub-pixel Spi provided by this application can satisfy the above-mentioned needs.

[0265] In this specification, the principles and embodiments of the present application have been described using specific examples, but the descriptions of the above-mentioned embodiments are intended solely to aid in understanding the method and core idea of ​​the present application. Furthermore, those skilled in the art will know that there are variations in specific embodiments and scope of application based on the idea of ​​the present application. In summary, it should be understood that the description in this specification is not intended to limit the present application. [Explanation of symbols]

[0266] 10: Node control module 20: First frequency division control module 30: First output module 40: First control module 50: Second output module 60: Second frequency division control module 70: Switching module 80: Second control module 90: Initialization module

Claims

1. A display panel comprising a plurality of subpixels, at least one of which comprises a light-emitting element, a drive transistor, a compensation transistor, and a reset transistor, wherein the drive transistor is arranged to generate a drive current to drive the light-emitting element to emit light, the output terminal of the reset transistor and the output terminal of the compensation transistor are electrically connected to the control terminal of the drive transistor, the input terminal of the compensation transistor is electrically connected to the output terminal of the drive transistor, and the input terminal of the reset transistor is arranged to receive a reset signal. The gate drive module includes a plurality of frequency division control lines electrically connected to the display panel and transmitting frequency division control signals, a first gate drive unit, and a second gate drive unit, wherein the plurality of frequency division control signals include a first frequency division control signal and a second frequency division control signal, the first gate drive unit includes a plurality of first gate drive circuits cascaded together, the second gate drive unit includes a plurality of second gate drive circuits cascaded together, the first gate drive circuit is arranged to control the level of the generated first gate control signal based on the first frequency division control signal, and the second gate drive circuit is arranged to control the level of the generated second gate control signal based on the second frequency division control signal. Here, both the first gate drive circuit and the second gate drive circuit include a first output terminal, the control terminals of the compensation transistors in a plurality of subpixels are electrically connected to the first output terminals of the first gate drive circuits in a plurality of stages to receive a plurality of first gate control signals, the control terminals of the reset transistors in a plurality of subpixels are electrically connected to the first output terminals of the second gate drive circuits in a plurality of stages to receive a plurality of second gate control signals, and in the same subpixel, the frequency of the second gate control signal received by the reset transistor and the frequency of the first gate control signal received by the compensation transistor are the same. Display device.

2. At least one of the subpixels includes a data transistor, the input terminal of the data transistor is arranged to receive a data signal, and the output terminal of the data transistor is electrically connected to the input terminal of the drive transistor. Both the first gate drive circuit and the second gate drive circuit include a second output terminal, the second output terminal of the first gate drive circuit outputs a third gate control signal, and the second output terminal of the second gate drive circuit outputs a fourth gate control signal. Here, the control terminals of the data transistors in the plurality of subpixels are electrically connected to the second output terminals of the plurality of first gate drive circuits and / or the second output terminals of the plurality of second gate drive circuits. The display device according to claim 1.

3. Within one display cycle, within at least one frame from the first frame onward, the frequency of the first gate control signal output from at least one of the first gate drive circuits is greater than or less than the frequency of the third gate control signal. The display device according to claim 2.

4. Within one display cycle, within at least one frame from the first frame onward, the frequency of the second gate control signal output from at least one of the second gate drive circuits is less than or greater than the frequency of the fourth gate control signal. The display device according to claim 2.

5. The plurality of frequency division control lines include a first frequency division control line for transmitting the first frequency division control signal and a second frequency division control line for transmitting the second frequency division control signal, and both the first gate drive circuit and the second gate drive circuit are, A node control module is electrically connected to the first node and is arranged to control the signals of the first node based on a corresponding start signal and a first clock signal. A first frequency division control module is electrically connected to the first node, the second node, and the third node, and is arranged to control signal transmission between the first node and the second node based on the signal of the third node and the corresponding frequency division control signal. The system includes the first node, the second node, the first output terminal, and a first output module which is electrically connected and arranged to control a gate control signal output from the first output terminal based on signals from the first node and the second node, Here, the first frequency division control module in the first gate drive circuit of multiple stages is electrically connected to the first frequency division control line, and the first frequency division control module in the second gate drive circuit of multiple stages is electrically connected to the second frequency division control line. The display device according to claim 2.

6. At least one of the first gate drive circuit and the second gate drive circuit is A third node, a fourth node, and a second output module electrically connected to the second output terminal, and arranged to control the gate control signal output from the second output terminal based on the signals of the third node and the fourth node, and the corresponding second clock signal, A second frequency division control module is electrically connected to the node control module by the first and third nodes, electrically connected to the corresponding second output module by the fourth node, and is configured to control signal transmission between the first and fourth nodes based on the corresponding frequency division control signals. The display device according to claim 5.

7. The first gate drive circuit and the second gate drive circuit each include X second output modules and X second output terminals, and each second output module is electrically connected to one second output terminal. Here, the phase difference of the first clock signals corresponding to the first gate drive circuits of two adjacent stages is XH, the phase difference of the first clock signals corresponding to the second gate drive circuits of two adjacent stages is XH, X ≥ 1, and H represents the unit time length. The display device according to claim 6.

8. X > 1, and X second output modules in the same first gate drive circuit are arranged to output a plurality of third gate control signals having a phase difference, and X second output modules in the same second gate drive circuit are arranged to output a plurality of fourth gate control signals having a phase difference. The display device according to claim 7.

9. Each of the second output terminals is electrically connected to the control terminals of the data transistors in a plurality of subpixels in a row. The control terminals of the data transistors in the subpixels of rows L to L+X-1 are electrically connected in correspondence to the X second output terminals of the first gate drive circuit of the K stage and / or the X second output terminals of the second gate drive circuit of the K stage, where K≧1 and L=XK-(X-1). The display device according to claim 7.

10. X = 1, Here, the control terminal of the compensation transistor in the subpixel of the L row is electrically connected to the first output terminal of the first gate drive circuit of the K+1 stage, and the control terminal of the reset transistor in the subpixel of the L row is electrically connected to the first output terminal of the second gate drive circuit of the K-3 stage. The display device according to claim 7.

11. It further includes multiple clock lines, including a first clock line, a second clock line, a third clock line, and a fourth clock line. Here, the first clock signal corresponding to the first gate drive circuit of the 4m+1 stage and the second gate drive circuit of the 4m+1 stage is a signal transmitted by the corresponding second clock line, the second clock signal corresponding to the first gate drive circuit of the 4m+1 stage and the second gate drive circuit of the 4m+1 stage is a signal transmitted by the corresponding first clock line, the first clock signal corresponding to the first gate drive circuit of the 4m+2 stage and the second gate drive circuit of the 4m+2 stage is a signal transmitted by the corresponding third clock line, and the second clock signal corresponding to the first gate drive circuit of the 4m+2 stage and the second gate drive circuit of the 4m+2 stage is a signal transmitted by the corresponding second clock line. The first clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+3 stage is a signal transmitted by the corresponding fourth clock line, the second clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+3 stage is a signal transmitted by the corresponding third clock line, the first clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+4 stage is a signal transmitted by the corresponding first clock line, and the second clock signal corresponding to the first gate drive circuit and the second gate drive circuit of the 4m+4 stage is a signal transmitted by the corresponding fourth clock line. The display device according to claim 10.

12. X ≥ 2, Here, the control terminal of the compensation transistor in the subpixels of the L row to the L+X-1 row is electrically connected to the first output terminal of the first gate drive circuit of the K stage, and the control terminal of the reset transistor in the subpixels of the L row to the L+X-1 row is electrically connected to the first output terminal of the first gate drive circuit of the K-2 stage. The display device according to claim 7.

13. X = 2, and the display device further includes a plurality of clock lines, the plurality of clock lines including a first clock line, a second clock line, a third clock line, and a fourth clock line. Here, the first clock line transmits the corresponding second clock signal to one second output module in the second k+1 stage first gate drive circuit and one second output module in the second k+1 stage second gate drive circuit, the second clock line transmits the corresponding second clock signal to another second output module in the second k+1 stage first gate drive circuit and another second output module in the second k+1 stage second gate drive circuit, the third clock line transmits the corresponding second clock signal to one second output module in the second k+2 stage first gate drive circuit and one second output module in the second k+2 stage second gate drive circuit, and the fourth clock line transmits the corresponding second clock signal to another second output module in the second k+2 stage first gate drive circuit and another second output module in the second k+2 stage second gate drive circuit, where k ≥ 0. The display device according to claim 12.

14. The third clock line transmits the corresponding first clock signal to the first gate drive circuit of the 2k+1 stage and the second gate drive circuit of the 2k+1 stage, and the first clock line transmits the corresponding first clock signal to the first gate drive circuit of the 2k+2 stage and the second gate drive circuit of the 2k+2 stage. The display device according to claim 13.

15. The plurality of frequency division control lines include a third frequency division control line and a fourth frequency division control line, and the first gate drive circuit and the second gate drive circuit each include one second frequency division control module. Here, the second frequency division control module in the first gate drive circuit of multiple stages is electrically connected to the third frequency division control line, and the second frequency division control module in the second gate drive circuit of multiple stages is electrically connected to the fourth frequency division control line. The display device according to claim 6.

16. The control terminals of the data transistors in multiple subpixels of the same row are electrically connected to the second output terminals of multiple first gate drive circuits and the second output terminals of multiple second gate drive circuits. Here, the third frequency division control line is electrically connected to the fourth frequency division control line. The display device according to claim 15.

17. In the first gate drive circuit of multiple stages, the start signal corresponding to the first gate drive circuit of the first stage has a change from an active level to an inactive level at a first time, and in the second gate drive circuit of multiple stages, the start signal corresponding to the second gate drive circuit of the first stage has a change from an active level to an inactive level at a first time. The display device according to claim 6.

18. The first gate drive circuit of the multiple stages is electrically connected to the control terminal of the compensation transistor in the multiple subpixels in a one-sided drive manner, and the second gate drive circuit of the multiple stages is electrically connected to the control terminal of the reset transistor in the multiple subpixels in a one-sided drive manner. The display device according to claim 1.

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