Cascode voltage regulator circuit

Abstract

The example cascode voltage regulator circuit (300) has an input voltage terminal (V IN A first transistor (302) is coupled to the source terminal and configured as a source follower to provide an output voltage at the source terminal, and the source terminal and output terminal (V) of the first transistor (302) are connected. OUT The system includes a second transistor (310) coupled in series with the first transistor (302) and configured as a current limiter, and current mirrors (322 and 324) coupled between the first and second control terminals of the first and second transistors (302 and 310), respectively, which receive a first current indicating a source follower current flowing through the first transistor (302), and are configured to turn off the second transistor (310) by coupling the first and second control terminals together in response to the source follower current exceeding a certain threshold.

Description

[Technical Field]

[0001] This document describes voltage regulation in circuits, and more specifically, cascode voltage regulator circuits. [Background technology]

[0002] Voltage regulator circuits are used in a variety of applications. Generally, a transistor has a maximum allowable input voltage determined by the maximum drain-source voltage that it can handle without damage. However, there are some high-voltage applications where the desired input voltage exceeds the technical limits of the transistor. This limits the implementable circuit configurations and can restrict the ability to design and apply voltage regulator circuits in certain applications. Therefore, several significant challenges remain in developing voltage regulator circuits. [Overview of the Initiative]

[0003] As an example, the cascode voltage regulator circuit includes: a first transistor having a first current terminal, a second current terminal, and a first control terminal, the first current terminal of which is coupled to an input voltage terminal; a second transistor coupled between the second current terminal and the output terminal of the first transistor, the second control terminal of which is coupled; a third transistor coupled between the second current terminal and the output terminal of the first transistor, the third control terminal of which is coupled to the second control terminal of the second transistor; a fourth transistor coupled between the first control terminal and the second control terminal, the fourth control terminal of which is coupled; and a fifth transistor coupled between the first control terminal and the fourth control terminal, the fifth control terminal of which is coupled to the fourth control terminal.

[0004] In another example, the cascode voltage regulator circuit includes a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at its source terminal; a second transistor coupled in series between the source terminal and output terminal of the first transistor and configured as a current limiter; and a current mirror coupled between the first control terminal and the second control terminal of the first and second transistors, respectively, which receives a first current indicating a source follower current flowing through the first transistor and is configured to turn off the second transistor by coupling the first control terminal and the second control terminal in response to the source follower current exceeding a certain threshold.

[0005] According to another example, a cascode voltage regulator circuit comprises a drain-extended n-channel metal oxide semiconductor (NMOS) transistor having a first gate terminal and coupled to a first input voltage terminal, a drain-extended p-channel metal oxide semiconductor (PMOS) transistor coupled in series between the source terminal and output terminal of the drain-extended NMOS transistor, a first reference output terminal coupled to the second gate terminal of the drain-extended NMOS transistor, and a second reference output terminal coupled to the second gate terminal of the drain-extended PMOS transistor, wherein a first control voltage is generated at the first gate terminal, and The device includes a reference generator circuit configured to provide a second control voltage at a second gate terminal, wherein the second control voltage differs from the first control voltage by a certain offset amount; a current mirror comprising a first transistor coupled between the first gate f terminal and the second gate terminal and having a first control terminal, and a second transistor whose second control terminal is coupled to the first control terminal; and a current sensing circuit coupled to the source terminal, second control terminal and output terminal of a drain-extended NMOS transistor, wherein the second transistor is coupled in series between the first gate terminal and the current sensing circuit. [Brief explanation of the drawing]

[0006] [Figure 1] A block diagram of an electrical system including a cascode voltage regulator circuit in one example.

[0007] [Figure 2] A plan view showing a drain extension transistor configuration in one example.

[0008] [Figure 3] A schematic diagram of a cascode voltage regulator circuit in one example.

[0009] [Figure 4] A diagram showing voltage as a function of time in one example.

[0010] [Figure 5] A schematic diagram of a reference generator circuit in one example.

Mode for Carrying Out the Invention

[0011] Cascode voltage regulator circuits are described. In some embodiments, the cascode voltage regulator circuit is configured to have a drain-extended transistor to adapt to higher input voltages, thereby making the circuit suitable for use in a wider range of applications and systems. In one such embodiment, the cascode voltage regulator circuit includes a drain-extended n-channel metal-oxide-semiconductor (NMOS) transistor configured as a source follower to provide a regulated output voltage that is biased to an intermediate voltage between two limits of input voltages (e.g., between a supply voltage and a reference voltage such as ground). In some such embodiments, a drain-extended p-channel metal-oxide-semiconductor (PMOS) transistor is coupled in series with the source follower and configured to provide a current-limiting function to protect the circuit. A current mirror may be coupled between the gate of the drain-extended NMOS transistor and the gate of the drain-extended PMOS transistor, receiving a current indicating the source follower current flowing through the NMOS transistor, and may be configured to turn off the PMOS transistor by coupling the gates of the drain-extended NMOS transistor and the drain-extended PMOS transistor in response to the source follower current exceeding a certain threshold. In some such examples, the cascode voltage regulator circuit may include a current sensing circuit configured to provide a current indicating the source follower current. A low-power reference generator circuit may be configured to supply an offset bias voltage to the gates of NMOS and PMOS drain extension transistors.

[0012] overview As described above, several major challenges are associated with developing voltage regulator circuits. For example, there are applications where the desired input voltage exceeds the maximum allowable input voltage set by the maximum drain-source voltage of the transistor used in the circuit. Drain-extended transistors exhibit asymmetric voltage growth by allowing the voltage in the drain region to be substantially higher than that in the gate, source, or body regions. Drain-extended transistors can be limited in principle by the breakdown voltage from the n-well (body or drain) to the p-well (body or drain). However, these devices can withstand higher input voltages because, as will be further described below, the breakdown voltage from the outer n-well to the p-substrate can be substantially higher than the drain-source voltage.

[0013] Accordingly, voltage regulator circuits that may be configured to accommodate higher input voltages, including a cascode configuration and a drain extension transistor, are described herein. As will be further described later, some embodiments provide an open-loop cascode circuit with robust current limiting for short-circuit protection. Some examples include low-power (e.g., current consumption of 1 microampere (μA) or less under normal operating conditions) reference generator circuits that provide a control voltage for the cascode circuit, while also providing an auxiliary output voltage that can be used for various internal functions (e.g., controller power or bias).

[0014] Electronic Systems Some examples of cascode voltage regulator circuits described herein can be used in any electronic system with a power supply having a voltage that exceeds the breakdown limit of transistor technology (e.g., exceeds the maximum drain-source voltage limit of the transistor) but is within the n-well breakdown voltage limit of that technology, so that it can be handled using drain-extended transistors. One example involves a high-voltage battery monitoring application where the monitored battery pack contains a large stack of series-connected battery cells. In such an application, the voltage across the battery pack can be significantly higher than the breakdown limit of transistor technology (e.g., tens to hundreds of volts higher). Therefore, one possible approach is to use multiple monitoring circuits to effectively "divide" the battery pack into smaller subunits and reduce the voltage to a level that can be handled by transistors. This approach adds relatively complex circuit elements and associated costs, which may be undesirable. In contrast, the cascode voltage regulator circuits described herein can operate in high-voltage applications and achieve a higher level of integration with relatively low complexity and cost.

[0015] Figure 1 illustrates an exemplary electronic system 100 for a battery monitoring application in which a high-voltage cascode regulator 300 according to an example described herein may be advantageously used. In the example of Figure 1, the electronic system 100 includes a battery monitoring integrated circuit (IC) 102 which includes a battery monitoring core / circuit 104 and a high-voltage cascode regulator circuit 300. In some embodiments, the battery monitoring IC 102 is coupled to a battery pack 106, which includes a plurality of battery cells coupled together in series. In another embodiment, the battery pack 106 may be integrated within the IC 102. The battery cells may be, for example, lithium-ion battery cells, but any battery technology may be used. The battery pack 106 may include any number of battery cells. In one example, the battery pack 106 includes about 40 battery cells. The battery pack 106 may be part of the electronic system 100 or coupled to the electronic system 100. In some cases, the electronic system 100 is implemented as a system-on-a-chip or as a chipset mounted on a printed circuit board (PCB) that can be mounted within the chassis of a multi-chassis system or other higher-level systems, but any number of implementations can be used. Although the term "system" is used, other terms such as "device" or "apparatus" can be applied equally.

[0016] As shown in Figure 1, the cascode voltage regulator circuit 300 is connected to the input voltage terminal 108, and the input voltage V IN It receives the input voltage V. In some examples, the input voltage V IN This is a relatively high voltage, such as approximately 20V, 200V, or higher, depending on the application. The cascode voltage regulator circuit 300 adjusts the output voltage V as will be described in more detail below. OUT The output terminal 110 provides the adjusted output voltage V. OUTIt is coupled to the output terminal to receive. The battery monitoring circuit 104 may include one or more sensing terminals, such as terminals TS, SRP, and SRN, as shown in Figure 1, which are used to monitor various characteristics of the battery pack 106, such as temperature, voltage, and / or charge. In the illustrated example, terminals SRP and SRN are terminals to which the sensing resistor 118 is coupled, so that SRP is on the positive side (for more positive voltages) of the sensing resistor and SRN is on the negative side (for more negative voltages) of the sensing resistor. Terminal TS is a temperature-appropriate voltage input that senses the voltage generated by the external thermistor 120. The battery monitoring circuit 104 may receive one or more control signals and / or provide one or more measurement output signals via the communication terminal 112 (for example, SDA and SCL in the example shown in Figure 1, but any number of data interfaces may be used). In the illustrated example, SCL and SDA relate to the I2C communication protocol, where SCL refers to the clock line used to synchronize data transmission over the I2C bus, and SDA is the data line.

[0017] In some examples, the output terminal 110 is coupled to a reference voltage terminal 114 (e.g., ground) via an external capacitor 116 (e.g., not part of the battery monitoring IC 102). In some applications, this capacitor 116 has a very large capacitance (e.g., nearly 1 μF or larger). As a result, this capacitor 116 may expose the cascode voltage regulator circuit 300 to possible short-circuit faults to ground or large inrush current starting conditions. Therefore, as will be described in more detail later, some embodiments of the cascode voltage regulator circuit include a current limiter to protect the circuit from such conditions.

[0018] Cascode voltage regulator circuit As described above, some embodiments of the cascode voltage regulator circuits described herein are configured to include drain-extended metal oxide semiconductor (MOS) devices for tolerably extend the input voltage range. Figure 2 illustrates illustrative implementations of drain-extended PMOS device 202 and drain-extended NMOS device 204 on a p-doped silicon substrate 206. Both devices include n-well regions 208 (identified as 208a and 208b, respectively) formed on the substrate 206. The PMOS device 202 includes a p-well drain 210 separated by a polysilicon (gate electrode) region 214 and a positive p-doped (P+) source 212. The NMOS device includes a p-well region 216. An n-well drain 218 and a positive n-doped (N+) source 202 are formed in the p-well region 216 and separated by a polysilicon (gate electrode) region 222. In yet another example, the gate electrode may be implemented using an electrode material other than polysilicon. The gate dielectric provided between the gate electrode and the channel region can be, for example, a native oxide of the channel region semiconductor material (e.g., a silicon channel region comprising a silicon dioxide gate dielectric and a polysilicon gate electrode). In each case, the breakdown voltage from the n-well to the p-well, represented by the Zener diodes 224a and 224b, is a first voltage level BV such as 100 volts (V). T This corresponds to the transistor technical breakdown limit mentioned above. The breakdown voltage from the outer n-well to the p-substrate is represented by Zener diodes 226a and 226b, and in some cases is around 200V, BV T A much higher second voltage level BV DE Therefore, one embodiment of the cascode voltage regulator circuit 300 utilizes this characteristic of the drain extension device so that the system in which it is used (e.g., battery monitoring IC 102) can, as described above, have a higher maximum input voltage V IN It makes it possible to adapt to it.

[0019] FIG. 3 illustrates an example of a cascode voltage regulator circuit 300 that may be implemented using a drain-extended transistor. The cascode voltage regulator circuit 300 includes a reference generator circuit 500 that provides two buffered control voltages V gate-n and V gate-p . An example of the reference generator circuit 500 will be described in more detail hereinafter with reference to FIG. 5. In the example of FIG. 3, the cascode voltage regulator circuit 300 includes a first transistor 302 coupled to an input supply voltage terminal 304. The first transistor 302 is configured as a cascode source follower and provides an adjusted output voltage at its current terminal (e.g., source) 306. The first transistor 302 has a first control terminal (e.g., gate) 308 and is driven by a first buffered control voltage V gate-n received at the first control terminal 308 from the reference generator circuit 500. A second transistor 310 is serially coupled to the first transistor 302 between the current terminal 306 of the first transistor 302 and an output voltage terminal 312 (which may correspond to the output terminal 110 in the example shown in FIG. 1). The second transistor 310 has a second control terminal (e.g., gate) 314 and is driven by a second buffered control voltage V gate-p received at the second control terminal 314 from the reference generator circuit 500. As described hereinafter, the second control voltage V gate-p may be offset from the first control voltage V gate-n by a certain amount. For example, the second control voltage V gate-p may be several volts lower than the first control voltage V gate-n . In one example, the second transistor 310 is configured to provide a current limiting function to protect the cascode voltage regulator circuit 300 against high current conditions, as will be further described hereinafter. In some such examples, the first transistor 302 is a drain-extended NMOS (DENMOS) transistor and the second transistor 310 is a drain-extended PMOS (DEPMOS) transistor.

[0020] The first transistor 302 is configured as a cascode source follower and has a regulated output voltage V OUT The adjusted output voltage V is provided at the output voltage terminal 312. OUT This generally corresponds to the voltage at the current terminal 306 of the first transistor 302, minus any small losses that may occur through the components in the circuit 300 between the current terminal 306 and the output voltage terminal 312. Figure 4 shows the input voltage V at the input supply voltage terminal 304. IN Adjusted output voltage V OUT This graph shows an example. Input voltage V IN When it rises, the output voltage V OUT Also, the control voltage V applied at the control terminal 308 of the first transistor 302 gate-n The threshold voltage level V is set by TH It rises until it reaches the output voltage V. OUT Next, as shown in Figure 4, the input voltage V IN Even if it continues to rise, it remains constant. Therefore, the output voltage V OUT The threshold level V TH It is adjusted to threshold level V. TH The specific value of may be set as needed by the reference generator circuit 500 and may be selected based on the application in which the cascode voltage regulator circuit 300 is used.

[0021] In some examples, the first transistor 302 is biased at an intermediate point between the supply voltage (VIN) at the input supply voltage terminal 304 and a reference voltage level, such as ground. Therefore, in such cases, the output voltage V OUT The input supply voltage V IN It is adjusted to half of it. However, in other examples, the first transistor 302 has an output voltage V OUTIt may be biased differently to set it to some other level. As described above, by using drain-extended transistor technology, relatively high input supply voltage levels can be accommodated by the cascode voltage regulator circuit 300. In one example, the first transistor 302 is a DENMOS transistor, and the first transistor 302 is biased to set the maximum input voltage V MAX The circuit elements can be configured such that the maximum input voltage V cannot exceed twice the maximum allowable drain-source voltage of the first transistor 302. However, in other examples, the maximum input voltage V MAX This may be more or less than twice the maximum allowable drain-source voltage.

[0022] Referring to Figure 5, an example of a reference generator circuit 500 according to a certain embodiment is illustrated. In this example, the reference generator circuit 500 includes a current source 502 configured to generate a reference current used to provide a reference voltage. The reference generator circuit 500 can be configured to set the reference voltage to a specific selected level, thereby allowing the reference generator circuit 500 to set the input voltage V IN Regardless of the value of , the current source 502 is designed to generate a stable reference voltage at its selected level that can be used by downstream circuit elements. In one example, the current source 502 is implemented using a depletion-mode transistor. A depletion-mode transistor built on a natural substrate without doping is naturally always on, and a negative applied voltage is used to turn it off. Therefore, using a depletion-mode transistor with its gate connected to its source provides a convenient implementation of the current source 502 that does not require additional circuit elements. However, in other examples, other implementations may be used.

[0023] In one example, to generate a reference voltage, the reference generator circuit 500 includes a breakdown diode 504, such as a Zener diode. The breakdown diode 504 may include, for example, a single Zener diode or a stack of two or more Zener diodes. The breakdown diode 504 generates a reference voltage based on the reference current supplied by the current source 502. As described above, the reference generator circuit 500 has two buffered control voltages V at the first reference output terminal 510 and the second reference output terminal 512, respectively. gate-n and V gate-p This generates the control voltage V. In one example, as described above, gate-n This corresponds to the reference voltage level generated by the breakdown diode 504, and the control voltage V gate-p This corresponds to a voltage level that is slightly offset from the reference voltage level. Therefore, the reference generator circuit 500 controls the voltage V gate-p The system includes an offset element 506 configured to generate a small drop at the reference voltage level for generating the input voltage V. In one example, the offset element is a Zener diode, but in other examples, other voltage drop elements may be used. IN In one example where is 200V, as described above, the reference voltage generated by the reference generator circuit 500 may be, for example, 100V, and the voltage drop generated by the offset element 506 may be, for example, 5V, but in other examples the voltage values ​​may be different.

[0024] The reference generator circuit 500 includes several transistors 508 (individually identified as transistors 508a to k) that perform various functions within the circuit. Transistor 508c operates to protect the current source 502. As shown in Figure 5, the gate of transistor 508c is coupled to terminal 514 of the breakdown diode 504, where a reference voltage is generated. Thus, transistor 508c operates to ensure that the current source 502 is not exposed to a voltage level higher than the reference voltage. In one example, transistor 508 is a depletion-mode transistor. Transistors 508b and 508d are coupled together in a current mirror configuration. Similarly, transistors 508f and 508i are coupled together in a current mirror configuration. In some examples, transistor 508 is implemented as a drain-extended transistor.

[0025] In some examples, a feedback loop may be created within the reference generator circuit 500. This is because the current source 502 provides a reference voltage level used to provide current through the breakdown diode 504 to provide a reference voltage, as described above, and that reference voltage level is fed back to the gate of transistor 508c to protect the current source 502. Thus, the reference voltage level is 0V (or close to 0V), and the input voltage V IN Under conditions where is non-zero (for example, 200V in the above example), the current source 502 is disconnected and does not generate current. In this situation, there is no reference current supplied to the current mirror, and the reference generator circuit 500 may self-lock. To prevent this condition, in one example, the reference generator circuit 500 includes a leakage start element 516 which operates to ensure that a leakage path exists through the leakage start element 516 in order to restart the circuit by starting to pull terminal 514 upward in voltage from the supply voltage terminal 304, if terminal 510 is grounded (for example, at 0V).

[0026] Referring again to Figure 3, in one example, the first transistor 302 and the second transistor 310 are large power transistors capable of providing high output current to drive downstream circuit elements in applications where the cascode voltage regulator circuit 300 is used. For example, in system 100 of Figure 1, the first transistor 302 may be capable of supplying the current required to operate any other circuit elements on the battery monitoring core 104 and / or the battery monitoring integrated circuit 102, based on a reference voltage supplied by the reference generator circuit 500. For example, the first transistor 302 may be capable of supplying a current of 50 milliamperes (or more) based on a reference voltage of 100V. In contrast, an example of the reference generator circuit 500 is configured to have a very low quiescent current (low IQ), for example, around 1 microampere, or possibly at the nanoampere level. Therefore, in operation, the first transistor 302 may be supplying an output current that is 50,000 times higher than the operating current of the reference generator circuit 500. Furthermore, in these examples where the first transistor 302 and the second transistor 310 are large power transistors, they may present very large gate capacitances to the reference generator circuit 500. As a result, any transients in the voltage and / or current at the gates of the first transistor 302 and the second transistor 310 may cause coupling within the reference generator circuit 500, which may destabilize the reference voltage and damage the reference generator circuit 500.

[0027] To address this potential concern, the example of the reference generator circuit 500 includes output stage components to protect the reference generator circuit 500. In particular, referring again to Figure 5, the reference generator circuit 500 includes transistors 508h and 508j configured as source followers to act as buffer elements for the first reference output terminal 510 and the second reference output terminal 512. As shown in Figure 5, transistor 508h is coupled between the input voltage terminal 304 and the first reference output terminal 510, with its control terminal coupled to the breakdown diode 504 (at terminal 514), providing a buffer element for the first reference output terminal 510. Transistor 508j is coupled between the input voltage terminal 304 and the second reference output terminal 512, with its control terminal coupled to the offset element 506, providing a buffer element for the second reference output terminal 512. Thus, the reference generator circuit 500 controls the control voltage V gate-n and V gate-p This is provided as a buffered control voltage.

[0028] Referring again to Figure 3, as described above, in some applications, the output voltage terminal 312 of the cascode voltage regulator circuit 300 may be coupled to a large external capacitor 116. The presence of this capacitor 116 may expose the first transistor 302 to possible short-circuit faults to ground or large inrush current starting conditions, as described above. In other applications and / or system configurations in which the cascode voltage regulator circuit 300 is used, other conditions, devices, or circuit elements may similarly pose a high current risk to the first transistor 302. Therefore, certain examples of the cascode voltage regulator circuit 300 include a current limiting function. In particular, as described above, in some examples, the second transistor 310 is coupled to the first transistor 302 and configured to act as a current limiter to protect the first transistor 302.

[0029] In one example, the current flowing through the second transistor 310 (and consequently through the first transistor 302) is monitored using a current sensing circuit. In the example shown in Figure 3, the current sensing circuit includes the second transistor 310, a sensing resistor 318, and a third transistor 316 connected in parallel to the fourth transistor 320. As shown in Figure 3, the third transistor has a first current terminal connected to the current terminal 306 of the first transistor 302 and a control terminal connected to the control terminal 314 of the second transistor 310. The sensing resistor 318 is connected in series between the second current terminal and the output voltage terminal 312 of the third transistor 316. The third transistor 318 senses the source follower current (for example, the current flowing through the second transistor 310 and consequently through the first transistor 302). The sensed current is dropped across the sensed resistor 318 and driven to a current mirror (implemented using a fifth transistor 322 and a sixth transistor 324) via a fourth transistor 320 coupled to the output voltage terminal 312, as shown in Figure 3. In some examples, the fourth transistor 320 is a DENMOS transistor. The current mirror dynamically limits the output current from the second transistor 310 (and thus the current flowing through the first transistor 302) via a feedback loop, resulting in robust current regulation for the first transistor 302.

[0030] Therefore, in the example in Figure 3, the fifth transistor 322 and the sixth transistor 324 are configured in a current mirror configuration, where the gates of transistors 322 and 324 are coupled together, the source terminals of transistors 322 and 324 are coupled together, and the drain terminal of the sixth transistor 324 is coupled to the gates of both transistors 322 and 324. As described above, in some examples, the two control voltages V output from the reference generator circuit 500 gate-n and V gate-pThese are offset from each other by a certain amount, for example, a few volts (e.g., 5V), thus resulting in a difference between the control terminals of the first transistor 302 and the second transistor 310. When the sensing current dropped across resistor 318 reaches a threshold corresponding to the threshold voltage of the fourth transistor 320, the current path is activated to the control terminals of transistors 322 and 324. As a result, the current mirror is turned on, and the voltage at the control terminal 314 of the second transistor 310 (V gate-p ) is increased, and the voltage (V) at the control terminal 308 of the first transistor 302 is increased. gate-n By making it equal to ), the second transistor 310 is turned off and the current is limited.

[0031] Therefore, in several embodiments and examples, we provide a compact cascode voltage regulator circuit that utilizes drain-extended transistor technology to handle high-voltage applications. The first transistor 302 provides voltage regulation as described above, and the second transistor 310 provides robust current regulation in combination with a current mirror and current sensing circuit. As described above, in some examples, the first transistor 302 and the second transistor 310 are large power transistors that can handle not only high input voltages but also high current loads. Thus, the first transistor 302 and the second transistor 310 may have a size W / L several times, or even many times, that of transistors 316, 322, and 324 (described as the width-to-length ratio (W / L) of the transistors). For example, transistors 316, 322, and 324 have a size W / L = 1, while the first transistor 302 and the second transistor 310 may have a size W / L = X, where X is a value greater than 1. In this case, the current mirror has a current limit I that turns off the second transistor 310. limit It can be calculated as follows: I limit =(X × Vth) Ms ) / R s Here, Vth Ms is the threshold voltage of transistor 320, and R s This is the resistance value of the sensing resistor 318.

[0032] In some cases where the regulated voltage provided by the first transistor 302 is high (e.g., 100V), in the event of a short circuit at output terminal 312 or other fault conditions, the power (wattage) encountered by circuit 300 can be high, even if the current is limited as described above. If the fault condition persists for a while, this high wattage could heat circuit 300, and potentially the integrated circuit on which circuit 300 is mounted (e.g., battery monitoring IC 102), to a temperature that could damage or even destroy components of circuit 300 or the chip on which circuit 300 is mounted. Therefore, in some cases, even in the event of a fault at output terminal 312, the circuit may remain operational and can be used to operate, for example, a temperature sensor or other circuit elements that can trigger a warning when a fault condition occurs (V AUX ) will be established.

[0033] Referring again to Figure 5, in some examples, the reference generator circuit 500 has an auxiliary output voltage V AUX This includes a third reference output terminal 518, which is provided with an auxiliary output voltage V. AUX V is the buffered output voltage and roughly corresponds to the reference voltage generated by the breakdown diode 504. Transistor 508a is configured as a source follower to act as a buffer element for the third reference output terminal 518. As shown in the figure, transistor 508a has a control terminal that is coupled in series between the input voltage terminal 304 and the third reference output terminal 518 and coupled to terminal 514 of the breakdown diode 504. As shown in the figure, the auxiliary voltage V is provided by the resistor 520 coupled in series between the input voltage terminal 304 and transistor 508a. AUX A current limit is provided for this. In some examples, the auxiliary voltage V AUX It can be used to deactivate circuit 300 in the event of a failure, for example, to supply a temperature sensor or a bandgap reference. However, in other examples, the auxiliary voltage V AUXThis may be used to supply various other low-IQ circuit elements. Auxiliary voltage V AUX This may be used to supply power to other active circuit elements when there is a short circuit or other fault at output terminal 312, or to supply various components or circuit elements via an additional path even when there is no fault condition associated with output terminal 312.

[0034] Further examples Example 1 is a cascode voltage regulator circuit, which includes a first transistor having a first current terminal, a second current terminal and a first control terminal, the first current terminal of which is coupled to an input voltage terminal; a second transistor coupled between the second current terminal and the output terminal of the first transistor, the second control terminal of which is coupled; a third transistor coupled between the second current terminal and the output terminal of the first transistor, the third control terminal of which is coupled to the second control terminal of the second transistor; a fourth transistor coupled between the first control terminal and the second control terminal, the fourth control terminal of which is coupled; and a fifth transistor coupled between the first control terminal and the fourth control terminal, the fifth control terminal of which is coupled to the fourth control terminal.

[0035] Example 2 includes the cascode voltage regulator circuit of Example 1, wherein the first transistor is a drain-extended n-channel metal-oxide-semiconductor (NMOS) transistor and the second transistor is a drain-extended p-channel metal-oxide-semiconductor (PMOS) transistor.

[0036] Example 3 includes a cascode voltage regulator circuit of either Example 1 or Example 2, the cascode voltage regulator circuit further includes a resistor, the resistor having a first resistor terminal coupled to an output terminal and a second resistor terminal coupled to a third transistor, the third transistor being coupled between the second current terminal and the second resistor terminal of the first transistor.

[0037] Example 4 includes the cascode voltage regulator circuit of Example 3, further including a sixth transistor having a sixth control terminal coupled between a fourth control terminal and an output terminal and coupled to a second resistor terminal.

[0038] Example 5 includes any one of the cascode voltage regulator circuits from Examples 1 to 4, the cascode voltage regulator circuit further includes a reference generator circuit having a first reference output coupled to a first control terminal of a first transistor and a second reference output coupled to a second control terminal of a second transistor.

[0039] Example 6 includes the cascode voltage regulator circuit of Example 5, wherein the reference generator circuit is configured to provide a first control voltage to a first control terminal of a first transistor and a second control voltage to a second control terminal of a second transistor, the first control voltage being approximately half of the input voltage applied at the input voltage terminal, and the first transistor is configured to provide an output voltage at a second current terminal, the output voltage being approximately equal to the first control voltage.

[0040] Example 7 includes the cascode voltage regulator circuit of Example 6, wherein the second control voltage differs from the first control voltage by a certain offset amount.

[0041] Example 8 includes any one of the cascode voltage regulator circuits from Examples 5-7, wherein the reference generator circuit includes a current source coupled to the input voltage terminal and a breakdown diode coupled to the current source, the breakdown diode being configured to generate a reference voltage based on the reference current supplied by the current source.

[0042] Example 9 includes the cascode voltage regulator circuit of Example 8, where the breakdown diode is a Zener diode.

[0043] Example 10 includes a cascode voltage regulator circuit from either Example 8 or Example 9, and the reference generator circuit further includes an offset element coupled between a first reference output and a second reference output.

[0044] Example 11 includes any one of the cascode voltage regulator circuits from Examples 8-10, and the reference generator circuit further includes a leakage start element coupled between the input voltage terminal and the breakdown diode.

[0045] Example 12 includes any one of the cascode voltage regulator circuits from Examples 1 to 11, where the first and second transistors are complementary transistors.

[0046] Example 13 provides an integrated circuit that includes any one of the cascode voltage regulator circuits from Examples 1 to 12 and a battery monitoring circuit coupled to the output terminal of the cascode voltage regulator circuit.

[0047] Example 14 includes the integrated circuit of Example 13, and further includes at least one sensor terminal and at least one communication terminal, wherein the battery monitoring circuit is coupled to at least one sensor terminal and at least one communication terminal.

[0048] Example 15 includes the integrated circuit of Example 14, wherein at least one sensor terminal includes a temperature sensing terminal that is coupled to a battery monitoring circuit.

[0049] Example 16 provides a cascode voltage regulator circuit comprising: a first transistor coupled to an input voltage terminal and configured as a source follower to provide an output voltage at its source terminal; a second transistor coupled in series between the source terminal and output terminal of the first transistor and configured as a current limiter; and a current mirror coupled between the first control terminal and the second terminal of the first and second transistors, respectively, wherein the current mirror receives a first current indicating a source follower current flowing through the first transistor and is configured to turn off the second transistor by coupling the first control terminal and the second control terminal together in response to the source follower current exceeding a certain threshold.

[0050] Example 17 includes the cascode voltage regulator circuit of Example 16, in which the first transistor is biased at the input voltage terminal to an intermediate voltage between the input voltage and the reference voltage.

[0051] Example 18 includes a cascode voltage regulator circuit from either Example 16 or 17, wherein the first transistor is a drain-extended n-channel metal-oxide-semiconductor (NMOS) transistor and the second transistor is a drain-extended p-channel metal-oxide-semiconductor (PMOS) transistor.

[0052] Example 19 includes any one of the cascode voltage regulator circuits from Examples 16-18, further including a current sensing circuit coupled to the source terminal of a first transistor, the control terminal of a second transistor, and a current mirror, the current sensing circuit being configured to supply a first current to the current mirror.

[0053] Example 20 includes the cascode voltage regulator circuit of Example 19, wherein the current mirror includes a third transistor coupled between a first control terminal and a second control terminal and having a third control terminal, and a fourth transistor coupled between the first control terminal and a current sensing circuit and having a fourth control terminal coupled to the third control terminal.

[0054] Example 21 includes the cascode voltage regulator circuit of Example 20, wherein the current sensing circuit includes a fifth transistor coupled to the source terminal of a first transistor and having a fifth control terminal coupled to the second control terminal of a second transistor; a resistor having a first resistor terminal and a second resistor terminal, the first resistor terminal of which is coupled to the fifth transistor and the second resistor terminal of which is coupled to the output terminal, such that the fifth transistor is coupled in series between the source terminal and the first resistor terminal of the first transistor; and a sixth transistor coupled between the fourth control terminal and the second resistor terminal of a fourth transistor and having a sixth control terminal coupled to the first resistor terminal.

[0055] Example 22 includes the cascode voltage regulator circuit of Example 21, where the first, second, third, fourth, fifth, and sixth transistors are drain-extended field-effect transistors (FETs).

[0056] Example 23 includes a cascode voltage regulator circuit from either Example 21 or 22, where the sixth transistor is a drain-extended n-channel metal-oxide-semiconductor (NMOS) transistor.

[0057] Example 24 includes any one cascode voltage regulator circuit from Examples 16 to 23, further including a reference generator circuit coupled to a current mirror, the reference generator circuit having a first reference output terminal coupled to a first control terminal of a first transistor and a second reference output terminal coupled to a second control terminal of a second transistor.

[0058] Example 25 includes the cascode voltage regulator circuit of Example 24, wherein the reference generator circuit is configured to provide a first control voltage at a first control terminal of a first transistor and a second control voltage at a second control terminal of a second transistor, the first control voltage being approximately half of the input voltage applied at the input voltage terminal, and the second control voltage being different from the first control voltage by a certain offset amount.

[0059] Example 26 includes a cascode voltage regulator circuit from either Example 24 or 25, wherein the reference generator circuit includes a current source coupled to the input voltage terminal and a breakdown diode coupled to the current source, the breakdown diode being configured to generate a reference voltage based on the reference current supplied by the current source.

[0060] Example 27 includes the cascode voltage regulator circuit of Example 26, where the breakdown diode is a Zener diode.

[0061] Example 28 includes any one of the cascode voltage regulator circuits from Examples 25-27, and the reference generator circuit further includes an offset element configured to generate an offset amount between a first control voltage and a second control voltage.

[0062] Example 29 includes any one of the cascode voltage regulator circuits from Examples 25-28, and the reference generator circuit further includes a leakage start element coupled between the input voltage terminal and the breakdown diode.

[0063] Example 30 provides an integrated circuit which includes any one cascode voltage regulator circuit from Examples 16 to 29, at least one sensor terminal, at least one communication terminal, and a battery monitoring circuit, the battery monitoring circuit being coupled to the output terminal of the cascode voltage regulator circuit, at least one sensor terminal, and at least one communication terminal.

[0064] Example 31 provides a cascode voltage regulator circuit, which includes a drain-extended n-channel metal oxide semiconductor (NMOS) transistor coupled to the input voltage terminal and having a first gate terminal, and a drain-extended p-channel metal oxide semiconductor (PMOS) transistor coupled in series to the source terminal and output terminal of the drain-extended NMOS transistor and having a second gate terminal. The cascode voltage regulator circuit further includes a reference generator circuit having a first reference output terminal coupled to the first gate terminal of a drain-extended n-channel NMOS transistor and a second reference output terminal coupled to the second gate terminal of a drain-extended PMOS transistor, configured to provide a first control voltage at the first gate terminal and a second control voltage at the second gate terminal, wherein the second control voltage differs from the first control voltage by a certain offset amount; a current mirror including a first transistor coupled between the first gate terminal and the second gate terminal and having a first control terminal, and a second transistor having a second control terminal coupled to the first control terminal; and a current sensing circuit coupled to the source terminal, second control terminal and output terminal of a drain-extended NMOS transistor, wherein the second transistor is coupled in series between the first gate terminal and the current sensing circuit.

[0065] Example 32 includes the cascode voltage regulator circuit of Example 31, wherein the current sensing circuit includes a resistor, the resistor having a first resistor terminal coupled to the output terminal and a second resistor terminal, a third transistor coupled in series to the source terminal of a drain-extended NMOS transistor and the second resistor terminal, and a third control terminal coupled to the second gate terminal of a drain-extended PMOS transistor, and a fourth transistor coupled between the second control terminal and the output terminal of the second transistor and having a fourth control terminal coupled to the second resistor terminal.

[0066] Example 33 includes the cascode voltage regulator circuit of Example 32, where the first, second, and third transistors are drain-extended field-effect transistors.

[0067] Example 34 includes a cascode voltage regulator circuit of one of Examples 32 and 33, wherein the first width-to-length ratio of the second transistor and the second width-to-length ratio of the third transistor are selected relative to each other to achieve a certain specified current-sensing-to-current-regulating ratio.

[0068] Example 35 includes any one of the cascode voltage regulator circuits from Examples 31 to 34, wherein the reference generator circuit includes a current source coupled to the input voltage terminal and a breakdown diode coupled to the input voltage terminal and the current source, the breakdown diode being configured to provide a reference voltage based on the reference current supplied by the current source.

[0069] Example 36 includes the cascode voltage regulator circuit of Example 35, wherein the reference generator circuit further includes an offset element coupled between a first reference output terminal and a second reference output terminal.

[0070] Example 37 includes the cascode voltage regulator circuit of Example 36, where the breakdown diode and offset element are Zener diodes.

[0071] Example 38 includes a cascode voltage regulator circuit from either Example 36 or 37, wherein the reference generator circuit includes a first buffer element coupled between a breakdown diode and a first reference output terminal, and a second buffer element coupled between an offset element and a second reference output terminal.

[0072] Example 39 provides an integrated circuit comprising any one cascode voltage regulator circuit from Examples 31 to 38, at least one sensor terminal, at least one communication terminal, and a battery monitoring circuit, wherein the battery monitoring circuit is coupled to the output terminal of the cascode voltage regulator circuit, at least one sensor terminal, and at least one communication terminal.

[0073] In this description, the term “to connect” may encompass any connection, communication, or signaling path that enables a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, if the intervening component C does not alter the functional relationship between device A and device B, device A is connected to device B via the intervening component C, so that device B is controlled by device A via the control signal generated by device A.

[0074] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) by the manufacturer at the time of manufacture to perform that function, and / or may be configured (or reconfigurable) by the user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the construction and / or layout of hardware components and device interconnections, or a combination thereof.

[0075] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless specifically otherwise stated, these terms are generally used to mean the interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0076] In this specification, a circuit or device described to include certain components may instead be adapted to be coupled to those components in order to form the described circuit element or device. For example, a structure described to include one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only semiconductor elements (e.g., semiconductor dies and / or integrated circuit (IC) packages) in a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources so that the described structure can be formed by an end user and / or a third party during or after manufacturing.

[0077] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field-effect transistor ("PFET") may be used in place of an n-channel field-effect transistor ("NFET") with little or no modification to the circuit. Other types of transistors (such as bipolar transistors (BJTs)) may also be used. Furthermore, devices may be mounted on or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs). References to transistor features such as gate, source, or drain are not intended to exclude any preferred transistor technology. For example, features such as source, drain, and gate are typically used to refer to an FET, and emitter, collector, and base are typically used to refer to a BJT. Such features may be used interchangeably herein. For example, a reference to the gate of a transistor may refer to the gate of an FET or the base of a BJT, and vice versa. In some examples, the control terminal may refer to either the gate of an FET or the base of a BJT. Any other transistor technology can also be used. Any such transistor can be used as a switch, with the gate, base, or other similar feature acting as a switch-selection input that can be driven to connect the source and drain (or, as applicable, the emitter and collector).

[0078] In this specification, a field-effect transistor (FET) being "on" (or switched off) means that a conduction channel exists in the FET and drain current can flow through the FET. In this specification, a field-effect transistor being "off" (or switched off) means that a conduction channel does not exist in the FET and drain current does not flow through the FET. However, current may still flow through the transistor's body diode even when the FET is "off".

[0079] The circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to the functionality available before the component substitution. Components indicated as resistors generally represent any one or more elements connected in series and / or parallel to provide the amount of impedance represented by the indicated resistor, unless otherwise specified. For example, a resistor or capacitor indicated and described herein as a single component may instead be multiple resistors or capacitors, each connected in parallel between the same nodes. For example, a resistor or capacitor indicated and described herein as a single component may instead be multiple resistors or capacitors, each connected in series between the same two nodes as a single resistor or capacitor.

[0080] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings herein. Unless otherwise stated herein, "approximately," "nearly," or "substantially" preceding a parameter means within ±10 percent of that parameter.

[0081] Modifications to the examples described are permitted within the scope of the claims, and other examples are also possible.

Claims

1. A cascode voltage regulator circuit, A first transistor having a first current terminal, a second current terminal, and a first control terminal, the first current terminal being coupled to an input voltage terminal, A second transistor coupled between the second current terminal and the output terminal of the first transistor, the second transistor having a second control terminal, A third transistor coupled between the second current terminal and the output terminal of the first transistor, the third transistor having a third control terminal coupled to the second control terminal of the second transistor, A fourth transistor having a fourth control terminal is coupled between the first control terminal and the second control terminal, A fifth transistor having a fifth control terminal coupled between the first control terminal and the fourth control terminal, and coupled to the fourth control terminal, A cascode voltage regulator circuit, including one.

2. A cascode voltage regulator circuit according to claim 1, wherein the first transistor is a drain-extended n-channel metal-oxide-semiconductor (NMOS) transistor and the second transistor is a drain-extended p-channel metal-oxide-semiconductor (PMOS) transistor.

3. The cascode voltage regulator circuit according to claim 1, further, A resistor having a first resistor terminal connected to the output terminal and a second resistor terminal connected to the third transistor, wherein the third transistor is connected between the second current terminal of the first transistor and the second resistor terminal. A cascode voltage regulator circuit, including one.

4. The cascode voltage regulator circuit according to claim 3, further, A sixth transistor having a sixth control terminal coupled between the fourth control terminal and the output terminal and coupled to the second resistor terminal, A cascode voltage regulator circuit, including one.

5. The cascode voltage regulator circuit according to claim 1, further, A reference generator circuit having a first reference output coupled to the first control terminal of the first transistor and a second reference output coupled to the second control terminal of the second transistor, A cascode voltage regulator circuit, including one.

6. A cascode voltage regulator circuit according to claim 5, The reference generator circuit is configured to provide a first control voltage to the first control terminal of the first transistor and a second control voltage to the second control terminal of the second transistor. The first control voltage is approximately half of the input voltage applied at the input voltage terminal. The first transistor is configured to provide a certain output voltage at the second current terminal, wherein the output voltage is approximately equal to the first control voltage. Cascode voltage regulator circuit.

7. A cascode voltage regulator circuit according to claim 6, wherein the second control voltage differs from the first control voltage by a certain offset amount.

8. A cascode voltage regulator circuit according to claim 1, wherein the first and second transistors are complementary transistors.

9. It is an integrated circuit, The cascode voltage regulator circuit according to claim 1, A battery monitoring circuit connected to the output terminal of the cascode voltage regulator circuit, An integrated circuit, including

10. The integrated circuit according to claim 9, further, At least one sensor terminal and At least one communication terminal, Includes, An integrated circuit in which the battery monitoring circuit is coupled to the at least one sensor terminal and the at least one communication terminal.

11. A cascode voltage regulator circuit, A first transistor, coupled to the input voltage terminal and configured as a source follower to provide an output terminal at the source terminal, A second transistor is coupled in series between the source terminal and output terminal of the first transistor, and is configured as a current limiter. A current mirror coupled between the first control terminal and the second control terminal of the first transistor and the second transistor, The current mirror is configured to receive a first current indicating a source follower current flowing through the first transistor, and to turn off the second transistor by coupling the first control terminal and the second control terminal in response to the source follower current exceeding a certain threshold. Cascode voltage regulator circuit.

12. A cascode voltage regulator circuit according to claim 11, wherein in operation, the first transistor is biased to an intermediate voltage between the input voltage and a reference voltage at the input voltage terminal.

13. A cascode voltage regulator circuit according to claim 11, wherein the first transistor is a drain-extended n-channel metal-oxide-semiconductor (NMOS) transistor and the second transistor is a drain-extended p-channel metal-oxide-semiconductor (PMOS) transistor.

14. A cascode voltage regulator circuit according to claim 11, The present invention further includes a current sensing circuit coupled to the source terminal of the first transistor, the control terminal of the second transistor, and the current mirror, A cascode voltage regulator circuit is configured such that the current sensing circuit provides the first current to the current mirror.

15. A cascode voltage regulator circuit according to claim 14, wherein the current mirror is A third transistor having a third control terminal coupled between the first control terminal and the second control terminal, A fourth transistor coupled between the first control terminal and the current sensing circuit, the fourth transistor having a fourth control terminal coupled to the third control terminal, A cascode voltage regulator circuit, including one.

16. A cascode voltage regulator circuit according to claim 15, The current sensing circuit, A fifth transistor coupled to the source terminal of the first transistor, the fifth transistor having a fifth control terminal coupled to the second control terminal of the second transistor, A resistor having a first resistor terminal and a second resistor terminal, wherein the first resistor terminal is coupled to the fifth transistor and the second resistor terminal is coupled to the output terminal, such that the fifth transistor is coupled between the source terminal of the first transistor and the first resistor terminal. A sixth transistor coupled between the fourth control terminal and the second resistor terminal of the fourth transistor, the sixth transistor having a sixth control terminal coupled to the first resistor terminal, A cascode voltage regulator circuit, including one.

17. A cascode voltage regulator circuit according to claim 16, wherein the first, second, third, fourth, fifth, and sixth transistors are drain-extended field-effect transistors (FETs).

18. A cascode voltage regulator circuit according to claim 17, wherein the first and sixth transistors are drain-extended n-channel metal oxide semiconductor (NMOS) transistors, and the second transistor is a drain-extended p-channel metal oxide semiconductor (PMOS) transistor.

19. A cascode voltage regulator circuit according to claim 11, The system further includes a reference generator circuit coupled to the current mirror, The reference generator circuit has a first reference output coupled to the first control terminal of the first transistor and a second reference output coupled to the second control terminal of the second transistor. Cascode voltage regulator circuit.

20. A cascode voltage regulator circuit according to claim 19, The reference generator circuit is configured to provide a first control voltage at the first control terminal of the first transistor and a second control voltage at the second control terminal of the second transistor. The first control voltage is approximately half of the input voltage applied at the input voltage terminal. A cascode voltage regulator circuit in which the second control voltage differs from the first control voltage by a certain offset amount.

21. It is an integrated circuit, The cascode voltage regulator circuit according to claim 11, At least one sensor terminal and At least one communication terminal, A battery monitoring circuit is connected to the output terminal of the cascode voltage regulator circuit, the at least one sensor terminal, and the at least one communication terminal. An integrated circuit, including

22. A cascode voltage regulator circuit, A drain-extended n-channel metal oxide semiconductor (NMOS) transistor, coupled to an input voltage terminal and having a first gate terminal, A drain-extended p-channel metal oxide semiconductor (PMOS) transistor having a second gate terminal is coupled in series between the source terminal and output terminal of the drain-extended NMOS transistor, A reference generator circuit having a first reference output terminal coupled to the first gate terminal of the drain-extended NMOS transistor and a second reference output terminal coupled to the second gate terminal of the drain-extended PMOS transistor, wherein the reference generator circuit is configured to provide a first control voltage at the first gate terminal and a second control voltage at the second gate terminal, and the second control voltage differs from the first control voltage by a certain offset amount, A current mirror comprising: a first transistor coupled between the first gate terminal and the second gate terminal and having a first control terminal; and a second transistor having a second control terminal coupled to the first control terminal; A current sensing circuit is coupled to the source terminal, the second control terminal, and the output terminal of the drain-extended NMOS transistor. Includes, The second transistor is coupled in series between the first gate terminal and the current sensing circuit. Cascode voltage regulator circuit.

23. A cascode voltage regulator circuit according to claim 22, wherein the current sensing circuit is A resistor having a first resistor terminal and a second resistor terminal connected to the output terminal, A third transistor coupled in series between the source terminal and the second resistor terminal of the drain-extended NMOS transistor, the third transistor having a third control terminal coupled to the second gate terminal of the drain-extended PMOS transistor, A fourth transistor having a fourth control terminal coupled between the second control terminal and the output terminal of the second transistor and coupled to the second resistor terminal, A cascode voltage regulator circuit, including one.

24. A cascode voltage regulator circuit according to claim 23, wherein the first, second, and third transistors are drain-extended field-effect transistors.

25. It is an integrated circuit, The cascode voltage regulator circuit according to claim 22, At least one sensor terminal and At least one communication terminal, A battery monitoring circuit is connected to the output terminal of the cascode voltage regulator circuit, the at least one sensor terminal, and the at least one communication terminal. An integrated circuit, including

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