Display boards and display devices

Abstract

The display board has a first display area and a second display area. The display board includes light-emitting elements, pixel circuits, and data lines. The pixel circuits are located in the first display area. The pixel circuit array includes a first pixel circuit array, a second pixel circuit array, a third pixel circuit array, and a fourth pixel circuit array. The first and second pixel circuit arrays are arranged alternately in the row direction, and the third or fourth pixel circuit array is located between adjacent first and second pixel circuit arrays. The first or third pixel circuit array is configured to drive the corresponding light-emitting elements to emit first and second color light, and the second or fourth pixel circuit array is configured to drive the corresponding light-emitting elements to emit third color light. The data lines are electrically connected to the pixel circuit arrays. The data lines include a first data line electrically connected to a third pixel circuit array, the first data line located between the third pixel circuit array and the second pixel circuit array.

Description

Technical Field

[0001] (Cross - reference to Related Applications) This application claims the priority of a Chinese patent application with application number 202310477789.9, filed on April 27, 2023, the entire content of which is incorporated herein by reference.

[0002] This disclosure relates to the field of display technologies, and in particular, to display substrates and display devices.

Background Art

[0003] With the development of display technologies, a full - screen display with a camera (abbreviated as FDC, Full Display with Camera) features an excellent screen - to - body ratio and is being applied to display products. In a full - screen display device, usually, optical elements such as cameras are arranged in the lower - side area of the screen of the display panel, significantly improving the screen - to - body ratio.

Summary of the Invention

Means for Solving the Problems

[0004] According to one embodiment, a display board is provided. The display board has a first display area and a second display area, the first display area being located on at least one side of the second display area. The display board includes a plurality of light-emitting elements, a plurality of pixel circuits, and a plurality of data lines. The plurality of light-emitting elements include a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits are located in the first display area and are electrically connected to each of the plurality of light-emitting elements. The plurality of pixel circuits are arranged in a plurality of pixel circuit arrays, which include a plurality of first pixel circuit arrays and a plurality of second pixel circuit arrays electrically connected to the plurality of first light-emitting elements, and a plurality of third pixel circuit arrays and a plurality of fourth pixel circuit arrays electrically connected to the plurality of second light-emitting elements. The plurality of first pixel circuit arrays and the plurality of second pixel circuit arrays are arranged alternately in the row direction, and at least one of the plurality of third pixel circuit arrays or at least one of the plurality of fourth pixel circuit arrays is located between adjacent first and second pixel circuit arrays. The first or third pixel circuit array is configured to drive a corresponding light-emitting element to emit a first color light and a second color light, and the second or fourth pixel circuit array is configured to drive a corresponding light-emitting element to emit a third color light. A plurality of data lines are located in the first display area and are electrically connected to each of the plurality of pixel circuit arrays. The plurality of data lines include a first data line electrically connected to the third pixel circuit array, and the first data line is located between the third and second pixel circuit arrays.

[0005] In some embodiments, a first light-emitting element electrically connected to a first pixel circuit array adjacent to the third pixel circuit array constitutes a target light-emitting element. The orthogonal projection of the first data lines onto the plane on which the display substrate is located and the orthogonal projection of the target light-emitting element onto the plane on which the display substrate is located do not overlap.

[0006] In some embodiments, the portion of the first data line adjacent to the target light-emitting element is linear, or the portion of the first data line adjacent to the target light-emitting element is wound along at least a portion of the edge of the target light-emitting element.

[0007] In some embodiments, a first light-emitting element electrically connected to a first pixel circuit array adjacent to the third pixel circuit array constitutes a target light-emitting element. The orthogonal projection of the first data lines onto the plane on which the display substrate is located and the orthogonal projection of the target light-emitting element onto the plane on which the display substrate is located partially overlap. The display substrate further includes a shielding pattern located between the first data lines and the target light-emitting element in a direction perpendicular to the plane on which the display substrate is located, and the shielding pattern is configured to access constant voltage electrical signals.

[0008] In some embodiments, the shield pattern, the target light-emitting element, and the first data line partially overlap in their orthogonal projection onto the plane on which the display substrate is located.

[0009] In some embodiments, the first color light is red light, the second color light is blue light, and the third color light is green light. The target light-emitting element that emits red light constitutes a red target light-emitting element, and the target light-emitting element that emits blue light constitutes a blue target light-emitting element, and the area of ​​the red target light-emitting element is smaller than that of the blue target light-emitting element. In a direction perpendicular to the plane on which the display substrate is located, the shield pattern is located between the blue target light-emitting element and the first data line, and the orthogonal projections of the shield pattern, the blue target light-emitting element, and the first data line partially overlap on the plane on which the display substrate is located.

[0010] In some embodiments, at least two of the shield patterns are connected to form an integrated structure.

[0011] In some embodiments, the display substrate further includes a plurality of first voltage signal lines located in the first display area, each of which is electrically connected to the plurality of pixel circuit arrays. The display substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes the plurality of data lines and the plurality of first voltage signal lines. The second conductive layer is located between the first conductive layer and the plurality of light-emitting elements, and the second conductive layer includes the shielding pattern electrically connected to at least one of the plurality of first voltage signal lines.

[0012] In some embodiments, the orthogonal projection of the first light-emitting element, which is electrically connected to the second pixel circuit array adjacent to the third pixel circuit array, onto the plane on which the display substrate is located, and the orthogonal projection of the first data line onto the plane on which the display substrate is located, partially overlap.

[0013] In some embodiments, the plurality of light-emitting elements are arranged in a plurality of light-emitting element rows, and at least one light-emitting element row includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. Data lines are electrically connected to a pixel circuit row electrically connected to the plurality of first light-emitting elements in the light-emitting element row, and data lines are electrically connected to a pixel circuit row electrically connected to the plurality of second light-emitting elements in the light-emitting element row.

[0014] In some embodiments, at least one third pixel circuit array and at least one fourth pixel circuit array are arranged on one side in the row direction of the second display area. The fourth pixel circuit array is closer to the second display area than the third pixel circuit array.

[0015] In another embodiment, a display substrate is provided having a first display area and a second display area, wherein the first display area is located on at least one side of the second display area. The display substrate includes a plurality of light-emitting elements, a plurality of pixel circuits, a plurality of data lines, and a shielding pattern. The plurality of light-emitting elements include a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits are located in the first display area and are electrically connected to each of the plurality of light-emitting elements, and the plurality of pixel circuits are arranged in a plurality of pixel circuit arrays including a plurality of first pixel circuit arrays and a plurality of second pixel circuit arrays electrically connected to the plurality of first light-emitting elements, and a plurality of third pixel circuit arrays and a plurality of fourth pixel circuit arrays electrically connected to the plurality of second light-emitting elements. The plurality of first pixel circuit arrays and the plurality of second pixel circuit arrays are arranged alternately in the row direction, and at least one of the plurality of third pixel circuit arrays or at least one of the plurality of fourth pixel circuit arrays is located between adjacent first and second pixel circuit arrays. The first or third pixel circuit array is configured to drive a corresponding light-emitting element to emit a first color light and a second color light, and the second or fourth pixel circuit array is configured to drive a corresponding light-emitting element to emit a third color light. A plurality of data lines electrically connected to each of the plurality of pixel circuit arrays are located in the first display area, and the plurality of data lines include a first data line electrically connected to the third pixel circuit array. A first light-emitting element electrically connected to a first pixel circuit array adjacent to the third pixel circuit array constitutes a target light-emitting element. The orthogonal projection of the first data line onto the plane on which the display board is located and the orthogonal projection of the target light-emitting element onto the plane on which the display board is located partially overlap. In a direction perpendicular to the plane on which the display board is located, the shielding pattern is located between the first data line and the target light-emitting element, and the shielding pattern is configured to access a constant voltage electrical signal.

[0016] In some embodiments, the shield pattern, the target light-emitting element, and the first data line partially overlap in their orthogonal projection onto the plane on which the display substrate is located.

[0017] In some embodiments, the first color light is red light, the second color light is blue light, and the third color light is green light. The target light-emitting element that emits red light constitutes a red target light-emitting element, and the target light-emitting element that emits blue light constitutes a blue target light-emitting element, and the area of ​​the red target light-emitting element is smaller than that of the blue target light-emitting element. In a direction perpendicular to the plane on which the display substrate is located, the shield pattern is located between the red target light-emitting element and the first data line, and the orthogonal projections of the shield pattern, the red target light-emitting element, and the first data line partially overlap on the plane on which the display substrate is located.

[0018] In some embodiments, at least two of the shield patterns are connected to form an integrated structure.

[0019] In some embodiments, the display substrate further includes a plurality of first voltage signal lines located in the first display area, each of which is electrically connected to the plurality of pixel circuit arrays. The display substrate includes a first conductive layer and a second conductive layer. The first conductive layer includes the plurality of data lines and the plurality of first voltage signal lines. The second conductive layer is located between the first conductive layer and the plurality of light-emitting elements, and the second conductive layer includes the shielding pattern electrically connected to at least one of the plurality of first voltage signal lines.

[0020] In some embodiments, the first data line is located between the third pixel circuit array and the first pixel circuit array.

[0021] In some embodiments, the plurality of light-emitting elements are arranged in a plurality of light-emitting element rows, and at least one light-emitting element row includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. Data lines are electrically connected to a pixel circuit row electrically connected to the plurality of first light-emitting elements in the light-emitting element row, and data lines are electrically connected to a pixel circuit row electrically connected to the plurality of second light-emitting elements in the light-emitting element row.

[0022] In some embodiments, at least one third pixel circuit array and at least one fourth pixel circuit array are arranged on one side in the row direction of the second display area. The fourth pixel circuit array is closer to the second display area than the third pixel circuit array.

[0023] In yet another embodiment, a display substrate is provided having a first display area and a second display area, wherein the first display area is located on at least one side of the second display area. The display substrate includes a plurality of light-emitting elements, a plurality of pixel circuits, and a plurality of data lines. The plurality of light-emitting elements include a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. The plurality of pixel circuits are located in the first display area and are electrically connected to each of the plurality of light-emitting elements, and the plurality of pixel circuits are arranged in a plurality of pixel circuit arrays including a plurality of first pixel circuit arrays and a plurality of second pixel circuit arrays electrically connected to the plurality of first light-emitting elements, and a plurality of third pixel circuit arrays and a plurality of fourth pixel circuit arrays electrically connected to the plurality of second light-emitting elements. The plurality of first pixel circuit rows and the plurality of second pixel circuit rows are arranged alternately in the row direction, at least one of the plurality of third pixel circuit rows or at least one of the plurality of fourth pixel circuit rows is located between adjacent first and second pixel circuit rows, the first or third pixel circuit row is configured to drive a corresponding light-emitting element to emit a first color light and a second color light, and the second or fourth pixel circuit row is configured to drive a corresponding light-emitting element to emit a third color light. A plurality of data lines are located in the first display area and are electrically connected to each of the plurality of pixel circuit rows, the plurality of data lines include a first data line electrically connected to the third pixel circuit row, and a first light-emitting element electrically connected to a first pixel circuit row adjacent to the third pixel circuit row constitutes a target light-emitting element. The orthogonal projection of the first data line onto the plane where the display substrate is located and the orthogonal projection of the target light-emitting element onto the plane where the display substrate is located do not overlap.

[0024] In some embodiments, the portion of the first data line adjacent to the target light-emitting element is linear, or the portion of the first data line adjacent to the target light-emitting element is wound along at least a portion of the edge of the target light-emitting element.

[0025] In some embodiments, the orthographic projection of the display substrate of the first light-emitting element, which is electrically connected to the second pixel circuit row adjacent to the third pixel circuit row, onto the plane where the display substrate is located, and the orthographic projection of the first data line onto the plane where the display substrate is located partially overlap.

[0026] In some embodiments, the plurality of light-emitting elements are arranged in a plurality of light-emitting element rows, and at least one light-emitting element row includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. A data line electrically connected to a pixel circuit row electrically connected to the plurality of first light-emitting elements in the light-emitting element row is connected to a data line electrically connected to a pixel circuit row electrically connected to the plurality of second light-emitting elements in the light-emitting element row.

[0027] In some embodiments, at least one third pixel circuit row and at least one fourth pixel circuit row are arranged on one side in the row direction of the second display area. The fourth pixel circuit row is closer to the second display area than the third pixel circuit row.

[0028] According to a further aspect, a display device is provided. The display device includes the display substrate according to any of the above embodiments and an optical element located on the non-light-emitting side of the display substrate, and at least a part of the optical element is located in the second display area of the display substrate.

[0029] To more clearly explain the technical solutions of the present disclosure, the drawings used in some embodiments of the present disclosure are briefly described below. The drawings in the following description are only the drawings of some embodiments of the present disclosure, and it is obvious to those skilled in the art that other drawings can be obtained from these drawings. Also, the drawings in the following description do not limit the actual size of the products according to the embodiments of the present disclosure, and can be regarded as schematic drawings.

Brief Description of the Drawings

[0030] [Figure 1]This is a configuration diagram of a display device according to several embodiments. [Figure 2] Figure 1 is a cross-sectional view of the display device in the CC direction. [Figure 3] This is a configuration diagram of another display board according to several embodiments. [Figure 4] This is a film layer configuration diagram of a pixel circuit according to several embodiments. [Figure 5] These are equivalent circuit diagrams of pixel circuits and light-emitting elements according to several embodiments. [Figure 6] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 7] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 8] This is a timing chart of data signals related to several embodiments. [Figure 9] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 10] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 11] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 12] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 13] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 14] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 15] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 16] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 17] This is a configuration diagram of yet another display board relating to several embodiments. [Figure 18] Figure 17 is a cross-sectional view of the display board in the DD direction. [Figure 19] This is a diagram showing the configuration of a second conductive layer according to several embodiments. [Figure 20]This is a configuration diagram of yet another display board relating to several embodiments. [Figure 21] This is a configuration diagram of yet another display board relating to several embodiments. [Modes for carrying out the invention]

[0031] The following describes, with reference to the attached drawings, some of the technical solutions of the embodiments of this disclosure clearly and completely, although it is clear that the embodiments described are only some of the embodiments of this disclosure, not all of them. All other embodiments that can be obtained by those skilled in the art based on the embodiments provided by this disclosure are within the scope of this disclosure.

[0032] Unless otherwise stated in the context, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” are interpreted in an open and comprehensive sense, meaning “including, but not limited to.” In the description, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that certain features, structures, materials, or properties related to such embodiment or example are included in at least one embodiment or example of this disclosure. The general indications of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any specific features, structures, materials, or properties described may be included in any one or more embodiments or examples in any appropriate manner.

[0033] Hereafter, the terms “first” and “second” are for illustrative purposes only and should not be understood as implicitly indicating or suggesting the relative importance of, or referring to, the number of technical features. Therefore, the features defining “first” and “second” may explicitly or implicitly include one or more features. In the description of the embodiments of this disclosure, “multiple” means two or more unless otherwise specified.

[0034] In describing some embodiments, the terms “connection” and their derived expressions may be used. The term “connection” should be understood in a broad sense; for example, a “connection” may be a fixed connection, a detachable connection, an integral connection, a direct connection, or an indirect connection via an intermediate medium. The embodiments disclosed herein are not necessarily limited to those disclosed herein.

[0035] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0036] The use of “applicable” or “configured to” in this specification means open and inclusive language and does not exclude devices that are applicable or configured to perform additional tasks or steps.

[0037] Furthermore, the use of "based on" implies an open and inclusive language, as a process, step, calculation, or other action "based on" one or more conditions or values ​​may actually be based on additional conditions or exceed the stated values.

[0038] As used herein, “approximately,” “about,” or “approximately” includes the stated value and the mean value within a range of acceptable deviations of a particular value, the range of acceptable deviations being determined by a person skilled in the art, taking into account the measurement under consideration and the errors (i.e., limitations of the measuring system) associated with the measurement of the particular quantity.

[0039] As used herein, “parallel” and “perpendicular” include the described situation and similar situations, the range of such similar situations being within the range of acceptable deviations that a person skilled in the art would determine, for example, taking into account the measurement under consideration and the error associated with the measurement of a particular quantity (i.e., the limits of the measuring system). For example, “parallel” includes absolutely parallel and nearly parallel, where the range of acceptable deviation for nearly parallel may be, for example, a deviation of ±5°, and “perpendicular” includes absolutely perpendicular and nearly perpendicular, where the range of acceptable deviation for nearly perpendicular may be, for example, a deviation of ±5°.

[0040] When a layer or element is described as being on another layer or substrate, please understand that the layer or element may exist directly on the other layer or substrate, or an intermediate layer may exist between the layer or element and the other layer or substrate.

[0041] Exemplary embodiments are described herein with reference to sectional and / or plan views, which serve as ideal illustrative drawings. In the drawings, for clarity, the thickness of the layers and the area of ​​the regions are enlarged. Thus, variations in shape from the drawings are possible, for example, due to manufacturing techniques and / or tolerances. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, and include, for example, shape deviations due to manufacturing. For example, an etching region shown as a rectangle typically has curved characteristics. Thus, the regions shown in the drawings are essentially schematic, and their shapes do not represent the actual shapes of the regions in the apparatus, nor do they limit the scope of the exemplary embodiments.

[0042] In the circuit configuration (for example, a pixel circuit) according to the embodiments of this disclosure, the transistors used in the circuit configuration may be thin-film transistors (TFTs), field-effect transistors (MOSs), or other switching elements having the same characteristics. In the embodiments of this disclosure, thin-film transistors will be used as an example.

[0043] In the circuit configuration according to the embodiments of this disclosure, the first electrode of each transistor is either the source or the drain, and the second electrode of the transistor is either the source or the drain. The source and drain of the transistor may be structurally symmetrical, so they do not need to be structurally distinguishable; that is, the first and second electrodes of the transistor in the embodiments of this disclosure do not need to be structurally distinguishable. For example, if the transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain, and if the transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0044] In the circuit configuration according to the embodiments of this disclosure, the nodes such as the first node, the second node, etc., do not represent actual existing components, but rather represent the confluence points of related electrical connections in the circuit diagram; that is, these nodes are equivalent to the confluence points of related electrical connections in the circuit diagram.

[0045] The transistors included in the circuit configuration according to the embodiment of this disclosure may all be N-type transistors, or all be P-type transistors, or some may be N-type transistors and the other some may be P-type transistors.

[0046] The following schematic explanation will be given using the example where all transistors included in the circuit configuration of the embodiment of this disclosure are P-type transistors.

[0047] Some embodiments of this disclosure provide display devices that can be any product or component having display and image acquisition functions, such as mobile phones, tablet computers, desktop computers, laptop computers, handheld computers, notebook computers, super mobile personal computers, artificial intelligence devices, smart wearable devices, in-vehicle devices, smart home devices, and / or smart city devices.

[0048] The embodiments of this disclosure do not particularly limit the specific form of the display device described above. For the sake of explanation, the following description will use the case where the display device is a mobile phone as an example.

[0049] Figure 1 shows the planar structure of the display device, and Figure 2 shows the cross-sectional structure of the display device shown in Figure 1 in the CC direction.

[0050] The above-mentioned display device 1000 includes a display substrate 100. This display substrate 100 is, for example, an organic light-emitting diode (OLED) display substrate, a quantum dot light-emitting diode (QLED) display substrate, etc. Next, a schematic explanation will be given using the case where the display substrate 100 is an OLED display substrate as an example.

[0051] The display board 100 has a first display area A1 and a second display area A2, the first display area A1 is located on at least one side of the second display area A2, and at least a portion of the first display area A1 surrounds the second display area A2. For example, the area of ​​the first display area A1 is larger than the area of ​​the second display area A2.

[0052] Here, the number of second display areas A2 may be at least one, and the number of first display areas A1 may be, for example, one. Next, as shown in Figure 1, the configuration of the display board 100 will be schematically described assuming that the number of second display areas A2 is one.

[0053] For example, the first display area A1 can enclose the second display area A2. In this case, the shape of the second display area A2 may be, for example, a circle, an ellipse, a rectangle, etc.

[0054] For example, the first display area A1 may surround a portion of the second display area A2. That is, a portion of the boundary of the first display area A1 may overlap with a portion of the boundary of the second display area A2. In this case, the shape of the second display area A2 may be, for example, a rectangle, a rounded rectangle, a teardrop shape, or a semicircle.

[0055] For example, in the display board 100, the light transmittance of the portion located within the first display area A1 is smaller than the light transmittance of the portion located within the second display area A2. This allows ambient light to enter the other side of the display board 100 by passing through the portion located within the second display area A2 from one side of the display board 100.

[0056] As shown in Figure 2, the display device 1000 further includes an optical element 200. This optical element 200 is located on the non-light-emitting side of the display substrate 100. Here, the display substrate 100 has a display side for displaying images, and the non-light-emitting side is on the opposite side from the display side.

[0057] Alternatively, the optical element 200 may include a photosensitive element. For example, the photosensitive element may include an image acquisition device (e.g., a camera) or an infrared receiver. Here, the number of optical elements 200 can be selected according to actual requirements.

[0058] For example, at least a portion of the optical element 200 is located in the second display area A2. That is, the entire optical element 200 may be located in the second display area A2. Alternatively, the optical element 200 and the second display area A2 may be offset from each other, such that a portion of the optical element 200 is located in the second display area A2 and another portion is located outside the second display area A2.

[0059] In the display board 100, the light transmittance of the portion located within the first display area A1 is smaller than the light transmittance of the portion located within the second display area A2. Therefore, ambient light passes through the portion of the display board 100 located within the second display area A2 and enters the optical element 200, enabling the optical element 200 to operate.

[0060] Let's take the case where the optical element 200 is a camera as an example.

[0061] For example, if the optical element 200 is not operating, a portion of the display board 100 located in the second display area A2 will be displayable, allowing the entire display board 100 and the display device 1000 to display an image.

[0062] Furthermore, for example, when the optical element 200 is operating (e.g., a user taking a selfie), a portion of the display board 100 located in the second display area A2 may display a black screen, and the portion of the display board 100 located in the first display area A1 may display the user's selfie screen, making the position of the optical element 200 relatively clear. Alternatively, the entire portion of the display board 100 located in both the first display area A1 and the second display area A2 may display the user's selfie screen without displaying the position of the optical element 200.

[0063] In the embodiments of this disclosure, by setting the light transmittance of the portion of the display substrate 100 located in the second display area A2 and arranging the optical element 200 in the second display area A2, it is possible to improve the display area of ​​the display substrate 100 and the display device 1000, and improve the screen-to-body ratio, while ensuring that the optical element 200 operates normally.

[0064] Alternatively, the display device 1000 may include a frame housing the display board 100 and optical elements 200, a circuit board arranged within the frame, a display driver IC (Integrated Circuit), and other electronic components.

[0065] Figure 3 is a schematic diagram showing the configuration of the display board.

[0066] The display board 100 described above includes a base 1, a plurality of pixel circuits 2, and a plurality of light-emitting elements 3. The plurality of pixel circuits 2 are located on the base 1, and the plurality of light-emitting elements 3 are located on the side of the plurality of pixel circuits 2 that is away from the base 1.

[0067] The multiple pixel circuits 2 and multiple light-emitting elements 3 described above are electrically connected to each other. Specifically, the electrical connection method between the multiple pixel circuits 2 and the multiple light-emitting elements 3 is one in which the pixel circuits 2 and light-emitting elements 3 are electrically connected in a one-to-one correspondence, but is not limited to this. There are various configurations for the pixel circuit 2, and can be selected and installed according to the actual needs. Examples of pixel circuit 2 configurations include "6T1C", "7T1C", "6T2C", and "7T2C", but is not limited to these. Here, "T" represents a transistor, the number before "T" represents the number of transistors, "C" represents a storage capacitor, and the number before "C" represents the number of storage capacitors.

[0068] The pixel circuit 2 is configured as a "7T1C" configuration. Here, Figure 4 shows the film layer configuration of the pixel circuit 2, and Figure 5 shows the equivalent circuit configuration of the pixel circuit 2 and the light-emitting element 3. The pixel circuit 2 includes a first reset transistor T1, a switching transistor T2, a drive transistor T3, a compensation transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, and a holding capacitor Cst.

[0069] Referring to Figures 4 and 5, the gate of the first reset transistor T1 is electrically connected to the first reset signal terminal Res1, the first electrode of the first reset transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first reset transistor T1 is electrically connected to the first node N1. The gate of the switching transistor T2 is electrically connected to the scan signal terminal Gate, the first electrode of the switching transistor T2 is electrically connected to the data signal terminal Data, and the second electrode of the switching transistor T2 is electrically connected to the second node N2. The gate of the drive transistor T3 is electrically connected to the first node N1, the first electrode of the drive transistor T3 is electrically connected to the second node N2, and the second electrode of the drive transistor T3 is electrically connected to the third node N3. The gate of the compensation transistor T4 is electrically connected to the scan signal terminal Gate, the first electrode of the compensation transistor T4 is electrically connected to the third node N3, and the second electrode of the compensation transistor T4 is electrically connected to the first node N1. The gate of the first light emission control transistor T5 is electrically connected to the enable signal terminal EM, the first electrode of the first light emission control transistor T5 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the first light emission control transistor T5 is electrically connected to the second node N2. The gate of the second light emission control transistor T6 is electrically connected to the enable signal terminal EM, the first electrode of the second light emission control transistor T6 is electrically connected to the third node N3, and the second electrode of the second light emission control transistor T6 is electrically connected to the fourth node N4. The gate of the second reset transistor T7 is electrically connected to the second reset signal terminal Res2, the first electrode of the second reset transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4. The first terminal of the storage capacitor Cst is electrically connected to the first node N1, and the second terminal of the storage capacitor Cst is electrically connected to the first voltage signal terminal VDD. The anode of the light-emitting element 3 is electrically connected to the fourth node N4, and the cathode of the light-emitting element 3 is electrically connected to the second voltage signal terminal VSS.

[0070] During the operation of the pixel circuit 2, the first reset transistor T1 is turned on under the control of the first reset signal transmitted from the first reset signal terminal Res1, and can transmit the first initial signal transmitted from the first initial signal terminal Vinit1 to the first node N1. The second reset transistor T7 is turned on under the control of the second reset signal transmitted from the second reset signal terminal Res2, and can transmit the second initial signal transmitted from the second initial signal terminal Vinit2 to the fourth node N4.

[0071] The switching transistor T2 and the compensation transistor T4 are turned on under the control of the scanning signal transmitted from the scanning signal terminal Gate, and the data signal transmitted from the data signal terminal Data is transmitted to the first node N1 sequentially via the switching transistor T2, the drive transistor T3, and the compensation transistor T4, thereby compensating the threshold voltage.

[0072] The first light emission control transistor T5 and the second light emission control transistor T6 can be turned on under the control of an enable signal transmitted from the enable signal terminal EM, and the drive transistor T3 generates a drive signal based on the potential of the first node N1 and a first voltage signal supplied from the first voltage signal terminal VDD.

[0073] The drive signals generated by each pixel circuit 2 are transmitted to the corresponding light-emitting element 3, which controls the light emission state of the corresponding light-emitting element 3 (e.g., brightness, presence or absence of light emission). The multiple light-emitting elements 3 work together to display an image on the display board 100.

[0074] The multiple light-emitting elements 3 described above can emit light of multiple colors. For example, this light of multiple colors may be a first color light, a second color light, and a third color light. Alternatively, this light of multiple colors may be a first color light, a second color light, a third color light, and a fourth color light. Or, one of the first and second color lights may be red light, the other blue light, the third color light may be green light, and the fourth color light may be white light. Different light-emitting elements 3 can work together to display a color image on the display substrate 100.

[0075] Furthermore, various methods can be considered to ensure that the light transmittance of the portion of the display board 100 located within the first display area A1 is smaller than the light transmittance of the portion located within the second display area A2, and these can be selected according to actual requirements.

[0076] The plurality of light-emitting elements 3 include, for example, a plurality of first light-emitting elements 3a located in a first display area A1 and a plurality of second light-emitting elements 3b located in a second display area A2. The plurality of pixel circuits 2 include a first pixel circuit 2a electrically connected to each first light-emitting element 3a and a second pixel circuit 2b electrically connected to each second light-emitting element 3b.

[0077] For example, the first pixel circuit 2a is located in the first display area A1, and the second pixel circuit 2b is located in the second display area A2. Also, the distribution density of the second pixel circuit 2b is smaller than that of the first pixel circuit 2a (it can also be considered that the distribution density of the second light-emitting element 3b is smaller than that of the first light-emitting element 3a). This allows the spacing between two adjacent pixel circuits 2 or two adjacent light-emitting elements 3 in the second display area A2 to be increased, thereby increasing the light transmittance of the portion of the display substrate 100 located in the second display area A2.

[0078] Furthermore, for example, the first pixel circuit 2a is located in the first display area A1, and the second pixel circuit 2b is located in an area other than the second display area A2 (for example, the second pixel circuit 2b is located in the first display area A1 or the frame area). This makes it possible to reduce the amount of light-shielding structure in the second display area A2, and to increase the light transmittance of the portion of the display substrate 100 located in the second display area A2. In this case, the distribution density of the first light-emitting element 3a and the distribution density of the second light-emitting element 3b may be the same or different.

[0079] In the embodiments of this disclosure, the example described is one in which each first pixel circuit 2a and each second pixel circuit 2b are located in the first display area A1, and the distribution density of the first light-emitting element 3a and the distribution density of the second light-emitting element 3b are the same.

[0080] The above-mentioned multiple light-emitting elements 3 can emit, for example, a first color light, a second color light, and a third color light, and there are various arrangements of these multiple light-emitting elements 3.

[0081] For example, as shown in Figure 3, the multiple light-emitting elements 3 are arranged in multiple rows and multiple columns. These multiple columns of light-emitting elements 3 are arranged sequentially along a first direction X, and each column of light-emitting elements 3 includes multiple light-emitting elements 3 arranged sequentially along a second direction Y. These multiple rows of light-emitting elements 3 are arranged sequentially along a second direction Y, and each row of light-emitting elements 3 includes multiple light-emitting elements 3 arranged sequentially along the first direction X. The first direction X and the second direction Y are parallel to the base 1 and have an angle between them. For example, the first direction X and the second direction Y are perpendicular.

[0082] Here, the colors of light emitted by the light-emitting elements 3 in the same column may be the same or different. The colors of light emitted by the light-emitting elements 3 in the same row may be the same or different.

[0083] Alternatively, the light emitted by the light-emitting elements 3 in the same row may be of different colors. For example, among the light-emitting elements 3 in the same row, the light-emitting element 3 emitting the first color light, the light-emitting element 3 emitting the third color light, the light-emitting element 3 emitting the second color light, and the light-emitting element 3 emitting the third color light are arranged periodically.

[0084] Alternatively, the light emitted by the light-emitting elements 3 in the same row may be of different colors. For example, among the light-emitting elements 3 in the same row, the light-emitting elements 3 emitting the first color of light and the light-emitting elements 3 emitting the second color of light may be arranged periodically.

[0085] Alternatively, the light emitted by the light-emitting elements 3 in the same row may be of the same color. For example, the light-emitting elements 3 in the same row may emit light of a third color.

[0086] Naturally, the arrangement of the light-emitting elements 3 is not limited to these.

[0087] As shown in Figure 6, the multiple pixel circuits 2 are arranged in multiple pixel circuit arrays 2c that are sequentially arranged along a first direction X, and each pixel circuit array 2c includes multiple pixel circuits 2 that are sequentially arranged along a second direction Y. Here, the first pixel circuit 2a electrically connected to the first light-emitting element 3a and the second pixel circuit 2b electrically connected to the second light-emitting element 3b are located in different pixel circuit arrays 2c. Although only one arrangement scheme is schematically shown in Figure 6, the arrangement scheme of the pixel circuit arrays 2c is not limited to that shown in Figure 6.

[0088] For example, referring to Figures 3 and 6, the first pixel circuits 2a electrically connected to each first light-emitting element 3a are arranged in at least a plurality of first pixel circuit arrays 2c-1 and a plurality of second pixel circuit arrays 2c-2. The second pixel circuits 2b electrically connected to each second light-emitting element 3b are arranged in at least a plurality of third pixel circuit arrays 2c-3 and a plurality of fourth pixel circuit arrays 2c-4. That is, the plurality of pixel circuit arrays 2c include at least a plurality of first pixel circuit arrays 2c-1, a plurality of second pixel circuit arrays 2c-2, a plurality of third pixel circuit arrays 2c-3, and a plurality of fourth pixel circuit arrays 2c-4.

[0089] Here, the first pixel circuit array 2c-1 is configured to drive the corresponding light-emitting element 3 (i.e., the first light-emitting element 3a) to emit a first color light and a second color light, and the second pixel circuit array 2c-2 is configured to drive the corresponding light-emitting element 3 (i.e., the first light-emitting element 3a) to emit a third color light. The third pixel circuit array 2c-3 is configured to drive the corresponding light-emitting element 3 (i.e., the second light-emitting element 3b) to emit a first color light and a second color light, and the fourth pixel circuit array 2c-4 is configured to drive the corresponding light-emitting element 3 (i.e., the second light-emitting element 3b) to emit a third color light. Here, the first color light is, for example, red light, the second color light is, for example, blue light, and the third color light is, for example, green light.

[0090] In response to this, the arrangement of multiple light-emitting elements 3 is such that, within the same row, a light-emitting element 3 emitting a first color of light, a light-emitting element 3 emitting a third color of light, a light-emitting element 3 emitting a second color of light, and a light-emitting element 3 emitting a third color of light are arranged periodically. Of at least two rows of light-emitting elements 3, all of the light-emitting elements 3 in the same row emit the third color of light. At the same time, of at least two rows of light-emitting elements 3, light-emitting elements 3 emitting the first color of light and light-emitting elements 3 emitting the second color of light are arranged alternately.

[0091] For example, the plurality of light-emitting elements 3 are arranged in a plurality of light-emitting element rows 3c that are sequentially arranged along a first direction X, and each light-emitting element row 3c includes a plurality of light-emitting elements 3 that are sequentially arranged along a second direction Y. In the embodiments of this disclosure, a plurality of light-emitting elements 3 located in the same row and emitting a first color light and a second color light are defined as a first light-emitting element row, and a plurality of light-emitting elements 3 located in the same row and both emitting a third color light are defined as a second light-emitting element row. In the first direction X, the first light-emitting element rows and the second light-emitting element rows are arranged alternately.

[0092] Correspondingly, the plurality of first pixel circuit arrays 2c-1 and the plurality of second pixel circuit arrays 2c-2 are arranged alternately in the row direction (i.e., the first direction X). At least one third pixel circuit array 2c-3 or at least one fourth pixel circuit array 2c-4 is located between adjacent first pixel circuit arrays 2c-1 and second pixel circuit arrays 2c-2. Embodiments of this disclosure will be described with an example where one third pixel circuit array 2c-3 is located between adjacent first pixel circuit arrays 2c-1 and second pixel circuit arrays 2c-2, and one fourth pixel circuit array 2c-4 is located between adjacent first pixel circuit arrays 2c-1 and second pixel circuit arrays 2c-2.

[0093] Alternatively, at least one first pixel circuit array 2c-1 and / or at least one second pixel circuit array 2c-2 may be provided between two adjacent pixel circuit arrays 2c for electrical connection to the second light-emitting element 3b (i.e., two adjacent third pixel circuit arrays 2c-3, two adjacent fourth pixel circuit arrays 2c-4, or adjacent third pixel circuit arrays 2c-3 and fourth pixel circuit arrays 2c-4). This is advantageous in reducing the amount of misalignment between the first light-emitting element 3a and the pixel circuit 2 electrically connected to it.

[0094] For example, one first pixel circuit array 2c-1 or one second pixel circuit array 2c-2 is provided between two adjacent pixel circuit arrays 2c for electrical connection with the second light-emitting element 3b.

[0095] Furthermore, for example, between two adjacent pixel circuit arrays 2c for electrically connecting to the second light-emitting element 3b, one first pixel circuit array 2c-1 and one second pixel circuit array 2c-2 are provided.

[0096] Furthermore, for example, between two adjacent pixel circuit arrays 2c for electrically connecting to the second light-emitting element 3b, two first pixel circuit arrays 2c-1 and two second pixel circuit arrays 2c-2 are provided.

[0097] Furthermore, for example, between two adjacent pixel circuit arrays 2c for electrically connecting to the second light-emitting element 3b, three first pixel circuit arrays 2c-1 and three second pixel circuit arrays 2c-2 are provided.

[0098] It is understood that the partitioning of the above-mentioned multiple pixel circuit arrays 2c depends on the arrangement method of the light-emitting element 3. This means that these multiple pixel circuit arrays 2c can also partition a fifth pixel circuit array, a sixth pixel circuit array, etc., according to a specific arrangement method, and the embodiments of this disclosure are not limited thereto.

[0099] In some examples, as shown in Figures 6 and 7, the display board 100 further includes a plurality of data lines DL located in the first display area A1, each electrically connected to the plurality of pixel circuit arrays 2c. For example, these plurality of data lines DL and the plurality of pixel circuit arrays 2c are electrically connected in a one-to-one correspondence. The pixel circuit arrays 2c and data lines DL are arranged alternately in the first direction X. Here, the pixel circuit shown in Figure 7 is an enlarged configuration of the pixel circuit located in area D in Figure 6.

[0100] Here, the different data lines DL may each be located to the left of the pixel circuit array 2c to which they are electrically connected, or to the right of the pixel circuit array 2c to which they are electrically connected. This is advantageous in improving the regularity of the arrangement of the pixel circuit array 2c and the data lines DL.

[0101] Each data line DL can supply a data signal to the Data terminal of each pixel circuit 2 in the pixel circuit array 2c, which is electrically connected to the display board 100 when displaying an image on the board.

[0102] For example, when displaying a grayscale screen on the display board 100, the data signals transmitted by data lines DL electrically connected to the first pixel circuit array 2c-1 and the third pixel circuit array 2c-3 are as shown in Data1 in Figure 8, and the data signals transmitted by data lines DL electrically connected to the second pixel circuit array 2c-2 and the fourth pixel circuit array 2c-4 are as shown in Data2 in Figure 8. Because there is a difference between the brightness of the first color light and the brightness of the second color light, the data voltage V1 required for the pixel circuit 2 corresponding to the first color light is different from the data voltage V2 required for the second color light. Also, since both the first pixel circuit array 2c-1 and the third pixel circuit array 2c-3 can drive the corresponding light-emitting element 3 to emit the first and second color light, the voltage shown in Data1 fluctuates up and down. The voltage shown in Data2 (i.e., V3) hardly changes.

[0103] For the sake of convenience in the following explanation, the data line DL electrically connected to the third pixel circuit array 2c-3 is defined as the first data line DL1. Referring to Figures 7 and 9, in Figure 9 and the following related drawings, some conductive layers (e.g., the first gate conductive layer, the second gate conductive layer, the first source / drain conductive layer, etc.) are omitted, and each pixel circuit array 2c is represented by a part of the pattern in the second source / drain conductive layer (also called the first conductive layer FL1). The first conductive layer FL1 is explained below, so its explanation is omitted here. Here, the pixel circuit shown in Figure 9 is an enlarged configuration of the pixel circuit located in region E in Figure 6.

[0104] In one embodiment, as shown in Figures 6 and 9, the first data line DL1 is located on the side of the third pixel circuit array 2c-3 that is closer to the first pixel circuit array 2c-1. The installation positions of the other data lines are the same as those of the first data line DL1.

[0105] As the inventors of this disclosure have verified, parasitic capacitance occurs between the first data line DL1 and the adjacent first pixel circuit array 2c-1. This parasitic capacitance includes, in the pixel circuit 2 of the first pixel circuit array 2c-1, the parasitic capacitance between the first node N1 and the first data line DL1, and the parasitic capacitance between the fourth node N4 and the first data line DL1 (the parasitic capacitance between the anode of the first light-emitting element 3a electrically connected to the first pixel circuit array 2c-1 and the first data line DL1). When the voltage of the data signal transmitted by the first data line DL1 fluctuates up and down, the potential of the first data line DL1 and the first node N1 constituting the parasitic capacitance changes, the drive signal generated by the pixel circuit 2 to which the first node N1 belongs changes, and a difference in the brightness of the light emitted by the first light-emitting element 3a electrically connected to the pixel circuit 2 occurs. Furthermore, the potential of the fourth node N4, which constitutes the parasitic capacitance with respect to the first data line DL1, also changes, further affecting the brightness of the light emitted by the first light-emitting element 3a. As a result, a display abnormality occurs on the display board 100 (for example, the vertical line defect shown in Figure 10).

[0106] Furthermore, the inventors of this disclosure have found that most of the above-mentioned display abnormalities occur at the position of the first pixel circuit array 2c-1 adjacent to the first data line DL1, and that the above-mentioned vertical line defect phenomenon hardly occurs at any other position.

[0107] As a result, as shown in Figures 11 and 12, in the display substrate 100 according to some embodiments of the present disclosure, the first data line DL1 is located between the third pixel circuit array 2c-3 to which it is electrically connected and the second pixel circuit array 2c-2 adjacent to the third pixel circuit array 2c-3. In this case, the third pixel circuit array 2c-3 and the data line DL to which the first pixel circuit array 2c-1 is electrically connected are spaced apart between the first data line DL1 and the adjacent first pixel circuit array 2c-1. Although only one arrangement method is shown in Figure 11, the arrangement method of the pixel circuit array 2c is not limited to that shown in Figure 11. The pixel circuit shown in Figure 12 is an enlarged configuration of the pixel circuit located in region F of Figure 11.

[0108] This effectively increases the pitch between the first data line DL1 and the adjacent first pixel circuit array 2c-1, that is, it increases the pitch between the first data line DL1 and the first node N1 and the fourth node N4 in the pixel circuit 2 of the first pixel circuit array 2c-1, and furthermore, it effectively reduces the parasitic capacitance between the first data line DL1 and the first node N1 and the fourth node N4 in the pixel circuit 2 of the adjacent first pixel circuit array 2c-1.

[0109] The inventors of this disclosure detect parasitic capacitance between a first data line DL1 and an adjacent first pixel circuit array 2c-1, and the detection results are shown in Table 1 below. [Table 1]

[0110] In Table 1 above, reference numeral (i) indicates that, in one embodiment, the first data line DL1 is located on the side of the third pixel circuit array 2c-3 closer to the first pixel circuit array 2c-1. Reference numeral (ii) indicates that, in some embodiments of the present disclosure, the first data line DL1 is located between the third pixel circuit array 2c-3 and the second pixel circuit array 2c-2. N1-1 is the parasitic capacitance between the first node N1 of the pixel circuit 2, which is electrically connected to the first light-emitting element 3a that emits a first color light (e.g., red light), in the first pixel circuit array 2c-1, and the first data line DL1. N1-2 is the parasitic capacitance between the first node N1 of the pixel circuit 2, which is electrically connected to the first light-emitting element 3a that emits a second color light (e.g., blue light), in the first pixel circuit array 2c-1, and the first data line DL1. N4-1 is the parasitic capacitance between the fourth node N4 of the pixel circuit 2, which is electrically connected to the first light-emitting element 3a that emits a first color light (e.g., red light) in the first pixel circuit array 2c-1, and the first data line DL1. N4-2 is the parasitic capacitance between the fourth node N4 of the pixel circuit 2, which is electrically connected to the first light-emitting element 3a that emits a second color light (e.g., blue light) in the first pixel circuit array 2c-1, and the first data line DL1.

[0111] As can be seen from Table 1, in some embodiments of this disclosure, the parasitic capacitance between the first data line DL1 and the adjacent first pixel circuit array 2c-1 is significantly reduced compared to the embodiment described above. Here, the parasitic capacitance between the first data line DL1 and the first node N1 in the pixel circuit 2 of the adjacent first pixel circuit array 2c-1 is reduced to 2aF or less, and the parasitic capacitance between the first data line DL1 and the fourth node N4 in the pixel circuit 2 of the adjacent first pixel circuit array 2c-1 is reduced to 1fF or less.

[0112] As a result, in some embodiments of the present disclosure, the display board 100 provides a first data line DL1 between a third pixel circuit array 2c-3 electrically connected to it and a second pixel circuit array 2c-2 adjacent to the third pixel circuit array 2c-3, thereby effectively increasing the pitch between the first data line DL1 and the adjacent first pixel circuit array 2c-1, effectively reducing the parasitic capacitance between the first data line DL1 and the adjacent first pixel circuit array 2c-1, and transmitting data via the first data line DL1. The data signal can reduce the influence on the potentials of the first node N1 and the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1. Furthermore, the accuracy of the drive signal generated by the pixel circuit 2 in the first pixel circuit array 2c-1 adjacent to the first data line DL1 can be improved, reducing the brightness difference of the light emitted by the first light-emitting element 3a electrically connected to this pixel circuit 2, thereby improving or eliminating vertical line defects in the display board 100 and improving the display effect of the display board 100.

[0113] It is understood that there are various ways in which the first data line DL1 is placed between the third pixel circuit array 2c-3 electrically connected to it and the second pixel circuit array 2c-2 adjacent to the third pixel circuit array 2c-3, and that this is not limited to the following example.

[0114] In some examples, the positions of the first data line DL1, the third pixel circuit array 2c-3 electrically connected to it, the first pixel circuit array 2c-1 adjacent to the first data line DL1, and the data line DL electrically connected to the first pixel circuit array 2c-1 are swapped. This improves the display effect of the display board 100 while reducing layout variations and design difficulty of the display board 100.

[0115] As can be understood, after swapping the positions of the first data line DL1, the third pixel circuit array 2c-3 electrically connected to it, the first pixel circuit array 2c-1 adjacent to the first data line DL1, and the data line DL electrically connected to the first pixel circuit array 2c-1, the shape, size, etc., of the first light-emitting element 3a electrically connected to the first pixel circuit array 2c-1 can be adaptively adjusted.

[0116] The above installation configuration will be schematically explained below based on the drawings.

[0117] Alternatively, between two adjacent pixel circuit arrays 2c for electrically connecting to the second light-emitting element 3b, two first pixel circuit arrays 2c-1 and two second pixel circuit arrays 2c-2 are provided.

[0118] Figure 9 shows six pixel circuit arrays 2c, which are sequentially arranged along a first direction X: the second pixel circuit array 2c-2, the third pixel circuit array 2c-3, the first pixel circuit array 2c-1, the second pixel circuit array 2c-2, the first pixel circuit array 2c-1, and the second pixel circuit array 2c-2.

[0119] For example, Figure 12 shows a configuration in which the positions of the third pixel circuit array 2c-3, the first data line DL1 electrically connected to it, the first pixel circuit array 2c-1 adjacent to the first data line DL1, and the data line DL electrically connected to the first pixel circuit array 2c-1 are swapped. In Figure 12, the first pixel circuit array 2c-1, the third pixel circuit array 2c-3, the second pixel circuit array 2c-2, the first pixel circuit array 2c-1, and the second pixel circuit array 2c-2 are arranged sequentially along the first direction X.

[0120] Naturally, the embodiments of this disclosure may also involve swapping the positions of the third pixel circuit array 2c-3, the first data line DL1 electrically connected to it, another first pixel circuit array 2c-1, and the data line DL electrically connected to this first pixel circuit array 2c-1. Here, Figure 13 shows a configuration in which the positions of the third pixel circuit array 2c-3, the first data line DL1 electrically connected to it, the first pixel circuit array 2c-1 adjacent to this first data line DL1, and the data line DL electrically connected to this first pixel circuit array 2c-1 are swapped. In Figure 13, the first pixel circuit array 2c-1, the second pixel circuit array 2c-2, the first pixel circuit array 2c-1, the third pixel circuit array 2c-3, and the second pixel circuit array 2c-2 are arranged sequentially along a first direction X.

[0121] To ensure clarity, Figures 12 and 13 illustrate an example where different data lines DL are located to the right of the pixel circuit array 2c to which they are electrically connected. Figures 14 and 15 show an example where different data lines DL are located to the left of the pixel circuit array 2c to which they are electrically connected. In Figure 14, the second pixel circuit array 2c-2, the third pixel circuit array 2c-3, the first pixel circuit array 2c-1, the second pixel circuit array 2c-2, the first pixel circuit array 2c-1, and the second pixel circuit array 2c-2 are arranged sequentially along the first direction X. In Figure 15, the first pixel circuit array 2c-1, the second pixel circuit array 2c-2, the third pixel circuit array 2c-3, the first pixel circuit array 2c-1, and the second pixel circuit array 2c-2 are arranged sequentially along the first direction X.

[0122] Alternatively, a first pixel circuit array 2c-1 and a second pixel circuit array 2c-2 are provided between two adjacent pixel circuit arrays 2c for electrical connection with the second light-emitting element 3b.

[0123] Figure 16 shows six pixel circuit arrays 2c, arranged sequentially along a first direction X: the first pixel circuit array 2c-1, the third pixel circuit array 2c-3, the second pixel circuit array 2c-2, the first pixel circuit array 2c-1, the third pixel circuit array 2c-3, and the second pixel circuit array 2c-2. However, the different data lines DL are all located to the right of the pixel circuit arrays 2c to which they are electrically connected.

[0124] As can be understood, the positional relationship between the first light-emitting element 3a, which is electrically connected to the first pixel circuit array 2c-1 adjacent to the third pixel circuit array 2c-3, and the first data line DL1 can vary and can be selected according to actual requirements. Here, the first light-emitting element 3a, which is electrically connected to the first pixel circuit array 2c-1 adjacent to the third pixel circuit array 2c-3, is defined as the target light-emitting element 3d.

[0125] In some embodiments, as shown in Figures 12 to 15, the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located does not overlap with the orthogonal projection of the target illumination device 3d onto the display substrate 100. The plane on which the display substrate 100 is located is parallel to the base 1. That is, in the direction perpendicular to the base 1, the first data line DL1 and the target light-emitting element 3d are offset from each other, and there is no overlap.

[0126] Here, the light-emitting element 3 includes an anode 31. The fact that the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located and the orthogonal projection of the target light-emitting element 3d onto the plane on which the display substrate 100 is located do not overlap means, for example, that the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located and the orthogonal projection of the anode 31 of the target light-emitting element 3d onto the plane on which the display substrate 100 is located do not overlap.

[0127] This makes it possible to further reduce the parasitic capacitance between the first data line DL1 and the anode 31 of the target light-emitting element 3d, that is, the parasitic capacitance between the first data line DL1 and the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1. This further reduces the influence of the data signal transmitted by the first data line DL1 on the potential of the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1, thereby improving or eliminating vertical line defects in the display board 100 and enhancing the display effect of the display board 100.

[0128] In this case, there are various arrangements between the target light-emitting element 3d and the first data line DL1, and these can be selected according to the actual needs.

[0129] For example, as shown in Figures 12 and 13, the portion of the first data line DL1 adjacent to the target light-emitting element 3d is linear. Here, the portion of the first data line DL1 adjacent to the target light-emitting element 3d refers to the portion of the first data line DL1 that overlaps with the anode 31 of the target light-emitting element 3d in an orthogonal projection onto a plane perpendicular to the first direction X.

[0130] In other words, in the wiring process, there is sufficient space to position the target light-emitting element 3d on the side of the first data line DL1 that is close to the third pixel circuit array 2c-3 which is electrically connected to it.

[0131] This improves the regularity of the topography of the first data line DL1 and reduces the difficulty of forming the first data line DL1.

[0132] For example, as shown in Figure 14, the portion of the first data line DL1 adjacent to the target light-emitting element 3d is wound along at least a part of the edge of the target light-emitting element 3d. That is, in the path along which the first data line DL1 extends, the portion of the first data line DL1 adjacent to the target light-emitting element 3d bypasses at least a part of the edge of the target light-emitting element 3d.

[0133] For example, the topography of the portion of the first data line DL1 adjacent to the target light-emitting element 3d is the same as or similar to the topography of the edge portion of the light-emitting element 3d that is close to the first data line DL1. In a direction perpendicular to the plane on which the display substrate 100 is located, there is a pitch between the portion of the first data line DL1 adjacent to the target light-emitting element 3d and the edge portion of the light-emitting element 3d that is close to the first data line DL1, and the pitch at different positions may be equal or approximately equal.

[0134] In the configuration shown in Figure 14, in the first direction X, the first data line DL1 is located to the left of the target light-emitting element 3d, and a portion of the edge of the target light-emitting element 3d located on the left side protrudes to the left. Correspondingly, the portion of the first data line DL1 adjacent to the target light-emitting element 3d protrudes to the left. Naturally, if the first data line DL1 is located to the right of the target light-emitting element 3d, and a portion of the edge of the target light-emitting element 3d located on the right side protrudes to the right side, the portion of the first data line DL1 adjacent to the target light-emitting element 3d protrudes to the right. In other words, the first data line DL1 can be rerouted from the target light-emitting element 3d by winding during the wiring process.

[0135] This makes it possible to avoid the target light-emitting element 3d. Parasitic capacitance between the first data line DL1 and the anode 31 of the target light-emitting element 3d can be reduced.

[0136] In some other embodiments, as shown in Figure 17, the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located and the orthogonal projection of at least one target light-emitting element 3d onto the plane on which the display substrate 100 is located partially overlap. That is, the first data line DL1 and the target light-emitting element 3d overlap in a direction perpendicular to the base 1.

[0137] Here, the partial overlap of the orthogonal projection of the first data line DL1 onto the plane where the display substrate 100 is located and the orthogonal projection of the target light-emitting element 3d onto the plane where the display substrate 100 is located includes, but is not limited to, the partial overlap of the orthogonal projection of the first data line DL1 onto the plane where the display substrate 100 is located and the orthogonal projection of the anode 31 of the target light-emitting element 3d onto the plane where this display substrate 100 is located.

[0138] Furthermore, as shown in Figure 17, the display substrate 100 further includes a shield pattern 4 located between the first data line DL1 and the target light-emitting element 3d in a direction perpendicular to the plane on which the display substrate 100 is located.

[0139] For example, the material of the shield pattern 4 is a conductive material, including but not limited to metallic materials. An insulating layer (also called a flat layer) is provided between the shield pattern 4 and the first data line DL1, and an insulating layer (also called a flat layer) is provided between the shield pattern 4 and the target light-emitting element 3d.

[0140] The shield pattern 4 described above is configured to access constant voltage electrical signals. That is, the shield pattern 4 has electrical signals whose voltage does not change. The constant voltage electrical signals accessed by the shield pattern 4 include, but are not limited to, a first voltage signal, a first initial signal, a second initial signal, etc.

[0141] This allows the shield pattern 4 to shield the target light-emitting element 3d, thereby reducing or shielding the influence of the data signal transmitted by the first data line DL1 on the anode 31 of the target light-emitting element 3d, that is, the influence of the data signal transmitted by the first data line DL1 on the potential of the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1. This improves the stability of the potential of the fourth node N4, improves or eliminates vertical line defects in the display board 100, and enhances the display effect of the display board 100.

[0142] As shown in Figure 18, the shield pattern 4, the target light-emitting element 3d, and the first data line DL1 partially overlap in their orthogonal projection onto the plane on which the display substrate 100 is located. Note that in Figure 18, the anode 31 of the target light-emitting element 3d is shown as the target light-emitting element 3d.

[0143] In other words, the first data line DL1, the shield pattern 4, and the target light-emitting element 3d have overlapping portions in a direction perpendicular to the base 1. The size of the area of ​​these three overlapping portions depends on the actual wiring configuration and is not limited to this disclosure.

[0144] As a result, the shield pattern 4 can separate the overlapping portion between the target light-emitting element 3d and the first data line DL1, ensuring a good shielding effect on the target light-emitting element 3d by the shield pattern 4, effectively reducing the influence of the data signal transmitted on the first data line DL1 on the anode 31 of the target light-emitting element 3d, and effectively improving the stability of the dot at the fourth node N4.

[0145] In some examples, the first color light is red light, the second color light is blue light, and the third color light is green light. Here, the target light-emitting element 3d that emits red light constitutes a red target light-emitting element R, and the target light-emitting element 3d that emits blue light constitutes a blue target light-emitting element B, and the area of ​​the red target light-emitting element R is smaller than that of the blue target light-emitting element B.

[0146] Here, as shown in Figure 17, a shield pattern 4 is positioned between the blue symmetric light-emitting element B and the first data line DL1, perpendicular to the plane on which the display substrate 100 is located. The orthogonal projections of the shield pattern 4, the blue symmetric light-emitting element B, and the first data line DL1 onto the plane on which the display substrate 100 is located partially overlap.

[0147] In other words, because the area of ​​the blue target light-emitting element B is large, the blue target light-emitting element B extends above the first data line DL1, and the orthogonal projection of the blue target light-emitting element B and the first data line DL1 partially overlaps on the plane on which the display substrate 100 is located. Also, because the area of ​​the red target light-emitting element R is small, there is a pitch between the orthogonal projection of the red target light-emitting element R onto the plane on which the display substrate 100 is located and the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located.

[0148] The number of shield patterns 4 may be, for example, multiple, and these multiple shield patterns 4 and the target light-emitting element 3d may be arranged in a one-to-one correspondence.

[0149] The multiple shield patterns 4 described above are provided, for example, in the same layer.

[0150] In this disclosure, "same layer" means a layer configuration formed by forming a film layer for a specific pattern using the same film deposition process, and then forming it in a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns within the formed layer configuration may be continuous or discontinuous, and these specific patterns may be at different heights and have different thicknesses. This allows multiple shield patterns 4 to be formed simultaneously, reducing the difficulty of manufacturing between display substrates 100.

[0151] For example, at least two of the above-mentioned multiple shield patterns 4 are connected and form an integrated structure. These at least two shield patterns 4 are, for example, at least two shield patterns 4 adjacent to a first direction X, or at least two shield patterns 4 adjacent to a second direction Y. Naturally, among these at least two shield patterns 4, at least two shield patterns 4 adjacent to the first direction X and at least two shield patterns 4 adjacent to the second direction Y may be included simultaneously.

[0152] For example, the multiple shielding patterns 4 included in the display board 100 have an integrated structure. In this case, as shown in Figure 19, these multiple shielding patterns 4 form a grid.

[0153] Here, "integrated structure" means that at least two connected shield patterns 4 are continuous and not separated. This allows for a larger dimension of the at least two integrated shield patterns 4, and reduces the difficulty of etching the film layer on which the shield patterns 4 are located.

[0154] In some examples, as shown in Figure 18, the display substrate 100 includes a first conductive layer FL1 and a second conductive layer FL2. In a direction perpendicular to the base 1, the first conductive layer FL1 is located between a plurality of pixel circuits 2 and a plurality of light-emitting elements 3, and the second conductive layer FL2 is located between this first conductive layer FL1 and the plurality of light-emitting elements 3.

[0155] The display board 100 further includes a plurality of first voltage signal lines VL1, each of which is electrically connected to a plurality of pixel circuit arrays 2c. For example, the plurality of first voltage signal lines VL1 and the plurality of pixel circuit arrays 2c are arranged in a one-to-one correspondence, and the first voltage signal lines VL1 are electrically connected to the first voltage signal terminal VDD of each pixel circuit 2 in the corresponding pixel circuit array 2c.

[0156] For example, the first conductive layer FL1 includes the plurality of data lines DL and the plurality of first voltage signal lines VL1.

[0157] By arranging the data line DL and the first voltage signal line VL1 on the first conductive layer FL1, the wiring space is increased.

[0158] The second conductive layer FL2 includes the shielding pattern 4. For example, all of the shielding patterns 4 are located on the second conductive layer FL2. Here, the shielding pattern 4 is electrically connected to the first voltage signal line VL1 and receives the first voltage signal.

[0159] The first voltage signal line VL1 electrically connected to the shield pattern 4 is, for example, the first voltage signal line VL1 electrically connected to the third pixel circuit row 2c-3. Multiple shield patterns 4 located in the same row are electrically connected to, for example, the same first voltage signal line VL1.

[0160] By placing a second conductive layer FL2 between the first conductive layer FL1 and the light-emitting element 3, and by placing a shielding pattern 4 on the second conductive layer FL2, it is advantageous to increase the wiring space and reduce the difficulty of wiring.

[0161] Naturally, if the data line DL and the first voltage signal line VL1 are located on different layers, the shield pattern 4 may be placed on the same layer as the first voltage signal line VL1.

[0162] In some embodiments, referring to Figures 3 and 11, at least one of the multiple arrays of light-emitting elements 3c in which the multiple light-emitting elements 3 of the display substrate 100 are arranged includes a plurality of first light-emitting elements 3a located in the first display area A1 and a plurality of second light-emitting elements 3b located in the second display area A2.

[0163] In the at least one light-emitting element array 3c, a data line DL is electrically connected to a pixel circuit array 2c electrically connected to a plurality of first light-emitting elements 3a in each light-emitting element array 3c, and a data line DL is electrically connected to a pixel circuit array 2c electrically connected to a plurality of second light-emitting elements 3b in the light-emitting element array 3c. Here, the data line DL electrically connected to the pixel circuit array 2c electrically connected to a plurality of second light-emitting elements 3b in this light-emitting element array 3c is the first data line DL1.

[0164] For example, as shown in Figure 11, the display substrate 100 further includes a plurality of transfer lines 5 that extend in a first direction X and connect data lines DL that are electrically connected to a pixel circuit row 2c electrically connected to a plurality of first light-emitting elements 3a in each light-emitting element row 3c, and data lines DL that are electrically connected to a pixel circuit row 2c electrically connected to a plurality of second light-emitting elements 3b in the same light-emitting element row 3c. That is, in a second direction Y, data lines DL that are electrically connected to a pixel circuit row 2c electrically connected to a first light-emitting element 3a located below the second display area A2 are connected to data lines DL that are electrically connected to a pixel circuit row 2c electrically connected to a second light-emitting element 3b located to the left or right of the second display area A2.

[0165] This allows the same data signal to be received by the pixel circuit 2c electrically connected to multiple first light-emitting elements 3a and the pixel circuit 2c electrically connected to the second light-emitting elements 3b within the same light-emitting element array 3c, making it easy to control the light-emitting state of each light-emitting element 3 located in the same light-emitting element array 3c.

[0166] In some embodiments, as shown in Figures 12 to 17, the first light-emitting element 3a, which is electrically connected to the second pixel circuit array 2c-2 adjacent to the third pixel circuit array 2c-3, partially overlaps the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located.

[0167] This facilitates the uniform arrangement of different light-emitting elements 3.

[0168] In some embodiments, as shown in Figure 11, at least one third pixel circuit array 2c-3 and at least one fourth pixel circuit array 2c-4 are arranged on the side of the second display area A2 in the row direction (i.e., the first direction X).

[0169] For example, the plurality of third pixel circuit arrays 2c-3 and the plurality of fourth pixel circuit arrays 2c-4 included in the display board 100 may all be arranged on the same side (e.g., left or right) in the row direction of the second display area A2. Naturally, some of the third pixel circuit arrays 2c-3 may be located on one side of the opposing sides in the row direction of the second display area A2, while other portions of the third pixel circuit arrays 2c-3 may be located on the other side of the opposing sides in the row direction of the second display area A2. Some of the fourth pixel circuit arrays 2c-4 may be located on one side of the opposing sides in the row direction of the second display area A2, while other portions of the fourth pixel circuit arrays 2c-4 may be located on the other side of the opposing sides in the row direction of the second display area A2.

[0170] This improves the regularity of the arrangement of the pixel circuit 2, facilitating the electrical connection between the third pixel circuit array 2c-3 and the corresponding second light-emitting element 3b, and facilitating the electrical connection between the fourth pixel circuit array 2c-4 and the corresponding second light-emitting element 3b.

[0171] In some cases, as shown in Figure 11, of the third and fourth pixel circuit arrays 2c-3 and 2c-4 located on the same side of the second display area A2, the fourth pixel circuit array 2c-4 is closer to the second display area A2 than the third pixel circuit array 2c-3.

[0172] In other words, of the third pixel circuit array 2c-3 and the fourth pixel circuit array 2c-4 located on the same side of the second display area A2, each of the fourth pixel circuit arrays 2c-4 is located between the third pixel circuit array 2c-3, which is closest to the second display area A2, and the second display area A2, while each of the third pixel circuit arrays 2c-3 is located on the side of the fourth pixel circuit array 2c-4 that is away from the second display area A2.

[0173] For example, Figure 11 shows three third pixel circuit arrays 2c-3 and three fourth pixel circuit arrays 2c-4 located to the left of the second display area A2. These three third pixel circuit arrays 2c-3 are located on the side of the three fourth pixel circuit arrays 2c-4 that is away from the second display area A2, and the three fourth pixel circuit arrays 2c-4 are located between the three third pixel circuit arrays 2c-3 and the second display area A2.

[0174] This makes it possible to improve the low-gradation illumination level of the second display area A2.

[0175] In some embodiments, as shown in Figure 11, the display board 100 further includes a plurality of dummy pixel circuits 6. Some of the dummy pixel circuits 6 are located in the same row as the third pixel circuit row 2c-3, and some of the dummy pixel circuits 6 are located in the same row as the fourth pixel circuit row 2c-4.

[0176] The configuration of the dummy pixel circuit 6 is the same as that of the pixel circuit 2, but the dummy pixel circuit 6 is not for generating drive signals and is not electrically connected to the light-emitting element 3. The data signal lines electrically connected to the dummy pixel circuit 6 may be in a floating state or may access a constant voltage point signal (for example, a first voltage signal).

[0177] As shown in Figures 17 and 20, some embodiments of the present disclosure further provide a display substrate 100 in which the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located and the orthogonal projection of the target light-emitting element 3d onto the plane on which the display substrate 100 is located partially overlap. That is, the first data line DL1 and the target light-emitting element 3d overlap in a direction perpendicular to the base 1.

[0178] Here, the partial overlap of the orthogonal projection of the first data line DL1 onto the plane where the display substrate 100 is located and the orthogonal projection of the target light-emitting element 3d onto the plane where the display substrate 100 is located includes, but is not limited to, the partial overlap of the orthogonal projection of the first data line DL1 onto the plane where the display substrate 100 is located and the orthogonal projection of the anode 31 of the target light-emitting element 3d onto the plane where the display substrate 100 is located.

[0179] Furthermore, as shown in Figures 17 and 20, the display substrate 100 further includes a shield pattern 4 located between the first data line DL1 and the target light-emitting element 3d in a direction perpendicular to the plane on which the display substrate 100 is located.

[0180] For example, the material of the shield pattern 4 is a conductive material, including but not limited to metallic materials. An insulating layer (also called a flat layer) is provided between the shield pattern 4 and the first data line DL1, and an insulating layer (also called a flat layer) is provided between the shield pattern 4 and the target light-emitting element 3d.

[0181] The shield pattern 4 described above is configured to access constant voltage electrical signals. That is, the shield pattern 4 has electrical signals whose voltage does not change. The constant voltage electrical signals accessed by the shield pattern 4 include, but are not limited to, a first voltage signal, a first initial signal, a second initial signal, etc.

[0182] This allows the shield pattern 4 to shield the target light-emitting element 3d, thereby reducing or shielding the influence of the data signal transmitted by the first data line DL1 on the anode 31 of the target light-emitting element 3d, that is, the influence of the data signal transmitted by the first data line DL1 on the potential of the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1. This improves the stability of the potential of the fourth node N4, improves or eliminates vertical line defects in the display board 100, and enhances the display effect of the display board 100.

[0183] In some cases, as shown in Figure 20, the shield pattern 4, the target light-emitting element 3d, and the first data line DL1 partially overlap in their orthogonal projection onto the plane on which the display substrate 100 is located.

[0184] In other words, the first data line DL1, the shield pattern 4, and the target light-emitting element 3d have overlapping portions in a direction perpendicular to the base 1. The size of the area of ​​these three overlapping portions depends on the actual wiring configuration and is not limited to this disclosure.

[0185] As a result, the shield pattern 4 can separate the overlapping portion between the target light-emitting element 3d and the first data line DL1, ensuring a good shielding effect on the target light-emitting element 3d by the shield pattern 4, effectively reducing the influence of the data signal transmitted on the first data line DL1 on the anode 31 of the target light-emitting element 3d, and effectively improving the stability of the dot at the fourth node N4.

[0186] In some examples, the first color light is red light, the second color light is blue light, and the third color light is green light. Here, the target light-emitting element 3d that emits red light constitutes a red target light-emitting element R, and the target light-emitting element 3d that emits blue light constitutes a blue target light-emitting element B, and the area of ​​the red target light-emitting element R is smaller than that of the blue target light-emitting element B.

[0187] Here, as shown in Figure 20, the shield pattern 4 is located between the red symmetric light-emitting element R and the first data line DL1 in a direction perpendicular to the plane on which the display substrate 100 is located. The orthogonal projections of the shield pattern 4, the red symmetric light-emitting element R, and the first data line DL1 onto the plane on which the display substrate 100 is located partially overlap.

[0188] In other words, the area of ​​the red symmetric light-emitting element R is small, the red symmetric light-emitting element R can extend above the first data line DL1, and the orthogonal projection of the red symmetric light-emitting element R and the first data line DL1 onto the plane on which the display substrate 100 is located partially overlaps.

[0189] Naturally, because the area of ​​the blue symmetric light-emitting element B is large, the blue symmetric light-emitting element B can extend above the first data line DL1, and the orthogonal projection of the blue symmetric light-emitting element B and the first data line DL1 onto the plane on which the display substrate 100 is located partially overlaps.

[0190] The number of shield patterns 4 may be, for example, multiple, and these multiple shield patterns 4 and the target light-emitting element 3d may be arranged in a one-to-one correspondence.

[0191] The multiple shield patterns 4 described above are provided, for example, in the same layer.

[0192] In this disclosure, "same layer" means a layer configuration formed by forming a film layer for a specific pattern using the same film deposition process, and then forming it in a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns within the formed layer configuration may be continuous or discontinuous, and these specific patterns may be at different heights and have different thicknesses. This allows multiple shield patterns 4 to be formed simultaneously, reducing the difficulty of manufacturing between display substrates 100.

[0193] For example, at least two of the above-mentioned multiple shield patterns 4 are connected and form an integrated structure. These at least two shield patterns 4 are, for example, at least two shield patterns 4 adjacent to a first direction X, or at least two shield patterns 4 adjacent to a second direction Y. Naturally, among these at least two shield patterns 4, at least two shield patterns 4 adjacent to the first direction X and at least two shield patterns 4 adjacent to the second direction Y may be included simultaneously.

[0194] For example, the multiple shielding patterns 4 included in the display board 100 have an integrated structure. In this case, these multiple shielding patterns 4 form a grid.

[0195] Here, "integrated structure" means that at least two connected shield patterns 4 are continuous and not separated. This allows for a larger dimension of the at least two integrated shield patterns 4, and reduces the difficulty of etching the film layer on which the shield patterns 4 are located.

[0196] In some examples, as shown in Figure 18, the display substrate 100 includes a first conductive layer FL1 and a second conductive layer FL2. In a direction perpendicular to the base 1, the first conductive layer FL1 is located between a plurality of pixel circuits 2 and a plurality of light-emitting elements 3, and the second conductive layer FL2 is located between this first conductive layer FL1 and the plurality of light-emitting elements 3.

[0197] The display board 100 further includes a plurality of first voltage signal lines VL1, each of which is electrically connected to a plurality of pixel circuit arrays 2c. For example, the plurality of first voltage signal lines VL1 and the plurality of pixel circuit arrays 2c are arranged in a one-to-one correspondence, and the first voltage signal lines VL1 are electrically connected to the first voltage signal terminal VDD of each pixel circuit 2 in the corresponding pixel circuit array 2c.

[0198] For example, the first conductive layer FL1 includes the plurality of data lines DL and the plurality of first voltage signal lines VL1.

[0199] By arranging the data line DL and the first voltage signal line VL1 on the first conductive layer FL1, the wiring space is increased.

[0200] The second conductive layer FL2 includes the shielding pattern 4. For example, all of the shielding patterns 4 are located on the second conductive layer FL2. Here, the shielding pattern 4 is electrically connected to the first voltage signal line VL1 and receives the first voltage signal.

[0201] The first voltage signal line VL1 electrically connected to the shield pattern 4 is, for example, the first voltage signal line VL1 electrically connected to the third pixel circuit row 2c-3. Multiple shield patterns 4 located in the same row are electrically connected to, for example, the same first voltage signal line VL1.

[0202] By placing a second conductive layer FL2 between the first conductive layer FL1 and the light-emitting element 3, and by placing a shielding pattern 4 on the second conductive layer FL2, it is advantageous to increase the wiring space and reduce the difficulty of wiring.

[0203] Naturally, if the data line DL and the first voltage signal line VL1 are located on different layers, the shield pattern 4 may be placed on the same layer as the first voltage signal line VL1.

[0204] In the example above, as shown in Figure 20, the first data line DL1 is located, for example, between the third pixel circuit array 2c-3 and the first pixel circuit array 2c-1. That is, the first data line DL1 is located on the side of the third pixel circuit array 2c-3 that is closer to the first pixel circuit array 2c-1.

[0205] In some embodiments, referring to Figures 3, 6, and 11, of the multiple arrays of light-emitting elements 3c in which the multiple light-emitting elements 3 of the display substrate 100 are arranged, at least one array of light-emitting elements 3c includes a plurality of first light-emitting elements 3a located in the first display area A1 and a plurality of second light-emitting elements 3b located in the second display area A2.

[0206] In the at least one light-emitting element array 3c, a data line DL is electrically connected to a pixel circuit array 2c electrically connected to a plurality of first light-emitting elements 3a in each light-emitting element array 3c, and a data line DL is electrically connected to a pixel circuit array 2c electrically connected to a plurality of second light-emitting elements 3b in the light-emitting element array 3c. Here, the data line DL electrically connected to the pixel circuit array 2c electrically connected to a plurality of second light-emitting elements 3b in this light-emitting element array 3c is the first data line DL1.

[0207] For example, as shown in Figures 6 and 11, the display substrate 100 further includes a plurality of transfer lines 5 that extend in a first direction and connect data lines DL that are electrically connected to pixel circuit arrays 2c electrically connected to a plurality of first light-emitting elements 3a in each light-emitting element array 3c, and data lines DL that are electrically connected to pixel circuit arrays 2c electrically connected to a plurality of second light-emitting elements 3b in the same light-emitting element array 3c. That is, in the second direction Y, data lines DL that are electrically connected to pixel circuit arrays 2c electrically connected to first light-emitting elements 3a located below the second display area A2 are connected to data lines DL that are electrically connected to pixel circuit arrays 2c electrically connected to second light-emitting elements 3b located to the left or right of the second display area A2.

[0208] As a result, within the same light-emitting element array 3c, the same data signal can be received by the pixel circuit array 2c electrically connected to multiple first light-emitting elements 3a and the pixel circuit array 2c electrically connected to the second light-emitting element 3b, making it easy to control the light-emitting state of the light-emitting elements 3 located in the same light-emitting element array 3c.

[0209] In some embodiments, as shown in Figures 6 and 11, at least one third pixel circuit array 2c-3 and at least one fourth pixel circuit array 2c-4 are arranged on one side in the row direction (i.e., the first direction X) of the second display area A2.

[0210] For example, the plurality of third pixel circuit arrays 2c-3 and the plurality of fourth pixel circuit arrays 2c-4 included in the display board 100 may all be arranged on the same side (e.g., left or right) in the row direction of the second display area A2. Naturally, some of the third pixel circuit arrays 2c-3 may be located on one side of the opposing sides in the row direction of the second display area A2, while other portions of the third pixel circuit arrays 2c-3 may be located on the other side of the opposing sides in the row direction of the second display area A2. Some of the fourth pixel circuit arrays 2c-4 may be located on one side of the opposing sides in the row direction of the second display area A2, while other portions of the fourth pixel circuit arrays 2c-4 may be located on the other side of the opposing sides in the row direction of the second display area A2.

[0211] This improves the regularity of the arrangement of the pixel circuit 2, facilitating the electrical connection between the third pixel circuit array 2c-3 and the corresponding second light-emitting element 3b, and facilitating the electrical connection between the fourth pixel circuit array 2c-4 and the corresponding second light-emitting element 3b.

[0212] In some examples, as shown in Figures 6 and 11, of the third and fourth pixel circuit arrays 2c-3 and 2c-4 located on the same side of the second display area A2, the fourth pixel circuit array 2c-4 is closer to the second display area A2 than the third pixel circuit array 2c-3.

[0213] In other words, of the third pixel circuit array 2c-3 and the fourth pixel circuit array 2c-4 located on the same side of the second display area A2, each of the fourth pixel circuit arrays 2c-4 is located between the third pixel circuit array 2c-3, which is closest to the second display area A2, and the second display area A2, while each of the third pixel circuit arrays 2c-3 is located on the side of the fourth pixel circuit array 2c-4 that is away from the second display area A2.

[0214] For example, Figures 6 and 11 show three third pixel circuit arrays 2c-3 and three fourth pixel circuit arrays 2c-4 located to the left of the second display area A2. These three third pixel circuit arrays 2c-3 are located on the side of the three fourth pixel circuit arrays 2c-4 that is away from the second display area A2, and the three fourth pixel circuit arrays 2c-4 are located between the three third pixel circuit arrays 2c-3 and the second display area A2.

[0215] This makes it possible to improve the low-gradation illumination level of the second display area A2.

[0216] As shown in Figures 14 and 21, some embodiments of the present disclosure further provide a display substrate 100 in which the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located does not overlap with the orthogonal projection of the target light-emitting element 3d onto the plane on which the display substrate 100 is located. The plane on which the display substrate 100 is located is the plane on which the display substrate 100 is located. That is, in the direction perpendicular to the base 1, the first data line DL1 and the target light-emitting element 3d are offset and there is no overlap.

[0217] Here, the light-emitting element 3 includes an anode 31. The fact that the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located and the orthogonal projection of the target light-emitting element 3d onto the plane on which the display substrate 100 is located do not overlap means, for example, that the orthogonal projection of the first data line DL1 onto the plane on which the display substrate 100 is located and the orthogonal projection of the anode 31 of the target light-emitting element 3d onto the plane on which the display substrate 100 is located do not overlap.

[0218] This reduces the parasitic capacitance between the first data line DL1 and the anode 31 of the target light-emitting element 3d, that is, the parasitic capacitance between the first data line DL1 and the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1. Furthermore, it reduces the influence of the data signal transmitted by the first data line DL1 on the potential of the fourth node N4 of the pixel circuit 2 in the adjacent first pixel circuit array 2c-1, thereby improving or eliminating vertical line defects in the display board 100 and enhancing the display effect of the display board 100.

[0219] In this case, there are various arrangements between the target light-emitting element 3d and the first data line DL1, and these can be selected according to the actual needs.

[0220] For example, as shown in Figures 12 and 13, the portion of the first data line DL1 adjacent to the target light-emitting element 3d is linear. Here, the portion of the first data line DL1 adjacent to the target light-emitting element 3d refers to the portion of the first data line DL1 that overlaps with the anode 31 of the target light-emitting element 3d in an orthogonal projection onto a plane perpendicular to the first direction X.

[0221] In other words, in the wiring process, there is sufficient space to position the target light-emitting element 3d on the side of the first data line DL1 that is close to the third pixel circuit array 2c-3 which is electrically connected to it.

[0222] This improves the regularity of the topography of the first data line DL1 and reduces the difficulty of forming the first data line DL1.

[0223] For example, as shown in Figures 14 and 21, the portion of the first data line DL1 adjacent to the target light-emitting element 3d is wound along at least a part of the edge of the target light-emitting element 3d. That is, in the path along which the first data line DL1 extends, the portion of the first data line DL1 adjacent to the target light-emitting element 3d bypasses at least a part of the edge of the target light-emitting element 3d.

[0224] For example, the topography of the portion of the first data line DL1 adjacent to the target light-emitting element 3d is the same as or similar to the topography of the edge portion of the light-emitting element 3d that is close to the first data line DL1. In a direction perpendicular to the plane on which the display substrate 100 is located, there is a pitch between the portion of the first data line DL1 adjacent to the target light-emitting element 3d and the edge portion of the light-emitting element 3d that is close to the first data line DL1, and the pitch at different positions may be equal or approximately equal.

[0225] In the configuration shown in Figure 21, in the first direction X, the first data line DL1 is located to the right of the target light-emitting element 3d, and a portion of the right edge of the target light-emitting element 3d protrudes to the right. Correspondingly, the portion of the first data line DL1 adjacent to the target light-emitting element 3d protrudes to the right. Naturally, as shown in Figure 14, if the first data line DL1 is located to the left of the target light-emitting element 3d, and a portion of the right edge of the target light-emitting element 3d protrudes to the left, the portion of the first data line DL1 adjacent to the target light-emitting element 3d protrudes to the left. In other words, during the wiring process, the first data line DL1 can be bypassed from the target light-emitting element 3d by winding.

[0226] This makes it possible to avoid the target light-emitting element 3d. Parasitic capacitance between the first data line DL1 and the anode 31 of the target light-emitting element 3d can be reduced.

[0227] In the example above, as shown in Figure 14, the first light-emitting element 3a, which is electrically connected to the second pixel circuit row 2c-2 adjacent to the third pixel circuit row 2c-3, partially overlaps the orthogonal projection of the first data line DL1 onto the plane on which the display board 100 is located.

[0228] Naturally, as shown in Figure 21, the orthogonal projection of the first light-emitting element 3a, which is electrically connected to the second pixel circuit array 2c-2 adjacent to the third pixel circuit array 2c-3, onto the plane where the display substrate 100 is located, and the orthogonal projection of the first data line DL1 onto the plane where the display substrate 100 is located do not have to overlap.

[0229] In some embodiments, referring to Figures 3, 6, and 11, of the multiple arrays of light-emitting elements 3c in which the multiple light-emitting elements 3 of the display substrate 100 are arranged, at least one array of light-emitting elements 3c includes a plurality of first light-emitting elements 3a located in the first display area A1 and a plurality of second light-emitting elements 3b located in the second display area A2.

[0230] In the at least one light-emitting element array 3c, data lines DL are electrically connected to a pixel circuit array 2c electrically connected to a plurality of first light-emitting elements 3a in each light-emitting element array 3c, and data lines DL are electrically connected to a pixel circuit array 2c electrically connected to a plurality of second light-emitting elements 3b in the light-emitting element array 3c.

[0231] This makes it easy to control the light emission state of the light-emitting elements 3 located in the same light-emitting element array 3c.

[0232] For example, as shown in Figures 6 and 11, the display substrate 100 further includes a plurality of transfer lines 5 that extend in a first direction and connect data lines DL that are electrically connected to pixel circuit arrays 2c electrically connected to a plurality of first light-emitting elements 3a of each light-emitting element array 3c, and data lines DL that are electrically connected to pixel circuit arrays 2c electrically connected to a plurality of second light-emitting elements 3b in the light-emitting element array 3c.

[0233] In some embodiments, as shown in Figures 6 and 11, at least one third pixel circuit array 2c-3 and at least one fourth pixel circuit array 2c-4 are arranged on one side in the row direction (i.e., the first direction X) of the second display area A2.

[0234] For example, the plurality of third pixel circuit arrays 2c-3 and the plurality of fourth pixel circuit arrays 2c-4 included in the display board 100 may all be arranged on the same side (e.g., left or right) in the row direction of the second display area A2. Naturally, some of the third pixel circuit arrays 2c-3 may be located on one side of the opposing sides in the row direction of the second display area A2, while other portions of the third pixel circuit arrays 2c-3 may be located on the other side of the opposing sides in the row direction of the second display area A2. Some of the fourth pixel circuit arrays 2c-4 may be located on one side of the opposing sides in the row direction of the second display area A2, while other portions of the fourth pixel circuit arrays 2c-4 may be located on the other side of the opposing sides in the row direction of the second display area A2.

[0235] This improves the regularity of the arrangement of the pixel circuit 2, facilitating the electrical connection between the third pixel circuit array 2c-3 and the corresponding second light-emitting element 3b, and facilitating the electrical connection between the fourth pixel circuit array 2c-4 and the corresponding second light-emitting element 3b.

[0236] In some examples, as shown in Figures 6 and 11, of the third and fourth pixel circuit arrays 2c-3 and 2c-4 located on the same side of the second display area A2, the fourth pixel circuit array 2c-4 is closer to the second display area A2 than the third pixel circuit array 2c-3.

[0237] In other words, of the third pixel circuit array 2c-3 and the fourth pixel circuit array 2c-4 located on the same side of the second display area A2, each of the fourth pixel circuit arrays 2c-4 is located between the third pixel circuit array 2c-3, which is closest to the second display area A2, and the second display area A2, while each of the third pixel circuit arrays 2c-3 is located on the side of the fourth pixel circuit array 2c-4 that is away from the second display area A2.

[0238] For example, Figures 6 and 11 show three third pixel circuit arrays 2c-3 and three fourth pixel circuit arrays 2c-4 located to the left of the second display area A2. These three third pixel circuit arrays 2c-3 are located on the side of the three fourth pixel circuit arrays 2c-4 that is away from the second display area A2, and the three fourth pixel circuit arrays 2c-4 are located between the three third pixel circuit arrays 2c-3 and the second display area A2.

[0239] This makes it possible to improve the low-gradation illumination level of the second display area A2.

[0240] The above are merely specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto. Any modifications or substitutions that a person skilled in the art could conceive of within the scope of the technology disclosed herein are included within the scope of the present disclosure. Accordingly, the scope of the present disclosure is subject to the claims.

Claims

1. A display board having a first display area and a second display area, The first display area is located on at least one side of the second display area, and the display board is A plurality of light-emitting elements, including a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area, A plurality of pixel circuits located in the first display area, each electrically connected to the plurality of light-emitting elements, and arranged in a plurality of pixel circuit rows, wherein the plurality of pixel circuit rows include a plurality of first pixel circuit rows and a plurality of second pixel circuit rows electrically connected to the plurality of first light-emitting elements, and a plurality of third pixel circuit rows and a plurality of fourth pixel circuit rows electrically connected to the plurality of second light-emitting elements, wherein the plurality of first pixel circuit rows and the plurality of second pixel circuit rows are arranged alternately in the row direction, and at least one third pixel circuit row among the plurality of third pixel circuit rows or at least one fourth pixel circuit row among the plurality of fourth pixel circuit rows is located between adjacent first pixel circuit rows and second pixel circuit rows, the first pixel circuit row or the third pixel circuit row is configured to drive a corresponding light-emitting element to emit a first color light and a second color light, and the plurality of pixel circuits are configured to drive a corresponding light-emitting element to emit a third color light. The first display area includes a plurality of data lines located in the first display area and electrically connected to each of the plurality of pixel circuit rows, The plurality of data lines include a first data line electrically connected to the third pixel circuit array, and the first data line is located between the third pixel circuit array and the second pixel circuit array on the display board.

2. The first light-emitting element electrically connected to the first pixel circuit array adjacent to the third pixel circuit array constitutes the target light-emitting element, The display board according to claim 1, wherein the orthogonal projection of the first data line onto the plane on which the display board is located and the orthogonal projection of the target light-emitting element onto the plane on which the display board is located do not overlap.

3. The portion of the first data line adjacent to the target light-emitting element is linear, or The display substrate according to claim 2, wherein the portion of the first data line adjacent to the target light-emitting element is wound along at least a portion of the edge of the target light-emitting element.

4. The first light-emitting element electrically connected to the first pixel circuit array adjacent to the third pixel circuit array constitutes the target light-emitting element, The orthogonal projection of the first data line onto the plane where the display substrate is located and the orthogonal projection of the target light-emitting element onto the plane where the display substrate is located partially overlap, The display board according to claim 1, further comprising a shielding pattern located between the first data line and the target light-emitting element in a direction perpendicular to the plane on which the display board is located, wherein the shielding pattern is configured to access a constant voltage electrical signal.

5. The display substrate according to claim 4, wherein the shield pattern, the target light-emitting element, and the first data line partially overlap in orthogonal projection onto the plane on which the display substrate is located.

6. The first colored light is red light, the second colored light is blue light, and the third colored light is green light. The target light-emitting element that emits red light constitutes a red target light-emitting element, the target light-emitting element that emits blue light constitutes a blue target light-emitting element, and the area of ​​the red target light-emitting element is smaller than that of the blue target light-emitting element. The display substrate according to claim 4 or 5, wherein, in a direction perpendicular to the plane on which the display substrate is located, the shield pattern is located between the blue symmetric light-emitting element and the first data line, and the orthogonal projections of the shield pattern, the blue symmetric light-emitting element, and the first data line partially overlap onto the plane on which the display substrate is located.

7. The display board according to any one of claims 4 to 6, wherein at least two of the shield patterns are connected to form an integrated structure.

8. It further includes a plurality of first voltage signal lines located in the first display area and electrically connected to each of the plurality of pixel circuit rows, The aforementioned display board is A first conductive layer including the plurality of data lines and the plurality of first voltage signal lines, A display substrate according to any one of claims 4 to 7, comprising a second conductive layer located between the first conductive layer and the plurality of light-emitting elements, and including the shielding pattern which is electrically connected to at least one of the plurality of first voltage signal lines.

9. A display board according to any one of claims 1 to 8, wherein the orthogonal projection of a first light-emitting element electrically connected to a second pixel circuit array adjacent to the third pixel circuit array onto the plane on which the display board is located and the orthogonal projection of the first data lines onto the plane on which the display board is located partially overlap.

10. The plurality of light-emitting elements are arranged in a plurality of light-emitting element rows, and at least one light-emitting element row includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. A display substrate according to any one of claims 1 to 9, wherein data lines electrically connected to a pixel circuit array electrically connected to a plurality of first light-emitting elements in the light-emitting element array are connected to data lines electrically connected to a pixel circuit array electrically connected to a plurality of second light-emitting elements in the light-emitting element array.

11. On one side in the row direction of the second display area, at least one third pixel circuit array and at least one fourth pixel circuit array are arranged. The display board according to any one of claims 1 to 10, wherein the fourth pixel circuit array is closer to the second display area than the third pixel circuit array.

12. A display board having a first display area and a second display area, The first display area is located on at least one side of the second display area, and the display board is A plurality of light-emitting elements, including a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area, A plurality of pixel circuits located in the first display area, each electrically connected to the plurality of light-emitting elements, and arranged in a plurality of pixel circuit rows, wherein the plurality of pixel circuit rows include a plurality of first pixel circuit rows and a plurality of second pixel circuit rows electrically connected to the plurality of first light-emitting elements, and a plurality of third pixel circuit rows and a plurality of fourth pixel circuit rows electrically connected to the plurality of second light-emitting elements, wherein the plurality of first pixel circuit rows and the plurality of second pixel circuit rows are arranged alternately in the row direction, and at least one third pixel circuit row among the plurality of third pixel circuit rows or at least one fourth pixel circuit row among the plurality of fourth pixel circuit rows is located between adjacent first pixel circuit rows and second pixel circuit rows, the plurality of pixel circuits in the first pixel circuit row or the third pixel circuit row are configured to drive corresponding light-emitting elements to emit first color light and second color light, and the plurality of pixel circuits in the second pixel circuit row or the fourth pixel circuit row are configured to drive corresponding light-emitting elements to emit third color light, A plurality of data lines, including a first data line located in the first display area, electrically connected to each of the plurality of pixel circuit rows, and electrically connected to the third pixel circuit row, wherein a first light-emitting element electrically connected to the first pixel circuit row adjacent to the third pixel circuit row constitutes a target light-emitting element, and the orthogonal projection of the first data line onto the plane on which the display substrate is located and the orthogonal projection of the target light-emitting element onto the plane on which the display substrate is located partially overlap a plurality of data lines, A display board including a shield pattern located between the first data line and the target light-emitting element in a direction perpendicular to the plane on which the display board is located, and configured to access a constant voltage electrical signal.

13. The display substrate according to claim 12, wherein the shield pattern, the target light-emitting element, and the first data line partially overlap in orthogonal projection onto the plane on which the display substrate is located.

14. The first colored light is red light, the second colored light is blue light, and the third colored light is green light. The target light-emitting element that emits red light constitutes a red target light-emitting element, the target light-emitting element that emits blue light constitutes a blue target light-emitting element, and the area of ​​the red target light-emitting element is smaller than that of the blue target light-emitting element. The display substrate according to claim 12 or 13, wherein, in a direction perpendicular to the plane on which the display substrate is located, the shield pattern is located between the red target light-emitting element and the first data line, and the orthogonal projections of the shield pattern, the red target light-emitting element, and the first data line partially overlap onto the plane on which the display substrate is located.

15. The display board according to any one of claims 12 to 14, wherein at least two of the shield patterns are connected to form an integrated structure.

16. It further includes a plurality of first voltage signal lines located in the first display area and electrically connected to each of the plurality of pixel circuit rows, The aforementioned display board is A first conductive layer including the plurality of data lines and the plurality of first voltage signal lines, A display substrate according to any one of claims 12 to 15, comprising a second conductive layer located between the first conductive layer and the plurality of light-emitting elements, and including the shielding pattern which is electrically connected to at least one of the plurality of first voltage signal lines.

17. The display board according to any one of claims 12 to 16, wherein the first data line is located between the third pixel circuit array and the first pixel circuit array.

18. The plurality of light-emitting elements are arranged in a plurality of light-emitting element rows, and at least one light-emitting element row includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. A display substrate according to any one of claims 12 to 17, wherein data lines electrically connected to a pixel circuit array electrically connected to a plurality of first light-emitting elements in the light-emitting element array are connected to data lines electrically connected to a pixel circuit array electrically connected to a plurality of second light-emitting elements in the light-emitting element array.

19. On one side in the row direction of the second display area, at least one third pixel circuit array and at least one fourth pixel circuit array are arranged. The display board according to any one of claims 12 to 18, wherein the fourth pixel circuit array is closer to the second display area than the third pixel circuit array.

20. A display board having a first display area and a second display area, The first display area is located on at least one side of the second display area, and the display board is A plurality of light-emitting elements, including a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area, A plurality of pixel circuits arranged in a plurality of pixel circuit arrays, each electrically connected to the plurality of light-emitting elements, including a plurality of first pixel circuit arrays and a plurality of second pixel circuit arrays electrically connected to the plurality of first light-emitting elements, and a plurality of third pixel circuit arrays and a plurality of fourth pixel circuit arrays electrically connected to the plurality of second light-emitting elements, wherein the plurality of first pixel circuit arrays and the plurality of second pixel circuit arrays are arranged alternately in the row direction, at least one of the plurality of third pixel circuit arrays or at least one of the plurality of fourth pixel circuit arrays is located between adjacent first and second pixel circuit arrays, the first pixel circuit array or the third pixel circuit array is configured to drive a corresponding light-emitting element to emit a first color light and a second color light, and the second pixel circuit array or the fourth pixel circuit array is configured to drive a corresponding light-emitting element to emit a third color light, A plurality of data lines located in the first display area, each electrically connected to the plurality of pixel circuit rows, and including a first data line electrically connected to the third pixel circuit row, wherein a first light-emitting element electrically connected to the first pixel circuit row adjacent to the third pixel circuit row includes a plurality of data lines constituting the target light-emitting element, A display board in which the orthogonal projection of the first data line onto the plane on which the display board is located and the orthogonal projection of the target light-emitting element onto the plane on which the display board is located do not overlap.

21. The portion of the first data line adjacent to the target light-emitting element is linear, or The display substrate according to claim 20, wherein the portion of the first data line adjacent to the target light-emitting element is wound along at least a portion of the edge of the target light-emitting element.

22. The display board according to claim 20 or 21, wherein the orthogonal projection of the first light-emitting element, which is electrically connected to the second pixel circuit array adjacent to the third pixel circuit array, onto the plane on which the display board is located, and the orthogonal projection of the first data line onto the plane on which the display board is located, partially overlap.

23. The plurality of light-emitting elements are arranged in a plurality of light-emitting element rows, and at least one light-emitting element row includes a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area. A display substrate according to any one of claims 20 to 22, wherein data lines electrically connected to a pixel circuit array electrically connected to a plurality of first light-emitting elements in the light-emitting element array are connected to data lines electrically connected to a pixel circuit array electrically connected to a plurality of second light-emitting elements in the light-emitting element array.

24. On one side in the row direction of the second display area, at least one third pixel circuit array and at least one fourth pixel circuit array are arranged. The display board according to any one of claims 20 to 23, wherein the fourth pixel circuit array is closer to the second display area than the third pixel circuit array.

25. A display board according to any one of claims 1 to 11, any one of claims 12 to 19, or any one of claims 20 to 24, A display device comprising an optical element located on the non-light-emitting side of the display substrate, wherein at least a portion of the optical element is located in a second display area of ​​the display substrate.

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