High-speed multi-payload length error correction system and method
By converting syndrome to parity in BCH error correction codes, the decoder area is reduced, enhancing the efficiency and cost-effectiveness of error correction in complex memory systems.
JP2026517692APending Publication Date: 2026-06-02MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2024-04-10
- Publication Date
- 2026-06-02
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Figure 2026517692000001_ABST
Abstract
A system and method for error location and error correction includes receiving an input in a processor circuit. The processor circuit generates a set of syndrome coefficients based on the input. The processor circuit generates a parity vector for the input based on the set of syndrome coefficients. The processor circuit determines the number of errors present in the input. In response to determining the number of errors present in the input, the processor circuit corrects the number of errors.
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