Linear redriver with adjustable low-frequency and high-frequency zeros in the equalizer stage

Abstract

The equalizer stage circuit includes a first transistor and a second transistor arranged in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes a high-frequency section comprising a first terminal coupled to the emitter or source of the first transistor, a second terminal coupled to the emitter or source of the second transistor, and a first plurality of high-frequency RC time constant elements connected in parallel between the first and second terminals, and a low-frequency section comprising a first capacitor coupled to the first terminal, a second capacitor coupled to the second terminal, and a second plurality of low-frequency RC time constant elements connected between the first and second capacitors.

Description

Background Art

[0001]

[0001] (Cross - Reference to Related Applications) This application claims the benefit and priority of U.S. Patent Application No. 18 / 631,996, entitled "Linear Driver with Adjustable Low - Frequency Zero and High - Frequency Zero in Equalizer Stages", filed on April 10, 2024, which is hereby incorporated by reference in its entirety.

[0002]

[0002] When a signal travels through a cable or a circuit board, it loses strength due to various factors including resistance and capacitance. Signal attenuation can distort the signal and make it more difficult to read and process at the receiving end. A linear driver is a microchip that improves the signal integrity of high - speed interfaces (e.g., high - speed data links). Linear drivers are particularly useful for extending the signal reach by canceling out signal attenuation caused by factors such as cable length or circuit board defects. A linear driver typically includes a continuous - time linear equalizer (CTLE) for selectively boosting the high - frequency components of the signal that are most affected by signal attenuation. Unlike some other signal conditioners, a linear driver does not change the basic characteristics of the signal. Instead, a linear driver amplifies the attenuated components while leaving the original signal shape intact. Maintaining signal characteristics is particularly beneficial for high - speed interfaces that rely on specific signal characteristics for proper functioning.

[0003]

[0003] Despite the advancements made in the field of linear drivers, there is a need in the art to improve the signal quality provided by linear drivers.

Summary of the Invention

[0004]

[0004] This disclosure generally relates to electronic circuits and equalizers. More specifically, embodiments of the present invention provide equalizer stage circuits of linear redrivers capable of achieving variations in equalizer gain. Embodiments described herein are applicable to a wide range of linear redrivers and electronic devices.

[0005]

[0005] One general embodiment includes an equalizer stage circuit. The equalizer stage circuit includes a first transistor. The equalizer stage circuit also includes a second transistor, and the first and second transistors are arranged in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes a high-frequency section comprising a first terminal coupled to the emitter or source of the first transistor, a second terminal coupled to the emitter or source of the second transistor, and a first plurality of high-frequency RC time constant elements connected in parallel between the first and second terminals, and a low-frequency section comprising a first capacitor coupled to the first terminal, a second capacitor coupled to the second terminal, and a second plurality of low-frequency RC time constant elements connected between the first and second capacitors.

[0006]

[0006] Embodiments may include one or more of the following features. In some embodiments, each of the first plurality of high-frequency RC time constant elements is selectively coupled between a first terminal and a second terminal based on a first set of control signals. In some embodiments, the high-frequency portion is characterized by a first fluctuating impedance based on a first set of control signals. In some embodiments, the first fluctuating impedance determines the location of the high-frequency zeros of the transfer function.

[0007]

[0007] In some embodiments, each of the second plurality of low-frequency RC time constant elements is selectively coupled between the first capacitor and the second capacitor based on a second set of control signals. In some embodiments, the low-frequency portion is characterized by a second fluctuating impedance based on the second set of control signals. In some embodiments, the second fluctuating impedance determines the position of the low-frequency zeros of the transfer function.

[0008]

[0008] In some embodiments, each of the second plurality of low-frequency RC time constant elements includes a first resistor connected to the first capacitor, a second resistor connected to the second capacitor, a first access transistor connected between the first resistor and ground, and a second access transistor connected between the second resistor and ground. In some embodiments, the equalizer stage circuit further includes a control unit configured to apply a second set of control signals to the gates of the first access transistors and the second access transistors of the second plurality of low-frequency RC time constant elements.

[0009]

[0009] In some embodiments, the equalizer stage circuit further includes a second selectable path. The second selectable path includes a third terminal coupled to the collector or drain of the first transistor, a fourth terminal coupled to the collector or drain of the second transistor, and a third plurality of high-frequency RC time constant elements connected between the third terminal and the fourth terminal. In some embodiments, each of the third plurality of high-frequency RC time constant elements is selectively coupled between the third terminal and the fourth terminal based on a third set of control signals. In some embodiments, the second selectable path is characterized by a third fluctuating impedance based on a third set of control signals. In some embodiments, the third fluctuating impedance determines the position of the high-frequency poles of the transfer function.

[0010]

[0010] Another common embodiment includes a linear redriver coupled between a transmitter and a receiver. The linear redriver includes an input stage circuit coupled to the transmitter, an output stage circuit coupled to the receiver, and an equalizer stage circuit coupled between the input stage circuit and the output stage circuit. The equalizer stage circuit includes a first transistor. The equalizer stage circuit also includes a second transistor, and the first and second transistors are arranged in a differential configuration. The equalizer stage circuit also includes a first selectable path. The first selectable path includes a high-frequency section comprising a first terminal coupled to the emitter or source of a first transistor, a second terminal coupled to the emitter or source of a second transistor, a first plurality of high-frequency RC time constant elements connected in parallel between the first and second terminals, a first capacitor coupled to the first terminal, a second capacitor coupled to the second terminal, and a second plurality of low-frequency RC time constant elements connected between the first and second capacitors.

[0011]

[0011] The present disclosure achieves many advantages over the prior art. For example, embodiments of the present invention provide an improved fit of trace loss compared to conventional methods. Furthermore, embodiments of the present invention, which are described more fully herein, provide fine-tuning of the gain profile and allow for a degree of freedom to achieve a relatively wide gain range at a desired frequency or desired frequency band. These and other embodiments of the present disclosure, along with many of their advantages and features, are described in more detail below in conjunction with the text and corresponding figures. [Brief explanation of the drawing]

[0012] [Figure 1] An embodiment of the present invention shows an equalizer stage circuit having selectable paths to the source / emitter and drain / collector for high-frequency zero and low-frequency zero variations. [Figure 2A] Figure 1 shows the selectable source / emitter path 120 for high-frequency zero and low-frequency zero variations according to an embodiment of the present invention. [Figure 2B]This shows a single RC time constant element of the high-frequency zero section according to an embodiment of the present invention. [Figure 2C] This shows a single RC time constant element for the low-frequency zero section according to an embodiment of the present invention. [Figure 3] Figure 1 shows the selectable path 150 on the drain / collector side for variation of the high-frequency electrode according to an embodiment of the present invention. [Figure 4] This shows a simulation of equalizer gain versus frequency with fixed high-frequency and low-frequency zero fluctuations according to an embodiment of the present invention. [Figure 5] This shows a simulation of equalizer gain versus frequency with a varied high-frequency zero and a varied low-frequency zero according to an embodiment of the present invention. [Figure 6] This shows a redriver including an equalizer stage circuit according to an embodiment of the present invention. [Modes for carrying out the invention]

[0013]

[0020] This disclosure generally relates to electronic circuits and equalizers. More specifically, embodiments of the present invention provide equalizer stage circuits for linear redrivers capable of achieving variations in equalizer gain. Embodiments described herein are applicable to a wide range of linear redrivers and electronic devices.

[0014]

[0021] Linear redriver equalizers (sometimes called “equalizer stages”) are often used to compensate for high-frequency losses in printed circuit board (PCB) traces or insertion losses due to the skin effect in transmission lines. Equalizers are typically implemented using active devices such as bipolar junction transistors (BJTs) and complementary metal oxide semiconductor (CMOS) devices. Poles and zeros of the transfer function are generated as appropriate. Values ​​that make the numerator of the transfer function zero are called the “zeros” of the transfer function, and values ​​that make the denominator of the transfer function zero are called the “poles” of the transfer function. Zeros of the transfer function are typically generated to achieve a desired gain. High-frequency zeros are generated to compensate for high-frequency losses in the PCB. Low-frequency zeros can also be added to further improve the degree of control to match the low-frequency loss characteristics of the PCB. A common embodiment of generating zeros of the transfer function is by a path coupled to the source / emitter terminals of an active device (typically in a differential pair configuration). The path is characterized by selectable capacitance values ​​chosen from a range of capacitance values. As a result, the gain of the equalizer is changed accordingly.

[0015]

[0022] The inventors understand that by adding low-frequency zero variation in addition to high-frequency zero variation, it is possible to achieve variation in the gain of the equalizer in the low-frequency region, thereby achieving a better fit of the insertion loss profile of the input trace before redriver. Examples of these techniques are described below with reference to Figures 1 to 5. However, these examples are not intended to be limiting, and those skilled in the art will recognize many variations, modifications, and alternatives.

[0016]

[0023] FIG. 1 shows an equalizer stage circuit having selectable paths to a source / emitter and a drain / collector for high-frequency zero and low-frequency zero variations, according to an embodiment of the present invention. In the example shown in FIG. 1, the equalizer stage circuit 100 includes, among other components, a first transistor 112, a second transistor 114, and a selectable path 120. In the embodiment shown in FIG. 1, the first transistor 112 and the second transistor 114 are BJTs. In other embodiments, the first transistor 112 and the second transistor 114 may be other types of transistors, such as metal-oxide-semiconductor field effect transistors (MOSFETs). The first transistor 112 and the second transistor 114 are arranged in a differential configuration.

[0017]

[0024] In some embodiments, the equalizer stage circuit 100 may further include a control unit 180 configured to provide various control signals, which will be described in more detail below with reference to FIGS. 2A-3. In some embodiments, the control unit 180 is a component included in the equalizer stage circuit 100. In other embodiments, the control unit 180 is external to the equalizer stage circuit 100 and a portion of a linear driver including the equalizer stage circuit 100. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0018]

[0025] The selectable path 120 is coupled between the emitter 192 of the first transistor 112 and the emitter 196 of the second transistor 114. Thus, the selectable path 120 may be referred to as an "emitter-side selectable path" or a "source-side selectable path" depending on the device types of the first transistor 112 and the second transistor 114. The selectable path 120 may also be referred to as a "transfer function zero selectable path" as compared to a "transfer function pole selectable path" described below with reference to FIG. 3.

[0019]

[0026] The first terminal ("Terminal A" in Figure 1) is coupled to the emitter 192 of the first transistor 112, and the second terminal ("Terminal B" in Figure 1) is coupled to the emitter 196 of the second transistor 114. The third terminal ("Terminal C-1" in Figure 1) is coupled to the control unit 180 to receive a control signal 182 that controls the high-frequency zero section 122, which will be described below. The fourth terminal ("Terminal C-2" in Figure 1) is coupled to the control unit 180 to receive a control signal 184 that controls the low-frequency zero section 124, which will be described below. The fifth terminal ("Terminal D" in Figure 1) is coupled to the lower power rail (e.g., ground). In Figure 1, only one wire between terminal C-1 and the control unit 180 is symbolically shown, but it should be understood that multiple wires may be used to supply multiple control signals 182, each separately. As described below with reference to Figure 2A, each of the multiple control signals 182 corresponds to one resistive-capacitive (RC) time constant element 132 of the high-frequency zero section 122. Similarly, although only one wire between terminal C-2 and the control unit 180 is symbolically shown in Figure 1, it should be understood that multiple wires may be used to supply each of the multiple control signals 184. As described below with reference to Figure 2A, each of the multiple control signals 184 corresponds to one RC time constant element 134 of the low-frequency zero section 124. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0020]

[0027] As will be described in more detail below with reference to Figures 2A to 2C, the selectable path 120 includes a high-frequency zero section 122 and a low-frequency zero section 124 coupled together. Under the control of digital control signals 182 and 184, the RC time constant element 132 of the high-frequency zero section 122 and the RC time constant element 134 of the low-frequency zero section 124 are selectively coupled between the emitter 192 of the first transistor 112 and the emitter 196 of the second transistor 114. The user can use an external pin control mechanism or I 2The control signals 182 and 184 applied to terminals C-1 and C-2 respectively can be set via any of the C control buses. The user can adjust the control signals 182 and 184 applied to terminals C-1 and C-2 according to the system or device being constructed in order to adapt to a specific insertion loss or input trace when building a particular system or device. The control signals 182 and 184 are usually fixed after the initialization process of the system or device, unless the loss profile changes significantly.

[0021]

[0028] FIG. 2A shows the selectable path 120 shown in FIG. 1 on the source / emitter side for variations in high-frequency zero and low-frequency zero according to an embodiment of the present invention. As mentioned above, the selectable path 120 includes a high-frequency zero portion 122 and a low-frequency zero portion 124 among other components. The low-frequency zero portion 124 is coupled to the high-frequency zero portion 122 via a first capacitor 202 and a second capacitor 204.

[0022]

[0029] The high-frequency zero portion 122 includes a first number (e.g., four in this example shown in FIG. 2A) of RC time-constant elements 132a, 132b, 132c, and 132d (collectively 132) connected in parallel between terminals A and B. The detailed structure of a single RC time-constant element 132 of the high-frequency zero portion 122 is shown in FIG. 2B.

[0023]

[0030] FIG. 2B shows a single RC time-constant element 132 of the high-frequency zero portion 122 according to an embodiment of the present invention. In the example shown in FIG. 2B, the RC time-constant element 132 includes a capacitor C1, a capacitor C2, a resistor R1, a resistor R2, a first access transistor M1, a second access transistor M2, and a third access transistor M3 connected as shown in FIG. 2B. The first access transistor M1 is connected in series between the capacitor C1 and the capacitor C2. The capacitor C1 is coupled to terminal A and the capacitor C2 is coupled to terminal B. When the first access transistor M1 is turned on, the capacitor C1 and the capacitor C2 are connected in series between terminals A and B.

[0024]

[0031] Resistor R1 is connected in series with the second access transistor M2 between node A and ground. Resistor R2 is connected in series with the third access transistor M3 between node B and ground. When the second access transistor M2 is turned on, resistor R1 is connected between node A and ground. When the third access transistor M3 is turned on, resistor R2 is connected between node A and ground. In short, the control signal 182 enables the first access transistor M1, the second access transistor M2, and the third access transistor M3 to be turned on, thereby selectively coupling the corresponding RC time constant elements 132 between terminals A and B.

[0025]

[0032] Thus, the control signals 182 applied to the gates of the first access transistor M1, the second access transistor M2, and the third access transistor M3 selectively couple the RC time constant element 132 between terminals A and B. The RC time constant element 132 is characterized by an RC time constant and corresponding impedance determined by the capacitance values ​​of capacitors C1 and C2 and the resistance values ​​of resistors R1 and R2. By adjusting the capacitance and resistance values, each RC time constant element can provide a desired RC time constant and impedance, thereby adjusting the position of the high-frequency zero. In one example, the gates of the first access transistor M1, the second access transistor M2, and the third access transistor M3 are connected to each other to receive the same control signal.

[0026]

[0033] In one embodiment, one or more of the RC time constant elements 132 are selected at a specific time. In another embodiment, only one of the RC time constant elements 132 is selected at a specific time. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0027]

[0034] The low-frequency zero section 124 includes a second number (for example, seven in the example shown in Figure 2A) of RC time constant elements 134a, 134b, 134c, 134d, 134e, 134f, and 134g (collectively 134) connected in parallel between terminals A and B via a first capacitor 202 and a second capacitor 204. The detailed structure of a single RC time constant element 134 of the low-frequency zero section 124 is shown in Figure 2C.

[0028]

[0035] Figure 2C shows a single RC time constant element 134 of a low-frequency zero section 124 according to an embodiment of the present invention. In the example shown in Figure 2C, the RC time constant element 134 includes resistors R3 and R4, a fourth access transistor M4, and a fifth access transistor M5 connected as shown in Figure 2C. Resistor R3 is connected between the first capacitor 202 and the fourth access transistor M4. Resistor R4 is connected between the second capacitor 204 and the fifth access transistor M5. The fourth access transistor M4 is connected between resistor R3 and ground, and the fifth access transistor M5 is connected between resistor R4 and ground. When the fourth access transistor M4 and the fifth access transistor M5 are turned on, resistor R3 is connected between terminal A and ground (via the first capacitor 202), and resistor R4 is connected between terminal A and ground (via the second capacitor 204).

[0029]

[0036] Thus, the control signals 184 applied to the gates of the fourth access transistor M4 and the fifth access transistor M5 selectively couple the RC time constant elements 134 between terminals A and B. Together with the first capacitor 202 and the second capacitor 204, the RC time constant elements 134 determine the RC time constant and impedance of the low-frequency zero section 124. By adjusting the resistance values ​​of resistors R3 and R4 and the capacitance values ​​of the first capacitor 202 and the second capacitor 204, each RC time constant element 134 can provide a desired RC time constant and impedance, thereby adjusting the position of the low-frequency zero. The introduction of the RC time constant elements 134 of the low-frequency zero section 124, in addition to the high-frequency zero section 122, facilitates further fine-tuning of the equalizer's gain curve. In one example, the gates of the fourth access transistor M4 and the fifth access transistor M5 are connected to each other to receive the same control signal.

[0030]

[0037] In one embodiment, only one of the RC time constant elements 134 is selected at a specific time. In other embodiments, one or more of the RC time constant elements 134 are selected at a specific time. A desired number of RC time constant elements 134 can be selected to achieve a desired impedance of the low-frequency zero section 124. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0031]

[0038] Referring back to Figure 1, in some embodiments, the equalizer stage circuit 100 further includes a selectable path 150. The selectable path 150 is coupled between the collector 194 of the first transistor 112 and the collector 198 of the second transistor 114. Thus, the selectable path 150 may be called a “collector-side selectable path” or a “drain-side selectable path,” depending on the device types of the first transistor 112 and the second transistor 114. The selectable path 150 may also be called a “transfer function pole selectable path,” in comparison to the “transfer function zero selectable path” described above with reference to Figure 2A.

[0032]

[0039] The first terminal ("Terminal E" in Figure 1) is coupled to the collector 194 of the first transistor 112, and the second terminal ("Terminal F" in Figure 1) is coupled to the collector 198 of the second transistor 114. The third terminal ("Terminal G" in Figure 1) is coupled to the control unit 180 to receive a control signal 186 that controls the selection of the RC time constant element 162, which will be described below. The fourth terminal ("Terminal H" in Figure 1) is coupled to the lower power rail (e.g., ground). In Figure 1, only one wire between terminal G and the control unit 180 is symbolically shown, but it should be understood that multiple wires may be used to supply multiple control signals 186, each respectively. As will be described below with reference to Figure 3, each of the multiple control signals 186 corresponds to one of the RC time constant elements 162, which will be described below. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0033]

[0040] Similarly, the user can use an external pin control mechanism or I 2 A control signal 186 can be set, which is applied to terminal G via one of the C control buses. The user may adjust the control signal 186 depending on the specific system or device being built, to adapt to a specific insertion loss or input trace when building a particular system or device. The control signal 186 is typically fixed after the system or device initialization process, unless the insertion loss or input trace changes significantly.

[0034]

[0041] Figure 3 shows the selectable path 150 on the drain / collector side shown in Figure 1 for high-frequency pole variation according to an embodiment of the present invention. The selectable path 150 includes, among other components, a third number (e.g., three in this example shown in Figure 3) of RC time constant elements 162a, 162b, and 162c (collectively 162) connected in parallel between terminals E and F. Each RC time constant element 162 of the selectable path 150 includes capacitors C3 and C4, a sixth access transistor M6, and a seventh access transistor M7 connected as shown in Figure 3.

[0035]

[0042] Capacitor C3 is connected between terminal E and the sixth access transistor M6, and capacitor C4 is connected between terminal F and the seventh access transistor M7. The sixth access transistor M6 is connected between capacitor C3 and ground, and the seventh access transistor M7 is connected between capacitor C4 and ground. When the sixth access transistor M6 and the seventh access transistor M7 are turned on, capacitor C3 is connected between terminal E and ground, and capacitor C4 is connected between terminal F and ground.

[0036]

[0043] Similarly, the control signals 186 applied to the gates of the sixth access transistor M6 and the seventh access transistor M7 selectively couple the RC time constant elements 162 between terminals E and F. The RC time constant elements 162 determine the RC time constant and impedance of the selectable path 150. By adjusting the capacitance values ​​of capacitors C3 and C4, each RC time constant element 162 can provide a desired RC time constant and impedance, thereby adjusting the position of the high-frequency pole. By adjusting the position of the high-frequency pole, as described below with reference to Figures 4 and 5, fine-tuning of the gain curve in the low-frequency region can be facilitated. In one example, the gates of the sixth access transistor M6 and the seventh access transistor M7 are connected to each other to receive the same control signal.

[0037]

[0044] Figure 4 shows a simulation of equalizer gain versus frequency with fixed high-frequency and low-frequency zero variations according to an embodiment of the present invention. As shown in Figure 4, the eight gain curves (i.e., red gain curve #1, gain curve #2, gain curve #3, gain curve #4, gain curve #5, gain curve #6, gain curve #7, and blue gain curve #8) correspond to eight different settings of the control signal, as shown in Table 1 below. [Table 1]

[0038]

[0045] As shown in Table 1, the high-frequency pole control signal 186 shown in the fourth column is fixed (i.e., set to 000 in this example). In other words, the control signal 186 applied to the selectable path 150 on the collector / drain side, as shown in Figure 3, is fixed with respect to the eight gain curves. Therefore, the position of the high-frequency pole remains unchanged.

[0039]

[0046] As shown in Table 1, the high-frequency zero control signal 182 shown in the second column is fixed (i.e., set to 0000 in this example). In other words, the control signal 182 applied to the high-frequency zero section 122 of the emitter / source selectable path 120, as shown in Figure 2B, is fixed with respect to the eight gain curves. Therefore, the position of the high-frequency zero remains unchanged. As shown in Figure 4, the eight gain curves intersect each other at an intersection point (labeled "P" in Figure 4). The intersection point is located at approximately 10 GHz, and the corresponding S-parameter is approximately 7 dB. The intersection of the eight gain curves at approximately 10 GHz provides a simple way to detect variations in the position of the low-frequency zero.

[0040]

[0047] As shown in Table 1, the low-frequency zero control signal 184 shown in the third column is varied (i.e., it is set to 0000000 for gain curve #1, 0000001 for gain curve #2, and so on). In other words, the control signal 184 applied to the low-frequency zero section 124 of the emitter / source selectable path 120, as shown in Figure 2C, is different for the eight gain curves. As a result, the RC time constant elements 134a, 134b, ..., 134g shown in Figure 2A are connected one by one as the control signal 184 progresses from 0000000 to 0000001, 0000011, 0000111, 0001111, 0011111, and 0111111 to 1111111. Gain curve #1 represents the highest RC time constant, and gain curve #8 represents the lowest RC time constant. Therefore, the position of the low-frequency zero can be adjusted as appropriate. As shown in Figure 4, the eight gain curves correspond to different positions of the low-frequency zero, and the slopes of the eight gain curves in the low-frequency region are different from each other, suggesting robust selectivity. As mentioned above, the position of the high-frequency zero remains unchanged (i.e., the eight gain curves intersect each other at the intersection point), so these eight gain curves can be distinguished using only the variation in the position of the low-frequency zero.

[0041]

[0048] Figure 5 shows a simulation of equalizer gain versus frequency with a variable high-frequency zero and a variable low-frequency zero according to an embodiment of the present invention. As shown in Figure 5, the eight gain curves (i.e., light blue gain curve #1, gain curve #2, gain curve #3, gain curve #4, gain curve #5, gain curve #6, gain curve #7, and yellow gain curve #8) correspond to eight different settings of the control signal, as shown in Table 2 below. [Table 2]

[0042]

[0049] As shown in Table 2, the low-frequency zero control signal 184 shown in the third column is varied (i.e., it is set to 0000000 for gain curve #1, 0000001 for gain curve #2, and so on). In other words, the control signal 184 applied to the low-frequency zero section 124 of the emitter / source selectable path 120, as shown in Figure 2C, is different for the eight gain curves. As a result, the RC time constant elements 134a, 134b, ..., 134g shown in Figure 2A are connected one by one as the control signal 184 progresses from 0000000 to 0000001, 0000011, 0000111, 0001111, 0011111, and 0111111 to 1111111. Gain curve #1 represents the highest RC time constant, and gain curve #8 represents the lowest RC time constant. Therefore, the position of the low-frequency zero can be adjusted as appropriate.

[0043]

[0050] However, unlike the example shown in Figure 4, in the example shown in Figure 5, the high-frequency zero control signal 182 shown in the second column is varied. In other words, the control signal 182 applied to the high-frequency zero section 122 of the emitter / source selectable path 120, as shown in Figure 2B, is varied with respect to eight gain curves. As a result, the RC time constant elements 132a, 132b, 132c, and 132d shown in Figure 2A are connected between terminal A and terminal B accordingly as the control signal 182 progresses from 0000 to 0001, 0011, and 0111 and then to 1111.

[0044]

[0051] Unlike the example shown in Figure 4, in the example shown in Figure 5, the high-frequency pole control signal 186 shown in the fourth column is varied. In other words, the control signal 186 applied to the selectable path 150 on the collector / drain side, as shown in Figure 3, is varied with respect to the eight gain curves. Therefore, the position of the high-frequency pole is adjusted accordingly. Note that the position of the high-frequency pole is adjusted with respect to gain curves #1, #2, #3, and #4 because gain curves #1, #2, #3, and #4 share the same position of high-frequency zero due to the same control signal setting (i.e., 0000). Therefore, despite having the same position of high-frequency zero, these four gain curves #1, #2, #3, and #4 can be further distinguished. By adjusting the position of the high-frequency pole, the gain curves can be fine-tuned to facilitate better operation of the low-frequency zero position in the low-frequency region. For example, by adjusting the position of the high-frequency pole, a relatively low gain (i.e., about 2 dB in the example shown in Figure 5) can be achieved with respect to gain curve #1.

[0045]

[0052] Therefore, as shown in Table 2 and explained above, by adjusting the high-frequency zero position, low-frequency zero position, and high-frequency pole position, a degree of freedom is available to achieve a relatively wide gain range at a desired frequency (e.g., approximately 17 GHz as shown by the dashed line in Figure 5) or a desired frequency band (e.g., approximately 16 GHz to approximately 18 GHz). A wider gain range means that the linear redriver's equalizer has a stronger ability to compensate for insertion losses. For example, when the desired frequency or target frequency is approximately 17 GHz, the gain range is approximately 2 dB (of gain curve #1) to approximately 14 dB (of gain curve #8). Knowing the desired frequency or target frequency, the user can adjust the high-frequency zero position, low-frequency zero position, and high-frequency pole position to achieve a relatively wide gain range.

[0046]

[0053] Figure 6 shows a redriver including an equalizer stage circuit according to an embodiment of the present invention. The linear redriver 600 is connected between the transmitter Tx and the receiver Rx. In the example shown in Figure 6, the linear redriver 600 includes, among other components, an input stage circuit 602, an equalizer stage circuit 100 (e.g., the equalizer stage circuit 100 shown in Figure 1), a level shifter 604, and an output stage circuit 606. This example is not intended to be limiting, and it should be understood that the linear redriver 600 may include other components as needed in other embodiments.

[0047]

[0054] The input terminals of the input stage circuit 602 are connected to the transmitter Tx. The input stage circuit 602 includes, among other components, an input matching circuit 612 (e.g., a T-coil), a 50-ohm input termination relative to a reference voltage, and a level shifter 614 (e.g., an emitter follower) that provides a voltage level shift from the input reference voltage to an internal bias voltage level. The output terminals of the level shifter 614 are connected to the input terminals of the equalizer stage circuit 100 (e.g., the base 193 of the first transistor 112 and the base 197 of the second transistor 114, as shown in Figure 1). The output terminals of the equalizer stage circuit 100 (e.g., terminals E and F, as shown in Figure 1) are connected to the level shifter 604 to prepare the bias voltage level for the output stage circuit 606 (specifically, the output buffer 616 of the output stage circuit 606). The output stage circuit 606 includes, among other components, an output buffer 616 and an output matching circuit 618. The output buffer 616 consists of a control circuit that adjusts the flat gain and linear swing control of the linear redriver 600 to adjust the degree of linearity. The output from the output buffer 616 is connected to a 50-ohm output termination relative to a reference voltage via the output matching circuit 618. The output of the output stage circuit 606 is connected to the receiver Rx.

[0048]

[0055] Various examples of this disclosure are provided below. When used below, any reference to the set of examples should be understood disjunctly as a reference to each of those examples (for example, “Examples 1-4” should be understood as “Examples 1, 2, 3, or 4”).

[0049]

[0056] Example 1 is an equalizer stage circuit comprising a first transistor, a second transistor wherein the first and second transistors are arranged in a differential configuration, and a first selectable path comprising a first terminal coupled to the emitter or source of the first transistor, a second terminal coupled to the emitter or source of the second transistor, a high-frequency section comprising a first plurality of high-frequency RC time constant elements connected in parallel between the first and second terminals, a first capacitor coupled to the first terminal, a second capacitor coupled to the second terminal, and a low-frequency section comprising a second plurality of low-frequency RC time constant elements connected between the first and second capacitors.

[0050]

[0057] Example 2 is the equalizer stage circuit of Example 1, wherein each of the first plurality of high-frequency RC time constant elements is selectively coupled between a first terminal and a second terminal based on a first set of control signals.

[0051]

[0058] Example 3 is an equalizer stage circuit of Examples 1-2, wherein the high-frequency section is characterized by a first fluctuating impedance based on a first set of control signals.

[0052]

[0059] Example 4 is an equalizer stage circuit of Examples 1-3, wherein the first fluctuating impedance determines the position of the high-frequency zero of the transfer function.

[0053]

[0060] Example 5 is an equalizer stage circuit of Examples 1-4, wherein each of the second set of low-frequency RC time constant elements is selectively coupled between the first capacitor and the second capacitor based on a second set of control signals.

[0054]

[0061] Example 6 is an equalizer stage circuit of Examples 1-5, wherein the low-frequency section is characterized by a second fluctuating impedance based on a second set of control signals.

[0055]

[0062] Example 7 is an equalizer stage circuit of Examples 1-6, wherein the second fluctuating impedance determines the position of the low-frequency zero of the transfer function.

[0056]

[0063] Example 8 is an equalizer stage circuit of Examples 1 to 7, wherein each of the second plurality of low-frequency RC time constant elements comprises a first resistor connected to the first capacitor, a second resistor connected to the second capacitor, a first access transistor connected between the first resistor and ground, and a second access transistor connected between the second resistor and ground.

[0057]

[0064] Example 9 is an equalizer stage circuit of Examples 1 to 8, further comprising a control unit configured to apply a second set of control signals to the gates of the first and second access transistors of a second plurality of low-frequency RC time constant elements.

[0058]

[0065] Example 10 is an equalizer stage circuit of Examples 1 to 9, further comprising a second selectable path having a third terminal coupled to the collector or drain of a first transistor, a fourth terminal coupled to the collector or drain of a second transistor, and a third plurality of high-frequency RC time constant elements connected between the third terminal and the fourth terminal.

[0059]

[0066] Example 11 is an equalizer stage circuit of Examples 1 to 10, wherein each of the third plurality of high-frequency RC time constant elements is selectively coupled between the third terminal and the fourth terminal based on a third set of control signals.

[0060]

[0067] Example 12 is an equalizer stage circuit of Examples 1-11, wherein the second selectable path is characterized by a third fluctuating impedance based on a third set of control signals.

[0061]

[0068] Example 13 is an equalizer stage circuit of Examples 1-12, in which the third fluctuating impedance determines the position of the high-frequency pole of the transfer function.

[0062]

[0069] Example 14 is a linear redriver coupled between a transmitter and a receiver, the linear redriver comprising an input stage circuit coupled to the transmitter, an output stage circuit coupled to the receiver, and an equalizer stage circuit coupled between the input stage circuit and the output stage circuit, the equalizer stage circuit comprising a first transistor, a second transistor, the first and second transistors arranged in a differential configuration, and a first selectable path comprising a first terminal coupled to the emitter or source of the first transistor, a second terminal coupled to the emitter or source of the second transistor, a high-frequency section comprising a first plurality of high-frequency RC time constant elements connected in parallel between the first and second terminals, a first capacitor coupled to the first terminal, a second capacitor coupled to the second terminal, and a low-frequency section comprising a second plurality of low-frequency RC time constant elements connected between the first and second capacitors.

[0063]

[0070] Example 15 is an equalizer stage circuit of Example 14, wherein each of the first plurality of high-frequency RC time constant elements is selectively coupled between a first terminal and a second terminal based on a first set of control signals.

[0064]

[0071] Example 16 is an equalizer stage circuit of Examples 14-15, wherein the high-frequency section is characterized by a first fluctuating impedance based on a first set of control signals.

[0065]

[0072] Example 17 is an equalizer stage circuit of Examples 14-16, wherein the first fluctuating impedance determines the position of the high-frequency zero of the transfer function.

[0066]

[0073] Example 18 is an equalizer stage circuit of Examples 14-17, wherein each of the second set of low-frequency RC time constant elements is selectively coupled between the first capacitor and the second capacitor based on a second set of control signals.

[0067]

[0074] Example 19 is an equalizer stage circuit of Examples 14-18, wherein the low-frequency section is characterized by a second fluctuating impedance based on a second set of control signals.

[0068]

[0075] Example 20 is an equalizer stage circuit of Examples 14-19, wherein the second fluctuating impedance determines the position of the low-frequency zero of the transfer function.

[0069]

[0076] Example 21 is an equalizer stage circuit of Examples 14-20, wherein each of the second plurality of low-frequency RC time constant elements comprises a first resistor connected to a first capacitor, a second resistor connected to a second capacitor, a first access transistor connected between the first resistor and ground, and a second access transistor connected between the second resistor and ground.

[0070]

[0077] Example 22 is an equalizer stage circuit of Examples 14-21, further comprising a control unit configured to apply a second set of control signals to the gates of the first and second access transistors of a second plurality of low-frequency RC time constant elements.

[0071]

[0078] Example 23 is an equalizer stage circuit of Examples 14-22, further comprising a second selectable path comprising a third terminal coupled to the collector or drain of a first transistor, a fourth terminal coupled to the collector or drain of a second transistor, and a third plurality of high-frequency RC time constant elements connected between the third and fourth terminals.

[0072]

[0079] Example 24 is an equalizer stage circuit of Examples 14-23, wherein each of the third plurality of high-frequency RC time constant elements is selectively coupled between the third terminal and the fourth terminal based on a third set of control signals.

[0073]

[0080] Example 25 is an equalizer stage circuit of Examples 14-24, wherein the second selectable path is characterized by a third fluctuating impedance based on a third set of control signals.

[0074]

[0081] Example 26 is an equalizer stage circuit of Examples 14-25, in which the third fluctuating impedance determines the position of the high-frequency pole of the transfer function.

[0075]

[0082] The examples and embodiments described herein are for illustrative purposes only, and it will be understood that various modifications or changes thereto will be suggested to those skilled in the art and should be included in the spirit and scope of this application and the appended claims.

Claims

1. Equalizer stage circuit, The first transistor and A second transistor, wherein the first transistor and the second transistor are arranged in a differential configuration, A first selectable route, A first terminal coupled to the emitter or source of the first transistor, A second terminal coupled to the emitter or source of the second transistor, A high-frequency section comprising a first plurality of high-frequency RC time constant elements connected in parallel between the first terminal and the second terminal, A first capacitor coupled to the first terminal, A second capacitor connected to the second terminal, and A low-frequency section comprising a second plurality of low-frequency RC time constant elements connected between the first capacitor and the second capacitor. A first selectable path comprising An equalizer stage circuit equipped with this.

2. The equalizer stage circuit according to claim 1, wherein each of the first plurality of high-frequency RC time constant elements is selectively coupled between the first terminal and the second terminal based on a first set of control signals.

3. The equalizer stage circuit according to claim 2, wherein the high-frequency section is characterized by a first fluctuating impedance based on the first set of control signals.

4. The equalizer stage circuit according to claim 3, wherein the first fluctuating impedance determines the position of the high-frequency zero of the transfer function.

5. The equalizer stage circuit according to claim 1, wherein each of the second plurality of low-frequency RC time constant elements is selectively coupled between the first capacitor and the second capacitor based on a second set of control signals.

6. The equalizer stage circuit according to claim 5, wherein the low-frequency section is characterized by a second fluctuating impedance based on the second set of control signals.

7. The equalizer stage circuit according to claim 6, wherein the second fluctuating impedance determines the position of the low-frequency zero of the transfer function.

8. Each of the second plurality of low-frequency RC time constant elements is, The first resistor connected to the first capacitor, The second resistor connected to the second capacitor, A first access transistor connected between the first resistor and ground, A second access transistor connected between the second resistor and the ground, The equalizer stage circuit according to claim 5, comprising:

9. The equalizer stage circuit according to claim 8, further comprising a control unit configured to apply the second set of control signals to the gates of the first access transistors and the gates of the second access transistors of the second plurality of low-frequency RC time constant elements.

10. A second selectable route, A third terminal connected to the collector or drain of the first transistor, A fourth terminal connected to the collector or drain of the second transistor, A third plurality of high-frequency RC time constant elements connected between the third terminal and the fourth terminal, A second selectable path comprising The equalizer stage circuit according to claim 1, further comprising:

11. The equalizer stage circuit according to claim 10, wherein each of the third plurality of high-frequency RC time constant elements is selectively coupled between the third terminal and the fourth terminal based on a third set of control signals.

12. The equalizer stage circuit according to claim 11, wherein the second selectable path is characterized by a third fluctuating impedance based on the third set of control signals.

13. The equalizer stage circuit according to claim 12, wherein the third fluctuating impedance determines the position of the high-frequency pole of the transfer function.

14. A linear redriver coupled between a transmitter and a receiver, wherein the linear redriver is An input stage circuit coupled to the transmitter, An output stage circuit coupled to the receiver, An equalizer stage circuit coupled between the input stage circuit and the output stage circuit, wherein the equalizer stage circuit is The first transistor, A second transistor wherein the first transistor and the second transistor are arranged in a differential configuration, and A first selectable route, A first terminal coupled to the emitter or source of the first transistor, A second terminal coupled to the emitter or source of the second transistor, A high-frequency section comprising a first plurality of high-frequency RC time constant elements connected in parallel between the first terminal and the second terminal, A first capacitor coupled to the first terminal, A second capacitor connected to the second terminal, and A low-frequency section comprising a second plurality of low-frequency RC time constant elements connected between the first capacitor and the second capacitor. A first selectable path comprising Equipped with an equalizer stage circuit A linear redriver equipped with

15. The equalizer stage circuit according to claim 14, wherein each of the first plurality of high-frequency RC time constant elements is selectively coupled between the first terminal and the second terminal based on a first set of control signals.

16. The equalizer stage circuit according to claim 15, wherein the high-frequency section is characterized by a first fluctuating impedance based on the first set of control signals.

17. The equalizer stage circuit according to claim 16, wherein the first fluctuating impedance determines the position of the high-frequency zero of the transfer function.

18. The equalizer stage circuit according to claim 14, wherein each of the second plurality of low-frequency RC time constant elements is selectively coupled between the first capacitor and the second capacitor based on a second set of control signals.

19. The equalizer stage circuit according to claim 18, wherein the low-frequency section is characterized by a second fluctuating impedance based on the second set of control signals.

20. The equalizer stage circuit according to claim 19, wherein the second fluctuating impedance determines the position of the low-frequency zero of the transfer function.

21. Each of the second plurality of low-frequency RC time constant elements is, The first resistor connected to the first capacitor, The second resistor connected to the second capacitor, A first access transistor connected between the first resistor and ground, A second access transistor connected between the second resistor and the ground, The equalizer stage circuit according to claim 18, comprising:

22. The equalizer stage circuit according to claim 21, further comprising a control unit configured to apply the second set of control signals to the gates of the first access transistors and the gates of the second access transistors of the second plurality of low-frequency RC time constant elements.

23. A second selectable route, A third terminal connected to the collector or drain of the first transistor, A fourth terminal connected to the collector or drain of the second transistor, A third plurality of high-frequency RC time constant elements connected between the third terminal and the fourth terminal, A second selectable path comprising The equalizer stage circuit according to claim 14, further comprising:

24. The equalizer stage circuit according to claim 23, wherein each of the third plurality of high-frequency RC time constant elements is selectively coupled between the third terminal and the fourth terminal based on a third set of control signals.

25. The equalizer stage circuit according to claim 24, wherein the second selectable path is characterized by a third fluctuating impedance based on the third set of control signals.

26. The equalizer stage circuit according to claim 25, wherein the third fluctuating impedance determines the position of the high-frequency pole of the transfer function.

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