Input / Output (I / O) Interface, Memory Device, and Memory System

Abstract

Methods, devices, and systems for managing warm-up operations in a memory device are provided. In one embodiment, the input / output (I / O) interface of a memory device may be configured to receive a first address of first data to be read, receive warm-up information indicating a warm-up period before reading the first data, and determine a second address of second data to be read during the warm-up period before reading the first data, based on the first address and the warm-up information.

Description

Technical Field

[0001] The present disclosure generally relates to memory devices and memory systems, and more particularly to managing warm-up operations in memory devices.

Background Art

[0002] Flash memory is a low-cost, high-density non-volatile solid-state memory medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations, such as program (write) and erase operations, can be performed by the flash memory to change the threshold voltage of each memory cell to respective levels. In the case of NAND flash memory, the erase operation can be performed at the block level, the program operation can be performed at the page level, and the read operation can be performed at the page level.

Summary of the Invention

[0003] The present disclosure includes methods, apparatuses, and systems for managing warm-up operations in memory devices. In one example, an input / output (I / O) interface of a memory device receives a first address of first data to be read, receives warm-up information indicating a warm-up period before reading the first data, and is configured to determine a second address of second data to be read during the warm-up period before reading the first data based on the first address and the warm-up information. The warm-up operation can be performed by reading the second data during the warm-up period before reading the first data.

[0004] In some implementations, the I / O interface includes an address shifter and a first frequency divider coupled to the address shifter. The address shifter is configured to determine, as the second address, the first address minus the number of warm-up cycles, and transmit the second address to the first frequency divider.

[0005] In some implementations, the address shifter is configured to consider negative values ​​when determining the second address in response to determining that the first address minus the number of warm-up cycles is a negative value.

[0006] In several implementations, the I / O interface receives a first clock signal. A first frequency divider is configured to generate a second clock signal having a frequency of 1 / 4 of the frequency of the first clock signal.

[0007] In some implementations, the first and second data are read from a first-in, first-out (FIFO) cache of the memory device.

[0008] In some implementations, the address shifter is configured to consider negative values ​​when determining the second address by sending a control signal to the first frequency divider. The control signal is configured to instruct the FIFO cache output pointer to skip the first rising edge of the second clock signal during the warm-up period.

[0009] In some implementations, the I / O interface includes a second frequency divider configured to generate a third clock signal having half the frequency of a first clock signal, and a third frequency divider configured to generate a fourth clock signal having one-eighth the frequency of the first clock signal.

[0010] In some implementations, the I / O interface is configured to, in response to receiving a read command to read a first piece of data, reset the data path of the I / O interface during the first pulse, read the data based on the fourth least significant bit of the second address during the second pulse, read the data based on the third least significant bit of the second address during the third pulse, and read the data based on the second least significant bit of the second address during the fourth pulse.

[0011] In some implementations, the I / O interface is configured to, in response to receiving a read resume command to read first data after a read pause, reset the data path of the I / O interface during the first pulse, read data based on the fourth least significant bit of the second address during the second pulse, read data based on the third least significant bit of the second address during the third pulse, and read data based on the second least significant bit of the second address during the fourth pulse.

[0012] In some implementations, the I / O interface is configured to output a second data during the warm-up period and a first data after the warm-up period.

[0013] One aspect of the present disclosure provides a memory device. The memory device includes a memory cell array containing memory cells and peripheral circuits coupled to the memory cell array. The peripheral circuits include an input / output (I / O) interface. The I / O interface is configured to receive a first address of first data to be read, receive warm-up information indicating a warm-up period before reading the first data, and determine a second address of second data to be read during the warm-up period before reading the first data, based on the first address and the warm-up information.

[0014] In some implementations, the I / O interface includes an address shifter and a first frequency divider coupled to the address shifter. The address shifter is configured to determine a second address by subtracting the number of warm-up cycles from the first address and to transmit the second address to the first frequency divider.

[0015] In some implementations, the address shifter is configured to consider negative values ​​when determining the second address in response to determining that the first address minus the number of warm-up cycles is a negative value.

[0016] In some implementations, the peripheral circuitry includes a first-in, first-out (FIFO) cache, and the first and second data are read from the FIFO cache.

[0017] In several implementations, the I / O interface receives a first clock signal. A first frequency divider is configured to generate a second clock signal having a frequency of 1 / 4 of the frequency of the first clock signal. An address shifter is configured to consider negative values ​​when determining the second address by sending a control signal to the first frequency divider. The control signal is configured to instruct the FIFO cache output pointer to skip the first rising edge of the second clock signal during the warm-up period.

[0018] In some implementations, the peripheral circuitry is configured to read the second data during the warm-up period and the first data after the warm-up period.

[0019] In some implementations, the memory device includes a NAND memory device.

[0020] One aspect of the present disclosure provides a memory system. The memory system includes a memory controller and a memory device coupled to the memory controller. The memory controller is configured to transmit a read command for reading first data, a first address of the first data, and warm-up information indicating a warm-up period before reading first data. The memory device includes a memory cell array including memory cells and peripheral circuitry including an input / output (I / O) interface. The I / O interface is configured to receive the read command, the first address, and the warm-up information, and to determine, based on the first address and the warm-up information, a second address of second data to be read during a warm-up period before reading the first data.

[0021] In some implementations, determining the second address includes determining, as the second address, the result of subtracting the number of warm-up cycles from the first address.

[0022] In some implementations, the peripheral circuit is configured to read second data during the warm-up period and read the first data array after the warm-up period.

[0023] Although generally described as computer-implemented software embodied on a tangible medium that processes and transforms each data, some or all of the aspects may be a computer-implemented method or may further be included in each system or other device for performing the described functions. Details of these and other aspects and implementations of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will become apparent from the specification text, the drawings, and the claims.

Brief Description of the Drawings

[0024] [Figure 1] A block diagram of an example of a system having a memory device according to some aspects of the present disclosure is shown. [Figure 2A] Some storage products according to some aspects of the present disclosure are shown. [Figure 2B] Some storage products according to some aspects of the present disclosure are shown. [Figure 3] A schematic diagram of an example of a memory device including a peripheral circuit according to some aspects of the present disclosure is shown. [Figure 4] Some examples of peripheral circuits according to some aspects of the present disclosure are shown. [Figure 5] A schematic timing diagram of an example of a data output process according to some aspects of the present disclosure is shown. [Figure 6] Some examples of circuits in an I / O interface according to some aspects of the present disclosure are shown. [Figure 7]A schematic diagram of an example of a process for generating a column address shifted based on a column address of output data and the number of warm-up cycles according to some aspects of the present disclosure is shown. [Figure 8] An example of a lookup table of shifted addresses according to the address of output data and the number of warm-up cycles according to some aspects of the present disclosure is shown. [Figure 9] A flowchart of an example of a process for fetching data from an output buffer according to some aspects of the present disclosure is shown. [Figure 10] An example of a method for reading data from a memory system according to some aspects of the present disclosure is shown. [Figure 11] A flowchart of an example of a process for executing a read operation including a warm-up cycle according to some aspects of the present disclosure is shown. [Figure 12] A schematic timing diagram of an example of read pause and resume according to some aspects of the present disclosure is shown.

[0025] Like reference numerals and signs in the various drawings indicate like elements.

Best Mode for Carrying Out the Invention

[0026] This specification relates to a memory device, memory system, and method for managing warm-up operations in NAND flash memory. In dynamic random access memory (DRAM) memory, a preamble / postamble mechanism is provided for the input / output (I / O) interface to ensure accurate data transmission. For example, extra transitions for clock signals, such as the write clock (WCK) signal and the read data strobe (RDQS) signal, are introduced before and after the clock signal for effective data transmission. Unlike DRAM I / O interfaces, a preamble / postamble mechanism is generally not provided for NAND I / O interfaces to take into consideration low power consumption. In particular, under high-speed data transmission in NAND I / O interfaces (e.g., 800 Mbps or higher), a warm-up cycle is introduced at the start of data input and / or output in NAND flash memory to improve the stability and accuracy of data transmission in the NAND I / O interface.

[0027] In some cases, the warm-up operation during the warm-up cycle is performed using a clock gating method. Specifically, after entering read / write mode, the clock path for read / write operations is locked during the warm-up cycle. After the warm-up cycle is complete, the global warm-up control sends a control signal to switch on the clock path for each data line (DQ) signal or data strobe (DQS) signal. The control signal from the global warm-up controller must reach each DQ within one cycle to trigger the next operation, and each DQ may need to switch its clock path precisely on within half a cycle. Switching the clock path too early or too late can create glitches in the clock path, resulting in abnormal read and / or write operations. However, as the speed of the NAND I / O interface continues to increase (e.g., beyond 3.6 Gbps), the time margin for switching the clock path on becomes thinner (e.g., less than 100 ps). Therefore, it is difficult to switch the clock path on within a half-cycle, and consequently, it is difficult to perform a warm-up operation using a clock gating method for high-speed NAND I / O interfaces.

[0028] This disclosure provides a technique for performing a warm-up operation in NAND flash memory by shifting a read address (e.g., the address of data output from an I / O interface). In some implementations, the NAND I / O interface may include an address shifter configured to determine the shifted read address based on the original read address (e.g., the address of data that the host intends to read, as indicated by a read command) and configuration information regarding the warm-up cycle (e.g., the number of warm-up cycles provided at the start of data output). For example, the shifted read address may be determined by subtracting the number of warm-up cycles from the original read address. Thus, when data output begins in a warm-up cycle, the data lines of the I / O interface can output dummy data (e.g., data not intended by the host to be read, also referred to as warm-up data) starting from the shifted read address. After the warm-up cycle is complete, the data lines of the I / O interface can output data starting precisely from the original read address.

[0029] In several implementations, the described techniques can achieve one or more technical effects. For example, the warm-up operation by shifting the read address does not require switching on the clock path within a specific time margin and is therefore more suitable for high-speed I / O interfaces. Also, compared to the warm-up operation using the clock gating method, in which the clock path is locked during the warm-up cycle and therefore no data is transmitted on the data lines during the warm-up cycle, the warm-up operation by shifting the read address transmits dummy data on the data lines during the warm-up cycle. In this way, more circuits within the I / O interface and other peripheral circuits of the NAND flash memory are warmed up by actively operating during the warm-up cycle, making the warm-up operation more comprehensive and effective. Furthermore, the described techniques do not require additional logic control on the high-speed clock path, thereby reducing clock noise. Moreover, the described techniques are independent of high-speed circuits and therefore can be used to implement the described techniques using slower devices with less leakage. In several implementations, this can reduce idle power consumption and simplify the layout of the NAND flash memory. In several implementations, additional or different technical effects can be achieved.

[0030] Figure 1 shows a block diagram of an example of a system 100 having a memory device according to several aspects of the present disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, argument reality (AR) device, or any other suitable electronic device having internal storage. As shown in Figure 1, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may include one or more processors of the electronic device. The processor may be a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host 108 may be configured to send and receive data and commands to and from the memory system 102.

[0031] The memory device 104 may be any memory device disclosed herein, such as a NAND flash memory device. Note that NAND flash is merely an example of a memory device for illustrative purposes. NAND flash may include any suitable solid-state non-volatile memory, such as NOR flash, ferroelectric RAM (FeRAM), phase-change memory (PCM), magnetoresistive random-access memory (MRAM), spin-transfer torque magnetic random-access memory (STT-RAM), or resistive random-access memory (RRAM). In some implementations, the memory device 104 includes a three-dimensional (3D) NAND flash memory device.

[0032] The memory controller 106 may be implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform various functions described in detail below.

[0033] In some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in low-duty-cycle environments such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in high-duty-cycle environments such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and for enterprise storage arrays. The memory controller 106 may be configured to control the operation of the memory device 104, such as read operations, erase operations, and program operations. The memory controller 106 can also be configured to manage various functions related to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 106 is further configured to process error correction codes (ECC) with respect to data read from or written to the memory device 104. Any other appropriate functions can also be performed by the memory controller 106, such as formatting the memory device 104.

[0034] The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with an external device via at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Extended Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol. The memory controller 106 is configured to send and receive commands to and from the host 108 and to perform or perform a number of functions and operations provided in the disclosure described later.

[0035] The memory controller 106 and one or more memory devices 104 can be incorporated into various types of storage devices. For example, the memory controller 106 and one or more memory devices 104 can be packaged in a Universal Flash Storage (UFS) package or an eMMC package. In one example shown in Figure 2A, the memory controller 106 and a single memory device 104 can be incorporated into a memory card 202. The memory card 202 may include PC cards (PCMCIA, personal computer memory card international association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may further include a memory card connector 204 that connects the memory card 202 to a host (for example, host 108 in Figure 1). In another example shown in Figure 2B, the memory controller 106 and multiple memory devices 104 can be incorporated into an SSD 206. The SSD206 may further include an SSD connector 208 that connects the SSD206 to a host (for example, host 108 in Figure 1). In some implementations, the storage capacity and / or operating speed of the SSD206 is greater than that of the memory card 202.

[0036] Figure 3 shows a schematic circuit diagram of an example of a memory device 300 including peripheral circuits according to several embodiments of the present disclosure. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array in which memory cells 306 are provided in the form of an array of NAND memory strings 308, each extending vertically above a substrate (not shown in Figure 3). In several implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the memory layer of the memory cell 306. The logical state (i.e., data) of each memory cell 306 in the memory block 304 may be determined based on a threshold voltage Vth of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trap transistor.

[0037] In some implementations, each memory cell 306 is a single-level cell (SLC) with two possible memory states capable of storing 1 bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing 2 or more bits of data in three or more memory states. For example, an MLC can store 2 bits per cell, 3 bits per cell (also known as a triple-level cell (TLC)), or 4 bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to support a range of possible nominal storage values. For example, if each MLC stores 2 bits of data, the MLC can be programmed from an erased state to one of three possible programming levels by writing one of three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erased state.

[0038] As shown in Figure 3, each NAND memory string 308 may include a source selection gate (SSG) 310 at its source end and a drain selection gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected NAND memory string 308 (array column) during read and program operations. In some implementations, the sources of NAND memory strings 308 within the same memory block 304 are coupled via the same source line (SL) 314, for example, a common SL. In other words, according to some implementations, NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some implementations, the DSG 312 of each NAND memory string 308 is coupled to its respective bit line 316, and data can be read from or written from its respective bit line 316 via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having the DSG312) or a deselection voltage (e.g., 0V) to each DSG312 via one or more DSG lines 313, and / or by applying a selection voltage (e.g., exceeding the threshold voltage of the transistor having the SSG310) or a deselection voltage (e.g., 0V) to each SSG310 via one or more SSG lines 315.

[0039] As shown in Figure 3, the NAND memory string 308 can be organized into multiple memory blocks 304, each having a common SL314 coupled to the ACS. In some implementations, each memory block 304 can function as a basic data unit for an erase operation, such that memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the SL314 coupled to the selected memory block 304 and the unselected memory blocks in the same plane can be biased with an erase voltage. For example, the erase voltage can be a high positive voltage (e.g., 20V or higher). In some implementations, the erase operation can be performed at the half-block level, the quarter-block level, or at any appropriate level with a number of memory blocks or a portion of memory blocks.

[0040] Memory cells 306 of adjacent NAND memory strings 308 may be connected via word lines 318. The word lines 318 can select which rows of memory cells 306 are affected by read and program operations. Each word line 318 may include gate lines connected to multiple control gates (gate electrodes) of multiple memory cells 306. An exemplary word line shown in Figure 3 lies between one or more DSG lines 313 and one or more SSG lines 315.

[0041] Figure 4 shows several exemplary peripheral circuits 302 relating to several aspects of the present disclosure. Peripheral circuits 302 may be coupled to the memory cell array 301 via bit lines 316, word lines 318, SL 314, SSG lines 315, and DSG lines 313. As previously stated, peripheral circuits 302 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit lines 316, word lines 318, SL 314, SSG lines 315, and DSG lines 313 and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuits 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. The exemplary peripheral circuitry 302 includes a page buffer / sense amplifier 404, a column decoder / bit line driver 406, a row decoder / word line driver 408, a voltage generator 410, control logic 412, registers 414, an input / output (I / O) interface 416, and a data bus. Some examples may also include additional peripheral circuitry not shown in Figure 4.

[0042] The page buffer / sense amplifier 404 may be configured to read and program (write) data to and from the memory cell array 301 according to a control signal from the control logic 412. In another example, the page buffer / sense amplifier 404 may also perform a program verification operation to ensure that data is properly programmed into the memory cell 306 coupled to the selected word line 418. In yet another example, the page buffer / sense amplifier 404 may also sense a low-power signal from the bit line 316 representing data bits stored in the memory cell 306 and amplify a small voltage amplitude to a logic level that is recognizable in the read operation. The column decoder / bit line driver 406 may be controlled by the control logic 412 and configured to select one or more NAND memory strings 308 by applying bit line voltages generated from the voltage generator 410.

[0043] The row decoder / word line driver 408 is controlled by control logic 412 and may be configured to select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 418 of memory blocks 304. The row decoder / word line driver 408 may be further configured to drive word lines 418 using word line voltages generated from a voltage generator 410. In some implementations, the row decoder / word line driver 408 can also select / deselect and drive SSG lines 415 and DSG lines 413. As will be described in detail below, the row decoder / word line driver 408 is configured to apply a program voltage to the selected word line 418 during program operation at the memory cell 306 coupled to the selected word line 418.

[0044] The voltage generator 410 may be controlled by the control logic 412 and configured to generate word line voltages (e.g., read voltage, program voltage, path voltage, local voltage, and verification voltage), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0045] The control logic 412 may be coupled to each of the aforementioned peripheral circuits and may be configured to control the operation of each peripheral circuit. The register 414 may be coupled to the control logic 412 and may include a state register, a command register, and an address register for storing state information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0046] The I / O interface 416 can be coupled to the control logic 412 and can function as a control buffer for buffering control commands received from the memory controller and relaying them to the control logic 412, as well as for buffering state information received from the control logic 412 and relaying it to the memory controller. The I / O interface 416 can also be coupled to the column decoder / bit line driver 406 via the data bus and can function as a data buffer for buffering and relaying data between the data input / output (I / O) interface and the memory cell array 301.

[0047] Figure 5 shows a schematic timing diagram of an example of a data output process 500 according to several aspects of the present disclosure. The data output process 500 may include command signals such as a read enable signal (RE_n), a data strobe signal (DQS) corresponding to RE_n, and a data line signal DQ[7:0].

[0048] To support high-speed operation, the I / O interface 416 can support a warm-up cycle before outputting data from or inputting data into the memory device 300. In some implementations, the data output process 500 may include a warm-up cycle 512 and a data output cycle 514 following the warm-up cycle 512. During the data output cycle 514, the I / O interface 416 outputs output data 524 (e.g., D0, D1, D2, D3, D4, ...) requested by the memory controller by one or more read commands. To ensure the integrity and accuracy of the data during the data output cycle 514, a warm-up cycle 512 is provided before the data output cycle 514. In some implementations, the warm-up cycle is provided by bringing about an additional RE_n transition and a corresponding DQS transition at the start of the data output process 500. The additional RE_n transition and DQS transition are associated with the warm-up data 522. For example, during a warm-up cycle 512, DQ[7:0] may output warm-up data 522 in response to both the rising and falling edges of the RE_n and DQS signals. In some implementations, warm-up data 522 may be different from the output data 524 preceding output data 524, for example, in a first-in, first-out (FIFO) cache. In some other implementations, warm-up data 522 may be the same as a portion of output data 524, for example, the beginning portion of output data 524.

[0049] In some implementations, the data output process 500 may include, for example, one, two, or four warm-up cycles 512. For example, as shown in Figure 5, the data output process 500 includes two warm-up cycles 512 before the data output cycle 514. Each warm-up cycle 512 includes a full RE_n cycle (including both the rising and falling edges in RE_n) and a full corresponding DQS cycle (including both the rising and falling edges in DQS). For example, if data is transmitted on both the rising and falling edges in DQS, two bits of warm-up data 522 can be output through each pin of DQ[7:0] during the warm-up cycle 512. In some implementations, the memory controller may transmit warm-up information (e.g., FA02h set features for NV-DDR2, NV-DDR3, and NV-LPDDR4 configurations) to the I / O interface 416. The warm-up information may indicate the number of warm-up cycles 512, in particular configuration information relating to the warm-up cycles 512, such as whether the warm-up cycles 512 are enabled with respect to the data input process and / or data output process, and the number of warm-up cycles provided for the data input process.

[0050] In some implementations, when the memory controller resumes the data output process after a pause, the resumed data output process may include a warm-up cycle 512 before continuing to output data after the pause. In some implementations, the data input process may also include a warm-up cycle. The number of warm-up cycles for the data input process and the data output process 500 may be configured as the same or different values. The warm-up cycle is active when the selected data interface is NV-DDR2, NV-DDR3, or NV-LPDDR4, and the warm-up cycle is enabled in the NV-DDR2 / NV-DDR3 / NV-LPDDR4 Configuration feature. For NV-DDR2, it is recommended that the NV-DDR2 / NV-DDR3 / NV-LPDDR4 Configuration feature be configured using the SDR data interface. If the warm-up cycle is enabled while the NV-DDR2, NV-DDR3, or NV-LPDDR4 interface is active, the warm-up cycle shall be used for all subsequent commands after the set feature is completed.

[0051] Figure 6 shows some exemplary circuits in an I / O interface 416 according to some aspects of the present disclosure. The exemplary circuits in the I / O interface 416 may include a gate delay circuit 602, a frequency divider 604, a read address shifter 606, and one or more inverters 608. The I / O interface 416 may also include other circuits such as a read clock generator, a write clock generator, and a serial-to-parallel converter.

[0052] In some implementations, the gate delay circuit 602 can receive a first read clock signal 612 (rd_clk_x1) and generate a second read clock signal 614 (rd_clk_x1_ser). For example, the first read clock signal 612 may be the RE_n signal in Figure 5. The second read clock signal 614 may be the DQS signal in Figure 4, having the same frequency as the first read clock signal 612 but with a delayed phase position compared to the first read clock signal 612. In some cases, the memory cell array (e.g., the memory cell array 301 in Figure 3) outputs data at a relatively low frequency, for example, a frequency lower than the frequency of the data output by the I / O interface. Another frequency divider circuit (not shown in Figure 6) can generate a low-frequency signal based on the first read clock signal 612 to control the data output from the memory cell array. For example, the low-frequency signal, along with the second read clock signal 612, may be received by a sterilizer that controls the serial data output from the memory cell array to the FIFO cache. A FIFO cache can be used as intermediate storage to compensate for the speed difference between the memory device and the memory controller. In some implementations, a FIFO cache in a NAND interface can be configured in various dimensions, such as multiple rows and columns, depending on the specific application requirements. For example, a FIFO cache can be configured as 32 rows x 8 columns (for example, each row can store 8 data points, and each data point can be a bit, byte, word, or larger unit), enabling the storage of a total of 256 data points. In some implementations, before outputting data from the memory device to the memory controller, the data is first read serially from the memory cell array and stored in the FIFO cache.

[0053] In some implementations, the frequency divider circuit 604 may include one or more frequency dividers. For example, as shown in Figure 6, the frequency divider circuit 604 includes a frequency divider 642 that generates a third read clock signal (rd_clk_x2) having half the frequency of the first read clock signal 612, a frequency divider 644 that generates a fourth read clock signal (rd_clk_x4) having one-quarter the frequency of the first read clock signal 612, and a frequency divider 646 that generates a fifth read clock signal (rd_clk_x8) having one-eighth the frequency of the first read clock signal 612.

[0054] In some implementations, the read address shifter 606 can receive a first input containing the address 662 of the output data 524 and a second input containing the number of warm-up cycles 664 prior to the data output cycle 514. For example, the full column address of the output data 524 may contain 14 bits represented by CA<13:0>, and CA <13> This is the most significant bit, CA <0> is the least significant bit. The memory controller can select a memory plane in the memory cell array based on the first 10 bits (CA<13:4>) in the column address, and the I / O interface 416 can select a specific memory cell in the selected memory plane using the last 4 bits (CA<3:0>) in the column address. In some implementations, address 662 may contain the second and third least significant bits (e.g., CA<2:1>) of the full column address of the output data 524.

[0055] In some implementations, the number of warm-up cycles, 664, can be represented by a 2-bit wu_do<1:0>. For example, a wu_do<1:0> of "00" indicates that no warm-up cycle 512 precedes the data output cycle 514; a wu_do<1:0> of "01" indicates that one warm-up cycle 512 precedes the data output cycle 514; a wu_do<1:0> of "10" indicates that two warm-up cycles 512 precede the data output cycle 514; and a wu_do<1:0> of "11" indicates that four warm-up cycles 512 precede the data output cycle 514.

[0056] The read address shifter 606 can output a shifted address 666 based on the address 662 of the output data 524 and the number of warm-up cycles 664. In some implementations, the shifted address 666 may be determined by subtracting the number of warm-up cycles 664 from address 662. Thus, the shifted address 666 is the address of the warm-up data 522 that should be read in the warm-up cycle 512.

[0057] In some implementations, the read address shifter 606 can send the shifted address 666 and the control signal 668 to the frequency divider 644. For example, the control signal 668 (e.g., sel_u2b) can be used to select two data points from four data points. The frequency divider 644 then receives the control signal (e.g., sel_u4b) and the fourth significant bit (CA) of the column address. <3> The frequency divider 646 can receive the signal (e.g., sel_u4b) and the FIFO address (e.g., FIFO <n:0>The data can be sent to the FIFO cache. For example, a control signal (e.g., sel_u8b) can be used to select 8 data points from 16 data points, and the FIFO address can indicate the starting address in the FIFO cache from which the data output process 500 (including the warm-up cycle) begins. In some implementations, when data is read from the memory cell array to the FIFO cache before outputting data to the memory controller, the data is read serially in units of 16 data points. Thus, the frequency divider circuit 604 can be configured to select 2 data points from 16 data points, and as a result, each data line of DQ[7:0] of the I / O interface 416 can output 2 data points during the DQS cycle.

[0058] Figure 7 shows a schematic diagram of an example of a process that generates an address 666 shifted based on the address 662 and warm-up cycle number 664 of the output data 524, according to some aspects of the present disclosure. In some implementations, the output data 524 is first stored in a FIFO cache 700 before being output to, for example, a memory controller. As an example, the FIFO cache 700 may be configured to have multiple rows, each row capable of storing eight data points. In a scenario where two data points are read during a DQS cycle (for example, data is read in response to both the rising and falling edges in a DQS), an address 662 (e.g., CA<2:1>) of "00" indicates that output data 524 starts at the first data point in one row of the FIFO cache 700; an address 662 of "00" (e.g., CA<2:1>) of "01" indicates that output data 524 starts at the third data point in that row; an address 662 of "00" (e.g., CA<2:1>) of "10" indicates that output data 524 starts at the fifth data point in that row; and an address 662 of "00" (e.g., CA<2:1>) of "11" indicates that output data 524 starts at the seventh data point in that row.

[0059] The read address shifter 606 can determine the shifted address 666 by subtracting the number of warm-up cycles (e.g., wu_do<1:0>) from the address (e.g., CA<2:1>) 662. As in the example shown in Figure 7, the output data 524 starts from the fifth data point in the row of the FIFO cache 700, where, for example, CA<2:1> is "10". If there are two warm-up cycles before the data output cycle (e.g., wu_do<1:0> is "10"), then the shifted address 666 (e.g., shifted CA<2:1>) is "00", meaning the warm-up data 522 starts from the first data point in the row of the FIFO cache 700. In some implementations, the output pointer 702 of the FIFO cache 700 can be shifted to the location indicated by the shifted address 666, thereby allowing the data output process 500 from the FIFO cache 700 to start at the shifted address 666. Thus, once the warm-up cycle is complete, the output pointer 702 can point to address 662 of the output data 524.

[0060] In several implementations, the FIFO cache 700 can have different configurations, and the read address shifter 606 can determine the shifted address in different ways.

[0061] Figure 8 shows an example of a lookup table 800 for a shifted address 666 (e.g., shifted CA<2:1>) based on the address 662 (e.g., CA<2:1>) and the number of warm-up cycles 664 (e.g., wu_do<1:0>) of the output data 524, according to some aspects of the present disclosure. In some cases, the difference between the column address CA<2:1> and the number of warm-up cycles wu_do<1:0> is a negative value, as indicated by the gray cells in the lookup table 800. In such cases, the read address shifter 606 can take the negative value into consideration when determining the shifted address 666. For example, if CA<2:1> is "00" and wu_do<1:0> is "01", the shifted column address will be "11". That is, the warm-up data 522 starts from the 7th data point in the row of the FIFO cache 700. Furthermore, the read address shifter 606 can send a control signal 668 to the frequency divider 644, which controls the output pointer 702 to remain on the same row. In some implementations, the control signal 668 can instruct the output pointer 702 to skip the first rising edge of the fourth read clock signal (rd_clk_x4) generated by the frequency divider 644. In this way, if the output pointer 702 moves to the end of a row in the FIFO cache 700 instead of the beginning of the next row, the output pointer 702 moves to the beginning of the same row. This ensures that once the warm-up cycle is complete, the output pointer 702 can accurately point to address 662 of the output data 524.

[0062] In some implementations, the frequency divider 644 may include four D flip-flops. The D flip-flops can generate signals that mimic the clock signal used to output warm-up data 522 during the warm-up cycle 512. For example, the signals generated by each D flip-flop may have the same frequency but different phases. Adjacent D flip-flops may have a phase difference of 90 degrees from each other.

[0063] Figure 9 shows a flowchart of an example of a process 900 for fetching data from an output buffer according to some aspects of the present disclosure. In some implementations, the I / O interface 416 can use four pulses to fetch data from an output buffer (e.g., the FIFO cache 700 in Figure 7) before outputting data to the memory controller. The process 900 can support warm-up operation by outputting warm-up data 522 during a warm-up cycle 512 prior to the data output cycle 514.

[0064] Before the first pulse, the I / O interface read address shifter 606 can generate a shifted address (e.g., shifted CA<2:1>) 666 based on address 662 (e.g., CA<2:1>) and warm-up cycle number 664 (e.g., wu_do<1:0>). The shifted address 666 can be the starting address of the warm-up data 522 to be read during the warm-up cycle 512.

[0065] In 902, during the first pulse, the I / O interface 416 resets the read clock (e.g., the first read clock signal 612 (rd_clk_x1) in Figure 6) and resets the data path (e.g., DQ<7:0> in Figure 5).

[0066] In 904, during the second pulse, the I / O interface 416 has the fourth least significant bit in the column address (e.g., CA) <3> ) fetches data (for example, from FIFO cache 700) based on ). In some implementations, CA <3> This can instruct the system to select either the first eight data points or the last eight data points from a given set of 16 data points in the FIFO cache 700. During the second pulse, the eight selected data points are fetched.

[0067] In 906, during the third pulse, the I / O interface 416 is the third least significant bit in the column address after the address shift (e.g., CA <2> Based on this, data is fetched (for example, from the FIFO cache 700 or another buffer that stores the eight data points fetched during the second pulse). In some implementations, CA <2> This allows you to specify whether to select the first four data points or the last four data points from the eight selected data points. During the third pulse, the four selected data points are fetched.

[0068] In 908, during the fourth pulse, the I / O interface 416 reads the second least significant bit in the column address after the address shift (e.g., CA <1> Based on this, data is fetched (for example, from the FIFO cache 700 or another buffer that stores the four data points fetched during the third pulse). In some implementations, CA <1> This can be used to instruct whether to select the first two or last two data points from the four selected data points. During the third pulse, the two selected data points are ready to be fetched and output via the DQ<7:0> data line.

[0069] In some implementations, process 900 is applied to outputting data in response to read commands from the memory controller. In some implementations, process 900 is also applied to resumed data output after a read pause, thereby including a warm-up cycle before the resumed data output. In such cases, before 902, either the chip enable signal (CE_n), the command latch enable signal (CLE), or the address latch enable signal (ALE) is set high to indicate a read pause. The read address shifter 606 can calculate a shifted address for the warm-up data at the start of the resumed data output, for example, based on the address of the data to be read again and the number of warm-up cycles. Similarly, the I / O interface 416 can use four pulses (as described with reference to 902, 904, 906, and 908, for example) to fetch data from the output buffer, resulting in the output of warm-up data at the start of the resumed data output.

[0070] Figure 10 illustrates an example of a method 1000 for reading data from a memory system (e.g., the memory system 102 in Figure 1) according to several aspects of the present disclosure. Method 1000 can be performed according to the exemplary techniques described with respect to Figures 1 to 9. The memory system may include a memory controller (e.g., the memory controller 106 in Figure 1) and a memory device (e.g., the memory device 104 in Figure 1). The memory device may include a memory cell array (e.g., the memory cell array 301 in Figure 3) and an I / O interface (e.g., the I / O interface 416 in Figures 4 and 6).

[0071] In 1002, the memory controller sends a read command to the I / O interface of the memory device. The read command may include the first address (e.g., column address 662) of the data to be read in response to the read command.

[0072] In 1004, in order to increase the speed of data transmission, the data is first read from the memory cell array into the I / O interface's FIFO cache (for example, FIFO cache 700 in Figure 7) before it is output from the I / O interface to the memory controller.

[0073] In 1006, the I / O interface's read address shifter (e.g., read address shifter 606 in Figure 6) shifts the first address to the second address. In some implementations, the read address shifter can receive inputs including the first address and the number of warm-up cycles prior to the data output cycle. The read address shifter can calculate the second address by subtracting the number of warm-up cycles from the first address. Thus, the second address can be the starting address of the warm-up data output during the warm-up cycle (e.g., warm-up data 522 in Figures 4 and 7). In some implementations, in response to the determination that the result of subtracting the number of warm-up cycles from the first address is a negative value (e.g., as shown in Figure 8), the read address shifter can consider negative values ​​when determining the second address.

[0074] In 1008, the memory device transmits data to the memory controller via the I / O interface. In some implementations, the I / O interface can fetch data from the FIFO cache using four pulses, as shown in Figure 9. The data line DQ[7:0] has its first address shifted to the second address by the read address shifter, so during the warm-up cycle, it first outputs warm-up data starting from the second address, and then outputs data starting from the first address. In some implementations, data starting from the first address is transmitted to the memory controller via the I / O interface.

[0075] The steps shown in Method 1000 do not have to be exhaustive, and other steps can be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from that shown in Figure 10. In some implementations, some of the steps may be performed by one or more components of a device or system, such as peripheral circuits for a memory device.

[0076] Figure 11 illustrates a flowchart of an exemplary process 1100 that performs a read operation including a warm-up cycle (e.g., a warm-up cycle 512 preceding the data output cycle 514 in Figure 5), relating to several aspects of the present disclosure. Process 1100 can be performed by any suitable device or system described herein, for example, in accordance with the exemplary techniques described with respect to Figures 1 to 10. For example, process 1100 can be performed by a memory device (e.g., memory device 104 in Figures 1-2B, or memory device 300 in Figure 3, which includes a memory cell array 301), by the I / O interface of a memory device (e.g., the I / O interface 416 in Figures 4 and 6), or by a memory system (e.g., memory system 102 in Figure 1).

[0077] In 1102, the first address (e.g., address 662) of the first data to be read during the read operation (e.g., output data 524 in Figures 5 and 7) is received. In some implementations, the first address may include the second and third least significant bits (e.g., CA<2:1>) of the full column address of the first data (e.g., CA<13:0>).

[0078] At 1104, warm-up information is received. The warm-up information may include warm-up configuration information indicating the warm-up period before reading the first data (e.g., including the warm-up cycle 512 in Figure 5). In some implementations, the warm-up period may include the number of warm-up cycles before reading the first data (e.g., 1, 2, or 4 warm-up cycles).

[0079] In 1106, the second address (e.g., the shifted address 666 in Figure 6) of the second data to be read during the warm-up period (e.g., the warm-up data 522 in Figures 5 and 7) can be determined based on the first address and the number of warm-up cycles during the warm-up period (e.g., the number of warm-up cycles 664 in Figure 6). In some implementations, the second address can be determined by subtracting the number of warm-up cycles from the first address, for example, as shown in the look-up table 800 in Figure 8.

[0080] In some implementations, the second address is received by a first frequency divider (e.g., frequency divider 644 in Figure 6) of a frequency divider circuit (e.g., frequency divider 604 in Figure 6). The first frequency divider can generate a second clock signal (e.g., a fourth read clock signal (rd_clk_x4)) having a frequency of 1 / 4 of the frequency of the first clock signal, based on a first clock signal (e.g., a first read clock signal (rd_clk_x1)). In some implementations, the second address is determined by considering negative values ​​in response to the determination that the first address minus the number of warm-up cycles is a negative value (e.g., as shown in the gray cell of lookup table 800). For example, an address shifter (e.g., a read address shifter 606 in Figure 6) can transmit a control signal (e.g., a control signal 668 in Figure 6) to the first frequency divider. The control signal is configured to instruct the output pointer of the FIFO cache (e.g., FIFO cache 700 in Figure 7) (e.g., output pointer 702 in Figure 7) to skip the first rising edge of the second clock signal during the warm-up period.

[0081] In 1108, data is read or output, for example, via DQ<7:0> starting from a second address. As shown in Figure 5, in response to the RE_n signal and the corresponding DQS signal, the second data is read during a warm-up cycle 512, starting from the second address. After the warm-up cycle, the first data is read from the first address during a data output cycle 514. Thus, a warm-up cycle is provided before outputting the first data, improving the integrity and accuracy of the data when outputting the first data. In some implementations, either or both of the first or second data are sent from the memory device to the memory controller via an I / O interface, for example.

[0082] The steps shown in process 1100 are not exhaustive, and other steps may be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from that shown in Figure 11. In some implementations, some of the steps may be performed by one or more components of a device or system, such as peripheral circuits for a memory device.

[0083] Figure 12 illustrates a schematic timing diagram 1200 of an example of read pause and resume according to several aspects of the present disclosure. The timing diagram 1200 includes signals such as the chip enable signal (CE_n), command latch enable signal (CLE), address latch enable signal (ALE), read enable signal (RE_t), and data strobe signal (DQS_t). To indicate a read pause, one of CE_n, CLE, or ALE may be held high for longer than a threshold duration (e.g., 1us). According to the Open NAND flash Interface (ONFi) specification, the time to resume data output after a read pause must be less than 45ns. Specifically, the duration for resuming data output should be less than the sum of (1) tCHZ (the time CE_n goes high and outputs Hi-Z) or tCLHZ (the time CLE goes high and outputs Hi-Z), which can last up to 30 ns; (2) tBDS (the time DQS_t is high and RE_t is high to set ALE, CLE, or CE_n low), which can last up to 5 ns; and (3) tCR (the time delay from when CE_n is set low until RE_t is set low) or tCLR (the time delay from when CLE is set low until RE_t is set low), which can last up to 10 ns.

[0084] In some implementations, a warm-up cycle is provided at the start of resumed data output. The I / O interface may use four pulses, as shown in Figure 9, to fetch data from the output buffer (e.g., FIFO cache 700 in Figure 7) and output the data before resuming, so that the data line DQ[7:0] can output warm-up data for the first time during the warm-up cycle. In some implementations, by including four pulses at the start of resumed data output, the duration for resuming data output is still less than 45 ns, thereby complying with the relevant protocols of the ONFi specification.

[0085] This specification includes many specific details of implementation, but these should not be interpreted as limitations on the scope of what can be claimed, but rather as descriptions of features that may be specific to a particular implementation. Certain features described herein in the context of separate implementations may be combined and implemented in a single implementation. Conversely, various features described in the context of a single implementation may be implemented separately or in any subcombination in multiple implementations. Furthermore, the aforementioned features may be described as acting in a particular combination and may be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from that combination, and the claimed combination may cover a partial combination or a variation of a partial combination.

[0086] Where used in this disclosure, the terms “a,” “an,” or “the” are used to include one or more than one unless otherwise explicitly indicated by the context. The term “or” is used to refer to a non-exclusive “or” unless otherwise specified. The statement “at least one of A and B” is synonymous with “A, B, or A and B.” Furthermore, any expressions or terms used in this disclosure, which are not otherwise defined, are for illustrative purposes only and not for limitation. The use of section headings is intended to aid in the reading of the document and should not be construed as limiting. Information related to section headings may occur inside or outside that particular section.

[0087] Where used in this disclosure, the terms “about” or “approximately” may allow for some variation in a value or range, for example, within 10%, 5%, or 1% of the stated limit of the stated value or range.

[0088] As used in this disclosure, the term “substantially” means a majority or almost the entirety, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0089] Values ​​expressed in range format should be interpreted flexibly to include not only the numbers explicitly listed as range limits, but also all individual numbers or subranges contained within that range, as if each number and subrange were explicitly listed. For example, the range "0.1% to approximately 5%" or "0.1% to 5%" should be interpreted to include approximately 0.1% to approximately 5%, as well as the individual values ​​within the indicated range (e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, and 3.3% to 4.4%). "X to Y" is synonymous with "approximately X to approximately Y" unless otherwise specified. Similarly, the notation "X, Y, or Z" is synonymous with "approximately X, approximately Y, or approximately Z" unless otherwise specified.

[0090] A specific implementation of the subject matter has been described. Other implementations, modifications, and substitutions of the described implementations are within the scope of the following claims, as will be obvious to those skilled in the art. Although the operations are shown in a specific order in the drawings or claims, such operations do not need to be performed in the specific order or sequential order shown, or not all of the operations shown need to be performed (some operations may be considered optional). In certain circumstances, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be performed in a manner that is considered advantageous and appropriate.

[0091] Furthermore, the separation or integration of various system modules and components in the aforementioned implementation forms is not required in all implementation forms, and the described components and systems can generally be integrated together or packaged into multiple products.

[0092] Therefore, the exemplary implementations described above do not define or limit this disclosure. Other modifications, substitutions, and variations are possible without departing from the intent and scope of this disclosure.

Claims

1. Receive the first address of the first data to be read, Warm-up information indicating the warm-up period before reading the first data is received, Based on the first address and the warm-up information, a second address of the second data to be read during the warm-up period before reading the first data is determined. An input / output (I / O) interface for a memory device, configured in such a way.

2. The I / O interface comprises an address shifter and a first frequency divider coupled to the address shifter, and the address shifter is The second address is determined by subtracting the number of warm-up cycles from the first address. The second address is transmitted to the first frequency divider. The I / O interface according to claim 1, configured as described above.

3. The address shifter mentioned above is In response to the determination that the difference between the first address and the number of warm-up cycles is a negative value, the negative value is taken into consideration when determining the second address. The I / O interface according to claim 2, configured as described above.

4. The I / O interface according to claim 3, wherein the I / O interface receives a first clock signal, and the first frequency divider is configured to generate a second clock signal having a frequency of 1 / 4 of the frequency of the first clock signal.

5. The I / O interface according to claim 4, wherein the first data and the second data are read from the first-in, first-out (FIFO) cache of the memory device.

6. The I / O interface according to claim 5, wherein the address shifter is configured to take the negative value into consideration when determining the second address by transmitting a control signal to the first frequency divider, and the control signal is configured to instruct the output pointer of the FIFO cache to skip the first rising edge of the second clock signal during the warm-up period.

7. A second frequency divider configured to generate a third clock signal having half the frequency of the first clock signal, A third frequency divider configured to generate a fourth clock signal having a frequency of 1 / 8 of the frequency of the first clock signal, An I / O interface according to any one of claims 4 to 6, comprising:

8. In response to receiving a read command for reading the first data, During the first pulse, reset the data path of the I / O interface. During the second pulse, read the data based on the fourth least significant bit of the second address. During the third pulse, read the data based on the third least significant bit of the second address. During the fourth pulse, read the data based on the second least significant bit of the second address. An I / O interface according to any one of claims 1 to 7, configured as described above.

9. After a pause in reading, in response to receiving a read resume command to read the first data, During the first pulse, reset the data path of the I / O interface. During the second pulse, read the data based on the fourth least significant bit of the second address. During the third pulse, read the data based on the third least significant bit of the second address. During the fourth pulse, read the data based on the second least significant bit of the second address. An I / O interface according to any one of claims 1 to 8, configured as described above.

10. During the aforementioned warm-up period, the second data is output. The first data is output after the warm-up period. An I / O interface according to any one of claims 1 to 9, configured as described above.

11. A memory cell array comprising memory cells, A peripheral circuit coupled to the aforementioned memory cell array, Receive the first address of the first data to be read, Warm-up information indicating the warm-up period before reading the first data is received, Based on the first address and the warm-up information, a second address of the second data to be read during the warm-up period before reading the first data is determined. Peripheral circuits and an input / output (I / O) interface configured as follows: A memory device equipped with the following features.

12. The I / O interface comprises an address shifter and a first frequency divider coupled to the address shifter, and the address shifter is The second address is determined by subtracting the number of warm-up cycles from the first address. The second address is transmitted to the first frequency divider. The memory device according to claim 11, configured as described above.

13. The address shifter mentioned above is In response to the determination that the difference between the first address and the number of warm-up cycles is a negative value, the negative value is taken into consideration when determining the second address. The memory device according to claim 12, configured as described above.

14. The memory device according to claim 13, wherein the peripheral circuit includes a first-in, first-out (FIFO) cache, and the first data and the second data are read from the FIFO cache.

15. The I / O interface receives a first clock signal. The first frequency divider is configured to generate a second clock signal having a frequency of 1 / 4 of the frequency of the first clock signal. The address shifter is configured to take the negative value into consideration when determining the second address by transmitting a control signal to the first frequency divider. The control signal is configured to instruct the output pointer of the FIFO cache to skip the first rising edge of the second clock signal during the warm-up period. The memory device according to claim 14.

16. The aforementioned peripheral circuitry is During the aforementioned warm-up period, read the second data, After the warm-up period, read the first data. A memory device according to any one of claims 11 to 15, configured as described above.

17. The memory device according to any one of claims 1 to 16, wherein the memory device comprises a NAND memory device.

18. It is a memory system, A memory controller configured to transmit a read command for reading first data, a first address of the first data, and warm-up information indicating a warm-up period before reading the first data, A memory device coupled to the memory controller The memory device comprises, A memory cell array comprising memory cells, The read command, the first address, and the warm-up information are received. Based on the first address and the warm-up information, a second address of the second data to be read during the warm-up period before reading the first data is determined. A peripheral circuit is provided, which has an input / output (I / O) interface configured as follows: Memory system.

19. Determining the second address is The second address is determined by subtracting the number of warm-up cycles from the first address. The memory system according to claim 18, including the following:

20. The aforementioned peripheral circuitry is During the aforementioned warm-up period, read the second data, After the warm-up period, read the first data array. The memory system according to claim 18 or 19, configured as described above.

Images