Gaming Machines

Abstract

To provide a game machine that can be manufactured suitably.SOLUTION: A substrate 002AK01 includes substrate-side-connectors AC01, AC02 that make signal transmission possible. A harness includes a harness-side-connector and a plurality of wiring systems connectable to the substrate-side-connectors AC01, AC02. A harness-side-connector and the substrate-side-connectors AC01, AC02 are commonly colored. Some wiring systems among the plurality of wiring systems included in the harness are specifically colored, and the wiring systems other than the some wiring systems are colored differently from the specific color. In the substrate 002AK01, color name information AB01, which corresponds to red, is indicated near the substrate-side connector AC01, and color name information AB02, which corresponds to blue, is indicated near the substrate-side connector AC02.SELECTED DRAWING: Figure 12-2

Description

[Technical field]

[0001] The present invention relates to a gaming machine capable of playing a game. [Background technology]

[0002] There has been proposed a gaming machine that can prevent incorrect wiring by configuring components with different colors (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-300015 A Summary of the Invention [Problem to be solved by the invention]

[0004] The technology described in Patent Document 1 could lead to difficulties in procuring parts, which could cause problems in the manufacture of gaming machines.

[0005] The present invention has been made in consideration of the above circumstances, and has an object to provide a gaming machine that can be appropriately manufactured. [Means for solving the problem]

[0006] In order to achieve the above object, the gaming machine according to the present invention is a gaming machine capable of playing a game (e.g., a pachinko gaming machine 1), and includes a board (e.g., board 002AK01, etc.) on which connectable members (e.g., board side connectors AC01, AC02, etc.) that enable signal transmission are arranged, and a harness (e.g., The connecting member and the connected member have a common color (e.g., white), and among a plurality of wires included in the harness, some of the wires (e.g., wires AH01, AH21, etc.) have a specific color (e.g., red or blue), and the wires other than the some of the wires (e.g., wires AH02 to AH10, AH22 to AH31, etc.) have a color different from the specific color (e.g., white), and teeth, Color designation information corresponding to the specific color (e.g., color name information AB01, AB02, etc.) and identification information relating to the connected member; is written The color designation information corresponding to the specific color is written in a larger size than the identification information regarding the connected member. Such a configuration allows for proper manufacturing. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a front view of the pachinko game machine. [Diagram 2] FIG. 2 is a configuration diagram showing various control boards, etc. [Diagram 3] FIG. 13 is a diagram showing an example of a random number for gaming. [Figure 4] 13 is a flowchart showing a main process for game control. [Diagram 5] 13 is a flowchart showing an example of a timer interrupt process for game control. [Figure 6] 13 is a flowchart showing an example of a special symbol process. [Figure 7] A diagram showing an example of the configuration of a special pattern process processing jump table. [Figure 8] 13 is a flowchart showing a main process for performance control. [Figure 9] 13 is a flowchart showing an example of a performance control process. [Figure 10-1] FIG. 2 is a diagram showing an example of the configuration of a microcomputer for game control. [Figure 10-2] FIG. 13 is a diagram illustrating an example of an address map. [Figure 10-3] 11A and 11B are diagrams showing main setting examples of addresses included in a function setting register area; [Figure 10-4] 11 is a diagram showing an example of main settings of addresses included in a function control register area; FIG. [Figure 10-5] A diagram for explaining an example of settings for random numbers for gaming. [Figure 10-6] FIG. 13 is a diagram for explaining a random number update period. [Figure 10-7] 10 is a flowchart illustrating an example of a power supply start response process. [Figure 10-8] FIG. 13 is a diagram illustrating an example of a configuration of a function setting register stored value table. [Figure 10-9] 13 is a diagram illustrating an example of the configuration of an RWM access protection register; [Figure 10-10] 10 is a flowchart illustrating an example of a power-off process. [Figure 10-11] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-12] 13 is a flowchart illustrating an example of a random number update process. [Figure 10-13] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-14] 13 is a flowchart illustrating an example of an initial value changing random number updating process. [Figure 10-15] 13 is a flowchart showing an example of an initial value determination random number update process. [Figure 10-16] 13 is a flowchart showing an example of a start port switch passing process. [Figure 10-17] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-18] 13 is a flowchart showing an example of normal special symbol processing. [Figure 10-19] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-20] 13 is a flowchart showing an example of a special pattern determination process. [Figure 10-21] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-22] 13 is a flowchart showing an example of a special symbol information setting process. [Figure 10-23] A flowchart showing an example of a jackpot information data selection process. [Figure 10-24] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-25] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-26] 13 is a flowchart showing an example of a variation pattern setting process. [Figure 10-27] 11 is a flowchart showing an example of a winning time fluctuation pattern type table selection process. [Figure 10-28] 11 is a flowchart showing an example of a process for selecting a fluctuation pattern type table when a loss occurs. [Figure 10-29] A diagram for explaining an example of the configuration of a fluctuation pattern type allocation table. [Figure 10-30] 13 is a diagram for explaining an example of the configuration of a fluctuation pattern allocation table. FIG. [Figure 10-31] 13 is a diagram for explaining an example of the configuration of a fluctuation pattern allocation table. FIG. [Figure 10-32] 13 is a diagram for explaining an example of the configuration of a fluctuation pattern allocation table. FIG. [Figure 10-33] 13 is a flowchart showing an example of normal symbol process processing. [Figure 10-34] FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 10-35] 13 is a flowchart showing an example of a gate switch passing process. [Figure 10-36] 13 is a flowchart showing an example of normal processing of normal symbols. [Figure 10-37]FIG. 13 is a diagram for explaining an example of use of a data configuration. [Figure 11-1] FIG. 2 is a diagram showing a memory area of ​​a ROM. [Figure 11-2] FIG. 13 is a diagram illustrating an example of setting unused data. [Figure 11-3] FIG. 13 is a diagram illustrating an example of the configuration of a RST command. [Figure 11-4] FIG. 2 is a diagram illustrating an example of a description of a program module. [Figure 11-5] FIG. 11 illustrates an example of how table data is stored. [Figure 11-6] FIG. 13 is a diagram illustrating an example of setting zero data. [Figure 11-7] FIG. 11 illustrates an example of how table data is stored. [Figure 11-8] FIG. 13 is a diagram illustrating an example of an output of a dump list. [Figure 12-1] FIG. 2 is a schematic diagram showing the appearance of a substrate. [Figure 12-2] 11 is an explanatory diagram showing an example of board-side connectors, color name information, etc. [Figure 12-3] FIG. 2 is an explanatory diagram showing an example of electronic components and component information. [Figure 12-4] 2 is a schematic diagram showing a harness side connector, a plurality of wires, and the like of the harness. FIG. [Figure 12-5] 1 is an explanatory diagram showing an example of a board-side connector, part information, a harness, etc.; [Figure 12-6] 11 is an explanatory diagram showing an example of board-side connectors and part information. FIG. [Figure 12-7] 13A and 13B are explanatory diagrams showing modified examples of the board-side connector. [Figure 12-8] 13A and 13B are explanatory diagrams showing modified examples of the board-side connector. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] (Basic explanation) First, the basic configuration and control of the pachinko gaming machine 1 will be described.

[0009] (Configuration of Pachinko Machine 1, etc.) Fig. 1 is a front view of a pachinko gaming machine 1, showing the layout of the main components. The pachinko gaming machine (gaming machine) 1 is broadly composed of a gaming board (gauge board) 2 that constitutes the gaming board surface, and a gaming machine frame (base frame) 3 that supports and fixes the gaming board 2. A gaming area is formed on the gaming board 2, and gaming balls as gaming media are shot into this gaming area by a predetermined ball shooting device.

[0010] A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions on the game board 2. In the example shown in FIG. 1, they are provided on the right side of the game area. The first special symbol display device 4A and the second special symbol display device 4B can each perform variable display of special symbols as multiple types of special identification information. The special symbols are also called "special symbols." The variable display of special symbols is also called "special symbol game." Both the first special symbol display device 4A and the second special symbol display device 4B are configured using 7-segment LEDs or the like. The special symbols are represented by numbers indicating "0" to "9," symbols indicating "-," or other arbitrary lighting patterns. The special symbols may include a pattern in which all LEDs are turned off.

[0011] The "variable display" of the special pattern means, for example, displaying multiple types of special patterns in a variable manner. For other patterns such as performance patterns, small patterns, and normal patterns, "variable display" also means displaying multiple types of patterns in a variable manner. Performance patterns are also called decorative patterns or ornamental patterns. Variable display is also called variable display, or simply "variation." Variations include updating multiple patterns, scrolling multiple patterns, and deforming, enlarging, and reducing one or more patterns. Variations may include a mode of displaying a pattern in a flashing manner. In the variable display of special patterns and normal patterns, multiple types of special patterns or normal patterns are displayed in a variable manner. In the variable display of performance patterns, multiple types of performance patterns are scrolled or updated, or one or more performance patterns are deformed, enlarged, or reduced. In the variable display of any pattern, a predetermined pattern is stopped and displayed as a display result at the end. Stop display is also called derived display, or simply derived. The symbol that is finally stopped and displayed in a variable display is also called a final stop symbol or a confirmed symbol. The final stop symbol in a special symbol game is also called a confirmed special symbol. The display result of the variable display includes the display result of the special symbol, and is also called a variable display result. The display result of the special symbol is also called a special symbol display result. The execution time of the variable display includes the special symbol change time, which is the change time of the special symbol, and is also called a variable display time. The special symbol change time can be set to a different time corresponding to the change pattern of the special symbol, of which multiple patterns are prepared in advance.

[0012] The special pattern variably displayed on the first special pattern display device 4A is also called the "first special pattern." The special pattern variably displayed on the second special pattern display device 4B is also called the "second special pattern." A special pattern game using the first special pattern is also called the "first special pattern game." A special pattern game using the second special pattern is also called the "second special pattern game." There may be only one type of special pattern display device that variably displays special patterns.

[0013] A normal symbol display 20 is provided at a predetermined position on the game board 2. In the example shown in FIG. 1, it is provided on the left side of the game area. The normal symbol display 20 can perform variable display of normal symbols as multiple types of normal identification information different from special symbols. The normal symbol is also called "normal symbol". The variable display of the normal symbol is also called "normal symbol game". The normal symbol display 20 is configured using 7-segment LEDs, etc. The normal symbol is represented by numbers indicating "0" to "9", symbols indicating "-", and other arbitrary lighting patterns. The normal symbol may include a pattern in which some or all of the multiple LEDs are lit, or a pattern in which all of the multiple LEDs are turned off. The final stop symbol in the normal symbol game is also called a confirmed normal symbol. The display result of the normal symbol is also called a normal symbol display result. The execution time during which the normal symbol is variably displayed in the normal symbol game is also called a normal symbol fluctuation time. The normal symbol variation time can be set to a different time in accordance with the normal symbol variation pattern, of which multiple patterns are prepared in advance.

[0014] An image display device 5 is provided near the center of the play area on the game board 2. The image display device 5 may be configured using a mechanism capable of forming any image, such as an LCD (liquid crystal display device), an organic EL (Electro Luminescence), a dot matrix LED, a projector and screen, a stereoscopic image projection device, or any other device. The image display device 5 is capable of displaying various types of performance images. Furthermore, the image display device 5 is not limited to performance images, and can display any control-related image, such as an inspection image or a setting image.

[0015] For example, on the screen of the image display device 5, a variable display of the performance symbols can be executed in synchronization with the first special symbol game or the second special symbol game. The performance symbols are display symbols showing numbers or the like, and are multiple types of decorative identification information different from the special symbols and the normal symbols. On the screen of the image display device 5 shown in FIG. 1, the performance symbol display areas 5L, 5C, and 5R of "left", "middle", and "right" are provided, and the performance symbols are displayed in a vertical scroll display or updated display in synchronization with the first special symbol game or the second special symbol game, for example, to perform the variable display of the performance symbols. The synchronization of the variable display may be such that the timing at which the variation of the symbols starts and the timing at which the variation ends and the symbols are finally stopped and displayed are common timing for different types of symbols. The final stop symbol in the variable display of the performance symbols is also called the determined performance symbol, determined decoration symbol, or determined decoration symbol. The variable display of the performance pattern is synchronized with the first special pattern game and the second special pattern game, so the variable display time of the performance pattern is the same as the special pattern change time.

[0016] A display area capable of displaying performance images corresponding to the reserved display and the active display may be provided on the screen of the image display device 5. The reserved display is a display corresponding to a variable display that has not yet been executed and is reserved. The active display is a display corresponding to a variable display that is being executed. The reserved display and the active display are also collectively referred to as a variable display-compatible display corresponding to the variable display. A display area that performs the reserved display is also referred to as a reserved display area. A display area that performs the active display is also referred to as an active display area. The number of reserved variable displays is also referred to as the reserved memory number. The reserved memory number corresponding to the first special game is also referred to as the first reserved memory number. The reserved memory number corresponding to the second special game is also referred to as the second reserved memory number. The sum of the first reserved memory number and the second reserved memory number is also referred to as the total reserved memory number.

[0017] A first reserved indicator 25A and a second reserved indicator 25B, each of which includes a plurality of LEDs, are provided above the first special symbol display device 4A and the second special symbol display device 4B shown in FIG. 1. The first reserved indicator 25A displays the first reserved memory number by the number of lit LEDs. The second reserved indicator 25B displays the second reserved memory number by the number of lit LEDs. A regular reserved indicator 25C, each of which includes a plurality of LEDs, is provided above the regular symbol display device 20 shown in FIG. 1. The regular reserved indicator 25C displays the regular reserved memory number by the number of lit LEDs. The regular reserved memory number is the reserved memory number corresponding to the regular game.

[0018] Below the image display device 5, a winning ball device 6A and a variable winning ball device 6B are provided. The winning ball device 6A forms a first start winning opening that is always kept in a constant open state so that game balls can enter, for example, by a predetermined ball receiving member. The variable winning ball device 6B forms a second start winning opening that can be changed between a closed state and an open state by a normal electric role solenoid 81 shown in FIG. 2 as a normal electric role. The variable winning ball device 6B is provided with, for example, an electric tulip-type role having a pair of movable wings, and when the normal electric role solenoid 81 is in an off state, the movable wings are in a vertical position, so that the second start winning opening is in a closed state in which game balls cannot enter, or in a normal open state in which game balls are unlikely to enter. When the normal electric accessory solenoid 81 is on, the variable winning ball device 6B has the movable wing piece in a tilted position, so that the second start winning port is in an open state where the game ball can enter, or in an expanded open state where the game ball can easily enter the second start winning port. The open state where the game ball can enter the second start winning port, or the expanded open state where the game ball can easily enter, is also called the first variable state. The closed state where the game ball cannot enter the second start winning port, or the normal open state where the game ball cannot easily enter, is also called the second variable state. The variable winning ball device 6B is not limited to one having an electric tulip-type accessory, as long as it can be changed between the first variable state and the second variable state.

[0019] The entry of a game ball into the first start winning hole formed by the winning ball device 6A is also called the first start winning. The entry of a game ball into the second start winning hole formed by the variable winning ball device 6B is also called the second start winning. The game ball that entered the first start winning hole is detected by the first start winning hole switch 22A shown in FIG. 2. The game ball that entered the second start winning hole is detected by the second start winning hole switch 22B shown in FIG. 2. Based on the occurrence of the first start winning, a predetermined number of prize balls, for example, three balls, are paid out, and the first reserved memory number can be updated so that it is incremented by one. However, if the first reserved memory number has reached the upper limit number, the first reserved memory number is not updated even if the first start winning occurs. In response to the case where the first reserved memory number is incremented by one, the first start condition is established, and the first special symbol game in which the special symbol is variably displayed by the first special symbol display device 4A becomes executable. Based on the occurrence of the second start winning, a predetermined number of prize balls, for example, 3 balls, are paid out, and the second reserved memory count can be updated so as to increment by 1. However, if the second reserved memory count has reached the upper limit, the second reserved memory count is not updated even if the second start winning occurs. In response to the second reserved memory count being incremented by 1, the second start condition is established, and the second special symbol game in which the special symbol is variably displayed by the second special symbol display device 4B becomes executable.

[0020] A general winning opening 10 that is always kept in a constant open state by a predetermined ball receiving member is provided at a predetermined position on the game board 2. In the example shown in Fig. 1, the general winning openings 10 are provided at two locations on the lower left of the game area. When a game ball enters one of the general winning openings 10, a predetermined number of prize balls, for example 10, are paid out.

[0021] In the game area formed by the game board 2, a first path and a second path are provided as flow paths through which game balls flow down. The first path is mainly provided in an area to the left of the image display device 5 when viewed from the front. The second path is mainly provided in an area to the right of the image display device 5 when viewed from the front. The left area of ​​the image display device 5 is also called the left game area or the left game area. The right area of ​​the image display device 5 is also called the right game area or the right game area. The left game area and the right game area may be divided, for example, by the end face of the image display device 5 in the game area or the arrangement of game nails. Firing a game ball toward the left game area to make it flow down the first path is also called a left hit. Firing a game ball toward the right game area to make it flow down the second path is also called a right hit. The first path is also called a left hit path. The second path is also called a right hit path. The first path and the second path may be configured by different paths, or may be a path having a part in common.

[0022] In response to the operation of a ball operation handle provided on the ball launching device, a game ball is launched from the ball launching device and launched into the game area. When the game ball launched into the game area is guided to the left game area and flows down the first path, it is guided, for example, along the array of game nails, making it impossible or difficult to guide to the second path in the right game area. When the game ball launched into the game area is guided to the right game area and flows down the second path, it is guided, for example, along the array of game nails, making it impossible or difficult to guide to the first path in the left game area.

[0023] The winning ball device 6A is provided on a first path in the left game area, and game balls flowing down the first path can enter. The variable winning ball device 6B is provided on a second path in the right game area, and game balls flowing down the second path can enter. The variable winning ball device 6B may be capable of being entered by game balls flowing down the first path in the left game area. The variable winning ball device 6B may be arranged so that game balls flowing down the second path in the right game area can enter more easily than game balls flowing down the first path in the left game area.

[0024] The second path in the right game area is provided with a passing gate 41 and a special variable winning ball device 50. The passing gate 41 forms a passing area through which the game ball can pass. The game ball that passes through the passing gate 41 is detected by the gate switch 21 shown in FIG. 2. Based on the game ball passing through the passing gate 41, the normal reserved memory number can be added and updated, and the normal pattern display 20 can perform variable display of the normal pattern as a normal pattern game. The passing gate 41 can be configured as a normal pattern operation port through which the game ball can enter. In this case, the gate switch 21 can be configured as a normal pattern operation port switch that can detect the game ball that has entered the normal pattern operation port.

[0025] The special variable winning ball device 50 forms a large winning port that can be changed between a closed state and an open state by a large winning port solenoid 82 as a special electric device. A guide passage having a passage width in the front-rear direction that allows the game ball to pass is formed in the upper part of the special variable winning ball device 50. This guide path is inclined downward from the right side to the left side, and walls are provided on the front side and the back side, which are both sides of the extended passage. A role entrance that serves as the large winning port is formed in the center of the guide passage. In the special variable winning ball device 50, a movable member 52 that can move in the front-rear direction is provided as a large winning port opening and closing member at a position where the large winning port can be opened and closed. In the special variable winning ball device 50, a fixed member 53 that forms a fixed passage is provided in the part of the guide passage where the large winning port is not formed.

[0026] The movable member 52 is driven by the large prize opening solenoid 82, and can move forward and backward to open and close the role entrance which becomes the large prize opening. In the special variable prize ball device 50, the game ball that enters the inside from the large prize opening is detected by the count switch 23. Inside the special variable prize ball device 50, a V prize area 51 which is a specific area is provided as a prize area through which the game ball can pass. In addition, inside the special variable prize ball device 50, a normal area different from the V prize area 51 is provided. At the top of the V prize area 51, a plate-shaped distribution member which can switch the V prize area 51 between an open state and a closed state is provided as a V prize opening opening and closing member. The distribution member is driven by the specific area solenoid 83, and can move forward and backward to open and close the V prize area 51. When the V prize area 51 is in an open state, the game ball can pass through it, and when it is in a closed state, the game ball cannot pass through it. The gaming ball that passes through the V winning area 51 is detected by the specific area switch 24. The gaming ball that does not pass through the V winning area 51 passes through the normal area. The gaming ball that passes through the V winning area 51 and the gaming ball that does not pass through the V winning area 51 but passes through the normal area are both detected by the discharge port switch 26 and then discharged to the outside of the special variable winning ball device 50.

[0027] In addition to the above configuration, the surface of the game board 2 is provided with a windmill that changes the direction and speed of the game balls flowing down, and numerous obstacle nails. At the bottom of the game area, an outlet is provided for game balls that do not enter any of the winning holes. Speakers 8L, 8R for playing and outputting sound effects and the like are provided at the upper left and right positions of the game machine frame 3, and game effect lamps 9 for lighting up the game effects are provided around the periphery of the game area. The game effect lamps 9 are configured to include LEDs. A movable body 32 that operates according to the effects is provided at a predetermined position on the game board 2.

[0028] A ball operation handle is provided at the lower right position of the gaming machine frame 3, which is operated by a player or the like to launch gaming balls toward the playing area by the ball launching device. The ball operation handle is also called an operation knob. At a predetermined position of the gaming machine frame 3 below the playing area, a ball supply tray is provided that holds gaming balls dispensed as prize balls or game balls lent by a predetermined ball lending machine so that they can be supplied to the ball launching device. The ball supply tray is also called the upper tray. Below the upper tray, a prize ball storage tray is provided where prize balls dispensed when the upper tray is full flow down and are stored. The prize ball storage tray is also called the lower tray.

[0029] A stick controller 31A and a push button 31B are provided at a predetermined position of the gaming machine frame 3 below the gaming area. The stick controller 31A can be held by a player and tilted, and is provided with a trigger button that the player can push and pull. An operation on the stick controller 31A is detected by a controller sensor unit 35A shown in FIG. 2. The push button 31B can be pressed by a player. An operation on the push button 31B is detected by a push sensor 35B shown in FIG. 2. In the pachinko gaming machine 1, the stick controller 31A and the push button 31B are used as detection means for detecting an action such as an operation by a player, but other detection means may be used.

[0030] (Outline of game progress) The game ball is launched toward the game area by the player rotating the ball-hitting operation handle provided on the pachinko game machine 1. When the game ball passes through the passing gate 41, the normal game is started by the normal symbol display 20. In addition, when the game ball passes through the passing gate 41 during the period when the previous normal game is being executed, the normal game based on the passage cannot be executed immediately, so the normal game based on the passage is reserved up to a predetermined upper limit number, for example, "4". In the normal game, when a specific normal symbol, such as a normal winning symbol, is stopped and displayed as a confirmed normal symbol, the display result of the normal symbol is "normal winning". In contrast, when a normal symbol other than the normal winning symbol, such as a normal losing symbol, is stopped and displayed as a confirmed normal symbol, the display result of the normal symbol is "normal losing". In the case of "normal winning", an opening control is performed to make the variable winning ball device 6B in an open state or an expanded opening state for a predetermined period. At this time, the second starting winning port is in an open state or an expanded open state.

[0031] When the game ball passes through and enters the first start winning hole formed in the winning ball device 6A, the first special game can be started by the first special pattern display device 4A. When the game ball passes through and enters the second start winning hole formed in the variable winning ball device 6B, the second special game can be started by the second special pattern display device 4B. Note that, during the period when the special pattern game is being executed or during the period when the game ball enters the start winning hole and a start winning occurs, the special pattern game based on the start winning cannot be executed immediately, so the special pattern game based on the start winning is reserved up to a predetermined upper limit number, for example, "4". In the special pattern game, when a specific special pattern such as a jackpot pattern is stopped and displayed as a confirmed special pattern, the display result of the special pattern is "jackpot". In contrast, when a predetermined special pattern, such as a small win pattern, different from a big win pattern, is stopped and displayed as the determined special pattern, the display result of the special pattern is "small win". Also, when a special pattern, such as a miss pattern, different from a big win pattern or a small win pattern, is stopped and displayed as the determined special pattern, the display result of the special pattern is "miss". Furthermore, when a special pattern, such as a time-saving pattern, different from a big win pattern, a small win pattern, or a miss pattern, is stopped and displayed as the determined special pattern, the display result of the special pattern may be "time-saving". The special pattern may not include a time-saving pattern. In other words, the display result of the special pattern may not include "time-saving".

[0032] In the special game, after the display result of the special pattern becomes "jackpot", the game is controlled to a jackpot game state as an advantageous state for the player. In the jackpot game state, the jackpot entry port formed in the special variable winning ball device 50 can be opened in a predetermined manner. The open state at this time continues until the timing of the passage of a predetermined period, such as 29 seconds or 1.8 seconds, or the timing of the number of game balls that have entered the jackpot entry port reaching a predetermined number, whichever comes first. The predetermined period during which the jackpot entry port can be controlled to be in an open state is the upper limit period during which the jackpot entry port can be opened in one round, and is also called the open upper limit period. One cycle during which the jackpot entry port is in an open state in the jackpot game state is called a round or round game. In the jackpot game state, such rounds can be repeatedly executed until a predetermined upper limit number of times is reached, such as 15 times or 2 times. In the jackpot game state, the player can obtain prize balls by entering the game ball into the jackpot entry port. Therefore, the big win gaming state is an advantageous state for the player. The more rounds there are in the big win gaming state, and the longer the upper limit open period, the more advantageous it is for the player.

[0033] When the display result of the special pattern is a "jackpot", it includes multiple jackpot types. For example, the opening mode of the jackpot entry port, such as the number of rounds and the maximum opening period, and the game state after the end of the jackpot game state, such as the normal state, the time-saving state, and the probability change state, are set to multiple different types, and a jackpot type is specified corresponding to each setting. The multiple jackpot types may include some or all of the jackpot types that can get many prize balls, the jackpot types that have few prize balls, or the jackpot types that can hardly get any prize balls, or may include jackpot types with the same amount of prize balls that can be obtained. Controlling to a jackpot game state based on the display result of the special pattern being a "jackpot" is also called a pattern jackpot, a jackpot by a special pattern, a variable display jackpot, or a direct hit jackpot.

[0034] In the special game, after the display result of the special pattern becomes "small hit", the game is controlled to a small hit game state. In the small hit game state, the large winning opening formed in the special variable winning ball device 50 can be opened in a predetermined opening state. For example, in the small hit game state, the large winning opening may be opened in the same opening state as the large winning game state in some large hit types. The large winning opening may be opened in the same opening state by having the same number of openings and opening period. Alternatively, in the small hit game state, the large winning opening may be opened in an opening state different from the large hit game state. As with the large hit type, multiple small hit types may be included even when the display result of the special pattern becomes "small hit". The large hit type and the small hit type are also collectively referred to as the hit type. The operation of opening and closing the large winning opening in the small hit game state is also called the starting operation. In the small win game state, when the special variable winning ball device 50's role entrance, which is the large winning port, is opened and the game ball passes through the V winning area 51 and is detected by the specific area switch 24, the conditions for a big win are met and control to the big win game state is possible. Control to the big win game state based on the occurrence of a V win by the game ball passing through the V winning area 51 in the small win game state is also called a big win via a small win.

[0035] After the jackpot game state ends, the game state can be controlled to a time-saving state or a probability-changing state in accordance with the jackpot type. In addition, in the special pattern game, after the display result of the special pattern becomes "time-saving", the game state is not controlled to the jackpot game state but is controlled to a time-saving state. The time-saving state is a game state in which the second special pattern game by the second special pattern display device 4B is more likely to be executed than in the normal state. A game state in which the second special pattern game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to pass through and enter the second start winning hole than in the normal state. The control of whether or not the game ball is more likely to pass through the second start winning hole is also called base control. The base control in the normal state is also called normal base control or low base control. The base control in the time-saving state includes high base control. In addition to the high base control, the time-saving state may include a medium base control. The medium base control is a base control in which the game ball is more likely to pass through the second start winning hole than the low base control, but is less likely to pass through the second start winning hole than the high base control. The game state in which the medium base control is performed is also called the medium base state. The game state in which the high base control is performed is also called the high base state. The high base control is also called the high opening control.

[0036] In the normal state, the medium base state, and the high base state, the time-saving pattern can be displayed as a stop result of the display of the special pattern. However, in the medium base state and the high base state, even if the time-saving pattern is displayed as a stop result of the display of the special pattern, base control based on the time-saving pattern is not performed, and new control to transition to the medium base state or the high base state is not started. In the time-saving state, time-saving control is possible to shorten the average variable display time more than in the normal state. For this reason, the time-saving state is also called the time-saving state.

[0037] The time-saving state is a state in which the efficiency of fluctuation of special symbols, especially the second special symbol, is improved, and therefore it is included in the special states that are advantageous to players, different from the jackpot game state. When the game state is the probability-changing state, in addition to the time-saving control, the probability-changing control is possible, which makes the probability of the display result of the special symbol being a "jackpot" higher than in the normal state. As a result, the probability-changing state is also called a probability-changing state. The probability-changing state is a state in which the efficiency of fluctuation of the special symbol is improved and in which it is easy to become a "jackpot", and therefore it is included in the special states that are advantageous to players, different from the jackpot game state. The time-saving state and the probability-changing state continue until one of the predetermined end conditions, such as the execution of a predetermined number of special symbol games or the control being made to the next jackpot game state, is met first. The end condition is that the specified number of special symbol games have been executed, and this is also called the number-cutting state. The number-cutting time-cutting state is also called the number-cutting time-cutting state. The number-cutting probability-changing state is also called the number-cutting probability-changing state.

[0038] The normal game state is a game state that is not included in advantageous states such as a big win game state that is advantageous to the player, predetermined states such as a small win game state, and special states such as a time-saving state and a probability change state. The normal state is a game state in which the probability that the display result in the normal game will be a "normal win" and the probability that the display result in the special game will be a "jackpot" are controlled to be the same as the initial setting state of the pachinko game machine 1. The initial setting state of the pachinko game machine 1 is a control state after the initial setting process is performed without performing a predetermined recovery process after power is turned on, such as when a system reset is performed.

[0039] A state in which the probability variable control is being executed is also called a high probability state, and a state in which the probability variable control is not being executed is also called a low probability state. A state in which the time-saving control is being executed is also called a high base state, and a state in which the time-saving control is not being executed is also called a low base state. Combining these, the time-saving state is also called a low probability high base state, the probability variable state is a high probability high base state, and the normal state is a low probability low base state. A high probability state and a low base state are also called a high probability low base state. Note that the pachinko game machine 1 may not include a probability variable state as a game state.

[0040] After the small win game state ends, there are cases where the game state is controlled to a big win game state based on the occurrence of a V win, and cases where the game state before the small win game state is not changed without the occurrence of a V win. However, when the display result of the special game becomes a "small win" and a predetermined number of special games are executed in the number cut, the control of the time-saving state and the probability change state may end and the normal state may be entered. Note that the pachinko game machine 1 may not include a small win game state as a game state. In other words, the display result of the special pattern may not include a "small win".

[0041] When a time-saving condition based on the number of executions of the variable display is established, the game state may be controlled to the time-saving state. Such a time-saving state is also called a rescue time-saving state. The time-saving condition may be a condition that can be established when, after the power is turned on to the pachinko game machine 1, after a jackpot occurs, or after the display result of the special game becomes "time-saving", control to a new jackpot game state or time-saving state is not performed even if a specific number of variable displays are executed.

[0042] (Progress of the performance, etc.) In the pachinko game machine 1, various effects can be executed in accordance with the progress of the game. These effects include effects that notify the progress of the game and effects that liven up the game. These effects include displaying various effect images on the image display device 5, outputting sound effects from the speakers 8L and 8R, turning on the game effect lamp 9, operating the movable body 32, vibrating the stick controller 31A or the push button 31B, or a combination of some or all of these, and may be executed using any effect device.

[0043] The effects that can be executed in accordance with the progress of the game include variable display of the effect symbols. In response to the start of the first special symbol game or the second special symbol game, the variable display of the effect symbols is started in the effect symbol display areas 5L, 5C, and 5R of "left", "middle", and "right" provided on the screen of the image display device 5. When the determined special symbol that is the display result in the first special symbol game or the second special symbol game is stopped and displayed, the determined effect symbol that is the display result is stopped and displayed in the variable display of the effect symbols. The determined effect symbol is composed of a combination of three effect symbols corresponding to the effect symbol display areas 5L, 5C, and 5R of "left", "middle", and "right". During the period from the start to the end of the variable display of the effect symbols, the display mode in the variable display of the effect symbols may become a reach mode. The reach mode is a mode in which the effect symbols that have stopped on the screen of the image display device 5 constitute part of a jackpot combination and the variation of the effect symbols that have not yet stopped continues. When the display mode in the variable display of the performance pattern becomes a reach mode, it is also said that a reach has been achieved.

[0044] A reach effect can be executed in response to the variable display of the effect pattern becoming a reach state. The pachinko gaming machine 1 can execute a plurality of types of reach effects so that the rate at which the display result of the variable display becomes a "jackpot" varies when the effect state differs. The rate of a "jackpot" corresponding to the effect state is also called the jackpot reliability or jackpot expectation rate. The reach effects include, for example, a normal reach and a super reach, which has a higher jackpot reliability than a normal reach. In addition, the reach effects may include a short reach and a long reach, which has a longer execution time than a short reach, in response to the execution time of the reach effect.

[0045] When the display result of the special symbols is a "jackpot", a fixed performance symbol that is a predetermined jackpot combination is displayed as a display result of the performance symbol on the screen of the image display device 5. As an example, the same performance symbols, such as a performance symbol showing the number "7", are displayed stopped on a predetermined effective line in the performance symbol display areas 5L, 5C, and 5R of the "left", "middle", and "right". In the case of a "probability jackpot" that is controlled to a probability jackpot state after the end of the jackpot game state, odd-numbered performance symbols, such as a performance symbol showing the number "7", may be displayed stopped. In the case of a "non-probability jackpot" that is not controlled to a probability jackpot state after the end of the jackpot game state, even-numbered performance symbols, such as a performance symbol showing the number "6", may be displayed stopped. A "non-probability jackpot" is also called a "normal jackpot". In this case, the odd-numbered performance symbols are also called probability jackpot symbols. The even-numbered performance symbols are also called non-probability jackpot symbols or normal symbols. After a reach state occurs with a non-probability variable pattern, a promotion effect may be executed that ultimately results in a "probability variable jackpot."

[0046] When the display result of the special pattern is a "small win", a fixed performance pattern that is a predetermined small win combination is stopped and displayed as a display result of the performance pattern on the screen of the image display device 5. As an example, the same performance pattern, such as a performance pattern showing a number other than "7", may be displayed stopped on a predetermined effective line in the "left", "center", and "right" performance pattern display areas 5L, 5C, and 5R. A common fixed performance pattern may be stopped and displayed when the display result of the special pattern is a "big win" and when it is a "small win".

[0047] When the display result of the special pattern is a "miss", the display result may be displayed as a stop without the variable display of the performance pattern being in a reach state. In this case, the fixed performance pattern of the non-reach combination is displayed as a display result of the performance pattern. The display result in which the fixed performance pattern of the non-reach combination is displayed as a stop without the reach state is also called a non-reach miss. When the display result of the special pattern is a "miss", the variable display of the performance pattern may be in a reach state, and the display result may be displayed as a stop after the reach performance is executed. In this case, the display result of the performance pattern may be displayed as a fixed performance pattern of the reach combination that is not a big win combination or a small win combination. The display result in which the fixed performance pattern of the reach combination is displayed as a stop after the reach state is reached is also called a reach miss.

[0048] The effects that the pachinko game machine 1 can execute include variable display-compatible displays such as reserved displays and active displays. In addition, for example, a preview effect that predicts the jackpot reliability can be executed during the variable display of the effect pattern. The preview effect may include a variable preview effect that predicts the jackpot reliability corresponding to the variable display being executed, and a look-ahead preview effect that predicts the jackpot reliability corresponding to the variable display before execution whose execution is on hold. The look-ahead preview effect may be capable of executing a change effect that changes the display mode of a variable display-compatible display such as reserved displays and active displays to a mode different from normal.

[0049] On the screen of the image display device 5, a pseudo consecutive performance may be executed in which the performance symbols are temporarily stopped during the variable display of the performance symbols, and then the variable display is resumed, so that one variable display appears to be multiple variable displays in a pseudo manner. The pseudo consecutive performance may be set so that the reliability of a big win is higher when the number of times the variable display is resumed after the performance symbols are temporarily stopped is large than when the number of times the number of times is small. In the variable display of the performance symbols, the pseudo consecutive performance may be executed before the reach state is reached, and may be executed after the reach state is reached. In addition, in the variable display of the performance symbols, the pseudo consecutive performance may be executed at multiple timings.

[0050] During control of the jackpot gaming state, a jackpot performance can be executed to notify the jackpot gaming state. The jackpot performance may include a performance to notify the number of rounds and a promotion performance to suggest or notify that the advantage of the jackpot gaming state will improve. During control of the small win gaming state, a small win performance can be executed to notify the small win gaming state. By executing a common performance during control of the jackpot gaming state and during control of the small win gaming state, it may be possible to make it impossible or difficult for the player to recognize whether the current gaming state is a jackpot gaming state or a small win gaming state.

[0051] In a non-play state where a special game or the like is not being executed and a game is not in progress, a demonstration effect image can be displayed on the screen of the image display device 5. A demonstration effect image is also called a demo image. Display of a demo image is also called a demo display. An effect by a demo display is also called a customer waiting demo effect.

[0052] (Board configuration) The pachinko game machine 1 is equipped with a main board 11, a performance control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17, and the like, as shown in Fig. 2. In addition, various boards are arranged on the back of the pachinko game machine 1, such as a payout control board, an information terminal board, and a firing control board.

[0053] The main board 11 is a main control board and has a function capable of controlling the progress of the game in the pachinko game machine 1. The progress of the game includes the execution of various games and transitions of game states, such as the execution of a special game accompanied by the management of reserved balls, the execution of a normal game accompanied by the management of reserved balls, a big win game state, a small win game state, a time-saving state, and a probability change state. The main board 11 includes a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

[0054] The game control microcomputer 100 provided on the main board 11 is, for example, a one-chip microcomputer, and can be configured to include a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, a random number circuit 104, and an I / O (Input / Output port) 105. A part or all of the ROM 101, the RAM 102, and the random number circuit 104 may be configured to be externally attached to the game control microcomputer 100, or may be configured to be built into the game control microcomputer 100. The switch circuit 110 takes in detection signals from various switches for game ball detection and transmits them to the game control microcomputer 100. The various switches for game ball detection include, for example, a gate switch 21, start port switches such as a first start port switch 22A and a second start port switch 22B, a count switch 23, a specific area switch 24, and an outlet switch 26. The detection signal indicates that a game ball has passed or entered and a switch has been turned on. The transmission of the detection signal indicates that the game ball has passed or entered. The solenoid circuit 111 can supply a solenoid drive signal from the game control microcomputer 100 to the normal electric role solenoid 81, the big prize opening solenoid 82, and the specific area solenoid 83. The solenoid drive signal may be any signal that turns on each solenoid.

[0055] The ROM 101 of the microcomputer 100 for game control is a non-volatile storage device that stores computer programs and data used for game control. The data stored in the ROM 101 includes table data constituting tables used for variation patterns, performance control commands, and various other settings, judgments, and decisions. The RAM 102 of the microcomputer 100 for game control is a temporary storage device that provides a work area used for game control and a stack for saving data. The RAM 102 may be a backup RAM that stores the contents of a part or all of the memory area so that they can be restored within a predetermined period even if the power supply to the pachinko game machine 1 is stopped. The RAM 102 is also called RWM (Read / Write Memory). The work area of ​​the RAM 102 includes a memory area capable of storing various data used for game control, such as a counter, a timer, a buffer, and a storage area for various other codes and numerical values. The CPU 103 included in the game control microcomputer 100 executes processes corresponding to the programs stored in the ROM 101, thereby being able to control the progress of the game in the pachinko game machine 1.

[0056] The random number circuit 104 provided in the game control microcomputer 100 counts updatable numerical data indicating various random number values ​​used when controlling the progress of a game. The random numbers used when controlling the progress of a game are also called game random numbers. Some or all of the game random numbers may be updated by hardware using a dedicated circuit, or may be updated by software such as a computer program executed by the CPU 103.

[0057] 3 shows an example of the random numbers for game. The random numbers for game include a random number MR1-1 for determining a special symbol, a random number MR1-2 for a winning symbol, a random number MR1-3 for an initial value for a winning symbol, a random number MR2-1 for a normal winning symbol, a random number MR2-2 for an initial value for a normal winning symbol, a random number MR3-1 for a normal symbol variation pattern, a random number MR3-2 for selecting a losing performance, a random number MR3-3 for selecting a variation pattern type, and a random number MR3-4 for a variation pattern.

[0058] The random number MR1-1 for determining the special symbol is used to determine the display result of the special symbol, such as whether the display result of the special symbol is a "big win" or whether the display result of the special symbol is a "small win". The random number MR1-2 for the winning symbol is used to select a confirmed special symbol from a plurality of special symbols, such as a big win symbol when the display result of the special symbol is a "big win" or a small win symbol when the display result of the special symbol is a "small win". The random number MR1-3, which is the initial value for the winning symbol, is used to set the initial value of the random number MR1-2. The random number MR2-1 for the winning normal symbol is used to select a confirmed normal symbol from a plurality of normal symbols to be displayed when the display result is a "normal win" in the variable display of the normal symbol. The random number MR2-2, which is the initial value for the winning normal symbol, is used to set the initial value of the random number MR2-1. The random number MR3-1 for the normal symbol variation pattern is used to determine the variation pattern of the normal symbol to one of a plurality of patterns prepared in advance. The random number MR3-2 for the miss performance selection is used to select whether or not the variable display of the performance pattern will be in a reach state when the display result of the special symbol is a "miss". The random number MR3-3 for the variation pattern type selection is used to select the variation pattern type of the special symbol. The variation pattern type of the special symbol is a group in which the variation pattern of the special symbol is previously classified based on, for example, the performance state during the variable display of the performance pattern, and may be configured to include one or more variation patterns. The random number MR3-4 for the variation pattern is used to select the variation pattern of the special symbol.

[0059] When making various judgments and decisions based on random numbers, such as numerical data indicating the value of a gaming random number, the CPU 103 reads and refers to various tables from the ROM 101. Even when random numbers are not used, necessary tables may be read from the ROM 101 and referred to to make various judgments, decisions, settings, and the like.

[0060] The I / O 105 of the game control microcomputer 100 includes an input port to which various signals are input and an output port to which various signals are output. The various signals input to the input port of the I / O 105 may include detection signals from various switches transmitted via the switch circuit 110. The various signals output from the output port of the I / O 105 may include signals for controlling the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first reserved display device 25A, the second reserved display device 25B, the normal reserved display device 25C, etc., and solenoid drive signals for driving the normal electric role solenoid 81, the large winning opening solenoid 82, the specific area solenoid 83, etc.

[0061] The main board 11 transmits a performance control command according to the progress of the game to the performance control board 12 as part of the operation of controlling the progress of the game by the game control microcomputer 100. The performance control command is a command that specifies or notifies the progress of the game. The performance control command output from the main board 11 is relayed by the relay board 15 and supplied to the performance control board 12. The performance control command may include commands that specify various determination results in the main board 11, such as the display result of the special game, the type of winning, and the variation pattern, commands that specify the game situation, such as the start and end of the variable display, the opening status of the big winning port, the occurrence of a winning, the number of reserved memories, and the game status, and commands that specify the occurrence of an error.

[0062] The performance control board 12 is a sub-control board independent of the main board 11, and has a function of receiving a performance control command and controlling the performance based on the received performance control command. The performances that can be controlled by the performance control board 12 include various performances according to the progress of the game, such as driving the movable body 32, and also various notifications such as error notifications and notifications of power outage recovery. The performance control board 12 includes a performance control CPU 120, a ROM 121, a RAM 122, a display control unit 123, a random number circuit 124, and an I / O 125.

[0063] The performance control CPU 120 executes a program stored in the ROM 121 to perform processing for controlling the execution of performance together with the display control unit 123. This processing is for implementing the various functions of the performance control board 12, and includes determining the performance to be executed. The performance control CPU 120 uses various data stored in the ROM 121, such as data of various tables, and also uses the RAM 122 as a main memory. The performance control CPU 120 may instruct the display control unit 123 to execute a performance based on a detection signal from the controller sensor unit 35A or the push sensor 35B. The detection signal here is a signal that is output when an operation by a player is detected, and may be a signal that appropriately indicates the content of the operation.

[0064] The display control unit 123 includes a VDP (Video Display Processor), a CGROM (Character Generator ROM), a VRAM (Video RAM), etc., and controls the performance mainly related to display based on the performance execution instruction from the performance control CPU 120. The display control unit 123 displays a performance image on the screen of the image display device 5 by supplying a video signal corresponding to the performance to be executed to the image display device 5. The display control unit 123 further supplies a sound designation signal to the sound control board 13 and a lamp signal to the lamp control board 14. The sound designation signal designates the sound to be output from the speakers 8L and 8R. The lamp signal designates the lighting state or the extinguishing state of the game effect lamp 9. The supply of the sound designation signal or the lamp signal enables the sound output from the speakers 8L and 8R and the lighting or extinguishing of the game effect lamp 9 in synchronization with the display of the performance image. The display control unit 123 may be capable of supplying a signal for operating the movable body 32 to a motor or solenoid of the movable body 32, or to a driver circuit that drives the movable body 32. A driver board for driving the movable body 32 may be provided separately from the performance control board 12.

[0065] The random number circuit 124 counts numerical data indicating various random number values ​​used when controlling the execution of various performances in an updatable manner. The random numbers used when controlling the execution of performances are also called random numbers for performance. The random numbers for performance may be updated by software such as a computer program executed by the performance control CPU 120. When making various judgments and decisions based on random number values, such as numerical data indicating the values ​​of the random numbers for performance, the performance control CPU 120 reads out and refers to various tables from the ROM 121. Even when random number values ​​are not used, the performance control CPU 120 may read out and refer to the necessary tables from the ROM 121 to make various judgments, decisions, settings, and the like.

[0066] The I / O 125 is configured to include, for example, an input port for taking in performance control commands transmitted from the main board 11, and an output port for transmitting various signals. The input port of the I / O 125 may include an input terminal for a detection signal supplied from the controller sensor unit 35A, and an input terminal for a detection signal supplied from the push sensor 35B. The output port of the I / O 125 may include an output terminal for a video signal supplied to the image display device 5, an output terminal for a sound designation signal supplied to the audio control board 13, and an output terminal for a lamp signal supplied to the lamp control board 14.

[0067] The sound control board 13 is equipped with various circuits for driving the speakers 8L and 8R, and drives the speakers 8L and 8R based on a sound designation signal from the display control unit 123, and outputs the sound designated by the sound designation signal from the speakers 8L and 8R. The lamp control board 14 is equipped with various circuits for driving the game effect lamps 9, and drives the game effect lamps 9 based on a lamp signal from the display control unit 123, and turns the game effect lamps 9 on or off in a manner designated by the lamp signal. In this way, the sound output from the speakers 8L and 8R and the turning on and off of the game effect lamps 9 can be controlled based on a signal from the display control unit 123. Note that the control of the sound output and the turning on and off of the lamps, such as the supply of the sound designation signal and the lamp signal, and the control of the movable body 32, such as the supply of a signal to operate the movable body 32, may be performed in part or in whole by the performance control CPU 120. Boards other than the main board 11, such as the performance control board 12, the audio control board 13, and the lamp control board 14, are also called sub-boards. As in the configuration example shown in Fig. 2, multiple sub-boards may be provided for different functions, or, unlike the configuration example shown in Fig. 2, one sub-board may be configured to have multiple functions.

[0068] The power supply board 17 can supply power from an AC power source such as AC 100V in an external power source such as a commercial power source to electrical components including various control boards such as the main board 11 and the performance control board 12. The power supply board 17 includes, for example, a rectifier circuit for converting AC to DC, and a power supply circuit for converting a predetermined DC voltage to a specific DC voltage (for example, DC 12V or DC 5V). The pachinko game machine 1 can switch between starting and ending the power supply by operating the power switch 91. The switch circuit 110 of the main board 11 takes in a reset signal, a power off signal, and a clear signal from the power supply board 17 and transmits them to the game control microcomputer 100. The reset signal is an operation stop signal for putting a control circuit such as the game control microcomputer 100 into an operation stop state, and may be output using any of a power supply monitoring circuit, a watchdog timer built-in IC, and a system reset IC. The power-off signal is turned off when the predetermined power supply voltage used in the pachinko game machine 1 exceeds a predetermined value, and is turned on when the period during which the predetermined power supply voltage is below the predetermined value continues for a power-off reference time or longer. The clear signal is turned on in response to, for example, pressing the clear switch 92 provided on the power supply board 17.

[0069] (operation) Next, the operation (action) of the pachinko gaming machine 1 will be described.

[0070] (Main operations of main board 11) First, a description will be given of the main operations of the main board 11. When power supply to the pachinko gaming machine 1 is started, the game control microcomputer 100 is started, and the CPU 103 executes main processing for game control.

[0071] FIG. 4 is a flow chart showing the main process P_MAIN for game control executed by the CPU 103 on the main board 11. When the main process P_MAIN for game control shown in FIG. 4 is started, the CPU 103 executes the power supply start response process P_POWER_ON (step S1), and then executes the RWM check process P_RWM_CHK (step S2). The power supply start response process P_POWER_ON in step S1 can execute the initial setting of the game control microcomputer 100 in response to the start of power supply in the pachinko game machine 1. The initial setting of the game control microcomputer 100 may include the initialization of the output port, the setting of the interrupt vector, the setting of the built-in device register, and the setting of the specific register. The RWM check process P_RWM_CHK in step S2 includes a checksum calculation process, and compares the checksum data obtained as a result of the process with the stored data in the checksum buffer, and if the two data match, it is determined that the stored contents in the RAM 102 are normal.

[0072] Next, it is determined whether or not a predetermined recovery condition is satisfied (step S3). The recovery condition can be satisfied when the clear signal corresponding to the operation of the clear switch 92 is in the OFF state, there is normal stored data in the checksum buffer, and the stored contents in the RAM 102 as the backup RAM are normal. When the power supply of the pachinko game machine 1 is turned on, for example, if the clear switch 92 provided on the power supply board 17 is pressed, a clear signal in the ON state is input to the game control microcomputer 100. When such a clear signal in the ON state is input, it is determined in step S3 that the recovery condition is not satisfied. The checksum buffer stores the checksum data calculated in the checksum calculation process when the backup judgment time was measured by the backup monitoring timer at the previous power cut. When the time value of the backup monitoring timer does not match the specific value corresponding to the backup judgment time, it is determined in step S3 that the recovery condition is not satisfied. The backup data may be stored data in the game work area in the RAM 102 as the backup RAM for game control. In step S3, it may be determined whether or not the recovery conditions can be met based on the results of checking or inspecting the presence or absence of backup data and data errors by the RWM check process P_RWM_CHK in step S2.

[0073] When the recovery condition is met (step S3; Yes), the backup setting process P_BACKUP_SET is executed (step S4). The backup setting process P_BACKUP_SET uses a backup command transmission table to enable transmission of performance control commands corresponding to backup from the main board 11 to the performance control board 12. The backup setting process P_BACKUP_SET also clears the process codes, timers, counters, and flags specified by the backup setting table to enable initialization.

[0074] If the recovery condition is not satisfied (step S3; No), the initialization setting process P_INIT_SET is executed (step S5). The initialization setting process P_INIT_SET enables clear data to be transferred to the game work area, which is the working area in RAM 102. This initializes the game work area in RAM 102. The initialization setting process P_INIT_SET then uses an initialization command transmission table to enable transmission of performance control commands corresponding to initialization from the main board 11 to the performance control board 12. The initialization setting process P_INIT_SET also clears buffers, timers, pointers, and counters specified by the initialization setting table to enable them to be initialized.

[0075] Then, the control start setting process P_STACON is executed (step S6). The control start setting process P_STACON may include a wait process. The wait process executes a loop process and waits until a set waiting time has elapsed, thereby ensuring that sub-boards such as the performance control board 12 can be started. The control start setting process P_STACON may also include a specific number of command transmission process or a command transmission process for chip individual number information. The specific number of command transmission process enables a performance control command that specifies the count value of a specific number counter when power is turned on to be transmitted from the main board 11 to the performance control board 12. The specific number counter is provided at a specified address in the RAM 102, and may be capable of counting the remaining number of times until the number of executions of the variable display reaches a specific number corresponding to the time-saving condition. The command transmission process for chip individual number information enables a performance control command that specifies the stored value of a chip individual number register to be transmitted from the main board 11 to the performance control board 12. The chip individual number register is included in the built-in register of the game control microcomputer 100, and may be any register capable of storing a different value assigned to each chip as the chip individual number.

[0076] The control start setting process P_STACON may include a start-up out-of-area process. The start-up out-of-area process is a process executed by reading out a program stored in a non-game program area of ​​the ROM 101 in response to start-up due to the start of power supply in the pachinko game machine 1. The start-up out-of-area process may be, for example, a performance display RWM initial value setting process. The performance display RWM initial value setting process makes it possible to set an initial value for performing an initial display by a 7-segment LED constituting the performance display monitor. The performance display monitor may be mounted on, for example, the main board 11, and may display contents related to the setting value and contents related to the base. When the pachinko game machine 1 is in a setting change state in which the settings can be changed, the setting value can be changed to one of a plurality of stages, for example, six stages, and makes it possible to set the probability that the display result of the special pattern will be a "jackpot". The base is calculated by dividing the number of prize balls paid out when a game ball passes through each winning port, such as the start winning port, the general winning port, and the large winning port, by the number of game balls launched into the game area.

[0077] After the control start setting process P_STACON in step S6, a timer interrupt counter setting is performed (step S7). In step S7, a PTC counter output value is set so that a regular timer interrupt occurs at a predetermined time interval, for example, 4 [ms (milliseconds)]. After that, the main process P_MAIN for game control enters a loop process. In this loop process, interrupt prohibition is set (step S8), an initial value determination random number update process P_TFINIT is executed (step S9), and an in-loop region outside process P_REGOUT is executed (step S10), and then interrupt permission is set (step S11), and the process returns to step S8. Then, when the interrupt permission state is in effect, the CPU 103 becomes capable of executing a timer interrupt process each time an interrupt request signal is input from the PTC to the CPU 103. This allows the CPU 103 to execute a timer interrupt process each time a predetermined time interval, for example, 4 [ms], has elapsed.

[0078] Fig. 5 is a flow chart showing an example of a timer interrupt process P_PCT for game control. In the timer interrupt process P_PCT shown in Fig. 5, a power cut process P_POWER_OFF is executed (step S51). Then, it is determined whether the misconduct monitoring flag is "0" or not (step S52). When a magnetism is detected by a magnet sensor or when a radio wave is detected by a frame radio wave sensor, the misconduct monitoring flag is set to "1" corresponding to an ON state. In other cases, the misconduct monitoring flag is set to "0" corresponding to an OFF state.

[0079] If the fraudulent activity monitoring flag is "1" (step S52; No), the game stop process P_GAME_STOP is executed (step S53). The game stop process P_GAME_STOP may be a process that initializes the output port and turns off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and if it is in the off state, the execution of the payout process in the payout control board is stopped.

[0080] When the fraudulent activity monitoring flag is "0" (step S52; Yes), the switch processing P_SW is executed (step S54), the switch error notification processing P_CON_CHK is executed (step S55), the random number update processing P_RANDOM is executed (step S56), and the initial value determination random number update processing P_TFINIT is executed (step S57). In addition, the special symbol process processing P_TPROC is executed (step S58), the normal symbol process processing P_FPROC is executed (step S59), the information output processing P_JYOUHOU is executed (step S60), the prize ball processing P_PAY is executed (step S61), and the display processing P_HYOUZI is executed (step S62). Furthermore, other timer interruption corresponding processing is executed (step S63). After that, the interrupt permission is set (step S64), and then the timer interruption processing P_PCT is terminated.

[0081] The power-off process P_POWER_OFF in step S51 judges the power confirmation signal transmitted from the power supply board 17, and enables checksum calculation process at the time of power-off, etc. to be executed. The switch process P_SW in step S54 judges the state of the input port, and enables update of the switch-on buffer, etc. The switch error notification process P_CON_CHK in step S55 can update the count value of the sensor-on counter specified by, for example, the switch error notification judgment table, and enables error notification display when the count value reaches a sensor abnormality error judgment value. The random number update process P_RANDOM in step S56 enables software random numbers among the game random numbers to be updated by software. The random number update process P_TFINIT for initial value determination in step S57 enables software to update random numbers used as random number initial values ​​among the game random numbers.

[0082] The special symbol process P_TPROC in step S58 includes processes related to the variable display of the special symbol and the game state, such as the management of the execution and reservation of the special symbol game, the control of the big win game state and the small win game state, and the control of the game state. The normal symbol process P_FPROC in step S59 includes processes related to the variable display of the normal symbol and the state control of the second start winning port, such as the management of the execution and reservation of the normal symbol game based on the detection signal from the gate switch 21, and the opening and closing control of the variable winning ball device 6B based on the "normal hit". The information output process P_JYOUHOU in step S60 sets the information output signal. The information output signal is a signal corresponding to information such as big win information, start information, and probability fluctuation information supplied to a hall management computer installed outside the pachinko game machine 1. The big win information indicates the number of big wins, etc. The start information indicates the number of start wins, etc. The probability fluctuation information indicates the number of times the probability variable state has been reached, etc. The prize ball processing P_PAY in step S61 includes a prize ball command output counter addition process and a prize ball control process. The prize ball command output counter addition process uses a prize ball number table to determine whether the switch is on, and when on is detected, updates the prize ball command output counter and the winning information output counter. The prize ball control process selects a process corresponding to the prize ball process code, and controls the prize balls based on the detection of the game ball so that they can be paid out. The display process P_HYOUZI in step S62 sets the display by the first reserve indicator 25A, the second reserve indicator 25B, the regular reserve indicator 25C, and various other status indicator lights.

[0083] FIG. 6 is a flow chart showing an example of processing that can be executed in step S58 shown in FIG. 5 as the special symbol process processing P_TPROC. In the special symbol process processing P_TPROC, the CPU 103 sets the first start winning corresponding flag (step S101). The first start winning corresponding flag setting reflects the state of the first start port switch 22A included in the switch-on buffer in the flag register of the CPU 103 by executing a logical operation command or the like. At this time, the zero flag in the flag register being in the on state indicates that the first start winning corresponding flag is in the off state. In contrast, the zero flag being in the off state indicates that the first start winning corresponding flag is in the on state. Next, the first start port winning table is set by a transfer command for setting the table pointer (step S102). Then, it is determined whether the first start winning corresponding flag is on or not (step S103). When the first start winning corresponding flag is on (step S103; Yes), the start port switch passing process P_TZU_ON is executed (step S104).

[0084] When the first start winning corresponding flag is off in response to step S103 (step S103; No), or after the start port switch passing process P_TZU_ON in step S104, the second start winning corresponding flag is set (step S105). The second start winning corresponding flag is set by executing a logical operation command or the like to reflect the state of the second start port switch 22B contained in the switch-on buffer in the flag register of the CPU 103. At this time, the zero flag in the flag register being on indicates that the second start winning corresponding flag is off. In contrast, the zero flag being off indicates that the second start winning corresponding flag is on. Next, the second start port winning table is set by a transfer command for setting the table pointer (step S106). Then, it is determined whether the second start winning corresponding flag is on (step S107). When the second start winning corresponding flag is on (step S107; Yes), the start port switch passing process P_TZU_ON is executed (step S108).

[0085] The start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102 to update the first reserved memory number and the total reserved memory number by adding 1 when the first reserved memory number is less than the upper limit number, extracts the random number MR1-1 for special pattern determination, the random number MR3-2 for miss performance selection, the random number MR3-3 for variation pattern type selection, and the random number MR3-4 for the variation pattern, stores them in the respective random number buffers, and then transfers them to the first special pattern reserved buffer. Also, the first reserved memory information designation command transmission table is used to enable the first reserved memory information designation command, which designates the first reserved memory number, to be transmitted from the main board 11 to the performance control board 12. Then, a value indicating "1" as the start port winning designation value is stored in the start port winning buffer.

[0086] The start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106 to update the second reserved memory number and the total reserved memory number by adding 1 when the second reserved memory number is less than the upper limit number, extracts the random number MR1-1 for special pattern determination, the random number MR3-2 for miss performance selection, the random number MR3-3 for variation pattern type selection, and the random number MR3-4 for variation pattern, stores them in the respective random number buffers, and then transfers them to the second special pattern reserved buffer. Also, the second reserved memory information designation command transmission table is used to enable the second reserved memory information designation command, which designates the second reserved memory number, to be transmitted from the main board 11 to the performance control board 12. Then, a value indicating "2" as the start port winning designation value is stored in the start port winning buffer.

[0087] A common start port switch passing process P_TZU_ON can be executed in steps S104 and S108. Meanwhile, the start port switch passing process P_TZU_ON in step S104 uses the first start port winning table set in step S102, whereas the start port switch passing process P_TZU_ON in step S108 uses the second start port winning table set in step S106. In this way, the common start port switch passing process P_TZU_ON is executed using different start port winning tables. Therefore, different data settings and controls are possible by the common process when the game ball enters the first start port and when the game ball enters the second start port. The start port switch passing process P_TZU_ON may include a winning performance process using the extracted game random number.

[0088] When the second start winning corresponding flag is off in response to step S107 (step S107; No), or after the start port switch passing process P_TZU_ON in step S108, a special symbol process processing jump table is set by a transfer command that sets a pointer (step S109). The special symbol process processing jump table is an address management table that selects and makes executable a process corresponding to the read value of the special symbol process code. The special symbol process code can be updated and set to any of 00[H] to 0B[H] in response to the progress of game control in the pachinko game machine 1, and is also called a special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] may also indicate a binary number.

[0089] Following step S109, a transfer command for reading out stored data loads the special symbol process code (step S110). Next, a 2-byte data selection process P_ABXEXEC is executed (step S111) to obtain the address of the process selected corresponding to the special symbol process code. The address obtained at this time is set in a pointer. After this, a subroutine call command executes the process pointed to by the pointer (step S112), making it possible to execute the process selected corresponding to the special symbol process code. When the process selected in this way ends and a return command is issued to return to the special symbol process P_TPROC, the special symbol process P_TPROC also ends, and a return command is issued to return to the timer interrupt process P_PCT for game control.

[0090] FIG. 7 shows a configuration example TT01 of a special symbol process jump table used in the special symbol process P_TPROC. The special symbol process jump table is configured to include table data that can set the address of the process selected corresponding to the special symbol process code in an internal register of the CPU 103 used as a pointer. The special symbol process jump table of the configuration example TT01 includes special symbol normal process P_TNORMAL when the special symbol process code is 00 [H], special symbol fluctuation process P_TSTART when the special symbol process code is 01 [H], special symbol stop process P_TSTOP when the special symbol process code is 02 [H], small win opening pre-processing P_TLFAN when the special symbol process code is 03 [H], small win opening mid-processing P_TLOPEN when the special symbol process code is 04 [H], small win opening post-processing P_TLCLSF when the special symbol process code is 05 [H], and ... The table data includes address values ​​that can be set in the pointers corresponding to P_TLOUT, the waiting process for small win ball discharge when the other pattern process code is 06[H], P_TLEND, the small win end process when the special pattern process code is 07[H], P_TINT, the process before the large prize opening is opened when the special pattern process code is 08[H], P_TOPEN, the process during the large prize opening is opened when the special pattern process code is 09[H], P_TCLSF, the process after the large prize opening is opened when the special pattern process code is 0A[H], and P_TEND, the big win end process when the special pattern process code is 0B[H].

[0091] The special symbol normal processing P_TNORMAL makes it possible to determine whether or not to start a special symbol game based on the presence or absence of stored reserved information, to determine the special symbol display result using the random number MR1-1 for special symbol determination, to determine the fixed special symbol to be displayed in the variable display of the special symbol, and to determine the variable pattern of the special symbol. The special symbol display result includes "big hit", "small hit", "miss", etc., and when it is determined to be a "big hit", it is determined to control to a big hit game state as an advantageous state advantageous to the player. Also, when the display result of the special symbol is a "big hit", it is determined which of the multiple types of big hit game states with different degrees of advantage for the player to control to, corresponding to the big hit symbol that is the fixed special symbol. Therefore, the CPU 103 can determine whether to control the state to an advantageous state that is advantageous to the player by executing the special symbol normal process P_TNORMAL, and can determine which of a plurality of types of advantageous states having different degrees of advantage to the player to control to. Furthermore, the CPU 103 can determine which of a plurality of types of variation patterns to control to by executing the special symbol normal process P_TNORMAL.

[0092] The special symbol change process P_TSTART measures the time that has elapsed since the special symbol started to change in the first special symbol display device 4A or the second special symbol display device 4B, and enables a determination as to whether or not the special symbol change time corresponding to the change pattern has elapsed. The special symbol stop process P_TSTOP measures the time that has elapsed since the special symbol stopped changing in the first special symbol display device 4A or the second special symbol display device 4B, and enables a determination as to whether or not the symbol stop time has elapsed. The symbol stop time may be set as the time for stopping the display of the special symbol when it is determined in the special symbol change process P_TSTART that the special symbol change time has elapsed. When the symbol stop time has elapsed, the special symbol process code is updated and various settings are made according to the special symbol display result. For example, if the special pattern display result is a "big hit", the special pattern process code can be updated to 08 [H], if the special pattern display result is a "small hit", the special pattern process code can be updated to 03 [H], and if the special pattern display result is a "miss", the special pattern process code can be updated to 00 [H].

[0093] The small win opening pre-processing P_TLFAN, the small win opening mid-processing P_TLOPEN, the small win opening post-processing P_TLCLSF, the small win discharge ball waiting process P_TLOUT, and the small win end process P_TLEND are processes for controlling the progress of the game in the small win game state. The large prize opening pre-processing P_TINT, the large prize opening mid-processing P_TOPEN, the large prize opening post-processing P_TCLSF, and the big win end process P_TEND are processes for controlling the progress of the game in the big win game state.

[0094] (Main operations of the performance control board 12) Next, there will be explained the main operations of the performance control board 12. In the performance control board 12, when a power supply voltage is supplied from the power supply board 17 or the like, the performance control CPU 120 starts up and executes the performance control main process.

[0095] FIG. 8 is a flow chart showing the main processing S_MAIN for performance control executed by the performance control CPU 120 in the performance control board 12. When the main processing S_MAIN for performance control shown in FIG. 8 is started, the performance control CPU 120 executes the performance control initialization processing S_INIT (step S71). The performance control initialization processing S_INIT includes clearing the RAM 122, setting various initial values, and register settings for the timer circuit mounted on the performance control board 12. Then, the initial operation control processing S_SYOKI is executed (step S72). The initial operation control processing S_SYOKI makes it possible to control the initial operation of the movable body 32, such as control to drive the movable body 32 to return it to its initial position and control to perform a predetermined operation check. Then, it is determined whether or not the timer interrupt flag is on (step S73). The timer interrupt flag is set to the on state every time a predetermined time, for example, 2 [ms (milliseconds)], has elapsed based on the register setting for the timer circuit. Since the timer interrupt flag is off (step S73; No), step S73 is repeated and the process waits.

[0096] When the timer interrupt flag is on (step S73; Yes), the timer interrupt flag is cleared to the off state (step S74), and a command analysis process S_COMMAND is executed (step S75), a performance control process S_CPROC is executed (step S76), a performance random number update process S_RANDOM is executed (step S77), and a performance output process S_OUT is executed (step S78). Then, other timer interrupt response processes are executed (step S79), and the process returns to step S73.

[0097] The command analysis process S_COMMAND in step S75 enables the reading of the performance control command stored in the performance control command receiving buffer and the setting and control corresponding to the read performance control command. By executing the command analysis process S_COMMAND, the performance control CPU 120 can update the storage data indicating the state of the flag, the storage data of the register, and any other storage data in the working area of ​​the RAM 122 in response to the performance control command transmitted from the main board 11. The performance control process S_CPROC in step S76 enables the execution of performances using various performance devices including, for example, the display of a performance image on the screen of the image display device 5, the sound output from the speakers 8L and 8R, the lighting or extinguishing of the decorative light-emitting body such as the game effect lamp 9 and the decorative LED, and the drive control of the movable body 32. The control contents of the performances using various performance devices may be judged, determined, set, etc. based on the performance control command transmitted from the main board 11 and the execution result of the processing by the performance control CPU 120. The performance random number update process S_RANDOM in step S77 enables at least a portion of the performance random numbers used on the performance control board 12 side to be updated by executing a program as software.

[0098] Fig. 9(A) is a flow chart showing an example of processing that can be executed in step S76 shown in Fig. 8 as the performance control process processing S_CPROC. The performance control CPU 120 executes the look-ahead performance setting processing S_SAKI_SET in the performance control process processing (step S151). The look-ahead performance setting processing S_SAKI_SET enables judgment, decision, setting, etc. regarding the execution of a look-ahead preview performance based on the performance control command at the time of the start winning transmitted from the main board 11, for example. In addition, the look-ahead performance setting processing S_SAKI_SET enables the pending display to be updated based on the number of pending memories specified from the performance control command.

[0099] After the pre-reading effect setting process S_SAKI_SET in step S151, a effect control process jump table is set by a transfer command that sets a pointer (step S152). The effect control process jump table is an address management table that selects and makes executable a process corresponding to the read value of the effect control process code. The effect control process code can be updated and set to any of 00[H] to 0A[H] in accordance with the progress of the effect control in the pachinko game machine 1, and is also called the effect process code. The effect control process code is loaded by a transfer command for reading out stored data (step S153). In accordance with the effect control process code thus obtained, the address of the process to be selected is set in the effect control pointer (step S154). Therefore, by executing the process pointed to by the effect control pointer (step S115), the process selected in accordance with the effect control process code becomes executable.

[0100] 9B shows an example of the configuration TT02 of the performance control process jump table used in the performance control process S_CPROC. The performance control process jump table includes table data that can set the address of the process selected in response to the performance control process code in a register used as a performance control pointer. The presentation control process jump table of the configuration example TT02 includes table data that can set, in the presentation control pointer, address values ​​corresponding to the following: waiting for a change pattern command when the presentation control process code is 00[H]; starting a change in presentation pattern when the presentation control process code is 01[H]; processing during a change in presentation pattern when the presentation control process code is 02[H]; stopping a change in presentation pattern when the presentation control process code is 03[H]; displaying a small win when the presentation control process code is 04[H]; processing during a small win opening when the presentation control process code is 05[H]; ending presentation processing after the small win when the presentation control process code is 06[H]; displaying a big win when the presentation control process code is 07[H]; processing during a round when the presentation control process code is 08[H]; post-round processing when the presentation control process code is 09[H]; and ending presentation processing after the big win when the presentation control process code is 0A[H].

[0101] The waiting for receiving a variation pattern command process makes it possible to determine whether or not a variation pattern designation command transmitted from the game control microcomputer 100 of the main board 11 has been received. When it is determined that a variation pattern designation command has been received, the performance control process code is updated to 01 [H] corresponding to the performance pattern variation start process, and when it is determined that a variation pattern designation command has not been received, the demo display can be controlled. The performance pattern variation start process makes it possible to start a variation-time performance corresponding to a special game. For example, in response to a variation pattern command transmitted from the main board 11, it makes it possible to select a performance pattern used to control the variation-time performance and to start updating a performance process timer that measures the performance execution time. The performance pattern variation process makes it possible to control the switching timing of each performance element that constitutes the performance pattern, and makes it possible to determine whether or not the performance execution time has elapsed based on the measured value of the performance process timer. When it is determined that the performance execution time has elapsed, the performance control process code is updated to 03 [H] corresponding to the performance pattern variation stop process. The performance pattern change stop process enables the end control of the performance during change and the display control of the performance result corresponding to the determined special pattern based on the establishment of the end condition of the performance during change, such as the lapse of the performance execution time or the reception of a performance pattern determination command. At this time, the performance control process code is updated and various settings are made according to the display result of the variable display. For example, when the display result of the variable display is "big hit", the performance control process code can be updated to 07 [H], when the display result of the variable display is "small hit", the performance control process code can be updated to 04 [H], and when the display result of the variable display is "miss", the performance control process code can be updated to 00 [H].

[0102] The small win display process, the small win open process, and the small win end performance process are processes for controlling the progress of the performance corresponding to the small win game state. The big win display process, the round process, the post-round process, and the big win end performance process are processes for controlling the progress of the performance corresponding to the big win game state.

[0103] (Variations of basic explanations, etc.) The pachinko gaming machine 1 is not limited to the configuration, functions, processing, and operation in the basic description and other descriptions, and various modifications and applications are possible. For example, the pachinko gaming machine 1 does not need to have all the technical features shown in the embodiment, and may have a part of the configuration described in the embodiment so as to solve at least one problem in the prior art. When a subordinate concept is described in the embodiment, an invention of a superordinate concept using a homologous or similar matter, or an invention of a superordinate concept using a common property, is included as the present invention, and may have a part of the structure or characteristics described in the embodiment so as to solve at least one problem in the prior art.

[0104] The pachinko game machine 1 may be a payout type game machine that pays out a predetermined number of game media as a prize when a prize is won, or it may be an enclosed type game machine that encloses game media and awards points when a prize is won.

[0105] The display during the variable display of the special symbol may be only one type of symbol, such as a symbol indicating "-", and the variable display may be such that this symbol is repeatedly displayed and turned off. One type of symbol may be displayed during the variable display, and this symbol may not be displayed when the variable display is stopped. For example, the display result may be a non-display state in which the symbol indicating "-" is not displayed and no special symbol is displayed.

[0106] The pachinko game machine 1 may be configured to change the winning probability of a jackpot and the ball payout rate in response to a plurality of set values. For example, in the special symbol normal processing of the special symbol process processing, the winning probability of a jackpot and the ball payout rate may be changed by using a different jackpot determination value for each set value. As a specific example, the set value is made up of six stages from 1 to 6, with 6 being the highest winning probability of a jackpot, and the winning probability of a jackpot decreasing in the order of 6, 5, 4, 3, 2, and 1. In this case, if 6 is set as the set value, the player has the highest advantage, and the advantage decreases stepwise in the order of 6, 5, 4, 3, 2, and 1. If the winning probability of a jackpot changes according to the set value, the ball payout rate may also change according to the set value. The winning probability of a jackpot is constant regardless of the set value, whereas the number of rounds in a jackpot game state may change according to the set value. The pachinko game machine 1 may be configured to be able to set one of a plurality of setting values ​​with different degrees of advantage for the player. The setting value set in the pachinko game machine 1 may be notified by transmitting a setting value designation command from the main board 11 to the performance control board 12. During execution of the variable display, a setting suggestion performance that suggests the setting value in the pachinko game machine 1 at a predetermined rate may be executed. The suggestion regarding the setting value of the pachinko game machine 1 is not limited to the suggestion of the setting value in the pachinko game machine 1, and may be, for example, the suggestion of whether the setting value in the pachinko game machine 1 has been changed. The setting suggestion performance may suggest the probability of a jackpot by any performance, and may also be able to suggest the setting value of the pachinko game machine 1.

[0107] Instead of a part or all of the suggestions regarding the control of the jackpot gaming state, or together with a part or all of the suggestions regarding the control of the jackpot gaming state, a suggestion regarding the control of a state that is advantageous to the player other than the jackpot gaming state may be given. For example, a suggestion regarding a probability variable state that is controlled after the end of the jackpot gaming state may be given. In addition, a suggestion may be given regarding a state in which any game value that is advantageous to the player is given as an advantageous state, depending on whether it is controlled or not.

[0108] The invention relating to the gaming machine is not limited to the pachinko gaming machine 1, and can also be applied to a slot machine as appropriate. The slot machine can execute a game in which medals are inserted, a predetermined bet amount is set, a plurality of types of symbols are rotated in response to the operation of a control lever by the player, and when the symbols are stopped in response to the operation of a stop button by the player, a predetermined number of medals are paid out to the player if a combination of stopped symbols is a specific combination. In a slot machine, an advantageous state that is advantageous to a player may include one or more of so-called bonuses, such as a big bonus, a regular bonus, RT, AT, ART, and CZ.

[0109] The programs and data for implementing various controls, including the progress of the game and the execution of the performance, may be distributed and provided to a computer device included in a gaming machine such as the pachinko gaming machine 1 by a removable recording medium, or may be distributed and provided by being installed in advance in a storage device of the computer device. Also, the device may be provided with a communication processing unit that can be connected to an external device on a network via a communication line, and the programs and data may be distributed and provided by downloading them from the external device. The execution form of the game and performance may be executable by mounting a removable recording medium, or may be executable by temporarily storing the programs and data downloaded via a communication line in an internal memory, or may be executable directly using the hardware resources of an external device on a network connected via a communication line, or may be executable by exchanging data with another computer device via a network.

[0110] When comparing various ratios such as the decision ratio of a process or data, the execution ratio of a performance, etc., expressions such as "high", "low", and "different" may include the case where one is a ratio of "0%" or "100%". For example, for one decision result or execution content, it may include the case where there is no decision or execution at a ratio of "0%", and may include the case where there is always a decision or execution at a ratio of "100%".

[0111] (Explanation of feature part 01AK) FIG. 10-1 shows a configuration example of the game control microcomputer 100 with respect to the characteristic part 01AK. The game control microcomputer 100 of the characteristic part 01AK is configured with an external bus interface 131, a clock circuit 132, a unique information storage circuit 133, a reset controller 134, an interrupt controller 135, a timer circuit 136, an address decode circuit 137, a free-running counter 138, and a serial communication circuit 139 in addition to the ROM 101, the RAM 102, and the CPU 103. The random number circuit 104 shown in FIG. 2 is configured to include a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I / O 105 shown in FIG. 2 is configured to include a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

[0112] The external bus interface 131 is a bus interface having an interface function between the external bus and the internal bus of the chip constituting the game control microcomputer 100, and a function of controlling the direction of the address bus, the data bus, and each control signal. For example, the external bus interface 131 may be connected to an external memory or an external input / output device externally attached to the game control microcomputer 100, and may transmit and receive address signals, data signals, various control signals, and the like between the external devices. The external bus interface 131 may include an internal resource access control circuit that controls access to the internal data of the game control microcomputer 100 from the external device.

[0113] The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the control external clock terminal EXC. A control clock generated by a control clock generating circuit provided in the game control microcomputer 100 may be input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, the 16-bit random number circuit 104A, and the 8-bit random number circuit 104B. The internal system clock SCLK can also be output from the system clock output terminal CLKO to the outside of the game control microcomputer 100. Alternatively, the internal system clock SCLK may be restricted so as not to be output to the outside of the game control microcomputer 100, making it difficult to identify the operating state of the game control microcomputer 100 from the outside.

[0114] The unique information storage circuit 133 can store, for example, multiple types of unique information that become internal information of the game control microcomputer 100. For example, the unique information storage circuit 133 may store a ROM code, a chip individual number, and an ID number as unique information that differs for each chip of the game control microcomputer 100. The ROM code is numerical data that can be generated from data stored in a predetermined area of ​​the ROM 101. The chip individual number and the ID number are numbers that are assigned when the game control microcomputer 100 is manufactured, and indicate different numerical values ​​for each chip. The chip individual number may be readable by a user program such as a game program, while the ID number may be set so that it cannot be read by the user program. The unique information storage circuit 133 may be included in a predetermined area of ​​the ROM 101, or may be included in a built-in register of the game control microcomputer 100.

[0115] The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100. Resets that can be controlled by the reset controller 134 include a system reset and a user reset. A system reset occurs when an input signal to an external system reset terminal XSRST is at a low level for a certain period of time. A user reset occurs due to a certain factor, such as the occurrence of a timeout signal from the watchdog timer 134A or the occurrence of an IAT. The reset controller 134 includes a watchdog timer 134A. The watchdog timer 134A can set a timer value corresponding to a monitoring time, and can perform a countdown that periodically updates the timer value by subtracting 1. When the timer value becomes "0" and a timeout occurs, the watchdog timer 134A can output a timeout signal to reset the game control microcomputer 100 and restart it. This allows the watchdog timer 134A to measure the monitoring time, and reset the game control microcomputer 100 when it is determined that the monitoring time has elapsed. The watchdog timer 134A can be set to enable or disable operation, for example, according to a game program.

[0116] The interrupt controller 135 can control various interrupt requests that occur inside or outside the game control microcomputer 100. Interrupts that can be controlled by the interrupt controller 135 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that can be accepted unconditionally even when the CPU 103 is in an interrupt-prohibited state, and is generated when the input signal of the external non-maskable interrupt terminal XNMI (also used as the input port PI6) is at a low level for a certain period of time. The maskable interrupt INT is an interrupt that can permit or prohibit the acceptance of an interrupt request by a setting command of the CPU 103, and multiple interrupts can be executed by setting a priority order. The cause of the maskable interrupt INT may be any of a number of types of interrupt causes, including the input signal of the external maskable interrupt terminal XINT (also used as input port PI5) being at a low level for a certain period of time, a timeout occurring in the timer circuit 136, and numerical data indicating a random value being stored in a random value register by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B. Any of these causes may be settable.

[0117] The timer circuit 136 includes a PTC (Programmable Timer Counter) as a timer counter corresponding to the three channels PTC0 to PTC2, and enables real-time interrupt generation and time measurement. Each of the channels PTC0 to PTC2 of the timer circuit 136 only needs to be able to update the timer value in response to a signal change of the count clock, such as the falling edge timing at which the clock signal changes from high level to low level, using a count clock generated based on the internal system clock SCLK.

[0118] The address decode circuit 137 can decode various signals obtained from each functional block inside the game control microcomputer 100, and can output a chip select signal which is a decoded signal for an external device. The chip select signal selectively enables the internal circuit of the game control microcomputer 100 or an external device which is a peripheral device, and enables access from the CPU 103. The output terminal that the address decode circuit 137 can use may be a multi-function terminal that can selectively output a parallel output signal from the POP 105B, a serial transmission signal from the serial communication circuit 139, a clock output signal from the clock circuit 132, and a chip select signal generated by the address decode circuit 137.

[0119] The free-running counter 138 includes counter circuits corresponding to the four channels FRC0 to FRC3, and can update the count value separately from the operation of the CPU 103. Each of the channels FRC0 to FRC3 of the free-running counter 138 can be started by an independent update clock, and can be set to stop or change its operation according to, for example, a game program. The count value by the free-running counter 138 can be stored in a hard latch register in response to a latch signal transmitted from an input terminal that serves as a latch signal input terminal in the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing a game program, etc.

[0120] The serial communication circuit 139 includes serial communication units corresponding to three channels SCU0, SCU1, and STU2, and enables communication with an external device by a serial communication method. Each of the channels SCU0, SCU1, and STU2 of the serial communication circuit 139 can process communication data in, for example, full duplex, asynchronous, or standard NRZ (Non Return to Zero) format. The channels SCU0 and SCU1 of the serial communication circuit 139 are included in a first channel transmission / reception circuit that can transmit and receive serial data bidirectionally with an external circuit. The channel STU2 of the serial communication circuit 139 is included in a second channel transmission circuit that can only transmit serial data unidirectionally with an external circuit. For example, the channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. Also, the channel SCU1 of the serial communication circuit 139 is used for data communication with the performance control board 12. Instead of the channel SCU1 of the serial communication circuit 139, the channel STU2 of the serial communication circuit 139 may be used for data communication with the performance control board 12.

[0121] The 16-bit random number circuit 104A includes random number generating units corresponding to the four channels RL0 to RL3, and each of them can generate random numbers from "0" to "65535" by independent operation using numerical data indicating the value of a 16-bit pseudo-random number. The maximum value of the random numbers generated by each channel RL0 to RL3 in the 16-bit random number circuit 104A can be set to any value within the range of "256" to "65535". By setting such a maximum value, it is possible to perform initial setting to select a random number start method so that updating of the numerical data indicating the random number value is started. Alternatively, it is possible to perform initial setting to select a random number start method so that each channel RL0 to RL3 in the 16-bit random number circuit 104A is automatically started when the operation mode of the game control microcomputer 100 shifts from the security mode to the user mode. The 16-bit random number circuit 104A can update the random number MR1-1 for determining a special symbol using the channel RL0, and can update the random number MR3-2 for selecting a losing performance using the channel RL2.

[0122] The 8-bit random number circuit 104B includes random number generating units corresponding to the four channels RS0 to RS3, and each of them can generate random numbers from "0" to "255" by numerical data indicating the value of an 8-bit pseudo-random number by independent operation. The maximum value of the random numbers generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value within the range of "16" to "255". By setting such a maximum value, it is possible to perform initial setting to select a random number start method so that updating of the numerical data indicating the random number value is started. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B may be initially set to select a random number start method so that it is automatically started when the operation mode of the game control microcomputer 100 shifts from the security mode to the user mode. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the type of variation pattern via channel RS1, can update the random number MR3-4 for the variation pattern via channel RS2, and can update the random number MR3-1 for the normal pattern variation pattern via channel RS3.

[0123] The PIP105A has an 8-bit wide dedicated input port built-in, and allows various signals to be input from outside the game control microcomputer 100. The PIP105A can use input terminals corresponding to the input ports PI0 to PI7. The input port PI5 uses a multifunction terminal that can be used with the external maskable interrupt terminal XINT. The input port PI6 uses a multifunction terminal that can be used with the external non-maskable interrupt terminal XNMI. The input port PI7 uses a multifunction terminal that can be used with the receiving terminal of the channel SCU0 in the serial communication circuit 139. The POP105B has an 11-bit wide dedicated output port built-in, and allows various signals to be output to the outside of the game control microcomputer 100. The POP105B can supply parallel output signals corresponding to the output ports PO0 to PO7 and PO10 to PO12 to the address decode circuit 137.

[0124] FIG. 10-2 shows an example of an address map in the game control microcomputer 100. In the example shown in FIG. 10-2, the area of ​​addresses 0000[H] to 3FFF[H] is assigned to the ROM 101, and includes a game program area, a game data area, a non-game program area, a non-game data area, a ROM comment area, a program management area, and other unused areas. The area of ​​addresses F000[H] to F3FF[H] is assigned to the RAM 102, and includes a game work area, a game stack area, a non-game work area, a non-game stack area, and other unused areas. The area of ​​addresses FE00[H] to FEBF[H] is a function setting register area assigned to the built-in register of the game control microcomputer 100. The area of ​​addresses FF00[H] to FFFF[H] is a function control register area assigned to the built-in register of the game control microcomputer 100.

[0125] In the ROM 101, the game program area can store a game program, which is a computer program related to the progress of a game. The game data area can store game data used by the game program. The non-game program area can store a non-game program, which is a computer program related to control or processing other than the progress of a game. The non-game data area can store non-game data used by the non-game program. These programs and data stored in the ROM 101 are designed and created in advance by the manufacturer of the pachinko game machine 1, who is the user of the game control microcomputer 100. Therefore, the game program and the non-game program are included in the user program. The game data and the non-game data are included in the user data.

[0126] The storage area of ​​ROM 101 is provided with a game program area capable of storing game programs related to the progress of a game, and a non-game program area for control and processing other than the progress of a game, and the area before the non-game program area to which the latter address is assigned is an unused area with a storage area of ​​more than the boundary byte number, for example 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to the progress of a game, and the non-game program area capable of storing non-game programs related to control and processing other than the progress of a game, making it easy to design and manage the programs and data stored in ROM 101.

[0127] The storage area of ​​the ROM 101 is provided with a game program area capable of storing a game program related to the progress of the game, and a game data area capable of storing game data used by the game program, and the area in front of the game data area to which the rear address of the game program area or the game data area is assigned is an unused area with a storage area of ​​more than the boundary byte number, for example 16 bytes. This makes it easy to specify the game program area capable of storing a game program related to the progress of the game, and the game data area capable of storing game data used by the game program, making it easy to design and manage the programs and data stored in the ROM 101.

[0128] In the storage area of ​​the ROM101, a non-game program area capable of storing non-game programs related to control and processing different from the progress of the game and a non-game data area capable of listening to non-game data used by the non-game programs are provided adjacent to each other, and among the non-game program area and the non-game data area, the area behind the non-game program area to which the forward address is assigned becomes the non-game data area, and the area before the non-game data area to which the backward address is assigned becomes the non-game program area. This allows the non-game program area capable of storing non-game programs related to control and processing different from the progress of the game and the non-game data area capable of storing non-game data used by the non-game program to be provided in storage areas to which consecutive addresses are assigned, thereby enhancing the unity, and facilitating the design and management of the programs and data stored in the ROM101. Note that an unused area of ​​storage area of ​​more than the boundary byte number may be provided between the non-game program area and the non-game data area, so that the non-game program area and the non-game data area can be easily identified.

[0129] In the storage area of ​​the ROM 101, data indicating a value of "0" may be stored in all areas in the storage area that is to be an unused area. This makes it easy to distinguish between the game program area and the game data area, the non-game program area and the non-game data area, and the unused area. Also, when illegal data is stored in the unused area, the data can be easily found. Note that data indicating a value of "1" may be stored in all areas in the storage area that is to be an unused area. That is, data indicating the same value may be stored in all areas in the storage area that is to be an unused area. This makes it easy to distinguish between multiple types of storage areas, and makes it easy to find illegal stored data.

[0130] In the RAM 102, the game work area can be used as a work area when the CPU 103 executes a game program. The game stack area can be used as a stack area when the CPU 103 executes a game program. The non-game work area can be used as a work area when the CPU 103 executes a non-game program. The non-game stack area can be used as a stack area when the CPU 103 executes a non-game program.

[0131] The game program area and the game data area provided in the storage area of ​​ROM 101, and the game work area and the game stack area provided in the storage area of ​​RAM 102 are included in the storage area for game control. The non-game program and the non-game data area provided in the storage area of ​​ROM 101, and the non-game work area and the non-game stack area provided in the storage area of ​​RAM 102 are included in the storage area for non-game control.

[0132] The ROM comment area provided in the storage area of ​​the ROM 101 stores data indicating any program specific information, such as the title and version of the program. The program management area provided in the storage area of ​​the ROM 101 can store setting information required for the internal setting of the game control microcomputer 100 so that the CPU 103 executes game programs and non-game programs.

[0133] 10-3 shows a main setting example AKA01 of addresses included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function setting register area is the first area for setting functions using various circuits included in the game control microcomputer 100, such as the watchdog timer 134A of the reset controller 134, the interrupt controller 135, the timer circuit 136, the serial communication circuit 139, etc.

[0134] In the setting example AKA01, the setting values ​​of the WDT start register at address FE1A[H] and the WDT clear register at addresses FE1B[H] to FE1C[H] are invalid values ​​corresponding to unused states. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. As the setting value of the interrupt mask register at address FE00[H] is 7E[H], the interrupt control function using the interrupt controller 135 is set to an available state for the maskable interrupt IR0. As the setting values ​​of the registers related to the channel PTC0 of the timer circuit 136 at addresses FE01[H] to FE03[H] are valid values, the time measurement function using the channel PTC0 of the timer circuit 136 is set to an available state. As the setting values ​​of the registers related to the channels PTC1 and PTC2 of the timer circuit 136 at addresses FE04[H] to FE09[H] are invalid values ​​corresponding to unused states, the time measurement function using the channels PTC1 and PTC2 of the timer circuit 136 is set to an unused state.

[0135] The serial communication function using channels SCU0 and SCU1 of the serial communication circuit 139 is set to an available state because the register setting values ​​for channels SCU0 and SCU1 of the serial communication circuit 139 at addresses FE0A[H] to FE11[H] are valid values. The serial communication function using channel STU2 of the serial communication circuit 139 is set to an unused state because the register setting values ​​for channel STU2 of the serial communication circuit 139 at addresses FE12[H] to FE14[H] are invalid values ​​corresponding to unused state.

[0136] Since the register settings at addresses FE2C[H]-FE2E[H] related to the input ports of PIP 105A are valid values, the signal input function using each input port is set to an available state. Since the register settings at addresses FE36[H]-FE4A[H] related to random number circuit 104 include valid and invalid values, the random number generation function using random number circuit 104 is set to an available state for channels corresponding to valid values, and to an unused state for channels corresponding to invalid values. For example, of the four channels RL0-RL3 in 16-bit random number circuit 104A, channels RL0 and RL2, whose corresponding maximum value setting register settings are valid values, have their random number generation function set to an available state, while channels RL1 and RL3, whose corresponding maximum value setting register settings are invalid values, have their random number generation function set to an unused state. In addition, of the four channels RS0 to RS3 in the 8-bit random number circuit 104B, channels RS1 to RS3 whose corresponding maximum value setting registers have valid settings have their random number generation function set to an available state, and channel RS0 whose corresponding maximum value setting register has an invalid setting has its random number generation function set to an unused state.

[0137] In this way, it is sufficient that the various circuits included in the game control microcomputer 100 can be set to either an available state or an unused state for the various functions using the respective circuits in accordance with the set values ​​in the function setting register area. The function setting register area is not limited to the various circuits included in the game control microcomputer 100, and may be a first area for setting any function.

[0138] 10-4 shows a main setting example AKA02 of addresses included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function control register area is a second area for function control using various circuits included in the game control microcomputer 100, such as the RAM 102, the random number circuit 104, the PIP 105A, the serial communication circuit 139, etc.

[0139] In the setting example AKA02, the RWM access protection register at address FF00[H] corresponds to a setting value of 00[H] or 01[H], enabling function control to prohibit or permit access to the RAM 102, which is the RWM. The internal information register at address FF01[H] has a setting value of an invalid value corresponding to unused, and function control using the corresponding circuit is in an unused state. The internal information register can store data indicating internal information such as an abnormality in the random number update state, an abnormality in the frequency of the random number update clock, a system reset occurrence, a WDT timeout occurrence, and an IAT occurrence, but is not used as an unused state in this embodiment.

[0140] Each of the registers at addresses FF25[H] to FF28[H] can store a setting value used when controlling the serial communication function using channel SCU0 of the serial communication circuit 139 when the function is available. Each of the registers at addresses FF29[H] to FF2C[H] can store a setting value used when controlling the serial communication function using channel SCU1 of the serial communication circuit 139 when the function is available.

[0141] Each register with addresses FF60[H] to FF67[H] can store a random number value that can be acquired by using the soft latch random number acquisition function of the 16-bit random number circuit 104A. Among them, the RL0 soft latch random number register with addresses FF60[H] to FF61[H] can store a random number that can be generated by the channel RL0 of the 16-bit random number circuit 104A when the numerical data indicating the value is acquired by the soft latch. The RL1 soft latch random number register with addresses FF62[H] to FF63[H] can store a random number that can be generated by the channel RL1 of the 16-bit random number circuit 104A when the numerical data indicating the value is acquired by the soft latch. The RL2 soft latch random number register with addresses FF64[H] to FF65[H] can store a random number that can be generated by the channel RL2 of the 16-bit random number circuit 104A when the numerical data indicating the value is acquired by the soft latch. The RL3 soft latch random number register at addresses FF66[H] to FF67[H] can store random numbers that can be generated by channel RL3 provided in the 16-bit random number circuit 104A when numerical data indicating the value of the random number is acquired by the soft latch.

[0142] Each of the registers at addresses FF68[H] to FF6B[H] can store random numbers that can be acquired using the soft latch random number acquisition function of the 8-bit random number circuit 104B. Among them, the RS0 soft latch random number register at address FF68[H] can store a random number that can be generated by the channel RS0 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. The RS1 soft latch random number register at address FF69[H] can store a random number that can be generated by the channel RS1 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. The RS2 soft latch random number register at address FF6A[H] can store a random number that can be generated by the channel RS2 of the 8-bit random number circuit 104B when numerical data indicating the value is acquired by the soft latch. The RS3 soft latch random number register at address FF6B[H] can store random numbers that can be generated by channel RS3 provided in the 8-bit random number circuit 104B when numerical data indicating the value of the random number is acquired by the soft latch.

[0143] The RL0 hard latch random number register number "0" at addresses FF88[H] to FF89[H] and the RL0 hard latch random number register number "1" at addresses FF98[H] to FF99[H] can store the random numbers that the channel RL0 provided in the 16-bit random number circuit 104A can generate, when the numerical data indicating the value is acquired by the hard latch. Here, the RL0 hard latch random number register includes a plurality of storage areas corresponding to a plurality of register numbers, and different hard latch conditions can be set corresponding to the storage areas of different register numbers. For example, the RL0 hard latch random number register number "0" corresponding to the register number "0" can establish the hard latch condition when the detection signal of the game ball by the first start hole switch 22A is in the ON state. On the other hand, the RL0 hard latch random number register number "1" corresponding to the register number "1" can establish the hard latch condition when the detection signal of the game ball by the second start hole switch 22B is in the ON state. As a result, the RL0 hard latch random number register number "0" can be stored when the numerical data indicating the value of the random number MR1-1 for determining a special symbol obtained in response to the occurrence of the first start winning is obtained by the hard latch. The RL0 hard latch random number register number "1" can be stored when the numerical data indicating the value of the random number MR1-1 for determining a special symbol obtained in response to the occurrence of the second start winning is obtained by the hard latch.

[0144] Each of the registers with addresses FFF0[H] to FFF2[H] and FF35[H] can store a signal value inputted to each input port in response to the signal input function using the input port of PIP 105A being in a usable state. Among these, the input port number "0" register with address FFF0[H] can store a signal value inputted for the input port with port number "0" provided in PIP 105A. The input port number "1" register with address FFF1[H] can store a signal value inputted for the input port with port number "1" provided in PIP 105A. The input port number "2" register with address FFF2[H] can store a signal value inputted for the input port with port number "2" provided in PIP 105A. The input port number "3" register with address FF35[H] can store a signal value inputted for the input port with port number "3" provided in PIP 105A.

[0145] In this way, it is sufficient that the various circuits included in the game control microcomputer 100 are capable of controlling their respective operating states in response to the stored values ​​in the function control register area, etc. Also, the various circuits included in the game control microcomputer 100 may be capable of updating the stored values ​​in the function control register area in response to the respective operating states, etc. The function control register area is not limited to the various circuits included in the game control microcomputer 100, and may be a second area for controlling any function.

[0146] Figure 10-5 is a diagram for explaining a setting example in this embodiment for the game random numbers shown in Figure 3. The game random numbers shown in Figure 3 can be classified into random numbers used to determine the display result in the variable display of special symbols, random numbers used to determine the display result in the variable display of normal symbols, and random numbers used to determine the display mode in the variable display of special symbols and normal symbols, according to their respective uses.

[0147] FIG. 10-5(A) shows a setting example AKA11 of a game random number used to determine the display result in the variable display of a special symbol. The game random number in the setting example AKA11 includes a random number MR1-1 for determining a special symbol, a random number MR1-2 for a winning symbol, and a random number MR1-3 that is an initial value for the winning symbol. For example, the random number MR1-1 for determining a special symbol can be used to determine whether the special symbol display result is a "big win" or a "small win". The random number MR1-2 for the winning symbol can be used to determine a big win symbol designation value or a small win symbol designation value corresponding to the determined special symbol when the special symbol display result is a "big win" or a "small win". The random number MR1-3 that is an initial value for the winning symbol can be used to set the initial value of the random number MR1-2.

[0148] The range of the random number MR1-1 is the range of values ​​that can update the random number MR1-1, which is "0" to "65535". The size of the random number MR1-1 is the total number of random numbers included in the update range of the random number MR1-1, which is "65536" corresponding to the range of the random number MR1-1, "0" to "65535". Since the size of the random number MR1-1 is "65536", the total number of random numbers included in the update range is not a prime number. The number of bytes of the numerical data used to update the value of the random number MR1-1 is "2". The method of setting the maximum value of the random number MR1-1 is by initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The method of updating the random number MR1-1 is by hardware update using the 16-bit random number circuit 104A. The update condition of the random number MR1-1 is the system clock input in the 16-bit random number circuit 104A. The acquisition conditions for the random number MR1-1 include a hard latch corresponding to the start winning and a read to the random number buffer by software corresponding to the start winning. The period of the random number MR1-1 is 4.369 [ms].

[0149] The range of the random number MR1-2 is the range of values ​​that can update the random number MR1-2, which is "0" to "199". The size of the random number MR1-2 is the total number of random numbers included in the update range of the random number MR1-2, which is "200" corresponding to the range of the random number MR1-2, "0" to "199". Since the size of the random number MR1-2 is "200", the total number of random numbers included in the update range is not a prime number. The number of bytes of the numerical data used to update the value of the random number MR1-2 is "1". The method of setting the maximum value of the random number MR1-2 is by setting the immediate value of the program code. The method of updating the random number MR1-2 is the software update SA1. The update condition of the random number MR1-2 is a timer interrupt due to the passage of a predetermined time. The acquisition condition of the random number MR1-2 is reading by software corresponding to the start winning. The period of the random number MR1-2 is 800 [ms].

[0150] The range of the random number MR1-3 is the range of values ​​that can update the random number MR1-3, and is the same as the random number MR1-2, "0" to "199". The size of the random number MR1-3 is the total number of random numbers included in the update range of the random number MR1-3, and is "200" the same as the random number MR1-2, corresponding to the range of the random number MR1-3, "0" to "199". Since the size of the random number MR1-3 is "200", the total number of random numbers included in the update range is not a prime number. The number of bytes of the numerical data used to update the value of the random number MR1-3 is "1". The method of setting the maximum value of the random number MR1-3 is by setting the immediate value of the program code. The method of updating the random number MR1-3 is the software update SA2. The update conditions of the random number MR1-3 include a timer interrupt due to the passage of a predetermined time and during loop processing, which is a standby processing in the main processing P_MAIN for game control. The condition for obtaining the random number MR1-3 is that the random number MR1-2 has completed one cycle. The period of the random number MR1-3 is indefinite due to the update condition.

[0151] FIG. 10-5(B) shows a setting example AKA12 of a game random number used to determine the display result in the variable display of a normal symbol. The game random number in the setting example AKA12 includes a random number MR2-1 for a normal symbol-perfect symbol and a random number MR2-2 that is an initial value for the normal symbol-perfect symbol. For example, the random number MR2-1 for a normal symbol-perfect symbol can be used to determine a normal symbol designation value corresponding to a confirmed normal symbol as a display result of the normal symbol. The random number MR2-2 that is an initial value for the normal symbol-perfect symbol can be used when setting the initial value of the random number MR1-2.

[0152] The range of the random number MR2-1 is the range of values ​​that can update the random number MR2-1, which is "0" to "198". The size of the random number MR2-1 is the total number of random numbers included in the update range of the random number MR2-1, which is "199" corresponding to the range of the random number MR2-1, "0" to "198". Since the size of the random number MR2-1 is "199", the total number of random numbers included in the update range is a prime number. The number of bytes of the numerical data used to update the value of the random number MR2-1 is "1". The method of setting the maximum value of the random number MR2-1 is by setting an immediate value in the program code. The method of updating the random number MR2-1 is software update SA1. The update condition of the random number MR2-1 is a timer interruption due to the passage of a predetermined time. The acquisition condition of the random number MR2-1 is reading by software in response to the game ball passing through the passing gate 41 that can be configured as a normal pattern operation port. The period of the random number MR2-1 is 796 [ms].

[0153] The range of the random number MR2-2 is the range of values ​​that can update the random number MR2-2, and is the same as the random number MR2-1, "0" to "198". The size of the random number MR2-2 is the total number of random numbers included in the update range of the random number MR2-2, and is "199" the same as the random number MR2-1, corresponding to the range of the random number MR2-2, "0" to "198". Since the size of the random number MR2-2 is "199", the total number of random numbers included in the update range is a prime number. The number of bytes of the numerical data used to update the value of the random number MR2-2 is "1". The method of setting the maximum value of the random number MR2-2 is by setting the immediate value of the program code. The method of updating the random number MR2-2 is the software update SA2. The update conditions of the random number MR2-2 include a timer interrupt due to the passage of a predetermined time and during loop processing, which is a standby processing in the main processing P_MAIN for game control. The condition for obtaining the random number MR2-2 is that the random number MR2-1 has completed one cycle. The period of the random number MR2-2 is indefinite due to the update condition.

[0154] FIG. 10-5(C) shows a setting example AKA13 of a game random number used to determine the display mode in the variable display of a special pattern or a normal pattern. The game random number in the setting example AKA13 includes a random number MR3-1 for a normal pattern variable pattern, a random number MR3-2 for selecting a miss effect, a random number MR3-3 for selecting a variable pattern type, and a random number MR3-4 for a variable pattern. For example, the random number MR3-1 for a normal pattern variable pattern can be used to determine a normal pattern variable pattern corresponding to the variable display of a normal pattern. The random number MR3-2 for selecting a miss effect can be used to determine a variable display mode corresponding to the variable display of a special pattern whose special pattern display result is "miss". The random number MR3-3 for selecting a variable pattern type can be used to select a variable pattern type corresponding to the variable display of a special pattern. The random number MR3-4 for a variable pattern can be used to determine a variable pattern corresponding to the variable display of a special pattern.

[0155] The range of the random number MR3-1 is the range of values ​​that can update the random number MR3-1, which is "0" to "232". The size of the random number MR3-1 is the total number of random numbers included in the update range of the random number MR3-1, which is "233" corresponding to the range of the random number MR3-1, "0" to "232". Since the size of the random number MR3-1 is "233", the total number of random numbers included in the update range is a prime number. The number of bytes of the numerical data used to update the value of the random number MR3-1 is "1". The method of setting the maximum value of the random number MR3-1 is by initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The method of updating the random number MR3-1 is by hardware update using the 8-bit random number circuit 104B. The update condition of the random number MR3-1 is the system clock input in the 8-bit random number circuit 104B. The acquisition condition of the random number MR3-1 is the start of variation in the variable display of the normal pattern. The period of the random number MR3-1 is 0.249 [ms].

[0156] The range of the random number MR3-2 is the range of values ​​that can update the random number MR3-2, which is "0" to "65518". The size of the random number MR3-2 is the total number of random numbers included in the update range of the random number MR3-2, which is "65519" corresponding to the range of the random number MR3-2, "0" to "65518". Since the size of the random number MR3-2 is "65519", the total number of random numbers included in the update range is a prime number. The number of bytes of the numerical data used to update the value of the random number MR3-2 is "2". The method of setting the maximum value of the random number MR3-2 is by initial setting of a register provided corresponding to the 16-bit random number circuit 104A. The method of updating the random number MR3-2 is by hardware update using the 16-bit random number circuit 104A. The update condition of the random number MR3-2 is the system clock input in the 16-bit random number circuit 104A. The condition for obtaining the random number MR3-2 is to read it into the random number buffer by software corresponding to the start winning. The period of the random number MR3-2 is 139.774 [ms].

[0157] The range of the random number MR3-3 is the range of values ​​that can update the random number MR3-3, which is "0" to "240". The size of the random number MR3-3 is the total number of random numbers included in the update range of the random number MR3-3, which is "241" corresponding to the range of the random number MR3-3, "0" to "240". Since the size of the random number MR3-3 is "241", the total number of random numbers included in the update range is a prime number. The number of bytes of the numerical data used to update the value of the random number MR3-3 is "1". The method of setting the maximum value of the random number MR3-3 is by initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The method of updating the random number MR3-3 is by hardware update using the 8-bit random number circuit 104B. The update condition of the random number MR3-3 is the system clock input in the 8-bit random number circuit 104B. The condition for obtaining the random number MR3-3 is to read it into the random number buffer by software corresponding to the start winning. The period of the random number MR3-3 is 0.257 [ms].

[0158] The range of the random number MR3-4 is the range of values ​​that can update the random number MR3-4, which is "0" to "250". The size of the random number MR3-4 is the total number of random numbers included in the update range of the random number MR3-4, which is "251" corresponding to the range of the random number MR3-4, "0" to "250". Since the size of the random number MR3-4 is "251", the total number of random numbers included in the update range is a prime number. The number of bytes of the numerical data used to update the value of the random number MR3-4 is "1". The method of setting the maximum value of the random number MR3-4 is by initial setting of a register provided corresponding to the 8-bit random number circuit 104B. The method of updating the random number MR3-4 is by hardware update using the 8-bit random number circuit 104B. The update condition of the random number MR3-4 is the system clock input in the 8-bit random number circuit 104B. The condition for obtaining the random number MR3-4 is to read it into the random number buffer by software corresponding to the start winning. The period of the random number MR3-4 is 0.268 [ms].

[0159] The software update SA1, which is a method of updating the random numbers MR1-2 and MR2-1, can be updated so that the previous value is added by 1 each time the software update process is executed. At this time, if the updated value exceeds the maximum random number value, it is changed to "0" as the minimum random number value. Also, if the updated value matches the random number initial value, the current random number value is set using the random number that is the corresponding initial value, and stored as a new random number initial value. For example, for the random number MR1-2, if the updated value matches the random number initial value, the current random number value is set using the random number MR1-3 that is the initial value for the winning symbol, and the random number value is stored as a new random number initial value. For the random number MR2-1, if the updated value matches the random number initial value, the current random number value is set using the random number MR2-2 that is the initial value for the winning symbol of the normal symbol, and the random number value is stored as a new random number initial value.

[0160] The software update SA2, which is a method of updating the random numbers MR1-3 and MR2-2, can update the previous value by adding 1 each time the software update process is executed. If the updated value exceeds the maximum random number value, it is changed to "0", the minimum random number value. In this case, unlike the software update SA1, the random number initial value is not used, so the updated value is either the previous value plus 1 or the minimum random number value "0".

[0161] FIG. 10-6 is a diagram for explaining a random number update period when a random number value is updated using the 16-bit random number circuit 104A or the 8-bit random number circuit 104B included in the random number circuit 104. Here, the random number that can be generated by the channels RL0 to RL4 provided in the 16-bit random number circuit 104A is defined as a 16-bit random number RLn. Also, the random number that can be generated by the channels RS0 to RS4 provided in the 8-bit random number circuit 104B is defined as an 8-bit random number RSn. The period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A completes one cycle is determined by a different relational expression depending on whether or not the maximum value of the 16-bit random number RLn is a specific maximum value expressed by a power of two. The period in which the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B completes one cycle is determined by a different relational expression depending on whether or not the maximum value of the 8-bit random number RSn is a specific maximum value expressed by a power of two.

[0162] FIG. 10-6(A) shows a 16-bit random number period setting example AKA21 in the 16-bit random number circuit 104A. The 16-bit random number period is a period in which the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A completes one cycle. In the 16-bit random number period setting example AKA21, the maximum value of the 16-bit random number RLn is 2 when m=9 to 16. m When m corresponds to -1, the period in which the 16-bit random number sequence goes round is the inverse of the count clock frequency, i.e., proportional to the count clock period. The maximum value is then increased by 1, i.e., it is a linear function with the magnitude of the 16-bit random number RLn as a variable. On the other hand, when the maximum value of the 16-bit random number RLn is any of m=9 to 16, the period is 2 mIf it does not correspond to -1, the period in which the 16-bit random number sequence goes round is proportional to the inverse of the count clock frequency, i.e., 32 times the count clock period. It is then a linear function with the maximum value plus 1, i.e., the magnitude of the 16-bit random number RLn, as a variable. In this way, when the maximum value of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, i.e., the update speed of the random number value is faster.

[0163] FIG. 10-6(B) shows an example AK22 of setting an 8-bit random number period in the 8-bit random number circuit 104B. The 8-bit random number period is a period in which the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B completes one cycle. In the example AK22 of setting an 8-bit random number period, the maximum value of the 8-bit random number RSn is 2 when m=5 to 8. m When m corresponds to -1, the period in which the 8-bit random number sequence goes round is the inverse of the count clock frequency, i.e., proportional to the count clock period. The maximum value is then increased by 1, i.e., it is a linear function with the magnitude of the 8-bit random number RSn as a variable. In contrast, when the maximum value of the 8-bit random number RSn is any of m=5 to 8, the period is 2 m If it does not correspond to -1, the period in which the 8-bit random number sequence goes round is proportional to the inverse of the count clock frequency, i.e., 16 times the count clock period. It is then a linear function with the maximum value plus 1, i.e., the magnitude of the 8-bit random number RSn, as a variable. In this way, when the maximum value of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is a specific maximum value, the random number update period is shorter than when the maximum value is other than the specific maximum value, i.e., the update speed of the random number value is faster.

[0164] FIG. 10-6(C) shows a comparative random number example AKA23 that compares the random number values ​​that can be updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B. The 16-bit random number circuit 104A can update the random number values ​​corresponding to the random number MR1-1 for determining a special symbol and the random number MR3-2 for selecting a losing performance. The 8-bit random number circuit 104B can update the random number values ​​corresponding to the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for a variation pattern.

[0165] The maximum value of the random number MR1-1 is "65535", and the 2 m This corresponds to -1. As a result, the period of the random number MR1-1 is 4.369 [ms], and the update speed at this time is 15000 [times / ms]. The maximum value of the random number MR3-2 is "65518", and the 2 m -1 is also not supported. As a result, the period of the random number MR3-2 is 139.774 [ms], and the update speed at this time is 469 [times / ms]. The maximum value of the random number MR3-3 is "240", and the 2 m -1 is also not supported. As a result, the period of the random number MR3-3 is 0.257 [ms], and the update speed at this time is 938 [times / ms]. The maximum value of the random number MR3-4 is "250", and the 2 m -1 is also not supported. As a result, the period of the random number MR3-4 is 0.268[ms], and the update speed is 938[times / ms].

[0166] In this way, the game random numbers that can be updated by the 16-bit random number circuit 104A include the random number MR1-1 for determining the special symbol and the random number MR3-2 for selecting the miss effect. The number of bytes of the numerical data of both of these random numbers MR1-1 and MR3-2 is "2", and the number of bytes is a specific number of 2 bytes. Since the size of the random number MR1-1 is "65536" and the size of the random number MR3-2 is "65519", if the total number of random numbers included in the update range of the random number MR1-1 is a specific number, the total number of random numbers included in the update range of the random number MR3-2 is a predetermined number smaller than the specific number. The update speed of the random number MR1-1 is 15000 [times / ms] and the update speed of the random number MR3-2 is 469 [times / ms], so the update speed of the random number MR1-1 is faster than that of the random number MR3-2. This suppresses the occurrence of synchronization of the random number values ​​and enables appropriate update of the random number values.

[0167] Furthermore, the game random numbers that can be updated by the 16-bit random number circuit 104A include a random number MR3-2 for selecting a losing performance. The game random numbers that can be updated by the 8-bit random number circuit 104B include a random number MR3-3 for selecting a variation pattern type and a random number MR3-4 for a variation pattern. The total number of random numbers included in the update range of each of these random numbers MR3-2 to MR3-4 is a prime number. The update speed of the random number MR3-2 is 469 [times / ms], while the update speed of the random numbers MR3-3 and MR3-4 is 938 [times / ms]. In other words, the update speed of the random numbers MR3-3 and MR3-4 is two times the update speed of the random number MR3-2, which is an integer multiple. Therefore, when the random number MR3-2 is the first random number value, and the random numbers MR3-3 and MR3-4 are the second random number values, the first random number value has an update speed of the first speed, and the second random number value has an update speed of the second speed, which is an integer multiple of the first speed. The update range of the random number MR3-2 is "0" to "65518", the update range of the random number MR3-3 is "0" to "240", and the update range of the random number MR3-4 is "0" to "250", so the total number of random number values ​​included in each update range is different between the first random number value and the second random number value, and the total number of random number values ​​included in each update range is a prime number. This makes it possible to suppress the occurrence of synchronization of random number values ​​and to update the random number values ​​appropriately.

[0168] The CPU 103 is provided with a plurality of registers, such as a program counter, an interrupt register, a stack pointer, an index register, a flag register, an address register, and a general-purpose register including an accumulator. The index register, the flag register, and the general-purpose register may be provided with a main register and a sub-register. The registers included in the main register and the sub-register, and the stack pointer may be provided so as to be able to configure a plurality of register banks. The plurality of register banks may include a first register bank for use within an area that can be used when executing a game program, and a second register bank for use outside the area that can be used when executing a non-game program. This makes it unnecessary to save values ​​stored in the general-purpose registers, etc., to the stack area or restore them from the stack area when switching between a game program and a non-game program, for example, and thus makes it possible to prevent an increase in the amount of programs and processing load.

[0169] The program counter is used to hold the address value of the next instruction to be executed by the CPU 103, and is also called a PC register. The stored value of the program counter is counted up each time an instruction is executed, and the address value of the branch destination of a branch instruction is set. The interrupt register can hold the upper address value of the interrupt vector table, and is also called an I register. The stored value of the I register is set in response to the start of power supply to the pachinko game machine 1.

[0170] The stack pointer can hold an address value corresponding to the game stack area or the non-game stack area, and is also called the SP register. The stored value of the stack pointer can specify a destination address for saving and holding a stored value or immediate value in a predefined register including the program counter or a register specified by an instruction in response to an interrupt occurrence, execution of a PUSH instruction, execution of a subroutine call instruction such as a CALL instruction, a CALLF instruction, or a RST instruction, and is updated to a value indicating the top address of the storage area holding the stored value upon saving. The stored value of the stack pointer can also specify a read address for restoring the saved stored value of a register in response to the end of an interrupt process, execution of a POP instruction, the end of a subroutine process, and is updated to a value indicating the address corresponding to the readout of the stored value upon the return. In addition, the stored value of the stack pointer can be set to a stored value or immediate value of a register specified by a load instruction such as an LD instruction.

[0171] The index register includes the IX register and the IY register, which have a storage capacity of 2 bytes and can store 16-bit data. The accumulator is also called the A register. Other general-purpose registers include multiple registers, such as the B register, C register, D register, E register, H register, and L register, which have a storage capacity of 1 byte and can store 8-bit data. The B register and the C register can be used as the BC register of a pair of registers that can store 16-bit data. The D register and the E register can be used as the DE register of a pair of registers that can store 16-bit data. The H register and the L register can be used as the HL register of a pair of registers that can store 16-bit data.

[0172] The internal registers of CPU 103 can update stored values ​​in response to calculation instructions and transfer instructions executed by CPU 103, and are used to specify program addresses, data addresses, or built-in register addresses provided in the game control microcomputer 100, to hold calculation data and transfer data, etc.

[0173] In the game control microcomputer 100, the instruction set for making the CPU 103 execute a program includes transfer instructions such as a load instruction, subroutine call instructions, jump instructions, other operation instructions including arithmetic operation instructions and logical operation instructions, input / output instructions, etc. Computer programs such as game programs and non-game programs executable by the CPU 103 are prepared in advance as program codes that describe these various instructions, and are stored in the ROM 101.

[0174] The load instruction is a transfer instruction that can be used in the following cases: when data read from the memory area or built-in device area of ​​ROM 101 or RAM 102 is stored and set in the internal register of CPU 103; when a value stored in the internal register of CPU 103 is written and stored in the memory area or built-in device area of ​​RAM 102; and when a numerical value specified by an operand is set or stored as an immediate value in the internal register of CPU 103 or the memory area or built-in device area of ​​RAM 102. The target to which data is transferred by the load instruction can be specified according to the instruction code or operand, and generally includes the source and destination of the data. However, when an immediate value is specified by the operand, the source of the data is not included.

[0175] The load instructions include a normal LD ​​instruction, a special LDQ instruction, a special LDF instruction, and a special ICPLD instruction. The normal LD ​​instruction is also called a normal transfer instruction. The special LDQ instruction is also called a first special transfer instruction. The special LDF instruction is also called a second special transfer instruction. The special ICPLD instruction is also called a third special transfer instruction.

[0176] The LD instruction, which is a normal transfer instruction, is a normal transfer instruction that can transfer data by specifying both a high-order address and a low-order address when transferring data to a storage area or built-in device area of ​​ROM 101 or RAM 102. Also, the LD instruction, which is a normal transfer instruction, can transfer data by specifying the destination or source address by using a pointer, by using a pair register such as the HL register as a pointer, when transferring data to a storage area or built-in device area of ​​ROM 101 or RAM 102.

[0177] The LDQ instruction, which is the first special transfer instruction, can transfer data by specifying only the lower address using the Q register, which is a special register included in the internal registers of the CPU 103. A stored value indicating a higher address is preset in the Q register, and by combining this with the lower address specified by the LDQ instruction, it is possible to specify the destination or source address and transfer data.

[0178] The LDQ instruction, which is the first special transfer instruction, can transfer data with a smaller amount of program code than the LD instruction, which is the normal transfer instruction. However, in a program that frequently changes the stored value in the Q register, the amount of program code may increase more than the normal LD ​​instruction. Therefore, it is sufficient to be able to execute data transfer using the LDQ instruction, which is the first special transfer instruction, in response to processing that requires transferring various data multiple times to the game work area at addresses F000[H] to F0D7[H], the function setting register area at addresses FE00[H] to FEBF[H], and the function control register area at addresses FF00[H] to FFFF[H].

[0179] The LDF command, which is the second special transfer command, can transfer data by specifying only the lower address of the stored data in a specific address range. The specific address range is, for example, the range of addresses 1200[H] to 1DFF[H]. Therefore, by setting the game data area of ​​ROM 101 in advance to be included in this specific address range and combining it with the lower address specified by the LDF command, it is possible to specify the address of the transfer source and transfer the data. Note that the game data area of ​​ROM 101 is read-only and cannot be written, so the address of the game data area is never specified as the transfer destination address.

[0180] The second special transfer instruction, the LDF instruction, can transfer data with a smaller amount of program code than the normal transfer instruction, the LD instruction. However, since the specific address range is fixed by specification, it is sufficient to set the storage area of ​​frequently used data, such as the game data area of ​​ROM 101, to be included in the specific address range and to be able to transfer data using the second special transfer instruction, the LDF instruction.

[0181] The ICPLD instruction, which is the third special transfer instruction, compares the update target value with a comparison judgment value, and updates the update target value by adding 1 if the update target value is less than the comparison judgment value, whereas it changes the update target value to the minimum value "0" if the update target value is equal to or greater than the comparison judgment value. The update target value may be a value indicated by the stored data at the address pointed to by the pointer, or may be a value stored in a register. The comparison judgment value may be a value stored in a register, or may be a value indicated by the operand of the ICPLD instruction.

[0182] In this way, the third special transfer instruction, the ICPLD instruction, is a single compare and add instruction that includes comparing the update target value with the comparison judgment value, adding 1 to the update target value if the comparison result is less than the comparison judgment value, and changing the update target value to the minimum value if the comparison result is equal to or greater than the comparison judgment value.

[0183] Setting a stored value in an internal register of CPU 103 using an immediate value based on an operand of a transfer command is also called "set." Reading out stored data in the game data area of ​​ROM 101 or the game work area of ​​RAM 102 and storing it in an internal register of CPU 103 is also called "load." Storing a stored value in an internal register of CPU 103 in a buffer, counter, timer, or any other storage area provided in the game work area of ​​RAM 102 is also called "store."

[0184] FIG. 10-7 is a flow chart showing an example of the power supply start response processing P_POWER_ON. The power supply start response processing P_POWER_ON is included in the processing that can be called from the main processing P_MAIN for game control shown in FIG. 4, and can be executed in step S1 in response to the start of power supply in the pachinko game machine 1. When the CPU 103 executes the power supply start response processing P_POWER_ON, it sets interrupt prohibition (step AKS1) and then sets the in-area stack pointer initial value to the stack pointer (step AKS2). The in-area stack pointer initial value may be an address F200[H] obtained by adding 1 to the final address of the game stack area, corresponding to the initial state in which no saved data is stored in the game stack area.

[0185] Following step AKS2, a connection confirmation signal ON output value is set by a transfer command for setting the internal register of CPU103 (step AKS3). The connection confirmation signal ON output value is a value indicating that the connection confirmation signal is ON, and may be, for example, 00[H]. At this time, a function control register upper address is set in the Q register by a transfer command for setting the Q register included in the internal register of CPU103 (step AKS4). The function control register upper address is a value FF[H] indicating the upper address of the function control register area in the setting example AKA02 shown in FIG. 10-4. When the function control register upper address is set in this way, a connection confirmation signal ON output value is stored by a transfer command using the upper address indicated by the stored value of the Q register (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer command. The stored value of the Q register is set to the upper address of the function control register area by step AKS4. Therefore, the connection confirmation signal ON output value set in step AKS3 can be stored in the function control register of the specified address in the function control register area by a transfer command for writing to the memory area of ​​the specified address, such as a special 2-byte LDQ command that specifies a lower address. In step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. As a result, the connection confirmation signal transmitted from the main board 11 to the dispensing control board is set to the ON state.

[0186] When the connection confirmation signal is set to the ON state in step AKS5, the SCU0 command register clear output value is stored by a transfer command using the upper address indicated by the stored value of the Q register (step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer command. The stored value of the Q register is set to the upper address of the function control register area in step AKS4. The SCU0 command register clear output value can be specified by the operand of the transfer command. Therefore, the SCU0 command register clear output value can be stored in the function control register of the specified address in the function control register area by a transfer command for writing to a memory area of ​​a specified address, such as a 3-byte special LDQ command that specifies a lower address and the SCU0 command register clear output value. In step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register provided at address FF28[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using the channel SCU0 of the serial communication circuit 139 is controlled to the initial state.

[0187] After step AKS6, the SCU1 command register clear output value is stored by a transfer command using the upper address indicated by the stored value of the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer command. The stored value of the Q register is set to the upper address of the function control register area by step AKS4. The SCU1 command register clear output value can be specified by the operand of the transfer command. Therefore, the SCU1 command register clear output value can be stored in the function control register of the specified address in the function control register area by a transfer command for writing to a memory area of ​​a specified address, such as a 3-byte special LDQ command specifying a lower address and the SCU0 command register clear output value. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register provided at address FF2C[H] of the function control register area in the setting example AKA02 shown in FIG. 10-4. As a result, the serial communication function using the channel SCU1 of the serial communication circuit 139 is controlled to the initial state.

[0188] When these serial communication functions are controlled to the initial state, a transfer command for setting the internal register of CPU 103 sets the interrupt vector table upper address (step AKS8). The interrupt vector table upper address is the upper address of the interrupt vector table provided in the game program area of ​​ROM 101. The interrupt vector table stores the top address at a table position corresponding to the interrupt priority for timer interrupt processing P_PCT for game control, which is executed in response to the occurrence of a timer interrupt, for example. Such an interrupt vector table upper address is set in the I register by a transfer command for setting the internal register of CPU 103 (step AKS9).

[0189] After step AKS9, the stored value of the Q register is updated to subtract 1 (step AKS10). The stored value of the Q register was set to the upper address of the function control register area by step AKS4. When this stored value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in FIG. 10-3 is stored in the Q register. In this way, after the function control register provided in the function control register area is set, the function setting register provided in the function setting register area is made settable. At this time, a transfer command for setting a pointer is used to set a function setting register stored value table address (step AKS11). The function setting register stored value table address is the address of the function setting register stored value table stored in the game data area of ​​the ROM101. Then, a transfer command for reading out the stored data of the address pointed to by the pointer is used to load the number of processes (step AKS12). Also, a function setting register store command is used to set the function setting register stored value table (step AKS13). The function setting register store instruction may be an instruction to specify a function setting register based on stored data at an address obtained by adding 1 to the address pointed to by the pointer, to store in the specified function setting register a function setting register setting value indicated by stored data at an address obtained by adding 2 to the address pointed to by the pointer, to add 2 to the stored value of the pointer, and to subtract 1 from the processing count, repeating this process until the processing count becomes 0. In this way, the function setting register can be initially set.

[0190] When the initial setting of the function setting register is completed in step AKS13, an access permission output value is stored in the RWM access protection register (step AKS14). The access permission output value of the RWM access protection register is set to, for example, 01 [H] by a transfer command for setting the internal register of the CPU 103. Such an access permission output value is stored in the RWM access protection register by a transfer command for writing to a storage area of ​​the top address in the function setting register area. The RWM access protection register enables function control to allow access to the RAM 102, which is the RWM, in response to the setting of the access permission output value 01 [H]. Therefore, by storing the access permission output value in the RWM access protection register in step AKS14, access to the RAM 102 is permitted in response to the start of power supply in the pachinko game machine 1.

[0191] After step AKS14, the upper address of the game work area, which is the work area of ​​RAM102, is set in the Q register (step AKS15), and the power supply start response process P_POWER_ON is terminated. In this way, after access to RAM102 is permitted by step AKS14, a value F0[H] indicating the upper address of the game work area in RAM102 is set in the Q register. After step AKS15, when the LDQ command, which is the first special transfer command, is executed, the value F0[H] stored in the Q register can be used as the upper address of the transfer destination or transfer source without being specified by an operand. This reduces the program capacity of the process using the game work area in RAM102, and improves the marketability of the gaming machine.

[0192] FIG. 10-8 shows a configuration example AKT01 of a function setting register storage value table used in the power supply start response process P_POWER_ON. In the power supply start response process P_POWER_ON, for example, the function setting register storage table whose address is set in step AKS11 is used to load the number of processes in step AKS12, and the stored values ​​of each function setting register are stored by a function setting register store command in step AKS13. In the function setting register storage value table of the configuration example AKT01, a value 18 [H] indicating the number of processes is stored at a top address 1200 [H]. In step AKS12, this table data is read and loaded into an internal register of the CPU 103. After that, the function setting register store command in step AKS13 sequentially reads table data combining the lower addresses and stored values ​​of the function setting registers, and enables the stored values ​​to be stored in the function setting registers corresponding to each lower address.

[0193] In the function setting register storage value table of the configuration example AKT01, the table data is configured so that the stored value of the function setting register with a smaller value indicating the lower address can be set first, and the stored value of the function setting register with a larger value indicating the lower address can be set later. As a result, in the function setting register area, the stored values ​​of the function setting registers are set in the order of the stored value of the function setting register closest to the top address being set first, and the stored value of the function setting register closest to the last address being set later. This makes it easier to design and manage the data indicating the stored values ​​of the function setting registers, and improves the marketability of the gaming machine.

[0194] The 16-bit random number circuit 104A can start updating from the channel whose maximum value setting register is set to a value indicating the maximum random number value corresponding to the four channels RL0 to RL3. The 8-bit random number circuit 104B can start updating from the channel whose maximum value setting register is set to a value indicating the maximum random number value corresponding to the four channels RS0 to RS3. The function setting register area of ​​the setting example AKA01 shown in FIG. 10-3 includes an RL0 maximum value setting register at addresses FE3F[H] to FE40[H], an RL1 maximum value setting register at addresses FE41[H] to FE42[H], an RL2 maximum value setting register at addresses FE43[H] to FE44[H], and an RL3 maximum value setting register at addresses FE45[H] to FE46[H], which correspond to the four channels RL0 to RL3 in the 16-bit random number circuit 104A. In addition, this function setting register area includes an RS0 maximum value setting register at address FE47[H], an RS1 maximum value setting register at address FE48[H], an RS2 maximum value setting register at address FE49[H], and an RS3 maximum value setting register at address FE4A[H], which correspond to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. In the function setting register storage value table of the configuration example AKT01, the table data is configured such that, among these maximum value setting registers, the stored value of the RL0 maximum value setting register is set first, the stored value of the RL2 maximum value setting register is set next, the stored value of the RS1 maximum value setting register is set next, the stored value of the RS2 maximum value setting register is set next, and the RS3 maximum value setting register is set last. Therefore, the update of channel RL0 in the 16-bit random number circuit 104A is started first, the update of channel RL2 in the 16-bit random number circuit 104A is started next, the update of channel RS1 in the 8-bit random number circuit 104B is started next, the update of channel RS2 in the 8-bit random number circuit 104B is started next, and the update of channel RS3 in the 8-bit random number circuit 104B is started last. In this way, since the updates start in order from the random value with the maximum random number value set, the uncertainty of the random value is increased depending on the timing at which the update of the random value is started, and the processing load is reduced, enabling appropriate update of the random value.

[0195] The power supply start response process P_POWER_ON is included in the process that can be called from the main process P_MAIN for game control, which is a startup process executed based on the start of power supply in the pachinko game machine 1, and makes it possible to set a stored value in the function setting register area as a storage area for functions using the function setting register storage value table of the configuration example AKT01. At this time, since the maximum random number value of the random number value updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, the power supply start response process P_POWER_ON can be executed as a maximum value setting process. The 16-bit random number circuit 104A can update a first random number value consisting of 16 bits corresponding to 2 bytes as a specific byte number. The 8-bit random number circuit 104B can update a second random number value consisting of 8 bits corresponding to 1 byte as a predetermined byte number smaller than the specific byte number. Then, when executing the power supply start response process P_POWER_ON, the function setting register stored value table of the configuration example AKT01 is used to set the maximum value of the first random number value that can be updated by the 16-bit random number circuit 104A, and then set the maximum value of the second random number value that can be updated by the 8-bit random number circuit 104B. In this way, by setting the first random number value of a specific number of bytes and then setting the second random number value of a predetermined number of bytes, the first random number value and the second random number value can be stably updated, making it possible to update the random number values ​​appropriately.

[0196] Figure 10-9 shows an example of the configuration of the RWM access protection register. The RWM access protection register is provided at address FF00[H] in the configuration example AKA02 of the function control register area shown in Figure 10-4. The value stored in the RWM access protection register is different depending on whether access to the RAM 102, which is the RWM, is prohibited or permitted.

[0197] Figure 10-9(A) shows an example of the bit configuration of the RWM access protection register. The RWM access protection register can store 8-bit data RAP with bit numbers from "0" to "7", and bit data RAP0 with bit number "0" can be set to 0[B] or 1[B]. In contrast, bit data from bit number "1" to bit number "7" are always set to 0[B], indicating a fixed value that is never set to "1".

[0198] FIG. 10-9(B) is a diagram for explaining an example of use of the bit data RAP of the RWM access protection register. In the bit data RAP, the bit data RAP0 with bit number "0" is an RWM access control bit, and a setting of 0[B] prohibits access to the RWM, and a setting of 1[B] permits access to the RWM. In response to the start of power supply to the pachinko gaming machine 1, the bit data RAP0 with bit number "0" is set to an initial value of 0[B]. This makes it possible to prohibit access to the RAM 102, which becomes the RWM, in response to the start of power supply to the pachinko gaming machine 1.

[0199] FIG. 10-10 is a flow chart showing an example of power-off processing P_POWER_OFF. Power-off processing P_POWER_OFF is included in the processing that can be called from timer interrupt processing P_PCT for game control shown in FIG. 5, and can be executed in step S51 every time a timer interrupt occurs. When executing power-off processing P_POWER_OFF, CPU 103 sets the backup monitoring timer address by a transfer command for setting a pointer (step AKS31). The backup monitoring timer address is the address of the backup monitoring timer provided in the game work area of ​​RAM 102.

[0200] Input port number "3" is input (step AKS32). Input port number "3" is an input port to which "3" is assigned as the port number, and includes a power check signal input bit. Therefore, a logical AND operation is performed using the input data of input port number "3" and the check data corresponding to the bit position of the power check signal input bit. At this time, it is determined whether the power check signal input bit is "0" or not depending on whether the zero flag is on or not (step AKS33). When the bit value of the power check signal input bit is 0 [B] corresponding to "0", it indicates that the power check signal is in the off state, and when the bit value is 1 [B] corresponding to "1", it indicates that the power check signal is in the on state.

[0201] If the power supply confirmation signal input bit is "1" rather than "0" (step AKS33; No), backup monitoring timer clear data is stored by a transfer command capable of updating the stored data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing the clear data in the backup monitoring timer, the backup monitoring timer can be cleared when the power supply confirmation signal is in the ON state, in correspondence with a state other than the power cut-off determination being made.

[0202] When the power supply confirmation signal input bit is "0" in response to step AKS33 (step AKS33; Yes), the backup monitoring timer is updated to add 1 to the time value (step AKS35). Also, the backup monitoring timer is loaded by a transfer command for reading the stored data of the address pointed to by the pointer (step AKS36). Then, by a calculation return command capable of comparing the time value of the backup monitoring timer with the judgment value corresponding to the backup judgment time (step AKS37), it is confirmed that the backup monitoring timer does not indicate the backup judgment time (step AKS38). This calculation return command enables the power off process to be terminated and the return to the special symbol process process in response to a zero flag that is turned off when the time value of the backup monitoring timer and the judgment value corresponding to the backup judgment time are different. Thus, when the backup monitoring timer does not indicate the backup judgment time (step AKS38; Yes), the power off process is terminated.

[0203] When the backup monitoring timer indicates the backup determination time in response to step AKS38 (step AKS38; No), a checksum calculation process P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC in step AKS39 may be a process common to the checksum calculation process included in the RWM check process P_RWM_CHK in step S2 in the main process P_MAIN for game control shown in FIG. 4. In this way, by executing a common checksum calculation process in response to the start and stop of power supply in the pachinko game machine 1, it becomes possible to determine whether or not recovery by backup data is possible depending on whether the memory contents in the game work area of ​​the RAM 102 are retained without change. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer command for writing to the memory area of ​​the address pointed to by the pointer (step AKS40).

[0204] After step AKS40, the clear data is set to the output value data by an exclusive OR operation instruction (step AKS41). This exclusive OR operation instruction operates the exclusive OR of the stored values ​​of a single register, so that all bit values ​​become the exclusive OR of the same values, and the stored value can be initialized to the clear data of 00 [H]. Such clear data is stored in the RWM access protection register by a transfer instruction for writing to a memory area of ​​the top address in the function setting register area (step AKS42). The RWM access protection register enables function control to prohibit access to the RAM 102, which is the RWM, in response to the setting of the clear data, 00 [H]. Therefore, by storing the clear data in the RWM access protection register by step AKS42, access to the RAM 102 is prohibited in response to the stop of the power supply to the pachinko game machine 1.

[0205] After step AKS42, the output port numbers "0" to "10" are cleared (step AKS43). The output port numbers "0" to "10" are output ports with port numbers "0" to "10", and are all the output ports in the game control microcomputer 100. Therefore, in response to the stop of the power supply in the pachinko game machine 1, all the output ports in the game control microcomputer 100 are set to a clear state by step AKS43. At this time, a connection confirmation signal off output value is set by a transfer command for setting the internal register of the CPU 103 (step AKS44). The connection confirmation signal off output value is a value indicating that the connection confirmation signal is in an off state, and may be, for example, 01 [H]. Such a connection confirmation signal off output value is stored in the output port number "1" register by a transfer command for writing it in a memory area of ​​a specified address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to an off state.

[0206] Following step AKS45, a PTC0 interrupt inhibit output value is set by a transfer command for setting an internal register of the CPU 103 (step AKS46). The PTC0 interrupt inhibit output value is an output value for inhibiting the occurrence of a timer interrupt using the channel PTC0 of the timer circuit 136. This PTC0 interrupt inhibit output value is stored in the PTC0 control register by a transfer command for writing to a function setting register at a specified address in the function setting register area (step AKS47). The PTC0 control register can set the usage state of the timekeeping function using the channel PTC0 of the timer circuit 136. In step AKS47, the PTC0 interrupt inhibit output value set in step AKS46 is stored in the PTC0 control register, and thus the timer interrupt for game control is set to the inhibited state in response to the stop of power supply in the pachinko game machine 1.

[0207] When the setting corresponding to the lapse of the backup determination time is performed, the process moves to a standby state by executing a loop process. In this standby state, the input port number "3" is input (step AKS48), and it is determined whether the power supply confirmation signal input bit is "0" or not (step AKS49). If the power supply confirmation signal is in the OFF state and the power supply confirmation signal input bit is "0" (step AKS49; Yes), the loop process returning to step AKS48 is continued. In this way, by maintaining the standby state until the operation is stopped due to a power cut in response to a power supply cut in the pachinko game machine 1, it is possible to prevent inconvenient changes to stored data and runaway processing by the CPU 103.

[0208] When the power check signal input bit is "1" and not "0" in response to step AKS49 (step AKS49; No), the power interruption recovery vector table address is set in the stack pointer (step AKS50), and then the power interruption processing P_POWER_OFF is terminated by the interrupt return command. The power interruption recovery vector table address is the address of the power interruption recovery vector table provided in the game program area of ​​ROM 101. The interrupt return command can use the stack pointer as a pointer to set the stored data of the storage area indicated by the address specified by the stored value of the stack pointer to the program counter. For example, the stored data of the storage area indicated by the address specified by the stored value of the stack pointer is set to the lower byte of the program counter, and the stored data of the storage area indicated by the address specified by the value obtained by adding 1 to the stored value of the stack pointer is set to the upper byte of the program counter.

[0209] FIG. 10-11 is a diagram for explaining an example of the use of data configuration related to the power-off process P_POWER_OFF. In the power-off process P_POWER_OFF, for example, step AKS38 executes branch processing using the time value of the backup monitoring timer, and step AKS40 saves checksum data using the checksum buffer. In addition, step AKS50 sets a vector table address at the time of power-off recovery, so that if the operation does not stop after the power supply stop is detected in the pachinko game machine 1 and normal power supply is resumed, the game control program can be executed from the beginning. In this way, the power-off process P_POWER_OFF enables control when the power supply to the pachinko game machine 1 is stopped using the backup monitoring timer, the checksum buffer, and the power-off recovery vector table.

[0210] FIG. 10-11(A) shows a configuration example AKB01 of a memory area that serves as a backup data area. The backup data area of ​​the configuration example AKB01 can store backup setting data used when backing up the stored data in the game work area of ​​the RAM 102. This backup data area includes a backup monitoring timer at address F000[H] and a checksum buffer at address F0DE[H]. Address F000[H] is the start address of the game work area, and address F0DE[H] is the end address of the game work area. In this way, by providing a backup data area at the start address and the end address of the game work area, it is possible to appropriately back up the stored data in the game work area of ​​the RAM 102.

[0211] FIG. 10-11(B) shows a configuration example AKT11 of the power interruption recovery vector table. The power interruption recovery vector table of the configuration example AKT11 can specify a return address from the power interruption process in response to an interrupt return command when normal power supply is resumed. The power interruption recovery vector table includes, as table data, lower address designation data 00[H] stored at address 0016[H] in the game program area of ​​ROM101 and upper address designation data 00[H] stored at address 0017[H] in the game program area of ​​ROM101. In step AKS50 of the power interruption process P_POWER_OFF, data indicating address 0016[H] is set in the stack pointer as the power interruption recovery vector table address. After that, the stored value of the program counter is set to 0000[H] by the interrupt return command to return the process, thereby making it possible to execute the main process P_MAIN for game control from the beginning.

[0212] FIG. 10-12 is a flow chart showing an example of the random number update process P_RANDOM. The random number update process P_RANDOM is included in the process that can be called from the timer interrupt process P_PCT for game control shown in FIG. 5, and can be executed in step S56 in response to the occurrence of a regular timer interrupt due to the lapse of a predetermined time, for example, 4 ms. On the other hand, the random number update process P_RANDOM is not included in the process that can be called from the main process P_MAIN for game control shown in FIG. 4, and is not executed in the loop process that is repeated until a timer interrupt occurs after step S7. Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt due to the lapse of a predetermined time, it is not included in the second process that can be repeatedly executed until the first process is executed. In addition, although the random number update process P_RANDOM can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, it cannot be called and executed in the standby process as a repeated loop process in the main process P_MAIN for game control that is executed based on the start of power supply in the pachinko game machine 1 after startup processes such as the power supply start response process P_POWER_ON in step S1.

[0213] The random number update process P_RANDOM uses the internal registers of the CPU 103, such as the B register, the DE register, and the HL register, to update the numerical data indicating the values ​​of the random number MR1-2 for the winning symbol and the random number MR2-1 for the winning symbol of the normal symbol. The random number MR1-2 for the winning symbol is used to determine the determined special symbol that is the display result of the special symbol in the special symbol game, which is the variable display of the special symbol in the first special symbol display device 4A or the second special symbol display device 4B. The random number MR2-1 for the winning symbol of the normal symbol is used to determine the determined normal symbol that is the display result of the normal symbol in the normal symbol game, which is the variable display of the normal symbol in the normal symbol display device 20. The random number update process P_RANDOM can update the respective random number values ​​using the B register, the DE register, and the HL register as the internal registers that are common to both the case of updating the random number MR1-2 for the winning symbol and the case of updating the random number MR2-1 for the winning symbol of the normal symbol.

[0214] When the CPU 103 executes the random number update process P_RANDOM, it sets the random number counter address for the winning symbol by a transfer command for setting the HL register used as a random number pointer (step AKS61). The random number counter address for the winning symbol is the address of the random number counter for the winning symbol provided in the game work area of ​​the RAM 102. The random number pointer can store the address of the random number counter corresponding to the random number value to be updated, and the random number value to be updated can be specified by setting the stored value. In step AKS61, the random number MR1-2 for the winning symbol can be set as the random number value to be updated by storing the address of the random number counter for the winning symbol in the random number pointer by the LDQ command.

[0215] Following step AKS61, a transfer command is issued to set the B register used as the random number maximum register, and a random number maximum value corresponding to the random number maximum judgment value for the winning symbol is set (step AKS62). The random number maximum register can store the maximum value that the random number to be updated can take, and the maximum random number value can be specified by setting the stored value. In step AKS62, for the random number MR1-2 for the winning symbol, the maximum value included in the update range of the random number MR1-2, such as C7[H] corresponding to "199", is stored in the random number maximum register by the LD command. This allows the maximum random number value of the random number MR1-2 that was set as the random number to be updated in step AKS61 to be set.

[0216] After step AKS62, a transfer command for setting the DE register used as an initial value pointer is used to set the random number initial value data buffer address for the winning symbol (step AKS63). The random number initial value data buffer address for the winning symbol is the address of the random number initial value data buffer for the winning symbol provided in the game work area of ​​the RAM102. The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number value to be updated, and the random number initial value can be obtained or changed by setting the stored value. In step AKS63, the address of the random number initial value data buffer for the winning symbol is stored in the initial value pointer by the LDQ command, thereby setting the random number initial value to be obtainable and changeable in response to the random number MR1-2 set as the random number to be updated in step AKS61. Then, an initial value change random number update process P_RANCP is executed by a subroutine call command (step AKS64). The initial value changing random number updating process P_RANCP in step AKS64 enables updating of the random numbers MR1-2 for the winning symbols, which are the random number values ​​to be updated, and changing of the random number initial value, based on the settings in steps AKS61 to AKS63.

[0217] After the initial value change random number update process P_RANCP in step AKS64, the random number counter address for the normal symbol is set by a transfer command for setting the HL register used as a random number pointer (step AKS65). The random number counter address for the normal symbol is the address of the random number counter for the normal symbol provided in the game work area of ​​RAM 102. In step AKS65, the random number MR2-1 for the normal symbol can be set as the random number value to be updated by storing the address of the random number counter for the normal symbol in the random number pointer by the LDQ command.

[0218] Following step AKS65, a transfer command for setting the B register used as the random number maximum register is used to set the random number maximum value corresponding to the random number maximum judgment value for the normal symbol pattern (step AKS66). In step AKS66, for the random number MR2-1 for the normal symbol pattern, the maximum value included in the update range of the random number MR2-1, for example C6[H] corresponding to the maximum value "198", is stored in the random number maximum register by the LD command. This allows the random number maximum value of the random number MR2-1 that was set as the random number value to be updated in step AKS65 to be set.

[0219] After step AKS66, a random number initial value data buffer address for normal symbols is set by a transfer command for setting the DE register used as an initial value pointer (step AKS67). The random number initial value data buffer address for normal symbols is the address of a random number initial value data buffer for normal symbols provided in the game work area of ​​RAM102. In step AKS67, the address of the random number initial value data buffer for normal symbols is stored in the initial value pointer by an LDQ command, and the random number initial value of the random number MR2-1 set as the random number value to be updated in step AKS65 is set to be obtainable and changeable. Next, an initial value change random number update process P_RANCP is executed by a subroutine call command common to step AKS64 (step AKS68). The initial value change random number update process P_RANCP of step AKS68 enables updating of the random number MR2-1 for the normal winning symbol, which is the random number value to be updated, and changing of the random number initial value, based on the settings in steps AKS65 to AKS67.

[0220] FIG. 10-13 is a diagram for explaining an example of the use of data configuration related to the random number update process P_RANDOM. In the random number update process P_RANDOM, the initial value change random number update process P_RANCP is executed in step AKS64 using the random number counter for winning symbols whose address is set in the random number pointer in step AKS61 and the random number initial value data buffer for winning symbols whose address is set in the initial value pointer in step AKS63. In addition, in the random number update process P_RANDOM, the initial value change random number update process P_RANCP is executed in step AKS68 using the random number counter for winning symbols for normal symbols whose address is set in the random number pointer in step AKS65 and the random number initial value data buffer for winning symbols for normal symbols whose address is set in the initial value pointer in step AKS67. The random number counter for winning symbols is provided in the random number buffer area for special symbols, and can store numerical data corresponding to the random numbers MR1-2 for winning symbols. The random number initial value data buffer for the winning symbol is provided in the random number data area for the winning symbol, and can store numerical data corresponding to the random number initial value of the random number MR1-2. The random number counter for the winning symbol for the normal symbol is provided in the random number data area for the winning symbol, and can store numerical data corresponding to the random number MR2-1 for the winning symbol for the normal symbol. The random number initial value data buffer for the winning symbol for the normal symbol is provided in the random number data area for the winning symbol, and can store numerical data corresponding to the random number initial value of the random number MR2-1. In this way, the random number update process P_RANDOM enables the random numbers MR1-2 and MR2-1 to be updated by software using the random number initial value data buffer for the winning symbol provided in the random number data area for the winning symbol, the random number counter for the winning symbol for the normal symbol, the random number initial value data buffer for the winning symbol for the normal symbol, and the random number counter for the winning symbol provided in the random number buffer area for the special symbol.

[0221] Fig. 10-13(A) shows a configuration example AKB11 of the winning symbol random number data area. The winning symbol random number data area of ​​the configuration example AKB11 includes a winning symbol random number initial value data buffer at address F050[H], a winning symbol initial value random number counter at address F051[H], a normal symbol winning symbol random number counter at address F052[H], a normal symbol winning symbol random number initial value data buffer at address F053[H], and a normal symbol winning symbol initial value random number counter at address F054[H]. Among these, the address F050[H] of the random number initial value data buffer for the winning symbol is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, the address F052[H] of the random number counter for the normal symbol is set to the random number pointer by step AKS65 of the random number update process P_RANDOM, and the address F053[H] of the random number initial value data buffer for the normal symbol is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The initial value random number counter for the winning symbol can store numerical data corresponding to the random number MR1-3 which is the initial value for the winning symbol. The initial value random number counter for the normal symbol can store numerical data corresponding to the random number MR2-2 which is the initial value for the normal symbol.

[0222] FIG. 10-13(B) shows a configuration example AKB12 of the random number buffer area for special symbols. The random number buffer area for special symbols of the configuration example AKB12 includes a random number buffer for determining special symbols at address F07F[H], a random number counter for winning symbols at address F081[H], a random number buffer for selecting a variation pattern type at address F082[H], a random number buffer for a variation pattern at address F083[H], and a random number buffer for selecting a losing performance at address F084[H]. Among these, the address F081[H] of the random number counter for winning symbols is set to the random number pointer by step AKS61 of the random number update process P_RANDOM. The random number buffer for determining special symbols can store numerical data corresponding to the random number MR1-1 for determining special symbols obtained from the 16-bit random number circuit 104A. The random number buffer for selecting a variation pattern type can store numerical data corresponding to the random number MR3-3 for selecting a variation pattern type obtained from the 8-bit random number circuit 104B. The random number buffer for the variation pattern can store numerical data corresponding to the random number MR3-4 for the variation pattern obtained from the 8-bit random number circuit 104B. The random number buffer for selecting a failure effect can store numerical data corresponding to the random number MR3-2 for selecting a failure effect obtained from the 16-bit random number circuit 104A.

[0223] FIG. 10-14 is a flowchart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the process that can be called from the random number update process P_RANDOM shown in FIG. 10-12, and can be executed in step AKS64 after the setting of the random number MR1-2 for the winning symbol is performed in steps AKS61 to AKS63, and can be executed in step AKS68 after the setting of the random number MR2-1 for the normal winning symbol is performed in steps AKS65 to AKS67. Such an initial value change random number update process P_RANCP makes it possible to update the value of the random number MR1-2 using the numerical data corresponding to the random number MR1-2 for the winning symbol in step AKS64. Also, the initial value change random number update process P_RANCP makes it possible to update the value of the random number MR2-1 using the numerical data corresponding to the random number MR2-1 for the normal winning symbol in step AKS68.

[0224] When the CPU 103 executes the initial value change random number update process P_RANCP, it first executes a compare and add instruction (step AKS101). This compare and add instruction can be executed by a single ICPLD instruction, which is a third special transfer instruction, with the stored data at the address indicated by the stored value of the HL register, which is a random number pointer, as the update target value, and the stored value of the B register, which is a random number maximum register, as the comparison judgment value. The stored value of the HL register, which is a random number pointer, indicates the address of the random number counter in which the numerical data corresponding to the update target random number value is stored. The stored value of the B register, which is a random number maximum register, indicates the random number maximum value set corresponding to the update target random number value. Then, when the count value of the random number counter indicating the update target random number value is less than the stored value of the random number maximum register, the count value of the random number counter is updated to be incremented by 1, thereby incrementing the update target random number value by 1. On the other hand, when the count value of the random number counter indicating the update target random number value is equal to or greater than the stored value of the random number maximum register, the random number counter is cleared and the count value is initialized to "0", thereby changing the update target random number value to the random number minimum value. Therefore, the compare and add instruction of step AKS101 is a single instruction that includes comparing the random number value to be updated with the maximum random number, incrementing the random number value to be updated by 1 if the comparison result is less than the maximum random number, and changing the random number value to the minimum random number if the comparison result is equal to or greater than the maximum random number. In this way, when updating the random number value to be updated by the initial value change random number update process P_RANCP, a single compare and add instruction is executed first. By executing such a single compare and add instruction first, it is possible to suppress the occurrence of malfunctions and update the random number value appropriately.

[0225] When the compare and add instruction is executed in step AKS101, a transfer instruction for reading stored data is used to load the random number value pointed to by the random number pointer (step AKS102). The random number pointer and the initial value pointer are also exchanged (step AKS103). The random number value loaded in step AKS102 is then compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). It is determined whether the compared random number value is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random number value to be updated. Therefore, in step AKS104, after the compare and add instruction of step AKS101 is executed, the random number value to be updated after the compare and add instruction is compared with the random number initial value.

[0226] If the random number value corresponds to step AKS105 and is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105; Yes), the initial value change random number update process P_RANCP ends. When the comparison and addition instruction of step AKS101 is executed, the count value of the random number counter indicating the random number value to be updated will indicate the updated random number value to be updated. Then, when the initial value change random number update process P_RANCP ends due to the judgment result of step AKS105, the stored value of the random number counter indicating the updated random number value to be updated is stored as the current random number value. Therefore, in step AKS105, if the updated random number value to be updated does not match the random number initial value, the initial value change random number update process P_RANCP ends, allowing the updated random number value to be stored as the current random number value.

[0227] When the random number value is the same as the value stored in the random number initial value data buffer pointed to by the initial value pointer in response to step AKS105 (step AKS105; No), the initial value random number counter pointed to when the value stored in the initial value pointer is incremented by 1 is loaded (step AKS106). In the configuration example AKB11 of the random number data area for winning symbols shown in FIG. 10-13(A), the next address F051[H] when the address F050[H] where the random number initial value data buffer for winning symbols is provided is incremented by 1 is provided with the initial value random number counter for winning symbols. Also, the next address F054[H] when the address F053[H] where the random number initial value data buffer for normal symbols is incremented by 1 is provided with the initial value random number counter for normal symbols. Therefore, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for the winning symbol, the count value of the initial value random number counter for the winning symbol is read out. Also, in step AKS106, when the stored value of the initial value pointer indicates the address of the random number initial value data buffer for the normal symbol, the count value of the initial value random number counter for the normal symbol is read out. In this way, in step AKS106, the count value of the initial value random number counter can be read out as the random number value for the initial value.

[0228] When the initial value random number counter is loaded in step AKS106, the count value of the initial value random number counter thus read is stored in the random number counter pointed to by the random number pointer (step AKS107). Since the stored value of the random number pointer indicates the address of the random number counter corresponding to the random number value to be updated, step AKS107 allows the count value of the initial value random number counter to be stored as the current random number value to be updated. Therefore, if the result of the determination in step AKS105 is that the random number value to be updated after updating matches the random number initial value, step AKS107 allows the random number value for initial value read in step AKS106 to be stored as the current random number value.

[0229] Following step AKS107, the count value of the initial value random number counter read out in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), and then the initial value change random number update process P_RANCP ends. Since the stored value of the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number value to be updated, the count value of the initial value random number counter can be stored as a new random number initial value in step AKS108. Therefore, if the update target random number value after update matches the random number initial value as determined in step AKS105, the initial value random number value is stored as the current random number value in step AKS107, and the initial value random number value read out in step AKS106 can be stored as a new random number initial value in step AKS108. In this way, the uncertainty of the random number value is increased by setting a new random number initial value, and by storing it as the current random number value as well, an increase in data volume is prevented, enabling appropriate random number value update.

[0230] The random number update process P_RANDOM shown in FIG. 10-12 executes the initial value change random number update process P_RANCP in step AKS64 after setting the update target random number value, the random number maximum value, and the random number initial value for the random number MR1-2 for the winning pattern in steps AKS61 to AKS63. The initial value change random number update process P_RANCP makes it possible to update the update target random number value and change the random number initial value based on the settings for the update target random number value, the random number maximum value, and the random number initial value. The initial value change random number update process P_RANCP in step AKS64 makes it possible to update the random number MR1-2 for the winning pattern set as the update target random number value in step AKS61 using the random number maximum value set in step AKS62 and the random number initial value set in step AKS63. In addition, the initial value change random number update process P_RANCP in step AKS64 enables the change of the random number initial value when the random number MR1-2 for the winning symbol set as the update target random number value in step AKS61 matches the random number initial value set in step AKS63. In this way, the update of the set update target random number value enables the appropriate update of the random number value.

[0231] The random number update process P_RANDOM executes the initial value change random number update process P_RANCP of step AKS68 after setting the update target random number value, the maximum random number value, and the initial random number value for the random number MR2-1 for the normal symbol per symbol in steps AKS65 to AKS67. The initial value change random number update process P_RANCP of step AKS68 enables the update of the random number MR2-1 for the normal symbol per symbol set as the update target random number value in step AKS65 using the maximum random number value set in step AKS66 and the initial random number value set in step AKS67. In addition, the initial value change random number update process P_RANCP of step AKS68 enables the change of the initial random number value for the random number MR2-1 for the normal symbol per symbol set as the update target random number value in step AKS65 when the value coincides with the initial random number value set in step AKS67. In this way, the update of the set update target random number value, etc., enables the update of the appropriate random number value. In addition, by updating the set random number value to be updated or changing the initial random number value, it becomes possible to update the random number value appropriately.

[0232] The random number update process P_RANDOM can update the random number MR1-2 for the winning symbol used when determining the display result of the special symbol by a first update process consisting of steps AKS61 to AKS64, and can update the random number MR2-1 for the winning symbol for the normal symbol used when determining the display result of the normal symbol by a second update process consisting of steps AKS65 to AKS68. Then, the random number MR1-2 for the winning symbol is updated as the first random number value by steps AKS61 to AKS64, and then the random number MR2-1 for the winning symbol for the normal symbol is updated as the second random number value by steps AKS65 to AKS68. The determined special symbol that is the display result of the special symbol corresponds to the maximum number of times the large prize opening is opened in the big win game state. In addition, the determined special symbol that is the display result of the special symbol may correspond to whether or not the game is controlled to a high probability state after the end of the big win game state, or the maximum number of times the game can be displayed in the time-saving state after the end of the big win game state. In contrast, the confirmed normal pattern, which is the display result of the normal pattern, corresponds to the opening time and number of times of the second large winning port. Therefore, the display result of the special pattern attracts more attention from the player than the display result of the normal pattern. By updating the random number MR1-2 as the first random number value and then updating the random number MR2-1 as the second random number value by the random number update process P_RANDOM, which is a specific update process, the first random number value used to determine the display result that attracts the player's attention is updated before the second random number value, thereby suppressing the occurrence of malfunctions and enabling appropriate update of the random number value.

[0233] In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2 that is the first random number value, and steps AKS65 to AKS68 can update the random number MR2-1 that is the second random number value. Then, the initial value change random number update process P_RANCP of step AKS64 can be called and executed in response to the random number MR1-2 that is the first random number value, and the initial value change random number update process P_RANCP of step AKS68 can be called and executed in response to the random number MR2-1 that is the second random number value. In this way, the random number update process P_RANDOM that is the specific update process updates the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value, making their initial values ​​changeable, by calling the initial value change random number update process P_RANCP that is the common update process in response to the first random number value and the second random number value. The initial value changing random number updating process P_RANCP, which serves as such a common updating process, prevents an increase in program capacity, and enables the first random number value and the second random number value to be stably updated, thereby enabling appropriate updating of the random number values.

[0234] In the random number update process P_RANDOM, steps AKS61 to AKS64 for making the random number MR1-2, which is the first random value value, updatable are the first update process, and steps AKS65 to AKS68 for making the random number MR2-1, which is the second random value value, updatable are the second update process. The first update process can be executed by calling the initial value change random number update process P_RANCP in step AKS64, and the second update process can be executed by calling the initial value change random number update process P_RANCP in step AKS68. In this way, the random number update process P_RANDOM updates the random number MR1-2 as the first random value value and the random number MR2-1 as the second random value value, and makes their initial values ​​changeable, by calling the initial value change random number update process P_RANCP as a common update process in the first update process and the second update process. The initial value changing random number updating process P_RANCP, which serves as such a common updating process, prevents an increase in program capacity, and enables the first random number value and the second random number value to be stably updated, thereby enabling appropriate updating of the random number values.

[0235] In the random number update process P_RANDOM, steps AKS61 to AKS64 for making the random number MR1-2, which will be the first random number value, updatable constitute the first update process, and steps AKS65 to AKS68 for making the random number MR2-1, which will be the second random number value, updatable constitute the second update process. In the first and second update processes, the HL, B, and DE registers of CPU103, which are common internal storage means, are used to make the random number MR1-2, which will be the first random number value, and the random number MR2-1, which will be the second random number value, updatable. In this way, the first and second random number values ​​can be stably updated using the common internal storage means, enabling appropriate random number value updating.

[0236] In the random number update process P_RANDOM, before executing the initial value change random number update process P_RANCP in step AKS64, reference information such as the winning symbol random number counter address, the winning symbol random number maximum judgment value, and the winning symbol random number initial value data buffer address is stored in the HL register, B register, and DE register of the CPU 103, which is an internal storage means, in steps AKS61 to AKS63. Also, in the random number update process P_RANDOM, before executing the initial value change random number update process P_RANDCP in step AKS68, reference information such as the normal symbol winning symbol random number counter address, the normal symbol winning symbol random number maximum judgment value, and the normal symbol winning symbol random number initial value data buffer address is stored in the HL register, B register, and DE register of the CPU 103, which is an internal storage means, in steps AKS65 to AKS67. The instruction used to update the random number MR1-2 to become the first random number value by step AKS61 and the instruction used to update the random number MR2-1 to become the second random number value by step AKS65 are common instructions in that they set the HL register of the CPU 103, and since the random number counter address for the winning symbol is set by step AKS61 but the random number counter address for the normal winning symbol is set by step AKS65, different reference destination information can be set. The instruction used to update the random number MR1-2 to become the first random number value by step AKS62 and the instruction used to update the random number MR2-1 to become the second random number value by step AKS66 are common instructions in that they set the B register of the CPU 103, and since the random number maximum value corresponding to the winning symbol random number maximum judgment value is set by step AKS62 but the random number maximum value corresponding to the normal winning symbol random number maximum judgment value is set by step AKS66, different reference destination information can be set.The instruction used to update the random number MR1-2 to become the first random number value by step AKS63 and the instruction used to update the random number MR2-1 to become the second random number value by step AKS67 are common instructions in that they set the DE register of the CPU103, and since the random number initial value data buffer address for the winning symbol is set by step AKS63, but the random number initial value data buffer address for the normal winning symbol is set by step AKS67, different reference destination information can be set. In these steps AKS61 to AKS63 and steps AKS65 to AKS67, different reference destination information can be set using a common instruction such as an LD instruction or an LDQ instruction, which are transfer instructions for setting the internal register of the CPU103. Then, in steps AKS64 and AKS68, the initial value change random number update process P_RANCP is called and executed by a common subroutine call instruction. In this way, in the random number update process P_RANDOM, which is the specific update process, the instruction used to update the random number MR1-2 serving as the first random number value and the instruction used to update the random number MR2-1 serving as the second random number value are common. By making it possible to update the random number MR1-2 serving as the first random number value and the random number MR2-1 serving as the second random number value using the common instruction, it becomes possible to stably update the first random number value and the second random number value, and to update the random number values ​​appropriately.

[0237] The random number update process P_RANDOM enables the random number MR1-2, which is the first random number value, to be updated by steps AKS61 to AKS64, which is the first update process, and enables the random number MR2-1, which is the second random number value, to be updated by steps AKS65 to AKS68, which is the second update process. Then, the initial value change random number update process P_RANCP can be called and executed by steps AKS64 and AKS68. The initial value change random number update process P_RANCP shown in FIG. 10-14 executes a single compare and add instruction first, so that the compare and add instruction can be executed first in both cases of updating the random number MR1-2 as the first random number value and updating the random number MR2-1 as the second random number value. By executing such a compare and add instruction first, it is possible to suppress the occurrence of defects in the first random number value and the second random number value, and to update the random number value appropriately.

[0238] The initial value change random number update process P_RANCP, when executed in step AKS64 of the random number update process P_RANDOM, can update the random number MR1-2 for the winning symbol, and can change the random number initial value corresponding to the random number MR1-2 for the winning symbol using the random number MR1-3 that is the initial value for the winning symbol. Also, the initial value change random number update process P_RANCP, when executed in step AKS68 of the random number update process P_RANDOM, can update the random number MR2-1 for the winning symbol of the normal symbol, and can change the random number initial value corresponding to the random number MR2-1 for the winning symbol of the normal symbol using the random number MR2-2 that is the initial value for the winning symbol of the normal symbol. Therefore, the random number MR1-3 serving as the initial value for the winning symbol is a first initial value random number used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR1-2 for the winning symbol, which is the first random number value, by executing the initial value change random number update process P_RANCP in step AKS64 of the random number update process P_RANDOM. The random number MR2-2 serving as the initial value for the winning symbol for the normal symbol is a second initial value random number used when changing the random number initial value in response to the case where the random number value to be updated is the random number MR2-1 for the winning symbol for the normal symbol, which is the second random number value, by executing the initial value change random number update process P_RANCP in step AKS68 of the random number update process P_RANDOM.

[0239] FIG. 10-15 is a flowchart showing an example of the initial value determination random number update process P_TFINIT. The initial value determination random number update process P_TFINIT is included in the process that can be called from the game control main process P_MAIN shown in FIG. 4, and can be executed in step S9 of the loop process that is repeated until a timer interrupt occurs after step S7. The initial value determination random number update process P_TFINIT is also included in the process that can be called from the game control timer interrupt process P_PCT shown in FIG. 5, and can be executed in step AKS57 in response to the occurrence of a periodic timer interrupt due to the lapse of a predetermined time, such as 4 ms. Therefore, the initial value determination random number update process P_TFINIT is included in the first process that can be executed in response to a timer interrupt due to the lapse of a predetermined time, and the second process that can be repeatedly executed until the first process is executed. Furthermore, the initial value determination random number update process P_TFINIT can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, and can also be called and executed by step S9 included in the standby process as a repeated loop process after startup processes such as the power supply start response process P_POWER_ON in step S1 in the main process P_MAIN for game control that is executed based on the start of power supply in the pachinko game machine 1. In this way, the initial value determination random number update process P_IFINIT is included in processes that can be executed in response to periodic timer interrupts as an initial value random number update process, and is also included in processes that can be repeatedly executed irregularly, making the update period and update speed of the initial value random number value indefinite, thereby increasing the uncertainty of the initial value random number value and enabling appropriate update of the random number value.

[0240] When the CPU103 executes the initial value determination random number update process P_TINIT, it sets the initial value random number counter address for the winning symbol by a transfer command for setting a pointer (step AKS81). The initial value random number counter address for the winning symbol is the address F051[H] assigned to the initial value random number counter for the winning symbol in the configuration example AKB11 of the random number data area for the winning symbol shown in FIG. 10-13(A). When the pointer is set in this way, the count value of the initial value random number counter for the winning symbol can be updated within the update range of "0" to "199" by a comparison and addition command (step AKS82). This comparison and addition command can be executed by a single ICPLD command, which is the third special transfer command, with the stored data of the address pointed to by the pointer as the update target value and the immediate value specified by the operand as the comparison and judgment value. The stored value of the pointer indicates the address of the random number counter in which the numerical data corresponding to the update target initial value random number value is stored. The immediate value specified by the operand indicates the maximum random number for initial value that is set corresponding to the random number for initial value to be updated. Then, if the count value of the random number counter indicating the random number for initial value to be updated is less than the maximum random number for initial value, the count value of the random number counter is updated to increment by 1, thereby incrementing the random number for initial value to be updated by 1. On the other hand, if the count value of the random number counter indicating the random number for initial value to be updated is equal to or greater than the value stored in the maximum random number for initial value register, the random number counter is cleared and the count value is initialized to "0", thereby changing the random number for initial value to be updated to the minimum random number value. Therefore, the compare and add instruction of step AKS82 is a single instruction including: setting the random number MR1-3, which is the initial value for the winning symbol, to the random number value for the initial value to be updated; comparing the random number value for the initial value to be updated with the maximum random number value for the initial value; adding 1 to the random number value for the initial value to be updated if the result of the comparison is less than the maximum random number value for the initial value; and changing the random number value for the initial value to the minimum random number value if the result of the comparison is equal to or greater than the maximum random number value for the initial value. Note that the compare and add instruction is not limited to the ICPLD instruction in which the address of the stored data indicating the update target value is specified by a pointer, and may be, for example, an ICPLDQ instruction in which the upper address is set using the Q register and the lower address is set using the immediate value specified by the first operand of the compare and add instruction.In this case, the immediate value specified by the second operand of the compare-and-add instruction is set as the comparison judgment value. By updating the random value for the initial value to be updated using such a compare-and-add instruction, it is possible to prevent the occurrence of errors and to update the random value appropriately.

[0241] After step AKS82, the address of the initial value random number counter for the normal symbol is set by a transfer command for setting the pointer (step AKS83). The address of the initial value random number counter for the normal symbol is the address F054[H] assigned to the initial value random number counter for the normal symbol in the configuration example AKB11 of the random number data area for the winning symbol shown in FIG. 10-13(A). When the pointer is set in this way, the count value of the initial value random number counter for the normal symbol is made updatable within the update range of "1" to "198" by a comparison and addition command (step AKS84), and the initial value determination random number update process P_TFINIT is completed. The comparison and addition command of step AKS84 may be the same as the comparison and addition command of step AKS82. However, in the comparison and addition instruction of step AKS84, the random number MR2-2, which is the initial value for the normal pattern, is set to the random number value for the initial value to be updated, so that the immediate value specified by the operand indicating the maximum random number value for the initial value is set to a value different from that of the comparison and addition instruction of step AKS82. Therefore, the comparison and addition instruction of step AKS84 is a single instruction including: setting the random number MR2-2, which is the initial value for the normal pattern, to the random number value for the initial value to be updated, comparing the random number value for the initial value to the maximum random number value for the initial value, adding 1 to the random number value for the initial value to be updated if the result of the comparison is less than the maximum random number value for the initial value, and changing the random number value for the initial value to the minimum random number value if the result of the comparison is equal to or greater than the maximum random number value for the initial value. By updating the random number value for the initial value to be updated using such a comparison and addition instruction, it is possible to suppress the occurrence of malfunctions and update the random number value appropriately.

[0242] The random number update process for determining initial values ​​P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol by steps AKS81 and AKS82 as an update of the random number value for the first initial value. At the same time, the random number update process for determining initial values ​​P_TFINIT updates the random number MR2-2 that is the initial value for the winning symbol of the normal symbol by steps AKS83 and AKS84 as an update of the random number value for the second initial value. The random number MR1-3 that is the initial value for the winning symbol is the first random number value used when changing the random number initial value when the random number value to be updated is the random number MR1-2 for the winning symbol that is the first random number value. The random number MR2-2 that is the initial value for the winning symbol of the normal symbol is the second random number value used when changing the random number initial value when the random number value to be updated is the random number MR2-1 for the winning symbol of the normal symbol that is the second random number value. Steps AKS81 and AKS82 of the random number update process P_TFINIT for determining initial values ​​are a first initial value update process capable of updating the first random value. Steps AKS83 and AKS84 of the random number update process P_TFINIT for determining initial values ​​are a second initial value update process capable of updating the second random value. By updating the random value values ​​for the first and second initial values ​​in this way, it becomes possible to appropriately update the random values ​​so that the uncertainty of the first and second random values ​​is reliably increased.

[0243] In addition, the initial value determination random number update process P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol as the first initial value random number value in steps AKS81 and AKS82, and then updates the random number MR2-2 that is the initial value for the winning symbol for the normal symbol as the second initial value random number value in steps AKS83 and AKS84. Therefore, the initial value determination random number update process P_TFINIT updates the random number MR1-3 that is the initial value for the winning symbol, which is the first initial value random number value, in steps AKS81 and AKS82, which are the first initial value update process, and then updates the random number MR2-1 that is the initial value for the winning symbol for the normal symbol, which is the second initial value random number value, in steps AKS83 and AKS84, which are the second initial value update process.

[0244] FIG. 10-16 is a flow chart showing an example of the start port switch passing process P_TZU_ON. The start port switch passing process P_TZU_ON is included in the process that can be called from the special symbol process process P_TPROC shown in FIG. 6, and can be executed in step S104 when the first start winning corresponding flag is on in step S103, and can be executed in step S108 when the second start winning corresponding flag is on in step S107. When the start port switch passing process P_TZU_ON is executed, the CPU 103 sets the start port winning memory counter address by a transfer command for setting a pointer (step AKS201). The start port winning memory counter address is the address of the first start port winning memory counter or the second start port winning memory counter provided in the game work area of ​​the RAM 102. In step AKS201, a different address in the game work area can be specified in response to the first start port winning table or the second start port winning table set by the special symbol process P_TPROC. For example, the upper address F0[H] of the game work area, which is the work area, is set to the upper byte of the pointer by a transfer command, and the lower address of the start port winning memory counter stored in the first start port winning table or the second start port winning table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command. As a result, the value indicating the address of the first start port winning memory counter or the second start port winning memory counter is stored in the internal register of the CPU103, which is the pointer. Next, the start port winning memory counter is loaded by a transfer command for reading out the stored data of the address pointed to by the pointer (step AKS202).

[0245] After step AKS202, it is determined whether the count value of the start port winning memory counter is equal to or greater than the counter maximum value (step AKS203). For example, if the value loaded in step AKS202 is equal to or greater than the counter maximum value, such as "4", by a comparison return command that can compare the value, the start port switch passing process P_TZU_ON is terminated and the process returns to the special symbol process P_TPROC. On the other hand, if the value is less than the counter maximum value (step AKS203; No), the count value of the start port winning memory counter is updated to add 1 (step AKS204). In this case, an arithmetic and logic operation command that increments the stored data at the address pointed to by the pointer enables the count value of the first start port winning memory counter or the second start port winning memory counter to be updated to add 1.

[0246] After step AKS204, the special symbol determination buffer address is set as the transfer destination (step AKS205). The special symbol determination buffer address is the address of the first special symbol determination buffer included in the first special symbol reservation buffer or the second special symbol determination buffer included in the second special symbol reservation buffer provided in the game work area of ​​RAM 102. In step AKS205, different addresses in the game work area can be specified in accordance with the first start hole winning table or the second start hole winning table set by the special symbol process processing P_TPROC and the count value of the first start hole winning counter or the second start hole winning counter loaded in step AKS202.

[0247] The first special symbol reservation buffer is secured as a plurality of storage areas, such as five storage areas corresponding to the buffer numbers "0" to "4", in correspondence with the case where the variable display of the first special symbol is being executed and the number of first reserved memories that have not yet been executed, by the first reserved memory buffer configured to include a first special symbol determination buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first miss performance selection buffer. The second special symbol reservation buffer is secured as a plurality of storage areas, such as five storage areas corresponding to the buffer numbers "0" to "4", in correspondence with the case where the variable display of the second special symbol is being executed and the number of second reserved memories that have not yet been executed, by the second reserved memory buffer configured to include a second special symbol determination buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second miss performance selection buffer.

[0248] In step AKS205, a value corresponding to the buffer size of the first reserved memory buffer or the second reserved memory buffer is multiplied by the count value of the start port winning counter, and the multiplied value is added to the lower address of the first reserved memory buffer or the second reserved memory buffer with the buffer number "1". By setting such an added value to the transfer destination pointer, the special symbol determination buffer address can be set as the transfer destination.

[0249] Following step AKS205, the RL0 hard latch random number register address is set (step AKS206). The RL0 hard latch random number register address is the address of the RL0 hard latch random number register provided in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer by a transfer command, and the lower address of the RL0 hard latch random number register stored in the first start port winning table or the second start port winning table pointed to by the table pointer is set to the lower byte of the pointer by a transfer command. The lower address of the RL0 hard latch random number register with buffer number "0" is stored in the first start port winning table. The lower address of the RL0 hard latch random number register with buffer number "1" is stored in the second start port winning table. As a result, an address different from the first start winning case to the second start winning case is stored in the internal register of CPU103, which serves as a pointer, as the address of the RL0 hard latch random number register.

[0250] After step AKS206, the RL0 hard latch random number register is loaded by a transfer command to read the stored data at the address pointed to by the pointer (step AK207). The value stored in the RL0 hard latch random number register thus obtained is stored in the special symbol determination random number buffer by a transfer command to write the value in the memory area of ​​the specified address in the game work area of ​​RAM102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random number register in the special symbol determination random number buffer, numerical data indicating the value of the special symbol determination random number MR1-1 is extracted, and the value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

[0251] After step AKS208, the RL2 soft latch random number register is loaded by a transfer command for reading out the stored data from the memory area of ​​the specified address in the function control register area (step AKS209). The stored value of the RL2 soft latch random number register obtained at this time is stored in the random number buffer for selecting a losing performance by a transfer command for writing to the memory area of ​​the specified address in the game work area of ​​RAM102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random number register in the random number buffer for selecting a losing performance, numerical data indicating the value of the random number MR3-2 for selecting a losing performance is extracted, and the value of the random number MR3-2 can be stored in the random number buffer for selecting a losing performance.

[0252] After step AKS210, the RS1 soft latch random number register is loaded by a transfer command for reading out the stored data from the memory area of ​​the specified address in the function control register area (step AKS211). The stored value of the RS1 soft latch random number register acquired at this time is stored in the random number buffer for selecting the variation pattern type by a transfer command for writing to the memory area of ​​the specified address in the game work area of ​​RAM102 (step AKS212). In this way, by storing the numerical data acquired from the RS1 soft latch random number register in the random number buffer for selecting the variation pattern type, the numerical data indicating the value of the random number MR3-3 for selecting the variation pattern type is extracted, and the value of the random number MR3-3 can be stored in the random number buffer for selecting the variation pattern type.

[0253] After step AKS212, the RS2 soft latch random number register is loaded by a transfer command for reading the stored data from the memory area of ​​the specified address in the function control register area (step AKS213). The stored value of the RS2 soft latch random number register acquired at this time is stored in the random number buffer for the fluctuation pattern by a transfer command for writing to the memory area of ​​the specified address in the game work area of ​​RAM102 (step AKS214). In this way, by storing the numerical data acquired from the RS2 soft latch random number register in the random number buffer for the fluctuation pattern, the numerical data indicating the value of the random numbers MR3-4 for the fluctuation pattern is extracted, and the value of the random numbers MR3-4 can be stored in the random number buffer for the fluctuation pattern.

[0254] Following step AKS214, block transfer is performed from the random number buffer to the special symbol determination buffer (step AKS215). The random number buffer includes a special symbol determination random number buffer in which the value of random number MR1-1 is stored by step AKS208, a loss performance selection random number buffer in which the value of random number MR3-2 is stored by step AKS210, a variation pattern type selection random number buffer in which the value of random number MR3-3 is stored by step AKS212, and a variation pattern random number buffer in which the value of random number MR3-4 is stored by step AKS214. In step AKS215, the address of the special symbol determination random number buffer is set as the transfer source, and a value corresponding to the buffer size of the random number buffer is set as the transfer count. The special symbol determination buffer address to be the transfer destination is set by step AKS205. Based on these settings, by executing a block transfer command, the value of each random number temporarily stored in the random number buffer can be stored as new reserved information in the first reserved memory buffer or the second reserved memory buffer.

[0255] When the new memory information is stored by step AKS215, it is determined whether the winning performance condition is satisfied (step AKS216). The winning performance condition may be set in advance as a condition for enabling the pre-reading performance. For example, when the starting port winning designation value is "2", it is determined that the winning performance condition is satisfied. Also, when the starting port winning designation value is "1", the time-saving function flag is "0" corresponding to the time-saving state not being in, and the special symbol process code is less than 03 [H] corresponding to the time-saving state not being in the small win game state or the big win game state, it is determined that the winning performance condition is satisfied. When it is determined that the winning performance condition is satisfied (step AKS216; Yes), the winning performance process P_GAME_CHK is executed (step AKS217). The winning performance process P_GAME_CHK includes a hit determination of the special symbol, and selects a performance designation value corresponding to the determination result, and enables the winning performance command to be transmitted.

[0256] When it is determined in step AKS216 that the winning performance condition is not satisfied (step AKS216; No), or after the winning performance process in step AKS217 is executed, a transfer command for setting a pointer is issued to set the performance memory information designation command transmission table address (step AKS218). The performance memory information designation command transmission table address is the address of the performance memory information designation command transmission table stored in the game data area of ​​ROM101. Then, by executing the command set process P_COM_SET (step AKS219), the first performance memory information designation command or the second performance memory information designation command can be transmitted as the start winning command. The first performance memory information designation command is a performance control command that designates the first reserved memory number indicated by the count value of the first start port winning memory counter. The second performance memory information designation command is a performance control command that designates the second reserved memory number indicated by the count value of the second start port winning memory counter. In this way, the command set process P_COM_SET in step AKS219 enables the performance control command, which becomes the command at the time of the initial winning, to be transmitted from the main board 11 to the performance control board 12.

[0257] After step AKS219, the start port winning buffer memory counter address is set by a transfer command for setting a pointer (step AKS220). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of ​​RAM102. In this way, the count value of the start port winning buffer memory counter whose address has been set is updated to add 1 (step AKS221). In addition, the pointer is updated corresponding to the start port winning buffer memory counter by a composite transfer command for setting a register or a pointer (step AKS222). For example, the count value of the start port winning buffer memory counter after the update by step AKS221 is loaded into the internal register of CPU103, and the stored value of the pointer is updated to add 1, so that a value indicating the top address of the start port winning buffer is stored in the pointer. Furthermore, the count value of the loaded start port winning buffer memory counter is added to the stored value of the pointer, making it possible to specify the storage area of ​​the buffer number to be updated in the start port winning buffer.

[0258] When the pointer is updated by step AKS222, a start port winning designation value is loaded (step AKS223). The start port winning designation value can be set to "1" indicating the first start port winning or "2" indicating the second start port winning, corresponding to the first start port winning table or the second start port winning table set by the special pattern process processing P_TPROC. In step AKS223, the start port winning designation value can be acquired by a transfer command for reading table data from the first start port winning table or the second start port winning table. The start port winning designation value thus acquired is stored in the start port winning buffer by a transfer command for writing to the memory area of ​​the address pointed to by the pointer (step AKS224), and the start port switch passing processing P_TZU_ON is terminated.

[0259] FIG. 10-17 is a diagram for explaining an example of the use of data configuration related to the start port switch passing process P_TZU_ON. In the start port switch passing process P_TZU_ON, various settings and controls are performed using the first start port winning table set in step S102 of the special pattern process process P_TPROC shown in FIG. 6 or the second start port winning table set in step S106. For example, the first start port winning memory counter and the second start port winning memory counter, whose count value can be updated in step AKS204, are provided in the special pattern control data area and can store data corresponding to the first reserved memory number and the second reserved memory number. The start port winning buffer memory counter, whose count value can be updated by AKS221, and the start port winning buffer, in which the start port winning designation value is stored by AKS224, are provided in the start port winning buffer area and can store the total number of times and the order of occurrence of the first start winning and the second start winning. In addition, in the command set process P_COM_SET in step AKS219, the first effect storage information designation command sending table or the second effect storage information designation command sending table whose address has been set in step AKS218 is used.

[0260] In this way, the start port switch passing processing P_TZU_ON enables control of the special pattern game, which is a variable display of special patterns, by using the first start port winning table or the second start port winning table, the first start port winning memory counter or the second start port winning memory counter provided in the special pattern control data area, the start port winning buffer memory counter and the start port winning buffer provided in the start port winning buffer area, and the first performance memory information designation command sending table or the second performance memory information designation command sending table.

[0261] Fig. 10-17 (A1) shows a configuration example AKT21 of the first start port winning table. The first start port winning table of the configuration example AKT21 is configured to include table data indicating the lower address of the first start port winning memory counter, the lower address of the RL0 hard latch random number register number "0", the lower address of the first special symbol determination buffer number "1", the address of the first performance memory information designation command transmission table, and the start port winning designation value "1".

[0262] The first start port winning memory counter is provided in the game work area of ​​the RAM 102, and can store data corresponding to the first reserved memory number. The RL0 hard latch random number register number "0" is an RL0 hard latch random number register with register number "0" provided in the function control register area, and can acquire and store numerical data indicating the value of the random number MR1-1 for special symbol determination that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A by hard latching. The first special symbol determination buffer number "1" is a first special symbol determination buffer included in the first reserved memory buffer with buffer number "1" in the first special symbol reservation buffer. The first performance memory information designation command transmission table is stored in the game data area of ​​the ROM 101, and is used when transmitting the first performance memory information designation command that designates the first reserved memory number. The start port winning designation value "1" is a designation value that identifiably indicates that the first start winning has occurred.

[0263] Fig. 10-17 (A2) shows a configuration example AKT22 of the second start port winning table. The second start port winning table of the configuration example AKT22 is configured to include table data indicating the lower address of the second start port winning memory counter, the lower address of the RL0 hard latch random number register number "1", the lower address of the second special symbol determination buffer number "1", the address of the second performance memory information designation command transmission table, and the start port winning designation value "2".

[0264] The second start port winning memory counter is provided in the game work area of ​​the RAM 102, and can store data corresponding to the second reserved memory number. The RL0 hard latch random number register number "1" is an RL0 hard latch random number register with register number "1" provided in the function control register area, and can acquire and store numerical data indicating the value of the random number MR1-1 for special symbol determination that can be generated by the channel RL0 provided in the 16-bit random number circuit 104A by hard latching. The second special symbol determination buffer number "1" is a second special symbol determination buffer included in the second reserved memory buffer with buffer number "1" in the second special symbol reservation buffer. The second performance memory information designation command transmission table is stored in the game data area of ​​the ROM 101, and is used when transmitting the second performance memory information designation command that designates the second reserved memory number. The start port winning designation value "2" is a designation value that identifiably indicates that the second start winning has occurred.

[0265] Figure 10-17 (B1) shows a configuration example AKB21 of the special symbol control data area. The special symbol control data area of ​​the configuration example AKB21 can store various data related to the control by the special symbol process P_TPROC, such as the special symbol game which is a variable display of the special symbol, and the small win game state and the big win game state which can be controlled based on the display result. This special symbol control data area includes a special symbol process timer at address F030[H], a win flag at address F032[H], a special symbol process code at address F033[H], a first start port winning memory counter at address F034[H], a big win symbol determination buffer at address F035[H], a small win symbol determination buffer at address F036[H], a big win port winning number counter at address F037[H], a big win port opening number counter at address F038[H], a big win port opening pattern timer at address F039[H], a big win port opening pattern table pointer at address F03B[H], a demo display flag at address F03D[H], and a second start port winning memory counter at address F099[H].

[0266] The special symbol process timer can store a time value corresponding to the control time by the special symbol process processing P_TPROC. The special symbol process code can specify the processing selected in the special symbol process processing P_TPROC. The first start port winning memory counter can store a count value corresponding to the first reserved memory number. The big win symbol determination buffer can store data corresponding to the big win symbol designated value. The big win symbol designated value is a designated value corresponding to the confirmed special symbol displayed when the display result in the variable display of the special symbol is "big win", and makes it possible to set the type of big win game state. The small win symbol determination buffer can store data corresponding to the small win symbol designated value. The small win symbol designated value is a designated value corresponding to the confirmed special symbol displayed when the display result in the variable display of the special symbol is "small win", and makes it possible to set the alcoholic beverage in the small win game state. The large prize opening number counter can store a count value corresponding to the number of game balls that have passed through the large prize opening formed by the special variable prize ball device 50. The large prize opening opening number counter can store a count value corresponding to the number of times the large prize opening is opened in a small win game state or a big win game state. The large prize opening opening pattern timer can store a time value corresponding to the remaining time for controlling the large prize opening to an open state in a small win game state or a big win game state. The large prize opening opening pattern table pointer can specify a storage address of the large prize opening opening pattern table in which the opening time of the large prize opening is set. The demo display flag can store a flag value corresponding to an on state or an off state depending on whether a demonstration display is being executed or not. The second start opening winning memory counter can store a count value corresponding to the second reserved memory number.

[0267] FIG. 10-17(B2) shows a configuration example AKB22 of the start port winning buffer area. The start port winning buffer area of ​​the configuration example AKB22 can store various data related to the first start winning and the second start winning that occur when the game ball enters the first start winning port and the second start winning port. This start port winning buffer area includes a start port winning buffer memory counter at address F0BA[H] and start port winning buffer numbers "0" to "8" at addresses F0BB[H] to F0C3[H].

[0268] The start port winning buffer memory counter can store a count value corresponding to the number of valid start port winning designation values ​​stored in the start port winning buffer area. Therefore, the count value of the start port winning buffer memory counter indicates the total number of first start winnings and second start winnings. The start port winning buffer numbers "0" to "8" are start port winning buffers to which buffer numbers "0" to "8" are assigned, and can store start port winning designation values ​​in the order in which the first start winnings and second start winnings occurred. As a result, the stored information in the start port winning buffer indicates the order in which the first start winnings and second start winnings occurred.

[0269] FIG. 10-17(C1) shows a configuration example AKT23 of the first performance memory information designation command transmission table. The first performance memory information designation command transmission table of the configuration example AKT23 is configured to include table data indicating the first performance memory information designation command upper byte and the first start port winning memory counter reference designation value. The command set process P_COM_SET of step AKS219 enables the first performance memory information designation command to be transmitted when the first performance memory information designation command transmission table is used. The first performance memory information designation command can set the lower byte corresponding to the count value of the first start port winning memory counter. By transmitting such a first performance memory information designation command, the first reserved memory number can be notified to the performance control board 12.

[0270] FIG. 10-17(C2) shows a configuration example AKT24 of the second performance memory information designation command transmission table. The second performance memory information designation command transmission table of the configuration example AKT24 is configured to include table data indicating the second performance memory information designation command upper byte and the second start port winning memory counter reference designation value. The command set process P_COM_SET of step AKS219 enables the second performance memory information designation command to be transmitted when the second performance memory information designation command transmission table is used. The second performance memory information designation command can set the lower byte corresponding to the count value of the second start port winning memory counter. By transmitting such a second performance memory information designation command, the second reserved memory number can be notified to the performance control board 12.

[0271] The start port switch passing process P_TZU_ON shown in FIG. 10-16 stores the stored value of the RL2 soft latch random number register loaded in step AKS209 in the random number buffer for selecting a miss performance in step AKS210, thereby making it possible to extract numerical data indicating the value of the random number MR3-2 for selecting a miss performance. The start port switch passing process P_TZU_ON also stores the stored value of the RS1 soft latch random number register loaded in step AKS211 in the random number buffer for selecting a fluctuation pattern type in step AKS212, thereby making it possible to extract numerical data indicating the value of the random number MR3-3 for selecting a fluctuation pattern type. The start port switch passing process P_TZU_ON also stores the stored value of the RS2 soft latch random number register loaded in step AKS213 in the random number buffer for a fluctuation pattern in step AKS214, thereby making it possible to extract numerical data indicating the value of the random number MR3-4 for a fluctuation pattern. Here, if the random number MR3-2 for selecting a losing performance is the first random number, the random number MR3-3 for selecting a variation pattern type is the second random number, and the random number MR3-4 for the variation pattern is the third random number, the start port switch passing process P_TZU_ON is executed in response to the occurrence of a start winning, so the first random number, the second random number, and the third random number can be extracted by the establishment of a common extraction condition, that is, the occurrence of a start winning, for the first random number, the second random number, and the third random number. The random number MR3-2 for selecting a losing performance is included in the game random numbers that can be updated by the 16-bit random number circuit 104A, and the random number MR3-3 for selecting a variation pattern type and the random number MR3-4 for the variation pattern are included in the game random numbers that can be updated by the 8-bit random number circuit 104B, and the total number of random numbers included in the update range for each is a prime number. The update speed of the random number MR3-2 is 469 times / ms, while the update speed of the random numbers MR3-3 and MR3-4 is 938 times / ms. In other words, the update speed of the random numbers MR3-3 and MR3-4 is two times the update speed of the random number MR3-2, which is an integer multiple.The update range of random number MR3-2 is "0" to "65518", the update range of random number MR3-3 is "0" to "240", and the update range of random number MR3-4 is "0" to "250", so the total number of random numbers included in each update range is different, and the total number of random numbers included in each update range is a prime number. In this way, when the update speed of the second random number value and the third random number value is an integer multiple of the update speed of the first random number value, the total number of random number values ​​included in each update range is different, and the total number of random number values ​​included in each update range is a prime number. This makes it possible to suppress synchronization between the first random number value, the second random number value, and the third random number value, and to update the random number values ​​appropriately.

[0272] FIG. 10-18 is a flow chart showing an example of the special symbol normal processing P_TNORMAL. The special symbol normal processing P_TNORMAL is included in the processing that can be called from the special symbol process processing P_TPROC shown in FIG. 6, and can be executed in step S112 when the special symbol process code loaded in step S110 is 00[H]. When the special symbol normal processing P_TNORMAL is executed, the CPU 103 sets the start port winning buffer memory counter address by a transfer command for setting a pointer (step AKS241). The start port winning buffer memory counter address is the address of the start port winning buffer memory counter provided in the game work area of ​​the RAM 102. In this way, it is determined whether the count value of the start port winning buffer memory counter whose address has been set is "0" or not (step AKS242). For example, an arithmetic jump instruction that branches processing depending on whether the stored data at the address pointed to by the pointer is 00[H] corresponding to "0" or not makes it possible to execute different processing contents depending on whether the count value of the start port winning buffer memory counter is "0" or other than "0."

[0273] If the count value of the start port winning buffer memory counter is not "0" in response to step AKS242 (step AKS242; No), the count value of the start port winning buffer memory counter is updated to subtract 1 (step AKS243). Also, a block transfer for shifting the start port winning buffer is performed (step AKS244). In step AKS244, the destination address is set to the lower address BB[H] of start port winning buffer number "0", the source address is set to the lower address BC[H] of start port winning buffer number "1", and the number of transfers is set to "8", which is the buffer size of the start port winning buffer. After that, by executing a block transfer command, the memory contents in the start port winning buffer can be transferred and shifted one unit at a time to the previous buffer. Then, the memory area of ​​the start port winning buffer number "8" can be initialized by clearing it.

[0274] Following step AKS244, a transfer command for setting a table pointer is used to set a second special symbol determination control table address (step AKS245). The second special symbol determination control table address is the address of the second special symbol determination control table stored in the game data area of ​​the ROM101. At this time, a start port winning check process is executed to determine whether the start port winning designation value is "1" (step AKS246). For example, in the start port winning check process, if the start port winning designation value is "1", the zero flag is turned on, and if the start port winning designation value is "2", the zero flag is turned off. After such a start port winning check process is executed, a jump command for branching the process depending on whether the zero flag is off makes it possible to execute different process contents depending on whether the start port winning designation value is "1" or "2".

[0275] When the start port winning designation value is "1" in response to step AKS246 (step AKS246; Yes), the first special symbol determination control table address is set by a transfer command for setting the table pointer (step AKS247). The first special symbol determination control table address is the address of the first special symbol determination control table stored in the game data area of ​​the ROM 101. In step AKS247, the value of the table pointer is overwritten by a transfer command for setting the table pointer. In this way, in the special symbol normal processing P_TNORMAL, after the second special symbol determination control table address is set in step AKS245, the start port winning designation value corresponds to "1" in step AKS246, and the first special symbol determination control table address is reset by overwriting in step AKS247. As a result, when the frequency of use of the second special symbol determination control table is higher than the frequency of use of the first special symbol determination control table, the program capacity required for table setting can be reduced, and the marketability of the pachinko game machine 1 can be improved. In addition, when the frequency of use of the second special pattern determination control table is higher than the frequency of use of the first special pattern determination control table, the processing using a jump command as a branch command can be simplified, making it easier to confirm at the design stage and improving the marketability of the pachinko game machine 1.

[0276] If the starting port winning designation value is "2" and not "1" in response to step AKS246 (step AKS246; No), or after step AKS247, the special pattern determination process P_TDECISION is executed (step AKS248), and then the variable pattern setting process P_TPATSET is executed (step AKS249), after which the normal special pattern processing ends.

[0277] When the count value of the start port winning buffer storage counter is "0" in response to step AKS242 (step AKS242; Yes), it is determined whether the demo display flag is on (step AKS250). The demo display flag is a flag indicating that a demonstration display is being executed. When the demo display flag is on (step AKS250; Yes), the special symbol normal processing ends. On the other hand, when the demo display flag is off (step AKS250; No), a transfer command for setting the demo display flag is used to store 01 [H], which is a designated value during demo display, in the demo display flag (step AKS251). This sets the demo display flag to an on state. In addition, a transfer command for setting a pointer is used to set a standby command transmission table address (step AKS252). The standby command transmission table address is the address of the standby command transmission table stored in the game data area of ​​ROM101. Then, the command set process P_COM_SET is executed (step AKS253), and the normal special symbol process ends.

[0278] FIG. 10-19 is a diagram for explaining an example of the use of the data configuration related to the special symbol normal processing P_TNORMAL. In the special symbol normal processing P_TNORMAL, the special symbol determination processing in step AKS248 is executed using the second special symbol determination control table whose address is set in step AKS245 or the first special symbol determination control table whose address is set in step AKS247. In addition, in the command set processing P_COM_SET in step AKS253, the standby command transmission table whose address is set in step AKS252 is used. In this way, the special symbol normal processing P_TNORMAL enables control related to the special symbol game, which is a variable display of the special symbol, using the first special symbol determination control table or the second special symbol determination control table or the standby command transmission table.

[0279] FIG. 10-19 (A1) shows a configuration example AKT31 of the first special symbol determination control table. The first special symbol determination control table of the configuration example AKT31 is configured to include table data indicating the address of the first special symbol buffer shift control table, the lower address of the first special symbol determination buffer number "0", the lower address of the first winning symbol buffer number "0", the lower address of the first special symbol buffer, and the address of the work setting table after the first special symbol hit determination. The first special symbol buffer shift control table is stored in the game data area of ​​ROM101 and is used when shifting the memory contents of the first special symbol reserved buffer. The first special symbol determination buffer number "0" is the first special symbol determination buffer included in the first reserved memory buffer of the buffer number "0" in the first special symbol reserved buffer. The first winning symbol buffer number "0" is a first winning symbol buffer included in the first reserved memory buffer of the buffer number "0" in the first special symbol reserved buffer. The first special symbol buffer is provided in the game work area of ​​the RAM 102, and can store a special symbol pattern designation value corresponding to the confirmed special symbol stopped and displayed in the first special symbol game by the first special symbol display device 4A. The first special symbol winning determination work setting table is stored in the game data area of ​​the ROM 101, and is used when initializing data in response to the end of the special symbol determination process P_TDECISION.

[0280] FIG. 10-19 (A2) shows a configuration example AKT32 of the second special symbol determination control table. The second special symbol determination control table of the configuration example AKT32 is configured to include table data indicating the address of the second special symbol buffer shift control table, the lower address of the second special symbol determination buffer number "0", the lower address of the second winning symbol buffer number "0", the lower address of the second special symbol buffer, and the address of the work setting table after the second special symbol hit determination. The second special symbol buffer shift control table is stored in the game data area of ​​ROM101 and is used when shifting the memory contents of the second special symbol reserved buffer. The second special symbol determination buffer number "0" is the second special symbol determination buffer included in the second reserved memory buffer of the buffer number "0" in the second special symbol reserved buffer. The second winning symbol buffer number "0" is a second winning symbol buffer included in the second reserved memory buffer of the buffer number "0" in the second special symbol reserved buffer. The second special symbol buffer is provided in the game work area of ​​the RAM 102, and can store a special symbol pattern designation value corresponding to the determined special symbol stopped and displayed in the second special symbol game by the second special symbol display device 4B. The second special symbol winning determination work setting table is stored in the game data area of ​​the ROM 101, and is used when initializing data in response to the end of the special symbol determination process P_TDECISION.

[0281] FIG. 10-19(B) shows a configuration example AKT33 of the standby command transmission table AKT33. The standby command transmission table of the configuration example AKT33 is configured to include table data indicating the number of processes, the second specific number of times designation command upper byte, the specific number of times command buffer reference designation value, the background color designation command upper byte, the special symbol state designation code reference designation value, the customer waiting demo command upper byte, and the customer waiting demo command lower byte. The command set process P_COM_SET of step AKS253 uses the standby command transmission table of the configuration example AKT33 to enable the second specific number of times designation command, the background color designation command, and the customer waiting demo command to be transmitted. The second specific number of times designation command can set a lower byte corresponding to the storage value of the specific number of times command buffer. The background color designation command can set a lower byte corresponding to the special symbol state designation code. The customer waiting demo command can set a lower byte using a fixed value 03[H].

[0282] FIG. 10-20 is a flow chart showing an example of the special symbol determination process P_TDECISION. The special symbol determination process P_TDECI...

Claims

[Claim 1] A gaming machine capable of playing a game, A substrate on which a connected member that enables signal transmission is disposed; a harness including a connecting member connectable to the connected member and a plurality of wirings, The connecting member and the connected member have a common color, Among the plurality of wires included in the harness, some of the wires have a specific color, and the remaining wires have a color different from the specific color, color designation information corresponding to the specific color and identification information relating to the connected member are written on the board near the connected member; the color designation information corresponding to the specific color is larger in size than the identification information regarding the connected member; A gaming machine characterized by:

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