BATTERY MANAGEMENT CIRCUIT, POWER STORAGE DEVICE, AND BATTERY MANAGEMENT METHOD

Abstract

A battery management circuit (4) used for each of a plurality of serially connected storage batteries (1) in a power storage device (100) that comprises the storage batteries (1) and a plurality of serially connected capacitors (3), wherein the battery management circuit (4) comprises: a positive-electrode connection terminal (14) connected to a positive electrode of the corresponding storage battery (1); a negative-electrode connection terminal (15) connected to a negative electrode of the corresponding storage battery (1); a capacitor connection terminal (16) connected to a terminal of the capacitor (3); and a control circuit (10) that controls the operation of connecting the positive-electrode connection terminal (14) or the negative-electrode connection terminal (15) with the capacitor connection terminal (16), and performs a control in the connection operation to synchronize with the operation of connecting another battery management circuit (4) among the plurality of battery management circuits (4).

Description

[Technical field]

[0001] The present disclosure relates to a battery management circuit used for each of a plurality of storage batteries in a power storage device including a plurality of storage batteries and one or more capacitors connected in series, a power storage device, and a battery management method. [Background technology]

[0002] Patent Document 1 discloses a technique for equalizing the voltages of a plurality of storage batteries connected in series. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2000-511398 Summary of the Invention [Problem to be solved by the invention]

[0004] The conventional technology has a problem in that a large power loss may occur during the voltage equalization operation.

[0005] In view of this, the present disclosure provides a battery management circuit, a power storage device, and a battery management method that suppress power loss during voltage equalization. [Means for solving the problem]

[0006] In order to solve the above problems, a battery management circuit in one embodiment of the present disclosure is a battery management circuit used for each of a plurality of storage batteries in a power storage device including a plurality of storage batteries connected in series and one or more capacitors, and includes a positive electrode connection terminal connected to the positive electrode of a corresponding storage battery, a negative electrode connection terminal connected to the negative electrode of the corresponding storage battery, a capacitor connection terminal connected to a terminal of the capacitor, and a control circuit that controls the connection operation between the positive electrode connection terminal or the negative electrode connection terminal and the capacitor connection terminal, and controls the connection operation to be synchronized with the connection operation of other battery management circuits among the plurality of battery management circuits.

[0007] In order to solve the above problem, a power storage device according to an aspect of the present disclosure includes the above battery management circuit, the one or more capacitors, and the multiple storage batteries.

[0008] In addition, a battery management method in one aspect of the present disclosure for solving the above problem is a battery management method executed by a battery management circuit used for each of a plurality of storage batteries in a power storage device including a plurality of storage batteries connected in series and one or more capacitors, the battery management circuit including a positive electrode connection terminal connected to a positive electrode of a corresponding storage battery, a negative electrode connection terminal connected to a negative electrode of the corresponding storage battery, a capacitor connection terminal connected to a terminal of the capacitor, and a control circuit that controls a connection operation between the positive electrode connection terminal or the negative electrode connection terminal and the capacitor connection terminal, and the battery management method determines whether the connection operation in the battery management circuit of an adjacent storage battery among the plurality of storage batteries has been released, and performs a new connection operation when it is determined that the connection operation has been released. Effect of the Invention

[0009] According to the battery management circuit, the power storage device, and the battery management method according to one aspect of the present disclosure, it is possible to suppress power loss during voltage equalization. [Brief description of the drawings]

[0010] [Figure 1]FIG. 1 is a circuit diagram illustrating a configuration example of a power storage device according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing another configuration example of the power storage device according to the embodiment. [Diagram 3] FIG. 3 is a circuit diagram showing yet another configuration example of the power storage device according to the embodiment. [Figure 4] FIG. 4 is a circuit diagram showing a configuration example of a power storage device according to an embodiment having three or more storage batteries. [Diagram 5] FIG. 5 is an example of a flowchart showing the flow of the voltage equalization process of the power storage device according to the embodiment. [Figure 6] FIG. 6 is an example of a time chart showing the voltage equalization process of the battery management circuit according to the embodiment. [Figure 7] FIG. 7 is a circuit diagram showing the voltage equalization device of Patent Document 1. [Figure 8] FIG. 8 is a circuit diagram showing a detail of a portion of FIG. [Figure 9] FIG. 9 is an explanatory diagram showing a case where power loss occurs due to irregular switching timing of the switches. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (Findings on which the present invention is based) The present inventors have found that the technique for equalizing the voltages of a plurality of storage batteries described in the "Background Art" section has the following problems.

[0012] First, the voltage equalization in Patent Document 1 will be described.

[0013] Fig. 7 is a circuit diagram showing a voltage equalization device, which is disclosed as Fig. 1 in Patent Document 1. The device in the figure connects each capacitor to one storage battery, then each capacitor to another storage battery, and equalizes the output voltages of multiple storage batteries by repeatedly switching between these connections.

[0014] However, the technique disclosed in Patent Document 1 has a problem in that a large power loss may occur during the voltage equalization operation. This problem will be described with reference to FIGS. 8 and 9.

[0015] FIG. 8 is a circuit diagram disclosed as FIG. 2 in Patent Document 1, and shows a detailed portion of FIG. 7. In FIG. 8, the switches 16b-2 and 16c-2 are turned on and off according to the gate signal q. The switches 16b-3 and 16c-3 are turned on and off according to the inverted signal of the gate signal q. Therefore, the switches 16b-2 and 16c-2 are turned on exclusively with the switches 16b-3 and 16c-3. For example, the voltage between the terminals of the capacitor 14b changes little because there exists only a period during which the output voltage of the storage battery Bb or the output voltage of the storage battery Bc is applied, and therefore no unnecessary current should flow through the capacitor.

[0016] However, the signal transmission path that transmits the gate signal q to each switch and the signal transmission path that transmits the inverted signal of the gate signal q are prone to variations in delay time of the gate signal of each switch because the potential difference of the power supply of each switch varies, and the switching timing of the switches may not be synchronized. The problem of power loss occurring due to the non-uniform switching timing of the switches occurs.

[0017] Fig. 9 is an explanatory diagram showing a case where power loss occurs due to mismatched switching timing of the switches. The upper part of Fig. 9 shows the timing (gate signal) at which the switches 16b-2, 16b-3, 16c-2, and 16c-3 are turned on and off, and the voltage change of the capacitor 14b. The lower left part of Fig. 9 shows the voltage applied to the capacitor 14b in the section T1 in the upper part. The lower right part of Fig. 9 shows the voltage applied to the capacitor 14b in the section T1 in the upper part.

[0018] 9 shows an example in which the on / off timing of switches 16b-2 and 16b-3 is delayed from the on / off timing of switches 16c-2 and 16c-3, and their on periods overlap. That is, in section T1, switches 16b-2 and 16c-3 are simultaneously in the on state. Also, in section T2, switches 16b-3 and 16c-2 are simultaneously in the on state.

[0019] In section T1, the voltage applied across the terminals of capacitor 14b is the voltage of batteries Bb and Bc connected in series. In section T2, both terminals of capacitor 14b are short-circuited. As shown by the dashed circle in the upper part of the figure, the voltage applied to capacitor 14b changes significantly. This voltage change causes unnecessary current to flow through capacitor 14b, resulting in a large power loss, as shown by the thick arrow in the lower part of the figure.

[0020] Thus, there is a problem in that a large power loss may occur due to the switching timing of the switches not being synchronized.

[0021] In view of this, the present disclosure provides a battery management circuit, a power storage device, and a battery management method that suppress power loss during voltage equalization.

[0022] In order to solve the above problems, a battery management circuit in one embodiment of the present disclosure is a battery management circuit used for each of a plurality of storage batteries in a power storage device including a plurality of storage batteries connected in series and one or more capacitors, and includes a positive electrode connection terminal connected to the positive electrode of a corresponding storage battery, a negative electrode connection terminal connected to the negative electrode of the corresponding storage battery, a capacitor connection terminal connected to a terminal of the capacitor, and a control circuit that controls the connection operation between the positive electrode connection terminal or the negative electrode connection terminal and the capacitor connection terminal, and controls the connection operation to be synchronized with the connection operation of other battery management circuits among the plurality of battery management circuits.

[0023] In order to solve the above problem, a power storage device according to an aspect of the present disclosure includes the above battery management circuit, the capacitor, and the multiple storage batteries.

[0024] In addition, a battery management method in one aspect of the present disclosure for solving the above problem is a battery management method executed by a battery management circuit used for each of a plurality of storage batteries in a power storage device including a plurality of storage batteries connected in series and a capacitor, the battery management circuit including a positive electrode connection terminal connected to a positive electrode of a corresponding storage battery, a negative electrode connection terminal connected to a negative electrode of the corresponding storage battery, a capacitor connection terminal connected to a terminal of the capacitor, and a control circuit that controls a connection operation between the positive electrode connection terminal or the negative electrode connection terminal and the capacitor connection terminal, and the battery management method determines whether the connection operation in the battery management circuit of another storage battery among the plurality of storage batteries has been released, and performs a new connection operation when it is determined that the connection operation has been released.

[0025] Hereinafter, the embodiments will be described in detail with reference to the drawings. Note that each of the embodiments described below shows a specific example of the present disclosure. The components, the layout and connection of the components, the drive timing, and the like shown in the following embodiments are merely examples and are not intended to limit the present disclosure. In addition, the realization of the present disclosure is not limited to the current independent claims, and may be expressed by other independent claims.

[0026] In addition, each drawing is not necessarily a strict illustration, and in each drawing, duplicated explanations of substantially the same configuration will be omitted or simplified.

[0027] (Embodiment) FIG. 1 is a circuit diagram showing a configuration example of a power storage device 100 according to an embodiment.

[0028] In the figure, the power storage device 100 includes a storage battery pack 2, a capacitor 3, and a plurality of battery management circuits 4.

[0029] The assembled storage battery 2 includes a plurality of storage batteries 1 connected in series. Each storage battery 1 has a plurality of battery cells B1 to B5 connected in series. Each battery cell is, for example, a lithium ion battery, but may be other secondary batteries such as nickel metal hydride batteries. Also included are storage cells connected in series such as lithium ion capacitors. The assembled storage battery 2 is connected to a load and a charging circuit. The load is, for example, a motor of an HEV or EV, but is not limited thereto. FIG. 1 shows an example in which the storage battery 1 has five battery cells B1 to B5, but the number of battery cells constituting the storage battery 1 may be one or more. The number of storage batteries 1 constituting the assembled storage battery 2 is the same as the number of the plurality of battery management circuits 4.

[0030] The number of capacitors 3 is one less than the number of the storage batteries 1. In other words, if the number of the storage batteries 1 is n, the number of capacitors 3 is (n-1). Each capacitor 3 is used in a voltage equalization process that equalizes the output voltages of the storage batteries 1. In the voltage equalization process, each capacitor is connected in parallel to one storage battery 1, and is also connected in parallel to another storage battery 1. These two types of parallel connections are alternately repeated to equalize the output voltages of the storage batteries 1.

[0031] The battery management circuits 4 are provided corresponding to the multiple storage batteries 1. Each battery management circuit 4 manages a corresponding storage battery 1. The battery management circuits 4 control switching between the above two types of parallel connection in the voltage equalization process. At that time, the battery management circuit 4 is configured to synchronize the above parallel connection switching operation with the connection operation of the other battery management circuits 4 among the multiple battery management circuits 4.

[0032] Therefore, each battery management circuit 4 includes a positive electrode connecting terminal 14, a negative electrode connecting terminal 15, a capacitor connecting terminal 16, a first main switch HM, a first auxiliary switch HS, a second main switch LM, a second auxiliary switch LS, a detection unit 9, a control circuit 10, and a resistance element 11.

[0033] The positive electrode connection terminal 14 is a terminal that is connected to the positive electrode of the storage battery 1 corresponding to the battery management circuit 4.

[0034] The negative electrode connection terminal 15 is a terminal that is connected to the negative electrode of the storage battery 1 corresponding to the battery management circuit 4.

[0035] The capacitor connection terminal 16 is a terminal connected to a terminal of the capacitor 3. Specifically, when there is a single capacitor 3, the capacitor connection terminal 16 is connected to one terminal of the capacitor 3, and when there are multiple capacitors 3, the capacitor connection terminal 16 is connected to a connection point between two of the multiple capacitors 3 connected in series, or to one terminal of each of the capacitors 3 at both ends.

[0036] The first main switch HM is a switch that connects the positive electrode connecting terminal 14 and the capacitor connecting terminal 16 as a high-side main switch.

[0037] The second main switch LM serves as a low-side main switch and connects the negative electrode connection terminal 15 and the capacitor connection terminal 16 together.

[0038] The first sub switch HS serves as a high-side sub switch for forming a first path that generates a potential difference by a current flowing from the positive electrode connecting terminal 14 to the capacitor connecting terminal 16. Here, the first path is a path that connects the positive electrode connecting terminal 14, the first sub switch HS, the resistor element 11, and the capacitor connecting terminal 16.

[0039] The second sub switch LS serves as a low-side sub switch and is a switch for forming a second path that generates a potential difference by a current flowing from the capacitor connecting terminal 16 to the negative electrode connecting terminal 15. Here, the second path is a path that connects the negative electrode connecting terminal 15, the second sub switch LS, the resistive element 11, and the capacitor connecting terminal 16.

[0040] The detection unit 9 detects the potential difference between the capacitor connection terminal 16 and the positive electrode connection terminal 14 as the potential difference in the first path. The potential difference in the first path is detected as a voltage drop occurring across a series circuit made up of the internal resistance (on-resistance) of the first secondary switch HS and the resistance element 11.

[0041] Furthermore, the detection unit 9 detects the potential difference between the capacitor connection terminal 16 and the negative electrode connection terminal 15 as the potential difference in the second path. The potential difference in the second path is detected as a voltage drop occurring across a series circuit consisting of the internal resistance (on-resistance) of the second secondary switch LS and the resistance element 11. If the on-resistance of the first secondary switch HS and the on-resistance of the second secondary switch LS are each negligibly small, the potential difference in the first path and the potential difference in the second path are detected as a voltage drop in the resistance element 11. If the on-resistance of the first secondary switch HS and the on-resistance of the second secondary switch LS are sufficiently large, the resistance element 11 may be omitted.

[0042] More specifically, the detection unit 9 includes a comparator 12 and a comparator 13 .

[0043] The comparator 12 judges whether or not the potential difference in the first path is equal to or less than a predetermined value th1. The predetermined value th1 is set by a reference voltage source of the positive input terminal of the comparator 12. The judgment of the comparator 12 means whether or not the connection operation (first main switch HM) of the other battery management circuit 4 has been released.

[0044] The comparator 13 judges whether or not the potential difference in the second path is equal to or greater than a predetermined value th5. The predetermined value th5 is set by a reference voltage source of the negative input terminal of the comparator 12. The judgment of the comparator 13 means whether or not the connection operation (second main switch LM) of the other battery management circuit 4 has been released.

[0045] The resistive element 11 is a resistive element for detecting the potential difference in the first path and the potential difference in the second path, and is shared by the first path and the second path.

[0046] In the voltage equalization process, the control circuit 10 controls the connection operation between the positive electrode connection terminal 14 or the negative electrode connection terminal 15 and the capacitor connection terminal 16. There are two types of connection operations. One is a connection operation between the positive electrode connection terminal 14 and the capacitor connection terminal 16 by the first main switch HM. The other is a connection operation between the negative electrode connection terminal 15 and the capacitor connection terminal 16 by the second main switch LM. The two types of connection operations correspond to the above-mentioned two types of parallel connections that connect the storage battery 1 and the capacitor 3.

[0047] The control circuit 10 controls the connection operation to be synchronized with the connection operations of other battery management circuits 4 among the multiple battery management circuits 4. For example, the control circuit 10 synchronizes with the other battery management circuits 4 using the detection result of the detection unit 9. Specifically, the battery management circuit 4 determines whether or not the connection operation of the other battery management circuits 4 has been released based on the potential difference detected by the detection unit 9, and performs control to perform a new connection operation when it is determined that the connection operation has been released.

[0048] More specifically, for the high side, the control circuit 10 turns on the first main switch HM after the detection unit 9 detects that the potential difference in the first path has increased to a predetermined value within a first time after the first sub switch HS has been turned on. Also, for the low side, the battery management circuit 4 turns on the second main switch LM after the detection unit 9 detects that the potential difference in the second path has decreased to a predetermined value within a second time after the second sub switch LS has been turned on.

[0049] The other battery management circuit 4 refers to a battery management circuit 4 corresponding to a storage battery other than the storage battery to which one battery management circuit 4 corresponds in the power storage device 100. The other battery management circuit 4 may be, for example, the battery management circuit 4 adjacent to the positive side (high side) of the multiple storage batteries 1 connected in series, or the battery management circuit 4 adjacent to the negative side (low side).

[0050] In this way, the control circuit 10 of the battery management circuit 4 uses the first sub switch HS and second sub switch LS and detection unit 9 in its battery management circuit, and the control circuit 10 of the other battery management circuit 4 uses the first sub switch HS and second sub switch LS and detection unit 9 in its battery management circuit, and controls to equalize the voltage of the storage battery 1 by repeating a first connection state in which the capacitor 3 is connected in parallel to the first storage battery 1 and a second connection state in which the capacitor 3 is connected in parallel to the second storage battery 1, while synchronizing the switching operation with the control circuit 10 of the other battery management circuit 4.

[0051] In FIG. 1, a control circuit 10 corresponds to each storage battery 1, and a group of switches prepared for each storage battery 1 is controlled by each control circuit 10. The group of switches refers to a first main switch HM, a second main switch LM, a first sub switch HS, and a second sub switch LS. Compared to FIG. 7 of the conventional art, FIG. 1 does not have a signal transmission path (a signal line of a gate signal q and a signal line of an inverted signal thereof) that transmits commands from one control unit to each group of switches, as shown in FIG. 7, and each control circuit 10 and switch belong to each battery management circuit 4 that uses the same storage battery 1 as a power source, so delay time errors are unlikely to occur. Therefore, power loss due to timing discrepancies in switching in multiple battery management circuits 4 can be suppressed.

[0052] Each battery management circuit 4 in FIG. 1 may be configured as an integrated circuit (IC). One battery management circuit 4 and one capacitor 3 may be configured as a printed circuit board. The battery management circuit 4 may measure the output voltage of the corresponding storage battery 1. The battery management circuit 4 may measure the temperature of the corresponding storage battery 1. The battery management circuit 4 may correct the measured voltage based on the measured temperature. The battery management circuit 4 may measure the current flowing through the storage battery 1.

[0053] Next, an example of a method for synchronizing switching between individual control circuits 10 provided for each storage battery 1 without a mutual signal transmission path will be described.

[0054] 1, the control circuit 10 turns on the first auxiliary switch HS, and then detects with the detection unit 9 that the voltage at the capacitor connecting terminal 16 has risen to a predetermined value within a predetermined time, after which it turns on the first main switch HM for a predetermined time, and then turns on the second auxiliary switch LS, and then detects with the detection unit 9 that the voltage at the capacitor connecting terminal 16 has fallen to a predetermined value within a predetermined time, after which it turns on the second main switch LM for a predetermined time. The control circuit 10 repeatedly operates according to this series of control procedures.

[0055] Each control circuit 10 performs the same control procedure.

[0056] Furthermore, the operation of the circuit in FIG. 1 in the above series of control procedures will be explained in detail.

[0057] When the second main switch LM is turned on and then turned off after a predetermined time has elapsed, and the first auxiliary switch HS is turned on, a current flows from the positive electrode connecting terminal 14 to the capacitor connecting terminal 16 via the resistive element 11. Meanwhile, in the adjacent control circuit 10, when the first auxiliary switch HS is turned on after the second main switch LM is turned off, a current also flows from the positive electrode connecting terminal 14 to the capacitor connecting terminal 16 via the resistive element 11.

[0058] After this, if the timing at which the first secondary switches HS turn on in the two adjacent control circuits 10 is synchronized, the voltage at the capacitor connection terminal 16 rises immediately. However, if the timing of the adjacent first secondary switches HS does not match and one turns on first while the other remains off and the second main switch LM remains on, the voltage at the capacitor connection terminal on the side where the first secondary switch HS turned on first rises over a long period of time according to a time constant determined by the product of the resistance value of the resistive element 11 and the capacitance value of the capacitor 3, and therefore remains without rising for a while.

[0059] Thereafter, when the other second main switch LM is turned off and both of the adjacent first sub switches HS are turned on, both terminals of the capacitor 3 become high impedance, and the voltage rises quickly. Therefore, after the detection unit 9 detects that the potential difference between the terminals of the capacitor 3 and the positive terminal or negative terminal of the storage battery 1 has risen to a predetermined value, the first main switch is turned on. This ensures that the timing at which the adjacent first main switches HM turn on is the same. Even if there is a slight error in the timing at which the adjacent first main switches HM turn on, the impedance of the capacitor terminals in the previous state is high, so no large current flows in the circuit.

[0060] Thereafter, when the first main switch HM is turned on and then turned off after a predetermined time has elapsed, and the second auxiliary switch LS is turned on, a current flows from the capacitor connection terminal 16 to the negative electrode connection terminal 15 via the resistance element 11. Meanwhile, in the adjacent control circuit 10, after the first main switch HM is turned off, when the second auxiliary switch LS is turned on, a current flows from the capacitor connection terminal 16 to the negative electrode connection terminal 15 via the resistance element 11.

[0061] After this, if the timings at which the second sub switches LS of the adjacent control circuits 10 turn on are the same, the voltage of the capacitor connection terminal 16 drops immediately. However, if the timings are not the same and only one of the switches turns on first while the other is still off and the first main switch HM remains on, the voltage of the capacitor connection terminal 16 of the adjacent second sub switch LS that turned on first drops over a long period of time with a time constant determined by the product of the resistance value and the capacitance value of the capacitor 3, so the voltage remains for a while without dropping. After that, when the other first main switch HM turns off and both of the adjacent second sub switches LS turn on, both terminals of the capacitor 3 become high impedance, so the voltage drops quickly. After the detection unit 9 detects that the potential difference between the capacitor connection terminal 16 and the positive electrode connection terminal 14 or the negative electrode connection terminal 15 has dropped to a predetermined value, the second main switch LM is turned on. As a result, the timings at which the adjacent second main switches LM turn on are the same. Even if there is a slight error in the timing at which adjacent second main switches LM are turned on, a large current will not flow in the circuit because the impedance of the capacitor terminal in the previous state is high.

[0062] Furthermore, the on-times of the respective main switches in adjacent control circuits 10, i.e., the time that the first main switch HM is on and the time that the adjacent first main switch HM is on, and the time that the second main switch LM is on and the time that the adjacent second main switch LM is on, do not need to be the same. This is because the main switch with a shorter on-time waits in that state until the first secondary switch HS or the second secondary switch LS is switched to the on state, after the main switch with a longer on-time.

[0063] By using this control method, the control circuits 10 can synchronize the timing at which the main switches are turned on via the voltage equalization capacitors, and switching can be synchronized even without a separate signal transmission path.

[0064] Next, another configuration example of the power storage device 100 will be described.

[0065] Fig. 2 is a circuit diagram showing another example of the configuration of the power storage device 100 according to the embodiment. In Fig. 1, the battery management circuit 4 generates a potential difference by a current flowing from the positive electrode connection terminal 14 to the capacitor connection terminal 16 using a resistance element 11, and generates a potential difference by a current flowing from the capacitor connection terminal 16 to the negative electrode connection terminal 15. In contrast, the battery management circuit 4 in Fig. 2 is configured to generate a potential difference corresponding to the voltage of the capacitor connection terminal 16 using a current source 17 and a current source 18.

[0066] When the battery management circuit 4 is configured as a semiconductor integrated circuit, it is easy to configure the current sources 17 and 18.

[0067] The roles and control methods of other parts are the same as those in FIG. 1, so the explanation will be omitted.

[0068] Next, still another configuration example of the power storage device 100 will be described.

[0069] FIG. 3 is a circuit diagram showing yet another configuration example of the power storage device 100 according to the embodiment.

[0070] In FIG. 1, the ON time of the main switches, that is, the first main switch HM and the second main switch LM, is determined by the control circuit 10, but in FIG. 3, a timer circuit 19 that controls the ON time of the main switches is added.

[0071] As mentioned above, the on-time of the main switch does not need to be the same for each storage battery 1. The adjacent main switch with the shorter on-time first switches the first sub switch HS or the second sub switch LS to the on-state, and then waits in that state until the main switch with the longer on-time switches the first sub switch HS or the second sub switch LS to the on-state. Therefore, even if the on-times of the main switches are not the same, an excessive current does not flow in the circuit. However, during the period when one side is waiting as described above, a small current flows, but a wasteful current flows, reducing efficiency, and since this period is ineffective for battery voltage equalization, the longer this time is, the longer it takes to equalize the battery voltages. Therefore, the shorter the waiting state is, the better, that is, it is ideal for the on-times of the main switches to be equal.

[0072] In FIG. 3, at least one of the plurality of battery management circuits 4, which is a timer circuit 19 that follows the switching timing of another, is provided with a timer control circuit 20 so that the time during which the first main switch HM and the second main switch LM are on is equal to or less than a predetermined value, and the timer time is automatically adjusted.

[0073] As a specific example, the timer control circuit 20 can be configured as a circuit that converts a signal representing the period during which the first secondary switch HS and the second secondary switch LS are on into a signal averaged by an integration circuit, and the timer circuit 19 can be configured as a circuit that lengthens the on time depending on the voltage of the control terminal.

[0074] In the circuit described above, if the ON times of the main switches of the battery management circuits 4 associated with the respective storage batteries 1 are equalized, a power storage device can be configured with less power loss and shorter time required for battery voltage equalization.

[0075] Although the battery pack is configured with two storage batteries 1 in the above-described embodiments shown in Figs. 1 to 3, the number of storage batteries 1 may be any number equal to or greater than two.

[0076] 4 is a circuit diagram showing an example of a configuration of an energy storage device according to an embodiment, in which three or more storage batteries 1 are included. Note that, although the storage batteries 1 are shown to be each configured with five unit cells, the number of unit cells built into the storage batteries 1 may be any number including one.

[0077] An example of a method for synchronizing switching between individual control circuits 10 provided for three or more storage batteries 1 without mutual signal transmission paths will be described with reference to Fig. 4. In Fig. 4, the number of storage batteries 1 is the same as the number of battery management circuits 4. The number of capacitors 3 is one less than the number of storage batteries 1.

[0078] 4, the control circuit 10 turns on the first auxiliary switch HS, and then detects with the detection unit 9 that the voltage at the capacitor connecting terminal 16 has risen to a predetermined value within a predetermined time, after which it turns on the first main switch HM for a predetermined time, and then turns on the second auxiliary switch LS, and then detects with the detection unit 9 that the voltage at the capacitor connecting terminal 16 has fallen to a predetermined value within a predetermined time, after which it turns on the second main switch LM for a predetermined time. The control circuit 10 repeats this series of control procedures.

[0079] The other control circuits 10 in the plurality of battery management circuits 4 also perform the same control procedure.

[0080] The operation of the entire circuit in FIG. 4 in the above series of control procedures will now be described in detail.

[0081] After switching the second main switch LM from on to off, each control circuit 10 turns on the first auxiliary switch HS to pass a positive current through the capacitor connection terminal 16 and waits until the voltage of each capacitor connection terminal 16 rises to a predetermined value. If any one of the second main switches LM in the multiple battery management circuits 4 is on, the voltage of the capacitor connection terminal 16 is maintained for a while, and when all the second main switches LM are turned off, the voltage of the capacitor connection terminal 16 rises rapidly. After the detection unit 9 detects that the potential difference between the capacitor connection terminal 16 and the positive electrode connection terminal 14 or the negative electrode connection terminal 15 has risen to a predetermined value, the first main switch HM is turned on. As a result, the timing at which the first main switches HM in the multiple battery management circuits 4 are turned on is consistent, and even if there is a slight error in the timing, the impedance of the capacitor terminal in the previous state is high, so no large current flows through the circuit.

[0082] After that, the control circuit 10 turns on the first main switch HM, switches it off after a predetermined time has elapsed, turns on the second sub switch LS to pass a negative current through the capacitor connection terminal 16, and waits until the voltage of each capacitor connection terminal 16 drops to a predetermined value. If any one of the first main switches HM of the multiple battery management circuits 4 is on, the voltage of the capacitor connection terminal 16 is maintained for a while, and when all the first main switches HM are turned off, the voltage of the capacitor connection terminal 16 drops rapidly. After the detection unit 9 detects that the potential difference between the capacitor connection terminal 16 and the positive electrode connection terminal 14 or the negative electrode connection terminal 15 has dropped to a predetermined value, the second main switch LM is turned on. As a result, the timing at which the second main switches LM of the multiple battery management circuits 4 are turned on is consistent, and even if there is a slight error in the timing, the impedance of the capacitor terminal in the previous state is high, so that a large current does not flow through the circuit.

[0083] The on-times of the main switches determined by the respective control circuits 10, i.e., the time that the first main switch HM is on and the time that the second main switch LM is on, do not need to be the same. This is because a control circuit 10 whose on-time of the main switch is shorter than the on-times of the main switches in the other battery management circuits 4 waits in that state after the first sub switch HS or the second sub switch LS is switched on until the control circuit 10 whose main switch is on for the longest time switches the first sub switch HS or the second sub switch LS to the on state.

[0084] With this control method, even for three or more storage batteries 1, the control circuits 10 can synchronize the timing at which the main switches are turned on, making it possible to synchronize the switching of all multiple battery management circuits 4 without the need for a separate signal transmission path.

[0085] Next, the flow of processing of the control circuit 10 of the energy storage device according to the embodiment will be described with reference to Fig. 5. Fig. 5 is an example of a flowchart showing the flow of voltage equalization processing of the energy storage device 100 according to the embodiment. All of the control circuits 10 belonging to multiple battery management circuits 4 perform the same processing. Fig. 6 is an example of a time chart showing the voltage equalization processing of the battery management circuit 4 according to the embodiment.

[0086] 5, the current of the first path, that is, the current flowing from the positive electrode connecting terminal 14 to the capacitor connecting terminal 16 via the first secondary switch HS, is called a high-side current. Also, the current of the second path, that is, the current flowing from the capacitor connecting terminal 16 to the negative electrode connecting terminal 15 via the second secondary switch LS, is called a low-side current.

[0087] The control circuit 10 first forms a second path, that is, forms a path for a low-side current by turning on the second auxiliary switch LS (S01). Next, it determines whether or not the voltage VC of the capacitor connection terminal 16 is equal to or lower than a predetermined value th1 (S02). If the condition is not satisfied (S02: NO), it determines whether or not the elapsed time t from turning on the second auxiliary switch LS is equal to or lower than a time limit th2 (S03). If it is within the time limit th2 (S03: YES), it returns to S01. If it is longer than the time limit th2 (S03: NO), it turns off all currents and switches (S14). If the condition is satisfied in S02 (S02: YES), it turns off the second auxiliary switch LS to open the second path, and turns on the second main switch LM (S04). In this way, during the period T12 in Figure 6, that is, the period T12 from just before S01 (S12) to S04, the battery management circuit 4 determines whether the connection operation of the first main switches HM of all other battery management circuits 4 has been released based on the potential difference VC detected by the detection unit 9, and controls so as to perform a new connection operation when it is determined that the connection operation has been released.

[0088] Next, it is determined whether the elapsed time t since the second main switch LM was turned on has passed a predetermined time th3 or whether the current I flowing through the second main switch LM exceeds a limit current th4 (S05). If the condition is not met (S05: NO), the process returns to S04, and if the condition is met (S05: YES), the second main switch LM is turned off and a predetermined time is waited (S06). The battery management circuit 4 may measure the current I flowing through the second main switch LM, or may obtain it from an external current measurement circuit.

[0089] Next, the control circuit 10 forms the first path, that is, forms a path for the high-side current by turning on the first auxiliary switch HS (S07). Next, it is determined whether the voltage VC of the capacitor connection terminal 16 is equal to or higher than a predetermined value th5 (S08). If the condition is not met (S08: NO), it is determined whether the elapsed time t from turning on the first auxiliary switch HS is equal to or lower than a time limit th6 (S09). If it is within the time limit th6 (S09: YES), the process returns to S07. If it is beyond the time limit th6 (S09: NO), all currents and switches are turned off (S14). If the condition is met in S08 (S08: YES), the first auxiliary switch HS is turned off and the first main switch HM is turned on (S10). In this way, during the period T11 in Figure 6, that is, the period from S06 to S10, the battery management circuit 4 determines whether or not the connection operation of the second main switch LM of all other battery management circuits 4 has been released based on the potential difference VC detected by the detection unit 9, and controls so as to perform a new connection operation when it is determined that the connection operation has been released.

[0090] Next, it is determined whether the elapsed time t since the first main switch HM was turned on has passed a predetermined time th7 or whether the current I flowing through the first main switch HM exceeds a limited current th8 (S11). If the condition is not met (S11: NO), the process returns to S10, and if the condition is met (S11: YES), the first main switch HM is turned off and a predetermined time is waited (S12). The battery management circuit 4 may measure the current I flowing through the first main switch HM, or may obtain it from an external current measurement circuit.

[0091] Next, it is determined whether to end the process (S13), and if not (S13: NO), the process returns to S01, and if to end the process (S13: YES), all currents and switches are turned off (S14). The determination of whether to end the process is based on whether the variation in the output voltages of the multiple storage batteries 1 is within a predetermined range, that is, whether the output voltages are equalized.

[0092] The control circuits 10 belonging to multiple battery management circuits 4 can all be unified with the same processing flow shown in FIG. 5, and in this processing flow, the timing for turning on the second main switch LM, which is a low-side switch, can be consistent in all battery management circuits 4, and the timing for turning on the first main switch HM, which is a high-side switch, can also be consistent.

[0093] In Fig. 5, the predetermined values ​​th1 and th5 may be the same or different. The limit times th2 and th6 may be the same or different. The predetermined times th3 and th7 may be the same or different. The limit currents th4 and th8 may be the same or different.

[0094] Next, the operation in the event of a failure will be described.

[0095] In the case where any of the first main switches HM (high side main switches) or second main switches LM (low side main switches) in the multiple battery management circuits 4 suffers a short-circuit failure, or any of the capacitor connection terminals 16 suffers a short-circuit failure to the positive electrode connection terminal 14 or the negative electrode connection terminal 15, or the capacitor 3 suffers a short-circuit failure, the voltage equalization process can be stopped by the processing flow shown in Figure 5.

[0096] If any of the first main switches HM has a short-circuit failure or if any of the capacitor connection terminals 16 has a short-circuit to the positive electrode connection terminal 14, the loop of S02, S03, and S01 continues after the second auxiliary switch LS is turned on in S01, and the voltage of the capacitor connection terminal 16 does not become equal to or higher than a predetermined value within the time limit th2, so that the determination in S03 becomes NO and the process proceeds to S14 to turn off all currents and switches. In other words, the battery management circuit 4 stops the voltage equalization process.

[0097] If any of the second main switches LM has a short-circuit failure or if any of the capacitor connection terminals 16 has a short-circuit to the negative electrode connection terminal 15, the loop of S08, S09, and S07 continues after the first auxiliary switch HS is turned on in S07, and the voltage of the capacitor connection terminal 16 does not become equal to or lower than a predetermined value within the time limit th6, so that the determination in S09 becomes NO and the process proceeds to S14, where all the currents and switches are turned off. In other words, the battery management circuit 4 stops the voltage equalization process.

[0098] If the capacitor is short-circuited, the determination in either S03 or S09 becomes NO, and the process proceeds to S14, where all currents and switches are turned off. In other words, the battery management circuit 4 stops the voltage equalization process.

[0099] Therefore, in the event of any of the above failures, an excessive current does not flow through the battery management circuit 4 and the capacitor 3, and the voltage equalization process can be stopped.

[0100] Furthermore, according to the battery management circuit 4 having the above-mentioned control method, even if a fault as described above occurs in any part of the energy storage device 100 corresponding to multiple storage batteries 1, all of the control circuits 10 can independently and simultaneously detect the fault and stop the voltage equalization process. Therefore, there is no need to install a signal transmission path between the battery management circuits 4 to transmit information about the fault detected by each battery management circuit 4 to the other battery management circuits 4, and the circuitry does not become complicated.

[0101] The battery management circuit 4 may include a communication circuit for communicating with other battery management circuits 4. In this way, the communication circuit can transmit fault information to other control circuits 10.

[0102] As described above, the battery management circuit 4 of the present disclosure can suppress power loss in the voltage equalization process. Furthermore, the battery management circuit 4 can reliably stop the voltage equalization process in the event of a failure.

[0103] As described above, the battery management circuit 4 in the embodiment is a battery management circuit used for each of the multiple storage batteries 1 in the energy storage device 100 which includes multiple storage batteries 1 connected in series and one or more capacitors 3, and includes a positive electrode connection terminal 14 connected to the positive electrode of the corresponding storage battery, a negative electrode connection terminal 15 connected to the negative electrode of the corresponding storage battery, a capacitor connection terminal 16 connected to the terminal of the capacitor, and a control circuit 10 which controls the connection operation between the positive electrode connection terminal 14 or the negative electrode connection terminal 15 and the capacitor connection terminal 16, and performs control to synchronize the connection operation with the connection operation of other battery management circuits among the multiple battery management circuits 4.

[0104] According to this, since the multiple battery management circuits operate independently while being synchronized with each other, it is possible to suppress power loss in the voltage equalization process. In addition, since there is no need for a control unit that centrally controls the multiple battery management circuits 4, and no need for a signal transmission line that supplies a switching signal to each switch corresponding to the multiple storage batteries 1, and there is no delay error in the switching signal, synchronization can be easily achieved whether the number of multiple storage batteries 1 is small or large.

[0105] Here, the battery management circuit 4 further has a detection unit 9 that detects the potential difference between the capacitor connection terminal 16 and the positive electrode connection terminal 14 or the negative electrode connection terminal 15, and the control circuit 10 may synchronize with other battery management circuits using the detection result of the detection unit 9.

[0106] This makes it possible to synchronize with other battery management circuits using the potential difference between the capacitor connection terminal and the positive electrode connection terminal or the negative electrode connection terminal.

[0107] Here, the control circuit 10 may determine whether or not the connection operation of the other battery management circuit has been released based on the potential difference detected by the detection unit 9, and may perform control to perform a new connection operation when it is determined that the connection operation has been released.

[0108] According to this, it is possible to determine whether or not the connection operation of another battery management circuit has been released based on the potential difference detected by the detection unit, and when it is determined that the connection operation has been released, a new connection operation is performed, thereby achieving synchronization.

[0109] Here, the battery management circuit 4 has a first main switch HM that connects the capacitor connection terminal 16 to the positive electrode connection terminal 14, and a first sub switch HS that forms a first path that generates a potential difference by a current flowing from the positive electrode connection terminal 14 to the capacitor connection terminal 16, and the control circuit 10 may turn on the first main switch HM after the detection unit 9 detects that the potential difference in the first path has increased to a predetermined value within a first time after turning on the first sub switch HS.

[0110] According to this, synchronization can be achieved by determining whether the connection operation of another battery management circuit has been released (i.e., whether the potential difference has risen to a predetermined value) based on the potential difference in the first path by the first sub switch HS.

[0111] Here, the battery management circuit 4 has a second main switch LM that connects the capacitor connection terminal 16 to the negative electrode connection terminal 15, and a second sub switch LS that forms a second path that generates a potential difference by a current flowing from the capacitor connection terminal 16 to the negative electrode connection terminal 15, and the control circuit 10 may turn on the second main switch LM after detecting with the detection unit 9 that the potential difference in the second path has dropped to a predetermined value within a second time after turning on the second sub switch LS.

[0112] According to this, synchronization can be achieved by determining whether the connection operation of the other battery management circuit has been released (i.e., whether the potential difference has dropped to a predetermined value) based on the potential difference in the second path by the second sub switch LS.

[0113] Here, the battery management circuit 4 may further include a timer circuit 19 that determines the on-time of the first main switch HM and the second main switch LM, and a timer control circuit 20 that adjusts the on-time of the timer circuit 19 so as to reduce the mismatch with the on-time of the timer circuits 19 in other battery management circuits 4.

[0114] This makes it possible to adjust the unevenness of the on-times of the first main switches HM in the multiple battery management circuits 4, and also to adjust the unevenness of the on-times of the second main switches LM.

[0115] Here, the timer control circuit 20 may adjust the on time of the timer circuit 19 according to the time from when the first sub switch HS is turned on to when the potential difference in the first path rises to a predetermined value, or the time from when the second sub switch LS is turned on to when the potential difference in the second path falls to a predetermined value.

[0116] This makes it possible to adjust the ON time of the first main switch HM or the ON time of the second main switch LM to a more appropriate time.

[0117] In addition, the battery management circuit 4 in the embodiment is a battery management circuit used for each of the multiple storage batteries 1 in a power storage device 100 that has multiple storage batteries 1 and a capacitor 3 connected in series, and is equipped with a positive electrode connection terminal 14 connected to the positive electrode of the corresponding storage battery, a negative electrode connection terminal 15 connected to the negative electrode of the corresponding storage battery, a capacitor connection terminal 16 connected to a terminal of the capacitor, a first main switch HM connecting the positive electrode connection terminal 14 and the capacitor connection terminal 16, a second main switch LM connecting the negative electrode connection terminal 15 and the capacitor connection terminal 16, a first auxiliary switch HS forming a first path that generates a potential difference by a current flowing from the positive electrode connection terminal 14 to the capacitor connection terminal 16, a second auxiliary switch LS forming a second path that generates a potential difference by a current flowing from the capacitor connection terminal 16 to the negative electrode connection terminal 15, and a control circuit 10 that performs control to turn on the first main switch HM in accordance with the potential difference of the first path and to turn on the second main switch LM in accordance with the potential difference of the second path.

[0118] According to this, since the multiple battery management circuits 4 operate independently while being synchronized with each other, it is possible to suppress power loss in the voltage equalization process. Moreover, the above synchronization can be easily achieved whether the number of multiple storage batteries 1 is small or large.

[0119] Here, the battery management circuit 4 may further include a detection unit 9 that detects the potential difference in the first path and the potential difference in the second path, and the control circuit 10 may synchronize with other battery management circuits using the detection result of the detection unit 9.

[0120] This makes it possible to synchronize with other battery management circuits 4 using the potential difference between the capacitor connection terminal 16 and the positive electrode connection terminal 14 or the negative electrode connection terminal 15 .

[0121] Here, the control circuit 10 may turn on the first main switch HM after the detection unit 9 detects that the potential difference in the first path has risen to a predetermined value within a first time after the first sub switch HS is turned on, and may turn on the second main switch LM after the detection unit 9 detects that the potential difference in the second path has fallen to a predetermined value within a second time after the second sub switch LS is turned on.

[0122] According to this, synchronization can be achieved by determining whether the connection operation of the other battery management circuit has been released (i.e., whether the potential difference has risen to a predetermined value) based on the potential difference in the first path by the first sub switch. Also, synchronization can be achieved by determining whether the connection operation of the other battery management circuit has been released (i.e., whether the potential difference has fallen to a predetermined value) based on the potential difference in the second path by the second sub switch.

[0123] Here, the first path and the second path may share the resistive element 11 for detecting the potential difference.

[0124] According to this, the potential difference in the first path and the potential difference in the second path can be generated by only one resistance element.

[0125] Here, the first path may have a first current source 17 that flows a current from the positive electrode connection terminal 14 to the capacitor connection terminal 16, and the second path may have a second current source 18 that flows a current from the capacitor connection terminal 16 to the negative electrode connection terminal 15.

[0126] According to this, since the potential difference in the first path and the potential difference in the second path are generated by the current sources 17 and 18, respectively, it is possible to improve the accuracy of detecting the potential difference.

[0127] Moreover, the power storage device 100 in the embodiment includes the above-mentioned battery management circuit 4, one or more capacitors, and a plurality of storage batteries.

[0128] According to this, since the multiple battery management circuits operate independently while being synchronized with each other, it is possible to suppress power loss in the voltage equalization process. Moreover, the above synchronization can be easily achieved whether the number of multiple storage batteries 1 is small or large.

[0129] Moreover, the battery management method in the embodiment is a battery management method executed by a battery management circuit 4 used for each of a plurality of storage batteries 1 in a power storage device 100 comprising a plurality of storage batteries 1 connected in series and one or more capacitors 3, the battery management circuit 4 comprising a positive electrode connection terminal 14 connected to the positive electrode of the corresponding storage battery, a negative electrode connection terminal 15 connected to the negative electrode of the corresponding storage battery, a capacitor connection terminal 16 connected to a terminal of the capacitor, and a control circuit 10 that controls the connection operation between the positive electrode connection terminal 14 or the negative electrode connection terminal 15 and the capacitor connection terminal 16, and the battery management method determines whether or not the connection operation in the battery management circuit of another storage battery among the plurality of storage batteries has been released, and when it is determined that the connection operation has been released, performs a new connection operation.

[0130] According to this, since the multiple battery management circuits operate independently while being synchronized with each other, it is possible to suppress power loss in the voltage equalization process. Moreover, the above synchronization can be easily achieved whether the number of multiple storage batteries 1 is small or large.

[0131] Although the battery management circuit 4, the power storage device 100, and the battery management method according to one or more aspects of the present disclosure have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceived by a person skilled in the art to the present embodiments and forms constructed by combining components in different embodiments may also be included within the scope of one or more aspects of the present invention. [Explanation of symbols]

[0132] 1. Storage battery 2 sets of storage batteries 3. Capacitor 4 Battery management circuit 9. Detection Unit 10 Control circuit 11 Resistance element 12 Comparator 13 Comparator 14 Positive connection terminal 15 Negative connection terminal 16 Capacitor connection terminal 17 Current source 18 Current source 19 Timer Circuit 20 Timer control circuit 100 Electricity storage device B1~B5 Battery cells HM 1st main switch HS 1st Sub Switch LM 2nd main switch LS Second Secondary Switch

Claims

1. A battery management circuit for use with each of a plurality of storage batteries in a power storage device including a plurality of storage batteries connected in series and one or more capacitors, a positive electrode connection terminal connected to a positive electrode of a corresponding storage battery; a negative electrode connection terminal connected to a negative electrode of the corresponding storage battery; a capacitor connection terminal connected to a terminal of the capacitor; a control circuit that controls a connection operation between the positive electrode connection terminal or the negative electrode connection terminal and the capacitor connection terminal, and controls the connection operation to be synchronized with connection operations of other battery management circuits among the plurality of battery management circuits; a detection unit that detects a potential difference between the capacitor connection terminal and the positive electrode connection terminal or the negative electrode connection terminal, The control circuit uses the detection result of the detection unit to synchronize with other battery management circuits. Battery management circuit.

2. The control circuit determines whether the connection operation of the other battery management circuit has been released based on the potential difference detected by the detection unit, and performs control to perform a new connection operation when it is determined that the connection operation has been released.

2. The battery management circuit of claim 1.

3. The battery management circuit includes: a first main switch that connects the capacitor connection terminal to the positive electrode connection terminal; a first sub switch that forms a first path that generates a potential difference by a current flowing from the positive electrode connection terminal to the capacitor connection terminal, The control circuit turns on the first main switch after the detection unit detects that the potential difference in the first path has increased to a predetermined value within a first time period after the first sub switch is turned on.

2. The battery management circuit of claim 1.

4. The battery management circuit includes: a second main switch that connects the capacitor connection terminal to the negative electrode connection terminal; a second sub switch that forms a second path that generates a potential difference by a current flowing from the capacitor connection terminal to the negative electrode connection terminal, The control circuit turns on the second main switch after the detection unit detects that the potential difference in the second path has decreased to a predetermined value within a second time period after the second sub switch is turned on.

2. The battery management circuit of claim 1.

5. The battery management circuit includes: a second main switch that connects the capacitor connection terminal to the negative electrode connection terminal; a second sub switch that forms a second path that generates a potential difference by a current flowing from the capacitor connection terminal to the negative electrode connection terminal, The control circuit turns on the second main switch after the detection unit detects that the potential difference in the second path has decreased to a predetermined value within a second time period after the second sub switch is turned on.

4. The battery management circuit of claim 3.

6. The battery management circuit further includes a timer circuit that determines an on-time of the first main switch and the second main switch. a timer control circuit that adjusts the on-time of the timer circuit so as to reduce misalignment with the on-time of a timer circuit in another battery management circuit.

6. The battery management circuit of claim 5.

7. The timer control circuit includes: The on-time of the timer circuit is adjusted according to a time from when the first sub switch is turned on until the potential difference in the first path rises to a predetermined value, or a time from when the second sub switch is turned on until the potential difference in the second path falls to a predetermined value.

7. The battery management circuit of claim 6.

8. A battery management circuit for use with each of a plurality of storage batteries in a power storage device including a plurality of storage batteries and a capacitor connected in series, a positive electrode connection terminal connected to a positive electrode of a corresponding storage battery; a negative electrode connection terminal connected to a negative electrode of the corresponding storage battery; a capacitor connection terminal connected to a terminal of the capacitor; a first main switch that connects the positive electrode connection terminal and the capacitor connection terminal; a second main switch that connects the negative electrode connection terminal and the capacitor connection terminal; a first sub switch that forms a first path that generates a potential difference by a current flowing from the positive electrode connection terminal to the capacitor connection terminal; a second sub switch that forms a second path that generates a potential difference by a current flowing from the capacitor connection terminal to the negative electrode connection terminal; a control circuit that performs control to turn on the first main switch in response to a potential difference in the first path and to turn on the second main switch in response to a potential difference in the second path. Battery management circuit.

9. the battery management circuit further includes a detection unit that detects the potential difference in the first path and the potential difference in the second path, The control circuit synchronizes with other battery management circuits using the detection result of the detection unit.

9. The battery management circuit of claim 8.

10. The control circuit controls the first path within a first time period after the first sub switch is turned on. After the detection unit detects that the potential difference has increased to a predetermined value, the first main switch is turned on; After the detection unit detects that the potential difference in the second path has decreased to a predetermined value within a second time period since the second sub switch was turned on, the second main switch is turned on.

10. The battery management circuit of claim 9.

11. The first path and the second path share a resistive element for detecting the potential difference. The battery management circuit according to any one of claims 8 to 10.

12. The first path includes a first current source that passes a current from the positive electrode connection terminal to the capacitor connection terminal, The second path includes a second current source that passes a current from the capacitor connection terminal to the negative electrode connection terminal. The battery management circuit according to any one of claims 8 to 10.

13. A battery management circuit according to any one of claims 1 to 12; the one or more capacitors; The plurality of storage batteries. Energy storage device.

14. A battery management method executed by a battery management circuit used for each of a plurality of storage batteries in a power storage device including a plurality of storage batteries connected in series and one or more capacitors, comprising: The battery management circuit includes: a positive electrode connection terminal connected to a positive electrode of a corresponding storage battery; a negative electrode connection terminal connected to a negative electrode of the corresponding storage battery; a capacitor connection terminal connected to a terminal of the capacitor; a control circuit that controls a connection operation between the positive electrode connection terminal or the negative electrode connection terminal and the capacitor connection terminal, and controls the connection operation to be synchronized with connection operations of other battery management circuits among the plurality of battery management circuits; a detection unit that detects a potential difference between the capacitor connection terminal and the positive electrode connection terminal or the negative electrode connection terminal, The control circuit uses the detection result of the detection unit to synchronize with another battery management circuit, The battery management method includes: determining whether the connection operation in the battery management circuit of another storage battery among the plurality of storage batteries has been released; When it is determined that the connection has been released, a new connection operation is performed. How to manage batteries.

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