Gaming Machines

Abstract

To appropriately perform error determination in data.SOLUTION: A game machine of the present invention includes a master device (sub-CPU 330a), and multiple slave devices (amplifier 206a, RTC 348) connected in parallel to the master device via one serial communication line. The master device establishes communication with a specific slave device (amplifier 206a) among the multiple slave devices, prohibits communication with other slave devices, transmits specific information (volume information or the like) to the specific slave device, generates error determination information (CRC result) on the basis of the specific information, transmits the error determination information to the specific slave device following the specific information, and permits communication with the other slave devices after transmitting the error determination information.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The present invention relates to a gaming machine that determines by lottery whether or not to award a gaming advantage to a player. [Background technology]

[0002] Generally, in a gaming machine (pachinko machine), a game ball is launched toward a gaming area within a gaming board by a player operating a handle, and a lottery for a special symbol is executed on the condition that the game ball that flows down the gaming area enters a starting hole. Then, a special symbol is displayed variably on a special symbol display, and the special symbol determined by the lottery is displayed in a static state, thereby notifying the player of the lottery result. At this time, when a specific special symbol indicating a jackpot is displayed in a static state on the special symbol display, a big prize game, which is more advantageous for the player than a normal game, begins. In this big prize game, an attacker device opens and closes a predetermined number of times, allowing the game ball to enter the big prize hole, allowing the player to receive a large number of prize balls.

[0003] In such gaming machines, the CPU communicates with various peripheral devices using various communication standards, such as I2C communication. In such communications, to determine whether the transmitted and received data is correct, the sender and receiver inspect the data and compare the inspection results to determine whether there is an error. For example, a technology has been disclosed that performs checksum processing on commands such as variation patterns to check the validity of the data (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-301405 Summary of the Invention [Problem to be solved by the invention]

[0005] In communication between devices within a gaming machine, to determine whether the data being sent and received is correct, the sending side checks the data, sends the check results along with the transmitted data, and the receiving side also checks the data and determines whether the check results match the received check results. In such communication, if an error occurs in the data, the check results will differ, and the data will be determined to be abnormal. However, even if there is no error in the data, depending on the communication mode and the specifications of the peripheral devices, the check results may differ and the data may be determined to be abnormal.

[0006] In view of the above problems, the present invention aims to provide a gaming machine that can appropriately determine whether there is a data error. [Means for solving the problem]

[0007] In order to solve the above problem, the gaming machine of the present invention comprises a master device and a plurality of slave devices connected in parallel to the master device via a single serial communication line, wherein the master device establishes communication with a specific slave device among the plurality of slave devices, transmits specific information to the specific slave device, generates first error determination information based on the specific information, and transmits the first error determination information to the specific slave device, wherein the specific slave device generates second error determination information based on data received via the serial communication line from the time it starts receiving the specific information from the master device until it receives the first error determination information from the master device, and makes an error determination by comparing the first error determination information with the second error determination information, wherein after establishing communication with the specific slave device, the master device prohibits communication with other slave devices, transmits the first error determination information following the specific information, and allows communication with the other slave devices after transmitting the first error determination information. In order to solve the above problem, another gaming machine of the present invention comprises a master device and a plurality of slave devices connected in parallel to the master device via a single serial communication line, wherein the master device establishes communication with a specific slave device among the plurality of slave devices, prohibits communication with other slave devices, transmits specific information to the specific slave device, generates error determination information based on the specific information, transmits the error determination information to the specific slave device following the specific information, and after transmitting the error determination information, permits communication with the other slave devices. [Effects of the Invention]

[0008] According to the present invention, it is possible to appropriately determine whether there is an error in the data. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a perspective view of the gaming machine showing the door in an open state. [Figure 2] FIG. [Figure 3] FIG. 1 is a block diagram of a gaming machine. [Figure 4] This is a block diagram for explaining the control modes of the performance display unit, performance prop device, performance lighting device, and music output device on the sub-control board. [Figure 5] 10 is a flowchart showing a control mode in the sub-control board. [Figure 6] FIG. 10 is a diagram illustrating an example of commands used in a table. [Figure 7] FIG. 10 is a diagram illustrating an example of a table. [Figure 8] 10 is a timing chart for explaining a stacked structure. [Figure 9] 10 is a timing chart showing an example of processing by a performance execution means. [Figure 10] 10 is a timing chart showing another example of processing by the performance execution means. [Figure 11] FIG. 10 is an explanatory diagram showing a comparative example of a communication mode between a sub-CPU and an RTC. [Figure 12] FIG. 2 is an explanatory diagram showing an example of a communication mode between a sub-CPU and an RTC. [Figure 13] 10 is a flowchart for explaining the operation of a sub-CPU. [Figure 14] 10 is a timing chart showing a comparative example of a communication mode between a sub-CPU and an amplifier. [Figure 15] FIG. 10 is an explanatory diagram illustrating a process for generating a CRC result. [Figure 16] 10 is a timing chart showing a comparative example of communication between a sub-CPU, an amplifier, and an RTC. [Figure 17] FIG. 10 is an explanatory diagram illustrating a process for generating a CRC result. [Figure 18] 10 is a timing chart showing an example of communication between a sub-CPU, an amplifier, and an RTC. [Figure 19] FIG. 10 is an explanatory diagram for explaining a process of generating a CRC result. [Figure 20] 10 is a timing chart for explaining a transmission mode of a sub-CPU. [Figure 21] FIG. 1 is an external view for explaining the general mechanical configuration of a slot machine. [Figure 22] FIG. 1 is an external view of the slot machine with the front door open, illustrating the general mechanical configuration of the slot machine. [Figure 23] FIG. 10 is a diagram showing the arrangement of symbols on the reels. [Figure 24] FIG. 2 is a block diagram showing a schematic electrical configuration of the slot machine. DETAILED DESCRIPTION OF THE INVENTION

[0010] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Dimensions, materials, and other specific values ​​shown in the embodiments are merely examples for facilitating understanding of the invention and, unless otherwise specified, do not limit the present invention. In this specification and drawings, elements having substantially the same functions and configurations are designated by the same reference numerals to avoid redundant explanation, and elements not directly related to the present invention are not shown.

[0011] To facilitate understanding of the embodiments of the present invention, first, a brief description will be given of the mechanical and electrical configurations of the gaming machine, and then specific processing on each board will be described.

[0012] 1 is a perspective view of a gaming machine 100 of this embodiment, showing a state in which the door is open. As shown in the figure, the gaming machine 100 includes an outer frame 102 having four sides arranged in a substantially rectangular shape to form an enclosed space, a middle frame 104 attached to the outer frame 102 by a hinge mechanism so as to be able to open and close freely, and a front frame 106 attached to the middle frame 104 by a hinge mechanism so as to be able to open and close freely.

[0013] The middle frame 104, like the outer frame 102, has four sides arranged in a substantially rectangular shape to form an enclosed space, and a game board 108 is held in this enclosed space. A glass or resin transparent plate 110 is held in the front frame 106. When the middle frame 104 and the front frame 106 are closed against the outer frame 102, the game board 108 and the transparent plate 110 face each other substantially parallel, maintaining a predetermined distance between them, and the game board 108 can be seen through the transparent plate 110 from the front side of the gaming machine 100.

[0014] 2 is a front view of the gaming machine 100. As shown in this figure, an operating handle 112 that protrudes from the front side of the gaming machine 100 is provided at the bottom of the front frame 106. This operating handle 112 is provided so that it can be rotated by a player, and when the player rotates the operating handle 112 to perform a firing operation, a gaming ball is fired by a firing mechanism (not shown) with a strength that corresponds to the rotation angle of the operating handle 112. The gaming ball thus fired rises between rails 114a and 114b provided on the gaming board 108 and is guided to a playing area 116.

[0015] The play area 116 is a space formed between the play board 108 and the transparent plate 110, and is an area where the play balls can flow down or roll. The play board 108 is provided with a large number of nails and windmills, and the play balls guided into the play area 116 collide with the nails and windmills, causing them to flow down or roll in irregular directions.

[0016] The play area 116 includes a first play area 116a and a second play area 116b, which have different degrees of entry of game balls depending on the launch strength of the launch mechanism. The first play area 116a is located on the left side of the play area 116 as seen by a player facing the gaming machine 100, and the second play area 116b is located on the right side of the play area 116 as seen by a player facing the gaming machine 100. Because the rails 114a and 114b are on the left side of the play area 116, game balls launched by the launch mechanism with a launch strength less than a predetermined strength will enter the first play area 116a, and game balls launched with a launch strength equal to or greater than the predetermined strength will enter the second play area 116b.

[0017] The gaming area 116 is also provided with a general prize opening 118, a first start opening 120, and a second start opening 122 through which game balls can enter, and when a game ball enters the general prize opening 118, the first start opening 120, or the second start opening 122, a predetermined prize ball is paid out to the player. The number of prize balls may be any number greater than or equal to one, and the number of prize balls paid out for the general prize opening 118, the first start opening 120, and the second start opening 122 may be different or the same number of prize balls. In this case, it is also possible to set the number of prize balls paid out when a game ball enters the first start opening 120 to be less than the number of prize balls paid out when a game ball enters the second start opening 122.

[0018] A first starting area is provided within the first starting hole 120, and a second starting area is provided within the second starting hole 122. When a gaming ball enters the first starting hole 120 or the second starting hole 122 and enters the first starting area or the second starting area, a lottery is held to determine one of a plurality of pre-established special symbols. Each special symbol is associated with various gaming benefits, such as whether or not a player can execute a major winning game advantageous to the player and what kind of gaming state the player will be in the future. Therefore, when a gaming ball enters the first starting hole 120 or the second starting hole 122, the player not only acquires a predetermined prize ball, but also has the opportunity to acquire the right to receive various gaming benefits.

[0019] Furthermore, the second starting opening 122 is provided with a movable piece 122b that can be opened and closed, and the ease with which the gaming ball can enter the second starting opening 122 changes depending on the state of this movable piece 122b. Specifically, when the movable piece 122b is in a closed state, the gaming ball cannot enter the second starting opening 122. In contrast, when a gaming ball passes through the entry area within the gate 124 provided in the gaming area 116, a lottery for a normal symbol is held, and if a winning combination is selected in this lottery, the movable piece 122b is controlled to an open state for a predetermined time. In this way, when the movable piece 122b is in the open state, the movable piece 122b functions as a tray that guides the gaming ball to the second starting opening 122, making it easier for the gaming ball to enter the second starting opening 122. Here, it is assumed that when the second starting port 122 is in a closed state, it is not possible for game balls to enter the second starting port 122, but it may also be configured so that game balls can enter the second starting port 122 at a certain frequency even when the second starting port 122 is in a closed state.

[0020] Furthermore, the game area 116 is provided with a big prize opening 128 into which game balls can enter. An opening / closing door 128b is provided in an openable / closable manner at the big prize opening 128, and normally the opening / closing door 128b closes the big prize opening 128, preventing game balls from entering the big prize opening 128. In contrast, when the big prize game described above is executed, the opening / closing door 128b is opened, allowing game balls to enter the big prize opening 128. When a game ball enters the big prize opening 128, predetermined prize balls are paid out to the player.

[0021] In addition, at the bottom of the game area 116, there is provided an outlet 130 that discharges game balls that do not enter any of the general prize opening 118, the first start opening 120, the second start opening 122, or the big prize opening 128 from the game area 116 to the back side of the game board 108.

[0022] The gaming machine 100 is equipped with a performance display device 200 consisting of a liquid crystal display device, a performance prop device 202 consisting of a drive device, a performance lighting device 204 consisting of lamps that can be controlled to various lighting modes and emission colors, a music output device 206 consisting of a speaker, and a performance operation device 208 that accepts operations by the player, as performance devices that perform performances while the game is in progress.

[0023] The effect display device 200 is equipped with an effect display unit 200a consisting of an image display unit that displays images, and this effect display unit 200a is arranged in the approximate center of the gaming board 108 so as to be visible from the front side of the gaming machine 100. As shown in the figure, this effect display unit 200a displays effect symbols 210a, 210b, and 210c in a variable manner, and a variable effect is executed in which the result of the big role lottery is notified to the player depending on the stop display mode of each of these effect symbols 210a, 210b, and 210c.

[0024] The effect role device 202 is disposed in front of the effect display unit 200a, and moves and rotates in an area visible to the player, thereby giving the player a sense of anticipation of a big win. For example, the rotating role device 202a as the effect role device 202 in FIG. 2 rotates about a front-to-rear axis in conjunction with the rotation of a motor (a pulse motor or a geared motor) that serves as a drive source, during the variable display of the above-mentioned effect symbols 210a, 210b, and 210c. Also, the moving role device 202b as the effect role device 202 in FIG. 2 is normally retracted to a retraction area on the gaming board 108, but moves to the front of the effect display unit 200a during the variable display of the above-mentioned effect symbols 210a, 210b, and 210c.

[0025] The effect lighting device 204 is composed of, for example, an LED (Light Emitting Diode) and is provided on the effect gimmick device 202, the game board 108, etc., and is controlled to light up in various ways in accordance with the images displayed on the effect display section 200a.

[0026] The music output device 206 is provided at the upper position of the front frame 106 or at the lowermost position of the outer frame 102, and outputs various music pieces toward the front side of the gaming machine 100 in accordance with the images displayed on the performance display section 200a.

[0027] The effect operation device 208 is composed of buttons that are pressed by the player and a rotation operation unit (for example, a jog dial) that is rotated by the player, and is located approximately in the center of the width of the gaming machine 100, and below the transparent plate 110. This effect operation device 208 is activated in accordance with the images displayed on the effect display unit 200a, and when it receives an operation from the player within the operation activation period, various effects are executed in accordance with the operation.

[0028] Additionally, behind the performance operation device 208 is an upper tray 132 to which prize balls paid out from the gaming machine 100 and game balls dispensed from the game ball dispenser are guided, and when this upper tray 132 is full of game balls, the game balls are guided to a lower tray 134. Additionally, a ball ejection hole (not shown) is formed on the bottom surface of this lower tray 134 to eject game balls from the lower tray 134. This ball ejection hole is normally closed by an opening / closing plate (not shown), but by sliding the ball ejection knob 134a left and right in the figure, the opening / closing plate slides together with the ball ejection knob 134a, making it possible to eject game balls from the ball ejection hole to below the lower tray 134.

[0029] In addition, the game board 108 is provided with a first special symbol display 160, a second special symbol display 162, a first special symbol reserved display 164, a second special symbol reserved display 166, a normal symbol display 168, a normal symbol reserved display 170, and a right-hit notification display 172 at positions outside the game area 116 and visible to the player. Each of these displays 160 to 172 is a device for displaying various situations related to the game.

[0030] (Internal configuration of control means) FIG. 3 is a block diagram showing the internal configuration of the control means that controls the progress of the game. The main control board 300 controls the basic operations of the game. This main control board 300 is equipped with a main CPU 300a, a main ROM 300b, and a main RAM 300c. The main CPU 300a reads out programs stored in the main ROM 300b and performs arithmetic processing based on input signals from each detection switch and timer, and also directly controls each device and display, or sends commands to other boards depending on the results of the arithmetic processing. The main RAM 300c functions as a data work area during arithmetic processing by the main CPU 300a.

[0031] The main control board 300 is connected to a general prize opening detection switch 118s that detects when a game ball has entered the general prize opening 118, a first start opening detection switch 120s that detects when a game ball has entered the first start opening 120, a second start opening detection switch 122s that detects when a game ball has entered the second start opening 122, a gate detection switch 124s that detects when a game ball has passed through the gate 124, and a special prize opening detection switch 128s that detects when a game ball has entered the special prize opening 128, and detection signals are input from each of these detection switches to the main control board 300.

[0032] In addition, the main control board 300 is connected to a normal electric role solenoid 122c that operates the movable piece 122b of the second starting opening 122, and a large prize opening solenoid 128c that operates the opening and closing door 128b that opens and closes the large prize opening 128, and the main control board 300 controls the opening and closing of the second starting opening 122 and the large prize opening 128.

[0033] Furthermore, the main control board 300 is connected to a first special pattern display 160, a second special pattern display 162, a first special pattern reserved display 164, a second special pattern reserved display 166, a normal pattern display 168, a normal pattern reserved display 170, and a right-hit notification display 172, and the display of each of these displays is controlled by the main control board 300.

[0034] The gaming machine 100 of this embodiment is broadly divided into a special game that is started when a gaming ball enters the first start hole 120 or the second start hole 122, and a normal game that is started when a gaming ball passes through the gate 124. The main ROM 300b of the main control board 300 stores various programs for progressing the special game and the normal game, as well as data and tables required for various games.

[0035] In addition, a dispensing control board 310 and a sub-control board 330 are connected to the main control board 300.

[0036] The payout control board 310 controls the firing of game balls and the payout of prize balls. This payout control board 310 also has a CPU, ROM, and RAM, and is connected to the main control board 300 so that it can communicate bidirectionally. A game information output terminal board 312 is connected to this payout control board 310, and various information on the progress of the game output from the main control board 300 is output to a hall computer or the like of the gaming parlor (hall) via the payout control board 310 and the game information output terminal board 312.

[0037] A payout motor 314 is connected to the payout control board 310 to pay out the game balls stored in the storage section to the player as prize balls. The payout control board 310 controls the payout motor 314 based on a payout number designation command sent from the main control board 300 to control the motor 314 to pay out a predetermined number of prize balls to the player. At this time, the number of paid out game balls is detected by a payout ball counting switch 316s, and it is possible to determine whether the prize balls that should have been paid out have been paid out to the player.

[0038] Also connected to the payout control board 310 is a tray full detection switch 318s that detects the full state of the lower tray 134. This tray full detection switch 318s is provided in a passage that leads game balls paid out as prize balls to the lower tray 134, and a game ball detection signal is input to the payout control board 310 every time a game ball passes through the passage.

[0039] Then, when a predetermined amount or more of game balls are accumulated in the lower tray 134 and it reaches a full state, game balls accumulate in the passage leading to the lower tray 134, and game ball detection signals are continuously input from the tray full detection switch 318s to the payout control board 310. When the payout control board 310 receives game ball detection signals continuously for a predetermined period of time, it determines that the lower tray 134 is in a full state, and sends a tray full command to the main control board 300. On the other hand, when the continuous input of game ball detection signals stops after sending the tray full command, it determines that the full state has been released, and sends a tray full release command to the main control board 300.

[0040] The payout control board 310 is also provided with a launch control circuit 320 that controls the launch of gaming balls. A touch sensor 112s that is provided on the operating handle 112 and detects when a player touches the operating handle 112, and an operation volume 112a that detects the operating angle of the operating handle 112 are connected to the payout control board 310. When signals are input from the touch sensor 112s and the operation volume 112a, the launch control circuit 320 controls the energization of a launch solenoid 112c provided on the gaming ball launcher to launch the gaming balls.

[0041] The sub-control board 330 mainly controls various effects during game play, standby, etc. The sub-control board 330 is equipped with a sub-CPU 330a, sub-ROM 330b, and sub-RAM 330c, and is connected to the main control board 300 so that it can communicate in one direction from the main control board 300 to the sub-control board 330 to prevent fraud. The sub-CPU 330a reads out programs stored in the sub-ROM 330b and performs arithmetic processing based on commands transmitted from the main control board 300, input signals from a timer, etc., and also controls the execution of effects. At this time, the sub-RAM 330c functions as a data work area during arithmetic processing by the sub-CPU 330a.

[0042] Specifically, the sub-control board 330 performs image display control to display images on the performance display unit 200a. The sub-ROM 330b stores a large amount of image data such as designs and backgrounds to be displayed on the performance display unit 200a, and the sub-CPU 330a reads the image data from the sub-ROM 330b to a VRAM (not shown) to control the image display on the performance display unit 200a. The sub-control board 330 also controls the drive of the performance prop device 202, controls the lighting of the performance lighting device 204, and performs music output control to output music from the music output device 206.

[0043] FIG. 4 is a block diagram illustrating the control modes of the sub-control board 330 for the effect display unit 200a, the effect prop device 202, the effect lighting device 204, and the music output device 206, and FIG. 5 is a flowchart illustrating the control modes common to these devices. The sub-CPU (CPU) 330a provided on the sub-control board 330 functions as effect determination means 332 and effect execution means 334 in cooperation with the programs stored in the sub-ROM 330b and the sub-RAM 330c. The effect determination means 332 performs status management, analyzes commands sent from the main control board 300, and determines effect patterns (contents indicating the flow of the effect) such as variable effects corresponding to the commands. It also generates messages for each device (the effect display unit 200a, the effect prop device 202, the effect lighting device 204, and the music output device 206) and adds them to the operation buffer. Here, the messages indicate the output timing to the devices and the operation pattern of each device. Then, the effect execution means 334 analyzes each message stored in the operation buffer and transmits commands to each device such as the image IC 340a, the controller 342, the music IC 346a, etc. according to the output timing included in the message. The effect determination means 332 and the effect execution means 334 are both interrupt-responsive processes (interrupt processes) and are executed at the interrupt timing associated with each device.

[0044] For example, as shown in FIG. 5, the effect determination means 332 waits for a predetermined interrupt period (e.g., 33.3 msec) to arrive (NO in S10). When the predetermined interrupt period arrives (YES in S10), it determines an image pattern (content corresponding to the image to be displayed on the effect display unit 200a among the effects indicated by the effect pattern) based on the effect pattern (S11). The effect determination means 332 then transmits the determined image pattern and its output timing as a message to the operation buffer (S12). The effect execution means 334 generates an image command capable of specifying image data based on the image pattern stored in the operation buffer (S13). The effect execution means 334 transmits the image command to the image IC 340a (S14), and repeats the process from step S10. The image IC 340a, also known as a VDP (Video Display Processor), reads image data specified by the image command from the image ROM 340b to the image RAM (VRAM) 340c, and sequentially outputs the image data to the effect display unit 200a. Note that some kind of image is always displayed on the effect display unit 200a. Therefore, the effect determination means 332 is always determining image data for each interrupt period. Note that the image RAM 340c has different layers, and different image data can be stored in each layer. The image IC 340a then superimposes the image data stored in the multiple layers, and the superimposed image data is output to the effect display unit 200a. Note that here, the image IC 340a, image ROM 340b, and image RAM 340c are shown as separate entities, but any two or all of these devices may be configured integrally, or any two or all of these devices may be configured integrally with the sub-CPU 330a.

[0045] In parallel with the control of the image IC 340a, the effect determination means 332 determines a reel pattern (contents indicating a series of operations of the reel device 202 among the effects indicated by the reel pattern) based on the reel pattern when a predetermined interrupt period (e.g., 2 msec) arrives (YES in S10), in conjunction with the determination of the reel pattern (S11). The effect determination means 332 then transmits the determined reel pattern and its output timing as a message to the operation buffer (S12). The effect execution means 334 generates a reel command indicating at least one of the direction of travel (direction of rotation), amount of travel (amount of rotation), and speed of travel (speed of rotation) based on the reel pattern stored in the operation buffer (S13). The effect execution means 334 transmits the reel command to the controller 342 at predetermined time intervals according to the reel pattern (S14), and repeats the process from step S10. The controller 342 drives the reel device 202 according to the reel command. Here, the performance prop device 202 operates only when the prop pattern is determined.

[0046] Furthermore, when a predetermined interrupt period (e.g., 33 msec) arrives (YES in S10) following the determination of the effect pattern, the effect determination means 332 determines a lighting pattern (contents indicating a series of lighting modes (light emission modes) of the effect lighting device 204 among the effects indicated by the effect pattern) based on the effect pattern (S11). Then, the effect determination means 332 transmits the determined lighting pattern and its output timing as a message to the operation buffer (S12). The effect execution means 334 generates a lighting command indicating the lighting mode (e.g., whether or not to light and brightness) of the effect lighting device 204 based on the message (lighting pattern) stored in the operation buffer (S13). The effect execution means 334 transmits lighting commands to the controller 342 at predetermined time intervals according to the lighting pattern, as with the special object pattern (S14), and repeats the processing from step S10. The controller 342 causes the effect lighting device 204 to emit light according to the lighting command. In this way, the lighting of the lamp that is the effect lighting device 204 is controlled. The effect lighting device 204 is constantly turning on and off repeatedly. Therefore, the effect determination means 332 is constantly determining an effect pattern for each interruption period.

[0047] In parallel with the control of the image IC 340a and the controller 342, the effect determination means 332 determines a music pattern (contents corresponding to the music to be output to the music output device 206 from among the effects indicated by the effect pattern) based on the effect pattern when a predetermined interrupt period (e.g., 50 msec) arrives (YES in S10), in conjunction with the determination of the effect pattern (S11). The effect determination means 332 then sends the determined music pattern and its output timing as a message to the operation buffer (S12). The effect execution means 334 generates a music command capable of identifying music data based on the music pattern stored in the operation buffer (S13). The effect execution means 334 sends the music command to the music IC 346a (S14), and repeats the process from step S10. The music IC 346a reads the music data identified by the music command from the music ROM 346b into the music IC 346a, and sequentially outputs the music data to the music output device 206. Although the music IC 346a and music ROM 346b are shown as separate entities here, they may be configured as an integrated unit, or they may be configured as an integrated unit with the sub-CPU 330a.

[0048] The music output device 206 includes an amplifier 206a and a speaker 206b. The amplifier 206a amplifies music data (music signals) input from the music IC 346a and outputs an analog signal. The speaker 206b generates physical vibrations from the amplified analog signal and outputs sound (music). The sub-CPU 330a can also send commands to the amplifier 206a via I2C (Inter-Integrated Circuit) communication to control the amplification amount of the amplifier 206a, i.e., the volume of the sound output from the speaker 206b. Some music is always being output from the music output device 206. Therefore, the effect determination means 332 is always determining music data for each interrupt period. The music IC 346a has multiple music buffers, each capable of storing different music data. Then, the music IC 346 a superimposes the music data stored in the multiple music buffers, and outputs the superimposed music data to the music output device 206 .

[0049] The I2C communication used to control the volume of the amplifier 206a of the music output device 206 is a short-distance serial communication line in which one master device (here, the sub-CPU 330a) and multiple slave devices (e.g., the amplifier 206a) are connected in parallel (party line connection, star connection) by two lines: a clock signal line and a data signal line. The parallel connection here refers to a connection in which the master device and multiple slave devices are each connected to a single I2C communication line, which is a serial communication line, and the master device can communicate directly with each of the multiple slave devices. In I2C communication, the master device always has control over the communication. Specifically, the master device first outputs data in the order of a Start Condition, an address, and a Read / Write request based on a clock. Only slave devices with matching addresses can continue to transmit and receive data. Transmission and reception then ends when the master device outputs a Stop Condition. Between the Start Condition and the Stop Condition, the master device communicates only with one slave device and does not accept communication requests from other slave devices (does not communicate). After completing communication with one slave device, the master device can communicate with another slave device.

[0050] 4, a plurality of slave devices, for example, an amplifier 206a and an RTC (Real Time Clock) 348, are connected to the clock signal line and data signal line of the I2C communication connected to the sub-CPU 330a. When the sub-CPU 330a instructs the volume of music data, it transmits the address of the amplifier 206a and then transmits volume information indicating the volume to the amplifier 206a. When the sub-CPU 330a reads the current time, it transmits the address of the RTC 348 and receives time information indicating the current time from the RTC 348.

[0051] The RTC 348 is an integrated circuit (electrical element) that generates digital data such as time and date based on an arbitrary clock. The RTC 348 has a power supply independent of the power supply of the sub-CPU 330a, and can continue to update the time and date even if the power supply of the sub-CPU 330a is cut off. Therefore, the RTC 348 continues to measure time from the time set during initialization, and the sub-CPU 330a can use the measured time to perform other processes such as presentations.

[0052] Furthermore, detection signals are input to sub-control board 330 from press detection switch 208s, which detects that performance operation device 208 has been pressed, and from rotation detection switch 209s, which detects that performance operation device 208 has been rotated. When a detection signal is input from performance operation device 208 (press detection switch 208s or rotation detection switch 209s), controller 342 transmits that information to performance determination means 332, and performance determination means 332 determines various performances, such as displaying an image on performance display unit 200a, in accordance with the input of such detection signal.

[0053] Here, a series of functional units such as sub-CPU 330a, sub-RAM 330c, image IC 340a, image ROM 340b, image RAM 340c, controller 342, music IC 346a, music ROM 346b, etc. are integrated into a single integrated circuit as an SoC (System-on-a-Chip). However, it is possible to arbitrarily set which functional units are integrated into such an SoC. Furthermore, each functional unit such as sub-CPU 330a, sub-RAM 330c, image IC 340a, image ROM 340b, image RAM 340c, controller 342, music IC 346a, music ROM 346b, etc. may be integrated into a separate integrated circuit and electrically connected.

[0054] Each board is connected to a power supply board (not shown), and power is supplied to each board from a commercial power source via the power supply board.

[0055] <Control of the lighting device 204> As described above, the effect determination means 332 determines an effect pattern, determines a lighting pattern based on the effect pattern, and transmits the determined pattern to the operation buffer. Then, the effect execution means 334 generates lighting commands indicating the lighting modes of the effect lighting device 204 based on the messages stored in the operation buffer, and transmits the generated commands to the controller 342. Here, a table of commands indicating the lighting patterns of the effect lighting device 204 is used as the message.

[0056] FIG. 6 is a diagram showing an example of commands used in a table. As shown in FIG. 6, the command "PUT" is a command to maintain a set brightness for a set duration. The command "SETUP" is a command to emit light at a set brightness. The command "SLINE" is a command to change the brightness from the initial brightness to the set brightness at equal intervals over a set duration. The command "WAIT" is a command to maintain a set brightness for a set duration. The command "LOOP" is a command to repeat the commands up to the command "NEXT" a set number of times. The command "NEXT" is a command indicating the end of the command "LOOP". The command "JUMP" is a command to jump the analysis destination to a specified address (table) and not return the analysis destination to the original address. The command "CALL" is a command to jump the analysis destination to a specified address (table) and return the analysis destination to the address next to the original address. Of the above commands, the "PUT", "SETUP", "SLINE", "WAIT", "LOOP", and "NEXT" commands consist of only a 2-byte basic command, while the "JUMP" and "CALL" commands consist of a 6-byte basic command and an extended command.

[0057] Fig. 7 is a diagram showing an example of a table. As shown in Fig. 7(a), the table is made up of 10 commands shown in 10 rows: command "LOOP", command "SLINE", command "SLINE", command "LOOP", command "SLINE", command "WAIT", command "SLINE", command "NEXT", command "NEXT", and command "END".

[0058] The table in FIG. 7(a) is operated by the effect execution means 334 according to the flowchart shown in FIG. 7(b). That is, the command "LOOP" (outside) on the first line repeatedly executes the multiple commands enclosed by the command "NEXT" (outside) on the ninth line. The command "SLINE" specifies the final brightness using 5 bits (32 levels from "00h" to "1Fh") and the duration using 6 bits (62 levels from "02h" to "3Fh", and if the interrupt period is 33.33 ms, 66.67 ms to 2010.00 ms). For example, the command "SLINE" on the second line linearly changes the brightness from the initial brightness (e.g., 0) to the final brightness (e.g., 31 (1FH)) over a duration of 2 seconds. The command "SLINE" on the third line linearly changes the brightness from the initial brightness (e.g., 31) to the final brightness (e.g., 0) over a duration of 2 seconds. The "LOOP" command (inside) on line 4 repeatedly executes the multiple commands enclosed by the "NEXT" command (inside) on line 8. The "SLINE" command on line 5 linearly changes the brightness from the starting brightness (e.g., 0) to the final brightness (e.g., 31) over a duration of 2 seconds. The "WAIT" command on line 6 maintains the starting brightness (e.g., 31) for a duration of 1 second. The "SLINE" command on line 7 linearly changes the brightness from the starting brightness (e.g., 31) to the final brightness (e.g., 0) over a duration of 2 seconds. When all repeated processes have been completed, the "END" command on line 10 terminates processing of the table.

[0059] For example, if the lighting effect device 204 is made up of three-color (RGB) LEDs, a table is set for each of the three color LEDs. The lighting effect execution means 334 references each table from the operation buffer, analyzes each table, specifies the lighting mode (e.g., brightness) that should be emitted by the lighting effect device 204, and generates a lighting command.

[0060] For example, the effect execution means 334 analyzes the table at every predetermined interrupt period (e.g., 33 msec), and identifies the brightness according to the execution time by referring to the command to be analyzed in the table and the execution time of that command (the time elapsed since the start of execution). For example, the effect execution means 334 analyzes the table shown in FIG. 7(a), and if the command to be analyzed is the command "SLINE" on the second line which linearly changes the brightness from 0 to 31 over a duration of 2 seconds, and the execution time of the command "SLINE" is 1 second, the brightness will be the intermediate value of 15. Also, if the command to be analyzed is the command "WAIT" on the sixth line which maintains the initial brightness (e.g., 31) for a duration of 1 second, and the execution time of the command "WAIT" is 0.5 seconds, the brightness will be 31.

[0061] In this way, the brightness of the illumination pattern changes from moment to moment depending on the elapsed time. Therefore, the performance execution means 334 cannot identify the brightness unless it analyzes the table and recognizes the command to be analyzed and the execution time of that command. For this reason, the performance execution means 334 performs the current analysis based on the results of the previous analysis (brightness generation information), for example, the command to be analyzed and the execution time of that command. In other words, the performance execution means 334 cannot perform the current analysis unless the results of the previous analysis are stored. In order to continuously identify the brightness corresponding to a predetermined table in this way, the performance execution means 334 must analyze the table and derive the analysis results at every predetermined interrupt period.

[0062] When the brightness is specified in this way, the performance execution means 334 generates a lighting command by associating the identifier of the target performance lighting device 204 with the brightness, and transmits the generated lighting command to the controller 342. In reality, the performance execution means 334 transmits the lighting command to the controller 342 via a DMA (Direct Memory Access) controller. Therefore, after setting the DMA controller to transmit the lighting command, the performance execution means 334 can perform processing other than the transmission processing without being involved in the transmission processing.

[0063] In this embodiment, the effect determination means 332 may determine multiple effect patterns in parallel. For example, this may occur when the player presses the effect operation device 208 and an effect is executed based on the operation while a variable effect is being performed in which the result of the big role lottery is notified to the player based on the game ball entering the first starting hole 120 or the second starting hole 122. In this case, multiple effect patterns are determined in parallel, and multiple illumination patterns are also determined in parallel based on the effect patterns.

[0064] In order to manage multiple such illumination patterns in parallel, this embodiment employs a layered structure (hereinafter referred to as layers). The operation buffer has multiple different layers, and tables and luminance generation information, which is the analysis result of the tables, can be associated with each layer. Note that different tables can be assigned to different layers at the same time, but different tables cannot be assigned to the same layer in an overlapping manner.

[0065] Each layer is assigned a priority. When a table assigned to a high-priority layer and a table assigned to a low-priority layer are executed simultaneously, both are analyzed. However, the analysis result of the table assigned to the high-priority layer takes precedence over the analysis result of the table assigned to the low-priority layer, and only the brightness specified by the table assigned to the high-priority layer is transmitted as a lighting command to the controller 342. Therefore, the player will see the effect lighting device 204 emitting light at the brightness specified by the table assigned to the high-priority layer. Note that the priority of the table assigned to a layer is equal to the layer priority, so the layer priority can be considered to be equal to the priority of the table assigned to the layer. Similarly, analyzing a table assigned to a layer is synonymous with analyzing the layer, so the analysis of a layer can be considered to be equal to the analysis of the table assigned to the layer.

[0066] Fig. 8 is a timing chart for explaining the stacked structure. For convenience of explanation, Fig. 8 will explain using two layers. However, the number of layers is not limited to two, and may be set to three or more. In Fig. 8, it is assumed that layer 1 has a higher priority than layer 2.

[0067] For example, suppose that at time T0, the effect determination means 332 assigns to layer 1, based on predetermined lighting pattern 1, table 1 consisting of a command "SLINE" that causes a linear change from brightness 0 to brightness 31 over a duration of 3 seconds. Also, suppose that at the same time T0, the effect determination means 332 assigns to layer 2, based on predetermined lighting pattern 2 different from lighting pattern 1, table 2 consisting of a command "SETUP" that causes light to be emitted at brightness 31 and a command "WAIT" that maintains the initial brightness for a duration of 5 seconds.

[0068] Thus, from time T0 to time T1, three seconds later, tables 1 and 2 are assigned to layers 1 and 2, respectively, and from time T1 to time T2, two seconds later, table 2 is assigned to layer 2. In this case, from time T0 to time T1, three seconds later, the effect execution means 334 analyzes table 1 assigned to layer 1 and table 2 assigned to layer 2, while prioritizing the analysis result of table 1 assigned to layer 1 over the analysis result of table 2 assigned to layer 2, and transmits only the brightness specified by table 1 assigned to layer 1 as a lighting command to the controller 342. Also, from time T1 to time T2, two seconds later, the effect execution means 334 analyzes table 2 assigned to layer 2, while transmitting only the brightness specified by table 2 assigned to layer 2 as a lighting command to the controller 342. In this way, the player will visually recognize the effect lighting device 204, whose brightness gradually increases over three seconds and is maintained for two seconds.

[0069] Here, attention is focused on the processing of the performance execution means 334 from time T0 to time T1, three seconds later. Here, Tables 1 and 2 are assigned to Layers 1 and 2, respectively, and Layer 1 is set to have a higher priority than Layer 2. Given this, if only the luminance determined by Table 1 assigned to Layer 1, which has a higher priority, is required, it may be thought that analyzing only Table 1 assigned to Layer 1 would be sufficient. However, as described above, the performance execution means 334 cannot perform the current analysis unless the previous analysis result is retained. In order to continuously determine the luminance corresponding to a specific table, the performance execution means 334 must analyze the table and derive the analysis result at each predetermined interrupt period. For example, in the example of FIG. 8 , the analysis result of Table 2 assigned to Layer 2 is not reflected in the lighting command from time T0 to time T1, but must be reflected from time T1 onward. To obtain the analysis result, the performance execution means 334 must continue analyzing Table 2 assigned to Layer 2 between time T0 and time T1.

[0070] Specifically, the performance execution means 334 analyzes the table and stores the results as brightness generation information in association with the layer. The brightness generation information includes a table identifier (for example, a table address), a command (or its address) to be analyzed, a command (or its address) if there is a repetition or call, the number of repetitions or calls, the execution time of the command to be analyzed (the elapsed time from the start of execution), the previous brightness value, a brightness change value, etc.

[0071] For example, the effect execution means 334 determines that the command "SLINE" is being executed based on Table 1, which linearly changes the brightness from 0 to 31 over a duration of 3 seconds, from time T0 to time T1, three seconds later. The effect execution means 334 adds the brightness change value (e.g., 0.36 = 32 × 33 msec / 3 seconds) as brightness generation information to the previous brightness value (e.g., 15) until the execution time of the command "SLINE" reaches 3 seconds, thereby determining the current brightness value (here, 15.36). Note that, for convenience of explanation, real numbers are used as the previous brightness value and brightness change value, but in reality, they are multiplied by a constant and expressed as integers. After processing the current brightness value, the effect execution means 334 overwrites the previous brightness value with the current brightness value for the next analysis.

[0072] Furthermore, the performance execution means 334 recognizes that the illumination pattern based on Table 1 has ended at time T1, and determines that a command "WAIT" is being executed to maintain the brightness at the start based on Table 2 from time T1 until time T2, two seconds later, and determines the current brightness value (here, 31) by using the previous brightness value (for example, 31) as is until the execution time of the command "WAIT" reaches five seconds. At this time, after processing the current brightness value, the performance execution means 334 overwrites the previous brightness value with the current brightness value for the next analysis.

[0073] Here, if the performance execution means 334 were to analyze only layer 1 from time T0 to time T1, the luminance generation information of table 2 assigned to layer 2 at time T1 would not be generated, and it would become impossible to identify the luminance from time T1 based on table 2. Therefore, the performance execution means 334 analyzes at least all layers to which tables are validly assigned, regardless of the layer priority, at every predetermined interrupt period (e.g., 33 msec), and generates the luminance generation information for each layer.

[0074] Fig. 9 is a timing chart showing an example of processing by the effect execution means 334. Here, an example of processing by the effect execution means 334 at any time T3 (for example, 1.5 seconds after time T0) between time T0 and time T1 in Fig. 8 will be described. This processing is performed at a predetermined interruption period (for example, 33 msec) and is completed within the interruption period.

[0075] At time T3, first, the performance execution means 334 sets layer 1 as the analysis target, references the brightness generation information of layer 1, and identifies table 1 from the table identifier in the brightness generation information. Based on the fact that the command to be analyzed is the command "SLINE," the performance execution means 334 adds the previous brightness value of "15" to the brightness change value of "0.36" to identify the current brightness value of "15.36." For the next analysis, the performance execution means 334 overwrites the previous brightness value in the brightness generation information of layer 1 with the current brightness value of "15.36."

[0076] Next, the performance execution means 334 sets layer 2 as the analysis target, references the brightness generation information of layer 2, and identifies table 2 from the table identifier in the brightness generation information. Furthermore, based on the fact that the command to be analyzed is the command "WAIT," the performance execution means 334 uses the previous brightness value of "31" as is to identify the current brightness value of "31." Furthermore, for the next analysis, the performance execution means 334 overwrites the previous brightness value in the brightness generation information of layer 2 with the current brightness value of "31."

[0077] Next, the performance execution means 334 specifies a brightness value to be sent to the performance lighting device 204 based on the priority of each layer. Here, the performance execution means 334 determines whether tables are effectively assigned to layers in descending order of priority, and specifies the layer with the highest priority (here, layer 1) among the layers to which tables are effectively assigned (e.g., layer 1, layer 2). Then, the performance execution means 334 sends the brightness specified based on table 1 assigned to layer 1 (e.g., previous brightness value "15.36") to the controller 342 as a lighting command.

[0078] Specifically, as shown in Fig. 9, the performance execution means 334 starts sending lighting commands by setting the DMA controller to send lighting commands, and then the DMA controller sends the lighting commands to the controller 342 independently of the performance execution means 334. In this way, the performance execution means 334 shifts the actual sending process of the lighting commands to the DMA controller that can operate independently of itself, and can then immediately execute other processes, for example, processes for other performance lighting devices 204. In this way, even when multiple layers are provided, lighting commands are sent appropriately based on the table assigned to the layer with the highest priority.

[0079] In Figure 9, an example has been given in which the performance execution means 334 first analyzes table 1 assigned to layer 1, and then analyzes table 2 assigned to layer 2, but this is not limited to this case, and analysis can be performed from a table assigned to any layer regardless of priority.

[0080] However, if there are multiple layers and transmission is to begin after analysis is completed for all layers to which tables are validly assigned, as in Fig. 9, depending on the number of layers, there is a risk that the start of transmission of the lighting command may be delayed, causing a delay in reflecting the brightness on the effect lighting device 204. For example, if the switching of the lighting pattern of the effect lighting device 204 is delayed compared to the switching of the image pattern displayed on the effect display unit 200a or the music pattern output to the music output device 206, the player may feel uncomfortable.

[0081] As described above, the performance execution means 334 performs the current analysis based on the results of the previous analysis, and cannot derive the current analysis result unless the previous analysis result (brightness generation information) is retained. However, if it is only necessary to identify the brightness of the performance lighting device 204, it is possible to do so by simply analyzing the table assigned to the layer with the highest priority. Therefore, the performance execution means 334 first analyzes the table assigned to the layer with the highest priority, identifies the brightness of the performance lighting device 204, and quickly transmits a lighting command. Meanwhile, the analysis process for the tables assigned to the remaining layers is performed after the lighting command transmission settings have been completed.

[0082] Fig. 10 is a timing chart showing another example of processing by the effect execution means 334. Here, an example of processing by the effect execution means 334 at any time T3 (for example, 1.5 seconds after time T0) between time T0 and time T1 in Fig. 8 will be described. This processing is also performed at a predetermined interruption period (for example, 33 msec) as in Fig. 9, and is completed within the interruption period.

[0083] At time T3, first, the performance execution means 334 identifies the layer to be analyzed first based on the priority of each layer. Specifically, the performance execution means 334 determines whether tables are effectively assigned to layers in descending order of priority, and identifies the layer with the highest priority (here, layer 1) among the layers to which tables are effectively assigned (for example, layer 1, layer 2).

[0084] Then, the performance execution means 334 analyzes layer 1, which has been determined to have a high priority, and references the brightness generation information of layer 1 to identify table 1 from the table identifier in the brightness generation information. Furthermore, based on the fact that the command to be analyzed is the command "SLINE," the performance execution means 334 adds the previous brightness value of "15" to the brightness change value of "0.36" to identify the current brightness value of "15.36." Furthermore, for the next analysis, the performance execution means 334 overwrites the previous brightness value in the brightness generation information of layer 1 with the current brightness value of "15.36."

[0085] Next, the performance execution means 334 transmits the brightness (for example, the previous brightness value "15.36") specified based on Table 1 assigned to that layer 1 to the controller 342 as a lighting command. Specifically, as shown in Fig. 10, the performance execution means 334 sets the DMA controller to send the lighting command, and then the DMA controller sends the lighting command to the controller 342 independently of the performance execution means 334. In this way, the performance execution means 334 shifts the actual sending process of the lighting command to the DMA controller that can operate independently of itself, thereby enabling it to immediately thereafter execute other processes, for example, processes for other layers.

[0086] Then, after the transmission process is shifted to the DMA controller, the performance execution means 334 sets layer 2 as the analysis target, references the brightness generation information of layer 2, and identifies table 2 from the table identifier in the brightness generation information. Furthermore, based on the fact that the command to be analyzed is the command "WAIT," the performance execution means 334 identifies the current brightness value "31" by using the previous brightness value "31" as is. Furthermore, for the next analysis, the performance execution means 334 overwrites the previous brightness value in the brightness generation information of layer 2 with the current brightness value "31."

[0087] In this way, even when multiple layers are provided, lighting commands can be sent appropriately and quickly based on the table assigned to the layer with the highest priority. Therefore, the lighting pattern of the effect lighting device 204 does not lag behind the image pattern displayed on the effect display unit 200a or the music pattern output to the music output device 206, and the player will not feel any discomfort.

[0088] Here, the tables assigned to layers other than the layer with the highest priority are analyzed after the lighting command is sent, but since all of this processing is performed in parallel within a specified interrupt period (e.g., 33 msec), the order in which the tables are analyzed does not affect the timing of brightness emission.

[0089] Furthermore, even when the analysis process for the table assigned to layer 1 is completed at time T1 in FIG. 10, the layer with the highest priority among the layers to which a table is validly assigned, in this case layer 2, is analyzed as the top priority, and therefore, as at time T3, a lighting command is sent appropriately and promptly.

[0090] For convenience of explanation, two layers (layer 1 and layer 2) are given here, and an example is given in which the layer with the highest priority (e.g., layer 1) is analyzed first, and the layer with the next highest priority (e.g., layer 2) is analyzed after the lighting command transmission setting. However, this is not limited to this case. If there are three or more layers, the layer with the highest priority among the three or more layers may be analyzed first, and the other layers may be analyzed in any order after the lighting command transmission setting. This is because lighting effect device 204 can output only one brightness, and as long as the brightness of the layer with the highest priority can be transmitted, the order of analysis of the other layers does not affect the control of lighting effect device 204.

[0091] Also, for convenience of explanation, an example has been described in which, for one lighting effect device 204, the analysis of the layer with the highest priority (e.g., layer 1) is performed first, and the analysis of the layer with the next highest priority (e.g., layer 2) is performed after the lighting command transmission setting. However, this is not limited to such a case. When lighting patterns are determined for each of a plurality of lighting effect devices 204 at once, the analysis of the layer with the highest priority for each of the plurality of lighting effect devices 204 may be performed first, the identified brightness may be transmitted, and then analysis of layers other than the layer with the highest priority for each of the plurality of lighting effect devices 204 may be performed.

[0092] In this way, the gaming machine 100 comprises a performance determination means 332 that determines a command module (e.g., a table) that indicates a lighting pattern, a performance execution means 334 that updates the lighting mode (e.g., brightness generation information) corresponding to the command module based on the command module, and a performance lighting device 204 that emits light based on the updated lighting mode (using the brightness of the brightness generation information), and a priority is assigned to the command modules.When there are multiple command modules to be processed in parallel, the performance execution means 334 updates the lighting mode corresponding to the command module with the highest priority, transmits the updated lighting mode based on the command module with the highest priority to the performance lighting device, and updates the lighting modes corresponding to command modules other than the command module with the highest priority among the multiple command modules to be processed in parallel.

[0093] Here, the command module has been described as a table, which is a group of commands that indicate lighting patterns, but this is not limited to this case. Anything that can represent the time-series changes in the lighting state of the lighting performance device 204 can be used, for example, a program written in a programming language, or a list that lists combinations of execution time and lighting state.

[0094] Also, here, luminance generation information has been described as an illumination mode. However, this is not limited to such a case. When analyzing the command module (table), it is sufficient to grasp the previous state, for example, which process of the command module was performed immediately before. Various information such as luminance values can be applied. Also, the state held according to the illumination mode is not limited to luminance and may be represented by two values of lighting "1" or extinguishing "0".

[0095] Also, here, an example has been described in which a hierarchical structure is provided for the illumination pattern of the effect lighting device 204, the analysis of the layer with the highest priority is performed first, and after reflecting the analysis result in the effect lighting device 204, the analysis of the layers other than the layer with the highest priority is performed. However, this is not limited to the illumination pattern of the effect lighting device 204 and can also be applied to the image pattern displayed on the effect display unit 200a and the prop pattern for driving the prop device 202.

[0096] <Control of RTC> As described above, when the sub-CPU 330a reads the current time, it transmits the address of the RTC 348 on the I2C communication line and receives data (time information) indicating the current time from the RTC 348. The RTC 348 is composed of an integrated circuit (electrical element) and can generate the time and date based on an arbitrary clock alone. Also, the RTC 348 has a power source independent of the power source of the sub-CPU 330a and can continue to update the time and date even when the power source of the sub-CPU 330a is cut off. Therefore, even if the time managed by the sub-CPU 330a is erased due to power-off, the sub-CPU 330a can read the time from the RTC 348 at power-on and perform processing using the current time.

[0097] For example, the sub-CPU 330a uses the current time acquired from the RTC 348, and when the current time reaches a predetermined time, it is possible to execute a predetermined effect (effect release). Also, the sub-CPU 330a uses the date of the current day, and when the date of the current day reaches a predetermined date, for example, the birthday of a character symbolizing the gaming machine 100, it is possible to execute a celebratory effect to celebrate this. Also, the sub-CPU 330a executes an effect corresponding to the season to which the current day belongs.

[0098] However, due to hardware malfunctions, the time recorded by the RTC 348 may differ from the actual time. The following explains the impact of such malfunctions.

[0099] FIG. 11 is an explanatory diagram showing a comparative example of communication between the sub-CPU 330a and the RTC 348. For ease of explanation, it is assumed here that the sub-CPU 330a acquires time information indicating the current time from the RTC 348 every four seconds (at a four-second cycle). Note that while the acquired time information is shown in hours, minutes, and seconds, this is not limiting and the acquired time information may be in units smaller than seconds, such as milliseconds or year, month, and day. Here, it is assumed that the RTC 348 has already been initialized, is showing the original time, and is being updated sequentially. Therefore, as shown in FIG. 11, the time (RTC update time) is incremented by one second according to the internal clock, starting from "11:23:45."

[0100] When a predetermined period (for example, 4 seconds) arrives, the sub-CPU 330a acquires time information from the RTC 348 via I2C communication. The sub-CPU 330a then executes processing according to the time indicated by the acquired time information. For example, suppose that the sub-CPU 330a acquires time information from the RTC 348 when the time in the RTC 348 is "11:23:47." The sub-CPU 330a executes a performance according to the time "11:23:47" indicated by the acquired time information.

[0101] Although the sub-CPU 330a has been described here as simply acquiring time information from the RTC 348 via I2C communication, specifically, to establish communication with the RTC 348, the sub-CPU 330a prohibits communication requests from other slave devices (i.e., prohibits communication with other slave devices) (communication lock), then transmits the address of the RTC 348 via I2C communication, receives data indicating the current time (time information) from the RTC 348, and after receiving the data, permits communication requests from other slave devices (communication unlock). The prohibition and permission of communication requests may be based on a communication permission flag. For example, when a communication request to one slave device is permitted while the sub-CPU 330a permits communication requests, the sub-CPU 330a turns on the communication permission flag. While the communication permission flag is on, the sub-CPU 330a prohibits communication requests from other slave devices. Once communication with the first slave device is complete, the sub-CPU 330a turns off the communication permission flag and permits communication requests from other slave devices.

[0102] Here, when the time in the RTC 348 is "11:23:49," suppose that a hardware malfunction, such as electromagnetic noise, affects the RAM or register that stores the time in the RTC 348. Here, suppose that this malfunction causes the time in the RTC 348 to change from "11:23:49" to "1:33:20." Therefore, the RTC 348 continues to increment by one second from the new time, "1:33:20." Then, after a predetermined period (e.g., four seconds) has elapsed, the sub-CPU 330a acquires time information from the RTC 348. Because four seconds have elapsed since the previous time, "11:23:47," the sub-CPU 330a should acquire the time, "11:23:51," but actually acquires the time, "1:33:22." In this case, the sub-CPU 330a executes a performance corresponding to the acquired time, "1:33:22."

[0103] For example, if the time is "11:23:51" and an effect that evokes daytime (such as a standby effect) is executed, an effect that evokes late night is executed in response to the time "1:33:22." In this case, the player will feel uncomfortable with the effect that does not match the current time.

[0104] The time on the RTC 348 is also used as a timestamp when an error occurs or when a setting change is made within the gaming machine 100. Therefore, if the time updated by the RTC 348 differs from the original time, for example, the time indicated by the error timestamp will differ from the actual time the error occurred. This can delay the detection of an error if the time does not meet the error detection criteria. Furthermore, because the time when the error occurred differs from the original time, it becomes difficult to properly reproduce the circumstances under which the error occurred, making it difficult to identify the cause of the error. Furthermore, if the time on the RTC 348 is changed through fraudulent activity, such as intentional application of strong electromagnetic waves to the RTC 348, the time when the fraudulent activity was committed will also change, which could delay detection or prevent sufficient collection of information related to the fraudulent activity. Furthermore, setting changes are typically made outside of pachinko parlor business hours. Even if a fraudulent setting change is made during pachinko parlor business hours, if the RTC 348 time indicates a time outside of business hours, the fact that the fraudulent setting change was made may be hidden.

[0105] Therefore, in parallel with updating the time in the RTC 348, the sub-CPU 330a also updates the time, and by making the two consistent, the time in the RTC 348 is maintained at an appropriate value.

[0106] 12 is an explanatory diagram showing an example of communication between the sub-CPU 330a and the RTC 348. As in FIG. 11, only the time (hour, minute, second) is shown here for the sake of convenience. Also, assume that the RTC 348 has already been initialized and is showing the original time, and that the time is being updated sequentially. Therefore, as shown in FIG. 12, the time is incremented by one second from "9:23:46" according to the internal clock.

[0107] The sub-CPU 330a acquires the time from the RTC 348 via I2C communication at any timing after power-on. The sub-CPU 330a then executes processing according to the acquired time. For example, suppose that the sub-CPU 330a acquires the time from the RTC 348 when the time in the RTC 348 is "9:23:47". The sub-CPU 330a executes a performance according to the acquired time "9:23:47".

[0108] The sub-CPU 330a further sets the acquired time "9:23:47" as the initial value, and then updates the time self-containedly, just like the RTC 348. However, unlike the RTC 348, the sub-CPU 330a can only update the time while the gaming machine 100 is powered on, and the time information is erased when the power is turned off. Even if the power is turned off, the time information can be fixedly stored in non-volatile RAM, but the time cannot be updated while the power is off. Therefore, when the power is turned on, the time displayed will be different from the actual time. Also, unlike the RTC 348, the sub-CPU 330a performs software timing. For example, the sub-CPU 330a counts the number of interrupts according to a predetermined interrupt period (e.g., 33 msec) and updates the time according to that value.

[0109] Here, assume that when the time in the RTC 348 is "11:23:49," a hardware malfunction, such as electromagnetic noise, affects the RAM or register that stores the time in the RTC 348. Here, assume that this malfunction changes the time in the RTC 348 from "11:23:49" to "1:33:20." The RTC 348 continues to increment by one second from the new time, "1:33:20." The sub-CPU 330a then acquires time information from the RTC 348 at a predetermined interval (e.g., every four seconds). Because four seconds have passed since the previous time, "11:23:47," the sub-CPU 330a should acquire the time "11:23:51" from the RTC 348, but it actually acquires the time "1:33:22."

[0110] However, in this embodiment, the sub-CPU 330a verifies the validity of the time acquired from the RTC 348. That is, the sub-CPU 330a compares the time it updates with the time acquired from the RTC 348. For example, when the sub-CPU 330a acquires the time "1:33:22" from the RTC 348, the sub-CPU 330a independently updates the time (CPU updated time) to "11:23:51." Therefore, the sub-CPU 330a can determine that the time it updates, "11:23:51," is different from the time "1:33:22" acquired from the RTC 348. In response, the sub-CPU 330a resets (corrects) the time it updates, "11:23:51," as the initial value of the RTC 348. The sub-CPU 330a then executes processing according to the time "11:23:51" that it has updated, rather than the time "1:33:22" acquired from the RTC 348.

[0111] Here, the sub-CPU 330a updates the time independently of the RTC 348. When the sub-CPU 330a acquires time information from the RTC 348, it compares the time indicated by the time information with the time it updates itself to determine whether it is valid. If the sub-CPU 330a determines that the time indicated by the time information acquired from the RTC 348 is valid (equal to the time it updates itself), it uses the time indicated by the time information acquired from the RTC 348. If the sub-CPU 330a determines that the time indicated by the time information acquired from the RTC 348 is invalid (different from the time it updates itself), it resets the time on the RTC 348 to the time it updates itself and executes processing using that time. This configuration makes it possible to maintain the time on the RTC 348 at an appropriate value.

[0112] Note that, here, if the time updated by the sub-CPU 330a differs from the time updated by the RTC 348, the time updated by the sub-CPU 330a is adopted as the correct value. This is because the RAM and registers of the sub-CPU 330a are designed to be more resistant to changes in the surrounding environment while powered on than the RTC 348, and are configured to be less susceptible to noise such as electromagnetic waves, for example.

[0113] Furthermore, the sub-CPU 330a uses, as the initial value of the time, the time indicated by the time information updated by the RTC 348 after power-on. This is because the sub-CPU 330a can only update the time while the gaming machine 100 is powered on, and once the power is turned off, the time held by the sub-CPU 330a becomes unreliable, and the most reliable time at that point is the time updated by the RTC 348.

[0114] Fig. 13 is a flowchart for explaining the operation of the sub-CPU 330a. Fig. 13(a) shows the initialization setting process when the gaming machine 100 is installed, and Fig. 13(b) shows the normal process after the gaming machine 100 is installed.

[0115] The time of the RTC 348 is initially set when the gaming machine 100 is shipped from the factory. When the gaming machine 100 is installed and powered on, the time of the RTC 348 is set to the initial value at the time of shipment, which may differ from the current time. Therefore, as shown in FIG. 13(a), the sub-CPU 330a determines whether or not a hall clerk or manager has input a time setting for the RTC 348 (S20), and waits for the input while there is no input (NO in S20). When a hall clerk or manager has input a time setting for the RTC 348 (YES in S20), the sub-CPU 330a sets the input time in the RTC 348 (S21).

[0116] Also, as shown in Figure 13(a), after setting the time of the RTC 348, when the gaming machine 100 is powered on, as shown in Figure 13(b), the sub-CPU 330a acquires time information from the RTC 348 (S30), and sets the time indicated by the acquired time information as the initial value of the time to be updated within the sub-CPU 330a (S31).

[0117] Then, the sub CPU 330a waits for the arrival of a predetermined interrupt period (e.g., 33.3 msec) (NO in S32), and when the predetermined interrupt period arrives (YES in S32), the sub CPU 330a acquires time information from the RTC 348 (S33). The sub CPU 330a also updates the time it manages in response to the arrival of the interrupt period (S34). For example, the sub CPU 330a increments a counter by 1 in response to the arrival of the interrupt period, and when it reaches 30 (1 second / 33 msec), it increments the time by 1 second and initializes the counter.

[0118] Next, the sub-CPU 330a compares the time indicated by the time information acquired from the RTC 348 with the time it has updated itself (S35). If the time indicated by the time information acquired from the RTC 348 and the time it has updated itself are equal (YES in S35), the sub-CPU 330a proceeds to step S37. If the time indicated by the time information acquired from the RTC 348 and the time it has updated itself are different (NO in S35), the sub-CPU 330a proceeds to step S36. If the time acquired from the RTC 348 and the time it has updated itself are different, the sub-CPU 330a determines that the time on the RTC 348 has become different from the original time due to some malfunction, and sets the time it has updated itself to the RTC 348 (S36). The sub-CPU 330a saves the time determined in this way in the sub-RAM 330b so that it can be referenced in other processes (S37).

[0119] With this configuration, even if a hardware malfunction causes the time on the RTC 348 to differ from the actual time, it is possible to maintain the time on the RTC 348 at an appropriate value. In this way, the sub-CPU 330a can execute effects that are synchronized with the appropriate time, and the player will not feel uncomfortable.

[0120] In addition, if an error occurs or a setting change is made within the gaming machine 100, the appropriate time is displayed as a timestamp, making it possible to properly identify the time and circumstances of the error or setting change.

[0121] Furthermore, while the power is on, the time updated by the sub-CPU 330a, which is more resistant to changes in the surrounding environment than the RTC 348, is used, and while the power is off, the RTC 348 updates the time, making it possible to properly refer to the original time regardless of whether the power is on or off.

[0122] In this way, the gaming machine 100 is equipped with a CPU (e.g., sub-CPU 330a) and an RTC (RTC element) 348, and the CPU acquires time information from the RTC 348 at a first timing (e.g., when the power is turned on, etc.), sets the time indicated by the time information acquired at the first timing as the initial value, then updates the time, acquires time information from the RTC 348 at a second timing after the first timing (e.g., when a predetermined period arrives, etc.), compares the first time, which is the time updated by the CPU, with the second time indicated by the time information acquired at the second timing, and if the first time and the second time are different, sets the RTC 348 to the first time.

[0123] Here, we have described an example in which time information is acquired from the RTC 348 at a second timing (e.g., at the arrival of a predetermined period), the sub-CPU 330a compares the first time, which is the time updated by the RTC 348, with the second time indicated by the time information acquired at the second timing, and if the first time and the second time differ, sets the RTC 348 to the first time. However, depending on the conditions, the RTC 348 may not be set to the first time. If a hardware malfunction occurs, the second time on the RTC 348 may change significantly. However, if the time difference between the first time and the second time is small, e.g., less than 3 seconds, it may not be due to a hardware malfunction but simply to an error in the time update. Therefore, the CPU (e.g., the sub-CPU 330a) may set the RTC 348 to the first time if the time difference between the first time and the second time is equal to or greater than a predetermined time difference (e.g., 3 seconds), and may not set the RTC 348 to the first time if the time difference between the first time and the second time is less than the predetermined time difference. Note that the RTC 348 is often more accurate than the sub-CPU 330a because it is specialized in updating the time. In this case, the second time is often more accurate than the first time. Therefore, here, if the first time and the second time are different and the time difference is less than a predetermined time difference (e.g., 3 seconds), the first time is not set in the RTC 348, but instead the second time is set in the sub-CPU 330a, thereby making it possible to maintain the time on the RTC 348 at an appropriate value. However, if the second time were to be set in the sub-CPU 330a whenever the time difference is less than the predetermined time difference, this could complicate the process. Therefore, if the first time and the second time are different and the time difference is equal to or greater than a specific time difference (e.g., 1 second) and less than a predetermined time difference (e.g., 3 seconds), the second time may be set in the sub CPU 330a, and if the time difference is less than the specific time difference, the second time may not be set in the sub CPU 330a (and the first time may not be set in the RTC 348).In this way, the process of setting the second time in the sub CPU 330a is not performed until the time difference between the first time and the second time becomes the specific time difference, which makes it possible to reduce the processing load.

[0124] <Amplifier control> Furthermore, when sub-CPU 330a instructs amplifier 206a on the volume of music data, it first transmits the address of amplifier 206a via I2C communication and then transmits volume information. Amplifier 206a amplifies the music data (music signal) input from music IC 346a according to the volume indicated by the volume information received from sub-CPU 330a, and outputs the amplified analog signal to speaker 206b.

[0125] Fig. 14 is a timing chart showing a comparative example of communication between the sub-CPU 330a and the amplifier 206a. In Fig. 14, transmitted information via I2C communication is surrounded by a solid line, and received information via I2C communication is surrounded by a dashed line.

[0126] When a volume setting instruction is received, the sub-CPU 330a, which is the master device, prohibits the acceptance of communication requests from other slave devices, i.e., prohibits communication with other slave devices (hereinafter simply referred to as locking communication), in order to establish communication with the amplifier 206a (specific slave device), which is a slave device, and transmits the address of the amplifier 206a, a Write request (indicated simply by "W" in FIG. 14), and volume information via I2C communication, as shown in FIG. 14. The amplifier 206a, which is the slave device, receives the volume information in response to its own address and the Write request. After transmitting the volume information, the sub-CPU 330a permits the acceptance of communication requests from other slave devices, i.e., permits communication with other slave devices (hereinafter simply referred to as unlocking communication). Note that the address includes a slave device address indicating the slave device with which communication is to be made, and a register address indicating the register in that slave device with which communication is to be made. For example, when transmitting volume information, the sub-CPU 330a specifies, as an address, a slave device address indicating the amplifier 206a and a register address (LSB=1b) indicating a storage location of the audio information. The volume information includes information indicating the volume that is normally transmitted, as well as information for setting or initializing the volume that is transmitted when power is turned on, when initialization is performed after an amplifier error occurs, or when the settings of the amplifier 206a are changed.

[0127] The sub-CPU 330a performs a cyclic redundancy check (hereinafter simply referred to as CRC) calculation on all transmitted data and generates a check result (hereinafter referred to as CRC result). The CRC result is the result of the CRC calculation and is a code that detects data errors. For example, the data transmitting side adds the remainder (e.g., 1 byte) obtained by dividing the data by a predetermined generating polynomial to the data as the CRC result and transmits it. The data receiving side also divides the data using the same generating polynomial, and the remainders, that is, the CRC results, are compared and collated to detect data errors and corruption.

[0128] When the CRC calculation is complete, the sub-CPU 330a locks communication again to establish communication with the amplifier 206a, and transmits the address of the amplifier 206a, a write request, and the CRC result (first error determination information) via I2C communication. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address (LSB=0b) indicating the storage destination of the CRC result. The amplifier 206a receives the CRC result in response to its own address and the write request. After transmitting the CRC result, the sub-CPU 330a unlocks communication.

[0129] In response to receiving the CRC result (storing the CRC result in the register indicated by the register address), the amplifier 206a generates a CRC result (second error detection information) for all the received data excluding the CRC result, compares the generated CRC result with the received CRC result to perform error detection, and stores the comparison result in memory within the amplifier 206a.

[0130] 15 is an explanatory diagram illustrating the process of generating a CRC result. The sub-CPU 330a calculates a CRC for all data transmitted to the amplifier 206a. Therefore, when the sub-CPU 330a completes transmission of the volume information and unlocks communication in FIG. 15, it calculates a CRC including the address and write request for transmitting the CRC result in addition to the address, write request, and volume information transmitted up to that point. Note that the address for transmitting the CRC result is predetermined, and therefore the sub-CPU 330a can grasp the address and write request when transmission of the volume information is completed, and can therefore calculate the CRC when transmission of the volume information is completed.

[0131] Meanwhile, the amplifier 206a also calculates a CRC for all received data. However, the amplifier 206a calculates a CRC for all data transmitted through I2C communication from the time it receives an address specifying itself as the communication destination in I2C communication until it receives a CRC result specifying itself as the communication destination. Therefore, as shown in FIG. 15, when the amplifier 206a receives a CRC result specifying itself as the communication destination, it calculates a CRC for all data received up to that point, excluding the CRC result, i.e., for data from the address specifying itself as the communication destination to the write request for transmitting the CRC result specifying itself as the communication destination. In this way, the amplifier 206a can compare its own calculated CRC result with the CRC result received from the sub-CPU 330a and determine whether there is an error. Note that the amplifier 206a sequentially calculates a CRC for the received data each time it receives data. In this way, the efficiency of CRC calculation can be improved.

[0132] Returning to FIG. 14, after a predetermined time has elapsed that is equal to or greater than the time it takes for the amplifier 206a to generate the CRC result, the sub-CPU 330a locks communication to establish communication with the amplifier 206a, sends the address of the amplifier 206a and a read request (indicated simply by "R" in FIG. 14) via I2C communication, receives the comparison result from the amplifier 206a, and unlocks communication after receiving the comparison result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address indicating the read destination of the comparison result. In this way, volume information is appropriately transmitted from the sub-CPU 330a to the amplifier 206a.

[0133] In this way, the sub-CPU 330a transmits volume information to the amplifier 206a via I2C communication. As described above, in such I2C communication, multiple slave devices can be connected to one master device (here, the sub-CPU 330a). For example, the RTC 348 is also connected as another slave device to the clock signal line and data signal line of the I2C communication to which the amplifier 206a is connected. In this case, the sub-CPU 330a does not accept communication with the RTC 348 while communication with the amplifier 206a is locked, but can communicate with the RTC 348 when communication with the amplifier 206a is unlocked. Therefore, the sub-CPU 330a may obtain time information from the RTC 348 between the transmission of the volume information and the CRC shown in FIG. 14. In this way, the following events may occur when communication with multiple slave devices is performed in parallel.

[0134] Fig. 16 is a timing chart showing a comparative example of communication between the sub-CPU 330a, the amplifier 206a, and the RTC 348. In Fig. 16, information transmitted via I2C communication is surrounded by a solid line, and information received via I2C communication is surrounded by a dashed line.

[0135] When a volume setting instruction is received, the sub-CPU 330a locks communication to establish communication with the amplifier 206a, and transmits the address of the amplifier 206a, a write request, and volume information via I2C communication. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address (LSB=1b) indicating the storage location of the volume information. The amplifier 206a receives the volume information in response to its own address and the write request. After transmitting the volume information, the sub-CPU 330a unlocks communication. In addition, the sub-CPU 330a calculates a CRC on the transmission data including the volume information and generates a CRC result.

[0136] However, when calculating the CRC, the sub-CPU 330a unlocks communication with the amplifier 206a and temporarily releases I2C communication to other slave devices. Let's assume that an instruction to acquire time information is received while I2C communication is released. In response to the instruction to acquire time information, the sub-CPU 330a locks communication to establish communication with the RTC 348 and transmits the address of the RTC 348 and a read request via I2C communication. The address here consists of a slave device address indicating the RTC 348 and a register address indicating the destination from which the time information is read. In response to its own address and the read request, the RTC 348 transmits time information indicating the time it is updating to the sub-CPU 330a. After receiving the time information, the sub-CPU 330a unlocks communication. In this way, the sub-CPU 330a acquires the time information and becomes aware of the current time.

[0137] When communication with the RTC 348 is unlocked and the calculation of the CRC result is completed, the sub-CPU 330a locks communication to establish communication with the amplifier 206a, transmits the address of the amplifier 206a and a write request via I2C communication, and transmits the CRC result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address (LSB=0b) indicating the storage destination of the CRC result. The amplifier 206a receives the CRC result in response to its own address and the write request. After transmitting the CRC result, the sub-CPU 330a unlocks communication.

[0138] As described above, in response to receiving the CRC result (storing the CRC result in the register indicated by the register address), the amplifier 206a generates a CRC result for all of the received data excluding the CRC result, compares the generated CRC result with the received CRC result to determine whether there is an error, and stores the comparison result in memory within the amplifier 206a.

[0139] 17 is an explanatory diagram for explaining the process of generating a CRC result. As in FIG. 15, the sub-CPU 330a calculates a CRC for all data transmitted to the amplifier 206a. Therefore, when the sub-CPU 330a completes transmission of the volume information and unlocks communication in FIG. 17, it calculates a CRC including the address and write request for transmitting the CRC result in addition to the address, write request, and volume information transmitted up to that point. Note that the address for transmitting the CRC result is predetermined, and therefore the sub-CPU 330a can grasp the address and write request when transmission of the volume information is completed, and can therefore calculate the CRC when transmission of the volume information is completed.

[0140] Meanwhile, the amplifier 206a also calculates a CRC for all received data. However, as described above, the amplifier 206a calculates a CRC for all data transmitted through I2C communication from the time it receives an address specifying itself as the communication destination in I2C communication until it receives a CRC result specifying itself as the communication destination. Therefore, as shown in FIG. 17, when the amplifier 206a receives the CRC result specifying itself as the communication destination, it calculates a CRC for all data received up to that point, excluding the CRC result, that is, for data from the address specifying itself as the communication destination to the Write request for transmitting the CRC result specifying itself as the communication destination. This means that the amplifier 206a calculates a CRC for data that does not specify itself as the communication destination, for example, communication data with the RTC 348 (address, Read request, time information). In this case, the CRC result generated by the sub-CPU 330a covers the address, write request, volume information, address, and write request, whereas the CRC result generated by the amplifier 206a covers the address, write request, volume information, address, read request, time information, address, and write request, which are different. Therefore, the amplifier 206a compares the CRC result it calculated with the CRC result received from the sub-CPU 330a, but the results are not consistent.

[0141] Returning to FIG. 16, after a predetermined time has elapsed that is equal to or greater than the time it took for the amplifier 206a to generate the CRC result, the sub-CPU 330a locks communication to establish communication with the amplifier 206a, transmits the address of the amplifier 206a and a read request via I2C communication, receives the comparison result from the amplifier 206a, and unlocks communication after receiving the comparison result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address indicating the read destination of the comparison result. However, as described above, since the CRC result generated by the sub-CPU 330a differs from the CRC result generated by the amplifier 206a, the amplifier 206a does not adopt the volume information, and the sub-CPU 330a also does not properly transmit the volume information.

[0142] Here, for example, because the amplifier 206a is configured to calculate the CRC for all data from when it receives an address that specifies itself as the communication destination in I2C communication until it receives a CRC result that specifies itself as the communication destination, that is, even for data that does not specify itself as the communication destination, the CRC result generated by the amplifier 206a will differ if communication with another slave device is performed before transmitting the CRC result. Therefore, in this embodiment, the sub-CPU 330a calculates the CRC and transmits the CRC result before unlocking communication when transmitting volume information, thereby preventing communication with another slave device from being performed between the transmission of the volume information and the transmission of the CRC result.

[0143] Fig. 18 is a timing chart showing an example of communication between the sub-CPU 330a, the amplifier 206a, and the RTC 348. In Fig. 18, information transmitted via I2C communication is surrounded by a solid line, and information received via I2C communication is surrounded by a dashed line.

[0144] When a volume setting instruction is received, the sub-CPU 330a locks communication to establish communication with the amplifier 206a and transmits the address of the amplifier 206a, a Write request, and volume information via I2C communication. The sub-CPU 330a transmits the volume information, calculates a CRC on the data including the volume information, and generates a CRC result (first error determination information). Note that, in order to transmit the volume information efficiently, the sub-CPU 330a sequentially generates volume information and, in parallel, sequentially transmits the generated volume information while sequentially calculating a CRC on the volume information. The sub-CPU 330a then transmits the calculated CRC result following the volume information. Here, to transmit the volume information and the CRC result at the same time, the address is configured with a slave device address indicating the amplifier 206a and a register address (LSB=0b) indicating the storage location of the volume information and the CRC result. The amplifier 206a, which is a slave device, receives the volume information in response to its own address and the Write request, and subsequently receives the CRC result. The sub CPU 330a unlocks the communication after transmitting the CRC result. In other words, the sub CPU 330a does not unlock the communication (leaves it locked) after transmitting the volume information, but unlocks the communication after transmitting the CRC result.

[0145] In response to receiving the CRC result (storing the volume information and the CRC result in the register indicated by the register address), the amplifier 206a generates a CRC result (second error detection information) for all the received data excluding the CRC result, compares the generated CRC result with the received CRC result to perform error detection, and stores the comparison result in memory within the amplifier 206a.

[0146] FIG. 19 is an explanatory diagram for explaining the process of generating a CRC result. The sub-CPU 330a calculates a CRC for all data transmitted to the amplifier 206a. Therefore, in FIG. 19, the sub-CPU 330a calculates a CRC for the addresses, write requests, and volume information transmitted up to that point, at the latest by the time transmission of the volume information is completed. The sub-CPU 330a does not transmit the CRC result independently of the volume information as in FIG. 16, but transmits the CRC result together with the volume information as shown in FIG. 18. In this way, the targets of the CRC calculation do not include the addresses and write requests for transmitting the CRC result as in FIG. 17. Therefore, the CRC calculation load on the sub-CPU 330a is reduced.

[0147] Meanwhile, the amplifier 206a also calculates a CRC for all received data. However, as described above, the amplifier 206a calculates a CRC for all data transmitted through I2C communication from the time it receives an address specifying itself as the communication destination in I2C communication until it receives a CRC result specifying itself as the communication destination. Therefore, as shown in FIG. 19, when the amplifier 206a receives the CRC result specifying itself as the communication destination, it calculates a CRC for all data received up to that point, excluding the CRC result, i.e., for data from the address specifying itself as the communication destination to the volume information. However, the sub-CPU 330a does not transmit the CRC result independently of the volume information as shown in FIG. 16, but transmits the CRC result together with the volume information as shown in FIG. 18. Therefore, in this case, from the time it receives an address specifying itself as the communication destination in I2C communication until it receives a CRC result specifying itself as the communication destination, information on communications with other slave devices is not included in the CRC calculation, as shown in FIG. 17. In this way, when the amplifier 206a compares the CRC result it has calculated with the CRC result received from the sub-CPU 330a, the two will match.

[0148] Returning to FIG. 18, after transmitting the CRC result, the sub-CPU 330a unlocks communication with the amplifier 206a and temporarily releases I2C communication to other slave devices. Let's assume that an instruction to acquire time information is received while the I2C communication is released. In response to the instruction to acquire time information, the sub-CPU 330a locks communication to establish communication with the RTC 348 and transmits the address of the RTC 348 and a read request via I2C communication. The address here consists of a slave device address indicating the RTC 348 and a register address indicating the destination from which the time information is read. The RTC 348 transmits the time information to the sub-CPU 330a in response to its own address and the read request. After receiving the time information, the sub-CPU 330a unlocks communication. In this way, the sub-CPU 330a acquires the time information and becomes aware of the current time.

[0149] When communication with the RTC 348 is unlocked and the calculation of the CRC result is completed, the sub-CPU 330a locks communication to establish communication with the amplifier 206a after a predetermined time has passed that is equal to or longer than the time it took for the amplifier 206a to generate the CRC result, sends the address of the amplifier 206a and a read request via I2C communication, receives the comparison result from the amplifier 206a, and unlocks communication after receiving the comparison result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address indicating the destination from which the comparison result is read.

[0150] Here, after transmitting the CRC result, the sub-CPU 330a establishes communication with the other slave device, the RTC 348, but all data to be used for the CRC calculation has already been transmitted to the amplifier 206a, and the amplifier 206a does not include information about communications with other slave devices in its CRC calculation from the time it receives an address specifying itself as the communication destination in I2C communication until it receives the CRC result specifying itself as the communication destination, as shown in Figure 17. Therefore, as shown in Figures 16 and 17, the CRC results do not differ between the sub-CPU 330a and the amplifier 206a, and an appropriate CRC result can be obtained.

[0151] Furthermore, in the comparative example of FIG. 16, the volume information and the CRC result are transmitted at different times, but in the example of FIG. 18, they are transmitted at the same time, so that the number of communications between the sub-CPU 330a and the amplifier 206a can be reduced, and the probability of communication with other slave devices being obstructed can be reduced.

[0152] Furthermore, by changing the timing, the address and write request that were previously required for both the volume information and the CRC result are now only required once for both the volume information and the CRC result, reducing the CRC calculation load on the sub-CPU 330a and the amplifier 206a and shortening the communication time. Therefore, when the power is turned on, for example, the sub-CPU 330a can start communication with another slave device, such as the RTC 348, and acquire time information early.

[0153] In the above example, the sub-CPU 330a does not immediately unlock (keeps locked) communication after transmitting volume information, but performs a CRC calculation and unlocks it after transmitting the CRC result. In such a case, it may be difficult in terms of processing power for the sub-CPU 330a to perform the CRC calculation in parallel while transmitting the volume information. In this case, the sub-CPU 330a calculates the CRC after transmitting the volume information and transmits the CRC result after the calculation. In other words, the I2C communication remains locked while the CRC is being calculated, so the sub-CPU 330a waits for the transmission of the CRC result. This wait state for the transmission of the CRC result can be resolved by using a DMA (Direct Memory Access) controller.

[0154] 20 is a timing chart illustrating the transmission mode of the sub-CPU 330a. The sub-CPU 330a generates volume information in response to a volume setting instruction. After generating the volume information, the sub-CPU 330a locks communication with the amplifier 206a and sets an address, a write request, and the volume information in the DMA controller. The DMA controller establishes communication with the amplifier 206a using the set address and write request, and transmits the volume information to the amplifier 206a.

[0155] After setting the address, write request, and volume information in the DMA controller, the sub-CPU 330a can execute processes other than the transmission process without being involved in the transmission process. Here, the sub-CPU 330a calculates a CRC for the address, write request, and volume information set in the DMA controller. After generating the CRC result, the sub-CPU 330a sets the generated CRC result in the DMA controller and unlocks communication with the amplifier 206a. The DMA controller transmits the set address and write request, as well as the CRC result, to the amplifier 206a.

[0156] Here, the sub-CPU 330a leaves communication with the amplifier 206a to the DMA controller, and generates the CRC result in parallel with the timing at which the DMA controller transmits data to the amplifier 206a. Therefore, the sub-CPU 330a has a small data transmission load, and depending on the CRC calculation, the processing load itself is also small, allowing it to quickly execute other processes. Note that, here, the sub-CPU 330a can immediately unlock communication after setting the CRC result in the DMA controller. This is because, once transmission data is set in the DMA controller, other transmission data will not interrupt the transmission information of the DMA controller until transmission of the transmission data is completed, and the amplifier 206a can properly receive the address, write request, volume information, and CRC result.

[0157] The timing and amount of communication between the sub-CPU 330a and the amplifier 206a are as follows: For example, the sub-CPU 330a transmits multiple bytes, e.g., 100 bytes, of volume information when the power is turned on, when initialization is performed after an amplifier error occurs, or when amplifier settings are changed (burst write). The sub-CPU 330a may also transmit one byte of volume information when the player adjusts the volume (single write).

[0158] In this way, the gaming machine 100 includes a master device (e.g., a sub-CPU 330a) and a plurality of slave devices (e.g., an amplifier 206a, an RTC 348, etc.) connected in parallel to the master device via one serial communication line (e.g., an I2C communication line). The master device establishes communication with a specific slave device (e.g., the amplifier 206a) among the plurality of slave devices, transmits specific information (e.g., an address, a write request, volume information) to the specific slave device, generates first error determination information (e.g., a CRC result) based on the specific information, transmits the first error determination information to the specific slave device, and executes the first error determination information. On the premise that the slave device generates second error determination information (e.g., CRC result) based on the data received through the serial communication line from the time it starts receiving specific information from the master device until it receives first error determination information from the master device, and compares the first error determination information with the second error determination information to make an error determination, the master device prohibits communication with other slave devices (communication lock) after establishing communication with the specific slave device, transmits the first error determination information following the specific information, and after transmitting the first error determination information, permits communication with other slave devices (communication unlock).

[0159] The gaming machine 100 also includes a master device (e.g., a sub-CPU 330a) and a plurality of slave devices (e.g., an amplifier 206a, an RTC 348, etc.) connected in parallel to the master device via one serial communication line (e.g., an I2C communication line), and the master device establishes communication with a specific slave device (e.g., the amplifier 206a) among the multiple slave devices, prohibits communication with the other slave devices (communication lock), transmits specific information (e.g., an address, a write request, volume information) to the specific slave device, generates error determination information based on the specific information, transmits the error determination information (e.g., a CRC result) to the specific slave device following the specific information, and after transmitting the error determination information, permits communication with the other slave devices (communication unlock).

[0160] While an I2C communication line is used as an example of a serial communication line, various communication standards that allow multiple devices to communicate serially with each other can be used. While the specific information used herein is a series of consecutive data items including an address, a write request, and volume information, any consecutive data items that may generate an error can be used. While the specific information used herein is a cyclic redundancy check (CRC) as a means for generating error detection information, various error detection methods, such as a parity code, a checksum, or a hash function, can also be used.

[0161] While the preferred embodiments of the present invention have been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such embodiments. It is clear that those skilled in the art can conceive of various modifications and alterations within the scope of the claims, and it is understood that such modifications and alterations also fall within the technical scope of the present invention.

[0162] For example, in the above-described embodiment, a pachinko machine was exemplified as a gaming machine, which includes a pattern determination means for determining one of a plurality of types of patterns including a jackpot pattern, a pattern display means for displaying the pattern on the pattern display unit when a predetermined variation time has elapsed since the pattern was determined, a big prize game execution means for executing a big prize game consisting of a plurality of rounds of play when the jackpot pattern is displayed on the pattern display unit, a game profit awarding means for awarding a predetermined game profit when a game ball that has entered a big prize opening enters a specific area during a predetermined specific round of play in the big prize game, and an effect execution means for executing an effect during the big prize game. However, this is not limited to such a case, and the present invention can also be applied to a slot machine that includes a winning role drawing means that determines one of a plurality of types of winning roles by drawing a winning role based on the operation of a start switch, a reel control means that controls the rotation of a plurality of rotating reels on which a plurality of types of symbols are respectively arranged in accordance with the operation of the start switch, and that controls the stop of each rotating reel corresponding to the operated stop switch based on the drawing result of the winning role drawing means in accordance with the operation of the stop switch corresponding to the rotating reel, and an effect control means that executes one of a plurality of types of effects. The slot machine 600 will be described in detail below.

[0163] (Mechanical configuration of slot machine 600) As shown in the external views of Figures 21 and 22, the slot machine 600 comprises a housing 602 which is a roughly rectangular box-shaped body, an upper front door 604 which is attached to the front opening of the housing 602 so as to be able to open and close by a rotatable connecting member, a lower front door 606 which is located below the upper front door 604 and which, like the upper front door 604, is attached to the front opening of the housing 602 so as to be able to open and close, and a receiving tray 608 which is located below the lower front door 606 and which stores medals paid out from a medal discharge port 608a.

[0164] An operation unit installation stand 622 is formed on the upper part of the front lower door 606, and on the operation unit installation stand 622, a medal insertion slot 624, a bet switch 626, a start switch 628, a stop switch 630, an effect switch 632, etc. are arranged.

[0165] The medal insertion unit 624, located to the right of the operation unit installation base 622, accepts medals inserted as game media through a medal insertion slot 624a and sends them to a medal selector (not shown) located on the back of the front lower door 606. The medal selector is equipped with a blocker (not shown) that guides medals inserted outside the medal insertion period or non-standard medals to a medal ejection slot 608a, and an inserted medal detection unit 624b that detects the passage of standard medals inserted within the insertion period. The medals guided to the medal ejection slot 608a are ejected into the receiving tray 608. If a player inserts more medals than the specified number required to start one game, the medals in excess of the specified number are electronically stored (hereinafter simply referred to as credits) within the slot machine 600, up to a predetermined number (e.g., 50). The above-mentioned one game will be described in detail later.

[0166] Here, the specified number of coins to be inserted is set to "3" or "2." If the number of medals required to play one game can be selected from multiple specified numbers of coins, the largest of the multiple specified numbers of coins to be inserted is called the maximum specified number of coins to be inserted, and the smallest is called the minimum specified number of coins to be inserted. If the specified number of coins to be inserted can be selected from 1 to 3, the maximum specified number of coins to be inserted is "3," and the minimum specified number of coins to be inserted is "1."

[0167] The bet switch 626 is a push-button switch that inserts (bet) a specified number of medals from among the credited medals. When the bet switch 626 is pressed when more than the specified number of medals have been credited, one game can be started and the number of credited medals is reduced by the specified number.

[0168] The start switch 628 located on the left side of the operation unit installation base 622 is composed of a lever that can detect tilting operation and detects the start operation of one game by the player. The start switch 628 can also be composed of a button switch that can detect pressing operation.

[0169] A colorless and transparent symbol display window 636 made of a glass plate, a transparent resin plate, or the like is provided in the approximate center of the lower part of the upper front door 604, and a reel unit 634 is provided in the cabinet 602 at a position corresponding to the symbol display window 636. The reel unit 634 has three rotating reels (a left reel 634a, a center reel 634b, and a right reel 634c) that are each equally divided into 21 areas and have a plurality of types of symbols arranged in each area, as shown in the reel symbol arrangement in FIG. 23 , and each reel is independently rotatable. A player can view the left reel 634a, the center reel 634b, and the right reel 634c through the symbol display window 636. When the start switch 628 is operated, the reel unit 634 starts rotating the left reel 634a, the center reel 634b, and the right reel 634c.

[0170] The stop switches 630 located in the center of the operation unit installation base 622 are button switches that are provided corresponding to the left reel 634a, center reel 634b, and right reel 634c, respectively, and can detect pressing operations by the player, and detect the player's stop operations to stop the left reel 634a, center reel 634b, and right reel 634c. Note that these three button switches in the stop switch 630 are specifically called stop button switches, and are referred to as stop button switch 630a, stop button switch 630b, and stop button switch 630c, from left to right, depending on their positions.

[0171] The effect switch 632 is composed of a push-button switch and a jog dial switch rotatably arranged around it, and detects the pressing and rotating operations of the player. The effect switch 632 is mainly used during the effect, and the effect mode can be changed depending on the player's operation.

[0172] A liquid crystal display unit 638 that displays various images associated with the performance is provided approximately in the center of the top of the front upper door 604. In addition, performance lamps 642, which are formed of, for example, high-intensity light-emitting diodes (LEDs), are provided on the top and left and right sides of the front upper door 604. In addition, a performance prop device 660, which is formed of a drive device, is provided between the pattern display window 636 and the operation unit installation base 622.

[0173] 22, speakers 640 for producing auditory effects such as sound effects and musical tones are provided on the left and right sides of liquid crystal display unit 638 on the back surface of upper front door 604 and on the left and right sides of the inside surface of lower front door 606. Furthermore, a medal payout device (medal hopper) 764 for paying out medals from medal discharge outlet 608a is provided below reel unit 634 within housing 602. Medal payout device 764 includes a medal storage unit 764a for storing medals, a payout control unit 764b for discharging medals stored in medal storage unit 764a from medal discharge outlet 608a, and a paid-out medal detection unit 764c for detecting medals discharged from medal discharge outlet 608a. Specifically, the payout control unit 764b is rotatably supported on the exterior of the main body of the payout control unit 764b and is equipped with a disk (not shown) having multiple medal insertion holes arranged circumferentially, into which medals dropped from the medal storage unit 764a are inserted one by one from above, and a disk motor (not shown) that rotates the disk.By rotating this disk, medals inserted in the medal insertion holes are ejected one by one to the outside through an extrusion mechanism, and the next medal is inserted sequentially into the medal insertion hole vacated by the ejection, thereby continuously ejecting medals one by one.

[0174] 21 and 22, reel backlights 644 (see FIG. 24) are provided inside each of the rotating reels 634a, 634b, 634c to individually and independently illuminate from the back the upper, middle, and lower symbols of each of the rotating reels 634a, 634b, 634c that correspond to the symbol display window 636 (which may be the target of an activated line that is the target of a payout) among the symbols on the left reel 634a, center reel 634b, and right reel 634c. Also, above-reel lights 646 are provided at the top of the back surface of the symbol display window 636 to directly illuminate the front of all of the left reel 634a, center reel 634b, and right reel 634c.

[0175] 21, in the operation unit installation base 622, a main credit display unit 652 and a main payout display unit 654 are provided on the approximately horizontal surface of a step 622a provided between the symbol display window 636 and the stop switch 630. In addition, a sub-credit display unit 656 and a sub-payout display unit 658 are provided between the symbol display window 636 and the operation unit installation base 622. The main credit display unit 652 and the sub-credit display unit 656 display the number of credits, and the main payout display unit 654 and the sub-payout display unit 658 display the number of medals to be paid out. The sub-credit display unit 656 and the sub-payout display unit 658 can also display various numerical values ​​associated with effects.

[0176] Furthermore, a power switch 648 is provided at an arbitrary position inside the cabinet 602. The power switch 648 is configured as a switch that can detect a pressing operation, such as a rocker switch, and is operated by an administrator who manages the slot machine 600 to switch between two states: a power-off state and a power-on state.

[0177] In this embodiment, the one game refers to the game from when a medal is inserted through the medal insertion section 624, when a credited medal is inserted through the operation of the bet switch 626, or when a medal is automatically inserted based on the display of a replay role on an active line, until the rotation of the multiple rotating reels 634a, 634b, 634c is controlled and a winning role is drawn in accordance with the operation of the start switch 628 by the player, and the rotating reels 634a, 634b, 634c corresponding to the operated stop button switches 630a, 630b, 630c are controlled to stop in accordance with the result of the winning role drawing and the operation of the multiple stop button switches 630a, 630b, 630c by the player, and if a winning role that allows for the payout of medals is achieved, the payout of medals is executed. In addition, if a winning combination that can receive a medal payout is not won, or if a winning combination is won but does not result in a prize, one game ends when all of the rotating reels 634a, 634b, and 634c have stopped. However, the start of one game may be interpreted as the player operating the start switch 628 instead of the insertion of a medal or the winning of a replay combination. In addition, the number of times one game is repeated is defined as the number of games.

[0178] (Electrical configuration of slot machine 600) FIG. 24 is a block diagram showing a schematic electrical configuration of the slot machine 600. As shown in FIG. 24, the slot machine 600 is primarily controlled by a control board. Here, as an example of a control board, a main control board 700 and a sub-control board 702, which share the functions of the control board, are described. For example, among programs related to the progress of a game, particularly important processes such as drawing winning combinations for the game and winning prizes are executed on the main control board 700, while other processes, such as those related to presentation, are executed on the sub-control board 702. Furthermore, as shown in FIG. 24, transmission of electrical signals between the main control board 700 and the sub-control board 702 is limited to one direction only, from the main control board 700 to the sub-control board 702, to prevent fraud, etc. However, if such restrictions were not present, bidirectional electrical communication would be technically possible.

[0179] (Main control board 700) The main control board 700 has various semiconductor integrated circuits including a main CPU 700a which is a central processing unit, a main ROM 700b which stores programs etc., a main RAM 700c which functions as a work area, etc., and controls the entire slot machine 600. However, a backup power supply (not shown) is connected to the main RAM 700c, so that even if the power is cut off, data is not erased and is maintained unless settings are changed and initialization processing of the main RAM 700c is executed.

[0180] The main control board 700 also has functional units such as an initialization means 800, a betting means 802, a winning combination lottery means 804, a reel control means 806, a judgment means 808, a payout control means 810, a state transition means 812, a command determination means 814, and a command transmission means 816, which function when the main CPU 700a cooperates with the main RAM 700c based on a program stored in the main ROM 700b.

[0181] The initialization means 800 executes initialization processing on the main control board 700. The betting means 802 bets medals to be used in games. Here, betting includes inserting credited medals through operation of the bet switch 626, inserting medals through the medal insertion unit 624, and automatically inserting medals based on the display of a replay role on an active line. The winning role drawing means 804 determines one of multiple types of winning roles, including small roles, replay roles, and bonus roles, or a losing role, by drawing a winning role based on the medal bet and operation of the start switch 628.

[0182] The reel control means 806 controls the rotation of the plurality of rotation reels 634a, 634b, 634c in response to the operation of the start switch 628, and controls the stop of the rotation reels 634a, 634b, 634c corresponding to the operated stop button switches 630a, 630b, 630c in response to the operation of the start switch 628. Furthermore, the reel control means 806 may extend the time from when the operation of the stop switch 630 in the previous game was enabled until when the operation of the stop switch 630 by the player is enabled to display the lottery result of the winning combination lottery (which was disabled upon completion of the operation of the stop switch 630 in the previous game) beyond a specified time, and may perform a reel effect (freeze effect) in which the rotation reels 634a, 634b, 634c are rotated in a variety of ways during that time. The reel effect can be achieved by not enabling any switch that should normally be enabled for a predetermined period of time, by suspending processing that should normally be executed for a predetermined period of time, or by not transmitting or receiving signals from any switch that should normally be transmitted or received for a predetermined period of time.

[0183] The determination means 808 determines whether or not a symbol combination corresponding to a winning role determined in the winning role lottery is displayed on an active line. Here, the display of a symbol combination corresponding to a winning role determined in the winning role lottery on an active line may be simply referred to as a win. The payout control means 810 pays out medals in the number corresponding to the winning role based on the display of a symbol combination corresponding to a winning role determined in the winning role lottery on an active line (a win). The state transition means 812 transitions the game state based on the winning of a bonus role or a win.

[0184] The command determination means 814 sequentially determines commands related to games in accordance with the operations of the betting means 802, the winning combination lottery means 804, the reel control means 806, the determination means 808, the payout control means 810, the state transition means 812, etc. The command transmission means 816 sequentially transmits the commands determined by the command determination means 814 to the sub-control board 702.

[0185] The main control board 700 receives various detection signals from the inserted medal detection unit 624b, the bet switch 626, the start switch 628, and the stop switch 630, and based on the received detection signals, the bet means 802, the winning combination lottery means 804, the reel control means 806, and the determination means 808 execute the various processes described above. Also connected to the main control board 700 are a main credit display unit 652 and a main payout display unit 654, and payout control means 810 controls the display of the number of medal credits and the number of medals paid out on both display units 652, 654.

[0186] A reel drive control unit 758 is also connected to the main control board 700. This reel drive control unit 758 drives a stepping motor 762 based on rotation start signals for each of the rotating reels 634 a, 634 b, and 634 c transmitted from the reel control means 806 in response to an operation signal from the start switch 628, and stops driving the stepping motor 762 based on stop signals for the left reel 634 a, center reel 634 b, and right reel 634 c transmitted from the reel control means 806 in response to an operation signal from the stop switch 630 and a detection signal from the rotation position detection circuit 760.

[0187] Furthermore, a medal payout device 764 is connected to the main control board 700. A detection signal from a payout medal detection unit 764c is input to the main control board 700, and payout control means 810 controls the discharge of medals from a payout control unit 764b while counting the number of medals paid out in accordance with the detection signal.

[0188] The main control board 700 is also provided with a random number generator 700d. The random number generator 700d sequentially increments a count value, loops (0 to 65535) within a predetermined total number (for example, 65536), and generates (acquires) a random number by extracting the count value at a predetermined time. The random number generated by the random number generator 700d of the main control board 700 (hereinafter referred to as a winning role lottery random number) is used to award a gaming benefit to a player, for example, when the winning role lottery means 804 executes a winning role lottery.

[0189] (Sub-control board 702) Similarly to the main control board 700, the sub-control board 702 has various semiconductor integrated circuits including a sub-CPU 702a which is a central processing unit, a sub-ROM 702b which stores programs and the like, and a sub-RAM 702c which functions as a work area, and controls, in particular, the effects based on commands from the main control board 700. Similarly to the main RAM 700c, the sub-RAM 702c is also connected to a backup power supply (not shown), so that data is not erased and is retained even if the power is cut off. Similarly to the main control board 700, the sub-control board 702 is also provided with a random number generator 702d, and the random numbers generated by the random number generator 702d (hereinafter referred to as effect lottery random numbers) are mainly used to determine the type of effect.

[0190] In addition, the sub-control board 702 has functional units such as an initialization determination means 830, a command receiving means 832, and a performance control means 834 that function when the sub-CPU 702a works in cooperation with the sub-RAM 702c based on a program stored in the sub-ROM 702b.

[0191] The initialization determination means 830 executes initialization processing on the sub-control board 702. The command receiving means 832 receives commands from other control boards, such as the main control board 700, and processes the commands. The effect control means 834 receives a detection signal from the effect switch 632 and determines the game effects to be performed by each device of the LCD display unit 638, the speaker 640, and the effect lamp 642 based on the winning combination command. Specifically, the effect control means 834 determines image data to be displayed on the LCD display unit 638 and illumination data for illumination effects using illumination devices such as the effect lamp 642, the reel backlight 644, the reel above-reel lights 646, the sub-credit display unit 656, and the sub-payout display unit 658, and also determines audio data constituting the sound to be output from the speaker 640. The effect control means 834 then executes the determined game effects.

[0192] The effects include those executed by the main control board 700, such as the reel effects described above, and those executed by the sub-control board 702. The effects executed by the sub-control board 702 are visual and audible representations provided as the game progresses through the LCD display unit 638, speaker 640, effect lamps 642, reel backlights 644, reel above-reel lights 646, sub-credit display unit 656, sub-payout display unit 658, etc., and can give the game a story-like quality or suggest the results of the winning combination lottery with more dynamic images. With such effects, for example, effects suggesting a bonus game win can be performed over multiple games, heightening the player's anticipation. Even if a player does not win any winning combination, the effects can create a sense of anticipation for a high payout, making it possible to keep the player entertained.

[0193] Here, the performance control means 834 functions as the performance determination means 332 and performance execution means 334 described above, and the performance lamp 642 functions as the performance lighting device 204. Also, the sub-CPU 702a functions as the sub-CPU 330a described above, and the speaker 640 functions as the speaker 206b described above. Also, although not described here, the sub-control board 702 includes an amplifier with the same function as the amplifier 206a described above, and an RTC with the same function as the RTC 348 described above. [Explanation of symbols]

[0194] 206 Music Output Device 206a Amplifier (slave device) 330a Sub-CPU (CPU, master device) 348 RTC (slave device)

Claims

1. A master device; a plurality of slave devices connected in parallel to the master device via a single serial communication line; Equipped with The master device Establishing communication with a specific slave device among the plurality of slave devices; Transmitting specific information to the specific slave device; generating first error determination information based on the specific information; Transmitting the first error determination information to the specific slave device; The specific slave device is generating second error determination information based on data received through the serial communication line from when reception of the specific information from the master device is started until when the first error determination information is received from the master device; A gaming machine that performs an error determination by comparing the first error determination information with the second error determination information, The master device After establishing communication with the specific slave device, prohibiting communication with other slave devices; Transmitting the first error determination information following the specific information; After transmitting the first error determination information, the gaming machine permits communication with the other slave device.

2. A master device; a plurality of slave devices connected in parallel to the master device via a single serial communication line; Equipped with The master device establishing communication with a specific slave device among the plurality of slave devices and prohibiting communication with other slave devices; Transmitting specific information to the specific slave device; generating error determination information based on the specific information; transmitting the error determination information to the specific slave device following the specific information; After transmitting the error determination information, the gaming machine permits communication with the other slave device.

Images