Gaming Machines

Abstract

To maintain RTC time to an appropriate value.SOLUTION: A game machine of the present invention incudes a CPU and an RTC element. The CPU acquires time information from the RTC element at a first timing, sets the time indicated by the time information acquired at the first timing as an initial value, then updates the time, acquires the time information from the RTC element at a second timing after the first timing, compares the first time which is the time updated by the CPU, with the second time indicated by the time information acquired at the second timing, and if the first time and the second time differ, sets the first time to the RTC element.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present invention relates to a gaming machine that determines by lottery whether or not to award a gaming advantage to a player. [Background technology]

[0002] In general, in a gaming machine (pachinko machine), a game ball is launched toward a game area in a game board by a player's handle operation, and a lottery for a special symbol is executed on the condition that the game ball that flows down the game area enters a start hole. Then, a special symbol is displayed variably on the special symbol display, and the special symbol determined by the lottery is displayed as a stop, thereby notifying the player of the lottery result. At this time, when a specific special symbol indicating a big win is displayed as a stop on the special symbol display, a big prize game that is more advantageous to the player than a normal game is started. In this big prize game, an attacker device opens and closes a predetermined number of times, allowing the game ball to enter the big prize hole, and the player can receive many prize balls.

[0003] Such gaming machines are equipped with a real-time clock (hereinafter referred to as RTC) that keeps track of the current time. In some gaming machines, the time is obtained from the RTC and effects are performed according to the time. In order to prevent data corruption when the RTC time is obtained in multiple time divisions, a technique has been disclosed in which, if the time currently obtained from the RTC is an earlier time than the time previously obtained from the RTC, the previously obtained time is used instead of the currently obtained time (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2014-042596 A Summary of the Invention [Problem to be solved by the invention]

[0005] In this way, even if the RTC time acquisition fails, the time on the RTC itself is not incorrect, so the CPU can temporarily substitute other values ​​such as the previous value. However, if the RTC time itself becomes out of sync due to some kind of hardware malfunction, there is no way to correct it to the correct time. Also, to correct the RTC time that has become out of sync, the substituted previous value can be set in the RTC, but there will be a difference in the cycle of the time reference, and the time cannot be corrected to the correct time.

[0006] In view of the above problems, the present invention has an object to provide a gaming machine capable of maintaining the RTC time at an appropriate value. [Means for solving the problem]

[0007] In order to solve the above problems, the gaming machine of the present invention is equipped with a CPU and an RTC element, and the CPU acquires time information from the RTC element at a first timing, sets the time indicated by the time information acquired at the first timing as an initial value, then updates the time, acquires time information from the RTC element at a second timing after the first timing, compares the first time, which is the time updated by the CPU, with the second time indicated by the time information acquired at the second timing, and if the first time and the second time differ, sets the RTC to the first time. The CPU may set the first time in the RTC element when the time difference between the first time and the second time is equal to or greater than a predetermined time difference, and may not set the first time in the RTC element when the time difference between the first time and the second time is less than the predetermined time difference. Effect of the Invention

[0008] According to the present invention, it is possible to keep the RTC time at an appropriate value. [Brief description of the drawings]

[0009] [Figure 1] 1 is an oblique view of the gaming machine showing the door in an open state. [Diagram 2] FIG. [Diagram 3] FIG. 2 is a block diagram of the gaming machine. [Figure 4] A block diagram for explaining the control modes of the performance display unit, performance prop device, performance lighting device, and music output device on the sub-control board. [Diagram 5] 13 is a flowchart showing a control mode in a sub-control board. [Figure 6] FIG. 13 is a diagram showing an example of commands used in the table. [Figure 7] FIG. 13 is a diagram illustrating an example of a table. [Figure 8] 1 is a timing chart for explaining a stacked structure. [Figure 9] 13 is a timing chart showing an example of processing by a performance execution means. [Figure 10] 13 is a timing chart showing another example of processing by the performance execution means. [Figure 11] FIG. 11 is an explanatory diagram showing a comparative example of a communication mode between a sub CPU and an RTC. [Figure 12] FIG. 2 is an explanatory diagram showing an example of a communication mode between a sub CPU and an RTC. [Figure 13] 13 is a flowchart for explaining the operation of a sub CPU. [Figure 14] 13 is a timing chart showing a comparative example of a communication mode between a sub CPU and an amplifier. [Figure 15] FIG. 11 is an explanatory diagram for explaining a process of generating a CRC result. [Figure 16] 11 is a timing chart showing a comparative example of communication between a sub CPU, an amplifier, and an RTC. [Figure 17] FIG. 11 is an explanatory diagram for explaining a process of generating a CRC result. [Figure 18] 4 is a timing chart showing an example of communication between a sub CPU, an amplifier, and an RTC. [Figure 19] FIG. 11 is an explanatory diagram for explaining a process of generating a CRC result. [Figure 20]11 is a timing chart for explaining a transmission mode of a sub CPU. [Figure 21] FIG. 1 is an external view for explaining a schematic mechanical configuration of a slot machine. [Figure 22] 1 is an external view of the slot machine with the front door open, illustrating the general mechanical configuration of the slot machine. FIG. [Diagram 23] FIG. 2 is a diagram showing the arrangement of symbols on the reels. [Figure 24] FIG. 2 is a block diagram showing a schematic electrical configuration of the slot machine. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. The dimensions, materials, and other specific values ​​shown in the embodiment are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In this specification and drawings, elements having substantially the same functions and configurations are given the same reference numerals to avoid repeated explanations, and elements not directly related to the present invention are not shown.

[0011] In order to facilitate understanding of the embodiments of the present invention, first, a brief description will be given of the mechanical and electrical configurations of the gaming machine, and then specific processing on each board will be described.

[0012] 1 is a perspective view of a gaming machine 100 of this embodiment, showing a state in which the door is open. As shown in the figure, the gaming machine 100 includes an outer frame 102 in which an enclosed space is formed by four sides assembled into a substantially rectangular shape, a middle frame 104 attached to the outer frame 102 by a hinge mechanism so as to be freely opened and closed, and a front frame 106 attached to the middle frame 104 by a hinge mechanism so as to be freely opened and closed.

[0013] The middle frame 104, like the outer frame 102, has four sides arranged in a substantially rectangular shape to form an enclosed space, and a game board 108 is held in this enclosed space. A glass or resin transparent plate 110 is held in the front frame 106. When the middle frame 104 and the front frame 106 are closed against the outer frame 102, the game board 108 and the transparent plate 110 face each other substantially parallel to each other while maintaining a predetermined distance therebetween, and the game board 108 can be seen from the front side of the gaming machine 100 through the transparent plate 110.

[0014] 2 is a front view of the gaming machine 100. As shown in this figure, an operating handle 112 that protrudes from the front side of the gaming machine 100 is provided at the bottom of the front frame 106. This operating handle 112 is provided so that it can be rotated by the player, and when the player rotates the operating handle 112 to perform a launch operation, a gaming ball is launched by a launch mechanism (not shown) with a strength according to the rotation angle of the operating handle 112. The gaming ball launched in this way rises between rails 114a and 114b provided on the game board 108 and is guided to a playing area 116.

[0015] The play area 116 is a space formed between the play board 108 and the transparent plate 110, and is an area in which the play balls can flow down or roll. The play board 108 is provided with a large number of nails and windmills, and the play balls guided to the play area 116 collide with the nails and windmills, causing them to flow down or roll in irregular directions.

[0016] The play area 116 includes a first play area 116a and a second play area 116b, which have different degrees of entry of game balls depending on the launch strength of the launch mechanism. The first play area 116a is located on the left side of the play area 116 as seen by a player facing the game machine 100, and the second play area 116b is located on the right side of the play area 116 as seen by a player facing the game machine 100. Since the rails 114a and 114b are on the left side of the play area 116, game balls launched by the launch mechanism with a launch strength less than a predetermined strength will enter the first play area 116a, and game balls launched with a launch strength equal to or greater than the predetermined strength will enter the second play area 116b.

[0017] In addition, the game area 116 is provided with a general winning hole 118, a first starting hole 120, and a second starting hole 122 through which game balls can enter, and when game balls enter the general winning hole 118, the first starting hole 120, and the second starting hole 122, a predetermined prize ball is paid out to the player. The number of prize balls may be any number greater than or equal to one, and the number of prize balls paid out from the general winning hole 118, the first starting hole 120, and the second starting hole 122 may be different or may be set to the same number of prize balls. In this case, it is also possible to set the number of prize balls paid out when a game ball enters the first starting hole 120 to be less than the number of prize balls paid out when a game ball enters the second starting hole 122.

[0018] In addition, a first starting area is provided in the first starting hole 120, and a second starting area is provided in the second starting hole 122. When a game ball enters the first starting hole 120 or the second starting hole 122 and enters the first starting area or the second starting area, a lottery is held to determine one of a plurality of special symbols provided in advance. Each special symbol is associated with various game benefits, such as whether or not a big role game advantageous to the player can be executed and what kind of game state the game state will be from then on. Therefore, when a game ball enters the first starting hole 120 or the second starting hole 122, the player will acquire a predetermined prize ball and at the same time, will acquire the opportunity to acquire the right to receive various game benefits.

[0019] In addition, the second starting hole 122 is provided with a movable piece 122b that can be opened and closed, and the ease of entry of the game ball into the second starting hole 122 changes depending on the state of the movable piece 122b. Specifically, when the movable piece 122b is in a closed state, the game ball cannot enter the second starting hole 122. In contrast, when the game ball passes through the entry area in the gate 124 provided in the game area 116, a lottery for a normal pattern is held, and if a winning lottery is won, the movable piece 122b is controlled to an open state for a predetermined time. In this way, when the movable piece 122b is in an open state, the movable piece 122b functions as a tray that guides the game ball to the second starting hole 122, making it easier for the game ball to enter the second starting hole 122. Here, it is stated that when the second starting hole 122 is in a closed state, it is not possible for a game ball to enter the second starting hole 122; however, it may be configured so that game balls can enter the second starting hole 122 at a certain frequency even when the second starting hole 122 is in a closed state.

[0020] Furthermore, the game area 116 is provided with a big prize opening 128 into which game balls can enter. An opening / closing door 128b is provided in the big prize opening 128 so that the opening / closing door 128b can be opened and closed, and normally, the opening / closing door 128b closes the big prize opening 128, making it impossible for game balls to enter the big prize opening 128. In contrast, when the big prize game described above is executed, the opening / closing door 128b is opened, making it possible for game balls to enter the big prize opening 128. Then, when a game ball enters the big prize opening 128, a predetermined prize ball is paid out to the player.

[0021] In addition, at the bottom of the game area 116, there is a discharge outlet 130 that discharges game balls that do not enter any of the general prize opening 118, the first start opening 120, the second start opening 122, or the large prize opening 128 from the game area 116 to the back side of the game board 108.

[0022] The gaming machine 100 is equipped with a performance display device 200 consisting of a liquid crystal display device, a performance prop device 202 consisting of a drive device, a performance lighting device 204 consisting of lamps that can be controlled to various lighting modes and emission colors, a music output device 206 consisting of a speaker, and a performance operation device 208 that accepts operations by the player, as performance devices that perform performance while the game is in progress.

[0023] The performance display device 200 is equipped with a performance display section 200a consisting of an image display section that displays an image, and this performance display section 200a is arranged in the approximate center of the game board 108 so as to be visible from the front side of the gaming machine 100. As shown in the figure, the performance display section 200a displays performance symbols 210a, 210b, and 210c in a variable manner, and a variable performance is executed in which the big role lottery result is notified to the player depending on the stop display mode of each of these performance symbols 210a, 210b, and 210c.

[0024] The performance role device 202 is disposed in front of the performance display section 200a, and moves and rotates in an area visible to the player, thereby giving the player a sense of expectation of a big win. For example, the rotating role 202a as the performance role device 202 in FIG. 2 rotates around an axis in the front-rear direction in conjunction with the rotation of a motor (a pulse motor or a geared motor) as a driving source during the variable display of the performance patterns 210a, 210b, and 210c. Also, the moving role 202b as the performance role device 202 in FIG. 2 is usually evacuated to an evacuation area in the game board 108, but moves to the front of the performance display section 200a during the variable display of the performance patterns 210a, 210b, and 210c.

[0025] The effect lighting device 204 is composed of, for example, LEDs (Light Emitting Diodes) and is provided on the effect part device 202, the game board 108, etc., and is controlled to light in various ways according to the images displayed on the effect display section 200a.

[0026] The music output device 206 is provided at the upper position of the front frame 106 or at the lowermost position of the outer frame 102, and outputs various pieces of music toward the front side of the gaming machine 100 in accordance with the images displayed on the performance display section 200a.

[0027] The effect operation device 208 is composed of a button that accepts a pressing operation by the player and a rotation operation part (for example, a jog dial) that accepts a rotation operation by the player, and is provided at a position approximately at the center in the width direction of the gaming machine 100 and below the transparent plate 110. This effect operation device 208 is enabled according to the image displayed on the effect display part 200a, and when the operation of the player is accepted within the operation valid period, various effects are executed according to the operation.

[0028] Behind the performance operation device 208, there is an upper tray 132 to which prize balls paid out from the gaming machine 100 and game balls lent from the game ball lending device are guided, and when this upper tray 132 is full of game balls, the game balls are guided to the lower tray 134. Also, a ball ejection hole (not shown) for ejecting game balls from the lower tray 134 is formed on the bottom surface of the lower tray 134. This ball ejection hole is usually closed by an opening and closing plate (not shown), but by sliding the ball ejection knob 134a in the left-right direction in the figure, the opening and closing plate slides together with the ball ejection knob 134a, making it possible to eject game balls from the ball ejection hole to the bottom of the lower tray 134.

[0029] In addition, on the game board 108, a first special symbol display 160, a second special symbol display 162, a first special symbol reserved display 164, a second special symbol reserved display 166, a normal symbol display 168, a normal symbol reserved display 170, and a right hit notification display 172 are provided outside the game area 116 and at positions visible to the player. Each of these displays 160 to 172 is a device for displaying various situations related to the game.

[0030] (Internal configuration of control means) 3 is a block diagram showing the internal configuration of the control means for controlling the progress of the game. The main control board 300 controls the basic operations of the game. This main control board 300 is equipped with a main CPU 300a, a main ROM 300b, and a main RAM 300c. The main CPU 300a reads out a program stored in the main ROM 300b based on input signals from each detection switch and timer, performs arithmetic processing, and directly controls each device and display, or transmits commands to other boards according to the results of the arithmetic processing. The main RAM 300c functions as a work area for data during the arithmetic processing of the main CPU 300a.

[0031] The main control board 300 is connected to a general prize opening detection switch 118s which detects when a game ball has entered the general prize opening 118, a first start opening detection switch 120s which detects when a game ball has entered the first start opening 120, a second start opening detection switch 122s which detects when a game ball has entered the second start opening 122, a gate detection switch 124s which detects when a game ball has passed through the gate 124, and a special prize opening detection switch 128s which detects when a game ball has entered the special prize opening 128, and detection signals are input from each of these detection switches to the main control board 300.

[0032] In addition, the main control board 300 is connected to a normal electric role solenoid 122c that operates the movable piece 122b of the second starting opening 122, and a large prize opening solenoid 128c that operates the opening and closing door 128b that opens and closes the large prize opening 128, so that the opening and closing of the second starting opening 122 and the large prize opening 128 is controlled by the main control board 300.

[0033] Furthermore, the first special pattern display device 160, the second special pattern display device 162, the first special pattern reserved indicator device 164, the second special pattern reserved indicator device 166, the normal pattern display device 168, the normal pattern reserved indicator device 170, and the right hit notification indicator device 172 are connected to the main control board 300, and the display of each of these indicators is controlled by the main control board 300.

[0034] The gaming machine 100 of this embodiment is broadly divided into a special game that is started by a game ball entering the first start hole 120 or the second start hole 122, and a normal game that is started by a game ball passing through the gate 124. The main ROM 300b of the main control board 300 stores various programs for proceeding with the special game and the normal game, as well as data and tables required for various games.

[0035] In addition, a dispensing control board 310 and a sub-control board 330 are connected to the main control board 300.

[0036] The payout control board 310 performs control for launching game balls and control for paying out prize balls. This payout control board 310 also has a CPU, ROM, and RAM, and is connected to the main control board 300 so as to be able to communicate bidirectionally. This payout control board 310 is connected to a game information output terminal board 312, and various information on the progress of the game output from the main control board 300 is output to a hall computer or the like of the game parlor (hall) via the payout control board 310 and the game information output terminal board 312.

[0037] A payout motor 314 is connected to the payout control board 310 to pay out the game balls stored in the storage section to the player as prize balls. The payout control board 310 controls the payout motor 314 based on a payout number designation command sent from the main control board 300 to control the payout motor 314 to pay out a predetermined number of prize balls to the player. At this time, the number of paid out game balls is detected by a payout ball count switch 316s, and it is possible to know whether the prize balls to be paid out have been paid out to the player.

[0038] In addition, a tray full detection switch 318s that detects the full state of the lower tray 134 is connected to the payout control board 310. This tray full detection switch 318s is provided in a passage that leads the game balls paid out as prize balls to the lower tray 134, and a game ball detection signal is input to the payout control board 310 every time a game ball passes through the passage.

[0039] Then, when a predetermined amount or more of game balls are stored in the lower tray 134 and the tray is in a full state, game balls are retained in the passage leading to the lower tray 134, and game ball detection signals are continuously input from the tray full detection switch 318s to the payout control board 310. When the payout control board 310 receives the game ball detection signals continuously for a predetermined time, it determines that the lower tray 134 is in a full state, and transmits a tray full command to the main control board 300. On the other hand, when the continuous input of the game ball detection signals is interrupted after transmitting the tray full command, it determines that the full state has been released, and transmits a tray full release command to the main control board 300.

[0040] The payout control board 310 is also provided with a launch control circuit 320 that controls the launch of game balls. The payout control board 310 is connected to a touch sensor 112s that is provided on the operation handle 112 and detects the touch of the operation handle 112 by a player, and an operation volume 112a that detects the operation angle of the operation handle 112. When signals are input from the touch sensor 112s and the operation volume 112a, the launch control circuit 320 controls the energization of a launch solenoid 112c provided on the game ball launching device to launch the game balls.

[0041] The sub-control board 330 mainly controls each presentation during play, standby, etc. The sub-control board 330 includes a sub-CPU 330a, a sub-ROM 330b, and a sub-RAM 330c, and is connected to the main control board 300 so as to be able to communicate in one direction from the main control board 300 to the sub-control board 330 in order to prevent fraud. The sub-CPU 330a reads out a program stored in the sub-ROM 330b and performs arithmetic processing based on commands sent from the main control board 300 and input signals from a timer, and also controls the execution of presentations. At this time, the sub-RAM 330c functions as a work area for data during arithmetic processing by the sub-CPU 330a.

[0042] Specifically, the sub-control board 330 performs image display control to display images on the performance display unit 200a. A large amount of image data such as patterns and backgrounds to be displayed on the performance display unit 200a is stored in the sub-ROM 330b, and the sub-CPU 330a reads the image data from the sub-ROM 330b to a VRAM (not shown) to control the image display on the performance display unit 200a. The sub-control board 330 also performs drive control of the performance prop device 202, lighting control of the performance lighting device 204, and music output control to output music from the music output device 206.

[0043] FIG. 4 is a block diagram for explaining the control mode of the performance display unit 200a, the performance props device 202, the performance lighting device 204, and the music output device 206 in the sub-control board 330, and FIG. 5 is a flowchart showing the control mode common to them. The sub-CPU (CPU) 330a provided in the sub-control board 330 functions as a performance determination means 332 and a performance execution means 334 in cooperation with the program stored in the sub-ROM 330b and the sub-RAM 330c. The performance determination means 332 performs state management, analyzes the command transmitted from the main control board 300, and determines the performance pattern (contents showing a series of performance flows) such as a variable performance corresponding to the command, and generates a message for each device (the performance display unit 200a, the performance props device 202, the performance lighting device 204, and the music output device 206) and adds it to the operation buffer. Here, the message indicates the output timing to the device and the operation pattern of each device. Then, the performance execution means 334 analyzes each message stored in the operation buffer, and transmits commands to each device such as the image IC 340a, the controller 342, the music IC 346a, etc., according to the output timing included in the message. Both the performance determination means 332 and the performance execution means 334 are processes corresponding to interrupts (interrupt processes), and are executed at the interrupt timing associated with each device.

[0044] For example, as shown in FIG. 5, the effect determination means 332 waits for the arrival of a predetermined interruption period (e.g., 33.3 msec) (NO in S10), and when the predetermined interruption period arrives (YES in S10), it determines an image pattern based on the effect pattern (contents corresponding to the image to be displayed on the effect display unit 200a among the effects indicated by the effect pattern) (S11). Then, the effect determination means 332 transmits the determined image pattern and its output timing as a message to the operation buffer (S12). The effect execution means 334 generates an image command capable of identifying image data based on the image pattern stored in the operation buffer (S13). The effect execution means 334 transmits the image command to the image IC 340a (S14), and repeats the process from step S10. The image IC 340a is also called a VDP (Video Display Processor), and reads image data identified by the image command from the image ROM 340b to the image RAM (VRAM) 340c, and outputs the image data sequentially to the effect display unit 200a. In addition, some image is always displayed on the performance display unit 200a. Therefore, the performance determination means 332 always determines image data for each interrupt period. In addition, the image RAM 340c has different layers, and each layer can hold different image data. Then, the image IC 340a superimposes the image data held in the multiple layers, and the superimposed image data is output to the performance display unit 200a. In addition, the image IC 340a, the image ROM 340b, and the image RAM 340c are shown here as separate entities, but any two or all of the devices may be configured integrally, and any two or all of the devices may be configured integrally with the sub-CPU 330a.

[0045] In addition, in parallel with the control of the image IC 340a, the performance determination means 332 determines a reel pattern (contents indicating a series of operations of the performance reel device 202 among the performances indicated by the performance pattern) based on the performance pattern when a predetermined interrupt period (for example, 2 msec) arrives (YES in S10) in accordance with the determination of the performance pattern (S11). Then, the performance determination means 332 transmits the determined reel pattern and its output timing as a message to the operation buffer (S12). The performance execution means 334 generates a reel command indicating at least one of the proceeding direction (rotation direction), proceeding amount (rotation amount), and proceeding speed (rotation speed) based on the reel pattern stored in the operation buffer (S13). The performance execution means 334 transmits the reel command to the controller 342 at a predetermined time interval according to the reel pattern (S14), and repeats the process from step S10. The controller 342 drives the performance reel device 202 according to the reel command. Here, the performance prop device 202 operates only when the prop pattern is determined.

[0046] In addition, when a predetermined interruption period (e.g., 33 msec) arrives (YES in S10) in accordance with the determination of the performance pattern, the performance determination means 332 determines a lighting pattern based on the performance pattern (contents indicating a series of lighting modes (light emission modes) of the performance lighting device 204 among the performances indicated by the performance pattern) (S11). Then, the performance determination means 332 transmits the determined lighting pattern and its output timing as a message to the operation buffer (S12). The performance execution means 334 generates a lighting command indicating the lighting mode (e.g., whether or not to light and brightness) of the performance lighting device 204 based on the message (lighting pattern) stored in the operation buffer (S13). The performance execution means 334 transmits a lighting command to the controller 342 at a predetermined time interval according to the lighting pattern, similar to the role pattern (S14), and repeats the process from step S10. The controller 342 causes the performance lighting device 204 to emit light according to the lighting command. In this way, the lamp, which is the performance lighting device 204, is controlled to light up. It should be noted that the effect lighting device 204 is constantly repeating turning on and off. Therefore, the effect determination means 332 is constantly determining the effect pattern for each interruption period.

[0047] In addition, in parallel with the control of the image IC 340a and the controller 342, when a predetermined interrupt period (for example, 50 msec) arrives (YES in S10) in accordance with the determination of the effect pattern, the effect determination means 332 determines a music pattern (contents corresponding to the music to be output to the music output device 206 among the effects indicated by the effect pattern) based on the effect pattern (S11). Then, the effect determination means 332 transmits the determined music pattern and its output timing as a message to the operation buffer (S12). The effect execution means 334 generates a music command capable of identifying music data based on the music pattern stored in the operation buffer (S13). The effect execution means 334 transmits the music command to the music IC 346a (S14) and repeats the process from step S10. The music IC 346a reads the music data identified by the music command from the music ROM 346b to the music IC 346a, and sequentially outputs the music data to the music output device 206. Although the music IC 346a and music ROM 346b are shown here as separate entities, they may be configured as an integrated unit, or they may be configured as an integrated unit with the sub-CPU 330a.

[0048] The music output device 206 includes an amplifier 206a and a speaker 206b. The amplifier 206a amplifies music data (music signal) input from the music IC 346a and outputs an analog signal. The speaker 206b generates physical vibrations from the amplified analog signal and outputs sound (music). The sub-CPU 330a can also send commands to the amplifier 206a via I2C (Inter-Integrated Circuit) communication to control the amount of amplification of the amplifier 206a, that is, the volume of the sound output from the speaker 206b. Some kind of music is always being output from the music output device 206. Therefore, the performance determination means 332 always determines music data for each interruption period. The music IC 346a has multiple music buffers (buffers), and each music buffer can hold different music data. Then, the music IC 346 a superimposes the music data held in the multiple music buffers, and the superimposed music data is output to the music output device 206 .

[0049] Here, the I2C communication used for controlling the volume of the amplifier 206a of the music output device 206 is a short-distance serial communication line in which one master device (here, the sub-CPU 330a) and multiple slave devices (for example, the amplifier 206a, etc.) are connected in parallel (party line connection, star connection) by two lines, a clock signal line and a data signal line. Here, the parallel connection indicates a connection in which the master device and each of the multiple slave devices are connected to an I2C communication line, which is one serial communication line, and the master device can directly communicate with each of the multiple slave devices. In I2C communication, the master device always has control of the communication. Specifically, first, the master device outputs data in the order of Start Condition, address, and Read / Write request based on the clock, and only the slave device with a matching address can continue the subsequent transmission and reception. Then, when the master device outputs Stop Condition, the transmission and reception ends. During the period from Start Condition to Stop Condition, the master device communicates only with one slave device and does not accept communication requests with other slave devices (does not communicate). After completing communication with one slave device, the master device can communicate with another slave device.

[0050] 4, a plurality of slave devices, for example, an amplifier 206a and an RTC (Real Time Clock) 348, are connected to the clock signal line and data signal line of the I2C communication connected to the sub-CPU 330a. Here, when the sub-CPU 330a instructs the volume of music data, it transmits the address of the amplifier 206a and then transmits volume information indicating the volume to the amplifier 206a. When the sub-CPU 330a reads the current time, it transmits the address of the RTC 348 and receives time information indicating the current time from the RTC 348.

[0051] The RTC 348 is an integrated circuit (electrical element) that generates digital data such as time and date based on an arbitrary clock. The RTC 348 has a power supply independent of the power supply of the sub-CPU 330a, and can continue to update the time and date even if the power supply of the sub-CPU 330a is cut off. Therefore, the RTC 348 continues to measure time from the time set at initialization, and the sub-CPU 330a can use the measured time to perform other processes such as presentation.

[0052] Furthermore, detection signals are input to the sub-control board 330 from a press detection switch 208s that detects that the performance operation device 208 has been pressed, and a rotation detection switch 209s that detects that the performance operation device 208 has been rotated. When a detection signal is input from the performance operation device 208 (press detection switch 208s or rotation detection switch 209s), the controller 342 transmits that information to the performance determination means 332, and the performance determination means 332 determines various performances, such as displaying an image on the performance display unit 200a, in response to the input of the detection signal.

[0053] Here, a series of functional units such as sub-CPU 330a, sub-RAM 330c, image IC 340a, image ROM 340b, image RAM 340c, controller 342, music IC 346a, music ROM 346b, etc. are integrated into one integrated circuit as a SoC (System-on-a-Chip). However, which functional units are integrated into such an SoC can be set arbitrarily. Also, each functional unit such as sub-CPU 330a, sub-RAM 330c, image IC 340a, image ROM 340b, image RAM 340c, controller 342, music IC 346a, music ROM 346b, etc. may be integrated into a different integrated circuit and electrically connected.

[0054] A power supply board (not shown) is connected to each board, and power is supplied to each board from a commercial power source via the power supply board.

[0055] <Control of the lighting device 204> As described above, the performance determination means 332 determines a performance pattern, determines a lighting pattern based on the performance pattern, and transmits the determined lighting pattern to the operation buffer. Then, the performance execution means 334 generates lighting commands indicating the lighting modes of the performance lighting device 204 based on the messages stored in the operation buffer, and transmits the generated lighting commands to the controller 342. Here, a table that is a group of commands indicating the lighting patterns of the performance lighting device 204 is used as the message.

[0056] FIG. 6 is a diagram showing an example of commands used in a table. As shown in FIG. 6, the command "PUT" is a command to continue a set brightness for a set duration. The command "SETUP" is a command to emit light at a set brightness. The command "SLINE" is a command to change the brightness from the start brightness to the set brightness at equal intervals over a set duration. The command "WAIT" is a command to maintain a set brightness for a set duration. The command "LOOP" is a command to repeat the commands up to the command "NEXT" a set number of times. The command "NEXT" is a command indicating the end of the command "LOOP". The command "JUMP" is a command to jump the analysis destination to a specified address (table) and the analysis destination does not return to the original address. The command "CALL" is a command to jump the analysis destination to a specified address (table) and the analysis destination returns to the address next to the original address. Of the above commands, the command "PUT", command "SETUP", command "SLINE", command "WAIT", command "LOOP", and command "NEXT" consist of only a 2-byte basic command, while the command "JUMP" and command "CALL" consist of a 6-byte basic command and an extended command.

[0057] Fig. 7 is a diagram showing an example of a table. As shown in Fig. 7(a), the table is made up of 10 commands shown in 10 rows: command "LOOP", command "SLINE", command "SLINE", command "LOOP", command "SLINE", command "WAIT", command "SLINE", command "NEXT", command "NEXT", and command "END".

[0058] The table in FIG. 7(a) is operated by the performance execution means 334 according to the flowchart shown in FIG. 7(b). That is, the command "LOOP" (outside) on the first line repeatedly executes multiple commands surrounded by the command "NEXT" (outside) on the ninth line. In the command "SLINE", the final brightness is set in 5 bits (32 steps from "00h" to "1Fh"), and the duration is set in 6 bits (62 steps from "02h" to "3Fh", and if the interrupt period is 33.33 ms, 66.67 ms to 2010.00 ms). For example, the command "SLINE" on the second line linearly changes the brightness from the start (e.g., 0) to the final brightness (e.g., 31 (1FH)) over a duration of 2 seconds. The command "SLINE" on the third line linearly changes the brightness from the start (e.g., 31) to the final brightness (e.g., 0) over a duration of 2 seconds. The "LOOP" command (inside) on line 4 repeatedly executes multiple commands enclosed by the "NEXT" command (inside) on line 8. The "SLINE" command on line 5 linearly changes the brightness from the starting brightness (e.g. 0) to the final brightness (e.g. 31) over a period of 2 seconds. The "WAIT" command on line 6 maintains the starting brightness (e.g. 31) for a period of 1 second. The "SLINE" command on line 7 linearly changes the brightness from the starting brightness (e.g. 31) to the final brightness (e.g. 0) over a period of 2 seconds. When all repeated processes have been completed, the "END" command on line 10 ends processing of the table.

[0059] For example, if the lighting effect device 204 is made up of three-color (RGB) LEDs, a table is set for each of the three colors of LEDs. The lighting effect execution means 334 refers to each table from the operation buffer, analyzes each table, and specifies the lighting mode (e.g., brightness) to be emitted by the lighting effect device 204 to generate a lighting command.

[0060] For example, the performance execution means 334 analyzes the table at every predetermined interruption period (e.g., 33 msec), and identifies the brightness according to the execution time by referring to the command to be analyzed in the table and the execution time of the command (time elapsed from the start of execution). For example, the performance execution means 334 analyzes the table shown in Fig. 7(a), and if the command to be analyzed is the command "SLINE" in the second line which linearly changes the brightness from 0 to 31 over a duration of 2 seconds, and the execution time of the command "SLINE" is 1 second, the brightness becomes the intermediate value of 15. Also, if the command to be analyzed is the command "WAIT" in the sixth line which maintains the brightness at the start (e.g., 31) for a duration of 1 second, and the execution time of the command "WAIT" is 0.5 seconds, the brightness becomes 31.

[0061] In this way, the luminance in the illumination pattern changes from moment to moment according to the elapsed time. Therefore, the performance execution means 334 cannot specify the luminance unless it analyzes the table and recognizes the command to be analyzed and the execution time of the command. For this reason, the performance execution means 334 performs the current analysis based on the result of the previous analysis (luminance generation information), for example, the command to be analyzed and the execution time of the command. In other words, the performance execution means 334 cannot perform the current analysis unless the previous analysis result is held. In this way, in order to continuously specify the luminance corresponding to a specific table, the performance execution means 334 must analyze the table and derive the analysis result at each specific interruption period.

[0062] When the brightness is specified in this manner, the performance execution means 334 generates a lighting command by associating the identifier of the target performance lighting device 204 with the brightness, and transmits the generated lighting command to the controller 342. Note that, in reality, the performance execution means 334 transmits the lighting command to the controller 342 through a DMA (Direct Memory Access) controller. Therefore, after setting the DMA controller to transmit the lighting command, the performance execution means 334 can execute processes other than the transmission process without being involved in the transmission process.

[0063] In this embodiment, the effect determination means 332 may determine a plurality of effect patterns in parallel. For example, during a variable effect in which the result of the big role lottery is notified to the player based on the game ball entering the first start hole 120 or the second start hole 122, the player presses the effect operation device 208 and an effect is executed based on the operation. In this case, a plurality of effect patterns are determined in parallel, and a plurality of illumination patterns are also determined in parallel based on the effect patterns.

[0064] In order to manage multiple such illumination patterns in parallel, this embodiment employs a layered structure (hereinafter referred to as layers). The operation buffer has multiple different layers, and can associate tables and luminance generation information, which is the analysis result of the tables, on a layer-by-layer basis. Different tables can be assigned to different layers at the same time, but different tables cannot be assigned to the same layer in a layer-by-layer manner.

[0065] In addition, a priority is set for each layer, and when a table assigned to a layer with a high priority and a table assigned to a layer with a low priority are executed at the same timing, both are analyzed, but the analysis result of the table assigned to the layer with a high priority is used in preference to the analysis result of the table assigned to the layer with a low priority, and only the brightness specified by the table assigned to the layer with a high priority is transmitted to the controller 342 as a lighting command. Therefore, the player will visually recognize the performance lighting device 204 that emits light at the brightness specified by the table assigned to the layer with a high priority. In addition, since the priority of the table assigned to the layer is equal to the priority of the layer, it can be considered that the priority of the layer = the priority of the table assigned to the layer. Similarly, since analyzing a table assigned to a layer is synonymous with analyzing the layer, it can be considered that the analysis of the layer = the analysis of the table assigned to the layer.

[0066] Fig. 8 is a timing chart for explaining a stacked structure. For convenience of explanation, two layers are given in Fig. 8. However, the number of layers is not limited to two, and may be set to three or more. In Fig. 8, it is assumed that layer 1 has a higher priority than layer 2.

[0067] For example, it is assumed that the performance determination means 332 assigns, at time T0, to layer 1, table 1 consisting of a command "SLINE" that causes a linear change from brightness 0 to brightness 31 over a duration of 3 seconds, based on a predetermined lighting pattern 1. It is also assumed that the performance determination means 332 assigns, at the same time T0, to layer 2, table 2 consisting of a command "SETUP" that causes light to be emitted at brightness 31, and a command "WAIT" that maintains the initial brightness for a duration of 5 seconds, based on a predetermined lighting pattern 2 different from lighting pattern 1.

[0068] Then, from time T0 to time T1, which is three seconds after time T0, tables 1 and 2 are assigned to layers 1 and 2, respectively, and from time T1 to time T2, which is two seconds after time T1, table 2 is assigned to layer 2. In this case, the performance execution means 334 analyzes table 1 assigned to layer 1 and table 2 assigned to layer 2 from time T0 to time T1, which is three seconds after time T0, and uses the analysis result of table 1 assigned to layer 1 in preference to the analysis result of table 2 assigned to layer 2, and transmits only the luminance specified by table 1 assigned to layer 1 to the controller 342 as a lighting command. Also, from time T1 to time T2, which is two seconds after time T1, the performance execution means 334 analyzes table 2 assigned to layer 2, and transmits only the luminance specified by table 2 assigned to layer 2 to the controller 342 as a lighting command. In this way, the player visually recognizes the performance lighting device 204 in which the luminance gradually increases over three seconds and is maintained for two seconds.

[0069] Here, attention is paid to the processing of the performance execution means 334 from time T0 to time T1, which is 3 seconds later. Here, tables 1 and 2 are assigned to layers 1 and 2, respectively, and layer 1 is set to have a higher priority than layer 2. Then, if only the luminance specified by table 1 assigned to layer 1, which has a higher priority, is required, it may be thought that analyzing only table 1 assigned to layer 1 is sufficient. However, as described above, the performance execution means 334 cannot perform the current analysis unless the previous analysis result is held, and in order to continuously specify the luminance corresponding to a specific table, it must analyze the table and derive the analysis result at each predetermined interruption period. For example, in the example of FIG. 8, the analysis result of table 2 assigned to layer 2 is not reflected in the lighting command from time T0 to time T1, but must be reflected after time T1, and in order to obtain the analysis result, the performance execution means 334 must continue to analyze table 2 assigned to layer 2 from time T0 to time T1.

[0070] Specifically, the performance execution means 334 analyzes the table and stores the result as luminance generation information in association with the layer. The luminance generation information includes a table identifier (e.g., a table address), a command (or its address) to be analyzed, a command (or its address) when there is a repetition or call, the number of repetitions or calls, the execution time of the command to be analyzed (the elapsed time from the start of execution), the previous luminance value, a luminance change value, etc.

[0071] For example, the performance execution means 334 identifies that the command "SLINE" is being executed to linearly change the brightness from 0 to 31 over a duration of 3 seconds based on table 1 from time T0 to time T1, which is 3 seconds later, and adds the brightness change value (e.g., 0.36=32×33 msec / 3 seconds) as the brightness generation information to the previous brightness value (e.g., 15) as the brightness generation information until the execution time of the command "SLINE" reaches 3 seconds to identify the current brightness value (here, 15.36). Note that, for convenience of explanation, real numbers are used as the previous brightness value and the brightness change value, but in reality, they are multiplied by a constant and expressed as integers. At this time, the performance execution means 334 processes the current brightness value and then overwrites the current brightness value to the previous brightness value for the next analysis.

[0072] Furthermore, the performance execution means 334 grasps that the illumination pattern based on table 1 has ended at time T1, and determines that a command "WAIT" for maintaining the luminance at the start based on table 2 is being executed from time T1 until time T2, two seconds after time T1, and determines the current luminance value (here, 31) by using the previous luminance value (e.g., 31) as is until the execution time of the command "WAIT" reaches 5 seconds. At this time, after processing the current luminance value, the performance execution means 334 overwrites the current luminance value with the previous luminance value for the next analysis.

[0073] Here, if the performance execution means 334 were to analyze only layer 1 from time T0 to time T1, the luminance generation information of table 2 assigned to layer 2 at time T1 would not be generated, and the luminance would not be able to be determined based on table 2 from time T1. Therefore, the performance execution means 334 analyzes at least all layers to which tables are validly assigned, regardless of the layer priority, at every predetermined interrupt period (e.g., 33 msec), and generates the respective luminance generation information.

[0074] Fig. 9 is a timing chart showing a processing example of the performance execution means 334. Here, a processing example of the performance execution means 334 at any time T3 (for example, 1.5 seconds after time T0) between time T0 and time T1 in Fig. 8 will be described. This processing is performed at every predetermined interruption period (for example, 33 msec) and is completed within the interruption period.

[0075] At time T3, first, the performance execution means 334 sets the analysis target to layer 1, references the luminance generation information of layer 1, and identifies table 1 from the table identifier in the luminance generation information. Based on the fact that the command to be analyzed is the command "SLINE", the performance execution means 334 adds the previous luminance value "15" to the luminance change value "0.36" to identify the current luminance value "15.36". For the next analysis, the performance execution means 334 overwrites the previous luminance value in the luminance generation information of layer 1 with the current luminance value "15.36".

[0076] Next, the performance execution means 334 sets the analysis target to layer 2, references the luminance generation information of layer 2, and identifies table 2 from the table identifier in the luminance generation information. Furthermore, based on the fact that the command to be analyzed is the command "WAIT", the performance execution means 334 identifies the current luminance value "31" by directly using the previous luminance value "31". Furthermore, for the next analysis, the performance execution means 334 overwrites the previous luminance value in the luminance generation information of layer 2 with the current luminance value "31".

[0077] Next, the performance execution means 334 specifies a luminance value to be transmitted to the performance lighting device 204 based on the priority of each layer. Here, the performance execution means 334 judges whether a table is effectively assigned to the layers in descending order of priority, and specifies the layer with the highest priority (here, layer 1) among the layers to which a table is effectively assigned (e.g., layer 1, layer 2). Then, the performance execution means 334 transmits the specified luminance (e.g., previous luminance value "15.36") based on table 1 assigned to layer 1 to the controller 342 as a lighting command.

[0078] Specifically, as shown in Fig. 9, the performance execution means 334 starts sending the lighting commands by setting the DMA controller to send the lighting commands, and then the DMA controller sends the lighting commands to the controller 342 independently of the performance execution means 334. In this way, the performance execution means 334 shifts the actual sending process of the lighting commands to the DMA controller that can operate independently of itself, and can then immediately execute other processes, for example, processes for other performance lighting devices 204. In this way, even when multiple layers are provided, the lighting commands are sent appropriately based on the table assigned to the layer with the highest priority.

[0079] In addition, in Figure 9, an example has been given in which the performance execution means 334 first analyzes table 1 assigned to layer 1 and then analyzes table 2 assigned to layer 2, but this is not limited to this case and analysis can be performed from a table assigned to any layer regardless of priority.

[0080] However, if there are multiple layers and transmission is started after analysis is completed for all layers to which tables are effectively assigned, as in Fig. 9, depending on the number of layers, there is a risk that the start of transmission of the lighting command will be delayed, causing a delay in reflecting the brightness in the effect lighting device 204. For example, if the switching of the lighting pattern of the effect lighting device 204 is delayed compared to the switching of the image pattern displayed on the effect display unit 200a or the music pattern output to the music output device 206, the player will feel uncomfortable.

[0081] As described above, the performance execution means 334 performs the current analysis based on the results of the previous analysis, and cannot derive the current analysis result unless the previous analysis result (luminance generation information) is held. However, if it is only necessary to identify the luminance of the performance lighting device 204, it is possible to do so by analyzing the table assigned to the layer with the highest priority. Therefore, the performance execution means 334 first analyzes the table assigned to the layer with the highest priority, identifies the luminance of the performance lighting device 204, and quickly transmits the lighting command. Meanwhile, the analysis process of the tables assigned to the remaining layers is performed after the completion of the setting for transmitting the lighting command.

[0082] Fig. 10 is a timing chart showing another processing example of the performance execution means 334. Here, a processing example of the performance execution means 334 at any time T3 (for example, 1.5 seconds after time T0) between time T0 and time T1 in Fig. 8 will be described. This processing is also performed at a predetermined interruption period (for example, 33 msec) as in Fig. 9, and is completed within the interruption period.

[0083] At time T3, the performance execution means 334 first identifies a layer to be analyzed first based on the priority of each layer. Specifically, the performance execution means 334 determines whether a table is effectively assigned to layers in descending order of priority, and identifies the layer with the highest priority (here, layer 1) among the layers to which a table is effectively assigned (e.g., layer 1, layer 2).

[0084] Then, the performance execution means 334 analyzes layer 1, which has been determined to have a high priority, and refers to the luminance generation information of layer 1 to identify table 1 from the table identifier in the luminance generation information. Based on the fact that the command to be analyzed is the command "SLINE", the performance execution means 334 adds the previous luminance value "15" and the luminance change value "0.36" to identify the current luminance value "15.36". For the next analysis, the performance execution means 334 overwrites the previous luminance value in the luminance generation information of layer 1 with the current luminance value "15.36".

[0085] Next, the performance execution means 334 transmits the brightness (e.g., previous brightness value "15.36") specified based on the table 1 assigned to that layer 1 as a lighting command to the controller 342. Specifically, as shown in Fig. 10, the performance execution means 334 sets the transmission of the lighting command to the DMA controller, and then the DMA controller transmits the lighting command to the controller 342 independently of the performance execution means 334. In this way, the performance execution means 334 shifts the actual transmission process of the lighting command to the DMA controller capable of operating independently of itself, thereby enabling it to immediately thereafter execute other processes, for example, processes for other layers.

[0086] Then, after the transmission process is shifted to the DMA controller, the performance execution means 334 sets the analysis target to layer 2, references the luminance generation information of layer 2, and identifies table 2 from the table identifier in the luminance generation information. Furthermore, based on the fact that the command to be analyzed is the command "WAIT", the performance execution means 334 identifies the current luminance value "31" by using the previous luminance value "31" as is. Furthermore, for the next analysis, the performance execution means 334 overwrites the previous luminance value in the luminance generation information of layer 2 with the current luminance value "31".

[0087] In this way, even when multiple layers are provided, lighting commands can be sent appropriately and quickly based on the table assigned to the layer with the highest priority. Therefore, the lighting pattern of the effect lighting device 204 does not lag behind the image pattern displayed on the effect display unit 200a or the music pattern output to the music output device 206, and the player does not feel uncomfortable.

[0088] Here, the tables assigned to layers other than the layer with the highest priority are analyzed after the lighting command is sent, but since all of this processing is performed in parallel within a specified interrupt period (e.g., 33 msec), the order in which the tables are analyzed does not affect the timing of luminance emission.

[0089] Furthermore, even when, for example, at time T1 in FIG. 10, i.e., when the analysis process of the table assigned to layer 1 is completed, the layer with the highest priority among the layers to which a table is validly assigned, that is, layer 2 in this case, is analyzed as the top priority, so that a lighting command is sent appropriately and promptly, as at time T3.

[0090] For convenience of explanation, two layers (layer 1, layer 2) are given here, and the analysis of the layer with the highest priority (e.g., layer 1) is performed first, and the analysis of the layer with the next highest priority (e.g., layer 2) is performed after the lighting command transmission setting is made. However, this is not limited to the above case. When there are three or more layers, the analysis of the layer with the highest priority among the three or more layers may be performed first, and the analysis of the other layers may be performed in any order after the lighting command transmission setting is made. This is because the lighting effect device 204 can output only one luminance, and as long as the luminance of the layer with the highest priority can be transmitted, the analysis order of the other layers does not affect the control of the lighting effect device 204.

[0091] Also, for convenience of explanation, an example has been described in which the analysis of the layer with the highest priority (e.g., layer 1) is performed first for one performance lighting device 204, and the analysis of the layer with the next highest priority (e.g., layer 2) is performed after the lighting command transmission setting. However, this is not limited to the above case, and when the lighting pattern is determined at once for each of multiple performance lighting devices 204, the analysis of the layer with the highest priority for each of the multiple performance lighting devices 204 may be performed first, the identified luminance may be transmitted, and then the analysis of layers other than the layer with the highest priority for each of the multiple performance lighting devices 204 may be performed.

[0092] In this way, the gaming machine 100 includes a performance determination means 332 that determines a command module (e.g., a table) that indicates a lighting pattern, a performance execution means 334 that updates the lighting mode (e.g., brightness generation information) corresponding to the command module based on the command module, and a performance lighting device 204 that emits light based on the updated lighting mode (using the brightness of the brightness generation information), and a priority is assigned to the command modules. When there are multiple command modules to be processed in parallel, the performance execution means 334 updates the lighting mode corresponding to the command module with the highest priority, transmits the updated lighting mode based on the command module with the highest priority to the performance lighting device, and updates the lighting modes corresponding to command modules other than the command module with the highest priority among the multiple command modules to be processed in parallel.

[0093] Note that, here, a command module has been described as a table, which is a group of commands that indicate lighting patterns; however, this is not limited to the above case, and it is sufficient if the command module can represent the time-series changes in the lighting state of the lighting performance device 204. For example, a program written in a programming language, or a list enumerating combinations of execution time and lighting state can also be used.

[0094] Also, here, luminance generation information was given as an example of the lighting mode. However, this is not limited to such a case. When analyzing the command module (table), it suffices to be able to grasp the previous state, for example, which process of the command module was performed immediately before. Various information such as luminance values can be applied. Also, the state held depending on the lighting mode is not limited to luminance and may be represented by two values of lighting "1" or extinguishing "0".

[0095] Also, here, an example was given in which a hierarchical structure is provided for the lighting pattern of the effect lighting device 204, the analysis of the layer with the highest priority is performed first, and after reflecting the analysis result in the effect lighting device 204, the analysis of layers other than the layer with the highest priority is performed. However, it can be applied not only to the lighting pattern of the effect lighting device 204 but also to the image pattern displayed on the effect display unit 200a and the prop pattern for driving the prop device 202.

[0096] <Control of RTC> As described above, when the sub-CPU 330a reads the current time, it transmits the address of the RTC 348 on the I2C communication line and receives data (time information) indicating the current time from the RTC 348. The RTC 348 is composed of an integrated circuit (electronic element) and can generate the time and date of year, month, and day based on an arbitrary clock alone. Also, the RTC 348 has a power source independent of the power source of the sub-CPU 330a and can continue to update the time and date of year, month, and day even if the power source of the sub-CPU 330a is turned off. Therefore, even if the time managed by the sub-CPU 330a is erased due to power-off, the sub-CPU 330a can perform processing using the current time by reading the time from the RTC 348 at power-on.

[0097] For example, the sub CPU 330a uses the current time acquired from the RTC 348, and when the current time reaches a predetermined time, it becomes possible to execute a predetermined effect (effect release). Also, the sub CPU 330a uses the date of the current day, and when the date of the current day reaches a predetermined date, for example, the birthday of a character symbolizing the gaming machine 100, it becomes possible to execute a congratulatory effect to celebrate this. Also, the sub CPU 330a executes an effect corresponding to the season to which the current day belongs.

[0098] However, with the RTC 348, there are cases where the time recorded differs from the actual time due to a hardware malfunction. The following describes the effects of such a malfunction.

[0099] FIG. 11 is an explanatory diagram showing a comparative example of a communication mode between the sub-CPU 330a and the RTC 348. For convenience of explanation, it is assumed here that the sub-CPU 330a acquires time information indicating the current time from the RTC 348 every 4 seconds (at a 4-second cycle). Note that while the acquired time information is shown in hours, minutes, and seconds here, this is not limiting, and the time information may be acquired in units smaller than seconds, such as msec units or year, month, and day. Here, it is assumed that the RTC 348 has already been initialized, indicates the original time, and is updated sequentially. Therefore, as shown in FIG. 11, the time (RTC update time) is incremented by one second at a time according to the internal clock from "11:23:45".

[0100] When a predetermined period (e.g., 4 seconds) arrives, the sub-CPU 330a acquires time information from the RTC 348 through I2C communication. The sub-CPU 330a then executes processing according to the time indicated by the acquired time information. For example, the sub-CPU 330a acquires time information from the RTC 348 when the time in the RTC 348 is "11:23:47". The sub-CPU 330a executes a presentation according to the time "11:23:47" indicated by the acquired time information.

[0101] Here, it is simply described that the sub-CPU 330a obtains time information from the RTC 348 through I2C communication. Specifically, in order to establish communication with the RTC 348, the sub-CPU 330a prohibits the reception of communication requests to other slave devices, i.e., prohibits communication with other slave devices (communication lock), then transmits the address of the RTC 348 through I2C communication, receives data (time information) indicating the current time from the RTC 348, and permits the reception of communication requests to other slave devices after receiving the data (communication unlock). The prohibition and permission of the reception of communication requests may be performed based on a communication permission flag. For example, when a communication request to one slave device is permitted to be received, the sub-CPU 330a turns on the communication permission flag, prohibits the reception of communication requests to other slave devices while the communication permission flag is on, and when communication with the one slave device is completed, turns off the communication permission flag and permits the reception of communication requests to other slave devices.

[0102] Here, when the time in the RTC 348 is "11:23:49", a malfunction caused by hardware, for example, noise from electromagnetic waves, affects the RAM or register that holds the time in the RTC 348. Here, it is assumed that the malfunction causes the time in the RTC 348 to change from "11:23:49" to "1:33:20". Therefore, the RTC 348 continues to increment by one second from the changed time "1:33:20". Then, when a predetermined period (for example, four seconds) has passed, the sub CPU 330a acquires time information from the RTC 348. Since four seconds have passed since the previous time "11:23:47", the sub CPU 330a should be able to acquire the time "11:23:51", but actually acquires the time "1:33:22". In this case, the sub CPU 330a executes a performance according to the acquired time "1:33:22".

[0103] For example, if a presentation reminiscent of daytime (such as a standby presentation) is to be executed at the time "11:23:51", a presentation reminiscent of late night is executed at the time "1:33:22". In this case, the player will feel uncomfortable with the presentation that does not match the current time.

[0104] The time of the RTC 348 is used as a time stamp when an error occurs or when a setting change is made in the gaming machine 100. Therefore, if the time updated by the RTC 348 is different from the original time, for example, the time indicated by the time stamp of the error will be different from the original time when the error occurred. In this case, if the time does not satisfy the error extraction condition, the error may be discovered late. In addition, since the time when the error occurred is different from the original time, it becomes difficult to properly reproduce the situation when the error occurred, and it becomes difficult to identify the cause of the error. In addition, if the time of the RTC 348 is changed due to fraudulent acts such as intentionally applying strong electromagnetic waves to the RTC 348, the time when the fraudulent acts were performed will also change, and there is a risk that detection will be delayed or information caused by the fraudulent acts will not be sufficiently collected. In addition, the setting is changed outside the business hours of the hall, but even if the setting is changed illegally during the business hours of the hall, if the time of the RTC 348 indicates outside the business hours, the fact that the setting was changed illegally may be hidden.

[0105] Therefore, in parallel with updating the time in the RTC 348, the sub-CPU 330a also updates the time, and by making the two consistent, the time in the RTC 348 is maintained at an appropriate value.

[0106] Fig. 12 is an explanatory diagram showing an example of a communication state between the sub-CPU 330a and the RTC 348. As in Fig. 11, only the time (hour, minute, second) is shown here for convenience of explanation. Also, assume that the RTC 348 has already been initialized and shows the original time, and that the time is updated sequentially. Therefore, as shown in Fig. 12, the time is incremented by one second from "9:23:46" according to the internal clock.

[0107] The sub CPU 330a acquires the time from the RTC 348 through I2C communication at any timing after power-on. The sub CPU 330a then executes processing according to the acquired time. For example, the sub CPU 330a acquires the time from the RTC 348 when the time in the RTC 348 is "9:23:47". The sub CPU 330a executes a performance according to the acquired time "9:23:47".

[0108] The sub CPU 330a further sets the acquired time "9:23:47" as an initial value, and thereafter updates the time self-containedly, like the RTC 348. However, unlike the RTC 348, the sub CPU 330a can only update the time while the gaming machine 100 is powered on, and the time information is erased when the power is turned off. Even if the power is turned off, the time information can be held fixedly by the non-volatile RAM, but the time cannot be updated while the power is off, so when the power is turned on, the time shown is the time at the time of power off, which is different from the original time. Also, unlike the RTC 348, the sub CPU 330a performs software timekeeping. For example, the sub CPU 330a counts the number of interrupts according to a predetermined interrupt period (for example, 33 msec) and updates the time according to the value.

[0109] Here, assume that when the time in the RTC 348 is "11:23:49", a hardware-related problem, for example, electromagnetic noise, affects the RAM or register that holds the time in the RTC 348. Assume that the problem causes the time in the RTC 348 to change from "11:23:49" to "1:33:20". The RTC 348 continues to increment the time by one second from the changed time "1:33:20". The sub-CPU 330a then acquires time information from the RTC 348 at a predetermined cycle (for example, every four seconds). Because four seconds have passed since the previous time "11:23:47", the sub-CPU 330a should be able to acquire the time "11:23:51" from the RTC 348, but actually acquires the time "1:33:22".

[0110] However, in this embodiment, the sub CPU 330a verifies the validity of the time acquired from the RTC 348. That is, the sub CPU 330a compares the time it updates with the time acquired from the RTC 348. For example, when the sub CPU 330a acquires the time "1:33:22" from the RTC 348, the sub CPU 330a independently updates the time (CPU updated time) to "11:23:51". Therefore, the sub CPU 330a can recognize that the time it updates, "11:23:51", is different from the time "1:33:22" acquired from the RTC 348. Then, the sub CPU 330a resets (corrects) the time it updates, "11:23:51", as the initial value of the RTC 348. The sub-CPU 330a then executes processing according to the time it has updated, "11:23:51," rather than the time "1:33:22" obtained from the RTC 348.

[0111] Here, the sub-CPU 330a updates the time independently of the RTC 348 in parallel with the RTC 348. When the sub-CPU 330a acquires time information from the RTC 348, it compares the time indicated by the time information with the time it updates itself to determine whether it is valid. If the sub-CPU 330a determines that the time indicated by the time information acquired from the RTC 348 is valid (equal to the time it updates itself), it uses the time indicated by the time information acquired from the RTC 348, and if it determines that the time indicated by the time information acquired from the RTC 348 is invalid (different from the time it updates itself), it resets the time of the RTC 348 to the time it updates itself and executes processing using that time. With this configuration, it is possible to maintain the time of the RTC 348 at an appropriate value.

[0112] In addition, here, when the time updated by the sub-CPU 330a differs from the time updated by the RTC 348, the time updated by the sub-CPU 330a is adopted as the correct value. This is because the RAM and registers of the sub-CPU 330a are designed to be more resistant to changes in the surrounding environment than the RTC 348 while powered on, and are configured to be less susceptible to noise such as electromagnetic waves, for example.

[0113] In addition, the sub CPU 330a uses the time indicated by the time information updated by the RTC 348 after power-on as the initial value of the time. This is because the sub CPU 330a can only update the time while the gaming machine 100 is powered on, and once the power is turned off, the time held by the sub CPU 330a becomes unreliable, and the most reliable time at that point in time is the time updated by the RTC 348.

[0114] Fig. 13 is a flowchart for explaining the operation of the sub-CPU 330a. Fig. 13(a) shows the initialization setting process when the gaming machine 100 is installed, and Fig. 13(b) shows the normal process after the gaming machine 100 is installed.

[0115] The time of the RTC 348 is initially set when the gaming machine 100 is shipped from the factory. When the gaming machine 100 is installed and powered on, the time of the RTC 348 is the initial value at the time of shipment, and may differ from the current time. Therefore, as shown in FIG. 13(a), the sub-CPU 330a determines whether or not a hall clerk or manager has set the time of the RTC 348 (S20), and waits for the setting input while there is no setting input (NO in S20). When a hall clerk or manager has set the time of the RTC 348 (YES in S20), the sub-CPU 330a sets the input time in the RTC 348 (S21).

[0116] Furthermore, after setting the time in the RTC 348 as shown in FIG. 13(a), when the gaming machine 100 is powered on, the sub-CPU 330a acquires time information from the RTC 348 (S30), as shown in FIG. 13(b), and sets the time indicated by the acquired time information as the initial value of the time to be updated within the sub-CPU 330a (S31).

[0117] Then, the sub CPU 330a waits for a predetermined interrupt period (e.g., 33.3 msec) to arrive (NO in S32), and when the predetermined interrupt period arrives (YES in S32), the sub CPU 330a acquires time information from the RTC 348 (S33). The sub CPU 330a also updates the time it manages in response to the arrival of the interrupt period (S34). For example, the sub CPU 330a increments a counter by 1 in response to the arrival of the interrupt period, and when it reaches 30 (1 second / 33 msec), it increments the time by 1 second and initializes the counter.

[0118] Next, the sub CPU 330a compares the time indicated by the time information acquired from the RTC 348 with the time updated by itself (S35). As a result, if the time indicated by the time information acquired from the RTC 348 is equal to the time updated by itself (YES in S35), the sub CPU 330a moves the process to step S37, and if the time indicated by the time information acquired from the RTC 348 is different from the time updated by itself (NO in S35), the sub CPU 330a moves the process to step S36. If the time acquired from the RTC 348 is different from the time updated by itself, it is determined that the time of the RTC 348 has become different from the original time due to some malfunction, and the sub CPU 330a sets the time updated by itself to the RTC 348 (S36). The sub CPU 330a saves the time thus determined in the sub RAM 330b so that it can be referred to in other processes (S37).

[0119] With this configuration, even if the time on the RTC 348 becomes different from the original time due to a hardware malfunction, it is possible to maintain the time on the RTC 348 at an appropriate value. In this way, the sub-CPU 330a can execute effects that match the appropriate time, and the player will not feel uncomfortable.

[0120] In addition, if an error occurs or a setting change is made within the gaming machine 100, the appropriate time is displayed as a timestamp, making it possible to properly identify the time and circumstances of the error or setting change.

[0121] In addition, while the power is on, the time updated by the sub-CPU 330a, which is more resistant to changes in the surrounding environment than the RTC 348, is used, and while the power is off, the RTC 348 updates the time, making it possible to properly refer to the original time regardless of whether the power is on or off.

[0122] In this way, the gaming machine 100 is equipped with a CPU (e.g., sub-CPU 330a) and an RTC (RTC element) 348, and the CPU acquires time information from the RTC 348 at a first timing (e.g., when the power is turned on, etc.), sets the time indicated by the time information acquired at the first timing as an initial value, then updates the time, acquires time information from the RTC 348 at a second timing after the first timing (e.g., when a specified period arrives, etc.), compares the first time, which is the time updated by the CPU, with the second time indicated by the time information acquired at the second timing, and if the first time and the second time differ, sets the RTC 348 to the first time.

[0123] Here, an example has been described in which time information is acquired from the RTC 348 at a second timing (e.g., when a predetermined period arrives, etc.), the first time, which is the time updated by the sub-CPU 330a, is compared with the second time indicated by the time information acquired at the second timing, and if the first time and the second time are different, the first time is set to the RTC 348. However, depending on conditions, the first time may not be set to the RTC 348. If a malfunction due to hardware occurs, the second time of the RTC 348 changes significantly. However, if the time difference between the first time and the second time is small, for example, less than 3 seconds, it may not be that a malfunction due to hardware has occurred, but rather that an error in updating the time has simply occurred. Therefore, the CPU (e.g., the sub-CPU 330a) may set the RTC 348 to the first time if the time difference between the first time and the second time is a predetermined time difference (e.g., 3 seconds) or more, and may not set the RTC 348 to the first time if the time difference between the first time and the second time is less than the predetermined time difference. In addition, the RTC 348 is often more accurate than the sub-CPU 330a because it is specialized in updating the time. In this case, the second time is often more accurate than the first time. Here, when the first time and the second time are different and the time difference between them is less than a predetermined time difference (e.g., 3 seconds), the first time is not set in the RTC 348, and instead the second time is set in the sub-CPU 330a, making it possible to maintain the time of the RTC 348 at an appropriate value. However, if the second time is always set in the sub-CPU 330a when the time difference is less than the predetermined time difference, the process may become complicated. Therefore, if the first time and the second time are different and the time difference between them is equal to or greater than a specific time difference (e.g., 1 second) and less than a predetermined time difference (e.g., 3 seconds), the second time may be set in the sub CPU 330a, and if the time difference is less than the specific time difference, the second time may not be set in the sub CPU 330a (and the first time may not be set in the RTC 348).In this way, the process of setting the second time in the sub CPU 330a is not performed until the time difference between the first time and the second time becomes the specific time difference, so that the processing load can be reduced.

[0124] <Amplifier control> When the sub-CPU 330a instructs the amplifier 206a on the volume of music data, the sub-CPU 330a transmits the address of the amplifier 206a via I2C communication and then transmits volume information. The amplifier 206a amplifies the music data (music signal) input from the music IC 346a according to the volume indicated by the volume information received from the sub-CPU 330a, and outputs the amplified analog signal to the speaker 206b.

[0125] Fig. 14 is a timing chart showing a comparative example of a communication mode between the sub-CPU 330a and the amplifier 206a. In Fig. 14, transmitted information via I2C communication is surrounded by a solid line, and received information via I2C communication is surrounded by a dashed line.

[0126] When a volume setting instruction is issued, the sub-CPU 330a, which is a master device, prohibits the reception of communication requests from other slave devices, i.e., communication with other slave devices (hereinafter, simply referred to as locking communication), in order to establish communication with the amplifier 206a (specific slave device), which is a slave device, and transmits the address of the amplifier 206a, a Write request (indicated simply as "W" in FIG. 14), and volume information through I2C communication, as shown in FIG. 14. The amplifier 206a, which is a slave device, receives the volume information in response to its own address and the Write request. After transmitting the volume information, the sub-CPU 330a permits the reception of communication requests from other slave devices, i.e., permits communication with other slave devices (hereinafter, simply referred to as unlocking communication). The address includes a slave device address indicating the slave device to be communicated with, and a register address indicating the register to be communicated with in the slave device. For example, when the sub-CPU 330a transmits volume information, it designates, as an address, a slave device address indicating the amplifier 206a and a register address (LSB=1b) indicating the storage destination of the audio information. The volume information also includes information indicating the volume normally transmitted, as well as information for setting or initializing the volume transmitted when the power is turned on, when an amplifier error occurs, or when the settings of the amplifier 206a are changed.

[0127] The sub-CPU 330a performs a cyclic redundancy check (hereinafter simply referred to as CRC) calculation on all transmitted data and generates a check result (hereinafter referred to as CRC result). The CRC result is the result of the CRC calculation and is a code that detects data errors. For example, the data transmitting side adds the remainder (e.g., 1 byte) of division by a predetermined generating polynomial to the data as the CRC result and transmits it, and the data receiving side also divides the data using the same generating polynomial, and the remainders, that is, the CRC results, are compared and collated to detect data errors and damage.

[0128] When the CRC calculation is completed, the sub CPU 330a again locks the communication to establish communication with the amplifier 206a, and transmits the address of the amplifier 206a, a write request, and the CRC result (first error determination information) through I2C communication. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address (LSB=0b) indicating the storage destination of the CRC result. The amplifier 206a receives the CRC result in response to its own address and the write request. After transmitting the CRC result, the sub CPU 330a unlocks the communication.

[0129] In response to receiving the CRC result (storing the CRC result in the register indicated by the register address), the amplifier 206a generates a CRC result (second error detection information) for all received data excluding the CRC result, compares the generated CRC result with the received CRC result to perform error detection, and stores the comparison result in memory within the amplifier 206a.

[0130] Fig. 15 is an explanatory diagram for explaining the generation process of the CRC result. The sub-CPU 330a calculates the CRC for all data transmitted to the amplifier 206a. Therefore, the sub-CPU 330a calculates the CRC including the address and the Write request for transmitting the CRC result in addition to the address, the Write request, and the volume information transmitted up to that point at the timing of completing the transmission of the volume information in Fig. 15 and unlocking the communication. Since the address for transmitting the CRC result is predetermined, the sub-CPU 330a can grasp the address and the Write request at the time of completing the transmission of the volume information, and can therefore calculate the CRC at the time of completing the transmission of the volume information.

[0131] On the other hand, the amplifier 206a also calculates the CRC for all the received data. However, the amplifier 206a calculates the CRC for all the data transmitted through the I2C communication from when it receives an address that specifies itself as the communication destination in the I2C communication until it receives the CRC result that specifies itself as the communication destination. Therefore, as shown in FIG. 15, at the timing when the amplifier 206a receives the CRC result that specifies itself as the communication destination, it calculates the CRC for all the data received up to that point, excluding the CRC result, that is, for the data from the address that specifies itself as the communication destination to the Write request for transmitting the CRC result that specifies itself as the communication destination. In this way, the amplifier 206a can compare the CRC result that it calculated with the CRC result received from the sub-CPU 330a and determine whether there is an error. Note that the amplifier 206a sequentially calculates the CRC for the received data every time it receives data. In this way, it is possible to improve the efficiency of the CRC calculation.

[0132] Returning to Fig. 14, after a predetermined time has elapsed that is equal to or longer than the time required for the amplifier 206a to generate the CRC result, the sub-CPU 330a locks communication to establish communication with the amplifier 206a, transmits the address of the amplifier 206a and a read request (indicated simply by "R" in Fig. 14) via I2C communication, receives the comparison result from the amplifier 206a, and unlocks communication after receiving the comparison result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address indicating the read destination of the comparison result. In this way, the volume information is appropriately transmitted from the sub-CPU 330a to the amplifier 206a.

[0133] In this way, the sub CPU 330a transmits volume information to the amplifier 206a through I2C communication. As described above, in such I2C communication, a plurality of slave devices can be connected to one master device (here, the sub CPU 330a). For example, the RTC 348 is also connected as another slave device to the clock signal line and data signal line of the I2C communication to which the amplifier 206a is connected. In this case, the sub CPU 330a does not accept communication with the RTC 348 while communication with the amplifier 206a is locked, but can communicate with the RTC 348 when communication with the amplifier 206a is unlocked. Therefore, the sub CPU 330a may obtain time information from the RTC 348 between the transmission of volume information and the transmission of the CRC shown in FIG. 14. In this way, the following events may occur when communication with a plurality of slave devices is performed in parallel.

[0134] Fig. 16 is a timing chart showing a comparative example of communication between the sub-CPU 330a, the amplifier 206a, and the RTC 348. In Fig. 16, information transmitted via I2C communication is surrounded by a solid line, and information received via I2C communication is surrounded by a dashed line.

[0135] When a volume setting instruction is received, the sub-CPU 330a locks communication to establish communication with the amplifier 206a, and transmits the address of the amplifier 206a, a write request, and volume information through I2C communication. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address (LSB=1b) indicating the storage destination of the volume information. The amplifier 206a receives the volume information in response to its own address and the write request. After transmitting the volume information, the sub-CPU 330a unlocks communication. In addition, the sub-CPU 330a calculates a CRC for the transmission data including the volume information, and generates a CRC result.

[0136] However, when calculating the CRC, the sub-CPU 330a unlocks communication with the amplifier 206a and temporarily releases the I2C communication to other slave devices. Here, it is assumed that an instruction to acquire time information is given while the I2C communication is released. In response to the instruction to acquire time information, the sub-CPU 330a locks communication to establish communication with the RTC 348 and transmits the address of the RTC 348 and a Read request through the I2C communication. Here, the address is composed of a slave device address indicating the RTC 348 and a register address indicating the destination from which the time information is read. In response to its own address and the Read request, the RTC 348 transmits time information indicating the time it is updating to the sub-CPU 330a. After receiving the time information, the sub-CPU 330a unlocks communication. In this way, the sub-CPU 330a can acquire the time information and grasp the current time.

[0137] When communication with the RTC 348 is unlocked and the calculation of the CRC result is completed, the sub-CPU 330a locks the communication to establish communication with the amplifier 206a, transmits the address of the amplifier 206a and a write request through I2C communication, and transmits the CRC result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address (LSB=0b) indicating the storage destination of the CRC result. The amplifier 206a receives the CRC result in response to its own address and the write request. After transmitting the CRC result, the sub-CPU 330a unlocks the communication.

[0138] As described above, in response to receiving the CRC result (storing the CRC result in the register indicated by the register address), the amplifier 206a generates a CRC result for all of the received data excluding the CRC result, compares the generated CRC result with the received CRC result to determine whether there is an error, and stores the comparison result in memory within the amplifier 206a.

[0139] Fig. 17 is an explanatory diagram for explaining the generation process of the CRC result. As in Fig. 15, the sub CPU 330a calculates the CRC for all data transmitted to the amplifier 206a. Therefore, at the timing when the sub CPU 330a completes the transmission of the volume information in Fig. 17 and unlocks the communication, the sub CPU 330a calculates the CRC including the address and the Write request for transmitting the CRC result in addition to the address, Write request, and volume information transmitted up to that point. Note that the address for transmitting the CRC result is predetermined, so the sub CPU 330a can grasp the address and the Write request when the transmission of the volume information is completed, and can therefore calculate the CRC at the timing when the transmission of the volume information is completed.

[0140] On the other hand, the amplifier 206a also calculates the CRC for all the received data. However, as described above, the amplifier 206a calculates the CRC for all the data transmitted through the I2C communication from when it receives an address that specifies itself as the communication destination in the I2C communication until it receives a CRC result that specifies itself as the communication destination. Therefore, as shown in FIG. 17, at the timing when the amplifier 206a receives the CRC result that specifies itself as the communication destination, it calculates the CRC for all the data received up to that point, excluding the CRC result, that is, for the data from the address that specifies itself as the communication destination to the Write request for transmitting the CRC result that specifies itself as the communication destination. This means that the amplifier 206a calculates the CRC for data that does not specify itself as the communication destination, for example, communication data with the RTC 348 (address, Read request, time information). In this case, the CRC result generated by the sub-CPU 330a has the following objects: address, write request, volume information, address, and write request, whereas the CRC result generated by the amplifier 206a has the following objects: address, write request, volume information, address, read request, time information, address, and write request, which are different. Therefore, the amplifier 206a compares the CRC result it has calculated with the CRC result it has received from the sub-CPU 330a, but the results are not consistent.

[0141] Returning to FIG. 16, after a predetermined time has elapsed that is equal to or longer than the time required for the amplifier 206a to generate the CRC result, the sub-CPU 330a locks the communication to establish communication with the amplifier 206a, transmits the address of the amplifier 206a and a read request through I2C communication, receives the comparison result from the amplifier 206a, and unlocks the communication after receiving the comparison result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address indicating the read destination of the comparison result. However, as described above, since the CRC result generated by the sub-CPU 330a is different from the CRC result generated by the amplifier 206a, the amplifier 206a does not adopt the volume information, and the sub-CPU 330a does not transmit the volume information appropriately.

[0142] Here, for example, the amplifier 206a is designed to calculate the CRC for all data from when it receives an address that specifies itself as the communication destination in I2C communication until it receives a CRC result that specifies itself as the communication destination, that is, even for data that does not specify itself as the communication destination, and therefore the CRC result generated by the amplifier 206a differs when communication with another slave device is performed before transmitting the CRC result. Therefore, in this embodiment, the sub-CPU 330a calculates the CRC and transmits the CRC result before unlocking communication when transmitting volume information, thereby preventing communication with another slave device from being performed between the transmission of volume information and the transmission of the CRC result.

[0143] Fig. 18 is a timing chart showing an example of communication between the sub CPU 330a, the amplifier 206a, and the RTC 348. In Fig. 18, information transmitted via I2C communication is surrounded by a solid line, and information received via I2C communication is surrounded by a dashed line.

[0144] When a volume setting instruction is given, the sub CPU 330a locks communication to establish communication with the amplifier 206a, and transmits the address of the amplifier 206a, a Write request, and volume information through I2C communication. The sub CPU 330a transmits the volume information, calculates CRC for data including the volume information, and generates a CRC result (first error determination information). In order to transmit the volume information efficiently, the sub CPU 330a sequentially generates the volume information, and in parallel sequentially transmits the generated volume information and sequentially calculates CRC for the volume information. Then, the sub CPU 330a transmits the calculated CRC result following the volume information. Here, in order to transmit the volume information and the CRC result at once, the address is configured with a slave device address indicating the amplifier 206a and a register address (LSB=0b) indicating the storage destination of the volume information and the CRC result. The amplifier 206a, which is a slave device, receives the volume information in response to its own address and the Write request, and subsequently receives the CRC result. The sub CPU 330a unlocks the communication after transmitting the CRC result. In other words, the sub CPU 330a does not unlock the communication (keeps it locked) after transmitting the volume information, but unlocks the communication after transmitting the CRC result.

[0145] In response to receiving the CRC result (storing the volume information and the CRC result in the register indicated by the register address), the amplifier 206a generates a CRC result (second error detection information) for all received data excluding the CRC result, compares the generated CRC result with the received CRC result to perform error detection, and stores the comparison result in memory within the amplifier 206a.

[0146] FIG. 19 is an explanatory diagram for explaining the generation process of the CRC result. The sub CPU 330a calculates the CRC for all data transmitted to the amplifier 206a. Therefore, the sub CPU 330a calculates the CRC for the address, the Write request, and the volume information transmitted up to that point at the latest by the timing when the transmission of the volume information is completed in FIG. 19. The sub CPU 330a does not transmit the CRC result independently of the volume information as in FIG. 16, but transmits the CRC result integrally following the volume information as shown in FIG. 18. In this way, the address and the Write request for transmitting the CRC result as in FIG. 17 are not included in the object of the CRC calculation. Therefore, the CRC calculation load on the sub CPU 330a is reduced.

[0147] On the other hand, the amplifier 206a also calculates the CRC for all the received data. However, as described above, the amplifier 206a calculates the CRC for all the data transmitted through the I2C communication from when it receives an address that specifies itself as a communication destination in the I2C communication until it receives a CRC result that specifies itself as a communication destination. Therefore, as shown in FIG. 19, at the timing when the amplifier 206a receives the CRC result that specifies itself as a communication destination, it calculates the CRC for all the data received up to that point, excluding the CRC result, that is, for the data from the address that specifies itself as a communication destination to the volume information. However, the sub-CPU 330a does not transmit the CRC result independently of the volume information as shown in FIG. 16, but transmits the CRC result together with the volume information as shown in FIG. 18. Therefore, here, from when it receives an address that specifies itself as a communication destination in the I2C communication until it receives a CRC result that specifies itself as a communication destination, information on communication with other slave devices is not included in the CRC calculation as shown in FIG. 17. In this way, when the amplifier 206a compares the CRC result it has calculated with the CRC result it has received from the sub-CPU 330a, the two will match.

[0148] Returning to FIG. 18, after transmitting the CRC result, the sub-CPU 330a unlocks communication with the amplifier 206a and temporarily releases the I2C communication to other slave devices. Here, assume that an instruction to acquire time information is received while the I2C communication is released. In response to the instruction to acquire time information, the sub-CPU 330a locks communication to establish communication with the RTC 348 and transmits the address of the RTC 348 and a Read request through the I2C communication. Here, the address is composed of a slave device address indicating the RTC 348 and a register address indicating the read destination of the time information. The RTC 348 transmits the time information to the sub-CPU 330a in response to its own address and the Read request. After receiving the time information, the sub-CPU 330a unlocks communication. In this way, the sub-CPU 330a can acquire the time information and grasp the current time.

[0149] When communication with the RTC 348 is unlocked and the calculation of the CRC result is completed, the sub-CPU 330a locks communication to establish communication with the amplifier 206a after a predetermined time has elapsed that is equal to or longer than the time it took for the amplifier 206a to generate the CRC result, transmits the address of the amplifier 206a and a read request through I2C communication, receives the comparison result from the amplifier 206a, and unlocks communication after receiving the comparison result. Here, the address is composed of a slave device address indicating the amplifier 206a and a register address indicating the read destination of the comparison result.

[0150] Here, the sub-CPU 330a establishes communication with the RTC 348, which is another slave device, after transmitting the CRC result, but all data to be calculated by CRC has already been transmitted to the amplifier 206a, and the amplifier 206a does not include information on communication with other slave devices in its CRC calculation from when it receives an address specifying itself as the communication destination in I2C communication until it receives the CRC result specifying itself as the communication destination, as shown in Fig. 17. Therefore, as shown in Figs. 16 and 17, the CRC results do not differ between the sub-CPU 330a and the amplifier 206a, and an appropriate CRC result can be obtained.

[0151] In addition, in the comparative example of FIG. 16, the volume information and the CRC result are transmitted at different times, but in the example of FIG. 18, they are transmitted at the same time. This reduces the number of communications between the sub-CPU 330a and the amplifier 206a, thereby reducing the probability of communication with other slave devices being interrupted.

[0152] In addition, by changing the timing, the address and write request that were previously required for both the volume information and the CRC result are now only required once for both the volume information and the CRC result, reducing the CRC calculation load on the sub-CPU 330a and the amplifier 206a and shortening the communication time. Therefore, when the power is turned on, the sub-CPU 330a can start communication with another slave device, for example, the RTC 348, and can acquire time information early.

[0153] In the above, an example was described in which the sub CPU 330a does not immediately unlock (keeps locked) the communication after transmitting the volume information, but performs a CRC calculation and unlocks it after transmitting the CRC result. In such a case, it may be difficult in terms of processing power for the sub CPU 330a to perform the CRC calculation in parallel while transmitting the volume information. In that case, the sub CPU 330a calculates the CRC after transmitting the volume information, and transmits the CRC result after the calculation. That is, since the I2C communication remains in a locked state while the CRC is being calculated, the sub CPU 330a is in a state of waiting for the transmission of the CRC result. This state of waiting for the transmission of the CRC result can be resolved by using a DMA (Direct Memory Access) controller.

[0154] 20 is a timing chart for explaining the transmission mode of the sub CPU 330a. The sub CPU 330a generates volume information in response to a volume setting instruction. When the sub CPU 330a generates the volume information, it locks communication with the amplifier 206a and sets an address, a Write request, and the volume information in the DMA controller. The DMA controller establishes communication with the amplifier 206a using the set address and Write request, and transmits the volume information to the amplifier 206a.

[0155] After setting the address, Write request, and volume information in the DMA controller, the sub CPU 330a can execute processes other than the transmission process without being involved in the transmission process. Here, the sub CPU 330a calculates a CRC for the address, Write request, and volume information set in the DMA controller. When the sub CPU 330a generates the CRC result, it sets the generated CRC result in the DMA controller and unlocks communication with the amplifier 206a. The DMA controller transmits the set address and Write request, as well as the CRC result to the amplifier 206a.

[0156] Here, the sub CPU 330a leaves communication with the amplifier 206a to the DMA controller, and generates the CRC result in parallel with the timing when the DMA controller transmits data to the amplifier 206a. Therefore, the sub CPU 330a has a small data transmission load, and depending on the CRC calculation, the processing load itself is also small, so that it can execute other processes early. Here, the sub CPU 330a can unlock the communication immediately after setting the CRC result in the DMA controller. This is because once the transmission data is set in the DMA controller, other transmission data will not interrupt the transmission information of the DMA controller until the transmission of the transmission data is completed, and the amplifier 206a can properly receive the address, write request, volume information, and CRC result.

[0157] The timing and amount of communication between the sub-CPU 330a and the amplifier 206a are as follows. For example, the sub-CPU 330a transmits multiple bytes, for example, 100 bytes, of volume information when the power is turned on, when an amplifier error occurs, or when the amplifier settings are changed (burst write). The sub-CPU 330a may also transmit one byte of volume information when the player adjusts the volume (single write).

[0158] In this manner, the gaming machine 100 includes a master device (e.g., the sub-CPU 330a) and a plurality of slave devices (e.g., the amplifier 206a, the RTC 348, etc.) connected in parallel to the master device via one serial communication line (e.g., an I2C communication line). The master device establishes communication with a specific slave device (e.g., the amplifier 206a) among the plurality of slave devices, transmits specific information (e.g., an address, a write request, volume information) to the specific slave device, generates first error determination information (e.g., a CRC result) based on the specific information, transmits the first error determination information to the specific slave device, and outputs the specific error determination information to the specific slave device. On the premise that the slave device generates second error determination information (e.g., CRC result) based on the data received through the serial communication line from the time it starts receiving specific information from the master device until it receives first error determination information from the master device, and performs error determination by comparing the first error determination information with the second error determination information, the master device prohibits communication with other slave devices (communication lock) after establishing communication with the specific slave device, transmits the first error determination information following the specific information, and permits communication with other slave devices (communication unlock) after transmitting the first error determination information.

[0159] The gaming machine 100 further includes a master device (e.g., a sub-CPU 330a) and a plurality of slave devices (e.g., an amplifier 206a, an RTC 348, etc.) connected in parallel to the master device via one serial communication line (e.g., an I2C communication line). The master device establishes communication with a specific slave device (e.g., the amplifier 206a) among the plurality of slave devices, prohibits communication with the other slave devices (communication lock), transmits specific information (e.g., an address, a write request, volume information) to the specific slave device, generates error determination information based on the specific information, transmits the error determination information (e.g., a CRC result) to the specific slave device following the specific information, and permits communication with the other slave devices after transmitting the error determination information (communication unlock).

[0160] Here, an I2C communication line is used as an example of a serial communication line, but the present invention is not limited to this, and various communication standards that allow multiple devices to serially communicate with each other can be adopted. Here, consecutive data of an address, a write request, and volume information are used as specific information, but the present invention is not limited to this, and any consecutive data that may cause an error will suffice. Here, a CRC (cyclic redundancy check) is used as a means for generating error determination information, but the present invention is not limited to this, and various error detection means such as a parity code, a checksum, and a hash function can be used.

[0161] Although the preferred embodiment of the present invention has been described above with reference to the accompanying drawings, it goes without saying that the present invention is not limited to such an embodiment. It is clear that a person skilled in the art can think of various modifications or alterations within the scope of the claims, and it is understood that these also naturally belong to the technical scope of the present invention.

[0162] For example, in the above-described embodiment, a pachinko machine is exemplified as a gaming machine, which includes a pattern determination means for determining one of a plurality of types of patterns including a jackpot pattern, a pattern display means for displaying a pattern on a pattern display section when a predetermined variation time has elapsed since the pattern was determined, a big prize game execution means for executing a big prize game consisting of a plurality of rounds of play when a jackpot pattern is displayed on the pattern display section, a game profit awarding means for awarding a predetermined game profit when a game ball that has entered a big prize opening enters a specific area during a predetermined specific round play among the rounds of play in the big prize game, and an effect execution means for executing an effect during the big prize game. However, the present invention is not limited to such a case, and can also be applied to a slot machine that includes a winning combination selection means for selecting one of a plurality of winning combinations by a winning combination selection based on the operation of a start switch, a reel control means for controlling the rotation of a plurality of reels on which a plurality of patterns are arranged in accordance with the operation of the start switch, and for controlling the stop of each of the reels corresponding to the operated stop switch based on the selection result of the winning combination selection means in accordance with the operation of the stop switch corresponding to the rotating reel, and an effect control means for executing one of a plurality of effects. The slot machine 600 will be described in detail below.

[0163] (Mechanical Configuration of Slot Machine 600) As shown in the external views of Figures 21 and 22, the slot machine 600 comprises a housing 602 which is a substantially rectangular box-shaped body, an upper front door 604 which is attached to the front opening of the housing 602 so as to be able to be opened and closed by a rotatable connecting member, a lower front door 606 which is located below the upper front door 604 and which, like the upper front door 604, is attached to the front opening of the housing 602 so as to be able to be opened and closed, and a receiving tray 608 which is located below the lower front door 606 and for storing medals paid out from a medal discharge port 608a.

[0164] An operation unit installation stand 622 is formed at the top of the front lower door 606, and on the operation unit installation stand 622, a medal insertion section 624, a bet switch 626, a start switch 628, a stop switch 630, a performance switch 632, etc. are arranged.

[0165] The medal insertion unit 624 located on the right side of the operation unit installation stand 622 accepts medals as game media through the medal insertion port 624a and sends the medals to a medal selector (not shown) provided on the back of the front lower door 606. The medal selector is provided with a blocker (not shown) that guides medals inserted outside the insertion period in which medals can be inserted or medals that do not meet the specifications to the medal discharge port 608a, and an inserted medal detection unit 624b that detects the passage of medals that meet the specifications and are inserted within the insertion period. Here, the medals guided to the medal discharge port 608a are discharged to the receiving tray 608. When a player inserts medals in excess of the specified insertion number, which is the number of medals required to start one game, the medals that exceed the specified insertion number are electrically stored (hereinafter simply referred to as credits) inside the slot machine 600 up to a predetermined number (for example, 50 medals). The above one game will be described in detail later.

[0166] Also, here, the specified number of coins to be inserted is set to "3" or "2." If the number of medals required to play one game can be selected from multiple specified numbers of coins, the largest of the multiple specified numbers of coins to be inserted is called the maximum specified number of coins to be inserted, and the smallest is called the minimum specified number of coins to be inserted. If the specified number of coins can be selected between 1 and 3, the maximum specified number of coins to be inserted is "3" and the minimum specified number of coins is "1."

[0167] The bet switch 626 is a push button switch that inserts (bet) a specified number of medals from among the credited medals. When the bet switch 626 is pressed when more than the specified number of medals have been credited, one game can be started and the number of credited medals is reduced by the specified number.

[0168] The start switch 628 located on the left side of the operation unit installation stand 622 is composed of a lever that can detect a tilt operation, and detects the start operation of one game by the player. The start switch 628 can also be composed of a button switch that can detect a push operation.

[0169] A colorless and transparent pattern display window 636 made of a glass plate or a transparent resin plate is provided at the approximate center of the lower part of the upper front door 604, and a reel unit 634 is provided at a position corresponding to the pattern display window 636 in the housing 602. As shown in the pattern arrangement of the reels in FIG. 23, the reel unit 634 has three rotating reels (left reel 634a, center reel 634b, right reel 634c) in which a plurality of types of patterns are arranged in each of 21 equal areas, and each reel is independently rotatably provided, and a player can visually recognize the left reel 634a, center reel 634b, and right reel 634c through the pattern display window 636. The reel unit 634 starts rotating the left reel 634a, center reel 634b, and right reel 634c when the start switch 628 is operated.

[0170] The stop switch 630 located in the center of the operation unit installation stand 622 is a button switch that is provided corresponding to each of the left reel 634a, the center reel 634b, and the right reel 634c and can detect the pressing operation by the player, and detects the player's stopping operation to stop each of the left reel 634a, the center reel 634b, and the right reel 634c. Note that the three button switches in the stop switch 630 are specifically called stop button switches, and are referred to as stop button switch 630a, stop button switch 630b, and stop button switch 630c from the left according to their positions.

[0171] The effect switch 632 is composed of a push button switch and a jog dial switch rotatably arranged around it, and detects the pressing operation and rotation operation of the player. The effect switch 632 is mainly used during the effect, and the effect mode can be changed depending on the operation of the player.

[0172] A liquid crystal display unit 638 that displays various images associated with the performance is provided approximately at the center of the upper part of the front upper door 604. In addition, performance lamps 642, for example, composed of high-brightness light-emitting diodes (LEDs), are provided at the upper part, left and right of the front upper door 604. In addition, a performance prop device 660 consisting of a drive device is provided between the pattern display window 636 and the operation unit installation stand 622.

[0173] 22, speakers 640 for providing auditory effects such as sound effects and musical sounds are provided on the left and right of the liquid crystal display unit 638 on the rear surface of the upper front door 604 and on the left and right of the inner surface of the rear surface of the lower front door 606. Furthermore, below the reel unit 634 in the housing 602, a medal payout device (medal hopper) 764 for paying out medals from the medal discharge port 608a is provided. The medal payout device 764 includes a medal storage section 764a for storing medals, a payout control section 764b for discharging the medals stored in the medal storage section 764a from the medal discharge port 608a, and a paid-out medal detection section 764c for detecting medals discharged from the medal discharge port 608a. Specifically, the payout control unit 764b is rotatably supported on the exterior of the main body of the payout control unit 764b and comprises a disk (not shown) with a plurality of medal insertion holes arranged in a circumferential direction, into which medals dropped from the medal storage unit 764a are inserted one by one from above, and a disk motor (not shown) that rotates the disk. By rotating the disk, medals inserted in the medal insertion holes are ejected one by one to the outside through an extrusion mechanism, and the next medal is inserted sequentially into the medal insertion hole vacated by the ejection, thereby continuously ejecting medals one by one.

[0174] 21 and 22, reel backlights 644 (see FIG. 24) are provided inside each of the rotating reels 634a, 634b, 634c to individually and independently illuminate the upper, middle, and lower patterns of each of the rotating reels 634a, 634b, 634c that correspond to the pattern display window 636 (which may be the target of the activated line that is the target of the payout) among the patterns on the left reel 634a, center reel 634b, and right reel 634c from the back side. Also, a reel upper light 646 is provided at the top of the back side of the pattern display window 636 to directly illuminate the front of all of the left reel 634a, center reel 634b, and right reel 634c.

[0175] 21, a main credit display section 652 and a main payout display section 654 are provided on the substantially horizontal surface of a step section 622a provided between the symbol display window 636 and the stop switch 630 in the operation unit installation stand 622. A sub-credit display section 656 and a sub-payout display section 658 are provided between the symbol display window 636 and the operation unit installation stand 622. The main credit display section 652 and the sub-credit display section 656 display the number of credits, and the main payout display section 654 and the sub-payout display section 658 display the number of medals to be paid out. The sub-credit display section 656 and the sub-payout display section 658 can also display various numerical values ​​associated with effects.

[0176] In addition, a power switch 648 is provided at an arbitrary position inside the housing 602. The power switch 648 is configured with a switch capable of detecting a pressing operation, such as a rocker switch, and is operated by an administrator who manages the slot machine 600, and is used to switch between two states, a power-off state and a power-on state.

[0177] In this embodiment, the one game refers to a game played from when a medal is inserted through the medal insertion section 624, when a credited medal is inserted through the operation of the bet switch 626, or when a medal is automatically inserted based on a replay role being displayed on an active line, until when the player operates the start switch 628 to control the rotation of the multiple reels 634a, 634b, 634c and execute a winning role lottery, and when the player operates the multiple stop button switches 630a, 630b, 630c, the reels 634a, 634b, 634c corresponding to the operated stop button switches 630a, 630b, 630c are controlled to stop, and when a winning role that can be awarded with a medal is won, the medal is paid out. In addition, if a player does not win a winning combination that can receive a medal payout, or if a player wins a combination but does not win a prize, one game ends when all of the rotating reels 634a, 634b, and 634c have stopped. However, the start of one game may be interpreted as the player operating the start switch 628 instead of the insertion of a medal or the winning of a replay combination. The number of times such one game is repeated is defined as the number of games.

[0178] (Electrical configuration of the slot machine 600) FIG. 24 is a block diagram showing a schematic electrical configuration of the slot machine 600. As shown in FIG. 24, the slot machine 600 is mainly controlled by a control board. Here, as an example of a control board, a main control board 700 and a sub-control board 702, which share the functions of the control board, are described. For example, among programs related to the progress of a game, particularly important processes such as drawing a winning combination for a game and winning the winning combination are executed by the main control board 700, and other processes such as those related to performance are executed by the sub-control board 702. Also, as shown in FIG. 24, the transmission of electrical signals between the main control board 700 and the sub-control board 702 is limited to only one direction from the main control board 700 to the sub-control board 702 from the viewpoint of preventing fraud, etc. However, if there is no such restriction, two-way electrical communication is technically possible.

[0179] (Main control board 700) The main control board 700 has various semiconductor integrated circuits including a main CPU 700a which is a central processing unit, a main ROM 700b in which programs and the like are stored, a main RAM 700c which functions as a work area, and the like, and generally controls the entire slot machine 600. However, a backup power supply (not shown) is connected to the main RAM 700c, and even if the power is cut off, data is not erased and is retained unless settings are changed and initialization processing of the main RAM 700c is executed.

[0180] The main control board 700 also has functional sections such as an initialization means 800, a betting means 802, a winning role selection means 804, a reel control means 806, a judgment means 808, a payout control means 810, a state transition means 812, a command determination means 814, and a command transmission means 816, which function by the main CPU 700a working in cooperation with the main RAM 700c based on the program stored in the main ROM 700b.

[0181] The initialization means 800 executes initialization processing in the main control board 700. The betting means 802 bets medals to be used in a game. Here, the bet includes any of the following: inserting medals credited through the operation of the bet switch 626, inserting medals through the medal inserting section 624, and automatically inserting medals based on the display of a replay role on an active line. The winning combination drawing means 804 determines, by a winning combination drawing, any of a plurality of winning combinations including a small combination, a replay combination, and a bonus combination, and a losing combination, based on the bet of medals and the operation of the start switch 628.

[0182] The reel control means 806 controls the rotation of the multiple rotating reels 634a, 634b, and 634c in response to the operation of the start switch 628, and controls the stop of the rotating reels 634a, 634b, and 634c corresponding to the operated stop button switches 630a, 630b, and 630c in response to the operation of the multiple stop button switches 630a, 630b, and 630c, respectively. In addition, the reel control means 806 may extend the time from enabling the operation of the stop switch 630 in the previous game to enabling the operation of the stop switch 630 by the player to display the lottery result of the winning combination lottery (disabled by the completion of the operation of the stop switch 630 in the previous game) to a specified time in response to the operation of the start switch 628, and during that time, perform a reel effect (freeze effect) in which the rotating reels 634a, 634b, and 634c are rotated in various ways. The reel effect can be achieved by not activating an arbitrary switch that should normally be activated for a predetermined period of time, by suspending a process that should normally be executed for a predetermined period of time, or by not transmitting or receiving a signal from an arbitrary switch that should normally be transmitted or received for a predetermined period of time.

[0183] The determination means 808 determines whether or not a symbol combination corresponding to a winning role determined by the winning role lottery is displayed on an active line. Here, the display of a symbol combination corresponding to a winning role determined by the winning role lottery on an active line may simply be referred to as winning. The payout control means 810 pays out medals in the number corresponding to the winning role based on the display of a symbol combination corresponding to a winning role determined by the winning role lottery on an active line (winning). The state transition means 812 transitions the game state based on the winning of a bonus role or winning.

[0184] The command determination means 814 sequentially determines commands related to the game in accordance with the operations of the betting means 802, the winning combination selection means 804, the reel control means 806, the determination means 808, the payout control means 810, the state transition means 812, etc. The command transmission means 816 sequentially transmits the commands determined by the command determination means 814 to the sub-control board 702.

[0185] The main control board 700 receives various detection signals from the inserted medal detection unit 624b, the bet switch 626, the start switch 628, and the stop switch 630, and based on the received detection signals, the bet means 802, the winning combination selection means 804, the reel control means 806, and the determination means 808 execute the various processes described above. In addition, the main control board 700 is connected to a main credit display unit 652 and a main payout display unit 654, and a payout control means 810 controls the display of the number of medal credits and the number of medals paid out on both display units 652, 654.

[0186] A reel drive control unit 758 is also connected to the main control board 700. This reel drive control unit 758 drives a stepping motor 762 based on rotation start signals for the respective rotating reels 634a, 634b, and 634c transmitted from the reel control means 806 in response to an operation signal from the start switch 628, and stops driving the stepping motor 762 based on stop signals for the left reel 634a, center reel 634b, and right reel 634c and detection signals from the rotation position detection circuit 760 transmitted from the reel control means 806 in response to an operation signal from the stop switch 630.

[0187] Furthermore, a medal payout device 764 is connected to the main control board 700. A detection signal from a payout medal detection unit 764c is input to the main control board 700, and payout control means 810 controls the discharge of medals from a payout control unit 764b while counting the number of medals paid out in response to the detection signal.

[0188] The main control board 700 is also provided with a random number generator 700d. The random number generator 700d sequentially increments a count value, loops (0 to 65535) within a predetermined total number (for example, 65536), and extracts a count value at a predetermined time point to generate (obtain) a random number. The random number (hereinafter, referred to as a winning combination lottery random number) generated by the random number generator 700d of the main control board 700 is used to determine a gaming profit to be given to a player, for example, to allow the winning combination lottery means 804 to execute a winning combination lottery.

[0189] (Sub-control board 702) Similarly to the main control board 700, the sub-control board 702 has various semiconductor integrated circuits including a sub-CPU 702a which is a central processing unit, a sub-ROM 702b which stores programs and the like, and a sub-RAM 702c which functions as a work area, and controls performances in particular based on commands from the main control board 700. Similarly to the main RAM 700c, the sub-RAM 702c is also connected to a backup power supply (not shown), so that data is not erased and is retained even if the power supply is cut off. Similarly to the main control board 700, the sub-control board 702 is also provided with a random number generator 702d, and the random numbers generated by the random number generator 702d (hereinafter referred to as performance selection random numbers) are mainly used to determine the mode of performance.

[0190] In addition, the sub-control board 702 has functional units such as an initialization determination means 830, a command receiving means 832, and a performance control means 834 that function in cooperation with the sub-RAM 702c based on the program stored in the sub-ROM 702b by the sub-CPU 702a.

[0191] The initialization determination means 830 executes initialization processing in the sub-control board 702. The command receiving means 832 receives commands from other control boards such as the main control board 700, and processes the commands. The performance control means 834 receives a detection signal from the performance switch 632, and determines the performance of the game performed by each device of the liquid crystal display unit 638, the speaker 640, and the performance lamp 642 based on the winning combination command. Specifically, the performance control means 834 determines image data to be displayed on the liquid crystal display unit 638, and illumination data for the performance through illumination devices such as the performance lamp 642, the reel backlight 644, the reel upper light 646, the sub-credit display unit 656, and the sub-payout display unit 658, and determines audio data constituting the sound to be output from the speaker 640. Then, the performance control means 834 executes the determined performance of the game.

[0192] The effects include effects executed by the main control board 700 such as the reel effects described above, and effects executed by the sub-control board 702. The effects executed by the sub-control board 702 are visual and audible expression means provided through the liquid crystal display unit 638, the speaker 640, the performance lamps 642, the reel backlights 644, the reel upper lights 646, the sub-credit display unit 656, the sub-payout display unit 658, etc. as the game progresses, and can give the game a story-like quality or suggest the results of the lottery for the winning combination with more dynamic images. In such effects, for example, effects suggesting the winning of the bonus game can be performed over multiple games, thereby increasing the player's sense of expectation. In addition, even if the player does not win any winning combination, the effects can be used to give the player a sense of expectation of a high payout, as if he or she had won, and the player can be prevented from getting bored.

[0193] Here, the performance control means 834 functions as the performance decision means 332 and the performance execution means 334 described above, and the performance lamp 642 functions as the performance lighting device 204. Also, the sub-CPU 702a functions as the sub-CPU 330a described above, and the speaker 640 functions as the speaker 206b described above. Also, although not described here, the sub-control board 702 includes an amplifier having the same function as the amplifier 206a described above, and an RTC having the same function as the RTC 348 described above. [Explanation of symbols]

[0194] 206 Music Output Device 206a Amplifier (slave device) 330a Sub-CPU (CPU, master device) 348 RTC (slave device)

Claims

1. A CPU, An RTC element; Equipped with The CPU includes: acquiring time information from the RTC element at a first timing; The time indicated by the time information acquired at the first timing is set as an initial value, and thereafter, the time is updated; acquiring time information from the RTC element at a second timing that is later than the first timing; comparing a first time, which is the time updated by the CPU, with a second time indicated by the time information acquired at the second timing; When the first time and the second time are different, the first time is set in the RTC element.

2. The CPU includes: When a time difference between the first time and the second time is equal to or greater than a predetermined time difference, the RTC element is set to the first time; 2. The gaming machine according to claim 1, wherein the first time is not set in the RTC element when the time difference between the first time and the second time is less than the predetermined time difference.

Images