Gaming Machines

Abstract

To provide a game machine capable of suitably accelerating a circulating body.SOLUTION: A stepping motor 442 includes: a rotor 451 disposed at the center; and a stator 452 including first to fourth poles 453-456 disposed around the rotor 451. The rotor 451 is composed of a forward rotor 451a polarized to an N pole, and a back-side rotor 451b polarized to an S pole, and is attached to a rotating shaft while being relatively shifted by 1 / 2 pitch such that a gear tooth provided around the back-side rotor 451b is positioned between gear teeth provided around the forward rotor 451a. Excitation phases of respective poles 453-456 are changed successively, and hence the rotor 451 is rotated. In this case, when starting acceleration, one phase excitation is performed to the stepping motor 442 and an excitation period of one phase excitation during the acceleration period is shorter than an excitation period of immediate bi-phase excitation.SELECTED DRAWING: Figure 89

Description

[Technical Field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Pachinko machines, slot machines, and the like are known as types of gaming machines. In these gaming machines, the progress of the game is controlled by various controls executed by a control device. Furthermore, when the various controls are executed by the control device, numerical information is used.

[0003] For example, a configuration is known in which an internal lottery is held based on the fulfillment of predetermined lottery conditions, and a bonus is awarded to a player based on the result of the internal lottery. In this internal lottery, when the predetermined lottery conditions are fulfilled, numerical information is acquired from an update means that updates numerical information for the lottery, and it is determined whether the acquired numerical information corresponds to winning information (see, for example, Patent Document 1). Also known is a configuration in which numerical information is acquired based on the fulfillment of predetermined acquisition conditions, and a specific effect or notification is performed based on the result of the internal lottery held using the numerical information. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-261415 Summary of the Invention [Problem to be solved by the invention]

[0005] Here, in gaming machines such as those exemplified above, it is necessary to obtain numerical information appropriately when drawing lots, and there is still room for improvement in this regard.

[0006] The present invention has been made in consideration of the circumstances exemplified above, and aims to provide a gaming machine that can suitably acquire numerical information during a lottery. [Means for solving the problem]

[0007] In order to solve the above problem, the invention described in claim 1 comprises: a numerical value updating means for updating numerical information; a storage execution means for storing the numerical information updated by the numerical value update means in an acquisition storage means when a first trigger occurs; a control means for executing a special process using the numerical information stored in the acquisition storage means when a second trigger occurs; Equipped with In the gaming machine, The storage and execution means an information setting means for setting acquired information when the first trigger occurs and the acquisition storage means stores the numerical information; a rewriting means for rewriting the numerical information stored in the acquisition storage means to the numerical information updated by the numerical value update means at that time when the first trigger occurs again in a situation where the acquired information has already been set; Equipped with The control means a determination means for determining whether the second trigger has occurred each time a monitoring timing occurs; a control execution means for executing the special process when the determination means determines that the second trigger has occurred, with at least one condition being that the acquired information has been set; Equipped with The gaming machine is provided with a means for executing a predetermined control that can grasp a situation in which the second trigger occurs but the acquired information is not set when the situation occurs a predetermined number of times, Even when the rewriting means rewrites the numerical information, the information setting means executes control to set the acquired information. It is characterized by: [Effects of the Invention]

[0008] According to the present invention, it is possible to suitably acquire numerical information at the time of a lottery. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a front view of a slot machine according to a first embodiment. [Figure 2] FIG. 10 is a diagram showing the arrangement of symbols on each reel. [Figure 3] 10 is an explanatory diagram showing the relationship between the symbols visible through the display window and the combination lines. FIG. [Figure 4] FIG. 10 is an explanatory diagram showing the relationship between winning modes and the benefits to be awarded. [Figure 5] FIG. 2 is a block diagram showing the electrical configuration of the slot machine. [Figure 6] FIG. 1 is a block diagram illustrating a hard random number circuit. [Figure 7] 4 is a flowchart showing a main process executed by the control IC. [Figure 8] 10 is a flowchart showing a timer interrupt process executed by the control IC. [Figure 9] 10 is a flowchart showing a start command setting process executed by the control IC. [Figure 10] 4 is a flowchart showing normal processing executed by the control IC. [Figure 11] 10 is a flowchart showing a lottery process executed by the control IC. [Figure 12] FIG. 10 is a diagram showing an example of a lottery table for a normal mode. [Figure 13] FIG. 10 is an explanatory diagram for explaining the relationship between the stopping order of the reels and the winning patterns that are achieved when the lottery table for the normal mode is selected. [Figure 14] FIG. 10 is a diagram showing an example of a lottery table for the first RT mode. [Figure 15] FIG. 10 is an explanatory diagram for explaining the relationship between the stop order of the reels and the winning patterns that are achieved when the lottery table for the first RT mode is selected. [Figure 16] FIG. 10 is a diagram showing an example of a lottery table for the second RT mode. [Figure 17] FIG. 10 is an explanatory diagram for explaining the relationship between the stop order of the reels and the winning patterns that are achieved when the lottery table for the second RT mode is selected. [Figure 18] 10 is a flowchart showing the response processing executed by the control IC when a game ends. [Figure 19] 10 is a flowchart showing a management operation executed by the control circuit. [Figure 20] 10 is a time chart showing the timing at which the control IC of the first slot machine for comparison acquires a random number. [Figure 21] 10 is a time chart showing the timing at which the control IC of a second slot machine for comparison acquires a random number. [Figure 22] 10 is a time chart showing the timing at which a control IC of a slot machine equipped with a latched status acquires a random number. [Figure 23] This is a time chart showing that the control IC of a slot machine equipped with a latched status does not acquire a random number when noise is mixed into the control side CPU. [Figure 24] FIG. 10 is a block diagram showing the configuration of a main control board in the second embodiment. [Figure 25] 10 is a flowchart showing a start command setting process executed by the control IC. [Figure 26] 10 is a flowchart showing an error handling process executed by the control IC. [Figure 27] 10 is a flowchart showing a management operation executed by a control side CPU. [Figure 28] 10 is a flowchart showing a random number acquisition process executed by the control IC. [Figure 29] 10 is a time chart showing the timing at which a control IC of a slot machine equipped with a confirmation command flag acquires a random number. [Figure 30] 10 is a time chart showing the timing at which a control IC of a slot machine equipped with a confirmation command flag transmits an abnormality signal. [Figure 31] 10(a) is a block diagram showing a connection between a control IC and a random number counter in another form of the second embodiment, and FIG. 10(b) is a flowchart showing a random number acquisition process executed by the control IC. [Figure 32] FIG. 11 is a block diagram showing the configuration of a main control board in the third embodiment. [Figure 33] 10 is a flowchart showing a start command setting process executed by the control IC. [Figure 34] 4 is a flowchart showing normal processing executed by the control IC. [Figure 35] 10 is a flowchart showing a management operation executed by a control side CPU. [Figure 36]10 is a time chart showing the timing at which a control IC of a slot machine that uses a start enable signal acquires a random number. [Figure 37] 10 is a time chart showing the timing at which an abnormality notification process is executed. [Figure 38] FIG. 13 is an explanatory diagram showing the relationship between winning modes and the benefits awarded in the fourth embodiment. [Figure 39] FIG. 2 is a block diagram for explaining the electrical configuration of a main control board. [Figure 40] 6 is a time chart showing timings at which the first management circuit and the second management circuit transmit latch signals. [Figure 41] 10 is a flowchart showing a start command setting process executed by the control IC. [Figure 42] 4 is a flowchart showing normal processing executed by the control IC. [Figure 43] 10 is a flowchart showing a lottery process executed by the control IC. [Figure 44] FIG. 10 is a diagram showing an example of a lottery table for a normal mode. [Figure 45] FIG. 10 is an explanatory diagram for explaining the relationship between the stopping order of the reels and the winning patterns that are achieved when the lottery table for the normal mode is selected. [Figure 46] 10 is a flowchart showing the response processing executed by the control IC when a game ends. [Figure 47] FIG. 10 is an explanatory diagram for explaining the transition of the game state. [Figure 48] 10 is a flowchart showing an AT process executed by the control IC. [Figure 49] 10 is a flowchart showing a BB process executed by the control IC. [Figure 50] 10 is a flowchart showing a stop order notification control process executed by a sub-side MPU. [Figure 51] 10 is a time chart showing the timing at which the control IC acquires a first random number and the timing at which the control IC acquires a second random number. [Figure 52]13 is a flowchart showing normal processing executed by a control IC in another form of the fourth embodiment. [Figure 53] 13(a) to 13(c) are explanatory diagrams for explaining random numbers for lottery in the fifth embodiment. [Figure 54] 4 is a flowchart showing normal processing executed by the control IC. [Figure 55] 10 is a flowchart showing a lottery process executed by the control IC. [Figure 56] FIG. 10A is a diagram showing an example of a lottery table for normal mode, and FIG. 10B is a table showing part of the numerical information set in each random number group. [Figure 57] 10 is a flowchart showing an AT process executed by the control IC. [Figure 58] 10A is a flowchart showing the additional lottery process executed by the control IC, and FIG. 10B is a flowchart showing the continuation lottery process executed by the control IC. [Figure 59] 10 is a flowchart showing a BB process executed by the control IC. [Figure 60] FIG. 13 is a block diagram for explaining the configuration of a hard random number circuit according to a sixth embodiment. [Figure 61] FIG. 13 is a block diagram for explaining the configuration of a hard random number circuit according to the seventh embodiment. [Figure 62] 10 is a flowchart for explaining a management operation in a control side CPU. [Figure 63] 10 is a flowchart for explaining AT processing in the control IC. [Figure 64] FIG. 13 is a front view showing the configuration of a game board of a pachinko machine in the eighth embodiment. [Figure 65] A vertical cross-sectional view of the recovery passage for the operating port to explain the recovery passage for the operating port and the winning detection sensor for the operating port. [Figure 66] FIG. 2 is a block diagram for explaining the electrical configuration of a hard random number circuit. [Figure 67]This is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. [Figure 68] 10 is a flowchart showing a timer interrupt process in the control IC. [Figure 69] 10 is a flowchart showing the special diagram special power control processing in the control IC. [Figure 70] FIG. 10A is a block diagram showing the configuration of a RAM, and FIG. 10B is a flowchart showing the process of acquiring hold information in a control IC. [Figure 71] 10 is a flowchart showing a random number acquisition process in the control IC. [Figure 72] 10 is a flowchart showing an error handling process in the control IC. [Figure 73] This is a time chart showing the timing at which the control IC obtains the jackpot random number. [Figure 74] 10 is a time chart showing the timing at which a control IC transmits a latch instruction signal. [Figure 75] FIG. 13 is a block diagram showing the electrical configuration of a main control board in the ninth embodiment. [Figure 76] 4 is a flowchart showing a main process executed by the control IC. [Figure 77] 4 is a flowchart showing normal processing executed by the control IC. [Figure 78] 10 is a flowchart showing a second reel control process executed by the control IC. [Figure 79] 10 is a time chart showing the timing at which the control IC acquires a second random number. [Figure 80] 20 is a flowchart showing a second reel control process executed by the control IC in the tenth embodiment. [Figure 81] 23 is a flowchart showing a second reel control process executed by the control IC in the eleventh embodiment. [Figure 82] 23 is a flowchart showing normal processing executed by a control IC in the twelfth embodiment. [Figure 83]23 is a flowchart showing a second reel control process executed by the control IC in the thirteenth embodiment. [Figure 84] 10 is a flowchart showing a medium provision process executed by the control IC. [Figure 85] 23 is a flowchart showing a lottery process executed by the control IC in the fourteenth embodiment. [Figure 86] 10A is a flowchart showing the effect lottery process executed by the control IC, FIG. 10B is a diagram showing an effect selection table for cherries, and FIG. 10C is a diagram showing an effect selection table for watermelons. [Figure 87] 10 is a flowchart showing an AT process executed by the control IC. [Figure 88] FIG. 23 is an assembled perspective view of the left reel in the fifteenth embodiment. [Figure 89] FIG. 2A is a connection diagram showing a drive system of a stepping motor, and FIG. 2B is a diagram showing the drive characteristics of the stepping motor. [Figure 90] FIG. 4 is an explanatory diagram for explaining the contents of an excitation sequence table. [Figure 91] FIG. 10 is an explanatory diagram for explaining required driving characteristics. [Figure 92] FIG. 10 is an explanatory diagram illustrating an example of an acceleration table in a conventional slot machine. [Figure 93] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern A. [Figure 94] FIG. 94 is an explanatory diagram for explaining the change over time in the number of steps for one interrupt when the acceleration table of FIG. 92 and the acceleration table of FIG. 93 are applied. [Figure 95] 10 is a flowchart showing a rotation start process executed by the main MPU. [Figure 96] 10 is a flowchart showing a stepping motor control process executed by a main MPU. [Figure 97] 4 is a flowchart showing a motor control process executed by a main MPU. [Figure 98]95A to 97B show the results of measurements, taken by taking images and analyzing the images, of the amount of fluctuation in the position of a mark attached at a predetermined location on the surface of the left reel that accompanies the execution of the acceleration process when the control process shown in FIGS. 95 to 97B is performed using the excitation sequence table shown in FIG. 90 and the acceleration table shown in FIG. 93 for a reel unit created according to Example 1. [Figure 99] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern B. [Figure 100] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern C. [Figure 101] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern D. [Figure 102] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern E. [Figure 103] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern F. [Figure 104] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern G. [Figure 105] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern H. [Figure 106] FIG. 10 is an explanatory diagram for explaining an acceleration table for acceleration pattern I. [Figure 107] FIG. 10 is an explanatory diagram for explaining an acceleration table of acceleration pattern J. [Figure 108] FIG. 10 is an explanatory diagram for explaining an acceleration table of acceleration pattern K. [Figure 109] FIG. 10 is an explanatory diagram for explaining an acceleration table of acceleration pattern L. [Figure 110] FIG. 10 is an explanatory diagram for explaining an acceleration table of acceleration pattern M. [Figure 111] FIG. 10 is an explanatory diagram for explaining an acceleration table of acceleration pattern N. [Figure 112] FIG. 1 is a diagram showing the results of various evaluations performed on Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0010] First Embodiment A first embodiment of the present invention, in which the present invention is applied to a slot machine, which is a type of gaming machine, will be described in detail below with reference to the drawings. Figure 1 is a front view of a slot machine 10.

[0011] The slot machine 10 includes a housing 11 that forms its outer shell. The housing 11 is formed by fastening a number of wooden panels together to form a box-like shape that is open to the front. A front door 12 is attached to the front side of the housing 11. The front door 12 is supported by the housing 11 with its left side as a pivot axis so that the interior space of the housing 11 can be opened and closed. The front door 12 is locked so that it cannot be opened by a locking device provided on the back side of the front door, and this locked state can be released by unlocking the key cylinder 14 with a specified key.

[0012] A game panel 20 that notifies the player of the game status is provided near the upper center of the front door 12. Three vertically long display windows 21L, 21M, and 21R are formed side by side on the game panel 20. The display windows 21L, 21M, and 21R are made of a transparent or translucent material, and the interior of the slot machine 10 can be seen through each of the display windows 21L, 21M, and 21R.

[0013] The housing 11 is provided with a reel unit 31. The reel unit 31 includes a left reel 32L, a center reel 32M, and a right reel 32R, each of which is cylindrical. Each of the reels 32L, 32M, and 32R is rotatably supported so that its central axis coincides with the axis of rotation of the reel. The axes of rotation of the reels 32L, 32M, and 32R are arranged on the same axis extending substantially horizontally, and each of the reels 32L, 32M, and 32R corresponds one-to-one to each of the display windows 21L, 21M, and 21R. Therefore, a portion of the surface of each of the reels 32L, 32M, and 32R is visible through the corresponding display window 21L, 21M, and 21R. Furthermore, when the reels 32L, 32M, and 32R rotate forward, the surfaces of the reels 32L, 32M, and 32R are projected through the display windows 21L, 21M, and 21R as if they are moving from top to bottom.

[0014] Each of these reels 32L, 32M, and 32R is connected to a stepping motor (not shown), and the reels 32L, 32M, and 32R can be rotated individually, i.e., independently of each other, by driving each stepping motor.

[0015] Various operation units that allow the player to start and stop the game using each of the reels 32L, 32M, and 32R are concentrated in an operation bulge 25 that is provided below the game panel 20 and bulges out in front of the slot machine 10 from the game panel 20. The various operation units concentrated in the operation bulge 25 will be described in detail below.

[0016] A start lever 41 that is operated to start the rotation of each of the reels 32L, 32M, and 32R is provided on the front left side of the operation bulge 25. When this start lever 41 is operated after medals have been bet, each of the reels 32L, 32M, and 32R starts to rotate simultaneously.

[0017] Stop buttons 42, 43, and 44 are provided on the front of the operation bulge 25 to the right of the start lever 41. These stop buttons 42, 43, and 44 are operated to individually stop the spinning reels 32L, 32M, and 32R. Each stop button 42, 43, and 44 is located directly below the display window 21L, 21M, and 21R corresponding to the reel 32L, 32M, and 32R to be stopped. Each stop button 42, 43, and 44 is ready to stop the left reel 32L after a predetermined time has elapsed since the reel started spinning.

[0018] One game (or game session) corresponds to the period from when the rotation of each reel 32L, 32M, 32R begins based on the operation of the start lever 41, when the rotation of each reel 32L, 32M, 32R stops based on the operation of each stop button 42, 43, 44, until the execution of various processes such as the awarding of game media and management of the game status is completed.

[0019] A medal insertion port 45 for inserting medals is provided on the right side of the upper surface of the operation bulge 25. Medals inserted through the medal insertion port 45 are guided by a selector 52 provided on the back surface of the front door 12 to a hopper device 53 inside the housing 11 if medals can be inserted, or to a medal receiving tray 59 from a medal discharge port 58 provided at the bottom front of the front door 12 if medals cannot be inserted. Note that the hopper device 53 has the function of dispensing medals stored in the storage tank through the medal discharge port 58 to the medal receiving tray 59 if a winning combination corresponding to the award of a medal is achieved on an active line.

[0020] A return button 46 is provided on the front surface of the operation bulge 25 below the medal insertion slot 45, and is pressed when medals inserted into the medal insertion slot 45 become stuck in the selector 52. Also, on the left side of the top surface of the operation bulge 25, there are provided a first credit insertion button 47 for inserting the maximum number of virtual medals that can be bet at one time, which are stored in the RAM 144 of the main control device 140 (described later), a second credit insertion button 48 for inserting two virtual medals at a time, and a third credit insertion button 49 for inserting one virtual medal at a time. Note that in this slot machine 10, the concept of game media includes medals and virtual medals.

[0021] A settlement button 51 is provided on the front of the operation bulge 25 to the left of the start lever 41. This slot machine 10 has a credit function that stores surplus inserted medals up to a predetermined maximum value (equivalent to 50 medals) and medals paid out when a prize is won as virtual medals in RAM 144 of the main control device 140 (described later). When the settlement button 51 is operated while virtual medals are stored and stored, the virtual medals are paid out from the medal outlet 58 as real medals.

[0022] A power supply unit 54 is provided inside the cabinet 11 to the left of the hopper unit 53. The power supply unit 54 includes a power switch that is operated when powering on or off, a reset button for resetting various states of the slot machine 10, and a setting key insertion hole that is operated to change the setting state of the slot machine 10 within the range of "Setting 1" to "Setting 6."

[0023] <The symbols on each reel 32L, 32M, and 32R> Next, the symbols on the reels 32L, 32M, and 32R will be described.

[0024] 2 shows the arrangement of symbols on the left reel 32L, center reel 32M, and right reel 32R. As shown in the figure, 21 symbols are arranged in a row on each of the reels 32L, 32M, and 32R. Numbers ranging from 0 to 20 are assigned to the reels 32L, 32M, and 32R, respectively. However, these numbers are used by the main control device 140 to identify the symbols visible through the display windows 21L, 21M, and 21R, and are not actually assigned to the reels 32L, 32M, and 32R. However, these numbers will be used in the following explanation.

[0025] There are seven types of symbols: "Bell" symbol (for example, the 20th symbol on the left reel 32L), "Replay" symbol (for example, the 19th symbol on the left reel 32L), "Watermelon" symbol (for example, the 18th symbol on the left reel 32L), "Red 7" symbol (for example, the 15th symbol on the left reel 32L), "BAR" symbol (for example, the 10th symbol on the left reel 32L), "Cherry" symbol (for example, the 9th symbol on the left reel 32L), and "White 7" symbol (for example, the 5th symbol on the left reel 32L). The number and arrangement order of each symbol is completely different on each of the reels 32L, 32M, and 32R.

[0026] 3 is a front view of the display window portions 21L, 21M, and 21R. Each display window portion 21L, 21M, and 21R is formed so that only three of the 21 symbols on the corresponding reel 32L, 32M, and 32R are visible in their entirety. Therefore, when each reel 32L, 32M, and 32R is stopped, 3 x 3 = 9 symbols are visible through the display window portion 21L, 21M, and 21R.

[0027] In the slot machine 10, one main line ML is set so as to connect positions where symbols on each of the reels 32L, 32M, and 32R are visible. The main line ML is a line connecting the middle symbols on the left reel 32L, the middle symbols on the middle reel 32M, and the middle symbols on the right reel 32R. When a predetermined number of gaming media have been bet, the reels 32L, 32M, and 32R start to rotate, and a winning combination is achieved on the main line ML, at least one of the following is awarded: a benefit in the form of gaming media, a benefit in the form of a replay, or a transition to a gaming state.

[0028] In other words, in the slot machine 10, only one main line ML is set as a line on which a win can be achieved. The main line ML is set as a line extending in a straight line. Therefore, even if a winning combination of symbols is achieved on the following lines, such as the subline S1 connecting the upper symbol on the left reel 32L, the middle symbol on the middle reel 32M, and the lower symbol on the right reel 32R, the subline S2 connecting the upper symbol on the left reel 32L, the upper symbol on the middle reel 32M, and the upper symbol on the right reel 32R, the subline S3 connecting the lower symbol on the left reel 32L, the lower symbol on the middle reel 32M, and the lower symbol on the right reel 32R, and the subline S4 connecting the lower symbol on the left reel 32L, the middle symbol on the middle reel 32M, and the upper symbol on the right reel 32R, no winning combination will be achieved.

[0029] The relationship between the winning symbol combination and the benefit that will be awarded when the winning symbol is obtained will be explained below with reference to Figure 4. Figure 4 is an explanatory diagram for explaining the relationship between the winning symbol combination and the benefit that will be awarded when the winning symbol is obtained.

[0030] The minor winning combinations that award gaming media include the first supplementary winning combination, the second supplementary winning combination, the third supplementary winning combination, the bell winning combination, the watermelon winning combination, and the cherry winning combination. Specifically, if the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the center reel 32M is a "replay" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the first supplementary winning combination will occur. Also, if the stopped symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopped symbol on the center reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the second supplementary winning combination will occur. Furthermore, if the stopped symbol on the left reel 32L on the main line ML is a "replay" symbol, the stopped symbol on the center reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, the third supplementary win will occur. The number of game media to be awarded in the case of any of the first to third supplementary wins will be "1" in a game state other than the BB state described below. On the other hand, the first to third supplementary wins are excluded from the targets for being achieved in the BB state described below.

[0031] When the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the center reel 32M is a "bell" symbol, and the stopped symbol on the right reel 32R is a "bell" symbol, a bell win occurs. The number of game media to be awarded when a bell win occurs is "9" if the game state is other than the BB state described below, and "8" if the game state is the BB state described below.

[0032] A watermelon win occurs when the stopped symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopped symbol on the middle reel 32M is either a "watermelon" symbol or a "cherry" symbol, and the stopped symbol on the right reel 32R is either a "watermelon" symbol or a "white 7" symbol. When a watermelon win occurs, the number of game media to be awarded is "7" if the game state is other than the BB state, and "8" if the game state is the BB state described below.

[0033] When the stopped symbol on the left reel 32L on the main line ML becomes a "cherry" symbol, a cherry win will occur regardless of the stopped symbol on the middle reel 32M or the stopped symbol on the right reel 32R. The number of game media to be awarded when a cherry win occurs will be "2" in game states other than the BB state. On the other hand, a cherry win is excluded from the possible wins in the BB state.

[0034] The winning combinations that grant a replay privilege, which allows the player to play the next game without betting gaming media, include the regular replay winning combination, the first replay winning combination, the second replay winning combination, the first fall replay winning combination, and the second fall replay winning combination. In detail, a regular replay winning combination occurs when the left reel 32L, the center reel 32M, and the right reel 32R stop symbols on the main line ML are "replay" symbols, "replay" symbols, and "replay" symbols, or when the left reel 32L, the center reel 32M, and the right reel 32R stop symbols are "cherry" and "bell" symbols, respectively. If the stopped symbol on the left reel 32L on the main line ML is a "bell" symbol, the stopped symbol on the middle reel 32M is a "replay" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, the first RT replay win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "watermelon" symbol, the stopped symbol on the middle reel 32M is a "replay" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, the second RT replay win will be awarded. If the stopped symbol on the left reel 32L on the main line ML is a "replay" symbol, the stopped symbol on the middle reel 32M is a "cherry" symbol, and the stopped symbol on the right reel 32R is a "replay" symbol, the first fall replay win will be awarded. If the stopping pattern on the left reel 32L on the main line ML is a "replay" pattern, the stopping pattern on the middle reel 32M is a "replay" pattern, and the stopping pattern on the right reel 32R is a "bell" pattern, the second fall replay win will occur.

[0035] If any of the above replay wins are achieved, it becomes possible to play the next game without needing to make a new bet of gaming media. Specifically, if any of the replay wins is achieved in a game in which three gaming media have been bet, it becomes possible to start playing the next game with three gaming media bet in place, without needing to make a new bet of gaming media.

[0036] Of the various replay wins mentioned above, the 1st RT replay win, 2nd RT replay win, 1st fall replay win, and 2nd fall replay win not only trigger the award of the replay win bonus, but also trigger a transition to the lottery mode. In this slot machine 10, multiple lottery modes are set in the lottery process (Fig. 11) so that the types of roles to be drawn and the winning probability of each role differ, and a transition between these lottery modes occurs when a replay win, which triggers a transition to the lottery mode, is achieved.

[0037] The first BB win and the second BB win are state transition wins that only result in a transition of the game state. Specifically, the first BB win occurs when the stopped symbols on the left reel 32L, the center reel 32M, and the right reel 32R on the main line ML are a "red 7" symbol. The second BB win occurs when the stopped symbols on the left reel 32L, the center reel 32M, and the right reel 32R on the main line ML are a "white 7" symbol. When the first BB win or the second BB win is achieved, the game state transitions to the BB state. The BB state is a game state in which the expected number of game media awarded per unit game is higher than any other game state except the BB state.

[0038] Specifically, the winning combination that allows the bell win to be achieved has a higher probability (e.g., 1 / 2) than in other gaming states, and if the winning combination is achieved, the bell win will be achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of the stop buttons 42 to 44 relative to the rotation positions of the reels 32L, 32M, and 32R. Also, the winning combination that allows the watermelon win to be achieved has a higher probability (e.g., 1 / 4) than in other gaming states, and if the winning combination is achieved, the watermelon win will be achieved regardless of the stopping order of the reels 32L, 32M, and 32R and the timing of the stop operation of the stop buttons 42 to 44 relative to the rotation positions of the reels 32L, 32M, and 32R. This ensures that even in a configuration in which multiple types of winning combinations that are eligible for the award of gaming media exist in the BB state, if a winning combination that corresponds to a winning combination that is eligible for the award of gaming media is achieved, the winning combination corresponding to the winning combination will be achieved. Furthermore, the number of game media awarded when a bell win or a watermelon win is achieved is the same, specifically 8. As a result, even if there are multiple types of wins that are eligible for the award of game media in the BB state, the number of game media awarded when such a win is achieved will be the same regardless of the type of win.

[0039] The BB state continues over multiple games and ends when an end condition is met based on the occurrence of an event corresponding to the game's execution. While the end condition can be any, the slot machine 10 sets the end condition to be one in which the total number of game media awarded since the start of the BB state reaches or exceeds the end reference number. The BB state is divided into a first BB state and a second BB state, and the end reference number differs between the first BB state and the second BB state. The end reference number for the first BB state is greater than five times the fixed payout number that would result from a winning combination that would award game media in the BB state, but not greater than six times that fixed payout number. Specifically, it is set to "41." Meanwhile, the end reference number for the second BB state is greater than 11 times the fixed payout number that would result from a winning combination that would award game media in the BB state, but not greater than twelve times that fixed payout number. Specifically, it is set to "89." With this configuration, in the first BB state, winnings that are eligible for the award of game media are reliably achieved only six times, and in the second BB state, winnings that are eligible for the award of game media are reliably achieved only 12 times. Also, as described above, in a configuration in which there are multiple types of winnings that are eligible for the award of game media in the BB state, if a winning combination corresponding to a winning combination that is eligible for the award of game media is won, the winning combination corresponding to that winning combination will reliably be achieved. Therefore, in the first BB state, only six games that win a winning combination corresponding to a winning combination that is eligible for the award of game media are reliably achieved, and in the second BB state, only 12 games that win a winning combination corresponding to a winning combination that is eligible for the award of game media are reliably achieved.

[0040] <Device for executing various notifications and various effects> Next, the devices for executing various notifications and various effects will be described.

[0041] As shown in FIG. 1 , an upper lamp 64 and an image display device 66 are provided at the top of the front door 12, and a speaker 65 is provided at the bottom of the front door 12. When an abnormality occurs in the slot machine 10, the upper lamp 64 is controlled to emit light in a manner corresponding to the abnormality, and is also controlled to emit light in a manner corresponding to the winning result. Furthermore, the upper lamp 64 is controlled to emit light so as to produce a light-emitting effect corresponding to the display effect on the image display device 66. The speakers 65 are provided as a pair on the left and right, and are controlled to output sound or audio corresponding to the abnormality when an abnormality occurs in the slot machine 10, and are also controlled to output sound or audio corresponding to the winning result. Furthermore, the speakers 65 are controlled to output sound so as to produce a sound output effect corresponding to the display effect on the image display device 66.

[0042] The image display device 66 has a display surface 66a, and is controlled to display an image corresponding to the abnormality on the display surface 66a when an abnormality occurs in the slot machine 10. The image display device 66 is also controlled to display images corresponding to the winning combinations in the lottery and the winning results in each game on the display surface 66a.

[0043] <Electrical Configuration of Slot Machine 10> Next, the electrical configuration of the slot machine 10 will be described with reference to the block diagram of FIG.

[0044] The main control device 140 is equipped with a main control board 141 that is responsible for the main control of the game. The main control board 141 is equipped with an MPU 142 that is equipped with a hard random number circuit 146 and a control IC 148. The hard random number circuit 146 is equipped with a random number generating means for updating the random numbers used in the lottery to determine whether a winning combination will be achieved. Details of the hard random number circuit 146 will be described later. It is not essential that the hard random number circuit 146 and the control IC 148 be integrated into a single chip for the MPU 142; they may each be integrated into separate chips.

[0045] The control IC 148 is a CPU that uses programs to execute main processing (FIG. 7) and timer interrupt processing (FIG. 8). The control IC 148 incorporates a ROM 143 that stores various control programs and fixed value data executed by the control IC 148, and a RAM 144 that is a memory for temporarily storing various data and the like when the control programs stored in the ROM 143 are executed. The control IC 148 also includes a clock circuit 145 that outputs a clock signal with a predetermined cycle, and a frequency divider circuit 147 located midway along the signal path between the clock circuit 145 and the control unit of the control IC 148.

[0046] The frequency divider circuit 147 functions as a frequency changer that changes the period of the clock signal from the clock circuit 145, and is configured to output a modified clock signal that allows the control IC 148 to specify the start timing of timer interrupt processing. Specifically, the frequency divider circuit 147 outputs a modified clock signal having a specific period of 1.49 msec to the control IC 148. The control IC 148 executes processing to check for the occurrence of a specific signal pattern, such as a rising or falling edge of the modified clock signal, and starts periodic processing (timer interrupt processing) using the occurrence of the specific signal pattern as at least one condition. In this case, the execution period of the periodic processing is the period (1.49 msec) of the modified clock signal.

[0047] It is not essential that the ROM 143 and the RAM 144 are integrated into one chip for the control IC 148, and they may be integrated into individual chips.

[0048] The MPU 142 is provided with an input port and an output port. Connected to the input side of the MPU 142 are various sensors, such as the reel unit 31 (more specifically, a reel index sensor that individually detects one rotation of each of the reels 32L, 32M, and 32R), stop detection sensors 42a, 43a, and 44a that individually detect the operation of each stop button 42, 43, and 44, an inserted medal detection sensor 45a that detects medals inserted through a medal insertion slot 45, credit insertion detection sensors 47a, 48a, and 49a that individually detect the operation of each credit insertion button 47, 48, and 49, a settlement detection sensor 51a that detects the operation of a settlement button 51, a payout detection sensor of a hopper device 53, a reset detection sensor 56a that detects the operation of a reset button 56, and a setting key detection sensor 57a that detects the insertion of a setting key into a setting key insertion hole 57. Signals from each of these sensors are input to the MPU 142.

[0049] Here, a detection signal SG1 from the start detection sensor 41a that detects the operation of the start lever 41 is input to the hard random number circuit 146 and the control IC 148. The detection signal SG1 rises from a low state to a high state when the start lever 41 is pressed down by the player, and returns from a high state to a low state when the pressing operation is completed. Details of the connection between the start detection sensor 41a and the hard random number circuit 146 and the connection between the start detection sensor 41a and the control IC 148 will be described later.

[0050] The output side of the MPU 142 is connected to the reel unit 31 (more specifically, the stepping motor for rotating each of the reels 32L, 32M, and 32R), the payout motor of the hopper device 53, the sub-controller 150, etc. In each game, the rotation drive control of each of the reels 32L, 32M, and 32R of the reel unit 31 is performed by the MPU 142, and when a small winning combination is achieved and medals are paid out, the drive control of the hopper device 53 is also performed by the MPU 142. In addition, commands are sent from the MPU 142 to the sub-controller 150 at each timing of each game.

[0051] A power outage monitoring circuit (not shown) provided in the power supply 54 is connected to the input side of the MPU 142. The power supply 54 is equipped with a power supply unit and a power outage monitoring circuit that supply drive power to the main control unit 140 and other electronic devices in the slot machine 10. The power outage monitoring circuit monitors the voltage applied to the power supply unit from an external power source and outputs a power outage signal to the MPU 142 when the voltage drops below a reference voltage. The MPU 142 executes power outage processing upon receiving the power outage signal and enables the device to return to the processing state before the power outage after power is restored. The power supply 54 also includes a power outage power supply unit that supplies backup power to the RAM 144 as power during power outage when the supply of operating power from the external power source is interrupted. This allows data to be stored and maintained in the RAM 144 even when the supply of operating power from the external power source is interrupted as long as the power outage power supply unit can supply backup power (e.g., for one or two days). However, by turning on the power supply of the slot machine 10 while pressing the reset button provided on the power supply device 54, the data stored and held in the RAM 144 is initialized.

[0052] The sub-control device 150 is equipped with a sub-control board 151 for executing control of various notifications and various performances. The sub-control board 151 is equipped with an MPU 152. The MPU 152 has built-in components such as a ROM 153 that stores various control programs and fixed value data executed by the MPU 152, a RAM 154 that is a memory for temporarily storing various data when the control programs stored in the ROM 153 are executed, a clock circuit 155 that outputs a rectangular wave of a predetermined frequency, an interrupt circuit, a data input / output circuit, and a random number generation circuit.

[0053] It is not essential that the ROM 153 and RAM 154 be integrated into a single chip for the MPU 152, and each may be integrated into a separate chip. When the supply of operating power from an external power source is cut off, backup power is supplied to the RAM 154 from a power-off power supply unit of the power supply device 54, and data is stored and held in the RAM 154 while the backup power is being supplied (for example, for one or two days). However, by pressing the reset button 56 provided on the power supply device 54 and then turning on the power to the slot machine 10, the data stored and held in the RAM 154 is initialized.

[0054] An input port and an output port are provided in the MPU 152. As already explained, the MPU 142 of the main control device 140 is connected to the input side of the MPU 152, and various commands are received from the MPU 142.

[0055] An upper lamp 64, a speaker 65, and an image display device 66 are connected to the output side of the MPU 152. Based on commands received from the MPU 142 of the main control device 140, the MPU 152 controls the light emission of the upper lamp 64, the sound output of the speaker 65, and the display of the image display device 66, thereby enabling various notifications and various effects to be performed.

[0056] For the sake of convenience, in the following explanation, the MPU 142, ROM 143, and RAM 144 of the main control device 140 will be referred to as the main MPU 142, main ROM 143, and main RAM 144, respectively, and the MPU 152, ROM 153, and RAM 154 of the sub-control device 150 will be referred to as the sub-MPU 152, sub-ROM 153, and sub-RAM 154, respectively.

[0057] <Configuration of main control board 141> Next, the configuration of the main control board 141 will be described in detail with reference to the block diagram of FIG.

[0058] As shown in Fig. 6, the control IC 148 has input terminals TA1 to TA3 and an output terminal TA4. Also, as shown in Fig. 6, the hardware random number circuit 146 has an update circuit 101 for updating the random numbers used to determine whether a winning combination has been achieved, a latch register 102 into which the random numbers updated by the update circuit 101 are written, and a control circuit 103 that can grasp the timing at which the start lever 41 has been operated using a detection signal SG1.

[0059] The control circuit 103 is equipped with a CPU 114 that executes processing using a program. The CPU 114 equipped in the control circuit 103 is referred to as the control-side CPU 114. The control-side CPU 114 is equipped with a ROM 115 that stores a program for executing management operations (FIG. 19), a RAM 116 that has an area for temporarily storing information, input terminals TB1 and TB2, and output terminals TB3 and TB4.

[0060] Here, in the management operation (FIG. 19), the control side CPU 114 detects a rise from a LOW state to a HI state in the detection signal SG1 input to the control side CPU 114, and, on the condition that it determines that the HI state of the detection signal SG1 has been maintained until 12.8 μs has elapsed from the timing of the detection, sends a latch signal, which is a pulse signal, to the latch register 102 and sets "1" to the latched status 113. Details of the management operation will be described later.

[0061] Next, we will explain the connection between the start detection sensor 41a and the control IC 148, and the connection between the start detection sensor 41a and the hard random number circuit 146. As shown in Fig. 6, one signal line from the start detection sensor 41a branches into two on the main control board 141. One of the signal lines is connected to the input terminal TA1 of the control IC 148, and the other signal line is connected to the input terminal TB1 of the control-side CPU 114 that constitutes the hard random number circuit 146. Therefore, if noise is mixed into one of the branched signal lines, it is possible to prevent the noise from affecting the other.

[0062] Next, the update circuit 101 will be described. As shown in Fig. 6, the update circuit 101 includes a clock circuit 104 that outputs a clock signal of a predetermined frequency (e.g., 16 MHz), a random number generation circuit 106 that generates an M-sequence random number that is updated at each update timing, and a random number counter 105 in which the random numbers are stored. Here, the control IC 148 operates based on a clock circuit 145 (Fig. 5) in the control IC 148. On the other hand, the update circuit 101 operates based on a clock circuit 104 in the update circuit 101 that operates independently of the clock circuit 145 in the control IC 148. Therefore, the update timing of the random numbers in the update circuit 101 is not affected by the processing being executed by the control IC 148.

[0063] Random number counter 105 has a 2-byte storage area, and stores random numbers between "1" and "65535". The 2-byte storage area is made up of 16 positive-edge D flip-flop circuits. The D flip-flop circuits that make up random number counter 105 are referred to as random number counter circuits 105a to 105p. Random number counter circuits 105a to 105p each have a clock terminal (CLK terminal), a D terminal, and a clear terminal (CLR terminal) as input terminals, and a Q terminal as an output terminal.

[0064] 6, a signal line coming out of the clock circuit 104 branches into two lines within the update circuit 101, and one of the branched signal lines further branches into 16 lines within the update circuit 101 and is connected to the CLK terminals of 16 random number counter circuits 105a to 105p. Therefore, the clock signal output from the clock circuit 104 is input to the CLK terminals of the random number counter circuits 105a to 105p.

[0065] The other branched signal line from clock circuit 104 is connected to random number generation circuit 106 via inverter circuit 107. When the signal input to random number generation circuit 106 via inverter circuit 107 rises, 16-bit data output from random number generation circuit 106 to D terminals of random number counter circuits 105a to 105p is updated. When the signal input to the CLK terminal rises, random number counter circuits 105a to 105p output the signal input to the D terminal from the Q terminal.

[0066] The update timing of the random numbers generated by the random number generating circuit 106 and the update timing of the random numbers stored in the random number counter 105 are shifted by half the period of the signal output from the clock circuit 104. Therefore, in the update circuit 101, the update of the data output from the random number generating circuit 106 and the update of the signals output from the Q terminals of the 16 random number counter circuits 105a to 105p in the random number counter 105 are alternately repeated.

[0067] Specifically, since the clock signal output from the clock circuit 104 is 16 MHz, the clock signal rises at a cycle of 62.5 ns. Therefore, data updates in the random number generation circuit 106 occur at a cycle of 62.5 ns, and data updates in the random number counter 105 occur between the time the data in the random number generation circuit 106 is updated and the time it is updated to the next data. As already explained, the execution cycle of the timer interrupt process executed by the control IC 148 is 1.49 msec, so the random number update interval is sufficiently shorter than the execution cycle of the timer interrupt process. Note that negative edge type D flip-flop circuits may be used in the random number counter circuits 105a to 105p instead of the positive edge type D flip-flop circuits.

[0068] Here, the random number stored in the random number counter 105 is a 16-digit binary number. The random number generation circuit 106 is a hardware circuit that generates M-sequence random numbers. The M-sequence random numbers are pseudo-random numbers with a period. The period of the M-sequence random numbers updated by the random number generation circuit 106 is "65535." The random number generation circuit 106 generates a second random number based on a preset initial value other than "0," and generates a third random number based on the second random number. In this way, the random number generation circuit 106 updates the random number represented by a 16-digit binary number, and after outputting 65535 numbers to the random number counter 105 once, it returns to the initial value. In this way, the order of random numbers output in the M-sequence random numbers is determined by the preset initial value, and each number from "1" to "65535" appears once within one period. Therefore, the probability of winning a winning combination can be set according to the number of numbers set as numbers corresponding to winning combinations.

[0069] The random numbers updated by the random number counter 105 are not limited to M-sequence random numbers. For example, the random number stored in the random number counter 105 may be incremented by "1" each time the update circuit 101 reaches an update timing, and when the value of the random number counter 105 reaches "65535", the random number counter 105 may be cleared to "0". In short, it is sufficient that the result of the hand win / loss determination performed using the random number is not biased towards a specific result.

[0070] Next, we will explain the latch register 102 to which the numerical information of the random numbers stored in the random number counter 105 of the update circuit 101 is written. The latch register 102 has a 2-byte storage area, similar to the random number counter 105 of the update circuit 101. Specifically, the latch register 102 has 16 positive edge trigger type D flip-flop circuits. The D flip-flop circuits that make up the latch register 102 are referred to as latch register circuits 102a to 102p. The latch register circuits 102a to 102p have a CLK terminal, a D terminal, and a CLR terminal as input terminals, and a Q terminal as an output terminal.

[0071] Signal lines coming from the Q terminals of the random number counter circuits 105a to 105p are connected to the D terminals of the latch register circuits 102a to 102p. More specifically, the numerical information stored in the random number counter 105 of the update circuit 101 and the numerical information stored in the latch register 102 are both 16-digit binary numbers. The Q terminals of the random number counter circuits 105a to 105p that store the nth digit of numerical information in the random number counter 105 are connected to the D terminals of the latch register circuits 102a to 102p that store the nth digit of numerical information in the latch register 102. Here, n is a natural number between 1 and 16.

[0072] The CLK terminals of the latch register circuits 102a to 102p are connected by signal lines to the output terminal TB4 of the control CPU 114. More specifically, one signal line coming out of the output terminal TB4 of the control CPU 114 branches into 16 lines which are fed to the CLK terminals of the latch register circuits 102a to 102p. The Q terminals of the latch register circuits 102a to 102p are connected to the input terminal TA3 of the control IC 148.

[0073] Next, we will explain the configuration for acquiring numerical information on the random numbers used by the control IC 148 to determine whether a winning combination has been achieved. When the detection signal SG1 input to the control CPU 114 rises from a LOW state to a HI state and the HI state is maintained for a certain period of time (12.8 μs), the control CPU 114 outputs a latch signal from the output terminal TB4 to the CLK terminals of the latch register circuits 102a to 102p.

[0074] Here, the latch signal is a pulse signal that rises from a low state to a high state and then falls from a high state to a low state. By configuring the control circuit 103 to wait 12.8 μs after the detection signal SG1 input to the control circuit 103 rises, it is possible to prevent the latch signal from being transmitted due to noise of less than 12.8 μs that enters the input terminal TB1 of the control side CPU 114.

[0075] Since the latch register circuits 102a to 102p are of the positive edge trigger type, when a latch signal is sent from the control side CPU 114 to the latch register 102, the random number stored in the random number counter 105 is written to the latch register 102, and the written random number is output to the input terminal TA3 of the control IC 148.

[0076] In detail, in synchronization with the rising edge of the signal input to the CLK terminal of the latch register circuits 102a to 102p, the numerical information output from the Q terminal of the random number counter circuits 105a to 105p and input to the D terminal of the latch register circuits 102a to 102p is output from the Q terminal of the latch register circuits 102a to 102p. When it is time to acquire a random number used to determine whether a winning combination has been achieved, the control IC 148 acquires the numerical information output from the Q terminal of the latch register circuits 102a to 102p and input to the input terminal TA3 of the control IC 148.

[0077] The random number counter 105 and the latch register 102 may be configured to include a D flip-flop circuit instead of the positive edge type D flip-flop circuit. Also, the random number counter 105 and the latch register 102 may be configured to include an RS flip-flop circuit or a JK flip-flop circuit instead of the D flip-flop circuit.

[0078] Next, the latched status 113 will be described. As shown in FIG. 6, the control circuit 103 has a latched status 113 that is set to "1" when the random number stored in the random number counter 105 is written to the latch register 102. The latched status 113 is a status register made up of one positive edge triggered T flip-flop circuit (T-FF). As shown in FIG. 6, the latched status, which is a T-FF, has a T terminal 113b and a CLR terminal 113c as input terminals, and a Q terminal 113a as an output terminal. The latched status 113 inverts the signal output from the Q terminal 113a in synchronization with the rise of the signal input to the T terminal 113b from a LOW state to a HIGH state.

[0079] Specifically, when a signal of "0" is being output from the Q terminal 113a, the signal output from the Q terminal 113a is inverted to "1" in synchronization with the rising edge of the signal input to the T terminal 113b. Also, when a signal of "1" is being output from the Q terminal 113a, the signal output from the Q terminal 113a is inverted to "0" in synchronization with the rising edge of the signal input to the T terminal 113b. The signal output from the Q terminal 113a is cleared to "0" when the signal input to the CLR terminal 113c rises from a LOW state to a HIGH state.

[0080] Here, the state in which "0" is set in latched status 113 means that "0" is being output from Q terminal 113a of latched status 113. Also, the state in which "1" is set in latched status 113 means that "1" is being output from Q terminal 113a of latched status 113.

[0081] The T terminal 113b of the latched status 113 is connected by one signal line to the output terminal TB3 of the control CPU 114. When the latched status 113 is set to "0", the control CPU 114 sends a short pulse signal to the T terminal 113b of the latched status 113, thereby inverting the signal output from the Q terminal 113a of the latched status 113 and setting the latched status 113 to "1".

[0082] Specifically, the control-side CPU 114 detects that the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 has risen from a LOW state to a HI state, and at the timing when it determines that the HI state has continued for 12.8 μs or more, it transmits a latch signal from the output terminal TB4 to the CLK terminals of the latch register circuits 102a to 102p, and transmits a pulse signal from the output terminal TB3 to the T terminal 113b of the latched status 113, thereby setting the latched status 113 to "1." Therefore, at the timing when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, the latched status 113 is set to "1."

[0083] On the condition that the latched status 113 is set to "0," the control-side CPU 114 raises the signal output from the output terminal TB3 to the T terminal 113b of the latched status 113, thereby inverting the signal output from the Q terminal 113a of the latched status 113 from a LOW state to a HIGH state. This sets the latched status 113 to a state in which "1" is set. Furthermore, if the latched status 113 has already been set to "1," the control-side CPU 114 maintains the state in which the latched status 113 is set to "1" without transmitting a pulse signal. Therefore, even if the start lever 41 is operated when the latched status 113 is set to "1," the value set in the latched status 113 will not be inverted from "1" to "0" as a result of this operation.

[0084] Here, when the control side CPU 114 determines that the detection signal SG1 input to the input terminal TB1 of the control side CPU 114 rises from a LOW state to a HI state and that the HI state has continued for 12.8 μs or more, it outputs a latch signal to the latch register 102 and updates the numerical information of the random number stored in the latch register 102, even if the latched status 113 is set to "1".

[0085] A specific example of a situation in which the start lever 41 is operated while the latched status 113 is set to "1" will be described below. There are cases in which the latched status 113 is set to "1" due to noise entering only the input terminal TB1 of the control CPU 114. Here, the control IC 148 starts the game under the conditions that it is a period in which the game can be started, the control IC 148 detects the rising edge of the detection signal SG1, and the latched status 113 is set to "1."

[0086] For this reason, even if the latched status 113 is set to "1" due to noise entering the input terminal TB1 of the control side CPU 114, the rising edge of the detection signal SG1 is not detected in the control IC 148, so the game does not start and the latched status 113 remains set to "0". When the start lever 41 is operated in this state, the numerical information stored in the latch register 102 is updated to the numerical information of a random number corresponding to the current operation of the start lever 41, while the latched status 113 remains set to "1".

[0087] In this way, by configuring the random number stored in the latch register 102 to be updated when the start lever 41 is operated while the latched status 113 is set to "1", it is possible to reduce the possibility that the random number stored in the latch register 102 will be used to determine whether a winning combination has been achieved due to noise.

[0088] Furthermore, the signal line extending from the Q terminal of the latched status 113 branches into two on the control circuit 103, one of which is connected to the input terminal TA2 of the control IC 148, and the other of which is connected to the input terminal TB2 of the control-side CPU 114. Therefore, the signal output from the Q terminal 113a of the latched status 113 is input to both the control IC 148 and the control-side CPU 114.

[0089] The control IC 148 can determine whether or not "1" is set in the latched status 113 of the control circuit 103 by grasping the signal input to the input terminal TA2 of the control IC 148. Also, the control-side CPU 114 can determine whether or not "1" is set in the latched status 113 by grasping the signal input to the input terminal TB2 of the control-side CPU 114.

[0090] Furthermore, a CLR terminal 113c of the latched status 113 is connected by one signal line to an output terminal TA4 of the control IC 148. The control IC 148 can clear the latched status 113 to "0" by raising the signal output to the CLR terminal 113c of the latched status 113 from a LOW state to a HIGH state.

[0091] When the control-side CPU 114 detects that the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 has risen from a low state to a high state, the control-side CPU 114 uses a timer counter to determine whether the high state has been maintained for 12.8 μs. Specifically, the timer counter starts counting at the timing when the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 has risen from a low state to a high state. Once the counting starts, the timer counter counts time in 0.1 μs increments. If the high state of the detection signal SG1 is not maintained until the timer counter has counted 12.8 μs, the timer counter is reset.

[0092] Next, we will explain the conditions under which the control IC 148 acquires the random number input to the input terminal TA3 of the control IC 148. During the timer interrupt process (FIG. 8) executed at a cycle of 1.49 ms, the control IC 148 acquires the random number input to the input terminal TA3 of the control IC 148 and uses it to determine whether the winning combination has been achieved, under the conditions that it is a period in which the game can be started, that the rising edge of the detection signal SG1 input to the control IC 148 has been detected, and that the latched status 113 is set to "1."

[0093] At the time when latched status 113 is set to "1", the random number input to input terminal TA3 of control IC 148 is updated to the random number for the current operation of start lever 41. Therefore, by configuring control IC 148 to acquire a random number on the condition that latched status 113 is set to "1", it is possible to avoid control IC 148 acquiring the random number before the update (the previous random number).

[0094] The timing at which the player operates the start lever 41 is arbitrary and is not affected by the timing at which the timer interrupt process is performed by the control IC 148. For this reason, the timer interrupt process may be performed before 12.8 μs has elapsed since the detection signal SG1 input to the control circuit 103 rose. At this time, the random number input to the input terminal TA3 of the control IC 148 is the previous random number. In this case, the condition that the latched status 113 is set to "1" is not met, so the control IC 148 does not obtain a random number. In this case, the game will not start with the current operation of the start lever 41, and the player must operate the start lever 41 again.

[0095] <Processing performed by control IC 148> Next, a description will be given of the processing executed by the control IC 148. First, a main processing that is started in the control IC 148 when the supply of operating power to the control IC 148 is started will be described with reference to the flowchart of FIG.

[0096] The main process first executes initialization (step S101), which allows timer interrupts and performs various initializations for registers in the control IC 148, I / O devices, and the like.

[0097] After the initialization process is completed, it is determined whether the setting key is inserted into the setting key insertion hole 57 and an ON operation has been performed (step S102). If the ON operation has been performed (step S102: YES), and if the reset button 56 has not been turned ON when the power switch 55 is turned ON (step S103: NO), a partial clear process is performed (step S104). If the reset button 56 has been turned ON when the power switch 55 is turned ON (step S103: YES), a full clear process is performed (step S105). In other words, if the setting values ​​of the slot machine 10 are changed without performing an operation to initialize the main RAM 144, a partial clear process is performed, and if an operation to initialize the main RAM 144 has been performed, a full clear process is performed.

[0098] In the partial clear process, some areas in the main RAM 144 are initialized, and in the full clear process, all areas in the main RAM 144 are initialized. In the partial clear process, each area in the main RAM 144 is cleared to "0" except for the area in which data indicating whether the main RAM 144 is in the BB state is stored, the area in which data indicating the total number of gaming media awarded in the BB state is stored, the area in which data indicating the type of lottery mode described below is stored, and the area in which data indicating a setting value is stored. In this case, the area in which a winning combination is stored is cleared to "0." In the full clear process, all areas in the main RAM 144 are cleared to "0," including areas that are not subject to "0" clearing in the partial clear process. As a result, even if the partial clear process is executed, the BB state is maintained in the state before the power was cut off, and when the full clear process is executed, the normal gaming state is restored regardless of the state before the power was cut off.

[0099] It should be noted that the present invention is not limited to the above configuration, and a configuration may be adopted in which if the power is cut off in the BB state and a partial clear process is executed, the state is not the BB state. Also, even if a partial clear process is executed, the area in which the data indicating that the BB role has been won is stored may not be cleared to "0".

[0100] After the processing of step S104 or step S105 is executed, a winning probability setting process is executed (step S106). In the winning probability setting process, the current setting value is read, provided that the setting key is inserted and turned ON, and the current setting value is displayed on a predetermined display unit provided on the gaming panel 20. If the area for storing setting value data in the main RAM 144 has been initialized immediately before the winning probability setting process, the setting value displayed on the predetermined display unit is "1," which corresponds to "Setting 1." In the winning probability setting process, the setting value is updated by 1 each time the reset button 56 is operated, and the updated setting value is displayed on the predetermined display unit. If the reset button 56 is operated when the setting value is "Setting 6," the setting value is updated to "Setting 1." The winning probability setting process is terminated when the setting key is released from ON after the start lever 41 is operated. In this case, the display of the setting value on the predetermined display unit is terminated.

[0101] After executing the winning probability setting process, a power restoration command is sent to the sub-side MPU 152 (step S107). The power restoration command is a command for the sub-side MPU 152 to recognize that the main process has ended after the supply of operating power to the control IC 148 has started, and that normal processing and timer interrupt processing can now be executed. Upon receiving the power restoration command, the sub-side MPU 152 executes processing corresponding to the start of the supply of operating power. In this case, if the all-clear process (step S105) has been executed, corresponding data is set in the power restoration command. When a power restoration command with this data set is received, the sub-side MPU 152 initializes the sub-side RAM 154; when a power restoration command without this data set is received, the sub-side MPU 152 does not initialize the sub-side RAM 154. After sending the power restoration command, the sub-side MPU 152 transitions to normal processing (step S108). The normal processing will be described in detail later.

[0102] If the setting key has not been turned on in the main process (step S102: NO), the power restoration process from step S109 onward is executed. The power restoration process is a process for restoring the state of the slot machine 10 to the state before the power was cut off. In the power restoration process, the main RAM 144 is checked to determine whether the setting value of the slot machine 10 is normal (step S109). Specifically, if the setting value is any of "Setting 1" to "Setting 6," it is determined to be normal, and if it is "0" or "7" or greater, it is determined to be abnormal. If the setting value is normal, it is checked whether a power outage flag is set to "1" (step S110). The power outage flag is provided in the main RAM 144, and if the supply of operating power to the control IC 148 is stopped and a predetermined power outage process is executed normally, the power outage flag is set to "1." If the power outage flag is set to "1," it is checked whether the RAM determination value is normal (step S111). Specifically, the checksum value of the main RAM 144 is checked to see if it is normal.

[0103] If the determinations in steps S109 to S111 are all affirmative, this means that the power outage processing at the time of the previous power outage was executed normally. In this case, the value of the stack pointer saved in the main RAM 144 is written to the stack pointer of the control IC 148, and the data saved in the main RAM 144 is restored to the register of the control IC 148, thereby restoring the state of the register of the control IC 148 to the state before the power was cut off (step S112). In addition, the power outage flag of the main RAM 144 is cleared to "0" (step S113). Thereafter, a power recovery command is sent to the sub-MPU 152 (step S114), and then the address before the power was cut off is restored (step S115).

[0104] On the other hand, if a negative determination is made in any of steps S109 to S111, an operation prohibition process is executed. In the operation prohibition process, the execution of the next timer interrupt process (FIG. 8) is prohibited (step S116), all output ports of the control IC 148 are cleared to "0" to turn off all actuators connected to those output ports (step S117), and an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S118). This then becomes an infinite loop. The operation prohibition process is released by executing the all-clear process (step S105).

[0105] Next, the timer interrupt process executed by the control IC 148 will be described with reference to the flowchart of Fig. 8. The timer interrupt process is started every 1.49 msec.

[0106] In the register save process (step S201), the values ​​of all registers in the control IC 148 used in the normal process (described later) are saved to the main RAM 144. In step S202, it is determined whether the power outage flag is set to "1." If the power outage flag is set to "1," the process proceeds to step S203, where power outage processing is executed. The power outage flag is set when a power outage signal is input to the control IC 148 from the power outage monitoring circuit of the power supply device 54. In the power outage processing, it is first determined whether command transmission has been completed. If transmission has not been completed, the process is terminated and the process returns to the timer interrupt process, thereby terminating command transmission. If command transmission has been completed, the value of the stack pointer of the control IC 148 is saved in the main RAM 144. Thereafter, the output status of the output port of the control IC 148 is cleared, and all actuators (not shown) are turned off. Then, when the power outage is resolved, a judgment value for determining whether the data in the main RAM 144 is normal is calculated and saved in the main RAM 144, and subsequent RAM access is prohibited. After the above processing is performed, an infinite loop is entered in preparation for the possibility that the power supply will be completely cut off and processing will no longer be possible.

[0107] If the power outage flag is not set to "1" in step S202, various processes from step S204 onwards are carried out. In step S204, a watchdog timer clear process is carried out to initialize the value of the watchdog timer, which is used to monitor for malfunctions. In step S205, an interrupt end declaration process is carried out, which enables the control IC 148 itself to set the next timer interrupt. In step S206, a start command setting process (Fig. 9) is carried out.

[0108] In the start command setting process, the start command flag 144c (FIG. 6) is set to "1" on the condition that a random number corresponding to the current operation of the start lever 41 has already been input to the input terminal of the control IC 148. If the start command flag 144c is set to "1," a random number is acquired in step S501 of the lottery process (FIG. 11) described below. Here, the random number corresponding to the current operation of the start lever 41 is a random number that is written from the random number counter 105 to the latch register 102 when the detection signal SG1 rises from a LOW signal to a HI signal due to the operation of the start lever 41.

[0109] On the other hand, if the random number input to the input terminal of the control IC 148 has not been updated to a random number corresponding to the current operation of the start lever 41, the start command flag 144c is not set to "1." In this situation, the control IC 148 does not acquire a random number. Here, a situation in which a random number corresponding to the current operation of the start lever 41 is not acquired means that the start command setting process is executed before 12.8 μsec has elapsed since the detection signal SG1 input to the input terminal of the control circuit 103 rose from a LOW signal to a HI signal. The start command setting process will be described in detail later.

[0110] In step S207, a stepping motor control process is performed to drive each stepping motor to rotate each reel 32L, 32M, and 32R. In step S208, the status of various sensors connected to the input ports is read, and a sensor monitoring process is performed to monitor whether the read results are normal. In step S209, a timer subtraction process is performed to subtract values ​​from each counter and timer. In step S210, a counter process is performed to output the count results of the number of gaming media bets and the number of payouts to the outside.

[0111] In step S211, a command output process is performed to send various commands to the sub-side MPU 152. In step S212, a port output process is performed to output data corresponding to the I / O device from the input / output port. In step S213, the values ​​of each register saved in the main-side RAM 144 in the previous step S201 are restored to the corresponding register in the control IC 148. Thereafter, in step S214, an interrupt enable process is performed to enable the next timer interrupt, and this series of timer interrupt processes is terminated.

[0112] Next, the start command setting process executed in step S206 of the timer interrupt process (FIG. 8) will be described with reference to the flowchart of FIG. 9. The start command setting process is executed by the control IC 148.

[0113] First, in step S301, it is determined whether or not the start possible flag 144a (FIG. 5) is set to "1." Here, the start possible flag 144a is a flag stored in the main RAM 144, and is set to "1" when it is possible to start a game, and is cleared to "0" when the game has started. Specifically, the start possible flag 144a is set to "1" in step S406 of the normal processing (FIG. 10) described later, and is cleared to "0" in step S409. If it is possible to start a game (step S301: YES), the process proceeds to step S302.

[0114] In step S302, it is determined whether the signal storage flag 144d (FIG. 5) is "0." Here, the signal storage flag 144d is a flag stored in the main RAM 144. The signal storage flag 144d stores the state of the detection signal SG1 input to the control IC 148 at the time when the start command setting process is performed. The signal storage flag 144d is set to "1" when the detection signal SG1 is in a HI state, and is cleared to "0" when the detection signal SG1 is in a LOW state.

[0115] Specifically, in steps S304 and S315 of this start command setting process, the signal storage flag 144d is set to "1," and in step S314, the signal storage flag 144d is cleared to "0." In step S302, if the signal storage flag 144d is "0" (step S302: YES), the process proceeds to step S303.

[0116] In step S303, it is determined whether the detection signal SG1 input to the control IC 148 is in a HI state. A positive determination in step S303 means that the detection signal SG1, which was in a LOW state in the previous start command setting process, has become a HI state in this start command setting process. In other words, this means that a rising edge of the detection signal SG1 has been detected. If a rising edge of the detection signal SG1 has been detected (step S303: YES), in step S304, the signal storage flag 144d is set to "1." This stores the fact that the detection signal SG1 input to the control IC 148 was in a HI state at the time when the current start command setting process was performed.

[0117] In the next step S305, it is determined whether or not "1" is set in the latched status 113. Specifically, it is determined whether or not the numerical information output from the Q terminal of the latched status 113 and input to the input terminal of the control IC 148 is "1."

[0118] If the latched status 113 is set to "1" (step S305: YES), this means that the random number corresponding to the current operation of the start lever 41 has already been stored in the latch register 102, and therefore, in step S306, the start command flag 144c (FIG. 5) is set to "1." Here, the start command flag 144c is a flag stored in the main RAM 144. If the start command flag 144c is set to "1," the processing from step S408 onward of the normal processing (FIG. 10), which will be described later, is executed to start the game. The start command flag 144c is cleared to "0" in step S408 of the normal processing (FIG. 10).

[0119] In the following step S307, the error counter 144b (FIG. 5) is cleared to "0," and in step S308, the latched status 113 is cleared to "0," thereby terminating this start command setting process. Here, the error counter 144b is a counter arranged in the main RAM 144. The error counter 144b is a counter that counts the number of consecutive events that result in a negative determination when a rising edge of the detection signal SG1 input to the control IC 148 is detected in a state where the game can be started, and the control IC 148 determines whether or not "1" is set in the latched status 113 (when the process of step S305 is executed).

[0120] If the latched status 113 is not set to "1" (step S305: NO), the error counter 144b is incremented by "1" in step S309, and it is determined in step S310 whether the value of the error counter 144b is "3." If the value of the error counter 144b is "1" or "2" (step S310: NO), the start command setting process is terminated. On the other hand, if the value of the error counter 144b is "3" (step S310: YES), this means that a negative determination has occurred three times in succession in step S305. In this case, the connection between the start detection sensor 41a and the control circuit 103 may have been cut off, and the detection signal SG1 may no longer be received by the control circuit 103. Therefore, the error counter 144b is cleared to "0" in step S311, and an abnormality notification process is performed in step S312, and the process enters an infinite loop.

[0121] In the abnormality notification process, an abnormality notification is issued by the upper lamp 64, speaker 65, and image display device 66 to indicate that an abnormality has occurred, and an external abnormality output is sent to the hall computer of the gaming hall. By notifying the gaming hall manager that the connection between the start detection sensor 41a and the control circuit 103 may have been cut, it is possible to avoid a situation in which the game does not start even when the start lever 41 is operated.

[0122] If the start enable flag 144a is not set to "1" in step S301, or if the signal storage flag is not set to "0" in step S302, a process is executed to store the state of the detection signal SG1 input to the control IC 148 at the time when the current start command setting process is performed (processing of steps S313 to S315).

[0123] Specifically, in step S313, it is determined whether the detection signal SG1 input to the control IC 148 is in a LOW state. If the detection signal SG1 is in a LOW state (step S313: YES), the signal storage flag 144d is cleared to "0" in step S314. If the detection signal SG1 is in a HIGH state (step S313: NO), the signal storage flag 144d is set to "1" in step S315.

[0124] In this start command setting process, if the rising edge of the detection signal SG1 input to the control IC 148 is not detected and therefore step S306 for setting the start command flag 144c to "1" is not performed, the latched status 113 is cleared to "0".

[0125] Specifically, after a negative determination in step S303, after the processing in step S314, or after the processing in step S315, the latched status 113 is cleared to "0" in step S316, and the start command setting process ends. More specifically, regarding step S316, the control IC 148 transmits a pulse signal to the CLR terminal of the latched status 113. The latched status 113 is cleared to "0" in synchronization with the rising edge of the signal input to the CLR terminal.

[0126] In this way, even if a rising edge of the detection signal SG1 is detected when the game can be started, by keeping the start command flag 144c at "0" if the latched status 113 is set to "0", it is possible to avoid a situation in which the random number stored in the latch register 102 before the current operation of the start lever 41 is acquired by the control IC 148 as the current random number.

[0127] Furthermore, if the start command setting process is executed within 12.8 μs after the detection signal SG1 input to the control circuit 103 rises, the latched status 113 is set to "1" after the start command setting process. Also, if noise of 12.8 μs or more is mixed only into the input terminal of the control circuit 103, the latched status 113 is set to "1." If the state in which the latched status 113 is set to "1" is maintained for a long time, the start lever 41 is more likely to be operated while the latched status 113 is set to "1."

[0128] In this case, the control IC 148 may acquire an old random number and determine whether the hand is successful or not based on the old random number, just as in the case where the latched status 113 is not used. In contrast, the control IC 148 may be configured to clear the latched status 113 to "0" in all start command setting processes in which the rising edge of the detection signal SG1 input to the control IC 148 is not detected, thereby reducing the possibility that the control IC 148 will acquire an old random number.

[0129] Next, the normal processing executed by the control IC 148 will be described with reference to the flowchart of FIG.

[0130] First, in step S401, an interrupt permission process is performed to permit the next timer interrupt, and in step S402, a start waiting process is executed. In the start waiting process, it is determined whether any replay wins occurred in the previous game. If any replay wins occurred, an automatic insertion process is performed to automatically insert virtual medals in the same number as the previous bet number, and the start waiting process is terminated. If no replay wins occurred, it is determined whether the settlement button 51 has been operated, and if the settlement button 51 has been operated, a medal return process is performed to pay out medals in the same number as the credited virtual medals.

[0131] At the start timing of the medal return process, the start possible flag 144a (FIG. 5) and the start command flag 144c (FIG. 5) are cleared to "0." By clearing the start possible flag 144a to "0" at the start timing of the medal return process, the period during which the game can be started ends. This makes it possible to avoid a situation in which the start command flag 144c may be set to "1" in the start command setting process (FIG. 9) even though the medals have been returned.

[0132] Also, there may be a case where the start command setting process (FIG. 9) is executed at a timing after a negative determination is made in step S407 and before the medal return process is executed in step S402, and the start command flag 144c is set to "1." If the medal return process is executed with the start command flag 144c set to "1" and the start command flag 144c is not cleared to "0," the game will start the next time the number of medals bet reaches the specified number, even if the player does not operate the start lever 41. In contrast, by clearing the start command flag 144c to "0" at the start of the medal return process, it is possible to avoid a situation in which the game starts before the player operates the start lever 41.

[0133] After the medal return process is completed or if the settlement button 51 has not been operated, it is determined whether medals have been inserted or the credit insertion buttons 47-49 have been operated between the previous start waiting process and the current start waiting process, and if either has been done, a medal insertion process is carried out to change the number of bets, etc., and the start waiting process is terminated. Also, if neither medals have been inserted nor the credit insertion buttons 47-49 have been operated between the previous start waiting process and the current start waiting process, the start waiting process is terminated.

[0134] After executing the start waiting process in step S402, it is determined in step S403 whether the number of medals bet has reached a specified number ("3" in this embodiment), and if the number of medals bet has not reached the specified number (step S403: NO), the process returns to the start waiting process in step S402. If the number of medals bet has reached the specified number (step S403: YES), it is determined in step S404 whether the start possible flag 144a is set to "1".

[0135] If "1" is not set in the start possible flag 144a (step S404: NO), in step S405, a pulse signal is sent to the CLR terminal of the latched status 113 to clear the latched status 113 to "0." By clearing the latched status 113 to "0" immediately after the game becomes ready to start, it becomes possible to know whether the start lever 41 was operated after the game became ready to start, even if the latched status 113 was set to "1" before the game became ready to start.

[0136] After the latched status 113 is cleared to "0" in step S405, the start possible flag 144a is set to "1" in step S406. The start possible flag 144a is a flag that is set to "1" when the game is ready to start, and is cleared to "0" in step S409 when the game starts.

[0137] After making a positive determination in step S404 or performing the processing of step S406, it is determined in step S407 whether or not the start command flag 144c is set to "1." The start command flag 144c is a flag that is set to "1" when the start lever 41 is operated in a state in which the game can be started and a random number corresponding to the current operation of the start lever 41 is input to the input terminal of the control IC 148. If the start command flag 144c is not set to "1" (step S407: NO), the process returns to the start wait processing of step S402.

[0138] If the start command flag 144c is set to "1" (step S407: YES), the start command flag 144c is cleared to "0" in step S408, and the start possible flag 144a is cleared to "0" in step S409. When the start possible flag 144a is cleared to "0", a negative determination is made in step S301 of the start command setting process (FIG. 9), and the processes from step S302 onwards are not executed, so the start command flag 144c is not newly set to "1" during the game.

[0139] In step S410, after the main line ML is activated, an acceptance prohibition process is executed. By executing the acceptance prohibition process, even if a medal is inserted into the medal insertion slot 45, the medal is discharged into the medal tray 59 without being detected by the inserted medal detection sensor 45a. In step S411, a lottery process for drawing lots for a winning combination in the current game (hereinafter also referred to as a winning combination lottery process) is executed, and in step S412, a reel control process for driving and controlling each of the reels 32L, 32M, 32R in a manner corresponding to the result of the winning combination lottery process is executed.

[0140] Here, the details of the reel control process will be explained below. In the reel control process, first, a rotation start process is performed to start the rotation of each of the reels 32L, 32M, and 32R. In the rotation start process, it is confirmed whether a predetermined waiting time (for example, 4.1 seconds) has elapsed since the start of rotation of the reels 32L, 32M, and 32R corresponding to the result of the lottery process for winning combinations (FIG. 11) in the previous game, and if not, the process waits until the waiting time has elapsed. The details of the lottery process for winning combinations will be explained later.

[0141] When the wait time has elapsed, the control IC 148 resets the wait time for the next game and sets rotation start information in the motor control storage area provided in the main RAM 144. By performing this process, the stepping motor acceleration process is initiated in the stepping motor control process of step S207 in the timer interrupt process (FIG. 8), and each of the reels 32L, 32M, and 32R begins to rotate. Thereafter, the control IC 148 waits until each of the reels 32L, 32M, and 32R rotates at a predetermined constant speed, and then ends the rotation start process. Furthermore, when the rotation speed of each of the reels 32L, 32M, and 32R reaches the constant speed, the control IC 148 lights up lamps (not shown) of each of the stop buttons 42 to 44, thereby informing the player that it is now possible to issue a stop command.

[0142] Thereafter, it is determined that a stop command has been issued, provided that one of the stop buttons 42 to 44 has been operated and that the operated stop button 42 to 44 is the stop button 42 to 44 that corresponds to the spinning reel. The MPU 152 waits until the conditions for issuing a stop command are met, and if a stop command is issued, it sets a stop command command. The stop command command is a command that causes the sub-side MPU 152 to recognize which of the stop buttons 42 to 44 has been operated to issue the stop command. If the stop command command is set, it performs stop control processing to stop the spinning reel.

[0143] In the stop control process, the symbol number of the reaching symbol that has reached the base position (the lower row in this embodiment) at the timing when the stop buttons 42 to 44 are operated is confirmed. Specifically, the symbol number of the reaching symbol that has reached the base position is confirmed based on the number of excitation pulses output from the time when the detection signal of the reel index sensor is input. After that, the number of slips of the reel that should be stopped this time is calculated based on the stop information stored in the main RAM 144.

[0144] In this slot machine 10, as the stop mode for stopping each reel 32L, 32M, 32R when the stop button 42-44 is operated, there are five stop modes available: a stop mode for stopping the reached symbol that has reached the base position as it is, a stop mode for stopping the corresponding reel after sliding it by one symbol, a stop mode for stopping it after sliding it by two symbols, a stop mode for stopping it after sliding it by three symbols, and a stop mode for stopping it after sliding it by four symbols. In this stop control process, one of the values ​​"0" to "4" is calculated as the number of slips based on the stop information stored in the main RAM 144.

[0145] Then, the calculated slip count is added to the symbol number of the reached symbol to determine the symbol number of the stop symbol that will actually stop at the base position. Then, it is determined whether the symbol number of the reached symbol of the reel to be stopped this time is equal to the symbol number of the stop symbol, and if so, a reel stop process is performed to stop the reel rotation. Then, it is determined whether all reels 32L, 32M, and 32R have stopped. If all reels 32L, 32M, and 32R have not stopped, a second stop information setting process is performed, and the process waits until the conditions for issuing a stop command are met. If a stop command is issued, a stop command command is set again and stop control process is performed.

[0146] Here, the stop information is information for making the stop mode of each reel 32L, 32M, 32R correspond to the result of the lottery process for winning combinations (FIG. 11). By using the stop information, it is possible to calculate the number of slips (specifically, "0" to "4") for the reaching symbol that has reached the base position when each stop button 42 to 44 is operated to stop. As the stop information, slip number data indicating the correspondence between each symbol and the number of slips is stored in advance in the main ROM 143 in correspondence with each lottery result and the stop order of each reel 32L, 32M, 32R. However, without being limited thereto, the slip number data corresponding to each lottery result and the stop order of each reel 32L, 32M, 32R may be derived during the rotation of the reels 32L, 32M, 32R.

[0147] The processes for setting the stop information include a first stop information setting process executed in step S509 of the lottery process (FIG. 11) described below, and a second stop information setting process executed in this reel control process. In the first stop information setting process, stop information is set according to the result of the lottery process for winning combinations. In the second stop information setting process, the stop information stored in the main RAM 144 in the first stop information setting process or the previous second stop information setting process is changed after the reels have stopped. In the second stop information setting process, stop information is changed based on the set winning data, the stop order of the reels 32L, 32M, and 32R, and the stop results of the stopped reels 32L, 32M, and 32R.

[0148] If it is determined that all reels 32L, 32M, and 32R have stopped, a win determination process is executed. In the win determination process, the type of symbols stopped on the main line ML on each reel 32L, 32M, and 32R is identified. If the combination of symbols stopped and displayed on the main line ML on each reel 32L, 32M, and 32R is a combination of symbols corresponding to a winning combination in the current combination lottery process, a winning combination is established and a win response process is executed. In the win response process, if the winning combination is a small combination, the number of medals to be paid out is set in the main RAM 144 so that game media can be awarded in the media award process. On the other hand, if the winning combination is a replay combination, a flag setting process is executed to enable the automatic insertion process to be executed in the next start waiting process (the process of step S402 in the normal process (FIG. 10)).

[0149] After the winning determination process is executed, a winning result command is set as an output target to the sub-MPU 152. The winning result command includes data indicating whether or not a win has been achieved this time, and if a win has been achieved, includes data indicating the type of win. The winning result command also includes data indicating whether the lottery mode when this game is over will be the normal mode, the first RT mode, or the second RT mode.

[0150] Returning to the explanation of the normal processing (FIG. 10), after the reel control processing is performed in step S412, the medium provision processing is executed in step S413. In the medium provision processing, if a small win has been achieved in the current game, a process is executed to provide the player with a number of game media corresponding to the small win. Specifically, when virtual medals are to be provided, a value corresponding to the current small win is added to the credit counter provided in the main RAM 144, and if the value of the credit counter has reached the upper limit of the number of medals that can be stored, the hopper device 53 is controlled and driven so that the number of medals exceeding the upper limit of the number of medals that can be stored is paid out to the medal tray 59.

[0151] After executing the medium provision process in step S413, a response process at the end of the game is executed in step S414 to enable the setting of the game status corresponding to the result of the current game, and an external output setting process is executed in step S415 to output the status of the slot machine 10 to the gaming hall's management computer. Then, in step S416, an acceptance permission process is executed, and the process returns to step S401. By executing the acceptance permission process, the medal inserted through the medal insertion slot 45 is detected by the inserted medal detection sensor 45a and then collected by the hopper device 53.

[0152] Next, the lottery process executed in step S411 of the normal process (FIG. 10) will be described with reference to the flowchart of FIG.

[0153] First, in step S501, a random number acquisition process is executed. In this random number acquisition process, a random number to be used when determining whether a winning combination has been achieved is acquired. Specifically, by acquiring the numerical information output from the Q terminals of the 16 latch register circuits 102a to 102p and input to the input terminal TA3 of the control IC 148, the numerical information of the random number, which is a 16-digit binary number, is acquired. In the following step S502, a lottery table for determining whether a winning combination has been achieved is read from the main ROM 143.

[0154] In this slot machine 10, six winning probabilities, from "Setting 1" to "Setting 6," are pre-set. By inserting a setting key into the setting key insertion hole 57, turning it ON, and performing a predetermined operation, the player can select which winning probability to use for the lottery process. Note that "Setting n+1" offers a higher winning probability than "Setting n." Even with the same setting value, the control IC 148 has three different lottery modes, namely, normal mode, first RT mode, and second RT mode. In addition to these lottery modes, a BB mode also exists as a game state. In step S502, a lottery table corresponding to the combination of the current setting value and the current game state is selected.

[0155] Taking the case of "setting 3" and non-BB state as an example, the lottery tables corresponding to the normal mode, the first RT mode, and the second RT mode will be explained. First, the lottery table for the normal mode selected in the case of the normal mode will be explained. Figure 12 is an explanatory diagram for explaining the lottery table for the normal mode. In the following explanation, the explanatory diagram of Figure 13 will be referred to as appropriate.

[0156] In the normal mode lottery table, as shown in Fig. 12, index values ​​IV are set, and each index value IV is associated with a winning combination and a point value PV is set. The point value PV determines the winning probability of the corresponding lottery combination in relation to the maximum value of the free run counter ("65535").

[0157] Specifically, bell winning data and first supplementary winning data are set for index value IV = 1. When a win occurs with index value IV = 1, as shown in Fig. 13, if the first stop (the reel on which the stop command was first issued) is the left reel 32L, a bell winning will definitely occur regardless of the types of the second and third stop target reels and the operation timing of each stop button 42 to 44, and in other cases, a first supplementary winning will definitely occur.

[0158] In the slot machine 10, reel control is performed on each of the reels 32L, 32M, and 32R, allowing up to four symbols to slide after the stop buttons 42-44 are operated. In other words, reel control is performed on each of the reels 32L, 32M, and 32R, allowing the reels 32L, 32M, and 32R to stop within a specified time (190 msec) after the stop buttons 42-44 are operated. This reel control makes it easier to achieve a winning combination corresponding to a winning symbol and prevents a winning combination corresponding to a non-winning symbol from being achieved. However, because the amount of rotation of the reels 32L, 32M, and 32R that can slide is limited as described above, if five or more symbols exist among the symbols that constitute a winning combination on one of the reels 32L, 32M, and 32R, depending on the timing of the operation of the corresponding stop button 42-44, the symbols may not stop on the main line ML (this phenomenon is also known as a "missed win"). The first to third supplementary wins, bell win, watermelon win and various replay wins are winning patterns that will not result in a miss if the reels 32L, 32M and 32R are stopped in the corresponding order, while the cherry win, first BB win and second BB win are winning patterns that may result in a miss depending on the timing of the stop operation of the stop buttons 42 to 44 relative to the rotation position of the reels 32L, 32M and 32R.

[0159] As shown in Fig. 12, bell winning data and second supplementary winning data are set for index value IV=2. When a win occurs with index value IV=2, as shown in Fig. 13, if the first stop is the center reel 32M, the bell winning is surely achieved regardless of the types of reels for the second and third stop targets and the operation timing of each stop button 42 to 44, and in other cases the second supplementary winning is surely achieved.

[0160] As shown in Fig. 12, bell winning data and third supplementary winning data are set for index value IV=3. When a win occurs with index value IV=3, as shown in Fig. 13, if the first stop is the right reel 32R, a bell winning is surely achieved regardless of the types of reels targeted for the second and third stops and the operation timing of each stop button 42 to 44, and in other cases, a third supplementary winning is surely achieved.

[0161] As shown in Fig. 12, only the watermelon winning data is set for index value IV=4. When a win occurs with index value IV=4, the watermelon winning is achieved regardless of the stopping order of the reels 32L, 32M, and 32R, as shown in Fig. 13. Also, when a win occurs with index value IV=4, the watermelon winning is achieved with certainty regardless of the operation timing of each stop button 42 to 44.

[0162] As shown in Figure 12, only cherry winning data is set for index value IV=5. If a win occurs with index value IV=5, a cherry winning can be achieved regardless of the stopping order of the reels 32L, 32M, and 32R, as shown in Figure 13. However, depending on the operation timing of the left stop button 42 relative to the rotation position of the left reel 32L, the cherry winning may not be achieved.

[0163] As shown in FIG. 12, first BB winning data is set for index value IV=6. When a win occurs with index value IV=6, the first BB winning can be achieved regardless of the stopping order of the reels 32L, 32M, and 32R, as shown in FIG. 13. However, depending on the operation timing of the stop buttons 42 to 44, the first BB winning may not be achieved. Also, as shown in FIG. 12, second BB winning data is set for index value IV=7. When a win occurs with index value IV=7, the second BB winning may be achieved regardless of the stopping order of the reels 32L, 32M, and 32R, as shown in FIG. 13. However, depending on the operation timing of the stop buttons 42 to 44, the second BB winning may not be achieved.

[0164] Here, winning data other than the first BB winning data and the second BB winning data is erased in the game in which a win occurs, regardless of whether a win is achieved or not, and is not carried over to games following the game in which the win occurred. In contrast, the first BB winning data and the second BB winning data are stored and held until the corresponding BB winning occurs, even in games following the game in which a win occurred, except when the master RAM 144 is cleared. In this case, in a game in which the first BB winning data or the second BB winning data is carried over, the index values ​​IV corresponding to the first BB winning data and the second BB winning data are excluded from the lottery. This makes it possible to prevent new BB winning data from being stored even when the first BB winning data or the second BB winning data is already stored and held, and to prevent multiple BB winning data from being accumulated and stored.

[0165] As shown in Fig. 12, normal replay winning data and first real-time replay winning data are set for index values ​​IV = 8 to 11. In this case, if a win occurs with index value IV = 8, as shown in Fig. 13, if the first stop is the center reel 32M, the second stop (the reel on which the second stop command was issued) is the left reel 32L, and the third stop (the reel on which the last stop command was issued) is the right reel 32R, the first real-time replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. In other cases, the normal replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. Also, if a win occurs with index value IV = 9, if the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, the first real-time replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. In other cases, the normal replay winning is surely achieved regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=10, and the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the center reel 32M, then the first RT replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44, and in all other cases, the normal replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44. Furthermore, if a win occurs with index value IV=11, and the first stop is the right reel 32R, the second stop is the center reel 32M, and the third stop is the left reel 32L, then the first RT replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44, and in all other cases, the normal replay win is surely achieved regardless of the timing of operation of the stop buttons 42 to 44.

[0166] When the normal mode lottery table of Figure 12 is selected, the probability of winning when the index value IV = 1, the probability of winning when the index value IV = 2, and the probability of winning when the index value IV = 3 are each approximately 1 / 5.0, the probability of winning when the index value IV = 4 is approximately 1 / 77, the probability of winning when the index value IV = 5 is approximately 1 / 423, the probability of winning when the index value IV = 6 is approximately 1 / 131, the probability of winning when the index value IV = 7 is approximately 1 / 655, and the probability of winning when the index value IV = 8, the probability of winning when the index value IV = 9, the probability of winning when the index value IV = 10, and the probability of winning when the index value IV = 11 are each approximately 1 / 28.0.

[0167] Here, as already explained, in the lottery table for the normal mode, in addition to the normal replay winning data, first RT replay winning data is set as winning data for index values ​​IV=8 to 11 (see FIG. 12). The probability of winning for any of these index values ​​IV=8 to 11 is approximately 1 / 7.0. When a winning occurs for any of the index values ​​IV=8 to 11, if the stop order of the first, second, and third stops of the reels 32L, 32M, and 32R corresponds to the winning combination, a first RT replay win is achieved, and the lottery mode shifts from the normal mode to the first RT mode. When the lottery mode shifts to the first RT mode, the lottery table referred to in the lottery process (FIG. 11) becomes the lottery table for the first RT mode.

[0168] Next, the lottery table for the first RT mode that is selected when the first RT mode is in "setting 3" will be described. Figures 14 and 15 are explanatory diagrams for explaining the lottery table for the first RT mode.

[0169] In the lottery table for the first RT mode, as shown in Fig. 14, the winning combination data set for each of the index values ​​IV = 1 to 7 and the winning probabilities for each index value IV are the same as those in the lottery table for the normal mode (Fig. 12). In this case, a combination that allows the award of game media is set for the index values ​​IV = 1 to 5, and since the winning combination data and the winning probabilities set for each of the index values ​​IV = 1 to 5 are the same, the types of combinations that allow the award of game media and the winning probabilities for those combinations are the same in both the normal mode and the first RT mode. In addition, BB winning data is set for the index values ​​IV = 6 to 7, as in the lottery table for the normal mode, and the winning probabilities are the same as those in the lottery table for the normal mode. In other words, the probability of winning any of the BB combinations is the same in both the normal mode and the first RT mode.

[0170] The winning combination data set for index values ​​IV=8 and above differs from that in normal mode. Specifically, in the lottery table for the first RT mode, as shown in FIG. 14, second RT replay winning data is set as winning data for index values ​​IV=8 to 11 in addition to normal replay winning data. The probability of winning any of these index values ​​IV=8 to 11 is approximately 1 / 10.1. When a winning combination occurs with index value IV=8, as shown in FIG. 15, if the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, the second RT replay winning will occur regardless of the operation timing of the stop buttons 42 to 44; otherwise, the normal replay winning will occur regardless of the operation timing of the stop buttons 42 to 44. Furthermore, if a win occurs with index value IV=9, and the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, the second RT replay prize will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in all other cases, a normal replay prize will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=10, and the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the center reel 32M, the second RT replay prize will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in all other cases, a normal replay prize will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=11, if the first stop is the right reel 32R, the second stop is the middle reel 32M, and the third stop is the left reel 32L, the second RT replay winning will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in all other cases, a normal replay winning will definitely occur regardless of the timing of operation of each stop button 42 to 44.In the first RT mode, when a win occurs with index value IV=8 to 11 and the first, second and third stops of the reels 32L, 32M and 32R are in the order of stops corresponding to the winning combination, a second RT replay win is established and the lottery mode shifts from the first RT mode to the second RT mode. When the lottery mode shifts to the second RT mode, the lottery table referred to in the lottery process (FIG. 11) becomes the lottery table for the second RT mode.

[0171] 14, in the lottery table for the first RT mode, in addition to the normal replay winning data, the first fall replay winning data is set as the winning data for the index value IV = 12 to 17. The probability of winning any of these index values ​​IV = 12 to 17 is approximately 1 / 10.9.

[0172] 15, if the first stop is the left reel 32L, the second stop is the center reel 32M, and the third stop is the right reel 32R, the normal replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44, and in any other cases the first fall replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44. Also, if the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the center reel 32M, the normal replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44, and in any other cases the first fall replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44. Furthermore, if a win occurs with index value IV=14, and the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a first fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=15, and the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a first fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=16, if the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a first fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44.Also, if a win occurs with index value IV=17, if the first stop is the right reel 32R, the second stop is the center reel 32M, and the third stop is the left reel 32L, a normal replay prize will occur regardless of the timing of operation of each stop button 42-44, and in all other cases, a first fall replay prize will occur regardless of the timing of operation of each stop button 42-44. If a first fall replay prize is achieved, the lottery mode will transition to normal mode. When transitioning to normal mode, the lottery table referenced in the lottery process (FIG. 11) will be the normal mode lottery table.

[0173] In the lottery table for the first RT mode, only normal replay winning data is set for index value IV=18. The probability of winning at index value IV=18 is set higher than the probability of winning other roles, specifically, the winning rate is approximately 1 in 6.7. If a win occurs at index value IV=18, a normal replay win will be achieved regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stopping operation of each reel 32L, 32M, and 32R.

[0174] In the lottery table for the first RT mode, combinations that enable the establishment of a replay win are set for index values ​​IV = 8 to 18. Since the winning probabilities of these combinations are set to the probabilities already explained, the winning probability of combinations that enable the establishment of a replay win in the first RT mode (hereinafter also referred to as the replay probability) is approximately 1 / 2.9. In contrast, the replay probability in the normal mode is approximately 1 / 7.0. In other words, the first RT mode is a gaming state in which the replay probability is higher than in the normal mode.

[0175] Next, the lottery table for the second RT mode that is selected when the "setting 3" is the second RT mode will be described. Figures 16 and 17 are explanatory diagrams for explaining the lottery table for the second RT mode.

[0176] In the lottery table for the second RT mode, as shown in FIG. 16, the winning combination data set for each of the index values ​​IV=1 to 7 and the winning probabilities for each index value IV are the same as those in the lottery table for the normal mode (FIG. 12) and the lottery table for the first RT mode (FIG. 14). In this case, a combination that allows the award of game media is set for the index values ​​IV=1 to 5, and since the winning combination data and the winning probabilities set for each of the index values ​​IV=1 to 5 are the same, the types of combinations that allow the award of game media and the winning probabilities for those combinations are the same in the normal mode, the first RT mode, and the second RT mode. In addition, BB winning data is set for the index values ​​IV=6 to 7, similar to the lottery table for the normal mode and the lottery table for the first RT mode, and the winning probabilities are the same as those in the lottery table for the normal mode and the lottery table for the first RT mode. In other words, the probability of winning any of the BB combinations is the same in the normal mode, the first RT mode, and the second RT mode.

[0177] The winning combination data set for index value IV=8 and onwards differs from those in the normal mode and the first RT mode. In detail, in the lottery table for the second RT mode, as shown in Fig. 16, second fall replay winning data is set as winning data for index value IV=8 to 13 in addition to normal replay winning data. The probability of winning any of these index values ​​IV=8 to 13 is approximately 1 / 5.5.

[0178] 17, if the first stop is the left reel 32L, the second stop is the center reel 32M, and the third stop is the right reel 32R, the normal replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44, and in any other cases the second fall replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44. Also, if the first stop is the left reel 32L, the second stop is the right reel 32R, and the third stop is the center reel 32M, the normal replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44, and in any other cases the second fall replay prize will be sure to occur regardless of the timing of operation of the stop buttons 42 to 44. Furthermore, if a win occurs with index value IV=10, and the first stop is the center reel 32M, the second stop is the left reel 32L, and the third stop is the right reel 32R, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a second fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=11, and the first stop is the center reel 32M, the second stop is the right reel 32R, and the third stop is the left reel 32L, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a second fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44. Furthermore, if a win occurs with index value IV=12, if the first stop is the right reel 32R, the second stop is the left reel 32L, and the third stop is the middle reel 32M, a normal replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44, and in any other cases, a second fall replay win will definitely occur regardless of the timing of operation of each stop button 42 to 44.Also, if a win occurs with index value IV=13, and the first stop is the right reel 32R, the second stop is the center reel 32M, and the third stop is the left reel 32L, a normal replay win will occur regardless of the timing of operation of each stop button 42-44, and in all other cases, a second fall replay win will occur regardless of the timing of operation of each stop button 42-44. If a second fall replay win is achieved, the lottery mode will shift to the first RT mode. When the lottery mode is shifted to the first RT mode, the lottery table referenced in the lottery process (FIG. 11) will be the lottery table for the first RT mode.

[0179] In the lottery table for the second RT mode, only normal replay winning data is set for index value IV=14. The probability of winning at index value IV=14 is set higher than the probability of winning other roles, specifically, the winning rate is approximately 1 in 6.3. If a win occurs at index value IV=14, a normal replay win will be achieved regardless of the stopping order of reels 32L, 32M, and 32R and the timing of the stopping operation of each reel 32L, 32M, and 32R.

[0180] In the lottery table for the second RT mode, combinations that enable the realization of a replay win are set for index values ​​IV = 8 to 14. Since the winning probabilities of these combinations are set as already explained, the winning probability of combinations that enable the realization of a replay win in the second RT mode (hereinafter also referred to as the replay probability) is approximately 1 / 2.9. In contrast, the replay probability in the normal mode is approximately 1 / 7.0. In other words, the second RT mode is a gaming state with a higher replay probability than the normal mode. Meanwhile, the replay probability in the first RT mode is approximately 1 / 2.9. In other words, the replay probability in the second RT mode is the same as that in the first RT mode. However, this is not limited to a configuration in which the replay probability in the first RT mode is the same as the replay probability in the second RT mode; for example, the replay probability may be slightly different between the first RT mode and the second RT mode but may be approximately the same, or the replay probability may be higher in the second RT mode than in the first RT mode, or the replay probability may be higher in the first RT mode than in the second RT mode.

[0181] The lottery table for the normal mode, the lottery table for the first RT mode, and the lottery table for the second RT mode are set in a one-to-one correspondence with each of "Setting 1" to "Setting 6," and the higher the setting value, the higher the probability of winning the BB role. However, the replay probability set in each lottery mode is the same or approximately the same regardless of the setting value. Also, if any of the BB roles has been won, the first BB role and the second BB role are excluded from the lottery target regardless of whether it is the normal mode, the first RT mode, or the second RT mode, so that the BB role is not won twice. In addition to the lottery table for the normal mode, the lottery table for the first RT mode, and the lottery table for the second RT mode, the main ROM 143 also stores a BB lottery table that is referenced in the lottery process (FIG. 11) when the first BB state or the second BB state is in effect. In the BB lottery table, only three types of roles are set as the roles to be selected: Bell, Watermelon, and Regular Replay, and the probability of winning the Bell role is set to approximately 1 / 2, the probability of winning the Watermelon role is set to approximately 1 / 4, and the probability of winning the Regular Replay role is set to approximately 1 / 4. As a result, the expected number of game media awarded per unit number of games in the BB state is higher than in other game states.

[0182] Returning to the explanation of the lottery process (FIG. 11), after selecting a lottery table in step S502, the index value IV is set to "1" in step S503, and a judgment value DV to be used when determining whether a winning combination has been achieved is set in step S504. In this judgment value setting process, a point value PV corresponding to the current index value IV is added to the current judgment value DV to set a new judgment value DV. Note that in the first judgment value setting process, the random number value acquired in step S501 is set as the current judgment value DV, and the point value PV corresponding to the current index value IV of "1" is added to this random number value to set a new judgment value DV.

[0183] In the following step S505, a judgment is made as to whether the combination corresponding to the index value IV has been won or not. In the judgment of whether the combination has been won or not, it is judged whether or not the judgment value DV has exceeded "65535". If it has exceeded "65535" (step S505: YES), in step S506, a winning data acquisition process is executed to set the winning combination data corresponding to the index value IV at that time in the master RAM 144. In the winning data acquisition process, all of the winning data set for the current index value IV in the lottery table being referenced is set in the master RAM 144. If the winning data is winning data other than BB winning data, the set state of the winning data is cleared to "0" after the end of the current game regardless of whether a win corresponding to the winning data has been achieved or not, and if it is BB winning data, it is cleared to "0" if a win is achieved.

[0184] If the judgment value DV does not exceed "65535" (step S505: NO), it means that the winning combination corresponding to the index value IV has not been achieved. In such a case, in step S507, 1 is added to the index value IV, and in step S508, it is determined whether or not there is a winning combination corresponding to the index value IV, i.e., whether or not there is a target for judgment as to whether it is a winning combination. Specifically, it is determined whether or not the index value IV to which 1 has been added exceeds the maximum value of the index value IV set in the lottery table. If there is a target for judgment as to whether it is a winning combination, the process returns to step S504, and the judgment of the winning combination continues. At this time, in step S504, the point value PV corresponding to the current index value IV is added to the judgment value DV used to judge whether or not the previous winning combination was achieved (i.e., the current judgment value DV) to obtain a new judgment value DV, and in step S505, the winning combination is judged based on the judgment value DV.

[0185] When the process of step S506 is executed, or when a negative determination is made in step S508, it means that the judgment of the winning or losing of the winning combination has been completed. In this case, in step S509, a first stop information setting process is executed to set stop information for reel stop control. The stop information set here is information for making the stopping pattern of each of the reels 32L, 32M, and 32R correspond to the result of the lottery process for the winning combination.

[0186] In the following step S510, a game start command is set as a command to be sent to the sub-side MPU 152. The game start command is a command for making the sub-side MPU 152 recognize that a new game has started, and is a command for making the sub-side MPU 152 recognize the result of the lottery process for the current winning combination in the control IC 148, and is sent to the sub-side MPU 152 in the command output process (step S212) in the timer interrupt process (FIG. 8).

[0187] Next, the end-of-game response process executed in step S414 of the normal process (FIG. 10) will be described with reference to the flowchart in FIG. 18. The end-of-game response process is executed when all of the reels 32L, 32M, and 32R have stopped spinning in each game.

[0188] First, in step S601, in a situation where the first BB role or the second BB role has been won, it is determined whether or not a winning combination corresponding to the winning BB role has been achieved. If the corresponding winning combination has been achieved (step S601: YES), then in step S602, BB start processing is executed. In the BB start processing, if the first BB winning combination has been achieved, the first BB flag provided in the main RAM 144 is set to "1," and the end reference number counter provided in the main RAM 144 is set to "41," which is the end reference number for the first BB state. On the other hand, if the second BB winning combination has been achieved, the second BB flag provided in the main RAM 144 is set to "1," and the end reference number counter in the main RAM 144 is set to "89," which is the end reference number for the second BB state.

[0189] The first BB flag is a flag for the control IC 148 to identify the first BB state, and the second BB flag is a flag for the control IC 148 to identify the second BB state. When the first BB flag or the second BB flag is set to "1," the BB lottery table is referenced in the winning combination lottery process (FIG. 11). The termination reference number counter is a counter for the control IC 148 to identify whether the total number of game media awarded in the BB state has reached the termination reference number, which is the condition for terminating the BB state. Each time a winning event that results in the award of game media is achieved in the BB state, the value set in the termination reference number counter is subtracted by the number of game media awarded by that winning event. Then, if the value of the termination reference number counter after the subtraction becomes "0," the control IC 148 determines that the rotation of the reels 32L, 32M, and 32R of the final game in the current BB state has stopped. In addition, when a winning combination that awards a predetermined number of game media is achieved in BB state, the predetermined number of game media will be awarded even if the value of the termination reference counter becomes "0" when a portion of the predetermined number is subtracted from the termination reference counter.

[0190] If a negative determination is made in step S601, it is determined in step S603 whether the state is either the first BB state or the second BB state, and if the state is either the first BB state or the second BB state (step S603: YES), BB processing is executed in step S604, and the corresponding processing at the time of ending this game is terminated. In the BB processing, if the awarding of game media has occurred in the current game, the value of the end reference number counter in the main RAM 144 is subtracted accordingly, and if the value of the end reference number counter after subtraction is "0", processing is executed to end the BB state.

[0191] If the state is not BB and a BB win has not been achieved (step S601 and step S603: NO), it is determined in step S605 whether or not the promotion condition is met, and if the promotion condition is met (step S605: YES), a lottery table change process at the time of promotion is executed in step S606, and the corresponding process at the end of this game is terminated. Specifically, if it is determined that a first RT replay win has occurred in the current game, the lottery table to be used in the lottery process for the winning combination is changed to the lottery table for the first RT mode, thereby transitioning to the first RT mode, and if it is determined that a second RT replay win has occurred in the current game, the lottery table to be used in the lottery process for the winning combination is changed to the lottery table for the second RT mode, thereby transitioning to the second RT mode.

[0192] If a negative determination is made in step S605, then in step S607 it is determined whether or not the fall condition is met, and if the fall condition is not met (step S607: NO), the response process at the end of this game is terminated. If the fall condition is met (step S607: YES), then in step S608, a process for changing the lottery table at the time of fall is executed, and the response process at the end of this game is terminated. Specifically, if it is determined that a second fall replay winning has occurred in the current game, the lottery table to be used in the lottery process for the winning combination is changed to the lottery table for the first RT mode, thereby transitioning to the first RT mode, and if it is determined that a first fall replay winning has occurred in the current game, the lottery table to be used in the lottery process for the winning combination is changed to the lottery table for the normal mode, thereby transitioning to the normal mode.

[0193] <Management operations in the control CPU 114> Next, the management operation in the control CPU 114 will be described with reference to the flowchart of FIG.

[0194] First, in step S701, the process waits until the detection signal SG1 input to the control-side CPU 114 goes to a LOW state. If the detection signal SG1 input to the control-side CPU 114 goes to a LOW state (step S701: YES), the process waits in step S702 until the detection signal SG1 input to the control-side CPU 114 goes to a HI state. If the detection signal SG1 input to the control-side CPU 114 goes to a HI state (step S702: YES), the process proceeds to step S703. In other words, if the control-side CPU 114 detects a rise in the detection signal SG1 input to the control-side CPU 114 from a LOW state to a HI state, the process proceeds to step S703.

[0195] In step S703, a timer counter is used to start counting the time that the detection signal SG1 input to the control side CPU 114 continues to be in a HI state. The time that the HI state continues is counted in units of 0.1 μs. In step S704, it is determined whether the detection signal SG1 is in a HI state, and if it is in a HI state (step S704: YES), in step S705 it is determined whether 12.8 μs has elapsed since the detection signal SG1 input to the control side CPU 114 became a HI state.

[0196] In step S705, if 12.8 μs has not elapsed since the detection signal SG1 input to the control side CPU 114 became HI, the process returns to the determination in step S704. Then, in step S705, if 12.8 μs has elapsed since the detection signal SG1 input to the control side CPU 114 became HI, the process proceeds to step S706.

[0197] In step S706, the timer counter is stopped from counting the time and reset, and in step S707, a latch signal, which is a pulse signal, is sent to the CLK terminals of the latch register circuits 102a to 102p, causing the numerical information of the random number stored in the random number counter 105 to be written to the latch register 102.

[0198] In the following step S708, the latched status 113 is set to "1", and the process returns to step S701. More specifically, the control-side CPU 114 raises the signal output from the output terminal TB3 to the T terminal 113b of the latched status 113, on the condition that the signal output from the Q terminal 113a of the latched status 113 and input to the input terminal TB2 of the control-side CPU 114 is in a LOW state. This sets the latched status 113 to "1". Furthermore, if the signal output from the Q terminal 113a of the latched status 113 and input to the input terminal TB2 of the control-side CPU 114 is in a HI state, the signal output from the output terminal TB3 to the T terminal 113b of the latched status 113 is maintained. This maintains the state in which the latched status 113 is set to "1".

[0199] Furthermore, if a negative determination is made in step S704, that is, if the detection signal SG1 input to the control-side CPU 114 returns to a low state before 12.8 μs has elapsed since the detection signal SG1 went high, it is considered that the detection signal SG1 rose due to short noise of less than 12.8 μs being mixed into the input terminal of the control-side CPU 114. In this case, in step S709, the timer counter stops counting the time and is reset, and the process returns to step S702.

[0200] In this way, the control-side CPU 114 sets the latched status 113 to "1" on the condition that it detects the rising edge of the detection signal SG1 input to the control-side CPU 114. Therefore, even when the start lever 41 is pressed down and the pressing operation continues for a long time, a latch signal, which is a pulse signal, is sent to the CLK terminal of the latch register circuits 102a to 102p in response to one pressing operation, and the latched status 113 is set to "1" only once. Even if the start lever 41 is pressed down for a long time, the latch signal is not sent repeatedly.

[0201] Furthermore, the control-side CPU 114 sets the latched status 113 to "1" even during a game. However, the control IC 148 is configured to set the start command flag 144c to "1" in the start command setting process (FIG. 9), with one condition being that the game is ready to start. Then, in the normal process (FIG. 10), the control IC 148 is configured to clear the latched status 113 to "0" when the start timing of the period when the game is ready to start arrives. For this reason, even if the latched status 113 is set to "1" during a game, this does not trigger the setting of the start command flag 144c to "1."

[0202] <Timing at which the control IC 148 acquires the random number> Next, the timing at which the control IC 148 acquires a random number will be described with reference to the time charts of FIGS.

[0203] First, a slot machine that does not have the latched status 113 will be described with reference to Figure 20. This slot machine will be referred to as a first slot machine for comparison. The first slot machine for comparison differs from the slot machine 10 of this embodiment in that it does not have the latched status 113.

[0204] Figure 20 is a time chart for explaining the timing at which the control IC acquires a random number from the latch register in the first slot machine for comparison. Figure 20(a) shows the state of the detection signal input to the control IC, Figure 20(b) shows the state of the signal storage flag, Figure 20(c) shows the state of the detection signal input to the control CPU, Figure 20(d) shows the timing at which the random number stored in the random number counter is written to the latch register, Figure 20(e) shows the timing at which the start command setting process (Figure 9) is executed in the control IC, and Figure 20(f) shows the timing at which the control IC acquires the random number output from the latch register and input to the input terminal of the control IC.

[0205] As shown in Figures 20(a) and (c), when a player operates the start lever, the detection signal input to the control IC and the control CPU rises from a LOW state to a HIGH state at time t1. The control CPU sends a latch signal to the latch register at time t4, 12.8 μs after the input detection signal rises. As shown in Figure 20(d), at time t4 when the latch register receives the latch signal, the numerical information of the random number stored in the random number counter is written to the latch register.

[0206] As shown in FIG. 20(e), the start command setting process is performed at t2, which is after t1 when the detection signal rises and before t4 when the random number numerical information is written to the latch register. As shown in FIG. 20(a), the detection signal input to the control IC is in a HI state at t2. Therefore, as shown in FIG. 20(b), the control IC sets the signal memory flag to "1" at t2. This indicates that the control IC has detected the rising edge of the detection signal. Therefore, as shown in FIG. 20(f), in the lottery process (FIG. 11) executed at t3, which is after t2 and before t4, the control IC acquires the random number numerical information input to the input terminal of the control IC.

[0207] The timing t3 at which the control IC acquires the numerical information of the random number precedes the timing t4 at which the random number corresponding to this start lever operation is written to the latch register, so the control IC acquires the numerical information of the random number written to the latch register before this start lever operation. In this way, if the latched status 113 is not used, a random number that does not correspond to the start lever operation may be used to determine whether the winning combination is correct or not.

[0208] For example, after a player has achieved a favorable game result, a possible fraudulent move would be to raise the detection signal from LOW to HI so that the start command setting process is performed before the random number corresponding to the operation of the start lever is written to the latch register. If such fraud is committed, the control IC will obtain the same random number information as the previous time. This poses the problem of the player being able to continue to achieve a favorable game result through fraud.

[0209] As shown in Figures 20(a) and (c), at time t5, which is after time t4, the detection signal input to the control IC and the control-side CPU falls from a HIGH state to a LOW state. Then, as shown in Figure 20(e), at time t6, the start command setting process is executed. As shown in Figure 20(a), the detection signal input to the control IC is in a LOW state at time t6. Therefore, as shown in Figure 20(b), the control IC clears the signal storage flag to "0" at time t6.

[0210] After time t6, the game played using the random number acquired by the control IC at time t2 ends, and the game can be restarted. Then, as shown in Figure 20(a), at time t7 after time t6, the detection signal input to the control IC rises from a LOW state to a HIGH state. However, as shown in Figure 20(c), the detection signal input to the control CPU 114 does not rise at time t7.

[0211] Therefore, as shown in Figure 20(d), the rising edge of the detection signal at time t7 does not trigger the writing of new random number numerical information to the latch register, and the numerical information stored in the latch register remains the same as the random number numerical information written at time t4.

[0212] As shown in Figure 20(e), the start command setting process is executed at t8, which is between t7, when the detection signal input to the control IC rises, and t10, when the detection signal input to the control IC falls. As shown in Figure 20(a), the detection signal input to the control IC is in a HI state at t8. Therefore, as shown in Figure 20(b), the control IC sets the signal memory flag to "1" at t8. This means that the control IC has detected the rising edge of the detection signal input to the control IC.

[0213] As shown in Figure 20(f), the control IC acquires the random number input to the input terminal of the control IC during the lottery process (Figure 11) that is executed at t9, which is after t8 when the rising edge of the detection signal is detected and before t10. The numerical information of the random number acquired at t9 is the numerical information of the random number written from the random number counter to the latch register at t4.

[0214] As explained for t7 to t10, when the detection signal input to the control CPU does not rise and only the detection signal input to the control IC rises, a problem occurs in a slot machine that does not have the latched status 113. For example, when noise is mixed only into the input terminal of the control IC, the noise may trigger the start of the game. Also, when the start lever is operated while the signal line connecting the start detection sensor and the control CPU is disconnected, the winning combination may be determined based on an old random number that does not correspond to the timing of the current start lever operation.

[0215] Next, we will explain a case where a slot machine that does not have the latched status 113 detects the rising edge of the detection signal input to the control IC and acquires the numerical information of the random number input to the control IC on the condition that the detection signal is confirmed to be in the HI state twice in a row. In the following explanation, this slot machine will be referred to as the second slot machine for comparison.

[0216] The second slot machine for comparison differs from the slot machine 10 of this embodiment in that it does not have a latched status 113, and in that, during the start command setting process (Figure 9) which is executed three times in succession, it acquires numerical information of the random number input to the input terminal of the control IC on the condition that the detection signal input to the control IC changes from LOW state → HI state → HI state.

[0217] The timing at which the control IC of the second slot machine for comparison acquires the numerical information of the random number input to the input terminal of the control IC will be explained with reference to the time chart in Figure 21. Figure 21(a) shows the state of the detection signal input to the control IC, Figure 21(b) shows the state of the detection signal input to the control CPU, Figure 21(c) shows the timing at which the numerical information of the random number stored in the random number counter is written to the latch register, Figure 21(d) shows the timing at which the start command setting process is executed in the control IC, Figure 21(e) shows the timing at which the control IC acquires the numerical information of the random number input to the input terminal of the control IC, and Figure 21(f) shows the connection state between the start detection sensor and the control CPU.

[0218] As shown in Figure 21(a), the start command setting process is executed at timing t1. As shown in Figure 21(f), at timing t1, the start detection sensor and the control-side CPU are connected, and the detection signal output from the start detection sensor is input to the control-side CPU. Also, as shown in Figure 21(a), at timing t1, the detection signal input to the control IC is in a LOW state. After that, when the start lever is pressed down at timing t2, as shown in Figures 21(a) and 21(b), the detection signal input to the control IC and the detection signal input to the control-side CPU rise from a LOW state to a HIGH state.

[0219] As shown in Fig. 21(d), the start command setting process is executed at timing t3, which is 12.8 μs before timing t2. As shown in Fig. 21(a), the detection signal input to the control IC at timing t3 is in the HI state.

[0220] At time t4, which is after time t3 and 12.8 μs has elapsed since time t2, the control CPU determines that the detection signal input to the control CPU has risen from a low state to a high state and that this high state has been maintained for 12.8 μs or more. The control CPU then sends a latch signal to the CLK terminal of the latch register circuit. As a result, the random number information stored in the random number counter at time t4 is written to the latch register, as shown in Figure 21(c).

[0221] Thereafter, as shown in FIG. 21(d), a start command setting process is executed at timing t5. As shown in FIG. 21(a), the detection signal input to the control IC at timing t5 is in a HI state. Since the detection signals input to the control IC at timings t1, t3, and t5 change from a LOW state to a HI state and back to a HI state, as shown in FIG. 21(e), in the lottery process (FIG. 11) executed at timing t6 after timing t5, the control IC acquires the numerical information of the random number input to the input terminal of the control IC and starts the game. The numerical information of the random number acquired by the control IC at timing t6 is the numerical information of the random number corresponding to the current operation of the start lever 41.

[0222] 21(a) and 21(b), the detection signal input to the control IC and the detection signal input to the control CPU each return to a LOW state at time t7, which is after time t6. The game also ends after time t7.

[0223] Thereafter, as shown in Fig. 21(d), the start command setting process is executed at timing t8. As shown in Fig. 21(a), the detection signal input to the control IC at timing t8 is in a LOW state.

[0224] If the start lever is subsequently pressed insufficiently, the detection signal input to the control IC and the detection signal input to the control-side CPU will both be in the HI state from time t9 to time t11, as shown in Figures 21(a) and 21(b). Here, the time interval from time t9 to time t11 is less than 12.8 μs. An insufficient press of the start lever refers to a press in which the start lever is held down for less than 12.8 μs.

[0225] In this case, the HI state of the detection signal input to the control CPU does not continue for 12.8 μs or more, so the insufficient pressing operation does not cause the control CPU to send a latch signal to the CLK terminal of the latch register circuit. Therefore, as shown in Figure 21, the random number information stored in the random number counter is not written to the latch register.

[0226] As shown in FIG. 21(d), the start command setting process is executed at timing t10, which is between timing t9 and timing t11. As shown in FIG. 21(a), the detection signal input to the control IC is in a HI state at timing t10. Then, after timing t11, noise is mixed only into the input terminal of the control IC. As a result, the detection signal input to the control IC is in a HI state from timing t12 to timing t15, as shown in FIG. 21(a).

[0227] In this case, as shown in Fig. 21(d), the start command setting process is executed at timing t13, which is between timing t12 and timing t15. As shown in Fig. 21(a), the detection signal input to the control IC at timing t13 is in a HI state.

[0228] Because the detection signal input to the control IC at times t8, t10, and t13 changed from LOW state to HIGH state and back to HIGH state, as shown in Figure 21(e), in the lottery process (Figure 11) executed at time t14 after time t13, the control IC acquires the numerical information of the random number input to the input terminal of the control IC and starts the game. As shown in Figure 21(c), from time t9 to time t14, the numerical information of the random number stored in the latch register was not updated. Therefore, the numerical information of the random number acquired by the control IC at time t14 is old numerical information of a random number that does not correspond to the current insufficient depression of the start lever 41.

[0229] In this way, if the start command setting process is executed both at the timing when the start lever 41 is pressed insufficiently and at the timing when noise is mixed into the input terminal of the control IC, the second slot machine being compared will determine whether the winning combination is successful or not based on the numerical information of the old random number.

[0230] As shown in Figure 21(f), at timing t16, which is after timing t15, the connection between the start detection sensor and the control-side CPU is cut off, resulting in a disconnection state. In this disconnection state, the detection signal output from the start detection sensor is input only to the control IC.

[0231] Thereafter, as shown in Figure 21(d), a start command setting process is executed at timing t17. Here, the game has already ended at timing t17, and the second slot machine under comparison is ready to start a game at timing t17. As shown in Figure 21(a), the detection signal input to the control IC at timing t17 is in a LOW state.

[0232] When the start lever is pressed at time t18, which is after time t17, the detection signal input to the control IC rises from a low state to a high state, as shown in Figure 21(a). However, as shown in Figure 21(f), the connection between the start detection sensor and the control CPU has been cut off since time t16. Therefore, as shown in Figure 21(b), the detection signal input to the control CPU does not rise at time t18.

[0233] As shown in Figure 21(d), at timing t19, the first start command setting process is executed after timing t18. As shown in Figure 21(a), the detection signal input to the control IC at timing t19 is in a HI state. Thereafter, as shown in Figure 21(d), at timing t20, the second start command setting process is executed after timing t18. As shown in Figure 21(a), the detection signal input to the control IC at timing t20 is in a HI state.

[0234] Because the detection signal input to the control IC at times t17, t19, and t20 changed from LOW state to HIGH state and back to HIGH state, the control IC acquires the numerical information of the random number input to the input terminal of the control IC in the lottery process (FIG. 11) executed at time t21, which is after time t20, as shown in FIG. 21(e), and starts the game. As shown in FIG. 21(c), the numerical information of the random number stored in the latch register was not updated between time t18 and time t21. Therefore, the numerical information of the random number acquired by the control IC at time t21 is the old numerical information of the random number that does not correspond to the current depression of the start lever.

[0235] In the second slot machine for comparison, which does not use the latched status 113, the control IC cannot grasp that the numerical information of the random number stored in the random number counter has been written to the latch register. For this reason, it is not possible to set the start command flag to "1" on the condition that the numerical information of the random number stored in the random number counter has been written to the latch register.

[0236] In slot machines that do not use the latched status 113, if the detection signal input to the control IC and the detection signal input to the control CPU behave differently due to noise, a broken wire, etc., the winning / losing of the winning combination is determined based on the numerical information of an old random number. In particular, if the connection between the start detection sensor and the control CPU is cut off, the winning / losing of the winning combination is repeatedly determined based on the numerical information of the same random number.

[0237] Next, the slot machine 10 of this embodiment in which the control IC 148 acquires a random number using the latched status 113 will be described with reference to FIG.

[0238] Figure 22 is a time chart illustrating the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Figure 22(a) shows the state of the detection signal SG1 input to the control IC 148, Figure 22(b) shows the state of the signal storage flag 144d (Figure 5), Figure 22(c) shows the state of the detection signal SG1 input to the control side CPU 114, Figure 22(d) shows the timing at which the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Figure 22(e) shows the state of the latched status 113, Figure 22(f) shows the timing at which the start command setting process (Figure 9) is executed in the control IC 148, Figure 22(g) shows the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148, and Figure 22(h) shows the state of the error counter 144b (Figure 5).

[0239] As shown in FIG. 22(a), during the game start possible period, noise is introduced into the input terminal TA1 of the control IC 148, causing the detection signal SG1 input to the control IC 148 to rise from a low state to a high state. As shown in FIG. 22(a), this high state continues until time t3. As shown in FIG. 22(f), the start command setting process is executed at time t2, which is between time t1 and time t3. As shown in FIG. 22(a), the detection signal SG1 input to the control IC 148 is in a high state at time t2. Therefore, as shown in FIG. 22(b), the control IC 148 sets the signal storage flag 144d to "1" at time t2. When the signal storage flag 144d changes from "0" to "1," the control IC 148 detects the rising edge of the detection signal SG1.

[0240] As shown in Figures 22(a) and 22(c), only the detection signal SG1 input to the control IC 148 rises at timing t1, and the detection signal SG1 input to the control-side CPU 114 does not rise. Therefore, as shown in Figure 22(e), the latched status 113 remains at "0" at timing t2. In the start command setting process performed at timing t2, the condition that the latched status 113 is set to "1" is not met, so as shown in Figure 22(g), the control IC 148 does not acquire numerical information of the random number. In this case, as shown in Figure 22(h), the control IC 148 increments the error counter 144b by "1" at timing t2.

[0241] In this way, by using the latched status 113, it is possible to avoid a situation where, when noise enters only the control IC 148, the control IC 148 acquires numerical information of an old random number input to the input terminal TA3 of the control IC 148 and determines whether the winning hand is successful or not based on the old random number. Also, when the signal line connecting the start detection sensor 41a and the control-side CPU 114 is disconnected, it is possible to avoid a situation where the control IC 148 repeatedly acquires numerical information of the same random number every time the start lever 41 is operated.

[0242] As shown in Fig. 22(a), after the detection signal SG1 input to the control IC 148 falls at timing t3, the start command setting process is executed at timing t4 as shown in Fig. 22(f). As shown in Fig. 22(a), the detection signal SG1 input to the control IC 148 is in a LOW state at timing t4, so the control IC 148 clears the signal storage flag 144d to "0" at timing t4 as shown in Fig. 22(b).

[0243] Thereafter, when the player operates the start lever 41 within the period in which the game can be started, the detection signal SG1 input to the control IC 148 and the control-side CPU 114 rises at timing t5, as shown in Figures 22(a) and (c). Here, timing t7 is the timing when 12.8 μs have elapsed since timing t5. As shown in Figure 22(c), at timing t7 when 12.8 μs have elapsed since the detection signal SG1 input to the control-side CPU 114 rose, the detection signal SG1 input to the control-side CPU 114 remains in the HI state.

[0244] Therefore, at timing t7, the control side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a to 102p. As a result, as shown in Fig. 22(d), at timing t7, the numerical information of the random number stored in the random number counter 105 is written to the latch register 102. Also, as shown in Fig. 22(e), the control side CPU 114 sets "1" to the latched status 113 at timing t7.

[0245] In this case, as shown in Figure 22(f), the start command setting process is executed at time t6, which is after time t5 and before time t7. As shown in Figure 22(a), the detection signal SG1 input to the control IC 148 is in a HI state at time t6, so the signal storage flag 144d is set to "1" at time t6, as shown in Figure 22(b). At time t6, when the signal storage flag 144d changes from "0" to "1," the control IC 148 detects the rising edge of the detection signal SG1.

[0246] However, as shown in Figure 22(e), at timing t6, the latched status 113 remains at "0." At timing t6, the condition that the latched status 113 is set to "1" is not met, so as shown in Figure 22(g), the control IC 148 does not acquire the numerical information of the random number. In this case, as shown in Figure 22(h), the control IC 148 adds "1" to the error counter 144b.

[0247] As shown in FIG. 22(f), the start command setting process is executed at time t8, which is later than time t7. As shown in FIG. 22(b), at time t8, the signal storage flag 144d has already been set to "1," and the control IC 148 does not detect the rising edge of the detection signal SG1 input to the control IC 148 at time t8. Therefore, in the start command setting process executed at time t8, the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113. As a result, the latched status 113 is cleared to "0" at time t8, as shown in FIG. 22(e).

[0248] In this way, in this slot machine 10 equipped with the latched status 113, even if the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control side CPU 114 rose from a LOW state to a HI state, it is possible to avoid a situation in which the control IC 148 obtains an old random number and determines whether the winning combination is correct or not based on that old random number.

[0249] In this configuration, even if a fraudulent attempt is made to raise the detection signal SG1 from a LOW state to a HIGH state so that the start command setting process is performed before the random number stored in the random number counter 105 is written to the latch register 102, the control IC 148 will not obtain the same random number as the previous time, resulting in an error. The number of consecutive errors is then counted by the error counter 144b. This makes it possible to prevent a situation in which a player continues to receive advantageous game results due to fraud.

[0250] If the condition for the control IC 148 to set the start command flag 144c to "1" is not met at the time the player operates the start lever 41, the player will need to operate the start lever 41 again. However, because the start command setting process is executed within the timer interrupt process (FIG. 8) which is executed every 1.49 ms, the frequency with which the start command setting process is executed within 12.8 μs after the player operates the start lever 41 is low. For this reason, the player will not frequently operate the start lever 41 again.

[0251] As shown in Figures 22(a) and 22(c), at time t9, which is later than time t8, the detection signal SG1 input to the control IC 148 and the control-side CPU 114 falls. Then, at time t10, which is later than time t9, the start command setting process is executed as shown in Figure 22(f). As shown in Figure 22(a), at time t10, the detection signal SG1 input to the control IC 148 is in a LOW state, so as shown in Figure 22(b), the control IC 148 clears the signal storage flag 144d to "0."

[0252] Thereafter, when the player operates the start lever 41 during the game start period, as shown in FIGS. 22(a) and 22(c), at time t11, the detection signal SG1 input to the control IC 148 and the control-side CPU 114 rises from a low state to a high state. As shown in FIG. 22(c), at time t12, 12.8 μs after the detection signal SG1 input to the control-side CPU 114 rises, the detection signal SG1 remains high. Therefore, at time t12, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a to 102p. As a result, as shown in FIG. 22(d), the random number information stored in the random number counter 105 is written to the latch register 102 at time t12. Furthermore, as shown in FIG. 22(e), the control-side CPU 114 sets the latched status 113 to "1" at time t12.

[0253] In this case, as shown in Fig. 22(f), the start command setting process is executed at timing t13, which is after timing t12. As shown in Fig. 22(a), the detection signal SG1 input to the control IC 148 is in a HI state at timing t13, so as shown in Fig. 22(b), the control IC 148 sets "1" to the signal storage flag 144d at timing t13. When the signal storage flag 144d changes from "0" to "1," the control IC 148 recognizes the rising edge of the detection signal SG1 input to the control IC 148.

[0254] As shown in Figure 22(e), at the timing t13 when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148, the latched status 113 is set to "1." Since the condition that the latched status 113 is set to "1" is satisfied at the timing when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148, the control IC 148 sets the start command flag 144c to "1." As shown in Figure 22(g), in the lottery process (Figure 11) executed at the timing t14 after the timing t13, the control IC 148 acquires numerical information of the random number input to the input terminal TA3 of the control IC 148 and uses it to determine whether the winning combination is a winning combination.

[0255] At timing t13 when the control IC 148 sets the start command flag 144c to "1", the control IC 148 clears the error counter 144b to "0" as shown in FIG. 22(h).

[0256] It is unlikely that the event of the start command setting process being performed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose is repeated. Even if this event occurs twice in a row, if the control IC 148 subsequently acquires numerical information of a random number corresponding to the operation of the start lever 41, the error counter 144b is cleared to "0." Therefore, the cases in which the value of the error counter 144b becomes "3" and the abnormality notification process (the process of step S311 of the start command setting process (FIG. 9)) is performed can be limited to almost all cases in which fraudulent attempts are made, such as changing the state of the detection signal SG1, and the connection between the start detection sensor 41a and the control-side CPU 114 is cut off.

[0257] Next, a case where noise of 12.8 μs or more enters only the control CPU 114 will be described with reference to the time chart of Fig. 23. Note that at the timings t1 to t4, the slot machine 10 is in a state where a game can be started.

[0258] Figure 23(a) shows the state of the detection signal SG1 input to the control IC 148, Figure 23(b) shows the state of the signal memory flag 144d, Figure 23(c) shows the state of the detection signal SG1 input to the control side CPU 114, Figure 23(d) shows the timing when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Figure 23(e) shows the timing when the start command setting process is executed in the control IC 148, Figure 23(f) shows the state of the latched status 113, and Figure 23(g) shows the timing when the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148.

[0259] 23(c), noise enters the input terminal TB1 of the control-side CPU 114, and only the detection signal SG1 input to the control-side CPU 114 rises from a LOW state to a HIGH state from the timing t1 to the timing t3. The timing t3 is later than the timing t2, which is 12.8 μs after the timing t1.

[0260] As shown in Figure 23(c), the detection signal SG1 input to the control-side CPU 114 rises at timing t1 and remains HI until timing t2, 12.8 μs after timing t1. Therefore, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a to 102p at timing t2. As a result, as shown in Figure 23(d), at timing t2, the numerical information of the random number stored in the random number counter 105 is written to the latch register 102. Also, as shown in Figure 23(f), the control-side CPU 114 sets "1" to the latched status 113 at the same timing t2.

[0261] As shown in Fig. 23(e), the start command setting process is executed at timing t4, which is after timing t3. As shown in Fig. 23(a), the detection signal SG1 input to the control IC 148 is in a LOW state at timing t4, and the rising edge of the detection signal SG1 is not detected by the control IC 148. In this case, as shown in Fig. 23(f), in the start command setting process executed at timing t4, the control IC 148 raises the signal output to the CLR terminal 113c of the latched status 113, thereby clearing the latched status 113 to "0."

[0262] In this way, even if the latched status 113 is set to "1" at timing t2 due to noise entering only the input terminal TB1 of the control side CPU 114, the latched status 113 is cleared to "0" in the start command setting process executed immediately thereafter at timing t4.

[0263] If the latched status 113 is not cleared to "0" at the timing of t4, three conditions may be met at a later timing: a period in which the game can be started, a rising edge of the detection signal SG1 input to the control IC 148 is detected, and "1" is set to the latched status 113. In contrast, by configuring the control IC 148 to clear the latched status 113 to "0" at the timing of t4, it is possible to reduce the possibility that the control IC 148 will use the random number written to the latch register 102 in response to noise to determine whether the winning combination is correct or not.

[0264] As described above, the control-side CPU 114 is configured to transmit a latch signal to the CLK terminal of the latch register circuits 102a-102p and set the latched status 113 to "1" when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102. The control IC 148 is also configured to acquire the numerical information of the random number input to the input terminal TA3 of the control IC 148 on the condition that the control IC 148 detects the rising edge of the detection signal SG1 when the game is ready to start and that the latched status 113 is set to "1" when the control IC 148 detects the rising edge of the detection signal SG1. This allows the numerical information of the random number acquired by the control IC 148 to be limited to the random number corresponding to the current operation of the start lever 41. This prevents the control IC 148 from acquiring an old random number and determining whether the winning combination is correct or not based on that old random number. By limiting the random number used to determine whether a winning combination is successful to the random number corresponding to the current operation of the start lever 41, it is possible to provide a gaming machine in which the winning combination is determined based on a random number that accurately reflects the player's actions.

[0265] Furthermore, the control-side CPU 114 is configured to transmit a latch signal to the latch register 102 at the timing when it determines that the detection signal SG1 input to the control-side CPU 114 has become HI and that this HI state has continued for 12.8 μs. Therefore, if the rising edge of the detection signal SG1 is caused by noise that is less than 12.8 μs, it is possible to prevent a random number from being written to the latch register 102 due to the noise.

[0266] The main RAM 144 also includes an error counter 144b. The error counter 144b counts the number of consecutive times that the latched status 113 is not set to "1" when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148 in a state where a game can be started. The control IC 148 performs an abnormality notification process when the value of the error counter 144b reaches "3." One possible cause of consecutive events in which the latched status 113 is not set to "1" when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148 is a disconnection between the start detection sensor 41a and the control CPU 114. By performing an abnormality notification when the value of the error counter 144b reaches "3," the gaming hall manager can be notified that there is a high possibility that a disconnection has occurred in the connection between the start detection sensor 41a and the control CPU 114.

[0267] Furthermore, if the start command setting process is executed within 12.8 μs after the detection signal SG1 input to the control-side CPU 114 rises, there is a possibility that the latched status 113 will be set to “1” after the start command setting process. Furthermore, if noise of 12.8 μs or more is mixed only into the input terminal of the control-side CPU 114, the latched status 113 will also be set to “1.” If the latched status 113 remains set to “1” for a long period of time, there is a high possibility that the start lever 41 will be operated while the latched status 113 is set to “1.” In this case, as in the case where the latched status 113 is not used, there is a possibility that the control IC 148 will obtain an old random number and determine whether the winning combination is successful or not based on that old random number. In contrast, by configuring the control IC 148 to clear the latched status 113 to “0” when the rising edge of the detection signal SG1 input to the control IC 148 is not detected during the start command setting process, the possibility of the control IC 148 obtaining an old random number can be reduced.

[0268] Furthermore, when the start lever 41 is operated during a game, a random number corresponding to the operation of the start lever 41 is written to the latch register 102, and the latched status 113 is set to "1." In contrast, by configuring the latched status 113 to be cleared to "0" at the start of the period in which the game can be started, it is possible to prevent the random number corresponding to the operation of the start lever 41 during the game from being used to determine whether the winning combination is a success or failure.

[0269] Furthermore, when the start lever 41 is operated under the condition that the latched status 113 is set to "1", the random number stored in the latch register 102 is rewritten to a random number corresponding to the operation of the start lever 41. Therefore, even if noise enters only the input terminal of the control side CPU 114 and the latched status 113 is set to "1" as a result of the noise, it is possible to reduce the possibility that the random number written to the latch register 102 as a result of the noise will be used to determine whether the winning combination is successful or not.

[0270] Furthermore, in a configuration in which a latch signal is sent when the rising edge of the detection signal SG1 input to the control IC 148 is detected, the random number used to determine whether a winning combination has been achieved varies depending on the timing of the start command setting process, even if the timing at which the player operates the start lever 41 is the same. In contrast, by configuring the control CPU 114 to output a latch signal to the CLK terminals of the latch register circuits 102a-102p when it determines that the detection signal SG1 input to the control CPU 114 rises from a low state to a high state and that the high state has continued for 12.8 μs, the random number 12.8 μs after the rising edge of the detection signal SG1 input to the control CPU 114 is always used to determine whether a winning combination has been achieved. This allows the timing at which the player operates the start lever 41 to be accurately reflected in the game results.

[0271] <Second embodiment> In this embodiment, one of the conditions in the start command setting process is that the control IC 148 determines that the latched status 113 is not set to "1," and the state of the latched status 113 is determined again in the next start command setting process. Also, if the detection signal SG1 input to the control side CPU 114 no longer rises due to a wire break or the like, the control side CPU 114 raises the latch signal in response to receiving a signal from the main side MPU 142. Note that a description of the same configuration as in the first embodiment will basically be omitted.

[0272] Fig. 24 is a block diagram for explaining the configuration of the main control board 141 in this embodiment. The control IC 148 has input terminals TA1 to TA3 (Fig. 6) and output terminal TA4 (Fig. 6), as well as an output terminal TA5 (Fig. 24). The control-side CPU 114 has input terminals TB1 and TB2 (Fig. 6) and output terminals TB3 and TB4 (Fig. 6), as well as an input terminal TB5 (Fig. 24). The output terminal TA5 of the control IC 148 and the input terminal TB5 of the control-side CPU 114 are connected by a signal line, and the signal output from the output terminal TA5 of the control IC 148 is input to the input terminal TB5 of the control-side CPU 114.

[0273] As shown in FIG. 24, the main RAM 144 also includes a start possible flag 144a, an error counter 144b, a start command flag 144c, a signal storage flag 144d, a confirmation command flag 144e, and an error state flag 144f.

[0274] Here, the confirmation command flag 144e is a flag for executing a process to determine the state of the latched status 113 again in the next start command setting process if the start command setting process (FIG. 25) is executed between the rise of the detection signal SG1 and the setting of "1" in the latched status 113. If it is determined in this process that "1" is set in the latched status 113, the control IC 148 sets "1" in the start command flag 144c, and the game starts.

[0275] In addition, the error state flag 144f is a flag that is set to "1" if the latched status 113 is not set to "1" in both the start command setting process (Figure 25) in which the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148, and the start command setting process next to the start command setting process.

[0276] Setting "1" to the error state flag 144f changes the content of the process by which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. When the error state flag 144f is set to "0", in the random number acquisition process (Fig. 28) of this embodiment, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 (Fig. 6) of the control IC 148.

[0277] Furthermore, if the error state flag 144f is set to "1," the random number acquisition process (FIG. 28) of this embodiment involves the control IC 148 transmitting a latch instruction signal to the control-side CPU 114. Here, the latch instruction signal is a signal that triggers the control-side CPU 114 to transmit a latch signal to the CLK terminal of the latch register circuits 102a to 102p. The latch instruction signal is output from the output terminal TA5 of the control IC 148 and input to the input terminal TB5 of the control-side CPU 114. After transmitting the latch instruction signal, if the latched status 113 is set to "1," the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Details of the random number acquisition process will be described later.

[0278] Next, the start command setting process in this embodiment will be described with reference to Fig. 25. The start command setting process is executed in step S206 of the timer interrupt process (Fig. 8).

[0279] First, in step S801, it is determined whether or not the game is ready to start. If the game is ready to start, the start ready flag 144a is set to "1." If the game is not ready to start (step S801: NO), the start command setting process is terminated. Therefore, even if the player operates the start lever 41 during the game, the start command flag 144c will not be set to "1" based on that operation.

[0280] If the game is ready to start (step S801: YES), then in step S802 it is determined whether the confirmation command flag 144e is set to "1." The confirmation command flag 144e is a flag that is set to "1" in step S810 if the latched status 113 is not set to "1" at the timing when the rising edge of the detection signal SG1 input to the control IC 148 is detected in a state where the game is ready to start. The confirmation command flag 144e is cleared to "0" in step S812.

[0281] The confirmation command flag 144e may be set to "1" when the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose, when noise has entered only the input terminal of the control IC 148, or when the connection between the start detection sensor 41a and the control-side CPU 114 is cut off and the detection signal SG1 input to the control-side CPU 114 no longer rises. Of these, if the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose, and it is determined in the start command setting process that the latched status 113 has not been set to "1," the latched status 113 is set to "1" within 12.8 μs of the determination.

[0282] Therefore, when the control IC 148 determines that the latched status 113 is not set to "1," it sets the confirmation command flag 144e to "1" and ends the start command setting process, and in the next start command setting process, it again determines whether or not the latched status 113 is set to "1," provided that the confirmation command flag 144e is set to "1." As a result, when the player operates the start lever 41 and the detection signal SG1 rises, the control IC 148 can obtain a random number corresponding to the current operation of the start lever 41 based on the operation of the start lever 41, regardless of the timing of the start command setting process.

[0283] By configuring the main RAM 144 to include the confirmation command flag 144e, it is possible to avoid a situation in which a game cannot be started even if the player operates the start lever 41 when the game is ready to start. It is also possible to avoid a situation in which the control IC 148 obtains an old random number that does not correspond to the current operation of the start lever 41.

[0284] If the confirmation command flag 144e is not set to "1" (step S802: NO), it is determined in steps S803 and S804 whether a rising edge of the detection signal SG1 input to the control IC 148 has been detected. Specifically, it is determined in step S803 whether the value of the signal storage flag 144d is "0." If the value of the signal storage flag 144d is "0" (step S803: YES), it is determined in step S804 whether the detection signal SG1 input to the control IC 148 is in a HI state. Then, if it is determined in step S804 that the detection signal SG1 is in a HI state (step S804: YES), the signal storage flag 144d is set to "1" in step S805.

[0285] In this way, when the signal storage flag 144d changes from "0" to "1", the control IC 148 enters a state in which it has detected the rising edge of the detection signal SG1 input to the control IC 148.

[0286] In the following step S806, it is determined whether or not "1" is set in the latched status 113 based on the signal output from the Q terminal 113a (FIG. 6) of the latched status 113 and input to the input terminal TB2 of the control IC 148. If "1" is set in the latched status 113 (step S806: YES), this means that numerical information of a random number corresponding to the current operation of the start lever 41 has already been input to the input terminal TA3 of the control IC 148. In this case, in step S807, the start command flag 144c is set to "1" so that the control IC 148 can obtain the numerical information of the random number input to the input terminal TA3 of the control IC 148 and start the game.

[0287] In the next step S808, the error counter 144b is cleared to "0." In this embodiment, the error counter 144b is a counter that is incremented by "1" when an event occurs in which the latched status 113 is not set to "1" in both the start command setting process in which the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148 and the start command setting process following the start command setting process. The error counter 144b is a counter used to determine whether the event is occurring consecutively.

[0288] Therefore, if it is confirmed that "1" is set in the latched status 113, the error counter 144b is cleared to "0" in step S808. Then, in step S809, a pulse signal is sent to the CLR terminal 113c (FIG. 6) of the latched status 113 to clear the latched status 113 to "0," and this start command setting process ends.

[0289] If it is determined in step S806 that the latched status 113 is not set to "1", then in step S810 the confirmation command flag 144e is set to "1" in order to again determine the state of the latched status 113 in the next start command setting process, and this start command setting process is terminated.

[0290] Furthermore, if it is determined in step S804 that the detection signal SG1 input to the control IC 148 is in a LOW state, this means that the rising edge of the detection signal SG1 has not been detected. In this case, since the signal storage flag 144d has already been set to "0," the latched status 113 is cleared to "0" in step S809, and the start command setting process ends.

[0291] Furthermore, if it is determined in step S803 that the signal storage flag 144d is set to "1," this means that the detection signal SG1 input to the control IC 148 was in a HI state and had already risen at the timing when the previous start command setting process was performed. In this case, in step S811, it is determined whether the detection signal SG1 input to the control IC 148 is in a LOW state. If the detection signal SG1 is in a LOW state (step S811: YES), the signal storage flag 144d is cleared to "0" in step S812.

[0292] After determining in step S811 that the detection signal SG1 input to the control IC 148 is in the HI state (step S811: NO), or after clearing the signal memory flag 144d to "0" in step S812, the latched status 113 is cleared to "0" in step S809, and this start command setting process is terminated.

[0293] Furthermore, if it is determined in step S802 that the confirmation command flag 144e is set to "1," this means that the current start command setting process is the next start command setting process following the start command setting process in which the confirmation command flag 144e was set to "1" in step S810. In this case, the confirmation command flag 144e is cleared to "0" in step S813, and it is determined in step S814 whether or not "1" is set in the latched status 113 based on the numerical information output from the Q terminal 113a of the latched status 113 and input to the input terminal TA2 of the control IC 148.

[0294] If it is determined in step S814 that the latched status 113 is set to "1," this means that the random number numerical information corresponding to the current operation of the start lever 41 has already been input to the input terminal TA3 of the control IC 148. In this case, the processes of steps S807 to S809 are executed, similarly to the case in which it is determined in step S806 that the latched status 113 is set to "1." Specifically, the start command flag 144c is set to "1" (step S807), and the error counter 144b is cleared to "0" (step S808). Then, a pulse signal is sent to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0" (step S809), and this start command setting process ends.

[0295] If it is determined in step S814 that the latched status 113 is not set to "1", an error handling process is performed in step S815, and the start command setting process is terminated. The error handling process is performed if the latched status 113 is not set to "1" within two executions of the start command setting process after the detection signal SG1 input to the control IC 148 rises.

[0296] Next, the error handling process executed in step S815 of the start command setting process (FIG. 25) will be described with reference to FIG. 26. FIG. 26 is a flowchart for explaining the error handling process executed by the control IC 148.

[0297] First, in step S901, it is determined whether the value of the error counter 144b is "0." If the value of the error counter 144b is "0" (step S901: YES), in step S902, "1" is added to the error counter 144b. If the value of the error counter 144b is not "0" (step S901: NO), this means that the error handling process has been executed twice consecutively. In this case, it is highly likely that the connection between the start detection sensor 41a and the control-side CPU 114 has been cut off. Therefore, in step S903, an abnormality signal is sent to the management computer of the amusement hall to notify the manager of the amusement hall that there is a high possibility of a disconnection.

[0298] Possible cases in which an error handling process is performed include when the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, and when noise is mixed into the control IC 148. If the value of the error counter 144b is "0," the possibility that noise has entered the control IC 148 cannot be ruled out, so only a latch instruction signal is sent without sending an abnormality signal. On the other hand, if the value of the error counter 144b is "1," there is a high possibility of a disconnection, so an abnormality signal is sent and a latch instruction signal is also sent.

[0299] When the detection signal SG1 input to the control CPU 114 does not rise even when the start lever 41 is pressed down, such as when the connection between the start detection sensor 41a and the control CPU 114 is cut off, the process of step S903 for transmitting an abnormality signal is continuously executed. The manager of the amusement hall can recognize that a disconnection has occurred by noticing that an abnormality signal is repeatedly being sent to the amusement hall's management computer.

[0300] After adding "1" to the error counter 144b in step S902, or after transmitting an abnormality signal in step S903, in step S904, a latch instruction signal is transmitted to the control-side CPU 114. When the control-side CPU 114 receives the latch instruction signal, it transmits a latch signal to the CLK terminal of the latch register circuits 102a to 102p (FIG. 6). As a result, the numerical information of the random number stored in the random number counter 105 is written to the latch register 102.

[0301] After transmitting the latch signal in step S904, the start command flag 144c is set to "1" in step S905, and the error state flag 144f is set to "1" in step S906, thereby terminating this error handling process.

[0302] When the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the control-side CPU 114 cannot grasp the timing at which the start lever 41 was operated. Therefore, even if the player operates the start lever 41, the numerical information of the random number stored in the random number counter 105 is not written to the latch register 102. In this state, if the control IC 148 obtains the numerical information of the random number input to the input terminal of the control IC 148, the winning or losing of the winning combination will be determined based on an old random number that does not correspond to the current operation of the start lever 41.

[0303] In response to this, the control IC 148 sends a latch instruction signal to the control side CPU 114, and the control side CPU 114, upon receiving the latch instruction signal, sends a latch signal to the latch register 102, so that the control IC 148 can obtain a random number corresponding to the current operation of the start lever 41. The occurrence of a disconnection is notified to the amusement hall manager, and the control IC 148 obtains a random number based on the operation of the start lever 41 until the amusement hall manager takes action, so that the amusement hall manager can perform maintenance at a timing that will not put players at an unfair disadvantage.

[0304] In this embodiment, there are two types of timing that trigger the control-side CPU 114 to send a latch signal to the CLK terminal of the latch register circuits 102a to 102p. The first timing is the timing when the detection signal SG1 input to the control-side CPU 114 rises from a LOW state to a HIGH state, and the control-side CPU 114 determines that the HIGH state of the detection signal SG1 has continued for 12.8 μs. This timing is referred to as the first timing.

[0305] The first timing is a timing that occurs a certain time (12.8 μs) after the player operates the start lever 41 and the detection signal SG1 input to the control side CPU 114 rises, and therefore is a timing that strongly reflects the timing when the player operates the start lever 41.

[0306] The second timing is the timing when the control IC 148 transmits a latch instruction signal in step S904 of the error handling process (FIG. 26) and the control-side CPU 114 receives the latch instruction signal. This timing is referred to as the second timing.

[0307] The error handling process is a process executed during the start command setting process (FIG. 25). The start command setting process is a process executed during the timer interrupt process (FIG. 8), which is executed every 1.49 ms. There is a range of approximately 1.49 ms between the time when the player operates the start lever 41 and the time when the first timer interrupt process is executed. Specifically, there is a possibility that the timer interrupt process will be executed immediately after the start lever 41 is operated, and there is also a possibility that the timer interrupt process will be executed approximately 1.49 ms after the start lever 41 is operated.

[0308] In this way, the second timing is a timing that reflects the timing when the player operates the start lever 41, but it is not a timing that reflects only the timing when the player operates the start lever 41. The second timing also reflects factors that are not dependent on the player's actions.

[0309] For this reason, in this embodiment, in a normal state where the signal line connecting the start detection sensor 41a and the control side CPU 114 is not disconnected, the numerical information of the random number stored in the random number counter 105 is written to the latch register 102 at the first timing. This makes it possible to determine whether the winning combination is successful or not using the numerical information of the random number that strongly reflects the timing of the player's operation of the start lever 41.

[0310] On the other hand, in an error state where the signal line connecting the start detection sensor 41a and the control-side CPU 114 is disconnected, the detection signal SG1 input to the control-side CPU 114 does not rise, and therefore the control-side CPU 114 cannot grasp the first timing. In this case, the control IC 148 sends a latch instruction signal to the control-side CPU 114, whereby the numerical information of the random number stored in the random number counter 105 is written to the latch register 102. As a result, even in an error state, it is possible to determine whether the winning combination is correct or not using the numerical information of the random number that reflects the timing of the player's operation of the start lever 41.

[0311] Next, the management operation executed by the control CPU 114 of this embodiment will be described with reference to Fig. 27. Fig. 27 is a flowchart showing the management operation in this embodiment.

[0312] First, in step S1001, it is determined whether or not a latch instruction signal has been received from the control IC 148. If a latch instruction signal has not been received in step S1001, it is determined in step S1002 whether or not the detection signal SG1 input to the control-side CPU 114 is in a LOW state. If the detection signal SG1 input to the control-side CPU 114 is in a HIGH state in step S1002, the process returns to step S1001.

[0313] If the detection signal SG1 input to the control-side CPU 114 is in a LOW state in step S1002, it is determined in step S1003 whether a latch instruction signal has been received. If a latch signal has not been received in step S1003, it is determined in step S1004 whether the detection signal SG1 input to the control-side CPU 114 is in a HI state. If the detection signal SG1 input to the control-side CPU 114 is in a LOW state (step S1004: NO), the process returns to step S1003.

[0314] If the detection signal SG1 input to the control-side CPU 114 is in a HI state in step S1004, this means that the detection signal SG1 has risen from a LOW state to a HI state. In this case, in step S1005, the control-side CPU 114 starts counting the time during which the detection signal SG1 input to the control-side CPU 114 remains in a HI state. This time is counted using a timer counter that counts time in 0.1 μs units.

[0315] In the next step S1006, it is determined whether or not a latch instruction signal has been received from the control IC 148. If a latch instruction signal has been received in step S1006 (step S1006: YES), a process is performed in step S1007 to invalidate the currently received latch instruction signal. Specifically, a latch signal is not sent to the latch register 102 based on the currently received latch instruction signal, and the record of the receipt of the latch instruction signal is erased so that it can be determined that a latch instruction signal has not been received until the next latch instruction signal is received.

[0316] After a negative determination is made in step S1006, or after the latch instruction signal is invalidated in step S1007, step S1008 determines whether the detection signal SG1 input to the control-side CPU 114 is in a HI state. If the detection signal SG1 is in a HI state, step S1009 determines whether 12.8 μs have elapsed since the detection of the rise of the detection signal SG1 input to the control-side CPU 114 from a LOW state to a HI state. If 12.8 μs have not elapsed since the detection of the rise, the process returns to step S1008.

[0317] If it is determined in step S1009 that 12.8 μs has elapsed since the rise of the detection signal SG1 input to the control side CPU 114 (step S1009: YES), other processing is performed in step S1010, and the process returns to step S1001. In this other processing, the processing in steps S706 to S708 in the management operation (FIG. 19) of the first embodiment is executed.

[0318] Furthermore, if the detection signal SG1 input to the control-side CPU 114 is in a LOW state in step S1008, that is, if the detection signal SG1 input to the control-side CPU 114 rises from a LOW state to a HIGH state and returns to a LOW state before 12.8 μs have elapsed since the rise, the timer counter stops counting time in step S1011, and the process returns to step S1003. In this case, the timer counter is reset.

[0319] Furthermore, if a latch instruction signal has been received in step S1001 or step S1003, a latch signal is sent to the latch register 102 in step S1012. Specifically, a pulse signal is sent to the CLK terminals of the latch register circuits 102a to 102p. This causes the numerical information of the random number stored in the random number counter 105 to be written to the latch register 102. In the following step S1013, the latched status 113 is set to "1", and the process returns to step S1001.

[0320] In this way, when a latch instruction signal is received from the control IC 148 in step S1001 or step S1003 of this management operation, a latch signal is sent to the CLK terminal of the latch register circuits 102a to 102p, and "1" is set in the latched status 113. Therefore, even if the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the control IC 148 can send a latch instruction signal to set "1" in the latched status 113 at a timing corresponding to the depression operation of the start lever 41.

[0321] Furthermore, if a negative determination is made in step S1004, the configuration is such that a determination as to whether or not a latch instruction signal has been received (step S1003) and a determination as to whether or not the detection signal SG1 input to the control side CPU 114 is in a LOW state (step S1004) are repeated. Therefore, even if a latch instruction signal is received while waiting for the detection signal SG1 to become a HI state in step S1004, it is possible to proceed to the process of raising the latch signal output to the CLK terminal of the latch register circuits 102a to 102p (step S1002) and the process of setting "1" to the latched status 113 (step S1003).

[0322] Furthermore, if a negative judgment is made in step S1009, the configuration is such that a judgment as to whether or not the detection signal SG1 is in a HI state (step S1008) and a judgment as to whether or not 12.8 μs have elapsed since the detection signal SG1 rose to a HI state (step S1009) are repeated.

[0323] As described above, if "1" is not set in the latched status 113 in both the start command setting process (FIG. 25) at the timing when the control IC 148 detects the rising edge of the detection signal SG1 input to the control IC 148 and the next start command setting process executed approximately 1.49 ms after the start command setting process, the control IC 148 is configured to transmit a latch instruction signal to the control-side CPU 114. Because the start command setting process is executed within the timer interrupt process (FIG. 8) executed at 1.49 ms intervals, the start command setting process will not be executed twice while waiting for 12.8 μs to elapse in steps S1008 and S1009.

[0324] The processing of steps S1005 to S1009 of this management operation is executed within 12.8 μs from the rise of the detection signal SG1 input to the input terminal TB1 of the control side CPU 114. Therefore, if noise is not a consideration, the latch instruction signal will not be received while waiting for 12.8 μs to pass in steps S1005 to S1009.

[0325] On the other hand, if noise is mixed into the input terminal TA1 of the control IC 148 to which the detection signal SG1 is input, there is a possibility that it will be determined that a latch instruction signal has been received in step S1006 of this management operation.

[0326] Specifically, this is the case when noise is mixed only into input terminal TA1 of control IC 148, or when noise of less than 12.8 μs is mixed into both input terminal TA1 of control IC 148 and input terminal TB1 of control side CPU 114, and the start command setting process (Figure 25) is executed in control IC 148 while the signal input to input terminal TA1 of control IC 148 is in a HI state due to the mixed noise.

[0327] In this case, the control IC 148 sets the confirmation command flag 144e to "1" in the start command setting process. If the signal input to the input terminal TB1 of the control side CPU 114 rises from a LOW state to a HIGH state at a timing after the start command setting process and before the next start command setting process, which is executed approximately 1.49 ms after the start command setting process, it may be determined that a latch instruction signal has been received from the control IC 148 in step S1006 of this management operation.

[0328] In this way, if a latch instruction signal is received in step S1006 of this management operation, the latch instruction signal has been affected by noise. For this reason, the control-side CPU 114 is configured to invalidate the latch instruction signal if it is determined in step S1006 that the signal has been received. This reduces the possibility that the control IC 148 will obtain the numerical information of the random number written to the latch register 102 due to noise and use the numerical information of the random number to determine whether the hand has been won or not.

[0329] Next, the random number acquisition process executed in step S501 of the lottery process (FIG. 11) will be described with reference to the flowchart of FIG. 28. The random number acquisition process is executed by the control IC 148.

[0330] First, in step S1101, it is determined whether the error state flag 144f is set to "1." If the error state flag 144f is not set to "1" (step S1101: NO), this means that the control-side CPU 114 has transmitted a latch signal to the CLK terminal of the latch register circuit 102a-102p at the timing when the control-side CPU 114 has determined that the detection signal SG1 input to the control-side CPU 114 has risen from a LOW state to a HIGH state and that the HIGH state of the detection signal SG1 has continued for 12.8 μs or more. Therefore, if a negative determination is made in step S1101, the control IC 148 has already confirmed that the latched status 113 has been set to "1."

[0331] On the other hand, when the error state flag 144f is set to "1" (step S1101: YES), this means that the control IC 148 has transmitted a latch instruction signal to the control-side CPU 114, and the control-side CPU 114, upon receiving the latch instruction signal, has transmitted a latch signal to the CLK terminals of the latch register circuits 102a to 102p. In this case, it is necessary to confirm that the random number information stored in the random number counter 105 has been written to the latch register 102. For this reason, in step S1102, the error state flag 144f is cleared to "0," and in step S1103, the process waits until the latched status 113 is set to "1." Then, when it is determined that the latched status 113 is set to "1" (step S1103: YES), in step S1104, a pulse signal is transmitted to the CLR terminal of the latched status 113 to clear the latched status 113 to "0."

[0332] After a negative judgment is made in step S1101, or after the latched status 113 is cleared to "0" in step S1104, in step S1105, the numerical information of the random number input to the input terminal of the control IC 148 is acquired, and this random number acquisition process is terminated.

[0333] Even when the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the control IC 148 acquires the numerical information of the random number input to the input terminal of the control IC 148, provided that the latched status 113 is set to "1." This makes it possible to avoid a situation in which the control IC 148 acquires the numerical information of the random number written in the latch register 102 before the current operation of the start lever 41.

[0334] Next, the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 will be described with reference to the time charts of FIGS.

[0335] 29, a case will be described in which the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control side CPU 114 rose. Note that, at the timings t1 to t5, the slot machine 10 is ready to start a game.

[0336] Figure 29(a) shows the state of the detection signal SG1 input to the control IC 148, Figure 29(b) shows the state of the signal memory flag 144d, Figure 29(c) shows the state of the detection signal SG1 input to the control side CPU 114, Figure 29(d) shows the timing when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Figure 29(e) shows the timing when the start command setting process is executed in the control IC 148, Figure 29(f) shows the state of the latched status 113, Figure 29(g) shows the state of the confirmation command flag 144e, and Figure 29(h) shows the timing when the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148.

[0337] When the player operates the start lever 41 at the timing t1, the detection signal SG1 input to the control IC 148 and the control side CPU 114 rises from the LOW state to the HIGH state, as shown in FIGS. 29(a) and 29(c).

[0338] The timing of t3 is the timing when 12.8 μs has elapsed from the timing of t1 when the detection signal SG1 input to the control-side CPU 114 rises. The timing of t2 is the timing after the timing of t1 and before the timing of t3. As shown in FIG. 29(e), the start command setting process is executed at the timing of t2. As shown in FIG. 29(a), the detection signal SG1 input to the control IC 148 is in a HI state at the timing of t2. Therefore, as shown in FIG. 29(b), the control IC 148 sets the signal storage flag 144d to "1" at the timing of t2. When the signal storage flag 144d changes from "0" to "1," the control IC 148 detects the rising edge of the detection signal SG1.

[0339] 29(f), at the timing t2 when the control IC 148 detects the rising edge of the detection signal SG1, the value of the latched status 113 is "0." Therefore, as shown in FIG. 29(g), the control IC 148 sets "1" to the confirmation command flag 144e in the start command setting process executed at the timing t2.

[0340] As shown in Figure 29(c), the detection signal SG1 input to the control-side CPU 114 rises at timing t1 and remains HI until timing t3, 12.8 μs after the rise. Therefore, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a to 102p at timing t3. As a result, as shown in Figure 29(d), the numerical information of the random number stored in the random number counter 105 is written to the latch register 102 at timing t3. Furthermore, as shown in Figure 29(f), the control-side CPU 114 sets "1" to the latched status 113 at timing t3.

[0341] Thereafter, as shown in Fig. 29(e), the start command setting process is executed at timing t4, which is after timing t3. As shown in Fig. 29(g), the confirmation command flag 144e is set to "1" at timing t4, and as shown in Fig. 29(f), the latched status 113 is also set to "1." Therefore, as shown in Fig. 29(f), at timing t4, the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0," and also clears the confirmation command flag 144e to "0," as shown in Fig. 29(g).

[0342] Also, at the same timing of t4, the control IC 148 sets the start command flag 144c to "1." Therefore, in the lottery process (FIG. 11) that is executed at timing t5 after timing t4, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148, as shown in FIG. 29(h).

[0343] In this way, if the latched status 113 is not set to "1" at the timing when the control IC 148 detects the rising edge of the detection signal SG1, the control IC 148 sets the confirmation command flag 144e to "1." If the confirmation command flag 144e is set to "1" and the latched status 113 is set to "1" in the start command setting process, the control IC 148 sets the start command flag 144c to "1" and acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Therefore, even if the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose, the control IC 148 can acquire the numerical information of the random number corresponding to the current operation of the start lever 41.

[0344] Next, the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 when the connection between the start detection sensor 41a and the control-side CPU 114 is cut off will be described with reference to the time chart of Fig. 30. Note that at the timings t1 to t5 and t8 to t12, the slot machine 10 is ready to start a game.

[0345] Figure 30(a) shows the state of the detection signal SG1 input to the control IC 148, Figure 30(b) shows the state of the signal memory flag 144d, Figure 30(c) shows the state of the detection signal SG1 input to the control side CPU 114, Figure 30(d) shows the timing when the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Figure 30(e) shows the timing when the start command setting process is executed by the control IC 148, Figure 30(f) shows the state of the latched status 113, Figure 30(g) shows the timing when the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148, Figure 30(h) shows the state of the confirmation command flag 144e, Figure 30(i) shows the state of the error counter 144b, and Figure 30(j) shows the timing when the control IC 148 sends an abnormality signal to the amusement hall's management computer.

[0346] As shown in Figure 30(a), when the player operates the start lever 41 at timing t1, the detection signal SG1 input to the control IC 148 rises from a LOW state to a HIGH state. As shown in Figure 30(c), since the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the detection signal SG1 input to the control-side CPU 114 remains in a LOW state.

[0347] As shown in Fig. 30(e), when the start command setting process is executed at timing t2, which is later than timing t1 when the detection signal SG1 rises, the detection signal SG1 input to the control IC 148 is in the HI state at timing t2, as shown in Fig. 30(a), so the control IC 148 sets the signal storage flag 144d to "1", as shown in Fig. 30(b). This brings about a state in which the control IC 148 has detected the rise of the detection signal SG1.

[0348] At time t2, a period during which the game can be started is detected, and the rising edge of the detection signal SG1 is detected. However, as shown in FIG. 30(f), the latched status 113 is not set to "1." Therefore, as shown in FIG. 30(g), the control IC 148 does not acquire a random number at time t2. As shown in FIG. 30(h), the control IC 148 sets the confirmation command flag 144e to "1" in the start command setting process performed at time t2, and ends this start command setting process.

[0349] As shown in FIG. 30(e), the next start command setting process following the start command setting process executed at time t2 is executed at time t3, approximately 1.49 ms after time t2. Because the player's operation of the start lever 41 is a human action, it is longer than the interval at which the start command setting process is executed. Therefore, as shown in FIG. 30(a), the detection signal SG1 is in the HI state even at time t3. Also, as shown in FIG. 30(h), the confirmation command flag 144e is set to "1" at time t3. However, because the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, the latched status 113 is not set to "1" even at time t3, as shown in FIG. 30(f). Also, as shown in FIG. 30(i), the value of the error counter 144b is "0" at time t3. Therefore, as shown in Fig. 30(h), the control IC 148 clears the confirmation command flag 144e to "0" in the start command setting process executed at timing t3, and performs the error handling process (Fig. 26). Then, as shown in Fig. 30(i), the control IC 148 increments the error counter 144b by "1" in the error handling process executed at timing t3.

[0350] Furthermore, the control IC 148 transmits a latch instruction signal in the error handling process executed at timing t3. The control-side CPU 114, which receives the latch instruction signal, transmits the latch instruction signal to the CLK terminals of the latch register circuits 102a to 102p. As a result, as shown in Fig. 30(d), at timing t4 after timing t3, the control-side CPU 114 transmits a latch signal to update the numerical information of the random number stored in the latch register 102, and sets "1" to the latched status 113 as shown in Fig. 30(f).

[0351] As shown in Figure 30(g), in the random number acquisition process (Figure 29) executed at timing t5 after timing t4, the control IC 148 starts the game by acquiring the numerical information of the random number input to the input terminal TA3 of the control IC 148. Also, as shown in Figure 30(f), at the same timing t5, the control IC 148 transmits a pulse signal to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0."

[0352] Thereafter, as shown in Fig. 30(a), the detection signal SG1 input to the control IC 148 falls at timing t6. Then, as shown in Fig. 30(e), the start command setting process is executed at timing t7, which is after timing t6. As shown in Fig. 30(a), the detection signal SG1 input to the control IC 148 is in a LOW state at timing t7, so as shown in Fig. 30(b), the control IC 148 clears the signal storage flag 144d to "0."

[0353] Thereafter, the game that started at time t5 ends, and when the player operates the start lever 41 at time t8 as shown in FIG. 30(a), the detection signal SG1 input to the control IC 148 rises. Then, at time t9 after time t8, the start command setting process is executed as shown in FIG. 30(e). As shown in FIG. 30(a), the detection signal SG1 input to the control IC 148 is in the HI state at time t9, so the control IC 148 sets the signal storage flag 144d to "1" at time t9 as shown in FIG. 30(b). When the signal storage flag 144d changes from "0" to "1," the control IC 148 enters a state in which it has detected the rising edge of the detection signal SG1.

[0354] As shown in Figure 30(f), at timing t9, the value of the latched status 113 is "0", so as shown in Figure 30(h), the control IC 148 sets the confirmation command flag 144e to "1" and terminates this start command setting process.

[0355] As shown in FIG. 30(e), at time t10, which is after time t9, the next start command setting process is performed after the start command setting process performed at time t9. As shown in FIG. 30(h), the confirmation command flag 144e is set to "1" at time t10. As shown in FIG. 30(f), the value of the latched status 113 is "0" at time t10. As shown in FIG. 30(i), the value of the error counter 144b is "1" at time t10. This situation indicates that, despite the control IC 148 detecting a rising edge of the detection signal SG1, an event has occurred twice in succession in which the latched status 113 is not set to "1" in response to the rising edge of the detection signal SG1. If this event occurs twice in succession, it is highly likely that the connection between the start detection sensor 41a and the control-side CPU 114 has been disconnected.

[0356] Therefore, as shown in Figure 30(h), the control IC 148 clears the confirmation command flag 144e to "0" at timing t10 ​​and performs error handling processing. As shown in Figure 30(j), the control IC 148 sends an abnormality signal to the gaming hall's management computer in the error handling processing performed at timing t10 ​​to notify the gaming hall manager that an abnormality has occurred in the behavior of the detection signal SG1 input to the control side CPU 114.

[0357] Furthermore, the control IC 148 transmits a latch instruction signal in the error handling process executed at timing t10. Upon receiving the latch instruction signal from the control IC 148, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a to 102p. As a result, as shown in FIG. 30(d), the numerical information of the random number stored in the random number counter 105 is written to the latch register 102 at timing t11. Furthermore, as shown in FIG. 30(f), the control-side CPU 114 sets "1" to the latched status 113 at the same timing t11.

[0358] Thereafter, in the lottery process (FIG. 11) executed at timing t12, as shown in FIG. 30(g), the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Also, as shown in FIG. 30(f), at the same timing t12, the control IC 148 clears the latched status 113 to "0."

[0359] In this way, when only the detection signal SG1 input to the control IC 148 rises and the detection signal SG1 input to the control-side CPU 114 does not rise, the control IC 148 transmits a latch instruction signal in response to the timing at which the control IC 148 detects the rise of the detection signal SG1. Then, upon receiving the latch instruction signal, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a to 102p. As a result, even when the connection between the start detection sensor 41a and the control-side CPU 114 is cut off, it is possible to determine whether the winning combination has been achieved using numerical information on the random number corresponding to the timing at which the player operated the start lever 41.

[0360] Furthermore, if an event occurs two or more times in succession where the latched status 113 is not set to "1" in response to the rising edge of the detection signal SG1 despite the control IC 148 detecting the rising edge of the detection signal SG1, the control IC 148 sends an abnormality signal to the gaming hall's management computer in the error handling process from the second time onwards. This makes it possible to notify the gaming hall manager that a game is continuing despite an abnormality in the behavior of the detection signal SG1 input to the input terminal TA3 of the control side CPU 114.

[0361] As described above, when the start command setting process is executed in a state where the game can be started, the rising edge of the detection signal SG1 input to the control IC 148 is detected, and it is determined that the latched status 113 is not set to "1," the confirmation command flag 144e is set to "1," and the state of the latched status 113 is determined again in the next start command setting process. If the latched status 113 is set to "1" in the next start command setting process after the start command setting process that ended with the confirmation command flag 144e set to "1," the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148. Therefore, even if the start command setting process is executed before 12.8 μs has elapsed since the detection signal SG1 input to the control-side CPU 114 rose, the win / loss determination can be performed using the numerical information of the random number corresponding to the current operation of the start lever 41.

[0362] Furthermore, if the latched status 113 is not set to "1" despite the detection of a rising edge of the detection signal SG1 input to the control IC 148, the control IC 148 transmits a latch instruction signal. The control-side CPU 114 then transmits a latch signal to the CLK terminals of the latch register circuits 102a-102p upon receiving the latch instruction signal. If the latched status 113 is not set to "1" despite the detection of a rising edge of the detection signal SG1 input to the control IC 148 two or more consecutive times, the control IC 148 transmits an abnormality signal to the gaming hall's management computer in the error handling process for the second or subsequent occurrences. This allows the control IC 148 to continue acquiring the random number information written to the latch register 102 upon depression of the start lever 41, even if the connection between the start detection sensor 41a and the control-side CPU 114 is disconnected. Furthermore, the gaming hall manager can perform maintenance on the slot machine 10 at a time that does not disadvantage players.

[0363] Furthermore, in the start command setting process executed when a game is ready to start, if a rising edge of the detection signal SG1 input to the control IC 148 is not detected, the control IC 148 sends a pulse signal to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0." Therefore, even if noise enters only the control CPU 114 before the player operates the start lever 41 and the noise causes the latched status 113 to be set to "1," if the start command setting process is executed between the time the noise enters and the time the player operates the start lever 41, the latched status 113 is cleared to "0" in the start command setting process. This reduces the possibility that the start lever 41 is operated with the latched status 113 set to "1," causing the control IC 148 to obtain numerical information on an old random number that does not correspond to the current operation of the start lever 41.

[0364] <Another embodiment of the second embodiment> In the error handling process of the second embodiment described above (FIG. 26), if the value of the error counter 144b is "1" (step S901: NO), the control IC 148 may be configured to directly acquire numerical information of the random number from the random number counter 105. Here, directly acquiring the random number by the control IC 148 means that the control IC 148 acquires numerical information of the random number output from the Q terminal of the random number counter circuit 105a to 105p without going through the latch register 102.

[0365] FIG. 31(a) is a block diagram illustrating the connection between the control IC 148 and the random number counter 105 provided on the main control board 141. The configuration of the main control board 141 in this configuration will be described using this block diagram. Note that components that are the same as those of the main control board 141 in the second embodiment are omitted. As shown in FIG. 31(a), in the main control board 141 of this configuration, signal lines extending from the Q terminals of the random number counter circuits 105a to 105p branch off and are connected to the D terminals of the latch register circuits 102a to 102p and the input terminal TA6 of the control IC 148. Therefore, the numerical information of the random number stored in the random number counter 105 is output to each of the latch register 102 and the input terminal TA6 of the control IC 148. The numerical information of the random number output to the latch register 102 is written to the latch register 102 at the timing when a pulse signal is sent to the CLK terminals of the latch register circuits 102a to 102p. In addition, the numerical information of the random number output to input terminal TA3 of control IC 148 is acquired by control IC 148 when the detection signal SG1 input to control IC 148 rises and latched status 113 is not set to "1".

[0366] Here, the input terminal TA3 (Fig. 6) of the control IC 148, to which the numerical information of the random numbers output from the Q terminals of the latch register circuits 102a to 102p is input, is a different input terminal from the input terminal TA6 (Fig. 31(a)) of the control IC 148, to which the numerical information of the random numbers output from the Q terminals of the random number counter circuits 105a to 105p is input. Therefore, the control IC 148 can distinguish between the numerical information of the random numbers output from the latch register 102 and the numerical information of the random numbers output from the random number counter 105 and selectively acquire the one.

[0367] When the control IC 148 directly acquires the numerical information of the random numbers output from the Q terminals of the random number counter circuits 105a to 105p and input to the input terminal TA6 of the control IC 148, the processing of step S904 is omitted in the error handling processing (FIG. 26) in the second embodiment. The error handling processing in this configuration will be specifically described below.

[0368] If the value of the error counter 144b is "0" (step S901: YES), the control IC 148 adds "1" to the error counter 144b (step S902) and then sets the start command flag 144c to "1" (step S905). Then, the control IC 148 sets the error state flag 144f to "1" (step S906) and ends this error handling process. On the other hand, if the value of the error counter 144b is "1" (step S901: NO), the control IC 148 sends an abnormality signal to the gaming hall's management computer (step S903) and then sets the start command flag 144c to "1" (step S905). Then, the control IC 148 sets the error state flag 144f to "1" (step S906) and ends this error handling process.

[0369] As described above, the control IC 148 in this configuration does not transmit a latch instruction signal to the control-side CPU 114. The management operation executed by the control-side CPU 114 in this configuration has the same processing configuration as the management operation executed by the control-side CPU 114 in the first embodiment (FIG. 19).

[0370] Specifically, the control CPU 114 first waits until the detection signal SG1 input to it goes low (step S701), and if it goes low (step S701: YES), it waits until the detection signal SG1 goes high (step S702). If the detection signal SG1 goes high (step S702: YES), it starts counting the time the high state continues using a timer counter (step S703).

[0371] If 12.8 μs has elapsed while the detection signal SG1 remains in the HI state (step S704: YES, step S705: YES), the timer counter stops counting the time (step S706). Then, a latch signal is sent to the CLK terminals of the latch register circuits 102a to 102p (step S707), and the latched status 113 is set to “1”, and the process returns to the initial process (step S701) of waiting until the detection signal SG1 becomes LOW again.

[0372] If the HIGH state of the detection signal SG1 returns to the LOW state in less than 12.8 μs (step S704: NO), the timer counter stops counting (step S709) and resets the timer counter, and the process returns to the second process (step S702) of waiting until the detection signal SG1 becomes HIGH again.

[0373] Next, a random number acquisition process in this configuration in which the control IC 148 directly acquires the numerical information of the random number stored in the random number counter 105 will be described with reference to the flowchart in FIG.

[0374] First, in step S1201, it is determined whether or not the error state flag 144f is set to "1." If the error state flag 144f is set to "1" in step S1201, this means that the numerical information of the random number corresponding to the current operation of the start lever 41 is not written to the latch register 102. In this case, the error state flag 144f is cleared to "0" in step S1202, and the numerical information of the random number output from the Q terminal of the random number counter circuit 105a to 105p and input to the input terminal TA3 (FIG. 6) of the control IC 148 is acquired in step S1203, and this random number acquisition process is terminated.

[0375] Furthermore, in step S1201, if the error state flag 144f is not set to "1", this means that the numerical information of the random number corresponding to this operation of the start lever 41 has already been written to the latch register 102. In this case, in step S1204, the numerical information of the random number output from the latch register 102 and input to the input terminal TA6 (Figure 31(a)) of the control IC 148 is acquired, and this random number acquisition process is terminated.

[0376] As described above, the control IC 148 of this configuration can acquire random numbers in two ways. Of these, the random numbers acquired by the control IC 148 using the method in which the control IC 148 acquires random numbers output from the Q terminals of the latch register circuits 102a to 102p and input to the input terminal TA3 of the control IC 148 are referred to as indirectly acquired random numbers. The indirectly acquired random numbers are random numbers stored in the random number counter 105 12.8 μs after the rising edge of the detection signal SG1 input to the control side CPU 114 is detected. The timing at which the indirectly acquired random numbers are acquired is the random numbers stored in the random number counter 105 a fixed time after the rising edge of the detection signal SG1, and this fixed time is a relatively short period of 12.8 μs.

[0377] On the other hand, the random numbers output from the Q terminals of the random number counter circuits 105a to 105p and input to the input terminal TA6 of the control IC 148 are referred to as directly acquired random numbers. These directly acquired random numbers are random numbers acquired during the timer processing (Figure 8) executed by the control IC 148. The directly acquired random numbers are random numbers stored in the random number counter 105 after an indefinite time from the rising edge of the detection signal SG1, and this indefinite time is within a time range of 1.49 ms. 1.49 ms is a long time compared to 12.8 μs.

[0378] For this reason, the indirectly obtained random numbers are random numbers that more closely reflect the timing of the player's operation of the start lever 41 than the directly obtained random numbers. This configuration is configured to use the indirectly obtained random numbers to determine whether the winning combination is successful or not when the connection between the start detection sensor 41a and the control side CPU 114 is not cut off, and is configured to switch the random numbers used to determine whether the winning combination is successful or not to the directly obtained random numbers when the connection between the start detection sensor 41a and the control side CPU 114 is cut off.

[0379] This configuration allows the timing of the player's operation of the start lever 41 to be accurately reflected in the game results, and even if the connection between the start detection sensor 41a and the control side CPU 114 is disconnected, the random number used to determine the success or failure of the winning combination can be updated according to the timing of the operation of the start lever 41.

[0380] <Third embodiment> In this embodiment, the timing at which the control side CPU 114 sets the latched status 113 to "1" is limited to a period during which the game can be started. Also, the control IC 148 starts the game when the detection signal SG1 input to the control IC 148 is in a HI state and the latched status 113 is set to "1". Note that a description of the same configuration as in the first embodiment will basically be omitted.

[0381] Fig. 32 is a block diagram for explaining the configuration of the main control board 141 in this embodiment. As shown in Fig. 32, the main MPU 142 in this embodiment includes a control IC 148 and a hardware random number circuit 146. The hardware random number circuit 146 includes a control circuit 103, an update circuit 101, and a latch register 102.

[0382] The update circuit 101 of this embodiment has the same configuration as the update circuit 101 of the first embodiment described above (FIG. 6). Therefore, the update circuit 101 includes a clock circuit 104 and a random number counter 105. The random number counter 105 of this embodiment has the same configuration as the random number counter 105 of the first embodiment described above. Specifically, the random number counter 105 is made up of 16 random number counter circuits 105a to 105p (FIG. 6).

[0383] Furthermore, the latch register 102 of this embodiment has the same configuration as the latch register 102 of the first embodiment described above. Specifically, the latch register 102 is made up of 16 latch register circuits 102a to 102p (FIG. 6).

[0384] The control circuit 103 of this embodiment has the same configuration as the control circuit 103 of the first embodiment described above (FIG. 6). More specifically, the control circuit 103 includes a control-side CPU 114 and a latched status 113. The control-side CPU 114 is a CPU that executes processing using a program. A program for executing management operations (FIG. 35) is stored in the ROM 115 of the control-side CPU 114, and a storage area for temporarily storing information is set in the RAM 116 of the control-side CPU 114.

[0385] 32, the main RAM 144 in this embodiment includes an error counter 144b and a start command flag 144c. The control IC 148 includes an output terminal TA7, and the control CPU 114 includes an input terminal TB7. The output terminal TA7 of the control IC 148 and the input terminal TB7 of the control CPU 114 are connected by a signal line, and the start enable signal output from the output terminal TA7 of the control IC 148 is input to the input terminal TB7 of the control CPU 114.

[0386] In normal processing (FIG. 34), the control IC 148 raises the start enable signal when the start timing of the period when the game can be started arrives, and lowers the start enable signal when the end timing of the period when the game can be started arrives. Therefore, the control side CPU 114 can determine whether or not it is a period when the game can be started by grasping the state of the start enable signal input to the input terminal TB7. In this embodiment, the control side CPU 114 sets the latched status 113 to "1" based on the fact that it is a period when the game can be started as one condition. Details of the normal processing (FIG. 34) in this embodiment will be described later.

[0387] 32, the control-side CPU 114 has an output terminal TB6 connected to the CLR terminal 113c of the latched status 113. Here, the control IC 148 in this embodiment does not have an output terminal connected to the CLR terminal 113c of the latched status 113. In this embodiment, the control-side CPU 114 clears the latched status 113 to "0."

[0388] Specifically, if the start enable signal falls to a LOW state before a certain time has elapsed after the control side CPU 114 sets the latched status 113 to "1," this means that it is time to start the game in the normal processing (FIG. 34) that was executed after the control IC 148 set the latched status 113 to "1." In this case, at the timing of the falling edge, a pulse signal is sent from the output terminal TB6 to the CLR terminal 113c of the latched status 113, thereby clearing the latched status 113 to "0."

[0389] Furthermore, if the start-ready signal does not fall to a LOW state even after a certain period of time has elapsed after the control side CPU 114 has set the latched status 113 to "1", this means that noise has entered only the input terminal TB1 of the control side CPU 114, and that this noise has triggered the control side CPU 114 to set the latched status 113 to "1".

[0390] In detail, when noise enters only the input terminal TB1 of the control side CPU 114, the signal input to said input terminal TB1 rises from a LOW state to a HI state, and said HI state is maintained for 12.8 μs, the control side CPU 114 sends a latch signal to the latch register 102 and also sends a pulse signal to the T terminal 113b of the latched status 113 to set "1" to the latched status 113.

[0391] In this case, the detection signal SG1 input to the input terminal TA1 of the control IC 148 does not rise, and therefore the start enable signal does not fall. The control-side CPU 114 is configured to determine whether or not a game is in progress based on the signal output from the output terminal TA7 of the control IC 148 and input to the input terminal TB7 of the control-side CPU 114. If the control-side CPU 114 sets the latched status 113 to "1" in response to noise, and the state in which the latched status 113 is set to "1" is maintained for a long time, the player will operate the start lever 41 while the latched status 113 is set to "1."

[0392] When the start lever 41 is operated while the latched status 113 is set to "1," the detection signal SG1 input to the input terminal TA1 of the control IC 148 and the input terminal TB1 of the control-side CPU 114 rises from a LOW state to a HI state. If the detection signal SG1 input to the input terminal TB1 of the control-side CPU 114 rises to a HI state and this HI state is maintained for 12.8 μs or more, then, 12.8 μs after the rise of the detection signal SG1, the control-side CPU 114 outputs a latch signal to the latch register 102 and sends a pulse signal to the T terminal 113b of the latched status 113 to set the latched status 113 to "1."

[0393] In this case, when the detection signal SG1 input to the input terminal TA1 of the control IC 148 rises and the start command setting process is executed before 12.8 μs has elapsed since the rise of the detection signal SG1, the detection signal SG1 input to the input terminal TA1 of the control IC 148 is in a HI state at the time the start command setting process is executed and the latched status 113 is set to "1", so the control IC 148 sets the start command flag 144c to "1" at that time. Therefore, in the normal process that is performed thereafter, the control IC 148 may execute a lottery for a winning combination using the numerical information of the random number written to the latch register 102 in response to the inclusion of noise.

[0394] On the other hand, if the start enable signal input to the input terminal TB7 of the control side CPU 114 does not fall from HI to LOW within a certain period of time from the time when the control side CPU 114 sets the latched status 113 to "1", the control side CPU 114 is configured to clear the latched status 113 to "0", thereby reducing the possibility that the control IC 148 will perform a lottery to determine whether the winning role will be selected using the numerical information of the random number written to the latch register 102 due to the inclusion of noise.

[0395] Here, the above-mentioned certain time is a time longer than the maximum time from when the detection signal SG1 rises until when the start enable signal falls in the slot machine 10, and is set to 5 ms in this embodiment. Note that in the slot machine 10, the maximum time from when the detection signal SG1 rises until when the start enable signal falls is experimentally determined at the design stage.

[0396] Next, the start command setting process executed in step S206 of the timer interrupt process (FIG. 8) will be described with reference to Fig. 33. Fig. 33 is a flowchart showing the start command setting process executed in the control IC 148.

[0397] First, in step S1301, it is determined whether or not it is a period during which the game can be started. If it is not a period during which the game can be started (step S1301: NO), the start command setting process is terminated. If it is determined that it is a period during which the game can be started (step S1301: YES), the process proceeds to step S1302.

[0398] In step S1302, it is determined whether the detection signal SG1 input to the control IC 148 is in a HI state, and if the detection signal SG1 is in a LOW state (step S1302: NO), the start command setting process is terminated. If the detection signal SG1 is in a HI state (step S1302: YES), it is determined in step S1303 whether the latched status 113 is set to "1." If the latched status 113 is set to "1" (step S1303: YES), this means that the conditions for starting the game have been met. Therefore, in step S1304, the start command flag 144c is set to "1," the error counter 144b is cleared to "0," and the start command setting process is terminated.

[0399] In this embodiment, the condition for starting the game is that the latched status 113 is set to "1" under the condition that the detection signal SG1 input to the control IC 148 is in a HI state.

[0400] Furthermore, if "1" is not set in the latched status 113 in step S1303, steps S1306 to S1309 are the same as steps S308 to S312 in the start command setting process (FIG. 9) of the first embodiment.

[0401] Specifically, after adding "1" to the error counter 144b (step S1306), if the error counter 144b becomes "3" (step S1307: YES), the error counter 144b is cleared to "0" (step S1308) and an abnormality notification process is executed (step S1309). On the other hand, if the error counter 144b after adding "1" is "2" or less (step S1307: NO), the start command setting process is terminated.

[0402] In this way, the control IC 148 is configured to start a game on the conditions that the detection signal SG1 input to the control IC 148 is in a HI state and that the latched status 113 is set to "1." Therefore, when the start command setting process is executed 12.8 μs after the detection signal SG1 output from the start detection sensor 41 a rises to a HI state and before the numerical information of the random number stored in the latch register 102 is updated, the processing load for the control IC 148 to determine the timing to start a game can be reduced compared to a configuration in which a flag is set to check the state of the latched status 113 again in the next start command setting process.

[0403] Next, the normal processing executed in the control IC 148 will be described with reference to Fig. 34. First, in step S1401, the same processing as step S401 in the normal processing (Fig. 10) of the first embodiment is executed. Specifically, an interrupt permission processing is executed to permit the next timer interrupt processing (Fig. 8).

[0404] In the next step S1402, the same process as step S402 in the normal process (FIG. 10) of the first embodiment is executed. Specifically, a start waiting process is executed. Here, when a medal return process is executed in the start waiting process of this embodiment, the control IC 148 clears the start command flag 144c to "0" and lowers the start possible signal at the start timing of the medal return process.

[0405] By clearing the start command flag 144c to "0" at the start timing of the medal return process, it is possible to avoid a situation in which the game starts before the start lever 41 is operated when the number of medals bet reaches the specified number again. Also, by turning off the start enable signal, it is possible to avoid a situation in which the control side CPU 114 sets "1" to the latched status 113 after the medals are returned.

[0406] In the next step S1403, the same process as step S403 in the normal process (FIG. 10) of the first embodiment is executed. Specifically, if the number of bets has not reached the specified number (step S1403: NO), the process returns to step S1402, and if the number of bets has reached the specified number (step S1403: YES), the process proceeds to step S1404.

[0407] In step S1404, it is determined whether the start possible signal output from output terminal TA7 (FIG. 32) of control IC 148 is in a HI state. If the start possible signal is in a LOW state (step S1404: NO), this means that it is time to start the period in which the game can be started, so in step S1405 the start possible signal is raised to a HI state. This allows the control side CPU 114, which has received the start possible signal, to know the start time of the period in which the game can be started.

[0408] Furthermore, if the start enable signal is in a HI state in step S1404, this means that the period in which the game can be started has already begun. After a negative determination is made in step S1404 or after the start enable signal is set to a HI state in step S1405, it is determined in step S1406 whether or not the start command flag 144c is set to "1," and if the start command flag 144c is not set to "1" (step S1406: NO), the process returns to step S1402.

[0409] Furthermore, if the start command flag 144c is set to "1" in step S1406 (step S1406: YES), this means that the random number information corresponding to the current operation of the start lever 41 has already been input to the input terminal TA3 of the control IC 148. In this case, the start command flag 144c is cleared to "0" in step S1407, and the start possible signal is turned off in step S1408. This allows the control CPU 114, which is receiving the start possible signal, to know that the timing has come to the end of the period in which the game can be started.

[0410] In the following step S1409, other processing is performed, and the process returns to step S1401. In the other processing, the same processing as that in steps S410 to S416 in the normal processing (FIG. 10) of the first embodiment is performed.

[0411] Next, the management operation executed by the control-side CPU 114 will be described with reference to the flowchart of Fig. 35. First, in step S1501, it is determined whether or not it is a period during which a game can be started. Specifically, if the start enable signal output from output terminal TA7 to the control IC 148 and input to input terminal TB7 of the control-side CPU 114 is in a LOW state, it is determined that it is outside the period during which a game can be started, and the control waits until the start enable signal rises to a HI state. On the other hand, if the start enable signal is in a HI state, it is determined that it is a period during which a game can be started, and the process proceeds to step S1502.

[0412] In steps S1502 to S1510, the same processing as steps S701 to S708 of the management operation (FIG. 19) in the first embodiment is executed. Specifically, the control CPU 114 waits until the detection signal SG1 input to the control CPU 114 goes low (step S1502). If the detection signal SG1 input to the control CPU 114 goes low (step S1502: YES), the control CPU 114 waits until the detection signal SG1 goes high (step S1503).

[0413] If the detection signal SG1 input to the control-side CPU 114 becomes HIGH (step S1503: YES), a timer counter is used to start counting the time the detection signal SG1 maintains the HIGH state (step S1504). In this embodiment, this count is referred to as the first count. After the first count is started, it is determined whether the HIGH state of the detection signal SG1 input to the control-side CPU 114 is maintained for 12.8 μs or more (steps S1505 and S1506). If the HIGH state of the detection signal SG1 continues for less than 12.8 μs (step S1505: NO), the first count is stopped and the timer counter is reset (step S1507), and the process returns to step S1503.

[0414] If it is determined that the detection signal SG1 has maintained the HI state for 12.8 μs or more (step S1505: YES, step S1506: YES), the first count is stopped and the timer counter is reset (step S1508).Then, a latch signal is sent to the CLK terminals of the latch register circuits 102a to 102p (step S1509), and the latched status 113 is set to “1” (step S1510).

[0415] After setting latched status 113 to "1" in step S1510, in step S1511, a timer counter is used to start counting the time that latched status 113 remains set to "1." This count is called the second count. In the following step S1512, it is determined whether the start enable signal is in a LOW state, and if the start enable signal is in a HI state (step S1512: NO), it is determined in step S1513 whether 5 ms have elapsed since latched status 113 was set to "1," and if 5 ms have not elapsed, the process returns to step S1512.

[0416] If the start enable signal is in a LOW state in step S1512, this means that the period during which the game can be started has ended, so the second count is stopped and the timer counter is reset in step S1514. Then, in step S1515, a pulse signal is sent to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0", and the process returns to step S1501.

[0417] Furthermore, if the determination in step S1513 is affirmative, this means that the start command flag 144c was not set to "1" in the start command setting process executed by the control IC 148 during the period from when "1" was set to the latched status 113 until 5 ms had elapsed since the latched status 113 was set to "1." This state occurs when noise is mixed into the input terminal TB1 of the control-side CPU 114, and the mixing of this noise triggers the setting of "1" to the latched status 113.

[0418] In this case, in step S1516, the second count is stopped and the timer counter is reset, and in step S1517, a pulse signal is sent to the CLR terminal 113c of the latched status 113 to clear the latched status 113 to "0", and the process returns to step S1502.

[0419] In this way, the control side CPU 114 determines whether or not it is a period in which the game can be started, and if it is a period in which the game can be started, sets "1" to the latched status 113. This reduces the processing load on the control IC 148 for executing the start command setting process.

[0420] Furthermore, detecting a rising edge of the detection signal SG1 input to the control-side CPU 114, where the detection signal SG1 changes from a LOW state to a HIGH state, is one of the conditions for setting "1" to the latched status 113. Therefore, when the start lever 41 is pressed down and the pressing operation continues for a long period of time, the process of setting "1" to the latched status 113 is performed only once in accordance with the start timing of the pressing operation. The process of setting "1" to the latched status 113 in response to the continuation of the pressing operation is not performed repeatedly.

[0421] Furthermore, being in a period in which a game can be started is one of the conditions for setting "1" to the latched status 113. Therefore, even if the start lever 41 is pressed outside of the period in which a game can be started, the pressing operation will not trigger the setting of "1" to the latched status 113.

[0422] Here, the process of lowering the start enable signal to a LOW state is the process of step S1408 of the normal process (FIG. 34) performed by the control IC 148. The process of step S1408 is performed on the condition that the start command flag 144c is set to "1." The process of setting the start command flag 144c to "1" (the process of step S1304 in the start command setting process (FIG. 33)) is performed on the condition that the latched status 113 is set to "1."

[0423] For this reason, after it is determined in step S1501 of this management operation that the start enable signal is in a HI state, the start enable signal does not fall to a LOW state until "1" is set to the latched status 113 in step S1510. For example, the start enable signal does not fall to a LOW state while waiting for the detection signal SG1 to go to a LOW state in step S1502, while waiting for the detection signal SG1 to go to a HI state in step S1503, and while waiting until it is determined in steps S1505 and S1506 that the HI state of the detection signal SG1 has continued for 12.8 μs or more.

[0424] Furthermore, the latched status 113 is set to "1" when the game is ready to start and when the detection signal SG1 input to the control CPU 114 rises from a LOW state to a HIGH state, among other conditions. Therefore, if the start lever 41 is pressed during a game and the game is ready to start while the pressing operation is continued, the latched status 113 will not be set to "1" as a result of the pressing operation. In this slot machine 10, a game is started when the start lever 41 is operated in a state where the game is ready to start, as one condition.

[0425] Next, the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 will be described with reference to the time chart of Fig. 36. Fig. 36(a) shows the state of the detection signal SG1 input to the control IC 148, Fig. 36(b) shows the state of the detection signal SG1 input to the control side CPU 114, Fig. 36(c) shows the timing at which the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, Fig. 36(d) shows the state of the latched status 113, Fig. 36(e) shows the timing at which the start command setting process is executed in the control IC 148, Fig. 36(f) shows the timing at which the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148, Fig. 36(g) shows the state of the start command flag 144c, Fig. 36(h) shows the period during which the game can be started, and Fig. 36(i) shows the state of the error counter 144b.

[0426] When noise is introduced only into the input terminal TB1 of the control-side CPU 114 at time t1, the detection signal SG1 input to the control-side CPU 114 rises from a LOW state to a HIGH state, as shown in FIG. 36(a). The HIGH state of the detection signal SG1 continues until time t3. At time t2, which is 12.8 μs after time t1 and before time t3, the control-side CPU 114 transmits a latch signal to the CLK terminals of the latch register circuits 102a-102p and transmits a pulse signal to the T terminal 113b of the latched status 113. As a result, the random number stored in the random number counter 105 at time t2 is written to the latch register 102, as shown in FIG. 36(c), and the latched status 113 is set to "1," as shown in FIG. 36(d).

[0427] As shown in Fig. 36(e), at time t4, which is after time t3, the control IC 148 executes the start command setting process. As shown in Fig. 36(a), the detection signal SG1 input to the control IC 148 is in the LOW state at time t4, so as shown in Fig. 36(g), the control IC 148 does not set the start command flag 144c to "1" at time t4. In this case, as shown in Fig. 36(d), at time t5, which is after time t4 and 5 ms after time t3, the control-side CPU 114 clears the latched status 113 to "0."

[0428] 36(a) and (b), at time t6 after time t5, the start lever 41 is pressed down, causing the detection signal SG1 input to the control IC 148 and the control-side CPU 114 to rise from a LOW state to a HIGH state. As shown in FIG. 36(e), at time t7 after time t6 and before time t8, which is 12.8 μs after time t6, the start command setting process is executed.

[0429] At the timing t7, the detection signal SG1 input to the control IC 148 is in a HI state as shown in Fig. 36(a), but since "1" is not set in the latched status 113 as shown in Fig. 36(d), the control IC 148 does not set "1" in the start command flag 144c at the timing t7 as shown in Fig. 36(g). As shown in Fig. 36(i), the control IC 148 increments "1" in the error counter 144b at the timing t7.

[0430] Thereafter, at timing t8, the control side CPU 114 sends a latch signal to the CLK terminal of the random number counter circuits 105a to 105p and sends a pulse signal to the T terminal 113b of the latched status 113, whereby the random number stored in the random number counter 105 is written to the latch register 102 as shown in Figure 36(c) and the latched status 113 is set to "1" as shown in Figure 36(d).

[0431] Thereafter, as shown in Fig. 36(e), a start command setting process is executed at timing t9. At timing t9, as shown in Fig. 36(a), the detection signal SG1 input to the control IC 148 is in a HI state, and as shown in Fig. 36(d), the latched status 113 is set to "1." Therefore, as shown in Fig. 36(g), the control IC 148 sets the start command flag 144c to "1" at timing t9, and clears the error counter 144b to "0" as shown in Fig. 36(i).

[0432] In the normal processing executed at timing t10 ​​after timing t9, the control IC 148 clears the start command flag 144c to "0" as shown in Figure 36(g), and drops the start enable signal to a LOW state as shown in Figure 36(h), thereby ending the period during which the game can be started.

[0433] The control-side CPU 114 clears the latched status 113 to "0" at the timing t9 when the start enable signal falls, as shown in Figure 36(d). Also, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 in the lottery process executed at the timing t9.

[0434] In this way, when the latched status 113 is set to "1" due to noise entering only the control side CPU 114, the latched status 113 is cleared to "0" after 5 ms. This makes it possible to avoid a situation in which the control IC 148 obtains an old random number when the start lever 41 is operated while the latched status 113 is set to "1."

[0435] Furthermore, the control IC 148 is configured to always determine whether or not "1" is set in the latched status 113 when the detection signal SG1 input to the control IC 148 is in a HI state. Therefore, even if the start command setting process is executed before 12.8 μs has elapsed since the rise of the detection signal SG1 output from the start detection sensor 41 a, the control IC 148 can obtain a random number corresponding to the current operation of the start lever 41.

[0436] Next, a case where the start lever 41 is pressed down while the connection between the start detection sensor 41a and the input terminal TB1 of the control-side CPU 114 is disconnected will be described with reference to the time chart of FIG. 37. FIG. 37(a) shows the detection signal SG1 input to the control IC 148, FIG. 37(b) shows the timing of the start command setting process executed by the control IC 148, FIG. 37(c) shows the state of the error counter 144b, and FIG. 37(d) shows the timing of the abnormality notification process. Here, the connection between the start detection sensor 41a and the input terminal TB1 of the control-side CPU 114 is disconnected. The timings t1 to t4 are the periods during which the game can be started.

[0437] As shown in Figure 37(a), when the start lever 41 is operated at timing t1, the detection signal SG1 input to the control IC 148 rises from a LOW state to a HIGH state. Thereafter, as shown in Figure 37(b), the start command setting process is executed at timing t2 and at timing t3, which is approximately 1.49 ms after timing t2. As shown in Figure 37(a), the detection signal SG1 input to the control IC 148 is in a HIGH state from timing t2 to timing t4, but because the detection signal SG1 input to the control-side CPU 114 does not rise, the latched status 113 is not set to "1."

[0438] Therefore, as shown in Fig. 37(c), "1" is added to the error counter 144b at each of the timings t2 and t3. In the start command setting process executed at the timing of t4, "1" is added to the error counter 144b, and the value of the error counter 144b becomes "3." As a result, the control IC 148 clears the error counter 144b to "0" at the timing of t4 as shown in Fig. 37(c), and executes an abnormality notification process as shown in Fig. 37(d), thereby notifying the manager of the gaming hall that "1" has not been set in the latched status 113.

[0439] In this way, in the start command setting process, if an event occurs three times in succession in which it is determined that the detection signal SG1 input to the control IC 148 is in a HI state and it is determined that "1" is not set in the latched status 113, it is possible to avoid a situation in which "1" is not set in the latched status 113 and the win / loss determination of the winning combination is repeated using an old random number that does not correspond to the operation of the start lever 41.

[0440] As described above, the conditions for setting the latched status 113 to "1" in the control-side CPU 114 are set as follows: a period in which the game can be started; detection of a rising edge of the detection signal SG1 input to the control-side CPU 114; and the HI state of the detection signal SG1 input to the control-side CPU 114 continuing for 12.8 μs or more from the detection of the rising edge. Therefore, the conditions for the control IC 148 to set the start command flag 144c to "1" in the start command setting process are narrowed down to the detection signal SG1 input to the control IC 148 being in a HI state and the latched status 113 being set to "1." This reduces the processing load on the control IC 148 for setting the start command flag 144c to "1."

[0441] Furthermore, the timing at which the control-side CPU 114 sets the latched status 113 to "1" is limited to only the period during which the game can be started, and the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 when both the conditions that the detection signal SG1 input to the control IC 148 is in the HI state and that the latched status 113 is set to "1" are satisfied. Therefore, even if the start command setting process is executed before the numerical information of the random number stored in the random number counter 105 is written to the latch register 102, the control IC 148 can acquire the random number corresponding to the operation of the start lever 41.

[0442] In the start command setting process, the control IC 148 acquires the numerical information of the random number input to the input terminal TA3 of the control IC 148 and starts the game, with one condition being that the detection signal SG1 input to the control IC 148 is in a HI state. Since the player is holding down the start lever 41 when the control IC 148 starts the game, even if the timing at which the control IC 148 acquires the numerical information of the random number is delayed due to a difference in the timing at which each process is performed, the game can be started with the player continuing to press down the start lever 41.

[0443] In detail, if the start command setting process is executed after the player starts to press the start lever 41 and before the latched status 113 is set to "1", the start command flag 144c is set to "1" in the next start command setting process, and the game is started.

[0444] For this reason, there are cases where the game is started by setting the start command flag 144c to "1" in the start command setting process that is executed first after the player operates the start lever 41, and cases where the game is started by setting the start command flag 144c to "1" in the start command setting process that is executed second time after the player operates the start lever 41. When the start command flag 144c is set to "1" in the second start command setting process, the timing at which the game starts is delayed compared to when the start command flag 144c is set to "1" in the first start command setting process.

[0445] However, in either case, at the timing when the game starts, the player is still pressing down the start lever 41. Therefore, the game starts after the player has finished pressing down the start lever 41, which makes it possible to avoid giving the player an uncomfortable feeling about the timing when the game starts.

[0446] Furthermore, by configuring the control side CPU 114 to clear the latched status 113 to "0" 5 ms after the latched status 113 is set to "1," it is possible to prevent the latched status 113 from being set to "1" due to noise, and the start lever 41 from being operated while this state is maintained, causing the control IC 148 to obtain an old random number.

[0447] The control-side CPU 114 considers the state in which a game can be started and the detection of the rising edge of the detection signal SG1 by the control-side CPU 114 as some of the conditions for sending a pulse signal to the CLK terminals of the latch register circuits 102a-102p. Therefore, even if the player continues to press the start lever 41 during a game and the start timing of the period in which a game can be started arrives with the start lever 41 pressed down, the game will not start immediately after the start timing. It is possible to configure the game to start only when the start lever 41 is operated within the period in which a game can be started.

[0448] <Fourth embodiment> The hardware random number circuit 146 in this embodiment is equipped with two latch registers 407, 408 (Figure 39). Different random number numerical information is written into the two latch registers 407, 408 at different times. The two random number numerical information written into the two latch registers 407, 408 are used for different lotteries. Note that a description of the same configuration as in the first embodiment will basically be omitted.

[0449] First, referring to Figure 38, we will explain the differences between the correspondence between the winning pattern combinations in this embodiment and the benefits awarded when a winning combination is achieved, compared to the correspondence in the first embodiment (Figure 4).

[0450] In this embodiment, there are two types of cherry combinations: a first cherry combination and a second cherry combination. First, the first cherry combination will be explained. In this embodiment, when the first cherry combination is won, the player enters the preparation state ST31 (Fig. 47) of the AT state ST3 (Fig. 47), which is advantageous for the player. In this embodiment, when the first cherry combination is won and the first cherry combination is won, game media is awarded. In other words, the first cherry combination is a small combination.

[0451] In detail, when the stopped symbol on the left reel 32L on the main line ML is a "cherry" symbol, the first cherry win will occur even if the stopped symbols on the middle reel 32M and the right reel 32R are any symbols other than "cherry" symbols ("bell" symbol, "watermelon" symbol, "replay" symbol, "red 7" symbol, and "white 7" symbol). When the first cherry win occurs, the number of game media to be awarded will be "2" if the game state is other than the BB state. On the other hand, the first cherry win is excluded from the winning targets in the BB state.

[0452] On the other hand, if the first cherry win occurs but the first cherry prize is not awarded, no gaming media will be awarded. In this case, the combination of the symbols on the left reel 32L, the center reel 32M, and the right reel 32R on the main line ML is a combination of symbols that will only be aligned in this case. Therefore, by looking at the combination of symbols, the player can understand that the first cherry win occurred or that the first cherry prize was not awarded.

[0453] Here, the number of games that can be continued is set as the number of games that the AT state ST3 continues. If the first cherry is won when the player is not in the AT state ST3, the number of games that can be continued is set to "30." Also, if the first cherry is won in the AT state ST3, "30" is added to the set number of games that can be continued. When the player transitions to the second RT mode in the preparation state ST31 of the AT state ST3, the player enters the base state ST32 of the AT state ST3 (Figure 47). The number of games that can be continued is not subtracted while the player is in the preparation state ST31, but is subtracted by "1" each time one game ends when the player enters the base state ST32. Details of the AT state ST3 will be described later.

[0454] Next, the second cherry role will be explained. In this embodiment, when the second cherry is won, the player enters the preparation state ST31 (Fig. 47) of the AT state ST3 (Fig. 47), which is advantageous for the player. In this embodiment, when the second cherry is won and the second cherry is won, the game medium is awarded. In other words, the second cherry is won as a small prize.

[0455] In detail, when the stopped symbol on the left reel 32L on the main line ML is a "cherry" symbol, the stopped symbol on the center reel 32M is a "cherry" symbol, and the stopped symbol on the right reel 32R is a "cherry" symbol, a second cherry win is achieved. The number of game media to be awarded when a second cherry win is achieved is "2" in game states other than the BB state. On the other hand, the second cherry win is excluded from the targets for realization in the BB state.

[0456] On the other hand, if the second cherry win occurs but the second cherry win does not occur, no gaming media will be awarded. In this case, the combination of the symbols on the left reel 32L, the center reel 32M, and the right reel 32R on the main line ML is a combination of symbols that will only occur in this case. Therefore, by looking at the combination of symbols, the player can understand that the second cherry win occurred or did not occur.

[0457] If the second cherry is won when not in the AT state ST3, the number of games that can be continued is set to "300". Also, if the first cherry is won in the AT state ST3, "300" is added to the number of games that can be continued. Details of the AT state ST3 will be described later.

[0458] Next, differences between the configuration of main control board 141 of this embodiment and main control board 141 of the first embodiment (FIG. 6) will be described with reference to Figure 39. Figure 39 is a block diagram showing the configuration of main control board 141 of this embodiment.

[0459] As shown in FIG. 39, the main MPU 142 includes a control IC 148 and a hardware random number circuit 146. The configuration of the control IC 148 will be described first. The control IC 148 includes a main ROM 143 that stores various control programs and fixed value data executed by the control IC 148, and a main RAM 144, which is a memory for temporarily storing various data and the like when executing the control programs stored in the main ROM 143. In this embodiment, the main RAM 144 includes a start enable flag 144a, a signal storage flag 144d, a first start command flag 144g, and a second start command flag 144h. The main RAM 144 also includes an addition random number counter (not shown). The addition random number counter updates the addition random number used in the addition lottery. The addition random number counter of the main RAM 144 is a loop counter that adds "1" to the previous value each time an update occurs, and returns to "0" after reaching a maximum value of "65535." The control IC 148 updates the random number for addition in the timer interrupt process (Figure 8) that is executed every 1.49 ms. The addition lottery is held when the watermelon role is won in the game played in the base state ST32 of the AT state ST3, and if the addition lottery is won, the number of games that can be continued is increased.

[0460] 39, the start detection sensor 41a and the control IC 148 are connected by a single signal line. A detection signal SG2 is output from the start detection sensor 41a. The detection signal SG2 is in a LOW state when the start lever 41 is not operated, and is in a HIGH state when the start lever 41 is pressed down.

[0461] The first start command flag 144g is a flag that is set to "1" when a rising edge of the detection signal SG2 input to the control IC 148 is detected, as one of the conditions. The control IC 148 acquires numerical information of the first random number, which is the first random number, when the first start command flag 144g is set to "1". The second start command flag 144h is a flag that is set to "1" when a falling edge of the detection signal SG2 input to the control IC 148 is detected, as one of the conditions. The control IC 148 acquires numerical information of the second random number, which is the second random number, when the second start command flag 144h is set to "1".

[0462] The main RAM 144 of this embodiment differs from the main RAM 144 of the first embodiment in that it does not include the error counter 144b (FIG. 5) and the start command flag 144c (FIG. 5).

[0463] Next, the configuration of the hardware random number circuit 146 will be described. As shown in Fig. 39, the hardware random number circuit 146 of this embodiment includes an update circuit 101 having a random number counter 105, latch registers 407 and 408 to which numerical information of the random number stored in the random number counter 105 is temporarily written, and management circuits 403 and 404 that send latch signals to the latch registers 407 and 408 when an input signal rises to a HI state and the HI state continues for 12.8 μs. In detail, the hardware random number circuit 146 of this embodiment includes a first latch register 407 and a second latch register 408 as latch registers, and a first management circuit 403 and a second management circuit 404 as management circuits.

[0464] 39, one signal line extending from the start detection sensor 41a branches at two branch points 171, 172 on the main control board 141. More specifically, the signal line extending from the start detection sensor 41a branches into two at a first branch point 171 on the main control board 141. One of the signal lines branching at the first branch point 171 is connected to an input terminal TA1 of the control IC 148. Therefore, the detection signal SG2 output from the start detection sensor 41a is input to the input terminal TA1 of the control IC 148.

[0465] Furthermore, the other signal line branched at first branch point 171 branches into two at second branch point 172 on main control board 141. One of the signal lines branched at second branch point 172 is connected to first management circuit 403, and the other signal line branched at second branch point 172 is connected to second management circuit 404 via inversion circuit 431 arranged on main control board 141. Therefore, detection signal SG2 is input to first management circuit 403, and inverted detection signal SG3 generated by inverting detection signal SG2 is input to second management circuit 404.

[0466] The first management circuit 403 is a hardware circuit equipped with a timer counter that subtracts "1" from a set value in 0.1 μs increments. The timer counter is preset to "128." In the first management circuit 403, a countdown by the timer counter is started when the signal input to the first management circuit 403 rises from a low state to a high state. The countdown by the timer counter continues until the timer counter value reaches "0" while the detection signal SG2 input to the first management circuit 403 remains high. When the timer counter value reaches "0," a latch signal is sent from the first management circuit 403 to the first latch register 407. In this case, the timer counter is reset to its initial value of "128." When the timer counter is reset, the initial value is maintained until the detection signal SG2 input to the first management circuit 403 rises again. Furthermore, when the detection signal SG2 input to the first management circuit 403 rises from a LOW state to a HIGH state, a countdown by the timer counter is started, and if the detection signal SG2 falls to a LOW state before the value of the timer counter reaches "0," the countdown by the timer counter is stopped. In this case, the timer counter is reset and the initial value is set.

[0467] The second management circuit 404 has the same configuration as the above-described first management circuit 403. The inversion detection signal SG3 is input to the second management circuit 404. Therefore, the inversion detection signal SG3 rises to a HI state, and a latch signal is output from the second management circuit 404 to the second latch register 408 at the timing when the HI state is maintained for 12.8 μs.

[0468] The update circuit 101 in this embodiment has the same configuration as the update circuit 101 in the first embodiment. Specifically, the update circuit 101 includes a clock circuit 104 and a random number counter 105. The clock circuit 104 outputs a 16 MHz clock signal. The numerical information of the random number stored in the random number counter 105 is updated at the rising edge of the clock signal. The random number counter 105 is made up of 16 random number counter circuits 105a to 105p (FIG. 6), and has a 2-byte storage area. The random number stored in the random number counter 105 is a 16-digit binary number.

[0469] Moreover, each of the first latch register 407 and the second latch register 408 has the same configuration as the latch register 102 in the first embodiment. Specifically, each of the first latch register 407 and the second latch register 408 is composed of 16 D flip-flop circuits and has a 2-byte storage area. The D flip-flop circuits constituting the first latch register 407 are referred to as first latch circuits 407a to 407p, and the D flip-flop circuits constituting the second latch register 408 are referred to as second latch circuits 408a to 408p. Each of the first latch register 407 and the second latch register 408 stores a 16-digit binary number.

[0470] A single signal line extending from the Q terminal of each of the random number counter circuits 105a to 105p branches into two, one of which is connected to the D terminal of each of the first latch circuits 407a to 407p, and the other of which is connected to the D terminal of each of the second latch circuits 408a to 408p. Specifically, a single signal line extending from the Q terminal of each of the random number counter circuits 105a to 105p that stores the nth digit of numerical information in the random number counter 105 is connected to the D terminal of each of the first latch circuits 407a to 407p that store the nth digit of numerical information in the first latch register 407, and to the D terminal of each of the second latch circuits 408a to 408p that store the nth digit of numerical information in the second latch register 408. Here, n is a natural number between 1 and 16.

[0471] 39, the Q terminals of the first latch circuits 407a to 407p are connected to the first management circuit 403, and the Q terminals of the second latch circuits 408a to 408p are connected to the second management circuit 404. In particular, one signal line output from the first management circuit 403 branches into 16 lines which are connected to the CLK terminals of the first latch circuits 407a to 407p, and one signal line output from the second management circuit 404 branches into 16 lines which are connected to the CLK terminals of the second latch circuits 408a to 408p. Also, as shown in FIG. 39, the Q terminals of the first latch circuits 407a to 407p are connected to the input terminal TA8 of the control IC 148, and the Q terminals of the second latch circuits 408a to 408p are input to the input terminal TA9 of the control IC 148.

[0472] Therefore, when a latch signal is sent from the first management circuit 403 to the CLK terminals of the first latch circuits 407a to 407p, the numerical information of the random numbers stored in the random number counter 105 is written to the first latch register 407 and is output to the input terminal TA8 of the control IC 148. Also, when a latch signal is sent from the second management circuit 404 to the CLK terminals of the second latch circuits 408a to 408p, the numerical information of the random numbers stored in the random number counter 105 is written to the second latch register 408 and is output to the input terminal TA9 of the control IC 148.

[0473] The relationship between the state of the detection signal SG2 output from the start detection sensor 41a and the timing at which latch signals are output from the first management circuit 403 and the second management circuit 404 will be described with reference to the time chart of Fig. 40. Fig. 40(a) shows the state of the start lever 41, Fig. 40(b) shows the state of the detection signal SG2 input to the first management circuit 403, Fig. 40(c) shows the state of the timer counter in the first management circuit 403, Fig. 40(d) shows the timing at which the first management circuit 403 sends a latch signal to the first latch register 407, Fig. 40(e) shows the state of the inversion detection signal SG3 input to the second management circuit 404, Fig. 40(f) shows the state of the timer counter in the second management circuit 404, and Fig. 40(g) shows the timing at which the second management circuit 404 sends a latch signal to the second latch register 408.

[0474] As shown in FIG. 40(a), when the start lever 41 is pressed down at time t1, the detection signal SG2 input to the first management circuit 403 rises from a low state to a high state as shown in FIG. 40(b). Then, as shown in FIG. 40(c), at time t1, a timer counter in the first management circuit 403 starts counting time. The timer counter subtracts "1" from its initial value of "128" every 0.1 μs. Furthermore, as shown in FIG. 40(e), at time t1, the inversion detection signal SG3 input to the second management circuit 404 falls from a high state to a low state.

[0475] As shown in FIG. 40(b), the HI state of the detection signal SG2 input to the first management circuit 403 continues from time t1 to time t3. Here, time t3 is later than time t2, which is 12.8 μs after time t1. Therefore, as shown in FIG. 40(c), the timer counter in the first management circuit 403 continues counting from time t1, and the value of the timer counter in the first management circuit 403 becomes "0" at time t2, which is 12.8 μs after time t1. At time t2, when the value of the first management circuit 403 becomes "0," the first management circuit 403 sends a latch signal to the first latch register 407, as shown in FIG. 40(d). As a result, the numerical information of the random number stored in the random number counter 105 at time t2 is written to the first latch register 407 as the numerical information of the first random number.

[0476] As shown in Figure 40(a), when the depression of the start lever 41 is completed at timing t3, the detection signal SG2 input to the first management circuit 403 falls from a HI state to a LOW state as shown in Figure 40(b). Then, as shown in Figure 40(e), at timing t3, the inversion detection signal SG3 input to the second management circuit 404 rises from a LOW state to a HI state. This causes the timer counter in the second management circuit 404 to start counting time as shown in Figure 40(f).

[0477] As shown in FIG. 40(e), the HI state of the inversion detection signal SG3 input to the second management circuit 404 continues even at time t4. Here, time t4 is the time when 12.8 μs have elapsed since time t3. Therefore, as shown in FIG. 40(f), the timer counter in the second management circuit 404 continues counting from time t3, and the value of the timer counter in the second management circuit 404 becomes "0" at time t4, when 12.8 μs have elapsed since time t3. At time t4, when the value of the second management circuit 404 becomes "0," the second management circuit 404 sends a latch signal to the second latch register 408, as shown in FIG. 40(g). As a result, the numerical information of the random number stored in the random number counter 105 at time t4 is written to the second latch register 408 as the numerical information of the second random number.

[0478] When the player presses down the start lever 41 once, the detection signal SG2 output from the start detection sensor 41a rises from a LOW state to a HIGH state, and after this HIGH state is maintained for 12.8 μs or more, it returns to a LOW state, as shown by the operation t1 to t4. By the operation t1 to t4, a first random number is written to the first latch register 407, and a second random number is written to the second latch register 408.

[0479] In this way, the numerical information of the first random number is numerical information of a random number that is written into the first latch register 407 with one condition being that the detection signal SG2 input to the first management circuit 403 rises. In other words, the first random number is a random number that corresponds to the timing when the player starts to press down the start lever 41. In contrast, the numerical information of the second random number is numerical information of a random number that is written into the second latch register 408 with one condition being that the inversion detection signal SG3 input to the second management circuit 404 rises. In other words, the second random number is a random number that corresponds to the timing when the player finishes pressing down the start lever 41.

[0480] The control IC 148 acquires the numerical information of the first random number input to the input terminal of the control IC 148 at the timing of the rising edge of the detection signal SG2 input to the control IC 148, and acquires the numerical information of the second random number input to the input terminal of the control IC 148 at the timing of the falling edge of the detection signal SG2 input to the control IC 148. This allows the control IC 148 to acquire two different random numbers while the player operates the start lever 41 once.

[0481] Since the player's operation of pressing down the start lever 41 is a human action, the duration for which the start lever 41 remains pressed down varies each time. Therefore, in one game, the control IC 148 can perform a lottery using the numerical information of the first random number, as well as a lottery using the numerical information of the second random number, which is a random number asynchronous with the first random number.

[0482] Next, the start command setting process of this embodiment will be described with reference to Fig. 41. The start command setting process is a process executed in step S206 of the timer interrupt process (Fig. 8).

[0483] First, in step S1601, it is determined whether or not the start possible flag 144a is set to "1," thereby determining whether or not it is a period in which the game can be started. If it is a period in which the game can be started (step S1601: YES), it is determined in step S1602 whether or not the signal storage flag 144d is set to "1." If the signal storage flag 144d is not set to "1" in step S1602, it is determined in step S1603 whether or not the detection signal SG2 input to the control IC 148 is in a HI state.

[0484] The fact that the detection signal SG2 is low in step S1603 means that the rising edge of the detection signal SG2, which was low in the previous start command setting process, was not detected. In this case, since the signal storage flag 144d is already "0," this start command setting process is immediatel...

Claims

1. A numerical value updating means for updating the numerical value information; a storage execution means for storing the numerical information updated by the numerical value update means in an acquisition storage means based on the occurrence of a first trigger; a control means for executing a special process using the numerical information stored in the acquisition storage means based on the occurrence of a second trigger; In a gaming machine equipped with The storage and execution means includes: an information setting means for setting acquired information when the first trigger occurs and the acquisition storage means stores the numerical information; a rewriting means for rewriting the numerical information stored in the acquisition storage means to the numerical information updated by the numerical update means at that time when the first trigger occurs again in a situation where the acquired information has already been set; Equipped with The control means a determination means for determining whether or not the second trigger has occurred each time a monitoring timing occurs; a control execution means for executing the special process under at least one condition that the acquired information is set when the determination means determines that the second trigger has occurred; Equipped with The gaming machine includes a means for executing a predetermined control that can grasp a situation in which the second trigger occurs but the acquired information is not set a predetermined number of times, A gaming machine characterized in that even when the rewriting means rewrites the numerical information, the information setting means executes control to set the acquired information.

2. The gaming machine described in Claim 1, characterized in that the first trigger and the second trigger are based on the establishment of a starting condition.

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