Communication terminal and communication system

Abstract

To provide a communication terminal and a communication system that are less susceptible to reflected waves and hardly make signal reading errors.SOLUTION: A communication terminal 30 receives, via a signal line 60, a voltage signal in which a signal voltage is superimposed on a predetermined reference voltage. The communication terminal 30 includes: a signal receiving unit 310 that has a receiving end B and receives the voltage signal; and a voltage clamp circuit 320 that clamps the receiving end B when a voltage at the receiving end B exceeds a first predetermined voltage V1, which is a voltage within a predetermined range from a reference voltage V10. The voltage clamp circuit 320 includes: a reference voltage holding unit 321 that holds the first predetermined voltage V1; and a voltage detection unit 322 that conducts the receiving end B with the reference voltage holding unit 321 when the voltage of the receiving end B exceeds the first predetermined voltage V1.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present disclosure relates to a communication terminal and a communication system.

Background Art

[0002] Conventionally, a communication system that performs load control using two-wire signal lines has been widespread. This communication system is configured by mutually connecting a transmitting terminal, which is a master unit as a central control device, and communication terminals such as switches with two-wire signal lines. This communication system has the feature that the connection, branching, and arrangement of the two-wire signal lines and communication terminals are free (referred to as free topology), and a flexible system configuration is possible. According to this communication system, a communication system can be realized with less wiring in a large-scale building. Patent Document 1 discloses an example of a communication system.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a communication system, there are demands for an increase in the number of communication terminals and high-speed large-capacity communication. As a countermeasure, it is conceivable to increase the signal frequency transmitted from the transmitting terminal. However, when the signal frequency increases, the influence of reflected waves cannot be ignored due to impedance mismatches between the signal line and the transmitting terminal or communication terminals. Due to the influence of reflected waves, signal reading errors occur in the communication terminals.

[0005] In high-frequency signals, impedance matching is typically used to suppress reflected waves. However, because this communication system has a free topology, changes in the arrangement of signal lines and communication terminals alter the characteristic impedance of the signal lines, making impedance matching difficult. A challenge arises from signal reading errors caused by reflected waves as the transmission signals of this communication system become higher in frequency.

[0006] The purpose of this disclosure is to provide a communication terminal and a communication system that are less susceptible to the effects of reflected waves and less prone to signal reading errors. [Means for solving the problem]

[0007] The communication terminal according to this disclosure is a communication terminal that receives a voltage signal in which a signal voltage is superimposed on a predetermined reference voltage via a signal line, and comprises a signal receiving unit having a receiving end that receives the voltage signal, and a voltage clamping circuit that clamps the receiving end when the voltage at the receiving end exceeds a first predetermined voltage which is a voltage within a predetermined range from the reference voltage. The voltage clamping circuit is characterized by having a reference voltage holding unit that holds the first predetermined voltage, and a voltage detection unit that causes the receiving end to conduct to the reference voltage holding unit when the voltage at the receiving end exceeds the first predetermined voltage. [Effects of the Invention]

[0008] According to this disclosure, it is possible to realize a communication terminal and communication system that are less susceptible to the effects of reflected waves and less prone to signal reading errors. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram illustrating the configuration of the communication system according to the embodiment. [Figure 2] This is an equivalent circuit diagram for one form of communication system. [Figure 3] This diagram illustrates the principle of reflected waves in transmission lines. [Figure 4] This is a waveform diagram showing the transmitted signal and its reflected wave in a transmission line. [Figure 5]This is a diagram illustrating the configuration of a communication system including a communication terminal of an embodiment. [Figure 6] This waveform diagram illustrates the suppression of reflected waves in a communication terminal according to the embodiment. [Figure 7] This is a circuit diagram of a communication terminal according to an embodiment. [Figure 8] This is a circuit diagram of a communication terminal in another embodiment. [Figure 9] This is a circuit diagram of a communication terminal in another embodiment. [Figure 10] This is a circuit diagram of a communication terminal in another embodiment. [Modes for carrying out the invention]

[0010] The embodiments of this disclosure will be described in detail below with reference to the drawings. In the following description, specific shapes, materials, directions, numerical values, etc., are examples to facilitate understanding of this disclosure and can be appropriately modified according to the application, purpose, specifications, etc. Furthermore, it is intended from the outset that the components of the embodiments and modifications described below can be selectively combined.

[0011] First, we will describe the overall configuration and general operation of the communication system in which the communication terminal described in this disclosure is used.

[0012] [Communication System] Figure 1 is a diagram of the communication system 10. The communication system 10 includes a transmitting terminal 20, a switch 31 and a terminal unit 32 as communication terminals 30, relays 40a to 40d, and lighting fixtures 50a to 50d. Lighting fixtures 50a to 50d are the controlled objects of the communication system 10. In addition to these devices, the communication system 10 may also be connected to other switches, other terminal units, other controlled objects, etc., but these are not shown in the diagram. The communication system 10 is a system that controls lighting fixtures 50a to 50d, etc., which are the controlled objects of the communication system 10, with the transmitting terminal 20 at its center. Control of lighting fixtures includes on / off control, dimming control, scene control, monitoring control, etc. Scene control is the control of lighting fixtures by adjusting the dimming and color temperature according to the location where the lighting fixture is installed (e.g., Japanese-style room, Western-style room, bedroom, study) and the situation in which the lighting fixture is used (e.g., morning, noon, night, mealtime, family time). Monitoring control is the monitoring of the control status of the lighting fixtures. These controls can be performed by operating switch 31.

[0013] The communication system 10 employs, for example, a time-division multiplex transmission method, and the signal line 60 is composed of a two-wire wire. Signals (information) are transmitted on the signal line 60 by pulse signals caused by the potential difference between the two wires. The communication system 10 also employs, for example, a cyclic transmission method, and signals transmitted from the transmitting terminal 20 pass through all devices connected to the signal line 60. Each device checks the content of the signal, and devices that require the signal receive it according to its content. For example, each device receives the signal if it contains its own address information, and ignores the signal if it does not contain its own address information. In this way, devices connected to the signal line 60 can check the content of signals transmitted from the transmitting terminal 20, even if the signal is not addressed to them.

[0014] The transmitting terminal 20 is a master controller that operates as the central unit in the communication system 10. The transmitting terminal 20 transmits signals from the switch 31 connected to the signal line 60 to the terminal unit 32. The switch 31 and terminal unit 32 in Figure 1 are the communication terminal 30 in this disclosure.

[0015] Switch 31 is a wall switch or the like provided for the user to control (turn on, turn off, dim, etc.) the lighting fixtures 50a to 50d. For example, as shown in Figure 1, switch 31 has four operating parts 31a to 31d. Each operating part has two states, for example, an on state and an off state, and the user can turn the lighting fixture corresponding to each operating part on or off by operating it.

[0016] For example, each control unit is assigned address information, and the address information is associated with each lighting fixture on a one-to-one basis.

[0017] The terminal unit 32 is a device that transmits signals sent from the transmitting terminal 20 to relays 40a to 40d. The terminal unit 32 has multiple terminals, to which relays 40a to 40d are connected.

[0018] Relays 40a to 40d are switches that turn the power supply to the lighting fixtures 50a to 50d connected to them on and off. For example, each relay turns on the power supply to the lighting fixture connected to it when it receives an instruction from the terminal unit 32 to turn on the power supply, and turns off the power supply to the lighting fixture connected to it when it receives an instruction to turn off the power supply. Note that the terminal unit 32 and relays 40a to 40d may be formed as a single unit.

[0019] Lighting fixtures 50a to 50d are installed, for example, on the ceiling of a floor in a facility. Each lighting fixture can be switched on and off, and its dimming rate (brightness) can be changed, for example, by a signal from the transmitting terminal 20. The light source of the lighting fixtures is not limited to LEDs or fluorescent lamps.

[0020] With this communication system 10, wiring to connect the controlled object and the switch 31 on a one-to-one basis becomes unnecessary. The communication system 10 only requires a signal line 60 consisting of two wires. This makes it possible to reduce the amount of wiring in the communication system 10, for example, in a large building.

[0021] The above describes an example where the control target of the communication system 10 is a lighting fixture. However, the control target is not limited to lighting fixtures. The communication system 10 may be configured to control other equipment, such as air conditioning equipment.

[0022] In the communication system 10, when increasing the number of connected terminals or increasing the amount of signal information between terminals, measures are taken to increase the frequency of the signals in order to maintain the system's response. When the frequency of control signals transmitted over the signal line is increased, the effects of reflected waves become apparent. The communication terminal in this disclosure has a configuration that suppresses signal reading errors without being affected by reflected waves.

[0023] The communication system 10 in this disclosure is a free topology and therefore does not require impedance matching. If impedance matching is not achieved, reflected waves will occur. The principle of reflected wave generation will be explained next.

[0024] [Principle of reflected wave generation] The principle of reflected wave generation will be explained with reference to Figures 2 to 4.

[0025] Figure 2 is an equivalent circuit diagram of the smallest unit of the communication system 10 of this disclosure, consisting of a transmitting terminal 20, a signal line 60, and a communication terminal 30.

[0026] Vi is a voltage signal transmitted from the transmitting terminal 20. Point A is the transmitting end of the transmitting terminal 20. Z A This is the output impedance of the transmitting terminal 20. The signal line 60 is connected between point A and point B, and Z ABis the characteristic impedance of the signal line 60. Point B is the receiving end of the communication terminal 30. Z B is the input impedance of the communication terminal 30.

[0027] ρ A represents the reflection coefficient at the transmitting end A, and ρ B represents the reflection coefficient at the receiving end B, and is defined by the following equations respectively. ρ A =(Z A -Z AB ) / (Z A +Z AB ) (Equation 1) ρ B =(Z B -Z AB ) / (Z B +Z AB ) (Equation 2) Let Td be the signal delay time in the signal line 60 (the time required for the signal to propagate from point A to point B).

[0028] The output impedance Z A of the transmitting terminal 20 is set to a low impedance to suppress the voltage drop due to the output current, and Z A <Z AB . Therefore, the sign of the numerator of Equation 1 is negative, and the reflection coefficient ρ A at the transmitting end is negative. The input impedance Z B of the communication terminal 30 is set to a high impedance to maintain the voltage signal amplitude at the receiving end, and Z B >Z AB . Therefore, the sign of the numerator of Equation 2 is positive, and the reflection coefficient ρ B at the receiving end is positive. In the communication system 10 of the present disclosure, unless otherwise specified, the description will be made under this condition.

[0029] Figure 3 is a conceptual diagram showing the reflected wave generated between the transmitting end A and the receiving end B. Figure 4 shows the voltage Vi at the transmitting terminal 20 and the receiving end voltage Vo at the receiving end B. The transmitting terminal 20 of this disclosure outputs a voltage signal in which a negative voltage is superimposed on a constant DC voltage (reference voltage V10). The voltage Vi in Figure 4 represents the voltage when a single voltage signal is transmitted from the transmitting terminal 20. The receiving end voltage Vo in Figure 4 is the voltage observed at the receiving end B and represents a waveform affected by the reflected wave.

[0030] [Reflected wave at the receiving end at time Td] At time 0, the transmitted voltage Vi from the transmitting terminal 20 is equal to the output impedance Z A The voltage V(t), which has been dropped by the voltage drop, propagates along the signal line 60 and reaches the receiving end B after a delay time Td. The receiving end voltage received at receiving end B is delayed by time Td from V(t) and can be expressed as V(t-Td). At receiving end B, since impedance matching is not achieved, a reflected wave is generated for the arrived voltage V(t-Td), which propagates along the signal line 60 and reaches the transmitting end.

[0031] At the receiving end B, the reflected wave is determined by the reflection coefficient ρ, which is equal to the received voltage V(t-Td). B multiplied by ρ B The reflection coefficient at the receiving end B is given by V(t-Td). B Since is positive, the reflected wave ρ B V(t-Td) is a voltage in phase with the voltage V(t). The reflected wave ρ B The voltage V(t-Td) propagates toward the transmitting end from time Td onward. At the receiving end B, the received voltage V(t-Td) and the reflected wave ρ are present. B The combined voltage V(t-Td) is observed. This voltage appears as a voltage that swings significantly in the negative direction from time Td onwards in Figure 4. In this disclosure, the signal that first swings to the negative side at the receiving end B is called the main wave (first wave).

[0032] The voltage generated at the receiving end B from time Td is expressed by the following formula. V(t-Td)+ρ B V(t-Td)=(1+ρ B)V(t-Td) (Equation 3)

[0033] [Reflected wave at the transmitting end at time 2Td] Reflected wave ρ at receiving end B B V(t-Td) reaches the transmitting end at time 2Td (twice the delay time). Since the transmitting end is also delayed by time Td, the arriving reflected wave is ρ B V(t-2Td) is obtained. Even at the transmitting end A, since impedance matching is not performed, reflected waves are generated. ρ B The reflected wave at the transmitting end A for V(t-2Td) is ρ A ρ B The reflection coefficient at the transmitting end A is negative, so the reflected wave ρ A ρ B V(t-2Td) is the voltage ρ reached. B This voltage ρ is in the opposite phase to V(t-2Td). A ρ B V(t-2Td) propagates along the signal line and reaches the receiving end B at time 3Td.

[0034] [Reflected waves at the receiving end from time 3Td onwards] Reflected wave ρ from transmitting end A A ρ B When V(t-2Td) reaches the receiving end B at time 3Td, there is a delay of time Td, so the voltage that arrives is ρ A ρ B The voltage is V(t-3Td). A reflected wave is generated for this reached voltage ρ. A ρ B The reflected wave for V(t-3Td) is ρ A ρ B 2 V(t-3Td) is obtained. The reflected wave ρ from the receiving end B. A ρ B 2 V(t-3Td) propagates to the transmitter. The combined voltage of the voltage that reaches time 3Td and its reflected wave is expressed by the following equation. ρ A ρ B V(t-3Td)+ρ A ρ B 2V(t-3Td)=ρ A ρ B (1+ρ B )V(t-3Td) (Equation 4)

[0035] On the other hand, at the receiving end B, the voltage represented by Equation 3, which occurred at time Td, still exists. Therefore, what is observed at the receiving end B is the combined voltage of the voltages represented by Equation 3 and Equation 4.

[0036] The voltage component represented by Equation 4 has the opposite sign to the voltage component in Equation 3. In Figure 4, the voltage component represented by Equation 4 appears as a voltage that swings to the positive side. In this disclosure, the signal that first swings to the positive side is referred to as the second wave.

[0037] Similarly, at time 5Td, the combined voltage of the voltage reaching the receiving end B and its reflected wave is expressed by the following formula. ρ A 2 ρ B 2 V(t-5Td)+ρ A 2 ρ B 3 V(t-5Td)=ρ A 2 ρ B 2 (1+ρ B )V(t-5Td) (Equation 5) This is the result.

[0038] The voltage component represented by Equation 5 has the same sign as the voltage component in Equation 3, which is positive. This voltage component appears in Figure 4 as the voltage that swings to the negative side for the second time. In this disclosure, this signal is referred to as the third wave.

[0039] Subsequently, reflections are repeated at the receiving end B and transmitting end A at time Td. At the receiving end B, the reflected wave arrives every 2Td of delay time, generating the Mth wave (where M is an integer).

[0040] [Effects of reflected waves in communication systems] In Figure 4, the amplitude direction of the third, fifth, and nth waves (where N is an odd number) is superimposed in the same negative direction as the main wave. When employing a signal transmission method that uses a reference voltage V10 as the ground state and superimposes a negative voltage to create the data signal, there is a risk of mistakenly reading the nth wave, such as the third and fifth waves, as the data signal. The third wave, in particular, which has low attenuation, is problematic.

[0041] Next, we will explain the details of the reflected wave suppression by the communication terminal in this disclosure.

[0042] [Mechanism of reflected wave suppression] Figure 5 is a block diagram showing the configuration of a communication terminal 30 connected to a communication system 10. The communication terminal 30 is connected to a signal line 60 at the receiving end B. A voltage clamp circuit 320, a bypass circuit 330, and a trigger circuit 340 are connected to the receiving end B. B This is the input impedance of the communication terminal 30, including the signal receiving unit 310.

[0043] The signal receiving unit 310 reads the signal from the receiving terminal voltage Vo and decodes the information contained in the signal transmitted from the transmitting terminal 20. The communication terminal 30 performs various operations based on the signal, but the details are omitted.

[0044] The voltage clamp circuit 320 receives the receiving end voltage Vo_ received at the receiving end B. The voltage clamp circuit 320 receives the receiving end voltage Vo_ and holds a first predetermined voltage V1 (hereinafter also referred to as the holding voltage V1). The voltage clamp circuit 320 clamps the receiving end voltage Vo_ to the first predetermined voltage V1 when the receiving end voltage Vo_ is equal to or greater than the first predetermined voltage V1. The first predetermined voltage V1 is set to a voltage within a predetermined range from the reference voltage V10 of the transmission signal of the communication system 10, for example, in the range of 0.3V to 1.4V.

[0045] The bypass circuit 330 is connected to the receiving terminal B and, when the receiving terminal voltage Vo_ exceeds a first predetermined voltage V1, bypasses the receiving terminal B with low impedance to suppress the rise in the receiving terminal voltage Vo_. The bypass circuit 330 operates upon receiving a trigger signal from the trigger circuit 340.

[0046] The trigger circuit 340 generates a trigger signal to activate the bypass circuit 330. The trigger circuit 340 is configured to generate a trigger signal when the receiving terminal voltage Vo_ exceeds a first predetermined voltage V1.

[0047] In the communication terminal 30 of this embodiment, a voltage clamp circuit 320 is provided at the receiving end B. When the second wave of the reflected wave shown in Figure 4 occurs, the receiving end voltage Vo_ is clamped to the first predetermined voltage V1. Specifically, the voltage of the second wave shown in Figure 4 above V1 is cut off. Since the second wave is eliminated, subsequent reflected waves from the third wave onward are also eliminated. This suppresses reflected waves that can cause errors in signal reading by the communication terminal 30.

[0048] In this embodiment, the reflected wave (main wave in Figure 4) generated at the receiving end B when the received signal transmitted from the transmitting terminal 20 first arrives is not suppressed. This is because the polarity of the received signal and the reflected wave at the receiving end B are the same, so only the amplitude increases, and there is no error in signal reading.

[0049] Figure 6 shows the receiving end voltage Vo_, the transmitting end voltage Vi, and the receiving end voltage Vo_ when reflected waves are not suppressed for the communication terminal 30 in this embodiment.

[0050] As described above, the voltage clamp circuit 320 has the effect of cutting off the portion of the receiving end voltage Vo that exceeds the first predetermined voltage V1 (shown by the shaded area in the figure) when reflected waves are not suppressed. In practice, the voltage clamp circuit 320 clamps the first positively polarized voltage (second wave) of the receiving end voltage Vo to the first predetermined voltage V1. This effectively suppresses reflection from the receiving end B to the transmitting end A. As a result, reflection from the transmitting end A is also eliminated, and higher-order reflected waves are eliminated. It can be seen that in the receiving end voltage Vo of the communication terminal 30 in this embodiment, voltages above the first predetermined voltage V1 are cut off. By cutting off the second wave in the receiving end voltage Vo, subsequent reflected waves from the third wave onward are suppressed. Through the above operation, reflected waves are suppressed, and the risk of signal reading errors is eliminated.

[0051] Further explanation will be provided through specific embodiments.

[0052] [First Embodiment] Figure 7(a) shows a circuit diagram of the first embodiment of the communication terminal 30. The signal receiving unit 310 is not shown. In the first embodiment, a voltage clamp circuit 320 and a bypass circuit 330 are connected in parallel to the receiving terminal B.

[0053] The voltage clamp circuit 320 consists of a series circuit of diode D1, resistor R3, and capacitor C1, and a resistor R1 in parallel with capacitor C1. The bypass circuit 330 consists of a series circuit of the emitter-collector of PNP transistor Q1 and resistor R2. Diode D1, resistors R3 and R4, and the emitter-base of transistor Q1 constitute the trigger circuit 340.

[0054] The capacitor C1 and resistor R1 of the voltage clamp circuit 320 constitute the reference voltage holding section 321. Capacitor C1 receives the receiving end voltage Vo_ received at the receiving end B and works to hold a first predetermined voltage V1. Capacitor C1 is set to a capacitance large enough to keep the voltage approximately constant with respect to the frequency of the signal contained in the receiving end voltage Vo_ (i.e., the frequency contained in the transmitted signal). Resistor R1 is the discharge resistor of capacitor C1 and prevents the holding voltage of capacitor C1 from rising excessively above the first predetermined voltage V1. Resistor R1 is set to a relatively high resistance. Diode D1 constitutes the voltage detection section 322. Diode D1 turns on when the receiving end voltage Vo_ becomes higher than the sum of the holding voltage of capacitor C1 and the forward voltage of diode D1, and current flows through resistor R3 to capacitor C1. Since the capacitance of capacitor C1 is set to a sufficiently large capacitance as described above, the voltage hardly changes due to the current through resistor R3. Resistor R3 is selected to have a smaller resistance value compared to resistor R1. The holding voltage V1 of capacitor C1 is maintained at a voltage obtained by subtracting the forward voltage of diode D1 (approximately 0.3~0.7V) from the reference voltage.

[0055] The voltage clamp circuit 320, as described above, prevents the receiving end voltage Vo_ received at receiving end B from rising above the first predetermined voltage V1. This suppresses reflected waves and eliminates the risk of signal reading errors.

[0056] In this embodiment, the bypass circuit 330 is connected in parallel with the voltage clamp circuit 320. The bypass circuit 330 bypasses the current by connecting resistor R2 to the receiving terminal B via transistor Q1, and assists the voltage holding function of the voltage clamp circuit 320.

[0057] In the bypass circuit 330, the emitter of the PNP transistor Q1 is connected to the receiving terminal B, and its collector is connected to one end of resistor R2. The other end of resistor R2 is connected to the circuit ground. It is preferable that resistor R2 be selected to have a low resistance. The base of transistor Q1 is connected to the connection point of resistor R3 and capacitor C1 via resistor R4.

[0058] When the receiving terminal voltage Vo_ rises above the holding voltage of capacitor C1, as described above, diode D1 turns on, and current flows through the path of diode D1, resistor R3, and capacitor C1. At this time, the forward voltage of diode D1 and the voltage drop across resistor R3 cause the base potential to be lower than the emitter potential of transistor Q1, and current flows from the emitter to the base of transistor Q1. As a result, the emitter-collector of transistor Q1 conducts, and a path is formed that bypasses the receiving terminal B through the emitter-collector of transistor Q1 and resistor R2. Since resistor R2 has low resistance, even when transistor Q1 turns on and the receiving terminal voltage Vo_ tries to rise, it bypasses the current and suppresses the rise in the receiving terminal voltage Vo_. The bypass circuit 330 can suppress a rapid rise in the receiving terminal voltage.

[0059] As described above, the diode D1, resistors R3 and R4, and the emitter-base junction of transistor Q1 act as the trigger circuit 340 for the bypass circuit 330. Diode D1 also acts as a voltage detection unit 322, which turns on when the receiving terminal voltage Vo_ becomes equal to or greater than the first predetermined voltage V1 of capacitor C1, thereby activating the trigger circuit 340.

[0060] When the receiving terminal voltage Vo_ falls below the sum of the holding voltage V1 of capacitor C1 and the forward voltage of diode D1 (the second predetermined voltage), diode D1 turns off, the emitter potential of transistor Q1 falls below the base potential of Q1, transistor Q1 turns off, and the bypass circuit 330 stops.

[0061] In other words, in this embodiment, when the receiving terminal voltage Vo_ exceeds a first predetermined voltage, a bypass circuit that bypasses the receiving terminal is activated, and then when the receiving terminal voltage Vo_ falls below a second predetermined voltage that is greater than or equal to the first predetermined voltage, the operation of the bypass circuit is stopped. Note that the first predetermined voltage and the second predetermined voltage are not limited to the relationship in this embodiment. The second predetermined voltage may be set to be the same as the first predetermined voltage.

[0062] As described above in the first embodiment, the operation prevents a voltage higher than the holding voltage V1 of capacitor C1 from occurring at the receiving terminal voltage Vo, thereby suppressing the effects of reflected waves. Therefore, errors in reading the signal can be prevented.

[0063] Figure 7(b) shows a modified version of the first embodiment. The configuration of the voltage clamp circuit 320 and the trigger circuit 340 is the same as in the first embodiment shown in Figure 7(a), except that the connection position of the bypass circuit 330 has been changed from the receiving terminal B to the cathode of diode D1.

[0064] When the receiving terminal voltage Vo rises above the holding voltage of capacitor C1 and diode D1 turns on, the voltage drop caused by the current flowing through resistor R3 makes the base potential of transistor Q1 lower than the emitter potential, causing current to flow from the emitter to the base. Compared to the embodiment in Figure 7(a), the voltage across the emitter-base of transistor Q1 is lower by the forward voltage of diode D1, but the operation of the bypass circuit 330 is the same. The holding voltage V1 of capacitor C1 is held at a voltage obtained by subtracting the sum of the forward voltage of diode D1 and the emitter-base voltage of transistor Q1 (approximately 1.4V) from the reference voltage.

[0065] When the signal voltage is received at receiving terminal B, that is, when the main wave arrives in Figure 6, the voltage at receiving terminal B is lower than the reference voltage V10. Since capacitor C1 of the voltage clamp circuit 320 maintains the holding voltage V1, a voltage V3 is generated from the non-ground terminal of capacitor C1 in the direction of receiving terminal B. In the configuration of Figure 7(a), voltage V3 is applied from the cathode to the anode of diode D1 and simultaneously from the base to the emitter of transistor Q1. When the amplitude of the signal voltage is large, that is, when voltage V3 is large, it is necessary to select a transistor Q1 with a high voltage rating between its terminals.

[0066] In the configuration shown in Figure 7(b), the voltage V3 is generated only from the cathode to the anode of diode D1, which has the advantage of allowing the selection of a transistor Q1 with a low voltage rating between its terminals. The effect of suppressing reflected waves is the same as in Figure 7(a).

[0067] [Second Example] Figure 8 shows a circuit diagram of a second embodiment of the communication terminal 30. In this embodiment, the voltage clamp circuit 320 is connected in parallel to the receiving terminal B, and there is no bypass circuit or trigger circuit.

[0068] The voltage clamp circuit 320 consists of a series circuit of diode D1 and capacitor C1, and a resistor R1 in parallel with capacitor C1. Capacitor C1 is a capacitor for holding the reference voltage, and resistor R1 is the discharge resistor for capacitor C1. Diode D1 turns on when the receiving terminal voltage Vo_ exceeds the holding voltage V1 of capacitor C1, and charges capacitor C1. The capacitance of capacitor C1 is set appropriately, and the voltage hardly changes due to this charging current. Therefore, the receiving terminal voltage Vo_ is clamped to the holding voltage V1 of capacitor C1.

[0069] The second embodiment does not include a bypass circuit. If only a discharge resistor R1 is connected in parallel with capacitor C1, the voltage of capacitor C1 may gradually rise due to the voltage increase of the reflected wave. Specifically, when a signal voltage is repeatedly transmitted from the transmitting terminal 20 and reflected waves in the positive direction from the reference voltage V10 are continuously generated, depending on the resistance value of resistor R1, the capacitor C1 may not be able to discharge sufficiently. If the holding voltage of capacitor C1 rises, the clamp voltage will rise, which may result in insufficient suppression of reflected waves. In the second embodiment, as a countermeasure, a discharge circuit for capacitor C1 is provided using a PNP transistor Q2 and resistors R5 and R6.

[0070] The discharge circuit for capacitor C1 works as follows: when the holding voltage V1 of capacitor C1 is higher than the receiving terminal voltage Vo_, the emitter potential of transistor Q2 becomes higher than the base potential, so transistor Q2 turns on and the charge of capacitor C1 can be discharged through resistor R5. Resistor R5 has a smaller resistance value than resistor R1 and is set to rapidly discharge the charge of capacitor C1. The discharge circuit for capacitor C1 is not limited to this configuration. Any configuration that monitors the voltage of capacitor C1 and connects a discharge resistor when it exceeds a predetermined voltage is acceptable.

[0071] Since the operation of the voltage clamp circuit 320 is the same as in the above-described embodiment, the effect of suppressing reflected waves and preventing errors in reading the signal is the same as in the above-described embodiment.

[0072] [Third Embodiment] Figure 9 shows the circuit diagram of the third embodiment of the communication terminal 30. Elements with the same function as in the first embodiment are given the same circuit symbols. In the third embodiment as well, the voltage clamp circuit 320 and the bypass circuit 330 are connected in parallel to the receiving terminal B.

[0073] In the third embodiment, the voltage clamp circuit 320 consists of a series circuit of diode D1, resistor R8, and capacitor C1, and a resistor R7 connected across the series circuit of resistor R8 and capacitor C1. The bypass circuit 330 consists of a series circuit of the collector-emitter junction of NPN transistor Q1 and resistor R2. The trigger circuit 340 consists of a comparator CP.

[0074] The capacitor C1 of the voltage clamp circuit 320, as in the first embodiment, receives the receiving end voltage Vo_ received at the receiving end B and maintains a first predetermined voltage V1. The capacitance of capacitor C1 is set to be sufficiently large so as to maintain the voltage approximately constant with respect to the frequency of the voltage signal. In the third embodiment, the discharge of capacitor C1 is performed via resistors R8 and R7. Resistor R7 is set to a relatively high resistance. Resistor R8 is set to a smaller resistance than resistor R7. Diode D1, as in the first embodiment, turns on when the receiving end voltage Vo_ becomes higher than the sum of the holding voltage of capacitor C1 and the forward voltage of diode D1, and current flows through resistor R8 to capacitor C1. Since the capacitance of capacitor C1 is set to be sufficiently large as described above, the voltage hardly changes due to the current flowing through resistor R8.

[0075] The bypass circuit 330 is composed of a series circuit of transistor Q1 and resistor R2, similar to the first embodiment. The difference from the first embodiment is that transistor Q1 has been changed to an NPN transistor. By passing current through the base of transistor Q1, transistor Q1 is turned on, and resistor R2 is connected to the receiving terminal B. The bypass circuit 330 in this embodiment also bypasses the current by connecting resistor R2 to the receiving terminal B, and assists the voltage holding function of the voltage clamp circuit 320.

[0076] The trigger circuit 340 of the third embodiment is composed of a comparator CP. The + input terminal of the comparator CP is connected to the connection point of diode D1 and resistor R8. The - input terminal of the comparator CP is connected to the connection point of resistor R8 and capacitor C1. The output terminal of the comparator CP is connected to the base of transistor Q1. The output terminal of the comparator CP is configured as, for example, an open collector, and a pull-up resistor is connected to the control power supply (not shown).

[0077] When the receiving terminal voltage Vo_ rises above the holding voltage V1 of capacitor C1, diode D1 turns on, and current flows through the path of diode D1, resistor R8, and capacitor C1. At this time, the voltage drop across resistor R8 generates an upward voltage across resistor R8 as shown in Figure 9. As a result, the voltage at the + input terminal of comparator CP becomes higher than the - input terminal voltage, so the output terminal of comparator CP outputs a Hi level. When the output terminal of comparator CP becomes Hi level, current flows to the base of transistor Q1, and transistor Q1 turns on. This creates a path that bypasses the receiving terminal B through the collector-emitter junction of transistor Q1 and resistor R2. Resistor R2 has low resistance, so even when transistor Q1 turns on and the receiving terminal voltage Vo_ tries to rise, it bypasses the current and suppresses the rise in the receiving terminal voltage Vo_. The bypass circuit 330 can suppress a rapid rise in the receiving terminal voltage Vo_.

[0078] In the third embodiment, the comparator CP acts as the trigger circuit 340 of the bypass circuit 330. Diode D1 acts as a voltage detection unit 322 that turns on when the receiving terminal voltage Vo_ becomes equal to or greater than the holding voltage V1 of capacitor C1, thereby activating the trigger circuit 340, as in the first embodiment.

[0079] When the receiving terminal voltage Vo_ falls below the holding voltage V1 of capacitor C1, diode D1 turns off, and the current flowing from diode D1 to resistor R8 stops. Subsequently, capacitor C1 gradually discharges through resistors R8 and R7. This discharge current biases resistor R8 in the opposite direction to before, causing the voltage at the - input terminal of comparator CP to become higher than the voltage at the + input terminal, and the output terminal of comparator CP to go low. As a result, the base current of transistor Q1 stops flowing, transistor Q1 turns off, and the bypass circuit stops operating.

[0080] The above operation prevents the receiving terminal voltage Vo_ from becoming higher than the holding voltage V1 of capacitor C1, thereby suppressing the effects of reflected waves. Therefore, errors in signal reading can be prevented.

[0081] [Fourth embodiment] In the fourth embodiment, the comparator CP of the trigger circuit 340 in the third embodiment was replaced with an operational amplifier OP as shown in Figure 10. A power supply circuit consisting of a diode D2 and a capacitor C2 in series is connected to the receiving terminal B. The voltage across capacitor C2 is used as the operating power supply for the operational amplifier OP.

[0082] The configuration of the voltage clamp circuit 320 and the bypass circuit 330 is the same as in the third embodiment, and the operation of the trigger circuit 340 is also the same as in the third embodiment, so a detailed explanation will be omitted.

[0083] In the fourth embodiment as well, it is possible to prevent the receiving terminal voltage Vo_ from being higher than the holding voltage V1 of capacitor C1, thereby suppressing the effects of reflected waves. Therefore, errors in reading the signal can be prevented.

[0084] [Other variations] The circuit configuration for suppressing reflected waves from the communication terminal 30 is not limited to the embodiment described above. For example, the trigger circuit 340 can also be realized using a microcontroller with an analog input terminal. The voltage clamp circuit 320 has the same configuration as in Figure 8, for example. A bypass circuit is formed by connecting a series circuit of a transistor and a resistor in parallel with the receiving terminal B. The receiving terminal voltage Vo_ is input to the analog input terminal of the microcontroller to monitor the receiving terminal voltage Vo_, and when the voltage at the analog input terminal exceeds a predetermined value (holding voltage V1 of capacitor C1), the transistor is turned on to bypass the receiving terminal B with a resistor. With a microcontroller incorporating a program that performs the above operation and the trigger circuit described above, the generation of reflected waves in the positive direction from the reference voltage can be cut off, and errors in reading signals due to reflected waves can be prevented.

[0085] The communication system 10 of this disclosure can be configured not only in which the transmitting terminal 20 transmits a signal and the communication terminal 30 receives it, but also in which the communication terminal 30 transmits a signal and the transmitting terminal 20 receives it. Therefore, it is preferable that the transmitting terminal 20 of the communication system 10 also has the above-mentioned configuration for suppressing reflected waves. Furthermore, it may be configured to allow communication between multiple communication terminals 30.

[0086] In the above embodiment, the explanation has been based on the assumption that impedance matching is not achieved at both the transmitting and receiving ends. However, an impedance matching unit may be provided in either the transmitting terminal or the communication terminal. Specifically, the output impedance of the transmitting terminal 20 may be made equal to the characteristic impedance of the signal line 60, or the input impedance of the communication terminal 30 may be made equal to the characteristic impedance of the signal line 60. In a communication system, if impedance matching is achieved, the effects of reflected waves are basically eliminated, but by providing the communication terminal configuration of this disclosure, the effects of unexpected reflections and noise can be suppressed.

[0087] It should be noted that the present invention is not limited to the embodiments and their modifications described above, and various changes and improvements are possible within the scope of the claims of this application. [Explanation of Symbols]

[0088] 10 Communication system, 20 Transmitting terminal, 30 Communication terminal, 31 Switch, 32 Terminal unit, 40 Relay, 50 Load (lighting fixture), 60 Signal line, 310 Signal receiving unit, 320 Voltage clamp circuit, 321 Reference voltage holding unit, 322 Voltage detection unit, 330 Bypass circuit, 340 Trigger circuit

Claims

1. A communication terminal that receives, via a signal line, a voltage signal in which a signal voltage is superimposed on a predetermined reference voltage, a signal receiving unit having a receiving end for receiving the voltage signal; a voltage clamp circuit that clamps the receiving end when the voltage at the receiving end exceeds a first predetermined voltage that is a voltage within a predetermined range from the reference voltage; The voltage clamp circuit a reference voltage holding unit that holds the first predetermined voltage; a voltage detection unit that makes the receiving end conductive with the reference voltage holding unit when the voltage at the receiving end exceeds the first predetermined voltage; A communication terminal having the above configuration.

2. a bypass circuit for bypassing the receiving end; a trigger circuit that triggers the bypass circuit when the voltage detection unit detects that the voltage at the receiving end exceeds the first predetermined voltage; The communication terminal according to claim 1 .

3. A communication system having a transmitting terminal that transmits the voltage signal and the signal line that transmits the voltage signal, The signal is used in connection with a communication system in which the sign of the reflection coefficient at the transmitting end of the transmitting terminal is different from the sign of the reflection coefficient at the receiving end of the communication terminal.

3. The communication terminal according to claim 1 or 2.

4. a reflection coefficient at the transmitting end is negative and a reflection coefficient at the receiving end is positive; The communication terminal according to claim 3.

5. When the voltage at the receiving end exceeds the first predetermined voltage and then falls below a second predetermined voltage, the bypass circuit stops operating. A communication terminal according to any one of claims 1 to 4.

6. the second predetermined voltage is equal to or greater than the first predetermined voltage; The communication terminal according to claim 5.

7. the reference voltage holding unit has a series circuit of a diode and a capacitor, the voltage detection unit detects that the voltage at the receiving end has exceeded the first predetermined voltage based on the on / off of the diode; the bypass circuit includes a series circuit of a switch and a resistor that is triggered by the voltage detection unit; The communication terminal according to any one of claims 2 to 6.

8. A communication terminal according to any one of claims 1 to 7; a transmitting terminal that transmits the voltage signal; a signal line for transmitting the voltage signal; A communication system comprising:

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