SYSTEM AND METHOD FOR MANAGING CHANNEL BANDWIDTH OF A COMMUNICATION SIGNAL - Patent application

Abstract

Provided herein are embodiments of systems and methods for managing channel bandwidth of signals. Exemplary methods include receiving signals from one or more antenna feeds, each signal having a first bandwidth. Some exemplary methods include performing one or more channelizer operations on portions of the signals in multiple processing blocks operating in parallel in one or more processors, each channelizer operation creating multiple channels having a bandwidth smaller than the first bandwidth. Some methods may include performing one or more combiner operations on the channels in multiple processing blocks in the one or more processors, each operation combining the bandwidths of a subset of the channels into a combined channel, the multiple processing blocks operating in parallel. The method then outputs the combined channel to a network.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 62 / 948,599, filed December 16, 2019, which is incorporated by reference herein as if fully set forth.

[0002] FIELD OF THE DISCLOSURE This disclosure relates to signal processing, and more particularly to implementing distributed computing using general-purpose processors to achieve high speed processing. [Background technology]

[0003] In some instances, satellite communication signals may require large ground stations and other facilities to transmit and / or receive and process the data locally, which may include extensive antenna arrays, associated radio frequency terminals (RFTs), and significant electronics (modems, signal processors, etc.) to receive, process, and use the data received from the associated satellites. Summary of the Invention

[0004] The present disclosure provides an improved communication system. The following summary is not intended to define all aspects of the invention, and other features and advantages of the disclosure will become apparent from the following detailed description, including the drawings. It is understood that the present disclosure is intended to be related as a unified document, and that all combinations of features described herein are contemplated, even if the combinations of features are not found together in the same sentence, paragraph, or section of the disclosure. Furthermore, the present disclosure includes, as an additional aspect, all embodiments of the invention that are narrower in scope in any way than the variations specifically mentioned herein.

[0005] As disclosed herein, digital signal processing (DSP) can be performed in many different ways using a general purpose processor or a central processing unit (CPU). Exemplary techniques implemented on a general purpose processor to achieve high speed processing capable of performing the disclosed functions include, but are not limited to: Use of multiple CPUs and parallel processing across many cores of each CPU, Use of Single Instruction Multiple Data (SIMD) techniques, Feedforward processing to break down feedback loops, Pre-computing metadata (or state information) to split the heavy lifting across several CPUs, and There is a collection of multiple functions into a single function to improve CPU performance or reduce memory bandwidth usage.

[0006] One way to improve the throughput of a general-purpose CPU is to utilize as many cores as possible on the CPU. This allows processing throughput to increase with the addition of more CPU cores, although great care must be taken to ensure that data is properly shared among the several cores within the CPU. It is also possible to use multiple CPUs on the same system, with each CPU containing multiple cores. All embodiments within this disclosure utilize the use of multiple cores in a CPU, and some embodiments utilize having multiple CPUs per system and / or group of systems in a server environment.

[0007] Another way to achieve high processing speeds is to take advantage of the single instruction, multiple data (SIMD) capabilities of general-purpose CPUs. This allows a single CPU core to perform up to 16 floating-point operations per single instruction, as in the case of AVX512 SIMD operations. One example of using SIMD is using a finite impulse response (FIR) filter function, where 16 floating-point results are calculated at once. Another example is when multiplying complex numbers together. Instead of calculating one pair of quadrature signals (IQ data), it is possible to calculate eight IQ pairs at once using AVX512. Complex multiplication is used in almost all processing algorithms described in this disclosure. Other examples of using SIMD include correlators in diversity combiners, decimation in signal analyzers, and conditioning in channelizers / combiners.

[0008] Some processing systems implement various forms of feedback, often involving phase-locked loops (PLLs) or delay-locked loops (DLLs). However, as is the case with PLLs and DLLs, feedback can be problematic because the very nature of feedback creates a bottleneck. Feedback loops force all incoming data to be processed through a single (e.g., linear) process that cannot be easily spilled or divided. In addition to feedback, there are other obstacles to overcome using PLLs and DLLs, including the frequency with which the error term is calculated. The feedback loop can be replaced with a feedforward loop, in which an error state can be processed on a block of data, and the calculated error term is then fed forward to another block that applies the error term. If appropriate overlap is used, the error calculation and application of the term can be split across several CPU cores to further increase throughput. An example of this is a diversity combiner, in which timing and phase corrections are calculated in one block, timing adjustments are applied in another block, and phase corrections are applied in yet another block. This method as a set can then be parallelized across several CPU cores to further increase throughput.

[0009] In addition to the feedforward approach to processing data, it may be beneficial to perform metadata precalculation within a single block and then split the processing of the data across several CPU cores. This method is similar to the feedforward method already described, but in this case, rather than splitting a loop (such as a feedback loop), the block simply leverages more CPU cores to increase the amount of data that can be processed. In this way, the block performing the precalculation does not perform CPU-intensive processing, but instead calculates necessary steps such as the iteration and start index in a for loop and the slope point between interpolated phase values. One such example is Doppler compensation performed in a diversity combiner. The required phase adjustment is created in the first block, but the CPU-intensive calculations to perform the phase adjustment are handed off downstream to a subsequent block. If the second part of the processing is CPU-intensive, this allows for the utilization of any number of CPU cores, thereby increasing processing speeds that would otherwise not be achievable within a single block.

[0010] Another technique that can be used on a general-purpose CPU to achieve high throughput is the way in which sets of functions are used and the memory type used. In some cases, memory bandwidth is the limiting factor for performance. When this is the case, the goal is to limit the amount of data that needs to be transferred to and from random access memory (RAM) (as opposed to fast memory like the CPU cache). To do this, functions need to be folded so that they all execute together rather than individually, with the goal of accessing the slower RAM as little as possible compared to accessing the faster CPU cache. Another way to reduce memory bandwidth is to utilize appropriate spatial memory types, for example, using int8 when possible versus float or double.

[0011] In one embodiment, a method for managing channel bandwidth of one or more downlink signals is provided herein. The method includes receiving one or more downlink signals from one or more antenna feeds, the one or more downlink signals having a first bandwidth. The method also includes performing, in a first one or more processing blocks within one or more processors, a first channelizer operation on first portions of the one or more downlink signals to create a first plurality of channels, each of the first plurality of channels having a bandwidth smaller than the first bandwidth. The method also includes performing, in a second one or more processing blocks within the one or more processors in parallel with the first one or more processing blocks, a second channelizer operation on second portions of the one or more downlink signals to create a second plurality of channels, each of the second plurality of channels having a bandwidth smaller than the first bandwidth. The method further includes performing, in a third one or more processing blocks within the one or more processors, a combiner operation that combines a subset of the first plurality of channels and a subset of the second plurality of channels into a combined channel, the combined channel having a second bandwidth that is smaller than the first bandwidth, and then outputting the combined channel to a network.

[0012] In another embodiment, another method for managing channel bandwidth of one or more downlink signals is provided herein. The method includes receiving one or more downlink signals from one or more antenna feeds, the one or more downlink signals having a first bandwidth. The method also includes performing, in a first one or more processing blocks within one or more processors, a first channelizer operation on first portions of the one or more downlink signals to create a first plurality of channels, each of the first plurality of channels having a bandwidth smaller than the first bandwidth. Additionally, the method includes performing, in a second one or more processing blocks within the one or more processors in parallel with the first one or more processing blocks, a second channelizer operation on second portions of the one or more downlink signals to create a second plurality of channels, each of the second plurality of channels having a bandwidth smaller than the first bandwidth. The method then outputs the first and second plurality of channels to a network.

[0013] In another embodiment, another method for managing channel bandwidth of one or more downlink signals is provided. The method includes receiving input signals of one or more downlink signals over a plurality of input channels, each input channel having a spectral bandwidth, and performing, in a plurality of processing blocks within one or more processors, a combiner operation on the input channels that combines the spectral bandwidths of a selected subset of the plurality of input channels into a combined channel, the plurality of processing blocks operating in parallel. The method then outputs the combined channel to a network.

[0014] In another embodiment, a system for managing channel bandwidth, or one or more downlink signals, is provided. The system includes one or more antennas configured to receive the multiple downlink signals, a digitizer operable to convert the received analog signals into a digital bitstream, and one or more processors communicatively coupled to the multiple antennas. The one or more processors have multiple processing blocks and are operable to perform one or more of the methods described above. [Brief explanation of the drawings]

[0015] The details of the present invention, both as to its structure and operation, can be gleaned in part from study of the accompanying drawings, in which like reference numerals refer to like parts and in which:

[0016] [Figure 1] 1 is a diagrammatic representation of one embodiment of a communication system according to embodiments disclosed herein. [Figure 2] 2 is a functional block diagram of a wired or wireless communication device for use as one or more components of the system of FIG. 1. [Figure 3] 1 is a diagrammatic representation of one embodiment of feedforward or pre-computed signal processing according to embodiments disclosed herein. [Figure 4] 4 is a diagrammatic representation of another embodiment of the feedforward or pre-computed signal processing of FIG. 3, according to embodiments disclosed herein. [Figure 5] FIG. 2 is a functional block diagram of one embodiment of a digital signal diversity combiner according to embodiments disclosed herein. [Figure 6] FIG. 6 is a functional block diagram of example processing blocks included in the diversity combiner of FIG. 5 according to embodiments disclosed herein. [Figure 7] FIG. 6 is a functional block diagram of example processing blocks included in the diversity combiner of FIG. 5 according to embodiments disclosed herein. [Figure 8]FIG. 6 is a functional block diagram of example processing blocks included in the diversity combiner of FIG. 5 according to embodiments disclosed herein. [Figure 9] 7 is a functional block diagram of exemplary functional blocks of the processing block of FIG. 6 according to embodiments disclosed herein. [Figure 10] 7 is a functional block diagram of exemplary functional blocks of the processing block of FIG. 6 according to embodiments disclosed herein. [Figure 11] 9 is a functional block diagram of exemplary functional blocks of the processing block of FIG. 8 according to embodiments disclosed herein. [Figure 12] FIG. 2 is a functional block diagram of one embodiment of a digital signal channelizer according to embodiments disclosed herein. [Figure 13] FIG. 2 is a functional block diagram of one embodiment of a digital signal combiner according to embodiments disclosed herein. [Figure 14A] FIG. 2 is a functional block diagram of an embodiment of a digital signal channelizer and combiner according to embodiments disclosed herein. [Figure 14B] FIG. 2 is a functional block diagram of an embodiment of a digital signal channelizer and combiner according to embodiments disclosed herein. [Figure 15] 13 is a functional block diagram of exemplary processing blocks for the digital signal channelizer of FIG. 12 according to embodiments disclosed herein. [Figure 16] FIG. 14 is a functional block diagram of example processing blocks for the digital signal combiner of FIG. 13 according to embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0017] Disclosed are embodiments of an improved communication system for achieving high-speed processing using a general-purpose processor. The embodiments disclosed herein provide an improved communication system that can efficiently achieve high-speed signal processing by utilizing a general-purpose processor. After reading this specification, it will become apparent to those skilled in the art how to implement the invention in various alternative embodiments and applications. However, while various embodiments of the invention are described herein, it is understood that these embodiments are presented only by way of example and illustration, and not limitation. Accordingly, this detailed description of various embodiments should not be construed as limiting the scope or breadth of the invention, which is set forth in the appended claims.

[0018] Throughout this specification, a reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0019] Although a communications system is used as the primary example throughout the description, application of the disclosed methods is not so limited. For example, any wireless or wireless communications system requiring the use of digital signal processing, modems, etc. may implement the systems, methods, and computer-readable media described herein.

[0020] This disclosure provides systems and methods for performing digital signal processing using general-purpose central processing units (CPUs) in either standard server environments or virtualized cloud environments. In some examples, the systems can use single-instruction, multiple-data (SIMD) techniques to achieve high throughput, including the SSE, SSE2, SSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX512 instruction sets. This disclosure describes how data processing is managed across multiple processing cores of a processor (e.g., a CPU) to achieve the required throughput without the use of specialized signal processing hardware, such as field-programmable gate arrays (FPGAs), or high-performance computing (HPC) hardware, such as graphics processing units (GPUs). The ability to perform this processing on general-purpose server CPUs, including, but not limited to, x86 architectures manufactured by Intel and AMD microprocessors, as well as ARM processors such as Cortex-A76, NEON, and AWS Graviton and Graviton2 processors, enables the deployment of functions within general-purpose cloud processing environments using virtualized processing architectures without the need for specialized hardware. Processing in the general-purpose CPU is enabled by a digital IF device that samples the analog signal and provides digitized samples to the CPU via an Ethernet connection. The digital IF device can also accept digitized samples and convert them to an analog signal, similar to that described in U.S. Patent No. 9,577,936, entitled "Packetized Radio Frequency Transport System," issued February 21, 2017, the contents of which are incorporated by reference in their entirety.

[0021] 1 is a diagrammatic representation of one embodiment of a communications system. Communications system (system) 100 may include a platform 110 and a satellite 111 communicating with multiple ground stations. Platform 110 may be an aircraft (e.g., an airplane, a helicopter, or an unmanned aerial vehicle (UAV)). Multiple ground stations 120, 130, and 140 may be associated with a terrestrial radio frequency (RF) antenna 122 or one or more satellite antennas 132 and 142. Ground station 120 may include an antenna 122 coupled to a digitizer 124. Digitizer 124 may include one or more analog-to-digital converters (A2D) for converting analog signals received at antenna 122 into a digital bit stream for transmission over a network. Digitizer 124 may also include corresponding digital-to-analog converters (D2A) for operation on the uplink to platform 110 and satellite 111.

[0022] Similarly, ground station 130 may have an antenna 132 and a digitizer 134 , and ground station 140 may have an antenna 142 and a digitizer 144 .

[0023] Ground stations 120, 130, 140 can each receive downlink signals 160 (labeled 160a, 160b, 160c) from platform 110 and downlink signals 170 (labeled 170a, 170b, 170c) from satellite 111 in a receive chain. Ground stations 120, 130, 140 can also transmit uplink signals via respective antennas 122, 132, 142 in a transmit chain. Digitizers 124, 134, 144 can digitize the received downlink signals 160, 170 for transmission as digital bitstream 152. Digital bitstream 134 can then be transmitted to a cloud processing system via network 154.

[0024] In some examples, the ground stations 120, 130, 140 can process all of the data (e.g., contained in the downlink signal) locally, but this can be prohibitively expensive in terms of time, resources, and efficiency. Therefore, in some embodiments, the downlink signal can be digitized and transmitted as a digital bit stream 152 to a remote signal processing server (SPS) 150. In some implementations, the SPS 150 can be located in a physical location, such as a data center located in an off-site facility accessible via a wide area network (WAN). Such a WAN can be, for example, the Internet. The SPS 150 can demodulate the downlink signal from the digital bit stream 152 and output data or information bits from the downlink signal. In some other implementations, the SPS 150 can use cloud computing or cloud processing to perform the signal processing and other methods described herein. The SPS 150 may also be referred to as a cloud server.

[0025] The SPS 150 can then provide the processed data to a user or transmit it to another site. The data and information may depend on the mission. Additionally, the information contained in the data may be the primary purpose of the satellite, including weather data, image data, and satellite communications (SATCOM) payload data. As mentioned above, SATCOM is used as the primary example herein, but any communications or signal processing system using a DSP may implement the methods described herein.

[0026] To achieve high processing speeds using software, a phase-locked loop (PLL) or delay-locked loop (DLL) approach can be problematic due to feedback within the loop. The feedback loop forces all of the incoming data (e.g., downlink signal 132) to be processed through a single (e.g., linear) process that cannot be easily spilled or divided. In addition to feedback, there are other obstacles to overcome using a PLL / DLL, including, for example, the frequency at which error terms must be calculated.

[0027] Figure 2 is a functional block diagram of a wired or wireless communication device for use as one or more components of the system of Figure 1. Processing device (device) 200 may be implemented, for example, as SPS 150 of Figure 1. Device 200 may be implemented as needed to perform one or more of the signal processing methods or steps disclosed herein.

[0028] The device 200 may include a processor 202 that controls operation of the device 200. The processor 202 may also be referred to as a CPU. The processor 202 may direct and / or execute functions attributed to, for example, the SPS 150. Some aspects of the device 200, including the processor 202, may be implemented as various cloud-based elements, such as cloud-based processing. Thus, the processor 202 may represent cloud processing distributed across several different processors over a network (e.g., the Internet). Alternatively, some components may be implemented in hardware. The processor 202 may be implemented with any combination of one or more of a general-purpose microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a state machine, gate logic, discrete hardware components, a dedicated hardware finite state machine, or any other suitable entity capable of performing calculations or other manipulations of information.

[0029] The processor 202 may have one or more cores 204 (shown as cores 204a through 204n) capable of performing computations. In implementations using cloud processing, the cores 204 may represent multiple iterations of distributed cloud processing. In some embodiments, using hardware, the processor 202 may be a complex integrated circuit in which all computations for the receiver are performed. As used herein, each core 204 may be one processing element of the processor 202. The processor 202 may implement multiple cores 204 to perform the parallel processing required for the methods disclosed herein. In some embodiments, the processor 202 may be distributed across multiple CPUs, as in cloud computing.

[0030] The device 200 may further include a memory 206 operatively coupled to the processor 202. The memory 206 may be cloud-based storage or local hardware storage. The memory 206 may include both read-only memory (ROM) and random access memory (RAM) that provide instructions and data to the processor 202. A portion of the memory 206 may also include non-volatile random access memory (NVRAM). The processor 202 typically performs logical and arithmetic operations based on program instructions stored in the memory 206. The instructions in the memory 206 may be executable to implement the methods described herein. The memory 206 may further include removable media or multiple distributed databases.

[0031] The memory 206 may also include a machine-readable medium for storing software. Software shall be broadly construed to mean any type of instructions, whether referred to as software, firmware, middleware, microcode, hardware description language, or the like. The instructions may include code (e.g., in source code format, binary code format, executable code format, or any other suitable code format). The instructions, when executed by the processor 202 or one or more cores 204, cause the device 200 (e.g., SPS 150) to perform various functions described herein.

[0032] The device 200 may also include a transmitter 210 and a receiver 212 to enable transmission and reception of data between the communication device 200 and a remote location. Such communication may occur, for example, between the ground station 120 and the SPS 150 via the network 124. Such communication may be wireless or may occur via wired communication. The transmitter 210 and the receiver 212 may be combined into a transceiver 214. The transceiver 214 may be communicatively coupled to the network 124. In some examples, the transceiver 214 may include or be part of a network interface card (NIC).

[0033] Device 200 may further include a user interface 222. User interface 222 may include a keypad, a microphone, a speaker, and / or a display. User interface 222 may include any element or component that conveys information to and / or receives input from a user of device 200.

[0034] The various components of device 200 described herein may be coupled together by a bus system 226. The bus system 226 may include, for example, a data bus, and in addition to the data bus, a power bus, a control signal bus, and a status signal bus. In some embodiments, the bus system 226 may be communicatively coupled to the network 124. The network 124 may provide, for example, a communications link between the device 200 (e.g., the processor 202) and the ground station 120. Those skilled in the art will understand that the components of device 200 may be coupled together or may accept or provide input to each other using some other mechanism, such as a local area network or a wide area network for distributed processing.

[0035] 3 is a schematic block diagram representation of feedforward or pre-computation signal processing 300. Method 300 can be performed, for example, as a generalized process incorporating multiple functions by processor 202. Processor 202 can perform multiple functions in a serial or parallel arrangement, as shown, to perform one or more desired processes. Each function can refer to a block or collection of instructions or software executable by processor 202 and stored in memory 206.

[0036] The first function 302 may be executed by the processor 202. In some embodiments, the first function 302 may be followed by the second function 304 in series. Thus, the processor 202 may divide blocks of data for different functions for processing on multiple cores 204 to execute the first function 302 and the second function 304.

[0037] The processor 202 can perform distributed processing of a third function 306 (shown as 306a, 306b...306n) in parallel following the second function 304. Parallel processing of the third function 306 can include, for example, dividing a block of data associated with the same function across several cores 204 (e.g., processing blocks) of the processor 202. For example, a "block of data" can refer to a group of samples that need to be processed.

[0038] The processor 202 can then serially execute the fourth function 308 and the fifth function 309. Similar to the first function 302 and the second function 304, the serial performance of the fourth function 308 and the fifth function 309 may include dividing up blocks of data associated with different functions for processing across multiple cores 204. Generally, each of the first function 302, the second function 304, the third function 306, the fourth function 308, and the fifth function 309 may each be executed by a different processing block. As used herein, a processing block may refer to a particular task performed on a block of data. A processing block may be associated with one or more of the cores 204, for example.

[0039] Thus, method 300 may, for example, divide blocks of data relating to the same function for processing across multiple cores 204. Similarly, method 300 may divide blocks of data relating to different functions for processing across multiple cores 204.

[0040] In some other implementations of method 300, the same processing block (e.g., core 204), whether the same function or a different function, may perform processing of data using single instruction multiple data (SIMD).

[0041] In other implementations, embodiments of method 300 can support processing blocks of data with minimal state information by using overlapping data. As used herein, state information can include variables needed during feedback (e.g., feedback processing), data frame boundaries, etc. For example, in the case of a feedback loop, the state information can include variables calculated within the loop that are needed during feedback when processing a continuous data stream. The state information can also include the location of frame boundaries within the data stream. Other examples can include things like FIR filters, where the state information includes values ​​stored in buffers (e.g., perhaps many delay elements) needed to maintain a continuous data flow.

[0042] By ignoring state information and overlapping portions of adjacent blocks of data, a process can use variable levels of overlap between blocks of data to take advantage of parallel processing.

[0043] FIG. 4 is a diagrammatic representation of one embodiment of the method for feedforward or pre-computation signal processing of FIG. 3. Method 400 can use the principles of method 300 for serial-parallel and / or parallel-serial processing for multiple functions. In one example, first function 302 (FIG. 3) can be data ingestion function 305, where processor 202 receives data for processing. Second function 304 (FIG. 3) can be data partitioning function 310, where processor 202 can analyze data in overlapping blocks of data. The overlapping blocks of data can then be processed in parallel in various parallel iterations of third function 306a-306n as processing blocks 315a-315n. The overlap in blocks of data can provide a level of redundancy that relies less (or not at all) on state information. The less state information required, the easier it is to process blocks of data in parallel, as opposed to a continuous stream.

[0044] The method 400 may further include a data combining function 320, similar to the fourth function 308 (FIG. 3), that combines the processed data, and a data output function 325, similar to the fifth function 309 (FIG. 3).

[0045] In a further example, the adjustable series-parallel or parallel-series arrangement of the various functions of method 300 provides several ways to implement feedforward processing to replace feedback loops, which is advantageous because it can increase throughput and avoid bottlenecks caused by feedback processing delays.

[0046] A further advantage of the serial-parallel or parallel-serial processing provided by method 300 and method 400 is that placing one or more of the desired algorithms within a processing block (e.g., one of the five processing blocks of method 300) allows processor 202 to distribute the processing load (e.g., across multiple cores 204) without worrying about the speed of a given algorithm within a processing block (e.g., core 204). Thus, each core 204 shares the exact same processing load, eliminating bottleneck problems caused by individual algorithms.

[0047] Further advantages of embodiments of method 300 may include customizing the particular ordering of algorithms (e.g., processing blocks) to reduce computational load within processor 202. As described below, the overall multi-stage processing of a given process may be agnostic to the ordering of multiple sub-processes. Thus, in some examples, ordering the fourth function 308 may have certain advantages if it is performed before the third function 306.

[0048] The method 300 can further implement different mutable types for memory bandwidth optimization, such as, for example, int8, int16, and float, which can accelerate some algorithms (e.g., based on type). Additionally, this can provide increased flexibility for maximizing memory bandwidth.

[0049] 5 is a functional block diagram of one embodiment of a digital signal diversity combiner. The method 500 for diversity combining can include feedforward block processing as described above. The method 500 includes multiple blocks. In some examples, each block represents a processing block and may perform a function in a manner similar to processing blocks 315a, 315b...315n (FIG. 4), etc. In other examples, multiple blocks can be grouped together as a single "processing block" that performs a function in a manner similar to processing blocks 315a, 315b...315n (FIG. 4), etc.

[0050] 12-16 are functional block diagrams of various embodiments of a channelizer and a combiner. The methods illustrated in FIGS. 12-14B illustrate exemplary processes including pre-computed signal processing. Similar to method 500, one or more of methods 1200, 1300, 1400a, 1400b, 1500, and / or 1600 may include multiple processing blocks. In some examples, each block may represent a processing block and perform a function in a manner similar to processing blocks 315a, 315b...315n (e.g., FIG. 4), etc. In other examples, multiple blocks may be grouped together as a single "processing block" that performs a function in a manner similar to processing blocks 315a, 315b...315n (e.g., FIG. 4), etc. For example, FIG. 15 diagrammatically illustrates an exemplary processing block implemented as a channelizer processing block 1500, and FIG. 16 diagrammatically illustrates an exemplary pre-computed processing block implemented as a combiner processing block 1600. The sub-elements or blocks of block 1500 may be performed separately or combined into a single block as shown in Figure 15. Similarly, the sub-elements or blocks of block 1600 may be performed separately or combined into a single block as shown in Figure 16.

[0051] In block 305, the SPS 150 may capture or otherwise receive (e.g., over the network 124) the digital bitstream 134. The data capture in block 305 may receive the digital bitstream 134 data from a network connection (e.g., Ethernet).

[0052] In block 310, the data may be separated into parallel data streams by a data splitter. In some embodiments, the processor 202 may perform the data separation function required in block 310. In some other embodiments, a separate data separation component (e.g., a data splitter) may be included in the device 200 (FIG. 2). Separating the data into multiple parallel streams may enable parallel processing of the downlink signal 132. Thus, the method 300 may utilize feedforward or pre-computation processing to enable the incoming digitized signal data to be broken down into smaller pieces and then processed on multiple cores 204. The digital bit stream 134 may be separated to form overlapping packets in in-phase / quadrature (I / Q) pairs. In some embodiments, "overlapping packets" may include data packets where successive packets overlap with adjacent data packets. In some embodiments, the data packets may all be the same length, but may overlap. The overlap of a data packet may be at the beginning or end of the data packet. In addition, a data packet may overlap with both a preceding and a following data packet. Also, the data packets can have different lengths (e.g., different amounts of data), and thus a first packet sent to processing block 315a may overlap or otherwise repeat some data in a second packet sent to processing block 315b.

[0053] The amount of overlap, or overlap size, between packets is programmable and can be set as needed. In some examples, the overlap can be set to one percent (1%) of the packet size. This overlap size can be increased or decreased as needed. For example, one particular parameter that can affect the overlap size is the uncertainty in the symbol rate in the data stream 134. For most signals, the worst-case uncertainty is less than 1%, so 1% covers most cases. In some other embodiments, the overlap can be as high as 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, or 10%, or anywhere in between, as needed. Similarly, it is also possible to have an overlap of less than 1%. If the uncertainty in the data rate is less than 0.1%, the overlap can be 0.1% or less.

[0054] The processor 202 can perform single instruction, multiple data (SIMD) processing on the digital bitstream 134. In some examples, SIMD can include advanced vector extensions using 512 bits (AVX-512), which allows 16 floating-point operations on a single CPU core on a single CPU instruction. For example, AVX-512 enables a CPU (e.g., CPU 202) to process vast amounts of data. For example, the processor 202 (and device 200) can receive a 500 MHz bandwidth data stream. 500 MHz bandwidth is significant in some respects because it is the commonly accepted practical limit of a 10 Gigabit Ethernet link. Sampling data at 500 MHz, with 8-bit samples for I / Q pairs, including parity bits, could saturate a 10 Gigabit Ethernet link. The 500 MHz example is not limiting of this disclosure. Data pipes larger than 10 Gigabit Ethernet links are possible. Additionally, the processing can be separated into n parallel blocks (eg, block 315) to accommodate any amount of data.

[0055] Block 315 is shown with a dashed line and indicates a processing step of method 300. Block 315 is illustrated with multiple parallel steps, i.e., blocks 315a, 315b, through 315n. The term "parallel" is used herein to describe processing occurring simultaneously or at the same time in processing blocks 315a through 315n. Packets being processed may be of different lengths from one processing block 315 to another, and thus, processing of packets may have the same rate or speed from one processing block 315 to the next. As discussed below, some of the processing blocks 315 may proceed faster or slower than others. Thus, the term parallel is not intended to be limited to simultaneous or parallel processing within processing blocks 315.

[0056] As used herein, a processing block 315 may refer to a collection of processing functions performed by the processor 202, for example. The digital bitstream 134 may be sent to multiple parallel processing blocks 315a, 315b, . . . 315n to distribute the processing load across several cores 204. Each individual processing block 315a, 315b, . . . 315n may represent an individual iteration of cloud processing. Thus, the processing of each processing block 315a-315n may be associated with a (cloud-based) core 204a-204n. The number of processing blocks 315 required varies based on the amount of data to be processed. In some embodiments, the number of processing blocks 315 may be limited by the number of logical cores available within the processor 202, via the network 154, or for local hardware processing. In some other embodiments, memory bandwidth constraints may cause a bottleneck in signal processing. Memory bandwidth may refer to the rate at which data can be read from or stored to a semiconductor memory (e.g., memory 206) by a processor (e.g., processor 202).

[0057] In some embodiments, the number of processing blocks 315 may vary. In general, the fewer processing blocks 315 there are, the better to limit the number of cores required for the overall process. This also allows the system to fit into smaller virtual private cloud (VPC) machines, which are cheaper to operate. A VPC may include, for example, an SPS 150 with several CPUs. In some embodiments, eight processing blocks 315 may be used for a 10 Gigabit Ethernet link. Such an embodiment may not include a forward error correction processing block. In some other embodiments, the only practical limit on the number of processing blocks 315 required is the bit rate and bandwidth (e.g., pipe size) of the communication link. Thus, any number (n) of processing blocks 315 is possible. However, in some embodiments, there may be a practical limit on the number (n) of processing blocks 315 based on the number of threads that can run on a CPU or the number of cores 204 in the processor 202. However, if a limit is reached within a single CPU, multiple CPUs (e.g., processors 202) together within the SPS 150 (e.g., VPC) have an unlimited number of cloud-based CPUs or cores 204 to perform processing. In addition, processors 202 can create new processing blocks 315 as needed. Processing cores 204 can be distributed across multiple distributed processors (e.g., processors 202) as needed for throughput and efficiency.

[0058] The processing blocks 315 are configured so that it does not matter which processing block 315a, 315b... 315n executes slowest (or fastest). Method 300 can share the processing load across the processing blocks 315, thus mitigating any processing delays caused by bottleneck issues in individual processing blocks 315. For example, individual subprocesses of a processing block 315 (see the description of FIG. 4 below) may not execute or may execute at equal rates (e.g., some faster than others). Thus, for example, the larger process of method 400 (FIG. 4) can account for variations in performance or processing time. Processing blocks 315 may then be created as many times as necessary to process incoming data.

[0059] In some embodiments, each processing block 315 may represent a collection of signal processing algorithms executed by the processor 202. As used herein, an algorithm may refer to the smallest collection of functions or method steps that perform a desired function. Several exemplary algorithms are described herein.

[0060] An exemplary advantage of method 300 is the ability to create more processing blocks 315 as needed. Generally, processing blocks 315 can be implemented in software and therefore can be created or deleted as needed to suit a given data rate or processing load. Each processing block 315 can be reconfigured to fit the needs of different received waveforms (e.g., downlink signals 132) and associated digital bitstreams 134.

[0061] In block 320, the processed signal data from the multiple processing blocks 315 may be recombined to form the original data that is encoded and modulated on the downlink signal 134. In some embodiments, the processor 202 may perform the function of a data recombiner. In other embodiments, the device 200 may have additional components for performing such functions. Each data packet or processed data block may have a timestamp. The data recombiner (e.g., the processor 202) may order the data blocks based on the timestamp and compare the phase between the ordered blocks. The recombiner may further adjust the phase of adjacent blocks reordering the data stream. In some embodiments, the phase of a subsequent data block may be adjusted to match the phase of the previous data block.

[0062] For every processing block shown in 315, there are at least four options for execution.

[0063] 1) Multiple blocks are executed, with each sub-element within processing block 315 (eg, each block 315a-315n) getting its own core (eg, cores 204a-204n).

[0064] 2) Multiple blocks are executed and the processing block 315 gets only one dedicated core for the entire block.

[0065] 3) A single block is executed, and each sub-element within the processing block gets its own core.

[0066] 4) A single block is executed and the processing block gets only one dedicated core for the entire block.

[0067] The more cores available, the higher the achievable rate.

[0068] At block 325, the device 200 may output data to an appropriate receiver. In some examples, such receivers may be one or more mission operations centers. This data may be mission dependent (e.g., satellite objectives) and may include weather data, image data, and SATCOM payload data, among others.

[0069] In a general-purpose CPU, there are at least three major factors that can limit high-speed performance: 1) data ingestion, 2) CPU capacity, and 3) memory bandwidth utilization. Data ingestion refers to how quickly data can be supplied to the CPU. CPU capacity is driven by the CPU clock speed and the number of cores in the CPU. Memory bandwidth refers to how quickly data can be transferred between the CPU and external DDR RAM (not the CPU cache). Memory bandwidth can be determined by the number of memory lanes and the DDR RAM clock speed. In some cases, the limiting factor for achieving high-speed processing is CPU capacity, while in other cases it is memory bandwidth. Care must be taken to determine which of the above cases is affecting performance, and if memory bandwidth is limited, the embodiments described below are non-limiting examples of how to reduce memory bandwidth utilization within the proposed patent approach.

[0070] Function calls within a given processing block can be configured to optimize CPU computation or memory bandwidth utilization. For example, referring to the function calls (exemplary shown as blocks) shown in FIG. 10, for the given example, various function calls (e.g., Raise to N Power block, Mixing block, and Decimation block) can be grouped to minimize memory bandwidth. These function calls can be called independently so that each function completes on one set of data before another function begins, thereby simplifying each function. In another example, multiple or all function calls can be combined into a single block, so that data is not transferred to RAM after each executed function, and the memory bandwidth of the combined functions is much smaller than if they were called independently. For independently called functions, the first function call (e.g., Raise to N Power) can be executed across the entire data set before the second function call (e.g., Mixing block) occurs. For combined functions, only a portion of the data is processed by the first function call before the second function is executed. In this way, memory bandwidth is reduced. This method can be applied to any grouping of functions, not just those shown in Figure 10. For example, this method can be applied to the timing and phase error calculations shown in Figure 11, or any other grouping for function calls performed in processing blocks as disclosed herein (e.g., the various function call blocks shown in Figures 7-16).

[0071] Another way to improve memory bandwidth utilization may be to collapse several function call blocks into a single block, similar to the approach described above. For example, in the case of a channelizer, separating one channel into N channels may require three main functions: 1) a finite impulse response (FIR) filter, 2) a circular buffer, and 3) an inverse fast Fourier transform (IFFT). In the case of a combiner, combining M channels into one c may require three main functions: 1) an IFFT, 2) a circular buffer, and 3) a finite impulse response (FIR) filter. Typically, for ease of operation and CPU optimization, each function requires its own block, as shown in Figures 15 and 16. However, to reduce memory bandwidth utilization, all functions can be combined into a single block. This tradeoff reduces memory bandwidth utilization for a hit in CPU performance. An exemplary embodiment of a diversity combiner with blind detection and Doppler compensation running on a general-purpose CPU using parallel processing on multiple cores to achieve high-throughput operation in a cloud environment

[0072] As mentioned above, FIG. 5 is a functional block diagram of one embodiment of method 500. In one example, method 500 may be referred to as diversity combiner method 500 with blind detection and Doppler compensation. Diversity combining may be used to combine multiple antenna feeds together such that the signals are aligned in time and phase and each is weighted based on signal quality to optimize information transfer across multiple channels. Signal quality may be determined using, for example, but not limited to, one or more of the following: signal-to-noise ratio, energy per symbol to noise power spectral density (Es / N0), power estimate, received signal strength indicator (RSSI), etc. The multiple antenna feeds may be from one or more remote locations, such as platform 110 or satellite 111. While satellites are used herein as an example, other wireless transmission systems, such as radio antennas (e.g., antenna 122) or other types of transmitters, may be implemented. Thus, the use of satellites is not intended to limit the present disclosure.

[0073] In the case of satellites such as those shown in FIG. 1, diversity combining can also be used during an antenna handover event, when platform 110 and satellite 111 are visible from the same ground station (e.g., ground station 122) but, for example, satellite 111 descends below the horizon (e.g., to the east) and platform 110 ascends above the horizon (e.g., to the west). To properly combine the downlink signals, several calculations must be performed. The disclosed system can digitize the signals and convert them to digital samples, which are then conveyed to signal processing elements. The system can further calculate and compensate for Doppler effects. The system can also determine the residual phase and frequency delta (e.g., difference) between the downlink signals, as well as the time difference and estimated signal-to-noise ratio of each channel. Following these operations, the signals are then combined together.

[0074] As noted above, the figure shows multiple blocks, each representing a processing block, that may be implemented as one or more of elements 306a, 306b,...306c (FIG. 4) and / or as one or more of processing blocks 315a, 315b...315n (FIG. 4). In another example, multiple blocks shown in FIG. 5 may be grouped as a single "processing block" that performs functions in a manner similar to processing blocks 315a, 315b...315n (FIG. 4) and / or elements 306a, 306b...306c (FIG. 3).

[0075] At a highest level, method 500 is illustratively shown in FIG. 5. Method 500 includes multiple processing blocks, such as one or more signal analyzer processing blocks 510a-510n (collectively referred to as signal analyzer processing blocks 510 or processing blocks 510), one or more Doppler compensator processing blocks 520a-520n (collectively referred to as Doppler compensator processing blocks 520 or processing blocks 520), and a diversity combiner processing block 530. In the illustrated example, multiple signal analyzer processing blocks 510a-510n and Doppler compensator processing blocks 520a-520n are shown for performing functions on multiple signals, with each block operating on a corresponding signal. While any number of signals is possible, the examples herein are described with reference to two signals.

[0076] An example of a signal analyzer processing block 510 is shown diagrammatically in Figure 6, an example of a Doppler compensator processing block 520 is shown diagrammatically in Figure 7, and an example of a diversity combiner processing block 530 is shown diagrammatically in Figure 8. Method 300 and / or method 400 may be used to process downlink signals 160, 170 (e.g., Figure 1) for each of processing blocks 510-530. One or more of processing blocks 510, 520, and / or 530 may be implemented as one or more of elements 306a-c of 306 of method 300 described in connection with Figure 3 or one or more of elements 315a-n of method 315 described in connection with Figure 4.

[0077] It is also possible to perform each processing block 510, 520, and 530 separately. One example is to use only diversity combiner processing block 530 when there is one transmitting satellite with two independent downlink signals, such as right- and left-hand polarized outputs, as opposed to the antenna handover case described above. In this case, timing and Doppler effects can be ignored, and therefore signal analyzer processing block 510 and Doppler compensator processing block 520 may not be necessary.

[0078] An exemplary signal analyzer processing block 510 is shown in FIG. 6 and may be used for blind detection, in which the symbol rate, modulation type (referred to herein as "mod type"), and / or center frequency may each be estimated without any input from a user. Processing block 510 may include multiple sub-elements, such as, for example, a coarse symbol rate estimator functional block 605, a timing recovery error calculator functional block 610, a Mod type and carrier estimator functional block 620, and an (Es / No estimator functional block 625. Processing block 510 may also include a timing recovery functional block 615.

[0079] An exemplary coarse symbol rate estimator function block 610 is shown diagrammatically in FIG. 9. The illustrated example of function block 610 includes multiple sub-elements or sub-function blocks 905-920. The first sub-function block 905 estimates the symbol rate using, as an example method, a Gardner arithmetic and / or a differential conjugate calculation. An example of a Gardner arithmetic is described in more detail in U.S. Pat. No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth. An example of a differential conjugate is the vector calculation y[n]=a[n]*conj(a[n+1]), where n ranges from 0 to the length of the input minus 1. In either calculation, sub-function block 905 outputs the estimated symbol rate to sub-function block 910, and an FFT of the output of sub-function block 905 is taken and the maximum peak frequency is found in sub-function block 920. The detected maximum peak frequency corresponds to the symbol rate, which can be estimated based on the detected maximum frequency. In various embodiments, the phase calculation function block 915 can also determine a coarse carrier estimate of the signal from the phase of the differential conjugate calculation y[n].

[0080] Referring again to FIG. 6, examples of timing recovery error calculation 610 and timing recovery 615 are described in U.S. Pat. No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth. For example, a Gardner timing error detector estimated in function block 605, as known in the art, can be applied to the input data to create timing information. In another embodiment, the incoming sample stream can be delayed by one sample. The undelayed data can then be multiplied by the conjugate of the delayed data (conjugate multiplication). Both have advantages and disadvantages, so it is an engineering trade-off that can be made.

[0081] An exemplary Mod type detection and carrier estimation function block 620 is shown diagrammatically in Figure 10. The illustrative example of function block 620 includes multiple sub-function blocks including, but not limited to, a Raise to N Power function block 1005, a Mix by Coarse Carrier Estimation function block 1010, a Decimate function block 1015, an FFT Trial function block 1020, and a Peak Detection function block 1025.

[0082] After timing recovery 615 in FIG. 6, the signal output from block 615 is then symbol synchronized, making mod type detection more accurate in symbol space than sample space. In sub-function block 1005, the signal input to mod type detection and carrier estimation function block 620 is boosted to the appropriate power based on the number of symbols (N) in the outer ring of the constellation (2 for BPSK, 4 for QPSK / OQPSK, 8 for 8PSK, 12 for 16APSK, etc.), and then mixed in sub-function block 1010 with the coarse carrier frequency provided by the differential conjugate calculation (if provided). The mixed signal is then decimated in sub-function block 1015, and then an FFT is performed on the signal in sub-function block 1020, and the peak-to-average ratio of the selected modulation type is determined in sub-function block 1025. This process is then repeated for all of the desired modulation types to be detected. The result with the highest peak-to-average value is the most likely modulation type. As a way to minimize memory bandwidth, sub-function block 1005, sub-function block 1010, and sub-function block 1015 can be combined to form one sub-function block, thereby reducing memory bandwidth. To further increase the data rate, sub-function block 1020 can run each modulation type attempt on its own thread, further increasing throughput.

[0083] The next processing block in method 500 is a Doppler compensation processing block 520, an example of which is shown diagrammatically in FIG. 7. Processing block 520 may include multiple function blocks, including, but not limited to, a phase precalculator function block 705 and a continuous phase adjustment function block 710. Phase corrections are precalculated in function block 705 based on the carrier estimate from signal analyzer processing block 510. Doppler compensator processing block 520, in various embodiments, smooths the compensation so that a PLL-based receiver can track the compensated signal. This precalculated phase information from function block 705 is then provided to the continuous phase adjustment function block 710, which removes most of the measured Doppler.

[0084] 6, the Es / No estimator function block 625 measures Es / No. There are several approaches to measuring Es / No that can be used depending on the modulation type. One illustrative example for measuring Es / No is to calculate (C / N)×(B / fs), where C / N is one of the carrier-to-noise ratio or signal-to-noise ratio, B is the channel bandwidth in Hertz, and fs is the symbol rate or symbols per second. However, it will be understood that any approach for measuring Es / No is equally applicable to the embodiments disclosed herein.

[0085] 8 diagrammatically illustrates an example of a diversity combiner processing block 530. Processing block 530 can be used as a standalone application when the timing and Doppler differences between multiple signals (e.g., two in this example) are small and the modulation type is known in advance. In various embodiments, processing block 530 can also be used in methods 300 and / or 400. The processing block includes multiple function blocks, such as, but not limited to, a coarse timing estimator function block 805, a timing and phase error calculation function block 810, one or more timing adjustment function blocks 815a-815n (collectively referred to as timing adjustment 815), one or more phase adjustment function blocks 820a-820n (collectively referred to as phase adjustment 820), and a weighting combiner function block 825. In the illustrated example, multiple timing adjustment function blocks 815a-815n and phase adjustment function blocks 820a-820n are shown for performing functions on multiple signals. Although any number of signals are possible, the examples described herein are described with reference to two signals.

[0086] The coarse timing estimator function block 805 may be used when the time delta between two arriving signals is not negligible. This may be required in the case of antenna handover. The estimator function block 805 looks for correlation spikes between multiple signals (e.g., two in this example) to determine the time difference. The estimator function block 805 may utilize FFT and / or IFFT to perform the correlation quickly, although any correlation technique may be utilized. When many correlations are required, methods 300 and 400 may be applied to increase throughput.

[0087] An example of a timing and phase error calculation function block 810 is shown diagrammatically in FIG. 11. An illustrative example of the timing and phase error calculation function block 810 includes multiple sub-elements or sub-function blocks, such as, but not limited to, a cross-calculator sub-function block 1105, a decimate sub-function block 1110, a timing estimate update sub-function block 1115, a phase delta generation sub-function block 1120, and a phase unwrap sub-function block 1125. The cross-correlator sub-function block 1105 may calculate early, immediate, and late (EPL) terms between multiple input signals (e.g., two in this example) used in a delay-locked loop (DLL). However, SIMD techniques can be used to efficiently calculate the EPL terms. Once the EPL terms are calculated, the signals are decimated in sub-function block 1110. The delta between the early and late terms may be used for the timing update sub-function block 1115 on the cross-correlator sub-function block 1105, as well as a feed-forward error term for subsequent timing adjustments.

[0088] The phase of the immediate term is then calculated in the phase delta generation sub-function block 1120 and provided to the phase unwrap sub-function block 1125. In one example, the phase unwrap sub-function block 1125 can use a phase-locked loop (PLL) in various embodiments. The phase unwrap function block 1125 includes a phase calculation of the decimated signal that is performed before the phase unwrap function block 1125. The phase unwrap calculation can provide continuous phase information for the data samples. The phase unwrap calculation stitches the phase together when the phase wraps from either π (pi) to -π radians or from -π to π radians. This angle unwrapping allows a curve fitting function to be performed on the phase signal without any discontinuities. This allows the processor 202 to reassemble the demodulated signal based on the timing and phase of the processed signal. It may be possible to replace the phase unwrap calculation with a Kalman filter to obtain phase, frequency, and Doppler rate information, or to use a PLL.

[0089] Referring again to FIG. 8 , this phase information from function block 810 is then provided to one or more timing adjustment block function blocks 815 and phase adjustment block function blocks 820 to adjust the phase of the signals to properly align them for later combining. Examples of timing adjustment and phase adjustment subelements are described in U.S. Pat. No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth. For example, each timing adjustment subelement function block 815 can apply the timing phase information calculated by the timing and phase error calculation function block 810. Function block 815 can then use a filter, such as, for example, but not limited to, a polyphase FIR filter, in which the appropriate bank of filters is selected based on the provided phase information, as known in the art. The timing can then be adjusted by function block 815 so that the timing adjustment is efficient in both CPU and bandwidth usage. The filters used in function block 815 can use SIMD techniques to further increase throughput. Linear, cubic, parabolic, or other interpolation types can also be used. Each function block 815 performs the above-described adjustment on a corresponding one of the signals (eg, two in the illustrated example).

[0090] Each of the phase adjustment function blocks 820 can apply the carrier phase information calculated by the timing and phase error calculation function block 810. The function blocks 820 can apply the phase information and use SIMD techniques to adjust the phase of the entire data block so that the multiple signals are properly aligned for combining. Each function block 820 performs the above adjustment on a corresponding one of the multiple signals (e.g., two in the illustrated example).

[0091] Once the signals are time and phase aligned, the weighting combiner function block 825 may apply scaling based on the Es / No estimates and power estimates calculated in the signal analyzer processing block 510. For example, a signal having a better signal-to-noise ratio compared to another signal may be assigned a higher weight than the other signal and scaled accordingly. Similarly, a higher Es / No estimate and / or power estimate may be assigned a larger weight and scaled accordingly. SIMD techniques can be used to efficiently scale and combine multiple signals (e.g., two signals in this example). Exemplary Embodiment of a Digital Signal Channelizer and Combiner on a General Purpose CPU Using Parallel Processing on Multiple Cores to Achieve High Throughput Operation in a Cloud Environment

[0092] 12-16 schematically illustrate various embodiments of methods for digital signal channelization and combining according to embodiments disclosed herein. In various embodiments, the channelization and combining illustrated in FIGS. 12-16 may be implemented to manage the spectral bandwidth of one or more downlink signals. In some implementations, the methods illustrated in FIGS. 12-14A for digital signal channelization and / or combining may be performed using method 300 of FIG. 3 and / or method 400 of FIG. 4. The channelizer may be configured to execute a DSP algorithm capable of separating the spectral bandwidth from one channel to many channels (1-to-N), as shown in FIG. 12. In another example, the combiner may be configured to execute a DSP algorithm in which the spectral bandwidth is combined from many channels to one channel (M-to-1), as shown in FIG. 13. In some implementations, processing begins with network equipment (e.g., one or more digitizers as described in connection with FIG. 1) that digitizes the analog signal, and the samples are then conveyed to a channelizer (the 1-to-N approach shown in FIG. 12), or the samples from the combiner are fed to network equipment, which converts them to an analog signal (the M-to-1 approach shown in FIG. 13).

[0093] In the case of a satellite such as that shown in FIG. 1 , a digital signal channelizer and combiner according to embodiments herein can be used for bandwidth compression, where a digitizer (e.g., one of digitizers 124, 134, and / or 144 in FIG. 1 ) digitizes a downlink signal (e.g., one of downlink signals 160 and / or 170) having a wide bandwidth, but not all of the bandwidth is useful for processing. In one example, a downlink signal having a 500 MHz bandwidth can be digitized, but only a subset of slices of the bandwidth (e.g., two slices) actually contain useful data. In this case, the channelizer creates a channel from the 500 MHz bandwidth spectrum at 512, and then a combiner combines the two channels together, where one channel may be, for example, 50 MHz and the other channel may be 100 MHz. These two smaller channels (50 MHz and 100 MHz) are, in any case, transmitted to processing server 150 for appropriate processing. In this example, only the sum of a subset of smaller channels (150 MHz) needs to be transmitted to the data center instead of the entire 500 MHz. This can save on the transport costs of transmitting data from the antenna to the data center. In this case, the digitized bandwidth is compressed, and the network bandwidth transmitted over the LAN or WAN is also reduced. Although a satellite is used as an example herein, other wireless transmission systems, such as a radio antenna (e.g., antenna 122) or other types of transmitters, can be implemented. Thus, the use of a satellite is not intended to limit the present disclosure.

[0094] In another example, digital signal channelizers and combiners according to embodiments herein can be used for channel splitting where many entire digitized bandwidths contain many independent carriers. The channelizer associated with a combiner according to embodiments herein then creates the appropriate channels to be processed by a receiver such as the receiver described in Patent No. 10,790,920, the disclosure of which is incorporated herein by reference as if fully set forth.

[0095] In another example, digital signal channelizers and combiners according to embodiments herein can be used for channel combining, where several downlink signals received from different types of sources, either other antennas or modulators, can be combined to create a larger composite bandwidth that can be digitally transmitted to an antenna for broadcast to a satellite.

[0096] 12 shows an example channelizer processing block 1200 for separating one channel into N channels. The illustrated example channelizer processing block 1200 includes multiple functional blocks, such as, but not limited to, an N-path filter functional block 1210, an N-point circular buffer functional block 1220, and an N-point IFFT functional block 1230. The channelizer processing block 1200 may be configured to capture digitized samples having a first bandwidth from a network device (e.g., a digitizer as described in connection with FIG. 1) via a given network protocol, such as, but not limited to, TCP / IP or UDP. The sample stream is then processed in the N-path filter functional block 1210 using a polyphase filter bank, then the N-point circular buffer functional block 1220, and then the N-point IFFT functional block 1230 to split the signal into N channels, each having a corresponding bandwidth smaller than the first bandwidth of the captured digitized samples.

[0097] Exemplary sources for input shown in FIG. 12 include, but are not limited to, a modulator, a digitizer (e.g., one of digitizers 124, 134, and / or 144 of FIG. 1), the output of a diversity combiner (e.g., such as those described above in connection with FIGS. 5-11), the output of a Doppler compensator (e.g., such as those described above in connection with FIGS. 5-11), and a digital sample file player.

[0098] 12, 14A, and 14B, the input feed to 1210 may represent an input signal interpolated by two (as indicated by the division of the input signal into two arrows), as is known in the art. This allows channelizer 1200 to avoid aliasing in the outputs, since all N outputs are interpolated by two from the start of processing.

[0099] 13 shows an exemplary combiner processing block 1300 for combining M channels into one channel. The illustrated exemplary combiner processing block 1300 includes multiple functional blocks, such as, but not limited to, an M-path filter and summer functional block 1310, an M-point circular buffer functional block 1320, and an M-point IFFT functional block 1330. In the M-to-1 processing block 1300, the process is reversed compared to the channelizer processing block 1200 of FIG. 12. For example, M channels are supplied to the M-point IFFT functional block 1330, then the M-point circular buffer functional block 1320, and then the M-point filter functional block 1310 using a polyphase filter bank. The filtered channels are then combined using the summer of the functional block 1310.

[0100] Exemplary sources for the inputs shown in FIG. 13 include, but are not limited to, a modulator, a digitizer (e.g., one of digitizers 124, 134, and / or 144 of FIG. 1), a diversity combiner output (e.g., such as those described above in connection with FIGS. 5-11), a Doppler compensator output (e.g., such as those described above in connection with FIGS. 5-11), a channelizer (e.g., such as those described in connection with FIG. 12), and a digital sample file player. As discussed above in connection with FIG. 12 and illustrated in FIGS. 14A and 14B, each input providing to 1200a-1200n, respectively, can represent an input signal interpolated by two (as indicated by the division of the input signal into two arrows), as known in the art. This allows each channelizer 1200a-1200n to avoid aliasing in its output, since all N outputs are interpolated by two from the start of processing.

[0101] In some embodiments, it is possible to use one or more channelizers and one or more combiners in combination to achieve any desired bandwidth from one or more channelizers such as those shown in Figures 14A and 14B. For example, as shown in Figure 14A, a digitized downlink signal may be split into N channels (e.g., 512 channels in this example) using one or more channelizers, e.g., channelizer processing blocks 1200a-1200n. Each of the N channels may have a smaller bandwidth than the digitized downlink signal. In some embodiments, each channelizer processing block 1200a-1200n may receive a discrete downlink signal such that each input a-n is not necessarily part of the same downlink signal. Thus, each input may be independent of the other inputs.

[0102] Once the input signals are split into N channels each, M of those channels (e.g., 20 in this example) can be recombined to form larger channels using a combiner, e.g., combiner processing block 1300 (e.g., only a single combiner 1300 as shown in FIG. 14A).

[0103] In some embodiments, multiple combiner processing blocks 1300a-1300n may be utilized, as shown in Figure 14B. As shown in Figure 14B, the digitized downlink signal may be split into N channels (e.g., 512 channels in this example) using a channelizer, e.g., channelizer processing block 1200. Once the input signal is split into each of the N channels, M of those channels (e.g., 20 in this example) may be recombined to form a larger channel using a combiner, e.g., multiple combiner processing blocks 1300a-1300n. Each combiner processing block 1300a-n may take the N channels and combine the M channels to form a larger combined channel that is output from each processing block 1300 as output a-output n.

[0104] The channels selected for recombining may include channels on which useful data is transmitted. Which data is useful may depend on the system processing the downlink. This method can be used to divide the digitized signal into N channels of smaller bandwidth and then aggregate any of the N channels into a wider channel of any size M, thereby compressing the bandwidth and reducing the network resources required to process and transmit the downlink signal. Thus, while the illustrative example describes 512 elements being channelized by a given channelizer 1200 and 20 elements being combined by a given combiner 1300 in the above example, it will be understood that any number of elements can be channelized by one or more channelizers, and any number of elements can be combined using a combiner, as needed. This allows the channelizer channel bandwidth to be fully programmable, allowing for any number of channels.

[0105] Although two input channels are shown in FIG. 14A, any number of input channels can be implemented as desired, e.g., one, two, or more input channels, fifty or more input channels, or one hundred or more input channels. If one input channel is used, FIG. 14 may utilize a single channelizer processing block. Similarly, FIG. 14B shows two output channels, but any number of combiner processing blocks can be implemented as desired, e.g., one, two, or more output channels. If one output channel is used, FIG. 14A may utilize a single combiner processing block. Thus, in some embodiments, multiple combiners (e.g., combiner processing blocks 1300a-n) can be placed after one or more channelizer processing blocks to output many channels of M / N scaled bandwidth. Additionally, gain stages (not shown) can be added after the channelizers and combiners to achieve either manual or automatic gain control of each channel.

[0106] Exemplary sources for each input shown in FIGS. 14A and 14B include, but are not limited to, a modulator, a digitizer (e.g., one of digitizers 124, 134, and / or 144 of FIG. 1), the output of a diversity combiner (e.g., such as those described above in connection with FIGS. 5-11), the output of a Doppler compensator (e.g., such as those described above in connection with FIGS. 5-11), and a digital sample file player. In some examples, channelizers and combiners may be cascaded together. For example, a first channelizer / combiner may feed another channelizer / combiner. In this case, the first channelizer / combiner may be configured to process any number of inputs at a low sample rate and output the combined signal to another channelizer / combiner that may output at a higher rate. For example, 100 modulators, each operating at 10 kSPS, may be combined into one channel operating at 1 MSPS. This 1 MSPS channel may then be fed into another channelizer / combiner with a final output sample rate of 512 MSPS. In some embodiments, each channelizer / combiner may be performed by a separate processing block, such as one or more of blocks 315a, 315b, ... 315n of Figure 4 and / or one or more of blocks 306a, 306b, ... 306n of Figure 3. That is, for example, a first channelizer / combiner may be performed in a first one or more processing blocks, and a second channelizer / combiner may be performed in a second one or more processing blocks.

[0107] In some embodiments, methods 1400a and 1400b may include an optional combiner input control 1410 (shown in FIG. 14A but not shown in FIG. 14B) configured to time-align inputs received from one or more channelizer processing blocks 1200. For example, because one possible exemplary implementation of the channelizer / combiner shown in FIG. 14 is to replace an existing analog radio frequency (RF) switch matrix, it may be desirable to maintain and match the current capabilities of the RF switch matrix. One such capability is time alignment. Because RF switch matrices are near-zero-delay combining or dividing of signals, time alignment is trivial in the analog domain. However, once signals are digitized and transmitted to a network, such as a cloud environment carried over a LAN or WAN, time alignment may no longer be trivial. A timestamp may be applied to each input channel and maintained throughout all processing within one or more channelizer processing blocks 1200. The combiner input control 1410 can then collect and buffer data for a short, programmable (e.g., preset) duration to allow the inputs to arrive within the duration. If all inputs arrive in time, they can be carefully time-aligned by the combiner input control 1410 based on each channel's corresponding input rate and timestamp. However, if a channel does not arrive on time, the combiner input control 1410 can replace that channel with an all-zero data source, so that the timely channel is not further blocked or delayed. In this way, the channelizer / combiner of FIG. 14A can replicate the near-zero delay combinations present in the RF switch matrix. Similarly, the combiner input control 1410 can be included in the method 1400b between the channelizer 1200 and multiple combiners 1300a-1300n and can be configured similarly to those described herein.

[0108] In some embodiments, methods 1400a and 1400b may also include a data splitting function that splits data of a given downlink signal into parallel data streams by a data splitter. Each of the channelizers of FIG. 12, the combiners of FIG. 13, and / or the combined channelizers / combiners of FIG. 14A and FIG. 14B may be preceded by a data splitting function such as block 310 of FIG. 4. For example, each channelizer 1200 and / or each combiner 1300 shown in FIG. 14A and FIG. 14B may be an example of one or more processing blocks 315 of FIG. 4, where block 310 may split data into parallel data streams as described in connection with FIG. 4. Block 310 may be referred to in some embodiments as a manager (or dealer) processing block. Splitting the data into multiple parallel streams may allow multiple channelizer portions 1200a-n to function in parallel threads to channelize the downlink signal, multiple combiner portions 1300a-n to function in parallel threads to combine the downlink signal, and / or one or more channelizers 1200 to both function in parallel with one or more combiners 1300. For example, for the channelizer processing block 1200 of FIG. 14A, each channelizer processing block 1200 may be implemented as one or more blocks 315a-n of FIG. 4. For the combiner processing block 1300 of FIG. 14B, each combiner 1300 may be implemented as one or more of blocks 315a-n of FIG. 4. In both cases, block 310 may split the data from the downlink signal into parallel data streams, each overlapping with adjacent data streams (e.g., as described above in connection with FIG. 4). Each parallel data stream can then be sent to one of processing blocks 315a-n for processing. Once each processing block 315a-n has completed processing its portion of the data, the processed portion of the data is sent to, for example, block 320 of Figure 4, which outputs the processed data. Block 320 then waits for the next processing block (e.g., the second block 315b) to complete its processing, and so on, before outputting each portion of the processed data.This process is sometimes called a round-robin processing scheme.

[0109] The higher the throughput desired for a given application, the more processing blocks 315 are required. For example, referring to FIG. 14B, if 512 MSPS is required as the output of a given combiner processing block 1300, it may be possible to create up to “n” processing blocks 315, each implemented as a combiner processing block 1300 (e.g., one of combiner processing blocks 1300a-n), to transmit outputs a-n. In this case, a first portion of input data is transmitted from or processed by block 310 to a first processing block 315a (e.g., implemented as the first combiner processing block 1300a) to be processed. A small portion of the processed data from block 315a may be saved and prepended by block 310 as duplicate data on the next portion of the data stream. This next portion of the data stream, including the duplicate data, is then transmitted to a second processing block 315b (e.g., implemented as the second combiner processing block 1300a). This pattern is repeated for as many processing blocks as needed to achieve the required high throughput. As each processing block (e.g., blocks 315a-n) finishes processing its portion of the data, the processed portion of the data is sent, for example, to block 320, which outputs the combined, processed data. Block 320 then waits for the next processing block (e.g., second block 315b) to complete its processing, and so on, before outputting the block of data. In some embodiments, block 310 can receive the output from channelizer 1200 and split the output as described above to feed multiple combiners 1300a-n. In another embodiment, block 310 may precede channelizer 1200 to split the downlink signal. Processing blocks 315a-n are used in this round-robin processing scheme, with block 310, as the manager or dealer, cycling through all processing blocks.

[0110] While the above example is described in connection with one or more combiners 1300, it will be understood that the above-described round-robin processing scheme for splitting and processing portions of data among processing blocks may be utilized in any of the embodiments described herein. For example, the round-robin processing scheme may also be used for the channelizer processing blocks 1200a-n of FIG. 14a to achieve high throughput. That is, each channelizer processing block 1200 may be implemented as a processing block 315a-n, with the data splitter block 310 splitting the data into parallel streams and processing each parallel portion as a channelizer in a given processing block 315a-n. Each channelizer 1200a-n may process its portion and, upon completion, output a respective plurality of N channels from each channelizer 1200a-n to block 320. Block 320 outputs the processed portion of data as described above and waits for the next processing block 315 to complete its processing. Similarly, this round-robin processing scheme may be utilized in conjunction with the diversity combiner with blind detection and Doppler compensation methods of Figures 5-11. That is, any one of processing blocks 510-530 may be implemented as one or more processing blocks 315a-n, and the data splitter function in block 310 may split the input downlink signal into parallel data streams and provide them to each processing block 315a-n in the manner described above. The resulting processed data for each processing block 315 may then be sent to block 320 for output as described above.

[0111] In some implementations, digital channelizer and / or combiner processing blocks (e.g., 1200, 1300, and / or 1400 described above) enabled by SPS 150 (e.g., using a general-purpose CPU and using SIMD techniques, including, but not limited to, the SSE, SSE2, SSE3, SSE4.1, SSE4.2, AVX, AVX2, and AVX512 instruction sets) can process data distributed across several cores of the CPU to improve throughput. Data processing can be managed through multiple cores of the processor (e.g., block 315) to achieve the required throughput without the use of dedicated signal processing hardware, such as an FPGA, or high-performance computing (HPC) hardware, such as a graphics processing unit (GPU). An example of a representative block 315 implemented as a channelizer is shown in FIG. 15. The ability to run this processing on general-purpose server CPUs allows functions to be deployed within general-purpose cloud processing environments using virtualized processing architectures without the need for specialized hardware such as, but not limited to, x86 architecture, Cortex-A76, NEON and AWS Graviton, Graviton2.

[0112] 15 and 16 diagrammatically illustrate exemplary processing blocks implemented as a channelizer processing block 1500 or a combiner processing block 1600, respectively. The channelizer processing block 1500 may be substantially similar to the channelizer processing block 1200 described in connection with FIG. 12. For example, the channelizer processing block 1500 may separate one channel into N channels using, for example, an N-path filter functional block 1510, an N-point circular buffer functional block 1520, and an N-point IFFT functional block 1530. The channelizer processing block 1500 is an illustrative example of a channelizer implemented as one of the processing blocks 315a-315n (e.g., FIG. 4) and / or one of the functions 306a-306n (e.g., FIG. 3). The multiple channelizer processing blocks 1500 may each be provided as one of the processing blocks 315a-315n (e.g., FIG. 4) and / or one of the functions 306a-306n (e.g., FIG. 3). In another embodiment, the functionality for performing a single channelizer processing block 1500 may be distributed among the multiple processing blocks 315a-315n (e.g., FIG. 4) and / or one of the functions 306a-306n (e.g., FIG. 3). In some embodiments, the round-robin processing scheme described above in connection with FIGS. 12-14B may be implemented using multiple processing blocks 1500. For example, the multiple processing blocks 1500 may be implemented as processing blocks 315a-n. Thus, the multiple processing blocks 1500 may be operable in parallel using the round-robin processing scheme described above.

[0113] Similarly, combiner processing block 1600 may be substantially similar to combiner processing block 1300 described in connection with FIG. 13 . For example, combiner processing block 1600 may combine M channels into one channel using, for example, an M-path filter and summer functional block 1610, an M-point circular buffer functional block 1620, and an M-point IFFT functional block 1630. Combiner processing block 1600 is an illustrative example of a combiner implemented as one of processing blocks 315 a-315 n (e.g., FIG. 4 ) and / or one of functions 306 a-306 n (e.g., FIG. 3 ). Multiple combiner processing blocks 1600 may each be provided as one of processing blocks 315 a-315 n (e.g., FIG. 4 ) and / or one of functions 306 a-306 n (e.g., FIG. 3 ). In another embodiment, the functionality for performing the single combiner processing block 1600 may be distributed among multiple processing blocks 315a-315n (e.g., FIG. 4) and / or one of functions 306a-306n (e.g., FIG. 3). In some embodiments, the round-robin processing scheme described above in connection with FIGS. 12-14B may be implemented using multiple processing blocks 1600. For example, multiple processing blocks 1600 may be implemented as processing blocks 315a-n. Thus, multiple processing blocks 1600 may be capable of operating in parallel using the round-robin processing scheme described above.

[0114] The channelizer and / or combiner described herein are examples of the memory bandwidth optimization mentioned above. The channelizer functions can be separated into separate blocks, as shown in Figures 15 and 16, or combined into one functional subelement or block where a small portion of data is processed. In this illustrative example, the small portion may refer to data equivalent to one IFFT. If the function is separated for the channelizer, many filter calculations may be performed, then many circular buffers, and then many IFFTs may be performed. Similarly, if the function is separated for the combiner, many IFFTs may be performed, then many circular buffers, and then many filter calculations may be performed.

[0115] An exemplary, non-limiting advantage of using a general-purpose CPU is the dynamic nature of resource allocation. For example, in the case of a channelizer / combiner such as that described in connection with FIGS. 14A and 14B, it may be desirable to reconfigure the system in real time, where input channels can come and go at any time. As shown in FIG. 14A, the processing blocks for channelizers 1200a-n allow each of these channelizers 1200a-n to be created and destroyed to achieve this goal. Any value of N can be used to accommodate the input bandwidth, and any number of channelizers 1200n can be instantiated to process the appropriate amount of input channels. Thus, as an illustrative example, at one moment, 10 channels of 15 MHz each can be combined, and then one second later, 5 channels of 45 MHz can be combined. Due to all the techniques described in this disclosure, such as multi-core, SIMD techniques, and memory bandwidth optimization approaches, the distribution of data processing at high throughput is possible. Although the examples provided herein are described with reference to a channelizer / combiner such as that shown in FIG. 14A, the beneficial results are equally achievable by using the techniques described herein with respect to a diversity combiner and Doppler compensation, e.g., as described with reference to FIGS. 5-11 and 14B. For example, any number of values ​​for processing block 510, processing block 520, and / or processing block 530 of FIG. 5 may be used to achieve a desired throughput. The number of each processing block 510-530 of FIG. 5 may be dynamically created and discarded in a manner similar to that described above to achieve a desired throughput. Other Aspects

[0116] The accompanying claims and their equivalents are intended to cover such forms or modifications as fall within the scope of the present disclosure. The various components shown in the figures may be implemented, for example, but not limited to, as software and / or firmware on a processor, or dedicated hardware. Also, the features and attributes of specific exemplary embodiments disclosed above can be combined in different ways to form additional embodiments, all of which fall within the scope of the present disclosure.

[0117] The foregoing method descriptions and process flow diagrams are provided merely as illustrative examples and are not intended to require or imply that the operations of the various embodiments must be performed in the order presented. As will be understood by one of ordinary skill in the art, the order of operations in the above embodiments can be performed in any order. Words such as "then," "then," and "next" are not intended to limit the order of operations; these words are merely used to guide the reader through the method descriptions. Additionally, any reference to claim elements in the singular, for example, using the articles "a," "an," or "the," shall not be construed as limiting the element to the singular.

[0118] The various illustrative logical blocks, modules, and algorithmic operations described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the inventive concept.

[0119] The hardware used to implement the various exemplary logic, logic blocks, and modules described in connection with the various embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of receiver devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0120] In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable or processor-readable storage medium. The operations of a method or algorithm disclosed herein may be implemented in processor-executable instructions, which may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that can be accessed by a computer or processor. By way of example and not limitation, such a non-transitory computer-readable or processor-readable storage medium may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disks and discs include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically and discs reproduce data optically with a laser. Combinations of the above are also included within the scope of non-transitory computer-readable media and processor-readable media. Furthermore, the operations of a method or algorithm may reside as one or any combination or set of code and / or instructions on a non-transitory processor-readable and / or computer-readable storage medium, which may be incorporated into a computer program product.

[0121] It is understood that the specific order or hierarchy of blocks in the disclosed processes / flowcharts is illustrative of example approaches. Based on design preferences, it is understood that the specific order or hierarchy of blocks within the processes / flowcharts can be rearranged. Also, some blocks may be combined or omitted. The accompanying method claims present elements of the various blocks in a sample order and are not meant to be limited to the specific order or hierarchy presented.

[0122] The previous description is provided to enable one skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects.

[0123] Accordingly, the claims are not intended to be limited to the aspects set forth herein but are to be accorded full scope consistent with the claims language, and references to elements in the singular do not mean "one and only one" unless so expressly stated, but rather "one or more."

[0124] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects. Unless otherwise specified, the term "some" refers to one or more.

Claims

1. 1. A method for managing channel bandwidth of one or more downlink signals, comprising: receiving the one or more downlink signals from one or more antenna feeds, the one or more downlink signals having a first bandwidth; In a first one or more processing blocks within the one or more processors, performing a first channelizer operation on a first portion of the one or more downlink signals to create a first plurality of channels, each of the first plurality of channels having a bandwidth smaller than the first bandwidth; in a second one or more processing blocks within the one or more processors in parallel with the first one or more processing blocks; performing a second channelizer operation on a second portion of the one or more downlink signals to create a second plurality of channels, each of the second plurality of channels having a bandwidth smaller than the first bandwidth; in a third one or more processing blocks within the one or more processors; performing a combiner operation to combine a subset of the first plurality of channels and a subset of the second plurality of channels into a combined channel, the combined channel having a second bandwidth that is smaller than the first bandwidth; outputting the combined channel to a network; A method comprising:

2. 2. The method of claim 1, wherein the first one or more processing blocks include first one or more central processing unit (CPU) cores and the second one or more processing blocks include second one or more CPU cores.

3. 3. The method of claim 1, wherein the one or more processors comprise a plurality of processors, the first one or more processing blocks being included in a first processor of the plurality, and the second one or more processing blocks being included in a second processor of the plurality of processors.

4. The method of claim 1 or 2, wherein the one or more processors include a single processor that includes the first one or more processing blocks and the second one or more processing blocks.

5. 5. The method of claim 1, wherein at least one of the third one or more processing blocks is included as part of one or more of (i) the one or more first processing blocks, and (ii) the one or more second processing blocks.

6. The method of any one of claims 1 to 4, wherein the third one or more processing blocks are separate from the first one or more processing blocks and the second one or more processing blocks.

7. The first channelizer operation includes a first plurality of functions, the first plurality of functions comprising: capturing samples from an input channel, the samples being received as first data packets included in the first portion of the one or more downlink signals; applying a multi-pass filter to the samples; performing a multipoint circular buffer on the filtered samples; Separating the samples into a plurality of channels based on applying a multipoint inverse fast Fourier transform to the samples; The method according to any one of claims 1 to 6, comprising:

8. 8. The method of claim 7, wherein the first one or more processing blocks include a first plurality of processing blocks, and wherein performing the first channelizer operation includes distributing the first plurality of functions among the first plurality of processing blocks and performing the distributed first plurality of functions in parallel.

9. The second channelizer operation includes a second plurality of functions, the second plurality of functions comprising: capturing samples from an input channel, the samples being received as second data packets included in the second portion of the one or more downlink signals; applying a multi-pass filter to the samples; performing a multipoint circular buffer on the filtered samples; Separating the samples into a plurality of channels based on applying a multipoint inverse fast Fourier transform to the samples; The method of claim 6, comprising:

10. 10. The method of claim 9, wherein the second one or more processing blocks include a second plurality of processing blocks, and wherein performing the second channelizer operation includes distributing the second plurality of functions among the second plurality of processing blocks and performing the distributed second plurality of functions in parallel.

11. 9. The method of claim 8, wherein one or more of the second plurality of functions are performed in the second one or more processing blocks in parallel with one or more of the first plurality of functions being performed in the first one or more processing blocks.

12. 10. The method of claim 1, wherein the combiner operation comprises combining spectral bandwidths from a plurality of input channels into the combined channel, the plurality of input channels comprising the subset of the first plurality of channels and the subset of the second plurality of channels.

13. The combiner operation includes a third plurality of functions, the third plurality of functions comprising: capturing samples from the subset of the first plurality of channels and the subset of the second plurality of channels as a plurality of input channels, the samples being received as data packets contained in the subset of the first plurality of channels and the subset of the second plurality of channels; applying a multipoint inverse fast Fourier transform to the samples of each of the plurality of channels; performing a multi-point circular buffer for each of the plurality of channels based on the application of a multi-point inverse fast Fourier transform to the samples; combining the samples into the combined channel based on applying a multi-pass filter and an adder; The method according to any one of claims 1 to 10, comprising:

14. 14. The method of claim 13, wherein the third one or more processing blocks include a third plurality of processing blocks, and wherein performing the combiner operation includes distributing the third plurality of functions among the third plurality of processing blocks and performing the distributed third plurality of functions in parallel.

15. 12. The method of claim 11 , wherein the third one or more processing blocks include a third plurality of processing blocks, and wherein at least two of the third plurality of functions are performed in parallel by the separate processing blocks of the third plurality of processing blocks.

16. 14. The method of claim 13, further comprising: performing a second combiner operation on another subset of the first plurality of channels and another said subset of the second plurality of channels in a fourth one or more processing blocks in the one or more processors in parallel with the third one or more processing blocks.

17. 10. The method of claim 1, further comprising: in one or more processors, dividing the digital bitstream into a plurality of data packets, each of the data packets of the plurality of data packets including overlapping data from adjacent packets.

18. The method of claim 11 , wherein the adjacent packets overlap in time by 1% of the length of the packets.

19. The method of claim 11 , wherein the plurality of data packets have different lengths.

20. The method of any preceding claim, wherein the one or more processors are one or more general purpose central processing units (CPUs).

21. The method of any preceding claim, wherein the one or more processors use Single Instruction Multiple Data (SIMD) techniques to achieve high throughput.

22. 1. A method for managing channel bandwidth of one or more downlink signals, comprising: receiving the one or more downlink signals from one or more antenna feeds, the one or more downlink signals having a first bandwidth; In a first one or more processing blocks within the one or more processors, performing a first channelizer operation on a first portion of the one or more downlink signals to create a first plurality of channels, each of the first plurality of channels having a bandwidth smaller than the first bandwidth; in a second one or more processing blocks within the one or more processors in parallel with the first one or more processing blocks; performing a second channelizer operation on a second portion of the one or more downlink signals to create a second plurality of channels, each of the second plurality of channels having a bandwidth smaller than the first bandwidth; outputting the first and second plurality of channels to a network; A method comprising:

23. 23. The method of claim 22, wherein the first one or more processing blocks include first one or more central processing unit (CPU) cores and the second one or more processing blocks include second one or more CPU cores.

24. 24. The method of claim 22 or 23, wherein the one or more processors comprise a plurality of processors, the first one or more processing blocks being included in a first processor of the plurality, and the second one or more processing blocks being included in a second processor of the plurality of processors.

25. 24. The method of claim 22 or 23, wherein the one or more processors include a single processor that includes the first one or more processing blocks and the second one or more processing blocks.

26. The first channelizer operation includes a first plurality of functions, the first plurality of functions comprising: capturing samples from an input channel, the samples being received as first data packets included in the first portion of the one or more downlink signals; applying a multi-pass filter to the samples; performing a multipoint circular buffer on the filtered samples; Separating the samples into a plurality of channels based on applying a multipoint inverse fast Fourier transform to the samples; The method according to any one of claims 22 to 5, comprising:

27. 27. The method of claim 26, wherein the first one or more processing blocks include a first plurality of processing blocks, and wherein performing the first channelizer operation includes distributing the first plurality of functions among the first plurality of processing blocks and performing the distributed first plurality of functions in parallel.

28. The second channelizer operation includes a second plurality of functions, the second plurality of functions comprising: capturing samples from an input channel, the samples being received as second data packets included in the second portion of the one or more downlink signals; applying a multi-pass filter to the samples; performing a multipoint circular buffer on the filtered samples; Separating the samples into a plurality of channels based on applying a multipoint inverse fast Fourier transform to the samples; 27. The method of claim 26, comprising:

29. 29. The method of claim 28, wherein the second one or more processing blocks include a second plurality of processing blocks, and wherein performing the second channelizer operation includes distributing the second plurality of functions among the second plurality of processing blocks and performing the distributed second plurality of functions in parallel.

30. 30. The method of claim 29, wherein one or more of the second plurality of functions is performed in the second one or more processing blocks in parallel with one or more of the first plurality of functions being performed in the first one or more processing blocks.

31. 31. The method of claim 22, further comprising: in one or more processors, dividing the digital bitstream into a plurality of data packets, each of the data packets of the plurality of data packets including overlapping data from adjacent packets.

32. 32. The method of claim 31 , wherein the adjacent packets overlap in time by 1% of the length of the packets.

33. 33. The method of claim 31 or 32, wherein the plurality of data packets have different lengths.

34. The method of any one of claims 22 to 32, wherein the one or more processors are one or more general purpose central processing units (CPUs).

35. The method of any one of claims 22 to 33, wherein the one or more processors use single instruction multiple data (SIMD) techniques to achieve high throughput.

36. 1. A method for managing channel bandwidth of one or more downlink signals, comprising: receiving input signals of the one or more downlink signals on a plurality of input channels, each input channel having a spectral bandwidth; performing, in a plurality of processing blocks within one or more processors, a combiner operation on the input channels that combines the spectral bandwidths of a selected subset of the plurality of input channels into a combined channel, the plurality of processing blocks operating in parallel; outputting the combined channel to a network; A method comprising:

37. 37. The method of claim 36, wherein the multiple processing blocks include multiple central processing unit (CPU) cores.

38. 38. The method of claim 36 or 37, wherein the one or more processors comprise a plurality of processors, and wherein at least a first processing block of the plurality of processing blocks is included in a first processor of the plurality, and a second processing block of the plurality of processing blocks is included in a second processor of the plurality of processors.

39. 38. The method of claim 36 or 37, wherein the one or more processors comprise a single processor.

40. The combiner operation includes a plurality of functions, the plurality of functions being: capturing samples from the selected subset of input channels, the samples being received as data packets contained in the subset of input channels; applying a multipoint inverse fast Fourier transform to the samples of each of the plurality of channels; performing a multi-point circular buffer for each of the plurality of channels based on the application of a multi-point inverse fast Fourier transform to the samples; combining the samples into the combined channel based on applying a multi-pass filter and an adder; 40. The method of any one of claims 36 to 39, comprising:

41. 37. The method of claim 36, wherein performing the combiner operation comprises distributing the functions among the processing blocks and performing the distributed functions in parallel.

42. 37. The method of claim 36, wherein at least two of the plurality of functions are performed in parallel by the separate processing blocks of the plurality of processing blocks.

43. the plurality of processing blocks includes first one or more processing blocks and second one or more processing blocks; performing, in the first one or more processing blocks, a first combiner operation on a first subset of input signals corresponding to a first subset of the plurality of input channels; performing a second combiner operation on a second subset of input signals corresponding to a second subset of the plurality of input channels in the second one or more processing blocks in parallel with the first one or more processing blocks; the first and second combiner options combine the spectral bandwidths of the first and second subsets of the plurality of input channels into the combined channel.

43. The method according to any one of claims 36 to 42.

44. 44. The method of any one of claims 36 to 43, further comprising: in one or more processors, dividing the digital bitstream into a plurality of data packets, each of the data packets of the plurality of data packets containing overlapping data from adjacent packets.

45. A method according to any one of claims 36 to 44, wherein the adjacent packets overlap in time by 1% of the length of the packets.

46. The method of any one of claims 36 to 45, wherein the plurality of data packets have different lengths.

47. The method of any one of claims 36 to 46, wherein the one or more processors are one or more general purpose central processing units (CPUs).

48. 48. The method of any one of claims 36 to 47, wherein the one or more processors use single instruction multiple data (SIMD) techniques to achieve high throughput.

49. 1. A system for managing one or more downlink signals, channel bandwidth, comprising: one or more antennas configured to receive the plurality of downlink signals; one or more processors communicatively coupled to the plurality of antennas, the one or more processors having a plurality of processing blocks and operable to perform the method of any one of claims 1 to 48; A system including:

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