Gaming Machines

Abstract

To reduce a program capacity in a game machine.SOLUTION: A game machine includes control means for performing control pertaining to progress of a game. The control means includes an accessible memory address space, and at least one register group including multiple general-purpose registers, and multiple upper-level value registers as registers for storing high-level values of a memory address space to be handled by partial instructions. The high-level value registers include a first type high-level value register and a second type high-level value register, and is configured so as to store a first high-level value in the first type high-level value register and a second high-level value differing from the first high-level value in the second type high-level value register, and refers to the first high-level value in the first type high-level value register in execution of a first instruction and refers to the second high-level value in the second type high-level value register in execution of a second instruction differing from the first instruction.SELECTED DRAWING: Figure 26

Description

Technical Field

[0001] The present invention relates to a gaming machine, and particularly to the details of the program executed by the gaming machine.

Background Art

[0002] For example, in gaming machines such as a pachinko gaming machine as a ball shooting gaming machine or a rotary gaming machine as a slot machine, an arithmetic processing device such as a CPU (Central Processing Unit) is provided as control means for performing control related to the progress of the game, and various operations of the gaming machine are realized by the arithmetic processing device performing processing according to the instructions described in the program.

[0003] Regarding related prior arts, Patent Document 1 below can be cited.

Prior Art Document

Patent Document

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, In recent years, the processes performed by gaming machines have become diverse, making it increasingly difficult to store the control system programs in the limited memory capacity. done.

[0006] Therefore, in the present invention, in the gaming machine Program size reduction aims to achieve.

Means for Solving the Problems

[0007] The gaming machine according to the present invention is The system includes control means for controlling gameplay, and the control means has an accessible memory address space and at least one group of registers, each containing multiple general-purpose registers and multiple high-value registers which store the high-value addresses of the memory address space used in some instructions. The high-value registers include a first-class high-value register and a second-class high-value register, the first-class high-value register stores the first high-value, and the second-class high-value register stores a second high-value different from the first high-value. When executing the first instruction, the first high-value of the first-class high-value register is referenced, and when executing a second instruction different from the first instruction, the second high-value of the second-class high-value register is referenced. such a thing.

[0008] Furthermore, the gaming machine could also be configured as follows: Specifically, the system comprises a first group of registers and a second group of registers, each comprising multiple general-purpose registers, a first interrupt management register and a second interrupt management register, a first instruction for writing an enable value to the first interrupt management register and the second interrupt management register, a second instruction for writing a prohibition value to the first interrupt management register and the second interrupt management register, a third instruction used when calling an out-of-bounds program from an in-bounds program, and a fourth instruction used when returning to the in-bounds program from the out-of-bounds program, wherein the third instruction can execute a process to write the prohibition value to the first interrupt management register and switch the group of registers to be used from the first group of registers to the second group before calling the out-of-bounds program, the fourth instruction can execute a process to overwrite the value of the second interrupt management register with the first interrupt management register and switch the group of registers to be used from the second group of registers to the first group before returning to the in-bounds program, and the third instruction is executed in the in-bounds program after the second instruction and before the first instruction is executed. When executing an out-of-bounds program, it is necessary to disable interrupts. Therefore, if the first instruction is executed before the third instruction, the interrupt-disabled and interrupt-enabled states will switch frequently. In contrast, if the third instruction is executed after the second instruction but before the first instruction, as described above, the interrupt-disabled state is maintained while calling the out-of-bounds program and returning to the in-bounds program, thus reducing the number of interrupt control state switches.

[0009] Also, as mentioned above Play In the machine, the first group of registers has a first stack pointer that stores a stack pointer, and the second group of registers has a second stack pointer that stores a stack pointer. The first stack pointer stores the address information of the stack memory used by the program within the region, and the second stack pointer stores the address information of the stack memory used by the program outside the region. When the program within the region executes the third instruction to call the program outside the region, it may call the program by specifying the first address of the program outside the region or by specifying the second address. In the program outside the region, whether the first address or the second address is called, it is possible to configure the machine to execute a fifth instruction to store the address information of the common stack memory in the second stack pointer.

[0010] This makes it possible to reset the value of the stack pointer used by the out-of-bounds program each time the out-of-bounds program is called.

[0011] Also, as mentioned above PlayIn the device, the first group of registers has a first stack pointer that stores a stack pointer, and the second group of registers has a second stack pointer that stores a stack pointer. The first stack pointer stores the address information of the stack memory used by the program within the region, and the second stack pointer stores the address information of the stack memory used by the program outside the region. When the program within the region executes the third instruction to call the program outside the region, it may either call the program by specifying the first address of the program outside the region, or it may call it by specifying the second address at a later timing. The program outside the region can be configured to execute a sixth instruction to store the address information of a predetermined stack memory in the second stack pointer only when the first address is called.

[0012] Since the address information of the stack memory that should be set for the second stack pointer at the start of processing of an out-of-bounds program is fixed address information, if the program at the second address is executed after the program at the first address as an out-of-bounds program, the storage of the address information for the second stack pointer only needs to be performed by the program at the first address, which is executed first. [Effects of the Invention]

[0013] According to the present invention, in a gaming machine Program size reduction It is possible to measure this. [Brief explanation of the drawing]

[0014] [Figure 1] This is a front perspective view showing the external appearance of a gaming machine as an embodiment of the present invention. [Figure 2] This diagram shows the configuration of the game board of a gaming machine as an embodiment. [Figure 3] This is a block diagram showing the control configuration of a gaming machine as an embodiment. [Figure 4]Explanatory diagram of an example of the preview notice effect in the embodiment. [Figure 5] Flowchart showing the main control side main processing of the embodiment. [Figure 6] Flowchart showing the initial setting process in FIG. 5. [Figure 7] Flowchart showing the power supply abnormality check process of the embodiment. [Figure 8] Diagram showing the correspondence relationship between each determination condition on the operation surface and the value of the W register when shifting to the setting change process, RAM clear process, setting confirmation process, and backup restoration process. [Figure 9] Flowchart showing the main loop process in FIG. 5. [Figure 10] Flowchart showing the setting change process in FIG. 5. [Figure 11] Flowchart showing the output management process in FIG. 10. [Figure 12] Diagram showing an example of a 7-segment decoding table. [Figure 13] Diagram exemplifying the relationship between the segment configuration and the segment display pattern in the display of the set value. [Figure 14] Flowchart showing the RAM clear process in FIG. 5. [Figure 15] Flowchart showing the setting confirmation process in FIG. 5. [Figure 16] Diagram showing an example of a set value offset conversion table. [Figure 17] Flowchart showing the pre-main loop process in FIG. 5. [Figure 18] Flowchart showing the main control side timer interrupt process of the embodiment. [Figure 19] Flowchart showing the power supply check / backup process in FIG. 18. [Figure 20] Flowchart showing the setting abnormality check process in FIG. 18. [Figure 21]This is an explanatory diagram of the memory area set in the main control unit. [Figure 22] This is an explanatory diagram of the regulations established for each area. [Figure 23] This diagram shows the register configuration in a previous example. [Figure 24] This diagram illustrates the program for the main loop processing (Figure 9) portion of the main control side main processing (Figure 5). [Figure 25] This diagram illustrates a program related to the performance display monitor aggregation division process (S304). [Figure 26] This figure shows the register configuration in the embodiment. [Figure 27] This is an explanatory diagram of the interrupt control flag update rule in the embodiment. [Figure 28] This figure illustrates an example of a domain-specific program when the processing transition method is applied as an embodiment. [Figure 29] This figure illustrates an example of an out-of-bounds program when the processing transition method is applied as an embodiment. [Figure 30] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 31] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 32] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 33] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 34] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 35] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 36] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 37] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 38] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 39] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 40] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 41] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 42] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 43] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 44] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 45] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 46] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 47] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 48] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 49] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 50] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 51]This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 52] This figure shows another example of a program within a domain when the processing transition method as an embodiment is applied. [Figure 53] This figure shows another example of an out-of-bounds program when the processing transition method as an embodiment is applied. [Figure 54] This diagram shows a modified example of a program within a region related to a register bank switching instruction. [Figure 55] This diagram shows a modified example of an out-of-bounds program related to a register bank switching instruction. [Figure 56] This diagram shows a modified example of a program within a region related to a register bank switching instruction. [Figure 57] This diagram shows a modified example of an out-of-bounds program related to a register bank switching instruction. [Figure 58] This diagram shows a modified example of a program within a region related to a register bank switching instruction. [Figure 59] This diagram shows a modified example of an out-of-bounds program related to a register bank switching instruction. [Figure 60] This diagram shows a modified version of the program within the region related to the register bank switching instruction. [Figure 61] This diagram shows a modified example of an out-of-bounds program related to a register bank switching instruction. [Figure 62] This diagram shows an example of a program within a memory area when using the "CALL" and "RET" instructions. [Figure 63] This diagram shows an example of an out-of-bounds program when using the "CALL" and "RET" instructions. [Figure 64] This figure shows the memory map of the main control unit in the embodiment. [Modes for carrying out the invention]

[0015] Hereinafter, embodiments of the present invention will be described in the following order with reference to the attached drawings. <1. Structure of a gaming machine> <2. Control Configuration of Gaming Machines> [2-1. Main Control Unit] (Regarding changing settings) (Regarding performance specifications) (Performance control command) [2-2. Production Control Unit] <3. Overview of Operation> [3-1. Symbol Variation Display Game] (Special symbol variation display game) (A game where decorative patterns change) (Normal symbol variation display game) (Regarding the hold) [3-2. Game Status] [3-3. Regarding the hit] [3-4. Regarding the direction / staging] (Performance Mode) (Preview / Preview) (Direction means) <4. Processing of the main control unit> [4-1. Main control side main processing] (Initial setup process) (Processing after initial setup) (Main loop processing) (Settings change process) (RAM clearing process) (Configuration confirmation process) (Pre-processing before the main loop) (Advantages of the data table for displaying setting values ​​and the setting value conversion table) [4-2. Main control side timer interrupt processing] (Power check and backup process) (Error management and processing for game progression, etc.) <5. Regarding the transition of processing between in-domain and out-of-domain processing> [5-1. Regarding the area used and the area not used] [5-2. Processing transition methods in previous examples] [5-3. Processing Transition Method as an Embodiment] [5-4. Another example of a program] [5-5. Variations of the program] [5-6. Other variations] <6. About the Q and U registers> <7. Summary of Embodiments>

[0016] <1. Structure of a gaming machine> The structure of a pachinko game machine 1 as an embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a front perspective view showing the external appearance of the pachinko game machine 1, and Figure 2 is a diagram showing the front side of the game board 3 of the pachinko game machine 1.

[0017] The pachinko game machine 1 shown in Figure 1 (hereinafter sometimes abbreviated as "game machine 1") has a wooden outer frame 4, a picture frame-like front frame 2 that can be opened and closed, a game board 3 (see Figure 2) mounted inside a game board storage frame (not shown) attached to the back of the front frame 2, and a game area 3a formed on the surface of the game board 3 facing the opening of the front frame 2. A glass door 6 supporting transparent glass is provided on the front side of this game area 3a. Various control boards (see Figure 3) for controlling game operation are arranged on the back side of the game board 3.

[0018] A key cylinder (not shown) for unlocking the door is provided on the front side of the glass door 6. By inserting a key into this key cylinder and operating it in one direction, the lock on the glass door 6 to the front frame 2 is released, and by operating it in the other direction, the lock on the front frame 2 to the outer frame 4 is released, allowing the door to be opened to the front.

[0019] Below the glass door 6, a front operation panel 7 is positioned, pivotally supported by a hinge (not shown) on the front frame 2 so as to be able to open and close. The front operation panel 7 is provided with an upper receiving unit 8, and this upper receiving unit 8 has an upper receiving tray 9 for storing the dispensed game balls.

[0020] The upper tray unit 8 is also equipped with a ball release button 14 for removing game balls stored in the upper tray 9 to the bottom of the game machine 1, a ball dispensing button 11 for requesting game balls from a game ball dispensing device (not shown), and a card return button 12 for requesting the return of a valuable medium inserted into the game ball dispensing device. The upper tray unit 8 is also equipped with a performance button 13 (operating means) configured to be operated by the player. This performance button 13 becomes operable (input accepted) when its built-in lamp (button LED 75) lights up during a predetermined input acceptance period, and by performing a predetermined operation (pressing, repeatedly pressing, holding down, etc.) while the built-in lamp is lit, it is possible to change the performance. Although not shown in Figure 1, the front control panel 7 is equipped with controls such as a directional pad 15a for players, hall staff, and other users to select various items and provide directions, and a confirmation button 15b for confirming selected items.

[0021] Furthermore, a launch operation handle 15 for operating the launch device 32 (see Figure 3) is provided on the right end of the front control panel 7.

[0022] Furthermore, speakers 46 are provided on both sides of the upper part of the front frame 2 and above the firing operation handle 15 to produce sound effects. In addition, multiple decorative lamps 45 (for example, full-color LEDs for light effects) are provided at appropriate locations on the glass door 6 to produce light effects. Multiple full-color LEDs (light effect LEDs) serving as decorative lamps 45 are provided circumferentially around the periphery of the front frame of the glass door 6, that is, around the edge of the front frame of the pachinko game machine.

[0023] Referring to Figure 2, the configuration of the game board 3 will be explained. The game board 3 shown in the figure has a ball guide rail 5 mounted in an annular shape as a board surface partitioning member to guide the launched game ball. The roughly circular area surrounded by this ball guide rail 5 is the game area 3a, and the four corners are non-game areas.

[0024] Approximately in the center of this game area 3a, there is a liquid crystal display (LCD) 36 that can independently display multiple types of decorative symbols (for example, left symbol (corresponding to the left display area), middle symbol (corresponding to the middle display area), and right symbol (corresponding to the right display area)) in three (left, middle, and right) display areas (symbol variation display areas). In the following explanation, the multiple types of decorative symbols that are displayed in the left, middle, and right symbols may each be referred to as "symbol groups". That is, for example, a symbol that is stopped and displayed in the left display area is considered to be one of the symbol groups that make up the left symbol. This liquid crystal display device 36, under the control of the performance control unit 24 described later, displays various effects as images, in addition to the changing display operation of decorative patterns.

[0025] Furthermore, a center ornament 48 is provided within the game area 3a, surrounding the display surface of the liquid crystal display device 36 at a distance. The center ornament 48 is provided along the front side of the game board 3, protecting the display surface of the liquid crystal display device 36 from surrounding game balls, and also functions as a flow path distribution means that allows the flow path of the game balls to be divided to the left or right depending on the force or stroke length of the launch of the game balls. In this embodiment, the center ornament 48 is positioned approximately in the center of the game area 3a so that the presence of the center ornament 48 forms flow paths for the game balls on both the upper sides (left and right) of the game area 3a. Game balls launched into the upper side of the game area 3a by the launching device 32 are divided to the left or right at the upper side of the armor frame portion 48b, and flow down either the left-downward flow path 3b on the left side of the center ornament 48 or the right-downward flow path 3c on the right side.

[0026] In addition, the non-game area near the upper right edge (upper right corner) of the game board 3 serves as various function display sections. A special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) are provided, which are configured by arranging 7-segment displays (with dots) horizontally corresponding to the upper start port 34 (for the first special symbol) and the lower start port 35 (for the second special symbol). In the special symbol display devices 38a and 38b, a special symbol variable display game is executed by the variable display operation of the "special symbol" expressed by the 7-segment display. And in the above liquid crystal display device 36, in synchronization with the variable display of the special symbol by the special symbol display devices 38a and 38b, a decorative symbol is variably displayed by an image, and a decorative symbol variable display game is executed together with various preview effects (effect images) (details of these symbol variable display games will be described later).

[0027] Also, in the various function display sections, a composite display device (LED display for suspended composite display) 38c composed of 7-segment displays (with dots) is disposed next to the special symbol display devices 38a and 38b. It is called "composite" because it is a suspended, time-shortening, high-probability composite display device (hereinafter simply referred to as "composite display device") having five display functions, namely, the display of the number of suspended balls for the special symbols 1 and 2 and the normal symbol, the state notification during the operation of the variable time shortening function (during time shortening) and the high-probability state (during high probability).

[0028] Furthermore, next to the composite display device 38c, the various function display units are provided with a regular symbol display device 39a (regular symbol display means) which consists of multiple LEDs (two in this embodiment). In this regular symbol display device 39a, a regular symbol variation display game is executed by the variation display operation of a regular symbol represented by the two LEDs. For example, as a variation display operation, the regular symbol represented by the LEDs repeatedly lights up and turns off alternately in a seesaw-like manner, and when it stops with one side lit, the success or failure of the regular symbol variation display game is determined. Adjacent to this regular symbol display device 39a, there is also a round number display device 39b which consists of three LEDs (1st to 3rd round display LEDs). This round number display device 39b notifies the prescribed number of rounds (maximum number of rounds) related to a jackpot based on the combination of the lit-off states of the three LEDs.

[0029] Below the center ornament 48, a regular variable prize winning device 41 is provided, with an upper starting port 34 (first special symbol starting port: first starting means) and a lower starting port 35 (second special symbol starting port: second starting means), and detection sensors 34a and 35a (upper starting port sensor 34a, lower starting port sensor 35a: see Figure 3) are formed inside each to detect the passage of the game ball.

[0030] The upper starting opening 34, which is the first special symbol starting opening, is a prize-winning opening related to the starting conditions for the variable display operation of the first special symbol (hereinafter, the first special symbol will be referred to as "special symbol 1," and sometimes abbreviated as "special symbol 1") in the special symbol display device 38a, and is configured as a prize-winning device with a fixed winning rate that does not have a starting opening opening opening means (means that allow the starting opening to be opened or enlarged). In this embodiment, due to the action of the game ball falling direction changing members in the game area 3a (for example, game pins (not shown), windmill 44, center decoration 48, etc.), the upper starting opening 34 is configured to be easily entered (prised) for game balls that have flowed down the left downward path 3b, while it is configured to be difficult or impossible for game balls that have flowed down the right downward path 3c to enter.

[0031] The standard variable prize winning device 41 is configured as a prize winning rate variable type prize winning device in which the prize winning rate of game balls entering the starting opening can be varied by the starting opening opening opening means. In this embodiment, the starting opening opening opening means is configured as a so-called "electric tulip type" prize winning device, which includes a pair of left and right movable wing pieces (movable members) 47 that can open or enlarge the lower starting opening 35, which is a second special symbol starting opening.

[0032] The lower starting port 35 of the normal variable prize winning device 41 is a prize winning port related to the starting conditions for the variable display operation of the second special symbol (hereinafter, the second special symbol will be referred to as "special symbol 2," and sometimes abbreviated as "special symbol 2") in the special symbol display device 38b. The prize winning area of ​​this lower starting port 35 is converted between an open state that makes it easier to win (easy prize winning state) and a closed state that makes it more difficult to win than the open state, or makes it impossible to win (difficult prize winning state), depending on the operating state (operated or inoperated) of the movable wing piece 47. In this embodiment, when the movable wing piece 47 is inoperated, the lower starting port 35 is kept in a closed state (impossible prize winning state) that makes it impossible to win.

[0033] Furthermore, on both sides of the normal variable prize winning device 41, there are a total of four general prize winning openings 43, three on the left and one on the right, and each of these has a general prize winning opening sensor 43a (see Figure 3) that detects the passage of the game ball. In addition, movable mechanical devices (not shown) that provide visual effects are placed within the area of ​​the game board in positions that do not obstruct the flow of the game ball.

[0034] Furthermore, above and to the right of the normal variable prize winning device 41, that is, above the middle of the right-flowing downward path 3c, is a normal symbol starting opening 37 (third starting means) consisting of a passage gate (specific passage area) through which game balls can pass. This normal symbol starting opening 37 is a prize winning opening related to the variable display operation of normal symbols in the normal symbol display device 39a, and a normal symbol starting opening sensor 37a (see Figure 3) for detecting passing game balls is formed inside it. In this embodiment, the normal symbol starting opening 37 is formed only on the right-flowing downward path 3c side and not on the left-flowing downward path 3b side. However, the present invention is not limited to this, and may be formed only on the left-flowing downward path 3b, or on both downward paths.

[0035] In the path from the normal symbol start opening 37 to the normal variable prize winning device 41 within the rightward flow path 3c, there is a special variable prize winning device 52 (special electric mechanism) configured to open or enlarge the large prize winning opening 50 by a retractable opening door 52b, and a large prize winning opening sensor 52a (see Figure 3) is formed inside it to detect game balls that have entered the large prize winning opening 50.

[0036] The area around the large prize opening 50 is a bulging portion (decorative member) 55 that protrudes from the surface of the game board 3, and the upper edge 55a of this bulging portion 55 forms the downstream guide portion of the rightward flow path 3c. When the large prize opening 50 is closed by the open door 52b (large prize opening closed state), the upper edge 55a of this bulging portion 55 forms a continuous surface, thereby forming a part of the downstream guide portion (upper edge 55a) of the rightward flow path 3c. Furthermore, in the downstream area of ​​the rightward flow path 3c, in the area above the upper edge 55a of the bulging portion 55, more precisely in the game area above the large prize opening 50, a flow path correction plate 51d is provided protruding almost parallel to the direction of the flow of the game balls, and its function is to guide the flowing game balls toward the large prize opening 50.

[0037] The process of a game ball entering the large prize slot 50 is as follows: The game ball, having passed through the free-moving area between the upper surface of the center ornament 48 and the ball guide rail 5, flows down along the top surface (upper edge) 55a of the bulging portion 55, which protrudes from the game board 3 and functions as a guide for the game ball. The game ball then comes into contact with the right end of the flow path correction plate 51d, which protrudes from the surface of the game board 3, thereby correcting the direction of the game ball's flow toward the large prize opening 50 (downward). At this time, if the large prize opening 50 is covered by the retractable opening door 52b (large prize opening closed), the game ball rolls over it and is further guided toward the tulip-type normal variable prize device 41 (lower starting opening 35) by a predetermined arrangement of game pins (not shown). At this time, if the lower starting opening 35 is in a prize-winning state (starting opening open), the game ball can enter the lower starting opening 35. On the other hand, if the open door 52b is retracted into the game board and the large prize opening 50 is open (large prize opening open state), the game ball will be guided into the large prize opening 50.

[0038] In this embodiment of the gaming machine 1, if the player aims the launch position towards the special variable prize winning device 52 (i.e., aims so that the game ball passes through the rightward downward path 3c), the configuration makes it difficult, or impossible, for the game ball to be guided towards the upper start opening 34. Therefore, if the "large prize winning opening is closed," unless the movable wing piece 47 of the normal variable prize winning device 41 is activated, it is difficult or impossible to win prizes in each start opening 34, 35. When the game state is accompanied by the electric support state described later, the movable wing piece 47 operates with an opening and closing pattern that is more advantageous than the normal state.

[0039] In this embodiment, the advantageous playing style for the player varies depending on the game state. Specifically, in a game state with "no electric support" (described later), "left-handed play," where the player aims to have the ball pass through the left-down path 3b, is advantageous. In a game state with "electric support" (described later), "right-handed play," where the player aims to have the ball pass through the right-down path 3c, is advantageous.

[0040] In the gaming machine 1 of this embodiment, when a ball enters one of the various prize-winning slots provided in the gaming area 3a, other than the regular symbol start slot 37, the number of prize balls awarded per winning ball for each prize-winning slot (for example, 3 balls for the upper start slot 34 or lower start slot 35, 13 balls for the large prize slot 50, and 10 balls for the general prize slot 43) is dispensed from the gaming ball dispensing device 19 (see Figure 3). Gaming balls that do not enter any of the above prize-winning slots are discharged from the gaming area 3a via the out slot 49. Here, "winning" refers to a game ball entering an entry point, or, if the entry point is not designed to take in game balls but consists of a pass-through gate (for example, the normal symbol start point 37), a game ball passing through that gate. In practice, if a game ball is detected by the entry detection switch formed for each entry point, it is treated as if a "winning" event has occurred at that entry point. The game ball involved in this winning is also called a "winning ball." Since a game ball entering an entry point will be detected by the entry detection switch, unless otherwise specified in this specification, the term "winning" may be used to include the case where a game ball enters an entry point, regardless of whether or not the game ball is detected by the entry detection switch.

[0041] <2. Control Configuration of Gaming Machines> Referring to the block diagram in Figure 3, the configuration (control configuration) for realizing the game operation control of the gaming machine 1 will be explained. The gaming machine 1 of this embodiment is configured to include a main control board (main control means) 20 (hereinafter referred to as "main control unit 20") which comprehensively controls the overall operation of the game (game operation control), an effect control board (effect control means) 24 (hereinafter referred to as "effect control unit 24") which receives effect control commands from the main control unit 20 and comprehensively controls the execution control of effects by the effect means (appearance control), a payout control board (payout control means) 29 which controls the payout of prize balls, and a power supply board (power supply control means (not shown)) which generates and supplies the power necessary for the gaming machine 1 from an external power supply (not shown). Note that the power supply routes to each component are omitted in Figure 3.

[0042] [2-1. Main Control Unit] The main control unit 20 is equipped with a microprocessor that incorporates a CPU (Central Processing Unit) 20a (main control CPU), a ROM (Read Only Memory) 20b (main control ROM) that stores various data necessary for game operation control as well as a control program that describes the game operation control procedure, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, thus forming a microcomputer as a whole.

[0043] Although not shown in the diagram, the main control unit 20 also includes a CTC (Counter Timer Circuit) for implementing periodic interrupts, a function to create pulse outputs of a fixed period (bitrate generator), and a time measurement function; an interrupt controller circuit that performs interrupt enable / disable functions such as timer interrupts that provide interrupt signals to the CPU 20a; a reset circuit that can reset the CPU 20a by outputting a system reset signal when power is turned on, cut off, or a power supply abnormality is detected; a watchdog timer (WDT) circuit that monitors abnormal operation of the control program; an Intrusion Prevention of Travel Outside Designated Area (IAT) circuit that monitors whether the program is being executed correctly within a preset address range; and a counter circuit for generating random numbers within a certain range in hardware.

[0044] The counter circuit described above includes a random number generation circuit that generates random numbers and a sampling circuit that samples random numbers from the random number generation circuit at predetermined timings, and functions as a 16-bit counter as a whole. The CPU 20a sends instructions to the sampling circuit according to the processing state to obtain the value indicated by the random number generation circuit as an internal random number for lottery (random number for jackpot determination (magnitude of random number: 65536)), and uses this random number for jackpot lottery. The internal random number for lottery is obtained by adding a software random number generated by appropriate software processing and a hardware random number to prevent cheating such as targeting specific jackpots.

[0045] Furthermore, the CPU 20a is equipped with multiple registers for storing various values. Details of the registers provided by the CPU 20a in this embodiment will be described later.

[0046] The main control unit 20 is connected to an upper start-up sensor 34a that detects entry into the upper start-up opening 34, a lower start-up sensor 35a that detects entry into the lower start-up opening 35, a regular symbol start-up sensor 37a that detects passage through the regular symbol start-up opening 37, a large prize-winning opening sensor 52a that detects entry into the large prize-winning opening 50, a general prize-winning opening sensor 43a that detects entry into the general prize-winning opening 43, and an OUT monitoring switch 49a that detects game balls (out balls) discharged from the out-out opening 49. The main control unit 20 is capable of receiving detection signals output from these sensors. Based on the detection signals from each sensor, the main control unit 20 can determine which prize-winning opening a game ball has entered.

[0047] Furthermore, the main control unit 20 is connected to a standard electric mechanism solenoid 41c for controlling the opening and closing of the movable blade 47 of the lower start opening 35, and to a large prize opening solenoid 52c for controlling the opening and closing of the opening door 52b of the large prize opening 50. The main control unit 20 is capable of transmitting control signals to control these.

[0048] Furthermore, the main control unit 20 is connected to a special pattern display device 38a and a special pattern display device 38b, and the main control unit 20 is capable of transmitting control signals for displaying and controlling special patterns 1 and 2. In addition, the main control unit 20 is connected to a normal pattern display device 39a, and is capable of transmitting control signals for displaying and controlling normal patterns.

[0049] Furthermore, the main control unit 20 is connected to a composite display device 38c and a round number display device 39b. The main control unit 20 is capable of transmitting control signals to control the display of various information shown on the composite display device 38c and control the display of the specified number of rounds due to a jackpot shown on the round number display device 39b.

[0050] Furthermore, the main control unit 20 is connected to an external centralized terminal board 21 for the frame, and the main control unit 20 is capable of transmitting predetermined game information (for example, jackpot information, prize ball count information, symbol change execution information, etc.) to a hall computer HC located outside the gaming machine via the external centralized terminal board 21 for the frame. The hall computer HC is an information processing device (computer device) that monitors game information from the main control unit 20 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0051] Furthermore, the main control unit 20 is connected to a payout control board (payout control unit) 29, and when it is necessary to pay out prize balls, it is possible to send a control command related to the payout (a payout control command specifying the number of prize balls) to the payout control board 29.

[0052] The payout control board 29 is connected to a launch control board (launch control unit) 28 that controls the launching device 32, and a game ball payout device (game ball payout means) 19 that dispenses game balls. The main roles of this payout control board 29 are to receive payout control commands from the main control unit 20, control the payout of prize balls by the game ball payout device 19 based on the payout control commands, and transmit status signals to the main control unit 20.

[0053] The game ball dispensing device 19 is equipped with a supply shortage detection sensor 19a for detecting insufficient supply of game balls and a ball counting sensor 19b for detecting the number of game balls (prize balls) to be dispensed, and the dispensing control board 29 is capable of receiving these detection signals. The game ball dispensing device 19 is also equipped with a dispensing motor 19c for driving a ball dispensing mechanism (not shown) for dispensing game balls, and the dispensing control board 29 is capable of transmitting control signals to control the dispensing motor 19c.

[0054] Furthermore, the payout control board 29 is connected to a fullness detection sensor 60 (in this embodiment, a detection sensor that detects the storage state of game balls stored in the upper tray 9) which detects when the upper tray 9 is full of game balls, and a front door open sensor 61 (in this embodiment, a detection sensor that detects when at least the front frame 2 is open).

[0055] The payout control board 29 is capable of transmitting various status signals to the main control unit 20 based on detection signals from the full-capacity detection sensor 60, the front door open sensor 61, the supply depletion detection sensor 19a, and the ball count sensor 19b. These status signals include a ball jam signal indicating a full-capacity state, a door open signal indicating that at least the front frame 2 is open, a supply depletion signal indicating insufficient supply of game balls from the game ball payout device 19, a counting error signal indicating insufficient payout of prize balls or an abnormality in the ball count sensor 19b, and a payout completion signal indicating that the payout operation has been completed. The main control unit 20 is configured to transmit a variety of status signals. Based on these status signals, the main control unit 20 monitors the open state of the front frame 2 (door open error), whether the payout operation of the game ball payout device 19 is normal or not (supply depletion error), and the full state of the upper tray 9 (ball jam error), etc.

[0056] Furthermore, a launch control board 28 is connected to the payout control board 29, and it is possible to send a permission signal to the launch control board 28 to allow launching. Based on the output of the permission signal from the payout control board 29, the launch control board 28 controls the power supply to the launch solenoid (not shown) provided on the launching device 32, thereby realizing the launching operation of the game ball by operating the launching operation handle 15. Specifically, the launching operation of the game ball is permitted under the following conditions: the payout control board 29 outputs a launch permission signal (launch permission signal ON state), a touch sensor (not shown) provided on the launching operation handle 15 detects that the player is touching the handle, and the launch stop switch (not shown) provided on the launching operation handle 15 is not operated. Therefore, if the launch permission signal is not output (launch permission signal OFF state), the launching operation will not be performed even if the launching operation handle 15 is operated, and no game ball will be launched. In addition, the strength of the launch of the game ball can be changed according to the amount the launching operation handle 15 is operated. Furthermore, when the dispensing control board 29 detects the ball jam error, it sends a ball jam signal to the main control unit 20 and stops outputting the launch permission signal to the launch control board 28 (launch permission signal OFF), and performs control to stop the launching operation until the upper tray 9 is cleared of its full state. Furthermore, the dispensing control board 29 outputs a launch permission signal to the launch control board 28 only when the main control unit 20 has instructed it to grant launch permission.

[0057] Here, the main control unit 20 is connected to a setting key switch 94 and a RAM clear switch 98, and is capable of receiving detection signals from these switches.

[0058] The RAM clear switch 98 is, for example, a push-button type switch used to input an instruction to initialize a predetermined area of ​​the RAM 20c. The setting key switch 94 is a key switch used to switch to setting change mode (when ON) by inserting a setting key held by a hall staff member when the power is turned on and performing an ON / OFF operation. Here, the setting change mode is a mode in which the setting value Ve can be changed. The setting value Ve represents a value that indicates the probability of winning a game state that is advantageous to the player.

[0059] The RAM clear switch 98 is turned ON / OFF in response to the operation of the RAM clear button, which is provided so that it can be operated when the front frame 2 is open. The setting key switch 98 is provided with a corresponding key cylinder into which the setting key described above can be inserted and removed. When the setting key inserted into the key cylinder is rotated in the forward direction, it turns ON, and when it is rotated in the reverse direction from the ON state, it turns OFF. The key cylinder is provided so that it can be operated by inserting the setting key when the front frame 2 is open. The key cylinder functions as an operating element that becomes operable when the setting key is inserted.

[0060] In this example, the RAM clear button is also used to change the setting value Ve. Specifically, the RAM clear button also functions as an operator for sequentially cycling through the setting value Ve.

[0061] The RAM clear switch 98 and the setting key switch 94 are provided in appropriate locations inside the gaming machine 1. For example, they are located on the main control board 20.

[0062] The main control unit 20 is also connected to a setting / performance indicator 97. The setting / performance indicator 97 is configured, for example, with a 7-segment display and functions as a display means capable of displaying the set value Ve and performance information (described later). The setting / performance indicator 97 is mounted, for example, in an easily visible position on the main control unit (main control board) 20. The main control unit 20 is capable of sending control signals to the setting / performance indicator 97 to display the set value Ve and performance information.

[0063] Here, the setting value Ve primarily defines the probability of winning at least one jackpot (the type of win that triggers the conditional device described later) in stages (for example, 6 stages from setting 1 to 6). The higher the setting value Ve, the higher the probability of winning (setting 1 is the lowest probability of winning, and thereafter the probability of winning increases in ascending order of the setting value), which is advantageous to the player. In other words, the higher the setting value Ve, the higher the so-called "machine payout rate (payout rate)," which is advantageous to the player. Thus, the set value Ve is a value that defines the probability of winning a jackpot and the payout rate, and represents a value related to the likelihood of specific events occurring, such as the profitable state that affects the player. In this embodiment, the degree of advantage related to the game is defined according to each set value Ve.

[0064] In this example, it is assumed that there are six levels (advantage levels) for the set value Ve that are permitted under the rules. Specifically, it is assumed that the range of the set value Ve that is permitted under the rules (hereinafter referred to as the "permissible range Re") is in the range of "1" to "6". Under this premise, the pachinko game machine 1 in this example uses only a subset of the setting values ​​Ve that are permitted under the regulations. Specifically, the pachinko game machine 1 in this example uses only three values, for example, "1", "2", and "6", from the setting values ​​Ve of "1" to "6" within the permitted range Re. In other words, the number of stages for winning probability is limited to three stages, rather than the maximum of six stages permitted under the regulations. Hereinafter, the range of setting values ​​Ve actually used in pachinko game machine 1, specifically the range of setting values ​​Ve actually used within the usable range Re (the range of "1", "2", and "6" in the above example), will be referred to as "usable range Ru".

[0065] The setting value Ve is set solely by the hall staff, such as hall employees, based on the hall's (amusement parlor's) business strategy. If there are multiple types of jackpots, the type of jackpot to which the winning probability is affected, and which jackpot types are affected, can be determined as appropriate. For example, if there are three types of jackpots, jackpots 1 through 3, a relatively higher setting value Ve may result in higher winning probabilities for all three jackpots, or a higher combined winning probability for all three. Alternatively, the winning probabilities of some jackpots may be increased. For example, the winning probabilities for jackpots 1 and 2 may be increased, while the winning probability for jackpot 3 remains constant regardless of the setting value Ve.

[0066] (Regarding changing settings) To change the setting value Ve, in this example, with the power to the gaming machine 1 turned off and the front frame 2 released, the setting key switch 94 is turned ON (operated to the setting change mode) and the RAM clear button is pressed (RAM clear switch 98 is ON), and then the power to the gaming machine 1 is turned on. Then, the current setting value Ve is displayed on the setting / performance display 97, and the system switches to "setting change mode" in which the setting value Ve (1, 2, 6 in this example) can be changed.

[0067] In this example, the decision of whether or not to transition to the setting change mode is made in the main control side main processing described later (see step S104 in Figure 5). When the above operating conditions for transitioning to the setting change mode are satisfied, the processing for changing the settings is executed accordingly.

[0068] After transitioning to the setting change mode, when the RAM clear button, which functions as an operator for changing the setting value Ve, is turned ON, the current displayed value of the setting / performance indicator 97 cycles through the usage range Ru, such as "1→2→6→1→2→6→...". When the desired setting value Ve is reached, the setting key switch 94 is turned OFF, the setting value Ve is finalized, and the information of the finalized setting value Ve is stored (memorized) in a predetermined area of ​​RAM 20c. Furthermore, when the setting key switch 94 is turned OFF, the setting change mode is terminated, and the display on the setting / performance indicator 97 is cleared. Once the settings change mode ends, the system transitions to a state where gameplay is permitted.

[0069] (Regarding performance specifications) The main control unit 20 is capable of transmitting control signals to the setting / performance indicator 97 to display predetermined performance information. Performance information refers to information that pachinko parlors and relevant government agencies want to verify. Typical examples include information on whether or not there are any fraudulent payout tactics such as excessive payouts on the gaming machine, and information on the machine's inherent payout performance. Therefore, unlike pre-announcement effects and other such information, performance information itself is not directly related to the progress of the game while the player is enjoying the game.

[0070] For this reason, the setting / performance indicator 97 is installed inside the gaming machine 1, for example, on the main control unit (main control board) 20, the payout control board 29, the launch control board 28, the relay board, the performance control unit (performance control board (including the LCD control board)) 24, or on the board case (protective cover that protects the board), in a position where the display information can be seen when the front frame 2 is open.

[0071] Here, the performance information can specifically include the following:

[0072] (1) Information based on the value obtained by dividing the total number of balls dispensed by winning during a specific state (total number of prize balls during the specific state: α) by the total number of balls discharged from the outlet 49 during the same specific state (number of balls discharged during the specific state: β) (α / β) (specific ratio information) can be adopted as performance information. The "total number of balls dispensed" mentioned above refers to the total number of game balls (prize balls) dispensed when a ball enters one of the prize winning slots (upper starting slot 34, lower starting slot 35, general prize winning slot 43, and large prize winning slot 50). In this embodiment, the upper starting slot 34 or lower starting slot 35 dispenses 3 balls, the large prize winning slot 50 dispenses 13 balls, and the general prize winning slot 43 dispenses 10 balls. Furthermore, the specific state to be adopted can be appropriately determined depending on the performance information to be captured under what state. In this embodiment, any of the following states can be adopted: normal state, latent probability state, time-saving state, probability variation state, or during a big win game. In addition, multiple types of states may be measured. For example, the normal state and probability variation state, or all game states except during a win game, and the types to be measured can be appropriately determined. Furthermore, the period within a specific state may be defined as a period in which the probability of winning a jackpot is either low or high. Alternatively, the total number of payouts may be calculated by excluding one or more specific winning slots from the measurement (total payouts excluding specific winning slots). For example, the total number of payouts may be calculated by excluding the 50 major winning slots from the measurement.

[0073] (2) In addition, the total number of balls dispensed, the total number of balls dispensed excluding specific prize slots, or the total number of balls that go out may be measured, and the measurement results may be used as performance information.

[0074] In this embodiment, the total number of balls dispensed during normal operation (normal number of balls dispensed) and the total number of balls out during normal operation (normal number of balls out) are measured in real time, and the value obtained by dividing the normal number of balls dispensed by the normal number of balls out and multiplying the result by 100 (calculated as normal number of balls dispensed ÷ normal number of balls out × 100) is displayed as performance information (hereinafter referred to as "normal ratio information"). The displayed value in this case is rounded to the first decimal place. Therefore, data on the number of balls dispensed under normal conditions, the number of balls out under normal conditions, and the ratio information under normal conditions are stored in the corresponding areas of RAM20c (specific total prize ball storage area, specific ball out storage area, and specific ratio information storage area). However, instead of simply measuring and displaying performance information indefinitely, the measurement is terminated once the total number of balls out reaches a predetermined number (for example, 60,000 balls). This predetermined number is not the total number of balls out under normal conditions, but the total number of balls out during all game states (including during winning games) (hereinafter referred to as "total number of balls out under all conditions"). This total number of balls out under all conditions is also measured in real time and stored in the corresponding area of ​​RAM20c (total number of balls out under all conditions storage area). For the sake of explanation, the specific total prize ball storage area, specific ball out storage area, specific ratio information storage area, and total number of balls out under all conditions storage area will be abbreviated as "measurement information storage area".

[0075] Then, the normal ratio information at the end of the measurement is stored in a predetermined area (performance display storage area) of RAM20c (to store the current normal ratio information), and after that, the measurement information storage area (normal payout count, normal out count, and total out count) is cleared, and then measurement is started again (measurement of normal payout count, normal out count, normal ratio information, and total out count is started). The setting / performance display unit 97 then displays the previous normal ratio information (measurement history information) and the normal ratio information currently being measured. Note that it may be configured to display history not only for the previous information, but also for the time before last and the time before that (3 times ago), and the number of times back in time to display information can be determined as appropriate.

[0076] In this example, the setting / performance indicator 97 displays either the setting value Ve or performance information. Specifically, in this example, setting changes and setting confirmations are performed only during startup when the power is turned on. Therefore, after startup following power-on, the setting value Ve is displayed on the setting / performance indicator 97 depending on whether the system has entered setting change mode or setting confirmation mode. After the setting change or confirmation is complete, the performance information is displayed. Furthermore, the system is not limited to displaying the set value Ve and performance information on a common display; it is also possible to use separate displays. In that case, the set value Ve and performance information may be displayed in parallel.

[0077] (Performance control command) The main control unit 20 is capable of transmitting various performance control commands, including information related to special symbol variation display games and error information, to the performance control unit 24, depending on the processing status. However, in order to prevent fraudulent activities such as cheating, the main control unit 20 only transmits signals to the performance control unit 24 and is configured for one-way communication in which it cannot receive signals from the performance control unit 24.

[0078] Here, the performance control command defines its function using a two-byte configuration consisting of a one-byte mode and a one-byte event. To distinguish between MODE and EVENT, Bit 7 of MODE is set to ON and Bit 7 of EVENT is set to OFF. When this information is to be transmitted as valid, a strobe signal is output corresponding to each of the mode and event. That is, when the CPU 20a (main control CPU) has a command to send, it sets and outputs mode information for sending the command to the performance control unit 24, and sends the first strobe signal after a predetermined time has elapsed since this setting. Furthermore, after a predetermined time has elapsed since the transmission of this strobe signal, it sets and outputs event information, and sends the second strobe signal after a predetermined time has elapsed since this setting. The strobe signal is controlled to be active by the CPU 20a for a predetermined period to ensure that the CPU 24a (performance control CPU) can reliably receive the command.

[0079] [2-2. Production Control Unit] The performance control unit 24 is primarily composed of a microcomputer equipped with a built-in CPU 24a (performance control CPU), a ROM 24b (performance control ROM) that stores performance data required for performance control processing, and a RAM 24c (performance control RAM) that functions as a work area and buffer memory. In addition, it is equipped with an audio control unit (sound source IC), an RTC (Real Time Clock) function unit, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc., to control the overall performance operation.

[0080] The performance control CPU 24a performs calculation processing for various performance operations and controls each performance means based on the performance control program and performance control commands received from the main control unit 50. In the case of the pachinko game machine 1 of this embodiment, the performance means are a liquid crystal display device 36 (main liquid crystal display device 36M, sub-liquid crystal display device 36S), an optical display device 45a, a sound generating device 46a, and a movable mechanism not shown in the figure.

[0081] The performance control ROM 24b stores the control program for performance operations performed by the performance control CPU 24a, as well as various data necessary for controlling performance operations. The performance control RAM 24c is used by the performance control CPU 24a as a work area for various calculation processes, a table data area, a buffer area for various input / output data and processing data, etc. The arithmetic control unit 24 can be configured with a single-chip microcomputer and its peripheral circuits, but various configurations are possible for the performance control unit 24. For example, in addition to the microcomputer, it may also include interface circuits to each part, a random number generation circuit to generate random numbers for drawing for performances, a CTC for various time counting, a watchdog timer (WDT) circuit, and an interrupt controller circuit that provides interrupt signals to the performance control CPU 24a.

[0082] The main roles of this performance control unit 24 are to receive performance control commands from the main control unit 20, to select and determine performances based on the performance control commands, to control the display of the liquid crystal display device 36 (supply of display data), to control the sound output of the sound generator 46a, to control the light emission of the light display device 45a (LED), and to control the operation of the movable parts (drive control of the movable part motor 80c).

[0083] Since the performance control unit 24 also functions as a control unit for the liquid crystal display device 36, the performance control unit 24 is equipped with the functions of a so-called VDP (Video Display Processor), image ROM, and VRAM (Video RAM), and the performance control CPU 24a also functions as a liquid crystal control unit. VDP refers to a function that controls all aspects of video output processing, including image unpacking and image rendering. Image ROM refers to the memory where image data (animation image data) that the VDP uses for image processing is stored. VRAM is an image memory area that temporarily stores image data expanded by VDP.

[0084] Based on these configurations, the performance control unit 24 generates various image data based on commands from the main control unit 20 and outputs it to the main liquid crystal display device 36M and the sub-liquid crystal display device 36S. As a result, various performance images are displayed on the main liquid crystal display device 36M and the sub-liquid crystal display device 36S.

[0085] Furthermore, the sound control unit 24 has an acoustic control unit (sound controller: sound source IC) for the sound generating device 46a, which includes a speaker 46. The acoustic signal output by the acoustic control unit is amplified by the amplifier unit 46d and supplied to the speaker 46. Furthermore, the performance control unit 24 is connected to a lamp driver unit 45d, which functions as a light display control unit for the light display device 45a, including decorative lamps 45 and various LEDs, and a motor driver unit 80d (motor drive circuit), which functions as a drive control unit for the movable body motor 80c that operates a movable body (not shown). The performance control unit 24 issues instructions to these lamp driver unit 45d and motor driver unit 80d to control the light display operation of the light display device 45a and the operation of the movable body motor 80c.

[0086] The performance control unit 24 is also connected to an origin switch 81 and a position detection sensor 82 for monitoring the movement of the movable parts. The origin switch 81 is composed of, for example, a photointerrupter, and detects whether the movable mechanism motor 80c is in the origin position. The origin position is, for example, a position where the movable mechanism is not normally visible on the panel in Figure 2. The performance control unit 24 is capable of determining whether the movable mechanism motor 80c is in the origin position based on the detection information from the origin switch 81. Furthermore, the performance control unit 24 monitors the current operating position of the movable mechanism (for example, the amount of movement from the origin position) based on the detection information from the position detection sensor 82 and controls its operation. In addition, the performance control unit 24 monitors for malfunctions in the operation of the movable mechanism based on the detection information from the position detection sensor 82, and if a malfunction occurs, it detects it as an error.

[0087] Furthermore, the performance control unit 24 is connected to the switches for the performance buttons 13, the directional pad 15a, and the select button 15b, which are shown as the operation unit 17 in the figure. In other words, the operation detection switches for the performance buttons 13, the directional pad 15a, and the select button 15b are connected to the performance control unit 24, and the performance control unit 24 is capable of receiving operation detection signals from the performance buttons 13, the directional pad 15a, and the select button 15b, respectively.

[0088] Furthermore, the performance control unit 24 is equipped with a handle sensor 83 (touch sensor) for detecting whether the operating handle 15 shown in Figure 1 is being touched by a user such as a player. Based on the detection information from this handle sensor 83, the performance control unit 24 can determine whether or not the operating handle 15 is being touched by a user.

[0089] The performance control unit 24, based on performance control commands sent from the main control unit 20, selects (determines) a performance pattern from a pre-prepared set of performance patterns either by lottery or uniquely, and controls various performance means at the necessary timing to produce the desired performance. This enables the display of performance images on the liquid crystal display device 36 corresponding to the performance pattern, the playback of sound from the speaker 46, and the operation of the lighting and flashing of decorative lamps 45 and LEDs. Various performance patterns (such as decorative pattern variation display operations and pre-announcement performances) unfold chronologically, realizing a "performance scenario" in a broad sense.

[0090] Here, regarding the performance control command, the performance control unit 24 (CPU 24a) generates an interrupt based on the input of the strobe signal transmitted by the main control unit 20 (CPU 20a) to receive and analyze it. Specifically, the CPU 24a executes a control program for command reception interrupt processing based on the input of the strobe signal, and in the interrupt processing realized thereby, it acquires the performance control command and analyzes the command content. In this case, when an interrupt occurs based on the input of a strobe signal, CPU24a will interrupt the execution of an interrupt process based on another interrupt (a timer interrupt process that is executed periodically) and perform a command reception interrupt process, and will prioritize the command reception interrupt process even if other interrupts occur simultaneously.

[0091] <3. Overview of Operation> [3-1. Symbol Variation Display Game] Next, we will explain the general operation of the gaming machine 1, which is realized by the control configuration described above (Figure 3). First, let me explain the game with changing symbols.

[0092] (Special symbol variation display game) In the gaming machine 1 of this embodiment, a "jackpot lottery" is performed by random number generation in the main control unit 20 based on predetermined starting conditions, specifically, when a game ball enters (wins a prize) into the upper starting port 34 or the lower starting port 35. Based on the lottery result, the main control unit 20 starts a special symbol variation display game by displaying special symbol 1 and special symbol 2 on the special symbol display devices 38a and 38b in a variable manner. After a predetermined time has elapsed, the result is displayed on the special symbol display device, thereby ending the special symbol variation display game.

[0093] In this embodiment, the jackpot lottery based on the ball entering the upper starting opening 34 and the jackpot lottery based on the ball entering the lower starting opening 35 are performed separately and independently. For this reason, the jackpot lottery result for the upper starting opening 34 is derived on the special symbol display device 38a side, and the jackpot lottery result for the lower starting opening 35 is derived on the special symbol display device 38b side. Specifically, on the special symbol display device 38a side, the first special symbol variation display game is started by displaying special symbol 1 in a variation manner when a game ball enters the upper starting opening 34, while on the special symbol display device 38b side, the second special symbol variation display game is started by displaying special symbol 2 in a variation manner when a game ball enters the lower starting opening 35. Then, when the special symbol variation display game is started on the special symbol display device 38a or the special symbol display device 38b, after a predetermined variation display time has elapsed, the special symbols that were being displayed in the variation display stop in a predetermined "jackpot" manner if the jackpot lottery result is "jackpot", or in a predetermined "miss" manner otherwise, and the game result (jackpot lottery result) is derived from this.

[0094] In this specification, for the sake of explanation, the first special symbol variation display game on the special symbol display device 38a side will be referred to as "Special Symbol Variation Display Game 1," and the second special symbol variation display game on the special symbol display device 38b side will be referred to as "Special Symbol Variation Display Game 2." Unless otherwise necessary, "Special Symbol 1" and "Special Symbol 2" will simply be referred to as "Special Symbol" (or abbreviated as "Special Symbol" in some cases), and "Special Symbol Variation Display Game 1" and "Special Symbol Variation Display Game 2" will simply be referred to as "Special Symbol Variation Display Game."

[0095] (A game where decorative patterns change) Furthermore, when the aforementioned special symbol variation display game is started, the decorative symbol variation display game is started by displaying decorative symbols (theatrical game symbols) in a variation manner on the main LCD display device 36M, and various effects are unfolded in conjunction with this. When the special symbol variation display game ends, the decorative symbol variation display game also ends, and a predetermined special symbol indicating the jackpot lottery result is displayed on the special symbol display device, and a decorative symbol reflecting the jackpot lottery result is displayed on the main LCD display device 36M. In other words, the theatrical decorative symbol variation display game, which includes the operation of displaying the variation of decorative symbols, reflects and displays the result of the special symbol variation display game.

[0096] Therefore, for example, if the result of the special symbol variation display game is a "jackpot" (if the jackpot lottery result is a "jackpot"), the decorative symbol variation display game will feature a performance that reflects that result. When the special symbol display device stops displaying a special symbol in a display mode indicating a jackpot (for example, the 7-segment display shows "7"), the main liquid crystal display device 36M stops displaying the decorative symbols in the "left," "center," and "right" display areas in a display mode that reflects a "jackpot" (for example, in the "left," "center," and "right" display areas, the three decorative symbols show "7," "7," and "7").

[0097] When a "jackpot" occurs, specifically, the special symbol variation display game ends, followed by the decorative symbol variation display game, and as a result, the "jackpot" symbol pattern is displayed. Then, the large prize slot solenoid 52c of the special variation prize device 52 activates, causing the opening door 52b to open and close in a predetermined pattern. This opens and closes the large prize slot 50, resulting in a special game state (jackpot game) that is more advantageous to the player than the normal game state. In this jackpot game, the opening door 52b keeps the large prize winning area open or expanded until a predetermined time (maximum opening time: for example, 29.8 seconds) has elapsed, or until the number of game balls that have entered the large prize winning area (the number of balls that have entered the large prize winning area 50) reaches a predetermined number (maximum number of balls that have entered: for example, 9 balls). Once either of these conditions is met, the large prize winning area is closed. This "round game" is repeated for a predetermined number of rounds (for example, a maximum of 16 rounds).

[0098] When the above-mentioned jackpot game begins, an opening sequence is played to announce that a jackpot has started. After the opening sequence ends, rounds of gameplay are played multiple times, up to a predetermined number of rounds. After the predetermined number of rounds is completed, an ending sequence is played to announce that the jackpot has ended, and the jackpot game concludes.

[0099] Regarding the information necessary to execute the above-mentioned decorative pattern variation display game, the main control unit 20 first performs a jackpot lottery based on the fact that a game ball has entered (won) the upper start port 34 or the lower start port 35, specifically, based on the fact that the game ball has been detected by the upper start port sensor 34a or the lower start port sensor 35a and the start condition (start condition related to special patterns) has been met, which includes a 'win / lose lottery (win / lose type lottery)' to determine whether it is a "jackpot" or a "miss", and a 'pattern lottery (winning type (winning pattern type) lottery)' to determine the type of jackpot if it is a "jackpot", and the type of miss if it is a "miss" (if there is only one type of miss, it is not necessary to perform a type lottery for the miss, so that lottery may be omitted), and based on the lottery result information, it determines the variation pattern of the special patterns and the special patterns to be displayed at the end according to the winning type (hereinafter referred to as "special stop patterns"). The main control unit 20 then sends a "variation pattern specification command" to the performance control unit 24 as a performance control command to identify the processing state, which includes at least information on the variation pattern of special symbols (for example, information on the jackpot lottery result and the variation time of the special symbols). This sends the basic information necessary for the decorative symbol variation display game to the performance control unit 24. In this embodiment, in order to provide a wide variety of performances, a "decorative symbol specification command" including information on special stop symbols (symbol lottery result information (information on the type of win)) is also sent to the performance control unit 24.

[0100] The variable pattern information of the special symbol can include information specifying the occurrence of a specific pre-announcement effect (for example, the "reach effect" or "pseudo-consecutive effect" described later). Specifically, the variable pattern of the special symbol is roughly classified into a "winning variable pattern" in the case of a win and a "losing variable pattern" in the case of a loss according to the jackpot lottery result. These variable patterns include, for example, a "reach variable pattern" that designates the occurrence of the reach effect described later, a "normal variable pattern" that does not designate the occurrence of the reach effect, a "pseudo-consecutive with reach variable pattern" that designates the occurrence of both the pseudo-consecutive effect and the reach effect (duplicate occurrence), a "pseudo-consecutive with normal variable pattern" that designates the occurrence of the pseudo-consecutive effect and does not designate the occurrence of the reach effect, and other multiple types of variable patterns. In view of ensuring the performance time of the reach effect and the pseudo-consecutive effect, usually, the variable patterns that designate the reach effect and the pseudo-consecutive effect are defined to have a longer variable time than the normal variable pattern.

[0101] Based on the information included in the effect control commands (here, the variable pattern designation command and the decorative symbol designation command) sent from the main control unit 20, the effect control unit 24 determines the effect content (effect scenario such as a pre-announcement effect) to be developed in chronological order during the decorative symbol variable display game and the decorative symbol (decorative stop symbol) to be finally stopped and displayed, and executes the decorative symbol variable display game by variably displaying the decorative symbol according to the time schedule based on the variable pattern of the special symbol. As a result, in synchronization with the variable display of the special symbol by the special symbol display devices 38a and 38b, the decorative symbol is variably displayed by the main liquid crystal display device 36M, and the period of the special symbol variable display game and the period during the decorative symbol variable display game have substantially the same time width. Further, the effect control unit 24 controls the main liquid crystal display device 36M, the light display device 45a, or the sound generation device 46a respectively so as to correspond to the effect scenario, and develops various effects in the decorative symbol variable display game. Thereby, the reproduction of the image (image effect) on the main liquid crystal display device 36M, the reproduction of the sound effect (sound effect), and the lighting and blinking drive of the decorative lamp 45, the LED, etc. (light effect) are realized.

[0102] Thus, the special symbol variation display game and the decorative symbol variation display game are inseparably related, and the results of the special symbol variation display game are reflected in the representations in the decorative symbol variation display game. Therefore, these two symbol variation display games can be considered equivalent symbol games. In this specification, unless otherwise necessary, the above two symbol variation display games may be simply referred to as "symbol variation display games."

[0103] (Normal symbol variation display game) In addition, in the gaming machine 1, based on the fact that a game ball has passed through (entered) the regular symbol starting opening 37, the main control unit 20 performs an "auxiliary win lottery" by random number drawing. Based on the result of this lottery, the regular symbols represented by LEDs are displayed in a variable manner on the regular symbol display device 39a to start the regular symbol variable display game, and after a certain period of time has elapsed, the result is displayed by stopping the LEDs in a combination of lit and unlit states. For example, if the result of the regular symbol variable display game is an "auxiliary win", the display unit of the regular symbol display device 39a is stopped to display a specific lighting state (for example, both LEDs 39 are lit, or the LED representing "○" among the LEDs representing "○" and "×" is lit).

[0104] When this "auxiliary win" occurs, the ordinary electric mechanism solenoid 41c (see Figure 3) is activated, causing the movable blade 47 to open in an inverted "V" shape, opening or expanding the lower start opening 35, making it easier for game balls to flow in (start opening state), resulting in an auxiliary game state (hereinafter referred to as "ordinary electric opening game") that is more advantageous to the player than the normal game state. In this ordinary electric opening game, the movable blade 47 of the ordinary variable prize winning device 41 opens or expands the prize winning area of ​​the lower start opening 35 until the opening time of the lower start opening 35 has elapsed for a predetermined time (for example, 0.2 seconds) or until the number of game balls that have entered the lower start opening 35 reaches a predetermined number (for example, 4 balls), and when either of these conditions is met, the lower start opening 35 is closed. This operation is repeated a predetermined number of times (for example, up to 2 times).

[0105] (Regarding the hold) In this embodiment, during a special / decorative symbol variation display game, a normal symbol variation display game, a jackpot game, or a normal power release game, if a ball enters the upper start port 34, lower start port 35, or normal symbol start port 37, that is, if a detection signal is input from the upper start port sensor 34a, lower start port sensor 35a, or normal symbol start port sensor 37a, and the corresponding start condition (symbol game start condition) is met, this is stored as data relating to the right to start the variation display game, up to a predetermined upper limit of the maximum number of reserved balls (for example, a maximum of 4), excluding those related to the variation display. Reserved data that is not used for the symbol variation display operation, or the game balls related to such reserved data, are also called "operated reserved balls." To make the number of these operated reserved balls clear to the player, a dedicated reserved ball indicator (not shown) is provided in an appropriate place on the game machine 1, or a reserved ball indicator provided as an icon image on the screen of the liquid crystal display device 36 (main liquid crystal display device 36M or sub-liquid crystal display device 36S) is lit up.

[0106] In this embodiment, up to four operational reserve balls for each of the special symbols 1, special symbol 2, and normal symbols are reserved and stored in the corresponding memory area of ​​the RAM 20c, and are reserved as the number of times the special symbol or normal symbol variation is confirmed. There is no particular limit on the maximum number of operational reserve balls that can be stored for each of the special symbols 1, special symbol 2, and normal symbols (maximum number of reserved balls). Furthermore, all or part of the maximum number of reserved balls for each symbol may be different, and the number can be appropriately determined according to the gameplay.

[0107] [3-2. Game Status] In the gaming machine 1 according to this embodiment, in addition to the special game state of a big win, it is configured to generate multiple types of game states. To facilitate understanding of this embodiment, the various game states will be explained first.

[0108] The gaming machine 1 of this embodiment is configured to execute and control at least four types of game states: normal state, time-saving state, hidden probability state, and probability variation state. These game states are distinguished by the presence or absence of the jackpot lottery probability state (low probability state, high probability state) and the electric reel support state (bonus game) (with electric support, without electric support), etc.

[0109] "Electric tuner support state" refers to the "extended opening state" in which the opening period of the movable wing piece 47 of the normal variable prize winning device 41 in normal electric opening game (at least one of the opening time of the movable wing piece 47 and the number of times it opens) is extended compared to the normal state. When the extended opening state occurs, the opening period of the movable wing piece 47 is extended, for example, from 0.2 seconds in the normal state (under the non-extended opening state) to 1.7 seconds, and the number of times it opens and closes is extended, for example, from 1 time in the normal state to 2 to 3 times. In this embodiment, under the electric reel support state, the auxiliary winning lottery probability changes from a low probability (e.g., 1 in 256) to a high probability (e.g., 255 in 256) of a predetermined probability (normal probability), resulting in a 'normal symbol probability change state'. At the same time, a 'normal symbol time reduction state' occurs, which shortens the average time required for one normal symbol change display game (normal symbol change display operation time) (for example, shortened from 10 seconds to 1 second). Therefore, when the electric reel support state occurs, normal electric reel opening games occur frequently, resulting in an improved operating rate state (high base state) in which the operating rate of the movable wing piece 47 per unit time is higher than in the normal state. Hereinafter, the electric reel support state will be abbreviated as "electric support enabled," and the state without electric support will be abbreviated as "electric support disabled."

[0110] In this embodiment, "normal state" refers to a game state where the probability of winning a jackpot is a low probability (for example, 1 in 399) of a predetermined probability (normal probability), and there is no electric support (low probability + no electric support).

[0111] "Shortened playtime" refers to a game state where the probability of winning a jackpot is the same low probability as in the normal state, but the average time required for one special symbol variation display game (the operation time of the special symbol variation display) is shortened compared to the normal state, and the electric reel support state is also activated. In other words, during the shortened playtime, it is "low probability + electric support + special symbol shortened playtime".

[0112] "Hidden probability state" refers to a 'special symbol probability change state' where the probability of winning a jackpot has increased from the low probability mentioned above to a high probability (for example, 1 in 39.9), and it is a game state without electric support (high probability + no electric support).

[0113] "Probability variation state" refers to a game state where the probability of winning a jackpot is as high as in the hidden probability state, but a special symbol time reduction state and an electric reel support state occur. In other words, during the probability variation state, it is "high probability + electric support + special symbol time reduction state".

[0114] Regarding the game state, focusing on the probability of winning a jackpot, if the game state is "normal state" or "time-saving state," the probability of winning a jackpot will be at least at a 'low probability state,' and if the game state is "hidden probability state" or "probability change state," the probability of winning a jackpot will be at least at a 'high probability state.' During a jackpot, a jackpot game occurs in which the large prize slot opens and closes, but the probability of winning a jackpot and the presence or absence of electric support remain the same as in the normal state described above, under a low probability and no electric support game state.

[0115] [3-3. Regarding the hit] Next, we will explain what constitutes a "win" in gaming machine 1. In the gaming machine 1 of this embodiment, a jackpot lottery (winning lottery) is conducted for multiple types of wins. In this example, the types of wins include jackpots belonging to the jackpot types, such as "Normal 4R", "Normal 6R", "Probability Change 6R", and "Probability Change 10R". The "R" notation above indicates the number of rounds (maximum number of rounds).

[0116] The type of jackpot is the win that triggers the activation of the conditional device. Here, the "conditional device" refers to a device whose activation is a condition required for the continuous activation of the mechanism that allows for round play, and which is activated when a specific combination of special symbols is displayed or when a game ball passes through a specific area within the jackpot entry point.

[0117] The above-mentioned probability variation state is a so-called "count-limited probability variation machine (ST machine)" where, if the number of executions of the special symbol variation display game ends after a predetermined number of times (for example, 70 times: prescribed ST count) without winning a jackpot of any type, the high probability state ends and the machine transitions to a low probability state. When the prescribed ST count ends, the machine transitions to the normal state from the next game. However, it may also be a "general probability variation machine" that continues until the next jackpot is won. Furthermore, the number of times the special symbol variation display game is executed may be the total number of executions of special symbol variation display game 1 and special symbol variation display game 2 (total number of variations for special symbol 1 and special symbol 2), or it may be the number of executions of either one (for example, the number of executions of special symbol variation display game 2). Also, the number of times the time-saving state is not limited to 60 or 100, but can be determined as appropriate according to the gameplay. In addition, there are no particular restrictions on the types of wins to be provided, and they can be determined as appropriate.

[0118] In this example, just like with the types of big wins, there are also multiple types of "misses." Specifically, there are three types of misses: "miss 1," "miss 2," and "miss 3." As mentioned above, if the result of the initial draw is a "loser," a draw for the losing type will be conducted in the subsequent design draw.

[0119] [3-4. Regarding the direction / staging] (Performance Mode) Next, the performance modes (performance states) will be explained. The gaming machine 1 of this embodiment is provided with multiple performance modes for displaying performances related to the game state, and is configured to allow switching between these performance modes. Specifically, there are normal performance modes, time-saving performance modes, hidden probability performance modes, and probability variation performance modes, corresponding to the normal state, time-saving state, hidden probability state, and probability variation state, respectively. In each performance mode, the background display, which serves as the background for the display screen of the changing decorative symbols, is displayed with different background performances, allowing the player to understand what game state they are currently in.

[0120] The performance control unit 24 (CPU 24a) has a function unit (performance state transition control means) that controls transitions between multiple types of performance modes. Based on specific performance control commands sent from the main control unit 20 (CPU 20a), specifically performance control commands that include game state information managed by the main control unit 20, the performance control unit 24 (CPU 24a) grasps the current game state in a manner consistent with the game state managed by the main control unit 20, and is configured to control transitions between multiple types of performance modes. Examples of such specific performance control commands include a variation pattern specification command, a decorative symbol specification command, and a game state specification command sent when a change occurs in the game state.

[0121] (Preview / Preview) Next, the pre-announcement effects will be explained. The effects control unit 24 is configured to be able to control the appearance of various "pre-announcement effects" related to the current effects mode and the jackpot lottery result, based on the content of the effects control commands from the main control unit 20, specifically, the variation pattern information included in at least the variation pattern specification command. Such pre-announcement effects suggest (predict) the expected probability of winning a jackpot type (hereinafter referred to as "winning probability") and act as "hype effects" to heighten the player's expectation of winning. Typical pre-announcement effects include "reach effects," "pseudo-consecutive effects," and "pre-read pre-announcement effects." The effects control unit 24 functions as a pre-announcement effect control means capable of controlling the execution (appearance) of these effects.

[0122] A "reach animation" refers to an animation pattern that involves a reach state (a variation display pattern that involves a reach state: a reach variation pattern), and specifically refers to an animation pattern that leads to and displays the final game result via a reach state. Reach animations include multiple types of reach animations associated with the probability of winning. For example, there are some that have a relatively higher probability of winning compared to when a normal reach animation appears. Such reach animations are called "super reach animations." Many of these "super reaches" have a relatively longer animation time (variation time) than normal reaches in order to heighten the expectation of winning. Also, normal reaches and super reaches include multiple types of reach animations. In this example, super reaches include multiple types of reach animations called super reach 1, 2, 3, and 4, and the probability of winning for these super reaches 1 to 4 is given the relationship "super reach 1 < super reach 2 < super reach 3 < super reach 4".

[0123] "Pseudo-consecutive display" refers to a display method that involves a pseudo-continuous display state of decorative symbols (pseudo-consecutive display). "Pseudo-consecutive display" refers to a display method in which, during a game of displaying decorative symbols, some or all of the decorative symbols are temporarily stopped, and then the display operation of the decorative symbols is performed again from that temporarily stopped state, and this display operation is repeated once or multiple times. In this respect, it differs from the "pre-announcement display (continuous announcement display)" described later, which unfolds across multiple games of displaying symbols. The occurrence rate (appearance rate) of such "pseudo-consecutive" is basically set so that the probability of winning increases as the number of pseudo-displays increases. For example, depending on the number of pseudo-displays, displays that heighten the sense of anticipation, such as super reach, are more likely to be selected.

[0124] A "pre-announcement effect" (hereinafter sometimes abbreviated as "pre-announcement" or "pre-announcement effect") refers to an effect that, based on the result of a pre-announcement judgment, notifies the player of the possibility of being controlled to a favorable state before the change in the target symbol is displayed. A "favorable state" refers to a state that is advantageous to the player. Specifically, the preview effect in this example mainly uses the holding display mode and the background effects of the symbol variation display game (special symbol variation display operation) that has not been executed yet for the holding balls that have not been used in the symbol variation display game (undigested holding balls), and is performed in an effect mode that can notify the winning probability in advance before the holding balls are used in the symbol variation display game. In the symbol variation display game, in addition to the above "reach effect", various effects such as the so-called "SU (step-up) preview effect", "timer preview effect", "revival effect", and "premium preview effect" occur to enliven the game content.

[0125] Here, referring to FIG. 4, the "holding change preview effect" as an example of the above preview effect will be described. In the case of the gaming machine 1 of this embodiment, in the upper display area within the screen of the main liquid crystal display device 36M, a display area (display area for displaying the symbol variation display effect and preview effect of the decorative symbol) for presenting the decorative symbol variation display game is provided, and in the lower display area within the screen, a holding display area 76 (holding display portions a1 to d1) for displaying the number of holding balls on the special symbol 1 side and a holding display area 77 (holding display portions a2 to d2) for displaying the number of holding balls on the special symbol 2 side are provided. Regarding the presence or absence of the holding balls, that fact is notified by a predetermined holding display mode. In FIG. 4, an example is shown in which information regarding the current number of holding balls is notified in a lit state (there are holding balls: "○ (white circle)" shown in the figure) or an unlit state (no holding balls: broken-line circle shown in the figure).

[0126] The display regarding the presence or absence of active reserved balls (reserved ball display) is displayed sequentially in the order of their occurrence (order of winning), and in each reserved ball display area 76, 77, the leftmost active reserved ball is displayed as the first active reserved ball to occur on the time axis (i.e., the oldest) among all active reserved balls in that reserved ball display. In addition, a variable display area 78 is provided to the left of the reserved ball display areas 76, 77 to show the active reserved balls currently being used in the special symbol variation display game. In this embodiment, the variable display area 78 is configured so that an image appears in which the icon of the game-running reserved ball K currently being used in the game is placed on the icon of the receiving seat J. That is, when the variation display of special symbol 1 or special symbol 2 starts, the icon (icon image) of the oldest reserved ball a1 or a2 that was displayed in the reserved ball display areas 76, 77 moves to the icon of the receiving seat J in the variable display area 78 as the icon of the game-running reserved ball K, and this state is maintained for a predetermined display time.

[0127] If a reserved ball is generated, the main control unit 20 sends a "reserved ball addition command" to the performance control unit 24, which specifies the pre-read judgment information related to the jackpot lottery result and the number of reserved balls at the time of the pre-read judgment (the number of reserved balls currently in existence, including the reserved ball generated this time) (see steps S1309 to S1312 in Figure 28). In this embodiment, the hold-add command consists of two bytes: the upper byte data that allows for the identification of the number of balls to be held in operation at the time of the pre-read determination, and the lower byte data that allows for the identification of the pre-read determination information.

[0128] As can be understood from the above explanation, in this embodiment, based on the occurrence of a winning ball in the upper starting port 34 or the lower starting port 35 and the creation of a new reserved ball, a jackpot lottery is performed for the symbol variation display game related to the reserved ball as a pre-read determination. As will be described later, the main control unit 20 stores information representing the result of the jackpot lottery performed as such a pre-read determination in the corresponding memory area of ​​the RAM 20c. The information obtained during the pre-read determination of the jackpot lottery results is used to select (draw) a symbol variation pattern in the symbol variation display game, and can be rephrased as "variation pattern selection information." Therefore, it can be said that the main control unit 20 performs a pre-read determination and stores the resulting "variation pattern selection information" in a predetermined area of ​​the RAM 20c.

[0129] When the performance control unit 24 receives the above-mentioned hold-add command transmitted by the main control unit 20, it performs performance control processing related to the "pre-announcement performance" as part of the display control processing related to the hold display, based on the pre-announcement judgment information contained therein. Specifically, it performs a "pre-announcement lottery" to determine whether or not the pre-announcement performance can be executed, and if it wins, it displays the pre-announcement performance.

[0130] Here, the pre-read judgment information specifically refers to game information obtained by the main control unit 20 by pre-reading the jackpot lottery result (jackpot lottery result at the start of the variation) and the variation pattern at the start of the variation when the operating reserve ball is used in the symbol variation display game. In other words, this information includes at least information obtained by pre-reading the win / loss lottery result at the start of the variation (pre-read win / loss information), and can also include information obtained by pre-reading the symbol lottery result (pre-read symbol information) and information obtained by pre-reading the variation pattern at the start of the variation (pre-read variation pattern information). The information to be included in the reserve addition command sent to the performance control unit 24 can be appropriately determined according to the content to be announced in the pre-read notification. In this example, the hold-add command is assumed to include pre-read win / loss information, pre-read symbol information, and pre-read variation pattern information.

[0131] Furthermore, the "pre-read variation pattern" obtained by the pre-read judgment when the activated reserve ball is generated does not necessarily have to be the same as the "variation pattern at the start of variation" obtained when the activated reserve ball is actually used for variation display operation. For example, if we take the case where the variation pattern at the start of variation is a variation pattern that specifies "Super Reach 1" as a representative example, in this case, the content specified by the pre-read variation pattern can be specified not as the type of reach effect "Super Reach 1" itself, but as the core "Super Reach type".

[0132] In this embodiment, if the pre-announcement lottery is won, a "hold display change type" pre-announcement effect (also referred to as "hold change announcement") is performed, in which the hold icon that is the target of the pre-announcement among the hold icons in the hold display units a1~d1 and a2~d2 may change from, for example, the white of the normal hold display (normal hold display mode) to the hold display with blue, green, red, danger pattern (or special colors or patterns such as rainbow) of the announcement display (special hold display mode). Figure 4 shows an example where the operating reserve ball in the hatched reserve display section b1 changes to a special reserve display. Here, the blue, green, red, and danger pattern of the reserve icons indicate increasing probability of winning, in that order. In particular, the danger pattern reserve icon is considered a premium reserve icon that indicates an extremely high probability of winning the jackpot.

[0133] (Direction means) Various effects in the gaming machine 1 are produced by effect means installed in the gaming machine 1. These effect means can be any stimulus transmission means that can produce an effect by appealing to human senses such as sight, hearing, and touch. Typical examples include light generating means such as decorative lamps 45 and LED devices (light display devices 45a: light effect means), sound generating devices such as speakers 46 (sound generating devices 46a: sound effect means), effect display devices (display means) such as the main liquid crystal display device 36M and the sub-liquid crystal display device 36S, pressure devices that transmit contact pressure to the operator's body, air pressure devices that apply air pressure to the player's body, and movable parts that produce a visual effect through their operation. Here, effect display devices are display devices that appeal to the sense of sight, just like image display devices, but they differ from image display devices in that they also include those that do not rely on images (for example, 7-segment displays). When referred to as image display devices, it mainly refers to types that produce effects by displaying images, and those that produce effects using means other than images, such as 7-segment displays, are included in the above concept of effect display devices.

[0134] <4. Processing of the main control unit> Next, the processing performed by the main control unit 20 of this embodiment will be described. The processing of the main control unit 20 mainly consists of a predetermined main processing (main control side main processing: Figure 8) and a timer interrupt processing (main control side timer interrupt processing: Figure 20) that is started by a scheduled interrupt from the CTC.

[0135] [4-1. Main control side main processing] Figure 5 is a flowchart showing the main processing on the primary control side. The main control side's main processing is initiated when a system reset occurs due to a system reset signal from the power supply board upon recovery from a power outage or power supply abnormality, or when the control program malfunctions, causing the watchdog timer (WDT) function to activate and the CPU 20a to be forcibly reset (WDT reset). In either case, once the main processing is initiated, the main control unit 20 (CPU 20a) first performs initial setup processing necessary for starting game operation, such as initializing the values ​​of the registers of each part, including the CPU 20a (step S101).

[0136] (Initial setup process) Figure 6 is a flowchart showing the initial setup process in step S101. In Figure 6, when the above-mentioned system reset or WDT reset occurs, CPU 20a sets itself to an interrupt-disabled state in step S201, and then, as a stack pointer setting process in step S202, it executes a process to set the value of the stack pointer of RAM 20c to correspond to the last address of the stack area. Then, in the following step S203, it disables RAM protection and disables the prohibited area in the RAM 20c's function to prevent travel outside the specified area.

[0137] Next, in step S204, the CPU 20a executes a process to turn off the security signal, the setting value display, and the firing permission signal. Here, the security signal is a signal output to the hall computer HC through the frame external centralized terminal board 21, and functions as a signal to notify the hall computer HC of the status, such as that settings are being changed. Turning off the setting value display means turning off the display of the setting value Ve on the setting / performance indicator 97. As mentioned above, the launch permission signal is a signal output from the payout control board 29 to the launch control board 28, and the CPU 20a gives instructions to the payout control board 29 to turn off the launch permission signal. Here, turning off the security signal and setting value display is a measure to prevent power interruptions during setting changes. In other words, since there is a possibility that the power may be cut off while the setting value Ve is being displayed during the setting change process, the setting value display and security signal are temporarily turned off.

[0138] In step S205, following step S204, CPU20a performs a power supply abnormality check process. As shown in Figure 7, the power supply abnormality check process clears the WDT timer (step S11) and determines whether the power supply abnormality signal is ON or OFF (step S12). The power supply abnormality signal is a signal output from the power supply board, where OFF indicates a normal level and ON indicates that the power supply abnormality signal is not at a normal level (i.e., abnormal). If the power supply abnormality signal is ON, the CPU 20a returns to step S101 shown in Figure 5 and restarts the main control side main process from the beginning. In other words, if a power supply abnormality is detected, the main control side main process is reset. If the power supply abnormality signal is not ON, no abnormality is detected in the power supply, and CPU20a finishes the power supply abnormality check process.

[0139] Returning to Figure 6, the CPU 20a, having completed the power supply abnormality check process in step S205, performs various startup setting processes in step S206. In this setting process in step S206, for example, interrupt mode setting processes are executed to set a predetermined interrupt mode, and internal hardware random number setting processes are executed to activate the internal hardware random number circuit. In addition, in this setting process in step S206, initial values ​​are set for predetermined registers among the various registers provided by the CPU 20a.

[0140] In step S207, following step S206, the CPU 20a sets the startup waiting time for the sub-control board (performance control unit 24). Then, through the processing in steps S208 to S210, it waits for the set startup waiting time to elapse. Specifically, the set startup waiting time is deducted by 1 (step S208), a power supply abnormality check is performed (step S209), and if the startup waiting time is not zero (step S210: ≠ 0), the process returns to step S208. Through this waiting process based on the startup waiting time, the startup of the performance control unit 24 is completed.

[0141] In step S210, if the above-mentioned startup waiting time has elapsed (waiting time = 0), the CPU 20a proceeds to step S211 and sends a standby screen display command to the performance control unit 24. Upon receiving this standby screen display command, the performance control unit 24 controls the liquid crystal display device 36 to execute a predetermined screen display that corresponds to startup, such as a screen displaying text such as "Please Wait...".

[0142] In response to the execution of the transmission process in step S211, the CPU 20a proceeds to step S212, and through the processes in steps S212 and S213, it performs a power supply abnormality check process (S212: see Figure 7) while waiting for a power-on signal to be sent from the payout control board 29. This power-on signal is output when the payout control board 29 starts up normally, and the CPU 20a waits until the payout control board 29 starts up normally. As a result, if the payout control board 29 is not functioning normally due to some trouble, the processes in steps S212 and S213 will be repeated and the game operation will not start. Therefore, payout abnormalities such as the failure to pay out prize balls will not occur, thus preventing the player from losing confidence. If the CPU 20a receives the above power-on signal (step S213: ON), it completes the initial setup process in step S101.

[0143] (Processing after initial setup) Having completed the initial setup process described above, CPU20a proceeds to step S102 shown in Figure 5. In step S102, the CPU 20a obtains information about input port n (i.e., a predetermined input port) and copies it to the W register. Here, input port n is assumed to be a 1-byte (8-bit) port, and in this example, the following signals are input. Note that "b0" to "b7" shown below represent bit positions. b0: Setting key (input signal from setting key switch 94) b1: Supply depletion detection signal b2: Counting error signal b3: Disconnection detection signal 1 b4: Disconnection detection signal 2 b5: Door open signal (detection signal from front door open sensor 61) b6: RAM clear button (input signal from RAM clear switch 98) b7: Power-on signal and payout communication confirmation signal Here, for the setting key b0, "0" means setting key switch 94 = OFF, and "1" means setting key switch 94 = ON. Also, for the door open signal b5, "0" means door closed (front frame 2 is closed), and "1" means door open. Furthermore, for the RAM clear button b6, "0" means RAM clear switch 98 = OFF (button not operated), and "1" means RAM clear switch 98 = ON (button operated).

[0144] In step S103, following step S102, the CPU 20a masks the values ​​in the W register. Specifically, it masks all values ​​except the setting key (b0), RAM clear button (b6), and door open signal (b5), which are necessary for determining the transition to the setting change process (S115), RAM clear process (at least S117 and S118), setting confirmation process (S109), and backup restore process (S111) described below. As can be understood from the previous explanation, the conditions for transitioning to the settings change process are that, at startup, the front frame 2 is open and both the settings key and the RAM clear button are in the pressed state. Furthermore, in this example, the conditions for transitioning to the RAM clear process are, in terms of operation, that the setting key is in an idle state and the RAM clear button is in an activated state at startup. Furthermore, the conditions for transitioning to the settings confirmation process are, in terms of operation, that the front frame 2 is open, the setting key is in the activated state, and the RAM clear button is in the deactivated state. Furthermore, the conditions for transitioning to the backup restoration process are, in terms of operation, that both the setting key and the RAM clear button must be in a non-operated state at startup.

[0145] Figure 8 shows the correspondence between the operational judgment conditions for transitioning to these configuration change, RAM clear, configuration confirmation, and backup restoration processes, and the values ​​of the W register. Figure 8 shows the order of the transition decisions for the configuration change process, RAM clear process, configuration confirmation process, and backup restore process. The determination for transitioning to the first setting change process is as shown in the diagram, with the conditions being setting key: ON (setting key switch 94: ON), door open: ON (front door open sensor 61: ON), and RAM clear switch 98: ON. Therefore, the conditions for the W register values ​​are bit 0: 1, bit 5: 1, and bit 6: 1. The second step, determining whether to proceed to the RAM clear process, is based on the condition that the RAM clear switch 98 is ON and that the value of the 6th bit in the W register is 1. In this example, the determination to proceed to the RAM clear process is executed when the conditions for proceeding to the setting change process are not met. Furthermore, the condition for proceeding to the setting confirmation process and the backup restore process is that the RAM clear switch 98 is OFF. From these points, if the conditions for proceeding to the setting change process are not met and the RAM clear switch 98 is ON, it can be inferred that the operation to proceed to the RAM clear process has been performed. For this reason, in this example, the determination to proceed to the RAM clear process, as described above, only determines whether the RAM clear switch 98 is ON (whether the 6th bit is 1 or not) in terms of operation.

[0146] The determination to proceed to the third setting confirmation process is based on the following conditions: setting key: ON, door open: ON, RAM clear switch 98: OFF. Therefore, the values ​​of the W register must be 1 for the 0th bit, 1 for the 5th bit, and 0 for the 6th bit. Furthermore, the determination for transitioning to the fourth backup restore process is based on the conditions that the setting key is OFF and the RAM clear switch 98 is OFF. Therefore, the values ​​of the W register must be 0 for the 0th bit and 0 for the 6th bit.

[0147] Here, regarding the backup restore process, the transition conditions for performing only the backup restore process without going through the setting confirmation process can be expressed as setting key: OFF and RAM clear switch 98: OFF in terms of operation, as described above. However, the condition for transitioning to a state where only the backup restore process is performed, regardless of whether the setting confirmation process is executed or not, is that the backup flag, which will be described later, is ON (see the determination process in step S106).

[0148] Return to the explanation in Figure 5. In response to the masking process performed in step S103, CPU 20a executes a setting change condition determination process in step S104. Specifically, in order to determine whether or not to transition to setting change mode, it checks whether the value (3 bits) after masking in step S103 is "111". If the value after masking is "111" and a positive result is obtained indicating that the setting change condition is met, the CPU 20a executes the setting change process in step S115. That is, it performs the process to set a new setting value Ve in response to the operation of the RAM clear button or setting key. Further details regarding the setting change process in step S115 will be explained later.

[0149] In this embodiment, as described above, the detection signals from the setting key switch 94, the front door open sensor 61, and the RAM clear switch 98—in other words, the detection signals used to determine the transition to the setting change mode—are input to the same input port of the main control unit 20, and it is determined collectively whether the values ​​of each input detection signal satisfy predetermined conditions. This reduces the number of determination processes required to determine whether to switch to the setting change mode, compared to individually determining whether the value of each detection signal satisfies predetermined conditions.

[0150] In response to the execution of the setting change process in step S115, the CPU 20a executes a RAM clear process in step S116. This RAM clear process includes initializing the values ​​in a predetermined area (used area) including the work area in RAM 20c, and sending a setting change completion command to notify the performance control unit 24 of the completion of the setting change process executed in step S115, but the details will be described later.

[0151] Next, in step S104, if the value after masking in step S103 is not "111" and a negative result is obtained indicating that the setting change condition is not met, the CPU 20a proceeds to step S105 to determine whether or not there is a RAM abnormality. Specifically, it determines whether or not the "setting value" stored in the work area of ​​RAM 20c is a value outside the usage range Ru (outside the range of "1", "2", and "6" in this example). Here, the value that the CPU 20a handles in relation to the setting value Ve is the setting value Vd. The setting value Vd is a value corresponding to the setting value Ve, and in this example it is a 1-byte value, with values ​​from 00H (0) to 02H (3) defined so that it can represent at least three levels corresponding to the usage range Ru mentioned above. Note that "H" means hexadecimal (the same applies below). In this example, setting value Vd=00H represents setting value Ve="1", setting value Vd=01H represents setting value Ve="2", and setting value Vd=02H represents setting value Ve="6". In the main control unit 20, the setting value Vd is mainly handled as the "setting value", and this setting value Vd is stored in the "setting value" storage area in the work area of ​​the RAM 20c of the main control unit 20. In the determination process of step S105, it is determined whether the set value Vd stored in the work area is within the range of 00H to 02H.

[0152] In step S105, if the set value is outside the above-mentioned usage range Ru (i.e., outside the normal range) and it is determined that there is a RAM abnormality, the CPU 20a proceeds to the process of waiting for a power-on restart, which continues from step S112 onwards. Specifically, in step S112, the CPU 20a sends a performance control command (setting change waiting command) to the performance control unit 24 as a command transmission process when the power is turned on. This command instructs the power of the pachinko game machine 1 to be turned on and a notification prompting a setting change to be issued. If a RAM abnormality is detected at startup, the system is forcibly switched to setting change mode to accept a change (setting) of the setting value Ve. For this reason, in step S112, the CPU 20a first notifies the performance control unit 24 that it will switch to setting change mode using the setting change waiting command. Upon receiving the setting change waiting command, the performance control unit 24 causes the liquid crystal display device 36 to display a screen prompting the user to change the settings, such as a screen containing text like "Open the door and change the settings." At this time, the performance control unit 24 may also perform control to display corresponding light effects (for example, lighting up all LEDs on the light display device 45a) or sound effects along with the screen display.

[0153] In step S113, following step S112, the CPU 20a sets the backup flag to 00H (i.e., OFF) and then repeats the error display process in step S114. In this error display process in step S114, processing is performed to cause the setting / performance indicator 97 to display an error. This error display process is repeated until the power to the pachinko machine 1 is cut off, and when the power is restored, the processing from step S101 onwards is executed again as the main control side main processing. At this time, if the operation to transition to setting change mode has been performed according to the above screen display, the system will transition to setting change mode and the RAM abnormal state will be resolved.

[0154] In step S105 described above, if it is determined that the set value is not outside the usable range Ru and that there is no RAM abnormality, the CPU 20a proceeds to step S106 to determine whether the backup flag is ON or not (in this example, the backup flag = 5AH is ON). In the gaming machine 1, when the power is cut off, the power check and backup process (step S901, see Figure 19) described later in the main control timer interrupt processing is used to back up the information stored in RAM 20c. If the backup process is performed correctly when the power is cut off, the backup flag is set to the ON state (see step S1010 in Figure 19). Therefore, in step S106, the backup flag is checked to determine whether or not backup restoration is possible. Specifically, in step S106, it is determined whether or not the backup flag stored in a predetermined area of ​​RAM 20c is in the ON state (5AH).

[0155] If step S106 determines that the backup flag is not ON, the CPU 20a proceeds to step S112 as described above. If the backup recovery conditions are not met, the system is forcibly switched to configuration change mode, similar to the case where a RAM abnormality is detected as explained earlier.

[0156] As mentioned above, the determination process in step S106 is equivalent to a process that determines whether or not the system can transition to a state where the backup restoration process is performed, regardless of whether or not the setting confirmation process is executed.

[0157] On the other hand, if the backup flag is determined to be ON in step S106, the CPU 20a determines in step S107 whether the RAM clear condition (condition for transitioning to the RAM clear process) is met. Specifically, it determines whether the value of the 6th bit of the W register is "1". If the value of the 6th bit of the W register is "1", and a positive result is obtained indicating that the RAM clear condition is met, the CPU 20a proceeds to step S116 described above. This executes the RAM clear process described above.

[0158] As can be seen by referring to the route from step S107 to S116 described above, in the gaming machine 1 of this embodiment, it is possible to clear the RAM without changing the settings. This makes it possible to clear data other than data related to the setting value Ve, such as payout-related data in RAM 20c.

[0159] Furthermore, if step S107 yields a negative result indicating that the RAM clear condition is not met, since the value of the 6th bit of the W register is not "1", the CPU 20a proceeds to step S108 to determine whether the setting confirmation condition (condition for transitioning to the setting confirmation process) is met. That is, it determines whether the value of the W register after masking in step S103 is "110". If the value of the W register after masking is "110" and a positive result is obtained indicating that the setting confirmation condition is met, the CPU 20a executes the setting confirmation process in step S109 and proceeds to step S110. That is, it moves on to the process for restoring the backup. Further details regarding the setting confirmation process in step S109 will be explained separately.

[0160] On the other hand, if the value of the W register after masking is not "110" and a negative result is obtained indicating that the setting confirmation condition is not met, the CPU 20a skips the setting confirmation process in step S109 and proceeds to step S110.

[0161] In step S110, the CPU 20a performs a process to send a predetermined performance control command corresponding to the backup restoration to the performance control unit 24 as a command transmission process during backup restoration.

[0162] In step S111, following step S110, CPU 20a performs a backup and restore process. The backup restore process is a process that restores the operation to what it was like before the power was cut off, based on the contents of RAM20c that were backed up when the power was cut off. Specifically, CPU20a restores the stack pointer from before the power was cut off and performs the process to start the game operation from the processing state at the time of the power cut off. Furthermore, in the backup restoration process, in order to ensure that a power outage restoration display command (OB03H) for issuing an information display instruction corresponding to the backup restoration is sent to the performance control unit 24 in the main loop preprocessing of step S119 described later, the lower byte data of the power outage restoration display command is stored in a register.

[0163] If the backup restoration process in step S111 is executed, or if the RAM clear process in step S116 described above is executed (i.e., if both the configuration change process and the RAM clear process are executed, or if only the RAM clear process is executed), the CPU 20a proceeds with the process in step S117.

[0164] In step S117, the CPU 20a sets up the CTC to periodically generate timer interrupts at predetermined intervals, such as 4ms. Once the setting process in step S117 is completed, interrupt request signals are periodically output to the interrupt controller, and the main control side timer interrupt processing is executed.

[0165] In the following step S118, the CPU 20a sends a performance control command to the performance control unit 24 to instruct the start of the game. Then, the process proceeds to step S119 to perform pre-main loop processing, and then the main loop processing in step S120 is performed. The main loop preprocessing in step S119 will be explained in more detail later.

[0166] (Main loop processing) Figure 9 is a flowchart showing the main loop processing in step S120. In the main loop processing shown in Figure 9, CPU 20a sets itself to an interrupt-disabled state in step S601, and then executes a random number update process in the following step S602. This random number update process updates the random numbers used to change the initial values ​​(start values) of various random numbers used in the special symbol variation display game and the normal symbol variation display game (random numbers related to the jackpot lottery that cycle through a predetermined numerical range by an increment process (random numbers for determining special symbols used in the symbol lottery) and random numbers related to the auxiliary win lottery (random numbers for determining auxiliary wins used in the lottery for determining whether auxiliary wins are won or lost) (initial random numbers for determining special symbols, initial random numbers for determining auxiliary wins), as well as the random numbers used for selecting variation patterns.

[0167] In this embodiment, the RAM 20c is provided with various random number counters used for symbol lottery, auxiliary win lottery, or variable pattern lottery related to the jackpot lottery, such as a counter for generating the initial value of the special symbol determination random number counter, a special symbol determination random number counter, a counter for generating the initial value of the auxiliary win determination random number counter, an auxiliary win determination random number counter, and a variable pattern random number counter. These counters serve as random number generation means for generating random numbers in software. In the random number update process of step S602, the above-mentioned two initial value generation counters that generate the initial values ​​of the special symbol determination random number counter and the auxiliary win determination random number counter, the variable pattern random number counter, etc. are updated to generate the above-mentioned various software random numbers. For example, if the numerical range that can be taken as the variable pattern random number counter is "0 to 238", a value is obtained from the count value storage area for generating the variable pattern random number value in RAM 20c, "1" is added to the obtained value, and then it is stored in the original count value storage area. At this point, if adding "1" to the acquired value results in "239", then "0" is stored in the original random number counter memory. Other random number counters used for generating initial values ​​are updated in the same manner.

[0168] After completing the random number update process in step S602, CPU 20a performs the process of saving the values ​​of all registers in step S603, and then performs the performance display monitor aggregate division process in step S604. This performance display monitor aggregation division process is a process that calculates the values ​​of the performance information mentioned above (here, for example, the values ​​of the "normal ratio information" mentioned above). As mentioned above, the value of the normal ratio information is calculated using the total number of balls dispensed and the total number of balls that go out. CPU 20a calculates the total number of balls dispensed based on the result of counting the number of game balls that entered the prize winning slots (upper starting slot 34, lower starting slot 35, general prize winning slot 43, large prize winning slot 50), and the total number of balls that go out is obtained by counting the number of game balls that were discharged from the out slot 49. The count of winning balls and the count of out balls are performed in the input management process described later in the main control side timer interrupt processing (see step S904 in Figure 18). Based on the count values ​​obtained from the count of winning balls and the count of out balls performed on the timer interrupt processing side, the CPU 20a calculates a value as normal ratio information in step S604. As described above, the calculated value as normal ratio information is stored in a predetermined area (measurement information storage area) of the RAM 20c. The normal ratio information values ​​calculated in this manner are displayed on the setting / performance indicator 97 by the performance display monitor display process (see step S916 in Figure 18) described later in the main control timer interrupt processing.

[0169] In step S605, following step S604, CPU20a performs a full register reset process, and then in the subsequent step S606, sets itself to an interrupt-enabled state before returning to step S601.

[0170] In this way, in the main loop processing of step S123, the processing of steps S601 to S606 is repeated in an infinite loop. The CPU 20a will repeatedly execute these steps S601 to S606, except when it is performing timer interrupt processing which is executed intermittently.

[0171] (Settings change process) Figure 10 is a flowchart showing the setting change process in step S115. This setting change process includes tasks such as setting the setting value Ve based on the operation, and sending performance control commands to the performance control unit 24 to notify that the setting change is in progress or that the setting change has been completed.

[0172] In Figure 10, the CPU 20a first executes the process of sending a setting change command (BA76H) to the performance control unit 24 in step S401. Upon receiving this setting change command, the performance control unit 24 performs processing to cause the liquid crystal display device 36 to display a screen indicating that the settings are being changed, such as a screen with text like "Settings being changed," or to cause the speaker 46 to output sound corresponding to the setting change. Furthermore, at this time, the performance control unit 24 may also light up predetermined LEDs (for example, all LEDs) in the aforementioned light generating means (light display device 45a) according to a predetermined lighting pattern.

[0173] In the following step S402, the CPU 20a sets the backup flag to 00H (i.e., OFF), and then in step S403 sets the system operation status to 2. This system operation status is information to at least identify whether or not the configuration change process in step S115 was performed at startup. "2" indicates that the configuration change process was performed, and any value other than "2" (for example, "0") indicates that the configuration change process was not performed. As can be seen by referring to Figure 5, in this example, the RAM clear process (program) is shared whether both the configuration change process and the RAM clear process (S116) are executed, or whether only the RAM clear process is executed without the configuration change process. However, by using the system operation status described above, it is possible to execute different processes depending on the former and latter cases while still sharing the RAM clear process program.

[0174] In step S404, following step S403, CPU 20a executes a process to obtain a setting value. Specifically, it obtains the setting value Vd (one of 00H to 02H in this example) stored in the work area of ​​RAM 20c.

[0175] The processes from step S405 onward, following step S404, are for updating the displayed value on the setting / performance indicator 97 in accordance with the sequential operation of setting value Ve (operation of the RAM clear button), and for setting the setting value Ve in accordance with the completion operation of setting change (operation of the setting key). First, in step S405, the CPU 20a decrements the acquired setting value Vd by 1 ("setting value - 1"), and then in the subsequent step S406, determines whether the setting value Vd is greater than 1 ( "setting value > 1"). In this example, since the maximum value of the setting value Vd is 02H, it is not determined that the setting value > 1 in step S406 which is executed for the first time after the start of the setting change process. In step S406, if the setting value Vd is not greater than 1, the CPU 20a sets the carry flag (sets it to ON) in step S407, then increments the setting value Vd by 1 ("setting value + 1") in step S408, and determines whether the carry flag is ON in step S409. If the carry flag is ON, the CPU 20a executes the acquisition process of the command at the time of setting change in step S411, and transmits the command at the time of setting change to the production control unit 24 by the command process in the subsequent step S412. Note that the command at the time of setting change will be described later. Then, in response to executing the command transmission process in step S412, the CPU 20a executes the output management process in step S413. By this output management process, the setting value Ve corresponding to the current setting value Vd is displayed on the setting / performance display 97. Note that the details of the output management process in step S413 will be described later.

[0176] In step S414 following step S413, the CPU 20a determines whether the setting key is OFF, that is, whether the setting key switch 94 is OFF. If the setting key is not OFF, it determines whether the change switch, that is, the RAM clear switch 98 is ON in step S415. If the RAM clear switch 98 is not ON, the CPU 20a executes the output management process in step S413 again. By the processes in steps S413 to S415, the CPU 20a waits until either the setting key or the change switch is ON, and during the waiting, repeats the process for displaying the current setting value Ve on the setting / performance display 97 by the process in step S413.

[0177] In step S415, if the change switch is ON, CPU20a returns to step S406. Here, if the setting value Vd obtained at the start of the setting change process in step S115 (the setting value Vd that was being set up to that point) was 02H, then in the process of step S406, which is executed in response to the determination in step S415 that the change switch is ON, the determination result is that "setting value > 1" (because it is subtracted by 1 in step S405 but added by 1 in step S408). In response to a change operation (sequential operation) performed while the setting value Vd was 02H, the setting value Vd should be returned to 00H. For this reason, if "setting value > 1" is determined in step S406, the carry flag setting process in step S407 is skipped and the process proceeds to step S408. As a result, in step S409, the carry flag is determined to be OFF, so the process proceeds to step S410 and the setting value Vd is returned to 00H ("setting value ← 0"). In response to the setting value Vd being reset to 00H in step S410, CPU 20a proceeds to step S413 via steps S411 and S412. In this case, the setting / performance indicator 97 displays the setting value Ve (1 in this example) corresponding to the setting value Vd=00H.

[0178] Through the above process, while a setting change is in progress, the setting value Vd is changed cyclically within the range of 00H to 02H (within the usage range Ru) according to the change operation, and the setting value Ve corresponding to the changed setting value Vd is displayed on the setting / performance indicator 97.

[0179] Furthermore, the setting change command transmitted in step S412 is a command to notify the performance control unit 24 of the setting value Ve corresponding to the selected setting value Vd during the setting change process, and is a command that stores information representing the selected setting value Ve. Through the series of processes described in steps S406 to S415 above, each time the selected setting value Ve is switched by the sequential operation of setting values, a setting change command reflecting the switched setting value Ve is sent to the performance control unit 24. Although not illustrated in Figure 10, when obtaining the setting value Ve corresponding to the setting value Vd, the CPU 20a uses the setting value offset conversion table described later (see Figure 16).

[0180] If it is determined in step S415 that the setting key is OFF, the CPU 20a proceeds to step S416 to execute the process of saving the setting value Vd. That is, it executes the process of storing the setting value Vd in a predetermined area in the work area of ​​RAM 20c. CPU 20a completes the setting change process in step S115 after executing the save process in step S416.

[0181] Figure 11 is a flowchart of the output management process in step S413. First, in step S501, the CPU 20a performs security signal output processing. Specifically, it performs processing to output a security signal to the hall computer HC through the frame external centralized terminal board 21. In the following step S502, the CPU 20a outputs 0 to the LED common port, that is, the common port of the LED which serves as the setting / performance indicator 97. Then, in step S503, it performs the process of acquiring display data from the 7-segment decode table. In other words, it acquires display data for the setting value Ve ("1", "2", "6") based on the setting value Vd. Note that if 0 is output to the LED common port in step S502, the setting / performance indicator 97 will be in an OFF state (no display state), but the significance of this will be explained later.

[0182] Figure 12 shows an example of a 7-segment decode table, and Figure 13 illustrates the relationship between the segment configuration and the segment display pattern in the setting / performance indicator 97. The 7-segment decoding table is stored in the ROM 20b of the main control unit 20.

[0183] In this example, the seven segments of the setting / performance indicator 97 are numbered with values ​​from 0 to 6, as shown in Figure 13A. The setting / performance indicator 97 is also provided with a DP (dot point) display unit (light-emitting unit) along with these seven segments numbered from 0 to 6, and the DP display unit is numbered "7". For the 7-segment display data, a total of 10 data points are provided, from the data for displaying the number "0" ("SEG_0") to the data for displaying the number "9" ("SEG_9"). The display data is 1 byte (8 bits) of data, and if the least significant bit is considered the 1st bit position, the 1st bit position represents the display / hide (illuminated / non-illuminated) of segment "0". Similarly, the 2nd bit position represents the display / hide of segment "1", the 3rd bit position represents segment "2", the 4th bit position represents segment "3", the 5th bit position represents segment "4", the 6th bit position represents segment "5", and the 7th bit position represents the display / hide of segment "6". Furthermore, in this example, the display data is such that the 8th bit position represents the display / hide status of DP ("7").

[0184] The 7-segment decode table shown in Figure 12 is configured to obtain the corresponding display data, specifically the display data for SEG_1, SEG_2, and SEG_6, from the set values ​​Vd=00H, 01H, and 02H. Specifically, in the 7-segment decode table of this example, an area is reserved to store display data for each setting value Vd from 00H to 05H, as shown in the address ranges "6203" to "6208" in the figure. The top layer of this area (the area with the lowest numbered address) stores display data SEG_1 ("06" in the figure) corresponding to setting value Vd=00H, the second layer stores display data SEG_2 ("5B" in the figure) corresponding to setting value Vd=01H, and the third layer stores display data SEG_6 ("7D" in the figure) corresponding to setting value Vd=02H. In this example, the fourth area corresponding to the setting value Vd=03H, the fifth area corresponding to the setting value Vd=04H, and the sixth area corresponding to the setting value Vd=05H all contain "00" as display data. The significance of this will be explained later. Furthermore, the 7-segment decode table in this example stores display data SEG_E ("79") in the 7th region for displaying "E" to indicate a setting value error. This makes it possible to notify the setting value error via the setting / performance indicator 97 when the setting value Vd shows an abnormal value, such as when the setting value Vd is outside the usage range Ru.

[0185] Return to the explanation in Figure 11. The CPU 20a processes the data obtained from the 7-segment decode table in step S503 and outputs it to the setting / performance indicator 97 in step S504. The subsequent steps S505 to S508 are processes to dynamically light up (intermittently light up) the LED used to display the set value Ve in the setting / performance indicator 97. Specifically, in step S505, the CPU 20a increments the LED counter by 1, and in the following step S506, it determines whether the 0th and 1st bits (lower 2 bits) of the LED counter are "11". Here, the lower 2 bits of the LED counter become "11" when the increment process in step S505 is performed a multiple of 4 times. In step S506, if the 1.0 bit of the LED counter is "11", the CPU 20a proceeds to step S507, outputs data to the LED common port specifying the segment for displaying the set value, and executes the display timer counting process in step S508. The output process in step S507 is executed, causing the setting / performance indicator 97 to display the set value Ve based on the display data output in step S504. This display state will then continue for the duration of the display timer in step S508 (4ms in this example).

[0186] The output management process shown in Figure 11 ends upon the execution of the process in step S509, which follows the timer count process in step S508. The process then proceeds to step S414, shown in Figure 10. However, if the setting key is OFF and the change switch is ON, the output management process in step S413 is repeated. As described above, in step S502, 0 is output to the LED common port, so the LED for displaying the setting value, which was turned on in the process in step S507, is cleared by the execution of step S502. Then, in step S505, the LED counter is incremented by 1, so in step S506, it is determined that the 0th and 1st bits of the LED counter are not "11", the output process in step S507 is skipped, and the timer count process in step S508 is executed. In other words, after the process in step S507 is executed and the LED for displaying the set value is lit for at least 4ms, the LED remains off until the 0th and 1st bits of the LED counter become "11" again, which in this example is at least 4ms × 3 = 12ms. In this way, dynamic lighting is achieved, in which the LEDs for displaying the set value are lit intermittently at a predetermined interval.

[0187] In Figure 11, the CPU 20a executes the input data creation process in step S509, in response to having executed the timer counting process in step S508. This input data creation process is executed, for example, by calling the same process in step S902 of the main control timer interrupt processing (Figure 18). As will be described later, the input data created by this input data creation process includes input data for the RAM clear switch 98 indicating whether or not a sequential operation of the set value Ve has been performed, and input data for the setting key switch 94 indicating whether or not a setting change operation has been completed. As can be seen by referring to Figure 10, the determination of whether the setting change operation has been completed (S414) and the determination of whether the setting value Ve has been advanced (S415) are performed after the output management process in step S413. By performing the input data creation process in step S509, the data required for these determination processes is obtained in advance.

[0188] (RAM clearing process) Figure 14 is a flowchart of the RAM clear process (S116) shown in Figure 5. First, in step S601, the CPU 20a executes a RAM initialization process within the memory area. This initialization process in step S601 initializes (clears) the values ​​in a predetermined area (used area) in RAM 20c, including the work area. However, in this initialization process in step S601, the storage area for the set value Vd in the work area is excluded from the initialization.

[0189] The performance information mentioned above is stored in an area outside the used area of ​​RAM20c (see Figure 21 for details, which will be described later), and therefore is not cleared during the initialization process in step S601. The data to be cleared in the RAM clear process is the data in the RAM areas (normal data storage areas) such as various flags, timers, counters, etc. that are necessary during normal game progress. Such data includes, for example, the following. That is, data related to game state designation (game state flags specifying the current game state such as normal state, probability variation state, time shortening state, potential probability state, etc.), a flag specifying whether it is a winning game (condition device operation flag), various data related to the execution of a winning game (current round number, maximum round number, etc.), data related to the jackpot lottery result (jackpot determination flag: winning / losing lottery result information, special symbol determination data: symbol lottery result information), reservation data related to activated reserved balls (number of activated reserved balls, various random number values used in jackpot lottery, various random number values used in supplementary winning lottery, random number for variation pattern), special symbol operation status, a timer for managing game progress (special symbol device operation timer), input / output data related to switches and sensors, various winning counters for counting the number of winning balls in winning ports, a flag specifying the presence or absence of the electric support state (release extension flag), an electric support count counter for counting the remaining number of electric supports, a counter for counting the remaining number of high probability states (special figure probability variation count counter, general figure probability variation count counter), various error flags (excluding the RAM error flag), and payout-related data, etc. In any case, when the RAM clear process is executed, all data except for specific data (set value Vd and performance information) is set to the initial state.

[0190] Here, as understood from the description of FIG. 5 above, when the setting change process (S115) is executed, the process proceeds to step S116 and the RAM clear process is executed. In the setting change process, the set value Vd can be changed. When the set value Vd is changed, the stored values other than the set value Vd in the work area of the RAM20c may be in a state inconsistent with the changed set value Vd. Therefore, when the setting change process is performed, by executing the RAM clear process, the areas other than the set value Vd in the work area are cleared (initialized).

[0191] In response to the initialization process in step S601, the CPU 20a sets the RAM clear notification timer to 30s in step S602 and also performs the process to set a losing outcome in the main special feature. The RAM clear notification timer is a timer for setting the time for the RAM clear notification that the performance control unit 24 executes in response to the RAM clear command sent in step S803 of Figure 17, which will be described later, and in this example, it is set to 30s. The main special feature referred to here means, for example, the special feature 1 and special feature 2 described above.

[0192] In step S603, following step S602, the CPU 20a determines whether the aforementioned system operation status is "2". That is, it determines whether the configuration change process in step S115 has been completed after startup. If the system operation status is "2", CPU 20a executes the corresponding process in steps S604 to S612, which is performed after the configuration change process. If the system operation status is not "2", the CPU 20a proceeds to step S613 to store the lower byte data of the RAM clear command in a register and finishes the RAM clear process in step S116. Furthermore, the operation of storing the lower byte data of the command in a register, as described above, functions as an operation to specify the type of command to be sent in step S804 of the main loop preprocessing (Figure 17), which will be described later.

[0193] If the configuration change process is performed, the CPU 20a first resets the system operation status to "0" in step S604, then executes the process of acquiring the configuration change completion command (BA77H) in step S605, and then sends the configuration change completion command to the performance control unit 24 in the command transmission process in the subsequent step S606.

[0194] The processing in steps S607 to S612, following step S606, is related to the display of the set value Ve in the setting / performance indicator 97. First, in step S607, the CPU 20a outputs data to the LED common port specifying a segment for displaying the set value. In the following step S608, it obtains display data corresponding to the set value Vd from the 7-segment decode table (see Figure 13). In step S609, it performs a process to add DP to the display data, that is, a process to set the value of the 7th bit position of the display data to "1". Finally, in step S610, the output process outputs the display data to the setting / performance indicator 97.

[0195] The processes in steps S612 and S613, following step S611, are for maintaining the display state of the set values ​​Ve and DP on the setting / performance indicator 97 for a predetermined time (1 s in this example). Specifically, the CPU 20a repeatedly executes the display timer count process in step S612 (for example, a timer count process with a 4 ms period, similar to the previous step S508 (see Figure 11)) until it is determined in step S612 that 1 s has elapsed.

[0196] If step S612 determines that 1 second has elapsed, the CPU 20a executes the memory processing in step S613 and finishes the RAM clearing process in step S116.

[0197] As can be understood from the above explanation, when the setting change process in step S115 is executed and the setting change completion operation is performed (step S412:Y in Figure 10), a setting change completion command is sent to the performance control unit 24 in the RAM clear process in step S116 (S605, S606), and notification is given that the setting change has been completed. In this example, the setting change completion command notifies the performance control unit 24 that the setting change has been completed, but it does not have the function to notify the setting value Ve set during the setting change process. In this example, the setting value Ve set during the setting change process is notified to the performance control unit 24 by a setting value command sent in step S808 of Figure 17 (main loop preprocessing), which will be described later.

[0198] (Configuration confirmation process) Figure 15 is a flowchart showing the setting confirmation process in step S109. The setting confirmation process is a process to confirm and display the setting value Ve that is currently being set. In Figure 15, CPU 20a first sets the malicious information timer to 30s in step S701. The malicious information timer is a timer used to manage the output time of the security signal to the hall computer HC, as described above. In the following step S702, the process of obtaining the current setting value information is performed. That is, the setting value Vd stored in the RAM work area is obtained.

[0199] In step S703, following step S702, the CPU 20a executes a process to obtain setting value data from the setting value offset conversion table.

[0200] Figure 16 shows an example of a setting value offset conversion table stored in the ROM 20b of the main control unit 20. The setting value offset conversion table converts setting value Vd (00H~02H) to setting value Ve ("1 It functions as a table for converting the identification data ("SETNUM1" to "SETNUM6") of "2" and "6". In this example, the setting value offset conversion table has an area reserved for each setting value Vd from 00H to 05H, as shown in the address ranges "6215" to "6220" in the figure, where identification data for setting value Ve is stored. The top area of ​​this range contains the identification data for setting value Ve "1" ("00" in the figure) corresponding to setting value Vd=00H, the second area contains the identification data for setting value Ve "2" ("01" in the figure) corresponding to setting value Vd=01H, and the third area contains the identification data for setting value Ve "6" ("05" in the figure) corresponding to setting value Vd=02H. In this example, the fourth area corresponding to the setting value Vd=03H, the fifth area corresponding to the setting value Vd=04H, and the sixth area corresponding to the setting value Vd=05H all store "00" as identification data for the setting value Ve. The significance of this will be explained later.

[0201] In Figure 15, the CPU 20a acquires the above identification data as "setting value data" through the acquisition process in step S703.

[0202] In response to the acquisition process in step S703, the CPU 20a performs the acquisition process for the setting confirmation command (BA6xH) in step S704, and then sends the setting confirmation command to the performance control unit 24 in the command transmission process in the subsequent step S705. In the acquisition process of step S704, CPU20a includes the setting value data acquired in step S703, that is, identification data to identify the setting value Ve currently being set among the setting values, in the setting confirmation command. As a result, the command transmission process in step S705 is executed, and the performance control unit 24 is notified that the settings are being checked and the current setting value Ve.

[0203] The processes in steps S706 and S707, following step S705, are for displaying the current setting value Ve on the setting / performance indicator 97. Specifically, in step S706, the CPU 20a first executes a process to acquire the setting value and DP data. That is, it executes a process to acquire the current setting value Vd stored in the work area of ​​RAM 20c and the DP data ("1") on the setting / performance indicator 97. Then, it executes the output management process in step S707. This output management process in step S707 is the same process as the output management process in step S413 shown in Figure 11. As a result, in this case, the setting / performance indicator 97 displays a value representing the current setting value Ve and the DP.

[0204] In step S708, following step S707, the CPU 20a determines whether the setting key is OFF (setting key switch 94 is OFF), that is, whether the instruction to end the setting confirmation display has been made. If the setting key is not OFF, the output management process of step S707 is executed again. As a result, after the setting confirmation command is sent in step S705, the system waits until the instruction to end the setting confirmation display is made by the process in step S708. During this waiting period, the process in step S707 continues to display the current setting values ​​Ve and DP on the setting / performance indicator 97.

[0205] If it is determined in step S708 that the setting key is OFF, the CPU 20a executes the process of acquiring the setting confirmation completion command (BA67H) in step S709, and then sends the setting confirmation completion command to the performance control unit 24 in the command transmission process in the subsequent step S710, and the setting confirmation process in step S109 is completed.

[0206] (Pre-processing before the main loop) Figure 17 is a flowchart of the main loop preprocessing in step S119. In the main loop preprocessing, the CPU 20a first executes the initialization command acquisition process in step S801, and then transmits the initialization command to the performance control unit 24 in the command transmission process in the subsequent step S802. The initialization command is a command to instruct the movable body motor 80c, which operates the movable body as a special feature, to initialize (return to its home position).

[0207] In step S803, following step S802, the CPU 20a performs a process to obtain transmission command data from the acquired lower byte command, and transmits the acquired command data to the performance control unit 24 by the command transmission process in step S804. Here, in the acquisition process of step S803, the data of commands whose lower byte data was stored in the register during the process that has been passed through since startup is acquired. Specifically, if the RAM clear process of step S116 is performed (when both the setting change process and the RAM clear process are performed, or when only the RAM clear process is performed and the setting change process is not performed), the data of the RAM clear command (BA02H) is acquired. On the other hand, if the backup restore process of step S111 is performed (when both the setting confirmation process and the backup restore process are performed, or when only the backup restore process is performed and the setting confirmation process is not performed), the data of the power outage recovery display command (OB03H) is acquired. As a result, the performance control unit 24 is configured to execute different processes depending on whether a RAM clear process is performed or a backup restore process is performed.

[0208] In step S805, following step S804, the CPU 20a executes a process to transmit the number of reserved figures for Special Figure 1 and Special Figure 2. In this step S805, if the backup restoration process in step S111 is performed, the number of reserved figures for Special Figure 1 and Special Figure 2 is transmitted to the performance control unit 24. If the RAM clear process in step S116 is performed, the number of reserved figures is not transmitted (because the information on the number of reserved figures has been cleared).

[0209] The processing in steps S806 to S808, following step S805, is for notifying the performance control unit 24 of the current setting value Ve using a setting value command. First, in step S806, the CPU 20a performs a process to obtain the current setting value information, specifically by obtaining the setting value Vd stored in the work area of ​​RAM 20c. Then, in the following step S807, it executes a process to obtain setting value data from the setting value offset conversion table (Figure 16). Specifically, it obtains identification data for the setting value Ve ("1", "2", "5") corresponding to the setting value Vd (00H~02H) obtained in step S806. Then, in the following step S808, the CPU 20a performs the process of acquiring the setting value command (F6xxH), and in the command transmission process of step S809, it sends the setting value command to the performance control unit 24. In the acquisition process of step S808, a setting value command containing the identification data acquired in step S807 is obtained. This setting value command allows the performance control unit 24 to be notified of the current setting value Ve.

[0210] In response to the execution of the command transmission process in step S809, the CPU 20a executes the internal function register setting process in step S810, that is, the register setting process for the initial setup of various functions such as the hardware random number counting function, and in step S811, it executes the process to set the performance display monitor illumination timer to 5s. The performance display monitor illumination timer is a timer that manages the operation time of the operation confirmation illumination operation (a blinking operation for 5 seconds in this example) when the setting / performance display unit 97 is started up.

[0211] Furthermore, in step S812 following step S811, the CPU 20a resets the system operation status to "0", and in step S813 turns on the launch permission signal to the payout control board 29. In response, the payout control board 29 determines that it is in a launch permission state and outputs the permission signal to the launch control board 28, allowing the launching device 32 to launch the game balls. This makes it possible to launch the game balls using the launch operation handle 15. In this example, the discharge control board 29 receives a launch permission signal from the main control unit 20 and permits the launch operation, meaning that the launch permission instruction information from the main control unit 20 is indirectly sent to the launch control board 28 through the discharge control board 29. However, the present invention is not limited to this, and for example, the launch permission signal from the main control unit 20 can be directly output to the launch control board 28. In response to having executed the process in step S813, CPU 20a completes the main loop preprocessing in step S119.

[0212] (Advantages of the data table for displaying setting values ​​and the setting value conversion table) In this embodiment, as shown in the setting value offset conversion table in Figure 16, the ROM 20b of the main control unit 20 stores a data table containing multiple setting value-related information selected by referring to the setting value. This data table contains first setting value-related information, which is selected when the main control unit 20 refers to a setting value Vd ("00H" to "02H") that can be set by the setting change process (see Figure 10), and second setting value-related information, which is selected when the main control unit 20 refers to a setting value that cannot be set by the setting change process. Specifically, the first setting value-related information corresponds to "00", "01", and "05" stored at addresses "6215", "6216", and "6217", respectively, in the setting value offset conversion table shown in Figure 16, and the second setting value-related information corresponds to "00", "00", and "00" stored at addresses "6218", "6219", and "6220", respectively. Furthermore, in the data table, at least specific information regarding the setting value Ve, which represents the stage with the lowest probability of winning (i.e., "00" at address "6215"), is stored as first setting value related information, and the same information as the specific information is stored as second setting value related information.

[0213] If the set value Vd is an unsettable value, it is possible to overwrite the set value Vd stored in RAM20c with a value representing the lowest level. However, if the data is tampered with after being overwritten, there is a risk that the corresponding information will be retrieved from the data table based on the unsettable setting value Vd, and that the system will perform actions corresponding to the unsettable setting value. According to the above configuration, it is impossible to obtain information corresponding to the unsettable setting value Vd from the data table, thus preventing fraudulent activity and enhancing the fairness of the game.

[0214] Furthermore, in this embodiment, 0 is stored as the specific information described above. This makes it possible to prevent fraudulent activities through tampering with settings by simply writing a specific piece of information (=0) into the setting-related information. In other words, it is possible to enhance the fairness of the game through a simple method.

[0215] Furthermore, in this embodiment, the 7-segment decode table shown in Figure 12 also includes first setting value related information (addresses "6203" to "6205"), which is setting value related information selected when the main control unit 20 refers to a setting value Vd that can be set by the setting change process, and second setting value related information (addresses "6206" to "6208"), which is setting value related information selected when the main control unit 20 refers to a setting value that cannot be set by the setting change process. In the 7-segment decode table, 0 is stored as the second setting value related information. This makes it possible to prevent the display of the setting value (in this example, the setting / performance indicator 97) from displaying the setting value, even if the data table is referenced with a setting value Vd that cannot be set during the setting change process due to fraudulent activity or some kind of malfunction. Specifically in this example, the data "00", i.e., "00000000", is acquired as the display data, so all segments from "0" to "6" in the 7-segment display for setting value display are hidden, and as a result, no numerical value is displayed. Therefore, it is possible to prevent incorrect display of set values.

[0216] [4-2. Main control side timer interrupt processing] The main control side timer interrupt processing will be explained with reference to the flowchart in Figure 18. The main control timer interrupt processing is triggered by an interrupt from the CTC at regular intervals (approximately 4ms) and is executed by interrupting the main control processing during execution.

[0217] In Figure 18, when a timer interrupt occurs, the CPU 20a first executes the power check and backup process in step S901. This power check and backup process mainly monitors the power level supplied from the power supply board, and if an abnormality such as a power outage occurs, it performs backup processing such as storing predetermined game information in RAM 20c so that gameplay can be resumed without problems when power is restored.

[0218] (Power check and backup process) Figure 19 is a flowchart showing the power check and backup process in step S901. In the power check and backup process, CPU 20a reads the power abnormality signal output from the power supply board twice in step S1001, and in the following step S1002, it determines whether the two read values ​​match. If the two values ​​do not match, it returns to step S1001 and reads the power abnormality signal twice again.

[0219] In step S1002, if both values ​​match, CPU 20a determines in step S1003 whether the power supply abnormality signal is at a normal level or not (if the power supply abnormality signal is OFF, it is at a normal level; if it is ON, it is not at a normal level). If the power supply abnormality signal is at a normal level (step S1003: OFF), the CPU 20a sets the backup flag to the OFF state in step S1004, clears the power supply abnormality confirmation counter in the following step S1005, and finishes the power supply abnormality check process in step S901. In other words, if it is confirmed that the power supply abnormality signal is at a normal level, the backup process described below is not performed and the timer interrupt process continues.

[0220] On the other hand, if the power supply abnormality signal in step S1003 is not at a normal level (step S1003: ON), the CPU 20a increments the value of the power supply abnormality check counter by 1 in step S1006, and then determines in step S1007 whether the value of the power supply abnormality check counter is equal to or greater than a predetermined threshold (threshold = a natural number greater than or equal to 2: for example, "2"). If the value of the power supply abnormality check counter is not above the threshold, the CPU 20a finishes the power supply abnormality check process in step S901. In other words, if a state where the power supply abnormality signal is not at a normal level is detected, but the detection is not continuous, the backup process is not performed and the timer interrupt process continues.

[0221] On the other hand, if the value of the power supply abnormality check counter is above the threshold, the CPU 20a performs the backup process shown in steps S1008 to S1011. Specifically, CPU20a first clears the power supply abnormality check counter value (S1108), turns off the launch permission signal (S1009), and then turns on the backup flag (S1010). Furthermore, the CPU 20a sends a power-off command to the performance control unit 24 (S1011), and proceeds to step S1012.

[0222] In step S1012, CPU20a performs a process to enable RAM protection and disable the prohibited area. RAM protection is a function that prevents rewriting of RAM20c due to malfunctions or incorrect operation. By enabling RAM protection, only data can be read from RAM20c, and data cannot be written. Furthermore, the prohibited area corresponds to the designated area in the IAT (Isolated Attack Control) function, and disabling the prohibited area will prevent IAT resets from occurring in the future.

[0223] In step S1013, following step S1012, CPU20a clears the output port value, and in the subsequent step S1014, it stops timer interrupt processing, sets itself to an interrupt-disabled state, and transitions to infinite loop processing. During this infinite loop, CPU20a is reset by the WDT and enters a shutdown state due to the loss of power supply.

[0224] Return to Figure 18 for explanation. In Figure 18, after completing the power check and backup process in step S901, the CPU 20a executes the input data creation process in step S902. Specifically, it creates input data based on input information (ON / OFF signals and rising edge states (ON edge, OFF edge)) from various sensors and switches. The input information here includes, for example, ON / OFF information (winning detection information) of switch signals output from winning detection switches such as the upper starting port sensor 34a, lower starting port sensor 35a, normal symbol starting port sensor 37a, large winning port sensor 52a, general winning port sensor 43a, and OUT monitoring switch 49a; ON / OFF information (operation information) of switch signals output from switches related to setting the setting value Ve, such as the setting key switch 94 and RAM clear switch 98; and status signals from the payout control board 29 (ON / OFF information of the front door open sensor 61 and full detection sensor 60). This allows monitoring of whether or not a game ball has been detected at the OUT port and each winning port with each interrupt.

[0225] After completing the input data creation process in step S902, the CPU 20a executes a timer management process in step S903 to manage the timers used for game operation control. Here, the values ​​of various timers used for game operation control of the gaming machine 1 are updated (subtracted).

[0226] Next, in step S904, the CPU 20a performs input management processing. In this input management processing, based on the input data created in the input data creation processing (S902), it updates the values ​​of the prize counter and the OUT ball monitoring counter. The "prize counter" is a counter provided for each prize slot that counts the number of game balls that have entered (prize ball count). The OUT ball monitoring counter is a counter that counts the game balls that are discharged from the OUT slot 49 (out balls). The input management process in step S904 functions as an input management means for managing input signals (detection signals) from various prize-winning sensor locations.

[0227] In step S905, following step S904, CPU20a performs a configuration anomaly check process.

[0228] Figure 20 is a flowchart showing the setting error check process in step S905. In Figure 20, CPU 20a checks the setting value error flag in step S1101. The setting value error flag is a flag that is set (turned ON) by the process in step S1103, which will be explained below, when an abnormality in the setting value Vd is detected. In this example, "5AH" means that the flag is ON.

[0229] In step S1101, if the setting value error flag is "5AH" (ON state), the CPU 20a finishes the setting error check process in step S905. In other words, if the setting value error flag is determined to be ON in step S1101, it means that the setting error command (a command instructing the performance control unit 24 to execute setting error notification) has already been sent in step S1104, which will be described later. Therefore, the setting error check process is finished without sending the setting value error flag again.

[0230] On the other hand, if it is confirmed in step S1101 that the setting value error flag is not "5AH" (it is OFF), the CPU 20a determines in step S1102 whether the setting value Vd is within the normal range (within the range of 0 to 2). Specifically, it retrieves the setting value Vd stored in the work area of ​​RAM 20c and determines whether the value is within the range of "00H" to "02H".

[0231] If the set value Vd is within the normal range, the CPU 20a completes the setting anomaly check process in step S905. If the set value Vd is not within the normal range, the CPU 20a proceeds to step S1103 to set the set value error flag (to the ON state), and in the following step S1104, sends a set value abnormality command to the performance control unit 24 to indicate that an abnormality has occurred in the set value Vd, and ends the set abnormality check process. Here, the setting error flag is used in step S1308 (setting error detection when winning) in Figure 25, which will be described later, as well as in step S1501 (setting error detection when determining the jackpot random number at the start of variation) in Figure 27, and in step S1701 (setting error detection when determining the variation pattern lottery at the start of variation) in Figure 30.

[0232] Upon receiving the above setting value anomaly command, the performance control unit 24 performs processing to notify the system of the data anomaly in the setting value Ve. For example, it performs processing to display an image on the liquid crystal display device 36 that includes a message such as "RAM anomaly. Please call an attendant." In gaming machine 1, setting errors (setting value errors) can be resolved by performing a setting change operation.

[0233] Return to Figure 18 for explanation. After the CPU 20a completes the setting abnormality check process in step S905, it executes error management processing in step S906. In this error management processing, it monitors whether or not an error has occurred based on input data from various sensors and status signals from the dispensing control board 29. If an error occurs, the CPU 20a performs error handling by sending an error command to the performance control unit 24 if the error type requires such a command. Upon receiving this error command, the performance control unit 24 executes an error notification according to the error type. Furthermore, if the error is resolved, the CPU 20a sends an error clear command to the performance control unit 24. Upon receiving this error clear command, the performance control unit 24 terminates the ongoing error notification.

[0234] Next, in step S907, CPU 20a executes timer interrupt-based random number management processing, which periodically updates the random numbers related to each variable display game. Here, in order to make the count value of the random number counter random, it updates the random numbers (adding +1 with each interrupt) for special symbol determination random numbers and auxiliary win determination random numbers, and changes the starting value of the random number counter each time the random number counter completes a cycle. Note that the random numbers for internal lottery (jackpot determination random numbers) are generated by the random number generation circuit and are therefore not updated here.

[0235] In step S908, following step S907, the CPU 20a executes the prize ball management process. In this prize ball management process, the CPU 20a checks the prize counter mentioned above, and if there are any prizes, it sends a payout control command specifying the number of prize balls to the payout control board 29. When the payout control board 29 receives the payout control command, it controls the game ball payout device 19 based on the prize ball count information contained therein and performs a payout operation for the specified number of prize balls.

[0236] Next, in step S909, the CPU 20a executes the normal symbol management process. This normal symbol management process performs the necessary processing to execute the normal symbol variation display game. Here, the normal symbol start sensor 37a monitors whether or not a game ball has been detected. If a game ball is detected, it acquires predetermined game information (such as a random number for auxiliary win determination) necessary for the auxiliary win lottery (random number acquisition process), and stores that game information as reserved data (operational reserved balls related to normal symbols) up to the maximum number of reserved balls (reserved storage process). Then, if the predetermined variation display start conditions for the normal symbols are met, an auxiliary win lottery is performed based on the operational reserved balls, and the variation pattern of the normal symbols and the stop display mode of the normal symbols (normal stop symbols) are determined based on the result of the auxiliary win lottery. Also here, in order to make the normal symbols change, if they are changing, LED display data for variation display is created, and if they are not changing, LED display data for stop display is created.

[0237] Furthermore, in step S910, the CPU 20a executes the normal electric mechanism management process. This normal electric mechanism management process performs the processing necessary for executing the normal electric opening game. Specifically, if the result of the auxiliary winning lottery is a win, it performs the process of setting solenoid control data for the normal electric mechanism solenoid 41c. Based on the solenoid control data set here, an excitation signal is output to the normal electric mechanism solenoid 41c, thereby controlling the opening and closing operation pattern of the movable blade 47.

[0238] Next, in step S911, CPU 20a executes special symbol management processing. In this special symbol management processing, a jackpot lottery is mainly conducted for the special symbol variation display game, and based on the lottery results, processing necessary for the special symbol variation display game is executed, such as determining the variation pattern of the special symbols (pre-read variation pattern and variation pattern at the start of variation) and the special stop symbols.

[0239] Next, in step S912, the CPU 20a executes special electric mechanism management processing. This special electric mechanism management processing performs the necessary setting processing to execute and control the winning game. Specifically, if the jackpot lottery result is a jackpot, it executes and controls the winning game (jackpot game) corresponding to that type of jackpot. Specifically, it performs tasks such as setting solenoid control data for the large prize slot solenoid 52c, counting the number of rounds (in the case of a jackpot), and monitoring the maximum number of entries into the large prize slot 50 and the opening time. Furthermore, when a winning game ends, it sets the transition to the game state based on the game state at the time of winning and the type of win.

[0240] Furthermore, multiple performance control commands are sent here according to the progress of the winning game. At the start of a jackpot, the start of a round of play, the end of a round of play, and when the maximum number of rounds has been completed, the jackpot start command, round start command, round end command, jackpot entry command, and jackpot end command are sent according to the timing of their transmission. The jackpot start command includes information on the type of win this time and is used by the performance control unit 24 to determine the series of jackpot performance scenarios that will unfold during the winning game. The jackpot end command includes information on the type of win this time and the game state at the time of the win, that is, information that can identify the game state after the jackpot ends and is used by the performance control unit 24 to determine the performance mode after the jackpot ends. Therefore, since this "jackpot end command" can identify the game state after the jackpot ends, it plays the role of a game state specification command that specifies the game state.

[0241] After completing the processing for game progression up to step S912, the CPU 20a performs external terminal management processing in step S913. In this external terminal management processing, the operating status information of the gaming machine 1 is output to external devices such as the hall computer HC and island lamps through the frame external centralized terminal board 21. The operating status information includes game information such as winning game occurrence information, symbol variation display game execution start information, number of winnings / prize balls information, and error information.

[0242] Next, in step S914, the CPU 20a executes LED management processing. This LED management processing controls the output of control signals (dynamic lighting data) to LED indicators such as the normal pattern display device 39a, special pattern display devices 38a and 38b, and the setting / performance indicator 97. The control signals based on the display data created in the normal pattern management processing (step S909), special pattern management processing (step S911), etc., are output to the corresponding display device or indicator in this LED management processing, and display control is performed. This enables a series of variable display operations (variable display and stop display) of special patterns in the special pattern display devices 38a and 38b and normal patterns in the normal pattern display device 39a.

[0243] In step S915, following step S914, the CPU 20a saves the values ​​of all registers and then performs the performance display monitor display process in step S916. In other words, this process displays the values ​​mentioned above as normal ratio information on the setting / performance display unit 97. As mentioned earlier, in this example, the value of the normal ratio information is recalculated each time the total number of out balls reaches a predetermined value, and the setting / performance indicator 97 is capable of displaying the current normal ratio information and the previous normal ratio information (the normal ratio information that was deemed to have been calculated at the most recent recalculation timing). Therefore, in the display process of step S916 in this case, the setting / performance indicator 97 is made to display the values ​​of these two types of normal ratio information. The current normal ratio information value is calculated in step S604 of the main loop processing (Figure 11) described above, while the previous normal ratio information value is stored in a predetermined area of ​​RAM 20c, and the CPU 20a reads this stored value and displays it on the setting / performance indicator 97.

[0244] Next, in step S917, CPU20a restores the values ​​of all registers, and in step S918, clears the WDT count value, thus ending the main control timer interrupt processing.

[0245] Once the timer interrupt processing described above is complete, CPU20a executes the main loop processing (S123) until the next timer interrupt occurs.

[0246] <5. Regarding the transition of processing between in-domain and out-of-domain processing> [5-1. Regarding the area used and the area not used] Figure 21 is an explanatory diagram of the memory area set in the main control unit 20. Specifically, it is an explanatory diagram of the memory area set as ROM 20b and RAM 20c, which are accessible by the CPU 20a.

[0247] The memory accessible by the CPU 20a is divided into a first memory area (shaded area in the diagram) and a second memory area (textured area in the diagram). The first memory area is designated as the area for which the CPU 80a will place predetermined programs and data used in the progress of game operations. The second memory area is designated as the area for which programs and data permitted to be placed outside the first memory area will be placed. In this example, the only items permitted to be placed in the second memory area are the programs and data related to the management and display of the performance information mentioned above. Specifically, these include the programs and data related to the performance display monitor aggregation division process (S304) in the main loop processing (S120) shown in Figure 9, and the programs and data related to the performance display monitor display process (S916) in the main control side timer interrupt processing shown in Figure 18.

[0248] Here, the first memory area is called the "used area" because it is the area that is available for use in the game progression process. On the other hand, the second memory area is called the "outside the used area" because it is the area that is available for use in specific processes other than the game progression process. In the following, the area referred to as the "out-of-use area" as the second memory area may also be referred to as the "unused area." Furthermore, in the following explanation, when "in-use area" and "out-of-use area" are used, they mean "in-use area" and "out-of-use area," respectively, unless otherwise specified.

[0249] As shown in the diagram, the first memory area and the second memory area each contain a control area for storing the program, a data area for storing data used by the program, and an R / W area (Read / Write area) for storing various flags, timer values, etc., generated during the program's processing in a rewritable manner. The control area and data area correspond to areas within ROM20b, and the R / W area corresponds to an area within RAM20c.

[0250] Figure 22 is an explanatory diagram of the regulations established for the first and second memory regions. In each of the first and second memory areas, the program in the control area is permitted to access and update (record) data in the read / write area within its own area. On the other hand, in each of the first and second memory areas, the program in the control area is only permitted to access data in the read / write area of ​​the other memory area, and is not permitted to update it. For example, a program in the second memory area can only access a flag recorded in the read / write area of ​​the second memory area by the program in the first memory area, and cannot update it. Although not shown in the diagram, only programs within the same memory area are permitted to access the data in the data area. In other words, a program in the first memory area is not permitted to access data in the data area of ​​the second memory area, nor is a program in the second memory area permitted to access data in the data area of ​​the first memory area.

[0251] [5-2. Processing transition methods in previous examples] In the process in which the CPU 20a executes the processing described with reference to Figures 5 to 20, there is a processing step in which, while the processing of the program within the region is being executed, the processing of the program outside the region is called, and the process returns to the processing of the program within the region upon completion of the processing of the program outside the region. In other words, there is a processing transition between the program within the region and the program outside the region. A specific example of such a processing transition is the main loop processing (S120) shown in Figure 9, where after the random number update processing (processing of the program within the region) in step S302 is executed, the performance display monitor aggregation division processing (processing of the program outside the region) in step S304 is executed, and then the process transitions back to the random number update processing in step S302.

[0252] Here, we will first describe a method for transitioning between processing within and outside the domain, as described above, as an example of a prior example. Figure 23 shows the register configuration of CPU 20a in a previous example. As shown in the figure, the CPU 20a in the prior example is equipped with a PC (program counter) register 100, an I (interrupt) register 101, and an R (refresh) register 102, as well as a front register 103 and a back register 104, each consisting of multiple registers. The table register 103 includes the Q register 105, the A (accumulator) register 106, the F (flag) register 107, the B register 108, the C register 109, the D register 110, the E register 111, the H register 112, the L register 113, the IX register 114, the IY register 115, and the SP (stack pointer) register 116. The hidden register 104 includes the Q' register 105', A' register 106', F' register 107', B' register 108', C' register 109', D' register 110', E' register 111', H' register 112', L' register 113', IX' register 114', and IY' register 115'. Of these various registers, at least registers B108 through L113 and registers B'108' through L'113' are designated as general-purpose registers.

[0253] Referring to Figures 24 and 25, an example of a program related to processing transitions between the inside and outside of a region will be explained. Figure 24 shows an example of the program corresponding to the main loop processing of step S120 (especially the interrupt waiting part: see Figure 9) in the main control side main processing (Figure 5), and Figure 25 shows an example of the program related to the performance display monitor aggregation division processing (S304), which is an out-of-bounds program.

[0254] For confirmation, let's explain the main instructions among the various instructions used in the program. Here, "instructions" refers to instructions expressed as mnemonics in assembly language. "DI" is a command to disable interrupts, and "EI" is a command to enable interrupts. "PUSH" is an instruction that pushes (saves) the value of a specified register into the stack area of ​​memory (RAM20c), while "POP" is an instruction that retrieves (writes) the value from the stack area to a specified register. "LD" is a load instruction, which writes the value specified on the right-hand side to the location specified on the left-hand side after the "LD" instruction. For example, "LD R,n" (where R is a value that specifies a register and n is a value that specifies a memory address) is an instruction that writes the value at the memory address specified by n to the register specified by R. Similarly, "LD n,R" is an instruction that writes the value of the register specified by R to the memory address specified by n. "CALL" is a program call instruction, and "RET" is an instruction that returns control to the caller.

[0255] The lower part of Figure 24 (labeled "ZANYO_1" in the figure) shows the program for the interrupt waiting process in the main loop processing (S120). As can be seen by referring to Figure 9, in the main loop processing, the random number update process (step S302) and the performance display monitor aggregation division process are executed during this interrupt waiting period. First, in the interrupt waiting process, the DI instruction is used to disable interrupts. The reason for disabling interrupts here is to prevent the interrupt process from being executed during the random number update process that will be executed by the next instruction. It also serves to prevent the interrupt process from being executed while an out-of-bounds program is running, as will be discussed later. If an interrupt processing program, which is an in-bounds program, is executed while an out-of-bounds program is running, the interrupt processing program will access the work memory within the used area and update the memory. In other words, the memory within the area will be updated while the out-of-bounds program is running, so the interrupt processing is disabled.

[0256] Next, the command "CALL M_RNDJOB" is invoked and executed to update various random numbers.

[0257] The instruction "PUSH AF" following the instruction "CALL M_RNDJOB" saves the values ​​of register A 106 and register F 107 to memory. This instruction is executed because the contents of register F 107 change when "LD SP,n" is executed in the out-of-bounds program described later, so it is necessary to save the contents of register F 107.

[0258] The "CALL _SHKSHM" command, following the "PUSH AF" command mentioned above, invokes the out-of-bounds performance display monitor aggregation division process.

[0259] As shown in Figure 25, in the performance display monitor aggregate division process, first, the stack pointer is set to an address outside the used area using the instruction "LD SP,_ESTPNT". Then, the instructions "LD (_RBCBUF),BC", "LD (_RDEBUF),DE", and "LD (_RHLBUF),HL" in the figure are used to save all registers from register B 108 to register L 113. The various instructions following "LD (_RHLBUF),HL" perform processing to calculate values ​​as performance information.

[0260] In the diagram, the instructions "LD BC,(_RBCBUF)", "LD DE,(_RDEBUF)", and "LD HL,(_RHLBUF)" from two lines before the last line to four lines before the last line perform the process of restoring all registers, and the instruction "LD SP,_ISTPNT2" one line before the last line restores the stack pointer. Then, the "RET" instruction on the last line returns control to the caller, that is, it returns to the execution of the program within the memory area.

[0261] In response to the "RET" instruction mentioned above, the "POP AF" instruction following "CALL _SHKSHM" in Figure 24 is executed. This "POP AF" instruction restores the values ​​of register A 106 and register F 107. Next, "EI" enables interrupt processing, and "JR ZANYO_1" returns processing to the beginning of "ZANYO_1," resulting in a loop process that waits for interrupts.

[0262] In the previous example, since there is only one SP (stack pointer) register 116, it is assumed that the SP pointer 116 is shared between the program within the memory region and the program outside the memory region. Therefore, when transferring processing between the program within the memory region and the program outside the memory region, it is necessary to perform "PUSH AF" or "POP AF" operations. In other words, when calling a program outside the memory region from a program within the memory region, it is necessary to always write these "PUSH AF" or "POP AF" instructions. As mentioned above, the usable area is defined as the area where programs related to the progress of game operations are placed. However, in recent years, due to the increasing complexity of game operations, the program capacity and data capacity of the usable area have been increasing, and the usable area is becoming constrained. For this reason, there is a need to reduce the program capacity in the usable area.

[0263] [5-3. Processing Transition Method as an Embodiment] Figure 26 shows the register configuration of the CPU 20a in the embodiment. As shown in the figure, the CPU 20a of the embodiment includes a PC register 100, an I register 101, and an R register 102, as well as a first register bank 121, a second register bank 122, and an IFF (interrupt control flag) register 125. Here, a register bank is a group of registers consisting of multiple registers, including general-purpose registers. The first register bank 121 and the second register bank 122 each have a main register 123 and a sub-register 124. The main register 123 corresponds to the table register 103 shown in Figure 23 and has the Q register 105, A register 106, F register 107, B register 108, C register 109, D register 110, E register 111, H register 112, L register 113, IX register 114, IY register 115, and SP register 116. Sub-register 124 corresponds to the hidden register 104 shown in Figure 23, and includes the following registers: Q' register 105', A' register 106', F' register 107', B' register 108', C' register 109', D' register 110', E' register 111', H' register 112', L' register 113', IX' register 114', and IY' register 115'. Note that the main register 123 also has a U register 130, which will be explained in more detail later.

[0264] The IFF register 125 is a register for storing the interrupt control flag IFF. The interrupt control flag IFF is a flag that manages the state of interrupt processing, i.e., the interrupt control state, which is whether interrupt processing is enabled or disabled. In this example, two types of interrupt control flags IFF are used: "IFF1" and "IFF2". Accordingly, the IFF register 125 is capable of storing the interrupt control flags IFF1 and IFF2 individually. Here, of the interrupt control flags IFF1 and IFF2, only IFF1 is used as the reference value for the interrupt control state, while IFF2 is used auxiliaryly to manage the value of IFF1.

[0265] In this embodiment, as shown in Figure 26, a first register bank 121 and a second register bank 122 are provided, with the first register bank 121 used by the in-domain program and the second register bank 122 used by the out-of-domain program. That is, when transitioning from processing an in-domain program to processing an out-of-domain program, the register bank used is switched from the first register bank 121 to the second register bank 122. Conversely, when transitioning from processing an out-of-domain program to processing an in-domain program, the register bank used is switched from the second register bank 122 to the first register bank 121.

[0266] As described above, by providing a first register bank 121 and a second register bank 122, and using the first register bank 121 for in-area programs and the second register bank 122 for out-area programs, dedicated SP registers 116 can be used for in-area programs and out-of-area programs, eliminating the need to execute "PUSH AF" or "POP AF". Therefore, the program size of in-area programs can be reduced.

[0267] Furthermore, in this embodiment, "CALLEX" and "RETEX" are adopted as instructions that can be substituted for "CALL" and "RET". "CALLEX" is an instruction that calls an out-of-bounds program from an in-bounds program. Specifically, it combines the interrupt handling disable instruction (DI), the instruction to switch the register bank to be used (switching from the first register bank 121 to the second register bank 122), and the CALL instruction for the specified out-of-bounds program into a single instruction. "RETEX" is an instruction used to return from an out-of-bounds program to an in-bounds program. Specifically, it combines the following instructions into a single instruction: an instruction to switch the register bank to be used (switching from the second register bank 122 to the first register bank 121), an instruction to execute a process to return the interrupt control state (enabled / disabled) to the state immediately before the execution of the CALLEX instruction, and a RET instruction to return control to the caller.

[0268] Here, in order to enable the system to enter an interrupt-disabled state by "CALLEX" and to return the interrupt control state to the state immediately before the execution of the CALLEX instruction by "RETEX", it is stipulated that the interrupt control flag IFF should be updated as follows when "CALLEX", "RETEX", "DI", and "EI" are executed. Figure 27 is an explanatory diagram of the update rules for the interrupt control flag (IFF). As shown in the diagram, when the "DI" instruction is executed, both interrupt control flags IFF1 and IFF2 are set to "0" (disabled value), indicating that interrupts are disabled. On the other hand, when the "EI" instruction is executed, both interrupt control flags IFF1 and IFF2 are set to "1" (enabled value), indicating that interrupts are enabled. Furthermore, when the "CALLEX" instruction is executed, the interrupt control flag IFF1 is set to the forbidden value "0", while the interrupt control flag IFF2 maintains its value (i.e., does not change). In addition, when the "RETEX" instruction is executed, the value of the interrupt control flag IFF2 is assigned to the interrupt control flag IFF1. At this time, the value of the interrupt control flag IFF2 is maintained.

[0269] The interrupt control flag IFF is updated according to the rules described above, which results in the execution of the "CALLEX" instruction disabling interrupts, and the execution of the "RETEX" instruction returns the interrupt control state to the state it was in immediately before the execution of the CALLEX instruction.

[0270] Figures 28 and 29 illustrate programs as embodiments of applying "CALLEX" and "RETEX" to the programs related to processing transitions between the region and the region exemplified in Figures 24 and 25. In Figures 28 and 29, the commands that are omitted by applying the method as an embodiment, among the various commands shown in Figures 24 and 25, are shown grayed out.

[0271] As mentioned above, by providing the first register bank 121 and the second register bank 122, the "PUSH AF" command, which was required when calling an out-of-bounds program, and the "POP AF" command, which was required when returning from an out-of-bounds program, become unnecessary in programs within the region. This makes it possible to reduce the program size of programs within the domain.

[0272] Here, since "CALLEX" includes the "DI" instruction, in some cases a reduction in the number of "DI" instructions (a reduction in program size) can be obtained. In the example in Figure 24, the program is structured so that a random number update process is performed before the out-of-bounds program is called. Therefore, the "DI" instruction is executed before the random number update process, and the out-of-bounds program is called while interrupts are disabled. In such cases, it is unnecessary to execute the "DI" instruction for the out-of-bounds program call in the first place, so the reduction in the number of "DI" instructions obtained by applying "CALLEX" cannot be obtained. However, there may be cases where the program is structured to call an out-of-bounds program while interrupts are enabled. In such cases, the "DI" instruction will be executed before the out-of-bounds program is called by "CALL", so by applying "CALLEX", the number of "DI" instructions can be reduced, and a reduction in program size can be obtained.

[0273] In this embodiment, by providing a second register bank 122 for out-of-bounds areas, it becomes unnecessary to save and restore register values ​​when transitioning from an in-bounds program to an out-of-bounds program. Therefore, in the out-of-bounds program (Figure 29), it becomes unnecessary to write the instructions "LD (_RBCBUF),BC", "LD (_RDEBUF),DE", and "LD (_RHLBUF),HL" to save register values, the instructions "LD BC,(_RBCBUF)", "LD DE,(_RDEBUF)", and "LD HL,(_RHLBUF)" to restore the saved values, and the instruction "LD SP,_ISTPNT2" to restore the value of the stack pointer within the area.

[0274] As can be understood by referring to the program illustrated in Figure 28, in this embodiment, the "CALLEX" instruction is executed after the "DI" instruction but before the "EI" instruction is executed in the region program. This can be rephrased as the third instruction being executed after the second instruction but before the first instruction is executed, if we consider the "EI" instruction as the "first instruction," the "DI" instruction as the "second instruction," and the "CALLEX" instruction as the "third instruction."

[0275] When executing an out-of-bounds program, it is necessary to disable interrupts. Under this premise, if EI (the first instruction) is executed before CALLEX (the third instruction), the system will frequently switch between the interrupt-disabled and interrupt-enabled states. Specifically, when EI is performed before CALLEX, the interrupt state is disabled at the first DI in the loop processing → random number update processing is executed → interrupt state is enabled by EI → interrupt state is disabled by CALLEX → interrupt state is enabled by RETEX. In other words, the number of switches within the main loop processing is 3. On the other hand, in the embodiment where EI is performed after CALLEX, the interrupt state is continuously maintained from the first DI until the execution of the program outside the region and then until the program inside the region is returned, and then it switches to the interrupt state by EI. In other words, the number of switches within the main loop processing is 1. Therefore, if EI is performed before CALLEX, the control state will switch frequently, impairing the stability of the control. However, according to the embodiment in which EI is performed after CALLEX, the number of control state switches can be reduced, thereby improving the stability of the control.

[0276] Furthermore, according to the transition method as described above, PUSH and POP processing is unnecessary, thus improving processing speed.

[0277] Figures 30 and 31 illustrate programs when CALLEX and RETEX are applied to the out-of-bounds program call in the main control-side timer interrupt processing shown in Figure 18. Figure 30 illustrates the program for the main control-side timer interrupt processing (in-bounds program), and Figure 31 illustrates the program corresponding to the performance display monitor display processing in step S916 (out-of-bounds program). Note that in Figure 30, for illustrative purposes, the instruction corresponding to the WDT clearing process in step S918 is omitted. Also, in Figures 30, 31, and subsequent figures up to Figure 63, instructions that are omitted due to the application of CALLEX and RETEX are shown in gray, similar to Figures 28 and 29.

[0278] In Figure 30, if the CALL instruction is used instead of CALLEX to call the performance display monitor processing, which is an out-of-bounds program (i.e., the register configuration in Figure 23 is adopted), the required instructions are "PUSH AF" → "DI" → "CALL _SHYMT" → "POP AF" → "EI" → "RETI". However, if CALLEX is used (i.e., the register configuration in Figure 26 is adopted), the required instructions are "CALLEX _SHYMT" → "EI" → "RETI", and the program size of the in-bounds program can be reduced by eliminating the "PUSH AF", "DI", and "POP AF" instructions.

[0279] Furthermore, in the performance display monitor processing program shown in Figure 31, the stack pointer is first set to specify an address outside the used area by the instruction "LD SP,_ESTPNT". In previous examples that used CALL or RET, the instructions "LD (_RBCBUF),BC", "LD (_RDEBUF),DE", and "LD (_RHLBUF),HL" were required as instructions after "LD SP,_ESTPNT" to save the register values, but these instructions are omitted in this embodiment. In the diagram, each instruction from "Initial RWM Determination" to "Initial Display Timer Subtraction Processing" is an instruction that implements the process of displaying performance information values ​​on the setting / performance indicator 97. After these instructions, in the previous example, the instructions "LD BC,(_RBCBUF)", "LD DE,(_RDEBUF)", and "LD HL,(_RHLBUF)" were required to restore the saved values ​​to the registers, and the instruction "LD SP,_ISTPNT2" was required to restore the stack pointer in the area, but in this embodiment, these instructions are also omitted. The "RETEX" command on the last line switches the register bank used from the second register bank 122 to the first register bank 121, restores the interrupt control state (in this case, maintains the disabled state), and returns processing to the caller.

[0280] Note that the "EI" instruction immediately preceding the last line in Figure 30 is not mandatory. This is because if the interrupt control state immediately before the execution of the CALLEX instruction in Figure 30 is "interrupt enabled," then the interrupt control state when returning to the program within the memory area by executing the RETEX instruction shown in Figure 31 will also be "interrupt enabled."

[0281] Here, in Figures 29 and 31, the first line of the out-of-bounds program executes the instruction "LD SP,_ESTPNT," that is, it executes the process of storing the address value of the stack memory used by the out-of-bounds program (the stored value of "ESTPNT" in memory) in the SP register 116 of the second register bank 122. This can be rephrased as follows: In other words, there are cases where the out-of-bounds program is called by specifying the first address using the "CALLEX" instruction in the in-bounds program ("CALLEX _SHKSHM" in Figure 28) and cases where it is called by specifying the second address ("CALLEX _SHYMT" in Figure 30). In both cases, the out-of-bounds program executes an instruction (the fifth instruction) that stores the common stack memory address information (the stored value of "ESTPNT") in the SP register 116 of the second register bank 122.

[0282] This makes it possible to reset the value of the stack pointer used by the out-of-bounds program each time the out-of-bounds program is called. Therefore, even if the value stored in the second stack pointer changes due to some malfunction after the execution of a certain program outside the memory region, the correct value of the stack pointer can be reset when another program outside the memory region is executed, thereby improving the stability of stack processing by programs outside the memory region.

[0283] Furthermore, since the value of the stack pointer that should be set at the start of processing of an out-of-bounds program is a fixed value of "ESTPNT", it is not necessary to execute "LD SP,_ESTPNT" every time processing of an out-of-bounds program begins. Specifically, the instruction "LD SP,_ESTPNT" only needs to be executed at least when the out-of-bounds program is executed for the first time each time the gaming machine is started. For example, if the out-of-bounds program in Figure 29 is executed before the out-of-bounds program in Figure 31, then the instruction "LD SP,_ESTPNT" only needs to be executed by the out-of-bounds program in Figure 29. Conversely, if the out-of-bounds program in Figure 31 is executed before the out-of-bounds program in Figure 29, then "LD SP,_ESTPNT" only needs to be executed by the out-of-bounds program in Figure 31. This can be rephrased as follows: In a local program, when calling an out-of-bounds program by executing the CALLEX instruction, there are two cases: one where the first address of the out-of-bounds program is specified (when calling one of the out-of-bounds programs in Figure 29 or Figure 31), and another where the second address is specified at a later timing (when calling the other out-of-bounds program in Figure 29 or Figure 31). In the out-of-bounds program, only when the first address is called, an instruction (the sixth instruction) is executed to store the address information of the common stack memory in the second stack pointer.

[0284] As mentioned above, the address information of the stack memory that should be set at the start of processing of an out-of-bounds program is fixed address information. Therefore, if the program at the second address is executed after the program at the first address as an out-of-bounds program, the storage of address information for the second stack pointer only needs to be performed in the program at the first address that is executed first. Therefore, by executing an instruction that stores the address information of a predetermined stack memory in the second stack pointer only when the first address is called as described above, the efficiency of processing can be improved.

[0285] [5-4. Another example of a program] Figures 32 and 33 show alternative examples of the programs shown in Figures 28 and 29. Specifically, they show an alternative example of the program corresponding to the part of the main loop processing (S120) that calls an out-of-bounds program (Figure 32), and an alternative example of the out-of-bounds program called by the processing in Figure 32 (Figure 33).

[0286] Figures 34 and 35 show alternative examples of the programs shown in Figures 30 and 31, namely, an alternative example of the main control-side timer interrupt processing program (Figure 34) and an alternative example of an out-of-bounds program called by the timer interrupt processing (Figure 35).

[0287] In addition, in the out-of-bounds programs shown in Figures 33 and 35, the memory address where the value to be set in the second stack pointer (SP register 116 in the second register bank 122) is stored is defined as "@RWM2SP" instead of "ESTPNT" as in Figures 29 and 31. As can be seen by referring to the "LD SP,@RWM2SP" instruction in Figures 33 and 35, this example shows how to set common address information as the stored value of "@RWM2SP" in the second stack pointer each time an out-of-bounds program is executed. However, even in this case, it is also possible to ensure that the storage of address information for the second stack pointer is performed only in the out-of-bounds program that is executed first.

[0288] Figures 36 to 53 show examples of programs when the processing transition method as an embodiment is applied to the processing of the main control unit in a slot machine. Figures 36, 38, 40, 42, 44, 46, 48, 50, and 52 show examples of programs for various processes, including calls to programs outside the domain, that are executed by the main control unit of a slot machine. Specifically, Figure 36 shows the initial setup process when the power is turned on, Figure 38 shows the game execution process, Figure 40 shows the process in response to the insertion of game tokens and the operation of the start lever, Figure 42 shows the RMW setting process at the start of the game, Figure 44 shows the process of updating information related to the payout ratio monitor display, Figure 46 shows the setting change process, Figure 48 shows the condition device signal output process, Figure 50 shows the game token insertion process, and Figure 52 shows the game token insertion error process. Figures 37, 39, 41, 43, 45, 47, 49, 51, and 53 illustrate programs outside the domain that are called by the CALLEX instruction in the processing of the various in-domain programs described above. Specifically, Figure 37 illustrates the program for out-of-domain work area processing 3, Figure 39 for re-play state identification signal output processing, Figure 41 for condition device signal output clear processing, Figure 43 for condition device signal output processing, Figure 45 for role ratio monitor control processing, Figure 47 for out-of-domain work area processing 1, Figure 49 for condition device signal output monitoring processing, Figure 51 for drowsiness check processing, and Figure 53 for out-of-domain work area processing 2.

[0289] Furthermore, for the programs within the specified region exemplified here, the "(DI guarantee)" shown in Figures 36, 38, and 40, for example, means that it is guaranteed that the interrupt-disabled state is guaranteed at least on the line in which the (DI guarantee) is written (that is, it is guaranteed that a DI instruction has been executed on any line prior to that line).

[0290] Of the region-specific programs exemplified here, the region-specific programs shown in Figures 38, 40, and 48 are examples of programs that execute the "CALLEX" instruction after executing the "DI" instruction and before executing the "EI" instruction. This prevents frequent switching of the interrupt control state, thereby improving control stability.

[0291] In particular, in the program shown in Figure 48, two CALLEX instructions are written consecutively. In this case, if the "CALLEX" instruction were not executed after the "DI" instruction and before the "EI" instruction, but rather before the "CALLEX" instruction, the number of interrupt control state switches would be 5. Specifically, this would be DI → EI → CALLEX (switch to interrupt disabled state) → RETEX (return to interrupt enabled state) → CALLEX (switch to interrupt disabled state) → RETEX (return to interrupt enabled state), for a total of 6 switches. On the other hand, if the method of executing the "CALLEX" instruction after the "DI" instruction and before the "EI" instruction is adopted, as in the embodiment, the number of interrupt control state switches can be reduced to 1, thereby improving control stability.

[0292] As can be seen by referring to "LD SP,CMN_STACK" shown in the first row of each of the figures 37, 39, 41, 43, 45, 47, 49, 51, and 53, the storage address of the stack pointer for the unused area (the value to be set in the SP register 116 in the second register bank 122) in this case is defined as "CMN_STACK". As can be seen from the fact that the instruction "LD SP,CMN_STACK" is included in various figures such as Figure 37, this example shows how to set common address information in the second stack pointer each time an out-of-bounds program is executed.

[0293] In the case of slot machines, there are three or more types of out-of-bounds programs that can be called from programs within the local area. When there are three or more types of out-of-bounds programs that can be called, it is possible to ensure that, for at least two of them, the storage of address information for the second stack pointer is performed only in the out-of-bounds program that is executed first. In this case, in order to improve processing efficiency, it is desirable that the storage of address information for the second stack pointer be performed only in the out-of-bounds program that is executed first among the three or more out-of-bounds programs.

[0294] [5-5. Variations of the program] Next, we will explain some variations of the program with reference to Figures 54 to 63. In the explanations so far, we have given examples that include register bank switching instructions used for CALLEX and RETEX, but it is also possible to define register bank switching instructions as independent instructions. Here, we will give an example in which the register bank switching instruction (mnemonic) is defined as "BANKF", but the specific name of the switching instruction is not limited to "BANKF".

[0295] When using the independent register bank switching instruction "BANKF", the transition of processing between the area and the area outside the area will require one "CALL" instruction, two "BANKF" instructions, and one "RET" instruction. Figures 54, 56, 58, and 60 show various program examples that can be considered as examples of applying the "BANKF" instruction to the power-on initialization process exemplified in Figure 36. Figures 55, 57, 59, and 61 show examples of out-of-area programs (out-of-area work area processing 3) called by the in-area programs in Figures 54, 56, 58, and 60, respectively.

[0296] The example shown in Figures 54 and 55 is one in which the program outside the domain executes a "BANKF" instruction to switch the register bank from the first register bank 121 for use within the domain to the second register bank 122 for use outside the domain, and the program inside the domain executes a "BANKF" instruction to switch from the second register bank 122 for use outside the domain to the first register bank 121 for use within the domain. In this case, the program within the region contains a "CALL" instruction (CALL O_CLRWM3) to call the program outside the region, as shown in Figure 54, followed by a "BANKF" instruction to switch the register bank from the second register bank 122 to the first register bank 121. In the program outside the region, as shown in Figure 55, the first line contains a "BANKF" instruction to switch the register bank from the first register bank 121 to the second register bank 122, and the last line contains a "RET" instruction.

[0297] In the out-of-bounds program shown in Figure 55, the instruction "LD SP,CMN_STACK" (a set of the second stack pointer) is written on the second line. However, if the out-of-bounds program executes a "BANKF" instruction to switch from the first register bank 121 to the second register bank 122, the "BANKF" instruction is executed before the "LD SP,CMN_STACK" instruction.

[0298] The example shown in Figures 56 and 57 illustrates how both the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 and the "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 are executed by the program within the memory area. In this case, as shown in Figure 56, the program within the region contains a "BANKF" instruction on the line immediately preceding the "CALL" instruction to switch from the first register bank 121 to the second register bank 122, and a "BANKF" instruction on the line following the "CALL" instruction to switch from the second register bank 122 to the first register bank 121.

[0299] The example shown in Figures 58 and 59 illustrates a case where the "BANKF" instruction to switch from the first register bank 121 to the second register bank 122 is executed by the program within the memory region, and the "BANKF" instruction to switch from the second register bank 122 to the first register bank 121 is executed by the program outside the memory region. As shown in Figure 58, in this case, the program within the region contains a "BANKF" instruction on the line immediately preceding the "CALL" instruction to switch from the first register bank 121 to the second register bank 122, while the program outside the region contains a "BANKF" instruction on the line immediately preceding the "RET" instruction to switch from the second register bank 122 to the first register bank 121, as shown in Figure 59.

[0300] The example shown in Figures 60 and 61 is one in which both the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 and the "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 are performed by the out-of-bounds program. As shown in Figure 61, in this case, the out-of-bounds program contains the "BANKF" instruction for switching from the first register bank 121 to the second register bank 122 on the first line, and the "BANKF" instruction for switching from the second register bank 122 to the first register bank 121 on the line immediately preceding the "RET" instruction.

[0301] By defining the "BANKF" instruction as described above, it becomes possible to provide alternatives to CALLEX and RETEX (CALL and BANKF, or RET and BANKF) as instructions for achieving processing transitions between areas within and outside the memory region, thereby increasing the flexibility of program creation.

[0302] Here, it is not mandatory to apply CALLEX and RETEX to all processing transitions between the in-domain and out-domain areas. For example, in an in-domain program, depending on the processing content of the program before and after a call instruction to an out-domain program, there are situations where CALL and RET can be used as before instead of CALLEX and RETEX. For instance, in situations where there is processing to be performed in an interrupt-disabled state after returning to the in-domain program via a return instruction, it is not necessary to execute EI upon returning to the in-domain, so even if CALL and RET are used instead of CALLEX and RETEX, an appropriate interrupt control state can be achieved.

[0303] Figures 62 and 63 illustrate program examples both within and outside the domain when using CALL and RET in such situations. In addition, Figures 62 and 63 show program examples where the second register bank 122 for out-of-bounds memory is not used. However, by using "BUNKF" as explained in Figures 54 and 55, for example, it is possible to omit instructions for saving and restoring the AF ("PUSH AF", "POP AF") in programs within the memory area, and also omit instructions for saving and restoring the stack pointer (the stack pointer for the memory area) ("LD (W_STKBAK),SP", "LD SP,(W_STKBAK)") and instructions for saving and restoring all registers ("PUSH ALL", "EX AF,AF'", "EXX", "PUSH GPR", "POP GPR", "EX AF,AF'", "EXX", "POP ALL") in programs outside the memory area.

[0304] [5-6. Other variations] In the explanation so far, we have given an example where, when a program within a region calls a program outside that region, CALLEX (third instruction) is executed after DI (second instruction) but before EI (first instruction). However, it is also possible to execute CALLEX after EI, or in other words, execute EI before CALLEX. By executing EI before executing CALLEX, the duration of the interrupt-disabled state can be shortened. In other words, processing delays caused by the inability to perform interrupt handling can be suppressed.

[0305] In this example, in the gaming machine 1, the prize information is updated during the timer interrupt processing (see the prize ball management processing in S908). Among the various out-of-bounds programs exemplified, the performance display monitor aggregation division processing shown in Figure 29, etc., calculates the performance information value using the prize information updated in this interrupt processing. Therefore, if the method of executing EI before CALLEX is adopted when calling such a performance display monitor aggregation division processing, the calculation of performance information in the out-of-bounds program can be performed using the prize information updated immediately before, which is preferable.

[0306] <6. About the Q and U registers> Next, we will explain the Q register (Q register 105 and Q' register 105') and the U register 130. First, we will explain the memory address space of the CPU 20a in the main control unit 20, referring to the memory map in Figure 64. As shown in the diagram, the memory address space for CPU20a is allocated a total of 65,536 bytes, from address 0000h (where h is a hexadecimal number) to address FFFFh. The area from address 0000h to address 3FFFh, comprising 16,384 bytes (16k bytes), is designated as the internal ROM area, while the area from address F000h to address F3FFh, comprising 1,024 bytes (1k bytes), is designated as the internal RAM area. The area between the internal ROM and internal RAM regions, from address 4000h to address EFFFh, is considered an unused area.

[0307] The area from address F400h to FDFFh is considered unused, the area from address FE00h to FEFFh is the area for internal register 1, and the area from address FF00h to address FFCFh is the area for internal register 2.

[0308] The region from address FFD0f to address FFFFh is designated as the XCS decode area. In this example, CPU 20a employs memory-mapped I / O as a method for managing data input / output. As is well known, memory-mapped I / O is a method of allocating I / O registers to the same address space as data memory. In this example, the XCS decode area is allocated a memory area corresponding to the I / O registers. In this sense, the XCS decode area will be referred to as the "input / output port area (I / O port area)" below.

[0309] As explained with reference to Figure 21 above, the memory area accessible by the CPU 20a is divided into a used area as the first memory area and an unused area as the second memory area. Figure 64 shows the division between the used and unused areas in the built-in RAM area. As shown in the figure, in the built-in RAM area in this example, the 512-byte area from address F000h to address F1FFh is the used area, and the 256-byte area from address F200h to address F2FFh is the unused area.

[0310] Based on the above, we will now explain the Q register and the "LDQ" instruction, which is related to the Q register. The Q register 105 and the Q' register 105' are registers that store the higher values ​​of some addresses handled by the "LDQ" instruction. In this example, these Q register 105 and Q' register 105' are 8-bit (1-byte) registers.

[0311] The "LDQ" instruction is written as, for example, "LDQ R,m" (where R is the value that specifies a register and m is the value that specifies a memory address) or "LDQ m,R", and functions as a load instruction similar to the "LD" instruction. Basically, it is an instruction that writes the value specified on the right side to the location specified on the left side after the "LDQ" instruction. The difference from the "LD" instruction is that only the lower value of the memory address needs to be specified as the value of "m". In other words, the "LDQ" instruction is an instruction that accesses an address where the value written as "m" is the lower value and the value stored in Q register 105 or Q' register 105' is the upper value. Specifically, in the case of "LDQ R,m", it is an instruction that writes the value stored in memory at the address where the value of "m" is the lower value and the value stored in Q register 105 or Q' register 105' is the upper value to the register specified by "R". Furthermore, if the instruction is "LDQ m,R", it will write the value of the register specified by "R" to a memory address where the value of "m" is the lower value and the value stored in Q register 105 or Q' register 105' is the upper value.

[0312] The Q register is a register provided to implement such "LDQ" instructions. By providing the Q register, it becomes unnecessary for the program to specify the higher values ​​of addresses, thereby reducing the program size.

[0313] In this example, the "LDQ" instruction described above is applied to access the used area in the built-in RAM region shown in Figure 64. Therefore, "F0h" and "F1h" are stored in the Q register 105 and the Q' register 105', respectively. As shown in Figure 64, the usable area in the built-in RAM is set to the region from address F000h to address F1FFh. In other words, this usable area is larger than 256 bytes, which can be covered by the lower byte (8 bits) of the address value. Therefore, if only one Q register is provided, the "LDQ" instruction described above can only be applied to the region where the upper address value in the usable area is either "F0h" or "F1h". In this example, by providing two Q registers, Q register 105 and Q' register 105', the "LDQ" instruction can be applied to any address in the used area of ​​the built-in RAM.

[0314] In this example, the storage of "F0h" and "F1h" as described above is performed not only for the Q register 105 and Q' register 105' in the first register bank 121, but also for the Q register 105 and Q' register 105' in the second register bank 122. The process of storing "F0h" and "F1h" for these Q registers 105 and Q' register 105' is automatically executed as an initial value setting process for the Q registers 105 and Q' register 105' when the CPU 20a is started after a reset. Alternatively, the storage of "F0h" and "F1h" for these Q register 105 and Q' register 105' can be performed, for example, in the "startup settings processing" (S206) in the "initial setup processing" (S101).

[0315] As mentioned above, the second register bank 122 is a group of registers used by programs outside the designated area. As described above, by storing "F0h" and "F1h" respectively in the Q register 105 and Q' register 105' of the second register bank 122, the "LDQ" instruction can be used even when an out-of-bounds program references stored data in the used area of ​​the built-in RAM. In other words, the program size can be reduced by using the "LDQ" instruction even for out-of-bounds programs. For clarification, it should be noted that programs outside the designated area are not permitted to update data in the area they are using, but they are permitted to access it (see Figure 22).

[0316] For actual examples of the use of the "LDQ" instruction, please refer to Figures 36, 39, 40, 42, 43, 46, and 50. Of these, the "LDQ" instruction shown in Figures 39 and 43 is an instruction that accesses the address of the memory area when an out-of-bounds program is being executed.

[0317] In order to properly access the used area of ​​the built-in RAM using the "LDQ" instruction, it is necessary to switch the Q register referenced by the "LDQ" instruction depending on the address of the target being accessed within that used area. Specifically, it is necessary to appropriately switch between referencing Q register 105 and Q' register 105'.

[0318] In this example, such switching of the Q register is achieved by the "EX" instruction. Specifically, it is achieved by the instruction "EX Q,Q'". In this example, the "EX Q,Q'" instruction is considered to be an instruction that toggles the Q register referenced by the "LDQ" instruction between Q register 105 and Q' register 105'. That is, in response to the "EX Q,Q'" instruction when the referenced Q register = Q register 105, the referenced Q register is switched to Q' register 105'. Also, in response to the "EX Q,Q'" instruction when the referenced Q register = Q' register 105', the referenced Q register is switched to Q register 105.

[0319] In the above example, the area to which the "LDQ" instruction applies (i.e., the area of ​​the built-in RAM used in this example) is 256 × 2 = 512 bytes, and two Q registers are provided accordingly. However, the area to which the "LDQ" instruction applies can be larger than 512 bytes. In that case, by setting the number of Q registers to three or more, the "LDQ" instruction can be used when accessing any address within the target area.

[0320] Next, we will explain the U register 130. The U register 130 is a register that stores the higher address values ​​of the input / output port area shown in Figure 64. Specifically, in this example, "FFh" is stored in the U register 130. By providing this U register 130, it becomes possible to eliminate the need to write the higher value of the access destination address in the program when specifying the access destination address of the input / output port area in input / output instructions ("IN" instruction or "OUT" instruction).

[0321] In this example, memory-mapped I / O is used, but the commands related to data input and output are the same "IN" and "OUT" commands used when port-mapped I / O is employed (see, for example, Figures 38, 40, and 48). Specifically, the "IN" instruction in this case is written as "IN r,m", and this instruction writes the value stored in the I / O port area address (i.e., a virtual I / O register) to the register specified by "r", with the value specified by "m" as the lower value and the value stored in U register 130 as the upper value. Similarly, the "OUT" instruction is written as "OUT m,r", and this instruction writes the value stored in the register specified by "r" to the address in the I / O port area address, with the value specified by "m" as the lower value and the value stored in U register 130 as the upper value. As can be understood from the above explanation of the "IN" and "OUT" instructions, when memory-mapped I / O is adopted, the "LD" instruction can also be used as an instruction related to data input and output.

[0322] As shown in Figure 26, in this example, only one U register 130 is provided in the first register bank 121 and only one in the second register bank 122. Specifically, in both the first register bank 121 and the second register bank 122, the U register 130 is provided as one of the main registers 123. By providing a U register 130 for the second register bank 122, it becomes possible to access the input / output port area using the higher address value stored in the U register 130, even when executing programs outside the designated area. In other words, it becomes possible to eliminate the need to specify the higher address value of the access destination in "IN" and "OUT" instructions, even when executing programs outside the designated area.

[0323] As mentioned above, the input / output port area is defined as the region from address FFD0h to address FFFFh, with a size of 48 bytes. In other words, it is the size of the region that can be covered by the lower end of the address. Therefore, in both the first register bank 121 and the second register bank 122, the number of U registers 130 is set to a single value.

[0324] Here, as mentioned above, for the Q register, a common value is stored for each of the first register bank 121 and the second register bank 122, specifically for Q register 105 and Q' register 105'. Similarly, for the U register 130, a common value is stored for each of the first register bank 121 and the second register bank 122. Specifically in this example, "FFh" is stored in each of the U registers 130. This process of storing "FFh" in the U register 130 is automatically executed when the CPU 20a is started up after a reset, as part of the process of setting the initial value for the U register 130. Alternatively, the process of storing "FFh" in the U register 130 can be performed, for example, in the "startup settings processing" (S206) in the "initial setup processing" (S101).

[0325] In the explanation of the Q register mentioned above, it was stated that the "EX" instruction is used when accessing a region with a different upper-order address value. However, using the "EX" instruction is not mandatory, and in some cases, the upper-order value of the target address can be written into the program to perform the access. For example, when accessing the address with the higher value "F1h" while Q register 105 is selected as the Q register to be used, instead of switching the Q register to be used to Q' register 105' with the "EX" instruction, the program may include address information that includes the higher value "F1h" as the access destination address information. Alternatively, when accessing the address with the higher value "F0h" while Q' register 105' is selected as the Q register to be used, instead of switching the Q register to be used to Q register 105 with the "EX" instruction, the program may include address information that includes the higher value "F0h" as the access destination address information. In the former case, the Q register is used when accessing the address of the higher value "F0h," but not when accessing the address of the higher value "F1h." In the latter case, the Q register is used when accessing the address of the higher value "F1h," but not when accessing the address of the higher value "F0h." In other words, in these cases, the Q register may or may not be used when accessing the memory area in use (i.e., the target area in memory). On the other hand, since register U 130 targets only the region with the upper address value "FFh", it will always be used when accessing the target region in memory.

[0326] <7. Summary of Embodiments> As described above, the first gaming machine as an embodiment comprises a first register group (first register bank 121) and a second register group (second register bank 122), each consisting of multiple general-purpose registers, a first interrupt management register (IFF1 of IFF register 125), and a second interrupt management register (IFF2 of IFF register 125). Furthermore, there is a first instruction ("EI" instruction) that writes enable values ​​to the first and second interrupt management registers, a second instruction ("DI" instruction) that writes prohibition values ​​to the first and second interrupt management registers, a third instruction ("CALLEX" instruction) used when calling an out-of-bounds program from an in-bounds program, and a fourth instruction ("RETEX" instruction) used when returning to an in-bounds program from an out-of-bounds program. Furthermore, the third instruction can execute a process to write a forbidden value to the first interrupt management register and switch the set of registers used from the first set of registers to the second set of registers before calling an out-of-bounds program, and the fourth instruction can execute a process to overwrite the value of the second interrupt management register with the first interrupt management register and switch the set of registers used from the second set of registers to the first set of registers before returning to the in-bounds program. Furthermore, within the program's domain, the third instruction is executed after the second instruction is executed, but before the first instruction is executed.

[0327] When executing an out-of-bounds program, it is necessary to disable interrupts. Therefore, if the first instruction is executed before the third instruction, the interrupt-disabled and interrupt-enabled states will switch frequently. In contrast, if the third instruction is executed after the second instruction but before the first instruction, as described above, the interrupt-disabled state is maintained while calling the out-of-bounds program and returning to the in-bounds program, thus reducing the number of interrupt control state switches. Therefore, the number of times the control state switches can be reduced, and the stability of the control can be improved.

[0328] Furthermore, in the first gaming machine as an embodiment, the first register group has a first stack pointer (SP register 116 of the first register bank 121) that stores the stack pointer, and the second register group has a second stack pointer (SP register 116 of the second register bank 122) that stores the stack pointer. The first stack pointer stores the address information of the stack memory used by the program within the region, and the second stack pointer stores the address information of the stack memory used by the program outside the region. When the program within the region calls the program outside the region by executing the third instruction, it may call the program by specifying the first address of the program outside the region or by specifying the second address. In the program outside the region, in either case, whether the first address or the second address is called, the fifth instruction is executed to store the address information of the common stack memory in the second stack pointer.

[0329] This makes it possible to reset the value of the stack pointer used by the out-of-bounds program each time the out-of-bounds program is called. Therefore, even if the value stored in the second stack pointer changes due to some malfunction after the execution of a certain program outside the memory region, the correct value of the stack pointer can be reset when another program outside the memory region is executed, thereby improving the stability of stack processing by programs outside the memory region.

[0330] Furthermore, in the first gaming machine as an embodiment, the first register group has a first stack pointer that stores a stack pointer, and the second register group has a second stack pointer that stores a stack pointer. The first stack pointer stores address information of the stack memory used by the program within the region, and the second stack pointer stores address information of the stack memory used by the program outside the region. When the program within the region executes the third instruction to call the program outside the region, it may either call the program by specifying the first address of the program outside the region, or it may call it by specifying the second address at a later timing. In the program outside the region, only when the first address is called, the sixth instruction is executed to store predetermined stack memory address information in the second stack pointer.

[0331] Since the address information of the stack memory that should be set for the second stack pointer at the start of processing of an out-of-bounds program is fixed address information, if the program at the second address is executed after the program at the first address as an out-of-bounds program, the storage of the address information for the second stack pointer only needs to be performed by the program at the first address, which is executed first. Therefore, by executing an instruction that stores the address information of a predetermined stack memory in the second stack pointer only when the first address is called as described above, the efficiency of processing can be improved.

[0332] The second gaming machine, as an embodiment, includes control means for controlling the progress of the game, and the control means has an accessible memory address space and at least one register group (register bank) which includes multiple general-purpose registers and multiple high-value registers, which are registers that store the high-values ​​of the addresses of the storage means used in some instructions. The memory address space consists of a first region (the "internal RAM" region) with a predetermined size, and a second region (the "input / output port area") which is different from the first region and has a smaller size than the predetermined size. The high-value registers consist of a first-kind high-value register (Q register) associated with the first region and a second-kind high-value register (U register) that stores the high-value of addresses in the second region. In the register group, there are multiple first-kind high-value registers and one second-kind high-value register. The multiple first-kind high-value registers in the register group include a first first-kind high-value register (Q register 105) and a second first-kind high-value register (Q' register 105') that stores a value consecutive to the value stored in the first first-kind high-value register.

[0333] By providing high-value registers, when accessing required addresses in the first or second memory area, it becomes possible to use the high-values ​​stored in these registers, eliminating the need to write the high-values ​​of those addresses in the program. In other words, it becomes possible to reduce the program size. However, depending on the number of bytes in the lower value of the address, it may not be possible to cover the entire area being accessed. For example, if the size of the area that can be covered by the lower value of the address is 256 bytes (i.e., lower value of address = 1 byte), and the size of the first memory area exceeds 256 bytes, then the lower value of the address cannot cover the entire first memory area. In this case, it is necessary to use different high-values ​​of the address for the area within 256 bytes and the area exceeding 256 bytes in the first memory area. For this reason, at least a first-kind high-value register and a second first-kind high-value register that stores a value consecutive to the value stored in the first first-kind high-value register are provided. This makes it possible to access any address in the first region using the higher value stored in the higher value register, eliminating the need to specify the higher value of the target address in the program. As for the second region, since it is smaller than a predetermined size, even if there is only one second-kind higher value register, it is still possible to eliminate the need to specify the higher value of the target address in the program. Therefore, by using a configuration with multiple first-class high-value registers and one second-class high-value register, as described above, the program size can be reduced.

[0334] Furthermore, in the second gaming machine as an embodiment, the second region is a region to which the input / output registers of the control means are allocated.

[0335] This enables the use of memory-mapped I / O. Memory-mapped I / O eliminates the need for hardware I / O registers, allowing for simplified internal circuitry in the control system, resulting in faster processing and lower costs.

[0336] Furthermore, in the second gaming machine as an embodiment, the first region includes a usable region which is a region usable by an in-region program and an unused region which is a region usable by an out-region program. The usable region consists of two regions with consecutive high-order addresses, and the unused region is a region with high-order addresses different from those of the usable region. The system includes a group of registers, at least a first group of registers used by the in-region program, and the first group of registers includes the first high-order register of the first kind and the second high-order register of the first kind.

[0337] This makes it possible to access any address within the memory area using the high-value address stored in one of the two first-kind high-value registers. In other words, it eliminates the need to specify the high-value address of the target address in the program within the memory area. Therefore, it is possible to reduce the program size in the used area.

[0338] Furthermore, in the second gaming machine as an embodiment, the first region includes a usable region which is a region usable by an in-region program and an unused region which is a region usable by an out-region program. The register group includes two groups: a first register group used by the in-region program and a second register group used by the out-region program. Each of the first and second register groups has a first type high-value register, a second type high-value register, and a second type high-value register. In each of the first and second register groups, a common value is stored for the first type high-value register, the second type high-value register, and the second type high-value register, respectively.

[0339] In other words, the two first-kind high-value registers and the single second-kind high-value register in the second register group store the same values ​​as in the first register group. This makes it possible to use the high-address values ​​stored in the first-kind high-value registers and second-kind high-value registers when accessing the first or second memory regions during the execution of an out-of-bounds program (i.e., when using the second register group). In short, it becomes possible to eliminate the need to specify high-address values ​​in instructions for accessing the first or second memory regions, even for out-of-bounds programs. Therefore, it is possible to prevent the size of programs outside the designated area from unnecessarily expanding. [Explanation of symbols]

[0340] 1. Pachinko game machine 13. Performance Button 15a D-pad 15b Confirm button 20 Main control board (main control unit) 20a CPU 20b ROM 20c RAM 24. Performance control board (performance control unit) 24a CPU 24b ROM 24c RAM 36M main LCD display 36S sub-LCD display device 38a, 38b Special Pattern Display Device 45 Decorative Lamps 45a Optical display device 46 speakers 46a Sound Generator 61 Front door open sensor 83 Handle Sensor 94 Setting Key Switches 97 Settings / Performance Display 98 RAM Clear Switch 100 PC (Program Counter) Registers 105 Q Register 105' Q' register 116 SP (Stack Pointer) Registers 121 First Register Bank 122 Second Register Bank 125 IFF (Interrupt Control Flag) Register 130 U register

Claims

[Claim 1] Equipped with a control means for controlling games, The control means It has an accessible memory address space, The memory address space includes at least one register group including a plurality of general-purpose registers and a plurality of upper-value registers that store upper values ​​of addresses in the memory address space handled by some instructions, the high-value registers include a first-type high-value register and a second-type high-value register, a first upper value is stored in the first type upper value register, and a second upper value different from the first upper value is stored in the second type upper value register; When a first instruction is executed, the first high value in the first type high value register is referenced, and when a second instruction different from the first instruction is executed, the second high value in the second type high value register is referenced. Gaming machine.

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