Transceiver and driver architecture with low emissions and high interference immunity - Patents.com

Abstract

A physical layer circuit for interfacing with a communication bus of a wired local area network is disclosed. The circuit includes a variable delay driver operably coupled to the communication bus. The communication bus includes a shared transmission medium. The variable delay driver is configured to control a slew rate of a driven transmit signal at a driver output. The circuit also includes a receiver circuit operably coupled to the communication bus. The circuit further includes a common mode dimmer operably coupled to the receiver circuit and the communication bus. The common mode dimmer is configured to protect the receiver circuit from common mode interference.

Description

[Technical field]

[0001] (Priority Claim) This application claims the benefit of back-filing to Chinese Patent Application No. 201910784373.5, filed on August 23, 2019, entitled "TRANSCEIVER AND DRIVER ARCHITECTURE WITH LOW EMISSION AND HIGH INTERFERENCE TOLERANCE," and to pending U.S. patent application Ser. No. 16 / 588,562, filed on September 30, 2019, entitled "TRANSCEIVER AND DRIVER ARCHITECTURE WITH LOW EMISSION AND HIGH INTERFERENCE TOLERANCE," the disclosures of each of which are incorporated herein by reference in their entireties.

[0002] (Technical field) The present disclosure relates generally to transceivers and drivers with low emissions and high interference immunity, and more particularly, some embodiments relate generally to transceivers and drivers for use in wired local area networks. [Background technology]

[0003] In certain environments where wired local area networks (e.g., Ethernet) are used, it may be desirable to provide robustness. One example is the automotive environment where the Automotive Standards Group and the International Electrical and Electronics Institute (IEEE) coordinate standard specifications for the operation of Ethernet devices. These standards include standards that include electromagnetic compatibility (EMC) and electromagnetic interference (EMI) requirements. Given the high levels of interference and noise in the automotive environment, the EMC and EMI standards are relatively stringent. While the disclosure concludes with claims that particularly point out and distinctly claim certain embodiments, the various features and advantages of embodiments within the scope of the present disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings. [Brief description of the drawings]

[0004] [Figure 1] 1 is a block diagram of a portion of a wired local area network according to some embodiments. [Diagram 2] 2 is a schematic diagram of an example of a physical layer circuit for the wired local area network of FIG. 1. [Diagram 3] 3 is a schematic diagram of an example variable delay driver of the physical layer circuit of FIG. 2. [Figure 4] 4 is a schematic diagram of an example sub-driver of the variable delay driver of FIG. 3. [Diagram 5] FIG. 3 is a schematic diagram of an example common mode dimmer for the circuit of FIG. [Figure 6] 3 illustrates simulated EMI emissions plots resulting from the circuit of FIG. 2 in accordance with some embodiments. [Figure 7] FIG. 1 is a block diagram of a computing device that may be used in some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0005] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific examples of embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments useful herein may be used, and changes in structure, materials, and processes may be made without departing from the scope of the present disclosure.

[0006] The illustrations presented herein are not intended to be actual diagrams of any particular method, system, device, or structure, but merely idealized representations used to describe embodiments of the present disclosure. In some cases, similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0007] The following description may include examples to assist those skilled in the art in enabling the disclosed embodiments to be practiced. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory, and the scope of the disclosure is intended to encompass examples and legal equivalents, and the use of such terms is not intended to limit the embodiments or the scope of the disclosure to specific components, steps, features, functions, etc.

[0008] It will be readily understood that the components of the embodiments as generally described herein and illustrated in the Figures could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. Although various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0009] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure unless otherwise specified herein. Furthermore, the block definitions and partitioning of logic between various blocks are illustrative of specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted, and such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of one skilled in the art.

[0010] Those skilled in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of display and explanation. Those skilled in the art will appreciate that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0011] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor (which may also be referred to herein as a host processor or simply a host) may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration. A general purpose computer including a processor is considered a special purpose computer, and a general purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0012] The embodiments may be described in terms of a process depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts may be performed in a different order, in parallel, or substantially simultaneously. In addition, the order of the acts may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, other structures, or combinations thereof. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, such as any medium that facilitates transfer of a computer program from one place to another.

[0013] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient way of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any way. In addition, unless otherwise stated, a set of elements may include one or more elements.

[0014] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0015] Vehicles (mobile machines), such as automobiles, trucks, buses, ships, and / or aircraft, may include a vehicle communication network. The complexity of the vehicle communication network may vary depending on the number of electronic devices in the network. For example, an advanced vehicle communication network may include various control modules, such as for engine control, transmission control, safety control (e.g., anti-lock brakes), and emissions control. To support these modules, the automotive industry relies on a variety of communication protocols.

[0016] 10SPE (i.e., 10Mbps Single Pair Ethernet) is a network technology specification currently being developed by the Institute of Electrical and Electronic Engineers as specification IEEE 802.3cg™. 10SPE may be used to provide collision-free, deterministic transmission over multi-drop networks. The 10SPE specification is driven by robustness (e.g., EMC / EMI requirements). For example, the 10SPE specification includes stringent automotive EMI standards. A relatively large degree of EMI and noise may be present in the automotive environment. The design of transceivers in wired local area networks often involves trade-offs between performance, chip area, power, risk, and robustness.

[0017] Embodiments of the present disclosure enable wired local area network (e.g., Ethernet) transceivers to withstand interference and noise inherent in the automotive environment, meet relevant automotive and IEEE standards, support error-free transmission and reception of differential signals, support signal detection, diagnostics, sleep / wake-up functions, other functions, and combinations thereof.

[0018] Some embodiments disclosed herein relate to a transceiver architecture for automotive control networks. The architecture features a low emission transmitter driver with multiple slew rate and multiple amplitude level control, and a receiver that tolerates relatively high levels of interference and noise, such as that inherent in the automotive environment. The architecture may also include a common mode dimmer circuit used to suppress interference while drawing relatively low power. Signal and activity detection is also implemented for collision detection and prevention and cable fault monitoring (e.g., cable quality monitoring including shorts, open circuits, other faults, or combinations thereof), as well as network wake-up. The architecture achieves a high impedance idle state, aids in passing automotive tests, and supports diagnostic features. Although some embodiments disclosed herein are discussed in the specific context of automotive control networks, it will be understood that the embodiments disclosed herein are equally applicable to other industrial and server backplanes, such as 10SPM for buildings, elevators, lighting, industrial sites, Internet of Things (IoT), other applications, or combinations thereof.

[0019] Some embodiments disclosed herein relate to a circuit for a physical layer of a wired local area network. The circuit includes a variable delay driver operably coupled to a communication bus. The variable delay driver includes sub-drivers operably coupled in parallel between a driver input of the variable delay driver and a driver output of the variable delay driver. The variable delay driver also includes one or more delay elements coupled between the driver input and one or more of the sub-drivers to deliver a transmit data signal to at least two of the sub-drivers at different times to control a slew rate of a driven transmit signal at the driver output. In some embodiments, at least one of the sub-drivers includes a high speed input stage and a high voltage intermediate stage. In some embodiments, the high speed input stage includes a high speed transistor. In some embodiments, the high voltage intermediate stage includes a high voltage transistor and a diode. In some embodiments, the circuit further includes a receiver circuit operably coupled to the communication bus. In some embodiments, the receiver circuit includes a signal detection circuit, a reflection detection circuit, a sleep mode detection circuit, a collision detection circuit, or a combination thereof. In some embodiments, the reflection detection circuit is configured to detect a short circuit, an open circuit, or both in the communication bus. In some embodiments, the receiver circuit includes at least one receive amplifier. In some embodiments, the circuit further includes a common mode dimmer configured to protect the receiver circuit from common mode interference. In some embodiments, the circuit further includes a common mode choke operably coupled between the variable delay driver and the communication bus. In some embodiments, the communication bus includes an unshielded twisted pair (UTP). In some embodiments, the circuit further includes a Manchester encoder operably coupled to the driver input.

[0020] Some embodiments disclosed herein include a circuit for a physical layer of a wired local area network. The circuit includes a receiver circuit operably coupled to a communication bus and a common mode dimmer operably coupled to the receiver circuit and the communication bus. The common mode dimmer is configured to protect the receiver circuit from common mode interference. In some embodiments, the common mode dimmer includes a differential amplifier and a common mode dimmer cell operably coupled to the differential amplifier. In some embodiments, the circuit further includes a transmit circuit including a variable delay driver operably coupled to the communication bus. In some embodiments, the circuit further includes one or more resistors coupled between the common mode dimmer and the communication bus.

[0021] Some embodiments disclosed herein include a circuit for a physical layer of a wired local area network. The circuit includes a variable delay driver operably coupled to a communication bus. The variable delay driver is configured to control a slew rate of a driven transmit signal at a driver output. The circuit also includes a receiver circuit operably coupled to the communication bus. The circuit further includes a common mode dimmer operably coupled to the receiver circuit and the communication bus. The common mode dimmer is configured to protect the receiver circuit from common mode interference. In some embodiments, the circuit further includes a common mode choke operably coupled between the communication bus and the variable delay driver, the common mode dimmer, and the receiver circuit. In some embodiments, the common mode choke is configured to suppress common mode interference on the communication bus. In some embodiments, the circuit further includes a Manchester encoder operably coupled to a driver input of the variable delay driver. In some embodiments, the circuit further includes one or more capacitors operably coupled between the communication bus and the variable delay driver, the receiver circuit, and the common mode dimmer. In some embodiments, the one or more capacitors are configured to isolate the variable delay driver, the receiver circuit, and the common mode dimmer from the DC voltage of the communication bus.

[0022] 1 is a block diagram of a portion of a wired local area network 100, according to some embodiments. The wired local area network 100 includes endpoints 106 operably coupled to a communication bus 104. The communication bus 104 includes a shared transmission medium (e.g., a single twisted pair) of the wired local area network 100. As used herein, the term "shared transmission medium" refers to a wired transmission medium, such as a single twisted pair, that both transmits and receives signals over the same conductive structure (e.g., wires). The endpoints 106 are configured to communicate over the communication bus 104. While connected to the wired local area network 100, the endpoints 106 function as nodes of the wired local area network 100.

[0023] Endpoint 106 includes physical layer circuitry 200 operably coupled to media access control (MAC) circuitry 102 and communications bus 104. Physical layer circuitry 200 is configured to act as an interface for a physical connection between MAC circuitry 102 and a network or device connected to physical layer circuitry 200 via communications bus 104. In some embodiments, physical layer circuitry 200 includes at least a portion of Ethernet physical layer circuitry.

[0024] Wired local area network 100 may be used in some embodiments in an automotive environment. By way of non-limiting example, wired local area network 100 may be configured to connect one or more sensors in a vehicle to a computer or controller.

[0025] 2 is a schematic diagram of an example of a physical layer circuit 200 of the wired local area network 100 of FIG. 1. The physical layer circuit 200 includes a transmitter circuit including a Manchester encoder 202 and a variable delay driver 300, a receiver circuit 218 including a detection circuit 212 and receive amplifiers 206, 208, 210, and an interference / noise compensation circuit including a common mode dimmer 500, a common mode choke 204, a resistor 214 (e.g., a 10 kiloohm (kΩ) resistor), and a capacitor 216 (e.g., a 100 nanofarad (nF) capacitor). The transmitter circuit and the receiver circuit 218 are both connected to the same communication bus 104. As a result, the communication bus 104 can be used for both transmitting and receiving data. In some embodiments, the communication bus 104 can include a single twisted pair (e.g., unshielded twisted pair, or UTP).

[0026] The variable delay driver 300 is configured to drive the signal provided to the variable delay driver 300 by the Manchester encoder 202 to the differential outputs TXP, TXN of the variable delay driver 300. The variable delay driver 300 is also configured to control the slew rate and amplitude (e.g., different output swing levels) of the driver output of the variable delay driver 300. The variable delay driver 300 is also configured to withstand high interference (e.g., common mode interference of + / - 40 volts or more) and noise received over the communication bus 104 at the driver output of the variable delay driver 300. The variable delay driver 300 is also configured to protect itself from high input voltages at the driver input of the variable delay driver 300. Because the 10SPE EMI standard for emissions is relatively stringent, the slew rate of the driver output of the variable delay driver 300 may be reduced to reduce high frequency components of the driven transmit signal provided to the driver output of the variable delay driver 300. The reduction in high frequency components of the driven transmit signal at the driver output may result in an overall reduction in emissions of the physical layer circuit 200. Additionally, the interference / noise immunity and input voltage protection allows the variable delay driver 300 to operate in the noisy and interference-prone environment of an automobile. These characteristics of the variable delay driver 300 make it well suited for the automotive environment. More details regarding the physical layer circuit 200 are disclosed below with reference to Figures 3 and 4.

[0027] The common mode dimmer 500 is configured to protect sensitive receiver circuitry (e.g., detection circuit 212 and receive amplifiers 206, 208, 210) from interference (e.g., common mode interference) and noise received from the communication bus 104 during Bulk Current Injection (BCI) conditions. For example, the common mode dimmer 500 is configured to draw enough current through resistor 214 to filter out dangerously high common mode interference and reduce the voltage of signals received over the communication bus 104 to a safe level at the receiver circuit 218. As a non-limiting example, the common mode dimmer 500 may be configured to keep the voltage of signals reaching the receiver circuit 218 below the high power rail (e.g., 3.3V) of the receiver circuit 218. The common mode dimmer 500 enables the use of high gain receivers (e.g., receive amplifiers 206, 208, 210) and signal / pulse / collision detectors (e.g., detection circuit 212) in the receiver circuitry 218 to filter common mode interference signals, resulting in low jitter and low power consumption. More details regarding the common mode dimmer 500 are discussed below with reference to FIG. 5. In some embodiments, the common mode dimmer 500 may be used for low power applications.

[0028] The detection circuit 212 may include a signal detection circuit, a reflection detection circuit, a sleep mode detection circuit, a collision detection circuit, other circuits, or combinations thereof. The signal detection circuit may be configured to detect a signal received over the communication bus 104. The reflection detection circuit may be configured to diagnose the communication bus 104 (e.g., by detecting shorts, open circuits, other problems, or combinations thereof on the communication bus 104). The sleep mode detection circuit may be configured to trigger the receiver circuit 218 to sleep or wake up in response to a sleep or wake message received over the communication bus 104. The collision detection circuit may be configured to detect signal collisions on the communication bus 104. Signal and activity detection may also be implemented.

[0029] To provide additional interference / noise protection, common mode choke 204 is configured to reduce (e.g., suppress) common mode interference received over communication bus 104, and capacitor 216 is configured to filter direct current (DC) components of signals received from communication bus 104.

[0030] 3 is a schematic diagram of an example of a variable delay driver 300 of the physical layer circuit 200 of FIG. 2. The variable delay driver 300 includes a plurality of sub-drivers 304 operatively coupled in parallel between a driver input 306 and a driver output 308. The variable delay driver 300 also includes one or more delay elements 302 coupled between the driver input 306 and one or more of the sub-drivers 304 to deliver an input transmit data signal 310 to at least two of the sub-drivers 304 at different times to control the slew rate of the driven transmit signal 312 at the driver output 308. Each of the sub-drivers 304 and its corresponding one of the delay elements 302 may be referred to as a "stage" where applicable (e.g., a first one of the sub-drivers 304 may or may not have a corresponding one of the delay elements 302).

[0031] The variable delay driver 300 also includes a delay controller 314 configured to control how much delay is induced by the delay elements 302. For example, the delay controller 314 may be configured to provide a plurality of delay signals 316 to the plurality of delay elements 302. Each of the plurality of delay elements 302 may be controllable to set the amount of delay induced thereby. As a non-limiting example, the delay signal 316 may include a two-bit signal configured to set the delay of the corresponding delay element to any one of four different delay values ​​(e.g., zero delay, 7.5 nanoseconds (ns) delay, 15 ns delay, 15 ns delay, or 25 ns delay). It should be understood that a delay signal 316 with more than two bits allows more than four different delay values ​​to be signaled to the delay elements 302. As a specific non-limiting example, the delay induced by the delay elements 302 may follow a fixed delay pattern, a delay following a raised cosine shape, or a combination thereof. The outputs of each stage may be summed together to generate the driven transmit signal 312.

[0032] In the embodiment illustrated in FIG. 3, the delay element 302 causes the sub-drivers 304 to receive the transmit data signal 310 at different times. As a result, at the driver output 308, each of the sub-drivers 304 starts to drive a new receive bit at a staggered time relative to the others. This staggering in the drive of the driven transmit signal 312 results in a reduced slew rate compared to a slew rate that does not stagger the drive. The reduced slew rate eliminates high frequency components at the driver output 308 that tend to result in EMI emissions. As a result, the variable delay driver 300 results in lower EMI emissions compared to a driver that does not use staggered drives. The use of stages such as the variable delay driver 300 of FIG. 3 may also allow for different delays and different current level control.

[0033] Each stage may also include an inductive current having a raised cosine or constant value. As a result, in addition to slew rate control, the variable delay driver 300 may also have amplitude control at its driver output 308. More details regarding the inductive current and the controllable amplitude are discussed below with reference to FIG.

[0034] 4 is a schematic diagram of an example of a sub-driver 400 of the variable delay driver 300 of FIG. 3. As seen in FIG. 4, the current of the sub-driver 400 is switched by differential data. The sub-driver 400 is configured to protect data and withstand high common mode surges at the outputs OUTP, OUTN of the sub-driver 400 operably coupled to the communication bus 104. These surges may be received from the communication bus 104 (FIG. 2). The sub-driver 400 includes a high-speed input stage 402 for each input DN, DP, and a high-voltage intermediate stage 404 for each input DN, DP. The high-speed input stage 402 includes a data switch including a high-speed transistor 406, and the high-voltage intermediate stage 404 includes a high-voltage transistor 408 cascaded with the high-speed transistor 406, and a protection diode 410 cascaded with the high-voltage transistor 408. The design of the transistor involves a trade-off between device speed and tolerance to high voltages (e.g., devices with relatively small dimensions tend to operate relatively fast, but tend to have relatively low voltage tolerance compared to devices with relatively large dimensions). Thus, as used herein, the terms "high speed transistor" and "high voltage transistor" acknowledge these design trade-offs. As used herein, the term "high speed transistor" is a transistor that switches on and off faster than a "high voltage transistor". Also, as used herein, a "high voltage transistor" is a transistor that can withstand a higher potential difference at its terminals than a "high speed transistor". As a result, the sub-driver 400 can switch at a relatively high speed provided by the high speed input stage 402 without sacrificing the relatively high voltage protection for the device and the data provided by the high voltage intermediate stage 404. As a result, the sub-driver 400 can withstand high common mode surges on the communication bus 104 (FIG. 2), which may be operably coupled to the outputs OUTP, OUTN. In some embodiments, the amplitude may be controlled by a Digital to Analog Converter (DAC).

[0035] The sub-driver 400 may also include a circuit component 412 that includes a capacitor CC (e.g., a 100 nF capacitor) with a resistor RR (e.g., a 25 Ω resistor) in series between the capacitors CC. As a non-limiting example, the circuit component 412 may be an off-chip circuit component (e.g., a separate capacitor and resistor configured to be soldered to a printed circuit board). During operation, a current I S may pass through a capacitor CC and a resistor RR. In some embodiments, the terminal between the resistor RR may be grounded (zero volts). As a result, the peak-to-peak voltage between the output terminals TXP, TXN of the sub-driver 400 (e.g., measured across the resistor RR of the circuit component 412) is Vtx(pk)=I S * (50Ω), where RR=25Ω. In some embodiments, I S can vary from 2.5 milliamps (mA) to 15 mA. As a non-limiting example, I S = 10mA, then Vtx(pk) may be approximately 1 volt peak-to-peak (where the terminal across resistor RR is grounded).

[0036] Vtx(pk) is the current I S Since the amplitude of the output of the sub-driver 400 is a function of I S As a result, the sub-driver 400 can be controlled by controlling the current I S 4. As a non-limiting example, the variable current source 414 may include an NMOS variable current source and the variable current source 416 may include a PMOS variable current source. In some embodiments, the variable current sources 414, 416 are each configured to control a resistor controller 42 2 , 418. The register controller 42 2 , 418 may be configured to output voltage signals 428, 426, respectively, corresponding to a desired voltage swing value of Vtx(pk) between output terminals TXP and TXN. The variable current sources 414, 416 supply appropriate currents I Sto achieve a desired voltage swing Vtx(pk) at the output terminals TXP, TXN. In an embodiment in which the variable current source 414 is controlled by an analog input and the resistor controllers 422, 418 provide digital voltage signals 428, 426, respectively, the sub-driver 400 may include one or more digital-to-analog converters (DACs) 4 24 , 4 2 0. DAC4 24 , 4 2 The register controllers 422, 418 are configured to convert the voltage signals 428, 426 to analog voltage signals 432, 430 that are provided to the variable current sources 414, 416, respectively. As a non-limiting example, the register controllers 422, 418 may be configured to control the variable current sources 414, 416 with 3-bit voltage signals 428, 426 corresponding to up to eight different voltage amplitude levels of Vtx(pk). In a specific non-limiting example, the voltage signals 428, 426 may selectively indicate 250 mV, 500 mV, 750 mV, 1 V, 1.25 V, or 1.5 V.

[0037] 5 is a schematic diagram of an example of a common mode dimmer 500 of the circuit 200 of FIG. 2. The common mode dimmer is configured to enable the receiver circuit 218 of the circuit 200 to tolerate high common mode interference under BCI conditions, implement common mode interference signal filtering, implement low jitter, and draw low power. The common mode dimmer 500 includes a common mode dimmer cell 502 operably coupled to a differential amplifier 504. The common mode dimmer 500 operably couples to the resistor 214 of the circuit 200 of FIG. 2 at the IOP and ION terminals of the common mode dimmer 500 of FIG. 5.

[0038] The common mode dimmer 500 also includes a voltage reference circuit 506 operably coupled to the non-inverting input terminal of the differential amplifier 504. The voltage reference circuit 506 is configured to provide a reference voltage VREF to the non-inverting input terminal of the differential amplifier 504. As a non-limiting example, the voltage reference circuit 506 may include a voltage divider circuit including resistors R1 and R2 in series between a high rail potential VDD and a low rail potential VSS, as illustrated in FIG. 5. The values ​​of resistors R1, R2 may be selected to set the reference voltage VREF to a desired level.

[0039] The common mode dimmer 500 is configured to maintain the voltages at the IOP and ION terminals operably coupled to the receiver circuit 218 of FIG. 2 below a reference voltage VREF. In some embodiments, the reference voltage VREF may be selected to be a high rail voltage (VDD) of the receiver circuit 218. In some embodiments, the common mode dimmer 500 is configured to maintain the voltages at the IOP and ION terminals above a low rail voltage VSS (e.g., ground) of the receiver circuit 218.

[0040] The inverting input of the differential amplifier 504 is operably coupled to the IOP and ION terminals of the common mode dimmer via feedback resistors R3, R4, respectively. As a result, the feedback voltage VFB received at the inverting input of the differential amplifier 504 is controlled by the signal level of the communication bus 104 of Figure 2. In other words, the communication bus 104 is operably coupled to the inverting input of the differential amplifier via two pairs of resistors (R3 and R4; resistor 214 of Figure 2).

[0041] The non-inverting output of the differential amplifier 504 is operatively coupled to the gate of transistor Q2, which is operatively coupled in series with transistor Q1 between a high rail potential VDD and a low rail potential. The gate of transistor Q1 is operatively coupled to the drains of transistors Q1 and Q2 and to the gates of transistors Q5 and Q6 of the common mode dimmer cell 502. The transistor Q5 of the common mode dimmer cell 502 is operatively coupled in series with transistor Q3 between VDD and VSS, and the transistor Q6 is operatively coupled in series with transistor Q4 between VDD and VSS. The drains of transistors Q5 and Q3 are operatively coupled to the IOP terminal, and the drains of transistors Q6 and Q4 are operatively coupled to the ION terminal. In other words, the common mode dimmer cell 502 includes two pairs of transistors (Q3 and Q5; Q4 and Q6), each pair of the two pairs of transistors being coupled in series between a high rail potential and a low rail potential. The gates of transistors Q3 and Q4 are operatively coupled to the inverting output of differential amplifier 504. Common mode dimmer cell 502 further includes capacitors C1, C2, C3, and C4 coupled between the gates and drains of transistors Q3, Q4, Q5, and Q6, respectively.

[0042] As illustrated in FIG. 5, transistors Q1, Q5, and Q6 are p-type transistors (e.g., P-type Metal Oxide Semiconductor (PMOS) transistors), and transistors Q2, Q3, and Q4 are n-type transistors (e.g., N-type Metal Oxide Semiconductor (NMOS) transistors). When a high common-mode interference potential (i.e., greater than the reference voltage VREF) is received at the IOP and ION terminals, the potential VFB at the inverting input of the differential amplifier 504 becomes higher than the reference voltage VREF at the non-inverting input of the differential amplifier 504. As a result, the differential amplifier 504 drives its non-inverting output to a low logic level and its inverting output to a high logic level. As a result, the gates of transistors Q3 and Q4 are driven high, turning on transistors Q3 and Q4 and conducting current from the IOP and ION terminals to the VSS terminal. When current is drawn from the IOP and ION terminals, the voltage drop across resistor 214 (FIG. 2) increases, pulling the potential at terminals IOP and ION down to VREF.

[0043] On the other hand, when a low common-mode interference potential (i.e., less than VSS) is received at the IOP and ION terminals, the potential VFB at the inverting input of differential amplifier 504 becomes lower than the reference voltage VREF at the non-inverting input of differential amplifier 504. As a result, differential amplifier 504 drives its non-inverting output to a high logic level and its inverting output to a low logic level. As a result, the gates of transistors Q5 and Q6 are driven low, turning on transistors Q5 and Q6 and sourcing current from the IOP and ION terminals to VDD. When current is sunk from the IOP and ION terminals, the magnitude of the voltage drop across resistor 214 (FIG. 2) increases (i.e., a more negative voltage drop), pulling the potential at terminals IOP and ION up to at least VSS.

[0044] Figure 6 illustrates a simulated EMI emissions plot 600 resulting from the circuit 200 of Figure 2, in accordance with some embodiments. The EMI emissions plot 600 includes a plot of a standard emission mask 602 and a plot of a simulated emissions spectrum 604 resulting from the circuit 200. As can be seen, the emissions spectrum 604 is well within the emission mask 602.

[0045] 7 is a block diagram of a computing device 700 that may be used in some embodiments. The computing device 700 includes one or more processors 702 (sometimes referred to herein as “processors 702”) operably coupled to one or more data storage devices 704 (sometimes referred to herein as “storage devices 704”). The storage devices 704 include computer-readable instructions stored therein. The computer-readable instructions are configured to instruct the processors 702 to perform operations of the embodiments disclosed herein. For example, the computer-readable instructions may be configured to instruct the processors 702 to perform at least some or all of the operations discussed for the circuit 200 (FIGS. 1 and 2), the variable delay driver 300 (FIGS. 2 and 3), the sub-driver 400 (FIG. 4), the common mode dimmer 500 (FIG. 5), or combinations thereof.

[0046] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation configured to perform the actions of a module or component and / or software object or routine that may be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, etc.) of a computing system. In some embodiments, different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored and / or executed on general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0047] As used in this disclosure, the term "combination" referring to multiple elements may include a combination of all elements or any of various different subcombinations of the elements. For example, the phrase "A, B, C, D, or combinations thereof" may refer to any one of A, B, C, or D; each combination of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D, etc.

[0048] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "including" should be interpreted as "including, but not limited to," etc.).

[0049] In addition, if a specific number is intended in an introduced claim recitation, such intent will be expressly recited in the claim, and in the absence of such recitation, no such intent exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as limiting any particular claim that includes such introduced claim recitation to embodiments that include only one of such recitations, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same applies to the use of express articles used to introduce claim recitations.

[0050] In addition, even if a particular number in an introduced claim recitation is explicitly recited, one of ordinary skill in the art will recognize that such recitation should be interpreted to mean "at least the recited number" (e.g., an explicit recitation of "two ____" without other modifiers means "at least two ____" or "two or more ____"). Furthermore, when a convention similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." is used, generally such a structure is intended to include only A, only B, only C, A and B together, A and C together, B and C together, or A, B, and C together.

[0051] Moreover, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0052] Working Example A non-exhaustive, non-limiting list of exemplary embodiments follows: Each of the exemplary embodiments listed below is not individually indicated as combinable with all other of the exemplary embodiments listed below and discussed above. However, these exemplary embodiments are intended to be combinable with all other exemplary embodiments and embodiments discussed above, except where it is apparent to one of ordinary skill in the art that the embodiments are not combinable.

[0053] Example 1: A physical layer circuit for interfacing with a communication bus of a wired local area network, the physical layer circuit having a variable delay driver operably coupled to the communication bus including a shared transmission medium, the variable delay driver comprising a plurality of sub-drivers operably coupled in parallel between a driver input of the variable delay driver and a driver output of the variable delay driver, and one or more delay elements operably coupled between the driver input and one or more of the plurality of sub-drivers to deliver a transmit data signal to at least two of the sub-drivers at different times to control a slew rate of a driven transmit signal at the driver output.

[0054] Example 2: The physical layer circuit of example 1, wherein at least one of the plurality of sub-drivers includes a high-speed input stage and a high-voltage intermediate stage.

[0055] The physical layer circuit of example 2, wherein the high speed input stage includes a high speed transistor.

[0056] Example 4: The physical layer circuit of any one of Examples 2 and 3, wherein the high voltage intermediate stage includes a high voltage transistor and a diode.

[0057] Example 5: The physical layer circuit of any one of Examples 1 to 4, further comprising a receiver circuit operably coupled to the communication bus.

[0058] Example 6: The physical layer circuit of example 5, wherein the receiver circuit includes a detection circuit.

[0059] Example 7: The physical layer circuit of example 6, wherein the reflection detection circuit is configured to detect a short circuit, an open circuit, or both in the communication bus.

[0060] Example 8: The physical layer circuit of any one of Examples 5 to 7, wherein the receiver circuit includes at least one receiving amplifier.

[0061] Example 9: The physical layer circuit of any one of Examples 5 to 8, further comprising a common mode dimmer configured to protect the receiving circuit from common mode interference.

[0062] Example 10: The physical layer circuit of Example 9, wherein the common mode dimmer includes a differential amplifier operably coupled to the common mode dimmer cell, the differential amplifier configured to drive the common mode dimmer cell to pull down excessively high common mode interference and pull up excessively low common mode interference in the receiver circuit.

[0063] Example 11: The physical layer circuit of any one of Examples 1 to 10, further comprising a common mode choke operably coupled between the variable delay driver and the communication bus.

[0064] Example 12: The physical layer circuit of any one of Examples 1 to 11, further comprising a Manchester encoder operably coupled to the driver input.

[0065] Example 13: A physical layer circuit for interfacing with a communication bus of a wired local area network, the physical layer circuit comprising: a receiver circuit operably coupled to the communication bus, the communication bus including a shared transmission medium; and a common mode dimmer operably coupled to the receiver circuit and the communication bus, the common mode dimmer configured to protect the receiver circuit from common mode interference.

[0066] Example 14: The circuit of example 13, wherein the common mode dimmer comprises a differential amplifier and a common mode dimmer cell operably coupled to the differential amplifier.

[0067] Example 15: The circuit of example 14, wherein the communication bus is operably coupled to the inverting input of the differential amplifier.

[0068] Example 16: The circuit of example 15, wherein the communication bus is operably coupled to the inverting input of the differential amplifier via two pairs of resistors.

[0069] Example 17: The circuit of any one of Examples 14 to 16, further comprising a voltage reference circuit operably coupled to the non-inverting input of the differential amplifier, the voltage reference circuit configured to provide a reference voltage to the non-inverting input of the differential amplifier.

[0070] Example 18: The circuit of example 17, wherein the common mode dimmer is configured to maintain a voltage level in the receiver circuitry below a reference voltage.

[0071] Example 19: The circuit of any one of Examples 14 to 18, wherein the common mode dimmer cell includes two pairs of transistors, each pair of the two pairs of transistors coupled in series between a high rail potential and a low rail potential.

[0072] Example 20: The circuit of Example 19, wherein the drains of a first pair of transistors of the two pairs of transistors are operably coupled to a first input terminal of a common mode dimmer, and the drains of a second pair of transistors of the two pairs of transistors are operably coupled to a second input terminal of the common mode dimmer.

[0073] Example 21: The circuit of any one of Examples 19 and 20, wherein the gates of the N-type metal oxide semiconductor transistors of the two pairs of transistors are operably coupled to the inverting output of the differential amplifier.

[0074] Example 22: The circuit of any one of Examples 19 to 21, wherein a gate of a P-type metal-oxide semiconductor (PMOS) transistor of the two pairs of transistors is operably coupled to a gate of another PMOS transistor, the other PMOS transistor being operably coupled in series with an N-type metal-oxide semiconductor (NMOS) transistor between a high rail potential and a low rail potential, and a gate of the NMOS transistor is operably coupled to a non-inverting output of the differential amplifier.

[0075] Example 23: The circuit of any one of Examples 13 to 22, further comprising a transmit circuit including a variable delay driver operably coupled to the communication bus.

[0076] Example 24: The circuit of any one of Examples 13-23, further comprising one or more resistors coupled between the common mode dimmer and the communication bus.

[0077] Example 25: A physical layer circuit for interfacing with a communication bus of a wired local area network, the circuit comprising: a variable delay driver operably coupled to a communication bus including a shared transmission medium, the variable delay driver configured to control a slew rate of a driven transmit signal at a driver output; a receiver circuit operably coupled to the communication bus; and a common mode dimmer operably coupled to the receiver circuit and the communication bus, the common mode dimmer configured to protect the receiver circuit from common mode interference.

[0078] Example 26: The circuit described in Example 25, further comprising a common mode choke operably coupled between the communication bus and the variable delay driver, the common mode dimmer, and the receiver circuit, the common mode choke configured to suppress common mode interference on the communication bus.

[0079] Example 27: The circuit of any one of Examples 25 to 26, further comprising a Manchester encoder operably coupled to the driver input of the variable delay driver.

[0080] Example 28: The circuit of any one of Examples 25 to 27, further comprising one or more capacitors operably coupled between the communication bus and the variable delay driver, the receiver circuit, and the common mode dimmer, the one or more capacitors configured to isolate the variable delay driver, the receiver circuit, and the common mode dimmer from the DC voltage of the communication bus.

[0081] Example 29: The circuit of any one of Examples 25 to 28, wherein the variable delay driver is further configured to control an amplitude of the voltage signal at a driver output of the variable delay driver.

[0082] Example 30: A circuit described in any one of Examples 25 to 29, wherein the variable delay driver includes a plurality of sub-drivers, at least one of the plurality of sub-drivers including at least one variable current source configured to control an amplitude of a voltage signal at a driver output of the variable delay driver by controlling an amount of current provided to at least one of the plurality of sub-drivers.

[0083] conclusion While the present disclosure has been described herein with respect to certain illustrated embodiments, those skilled in the art will recognize and understand that the present invention is not so limited. Rather, numerous additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below along with their legal equivalents. In addition, features of one embodiment may be combined with features of other embodiments as contemplated by the inventors and still fall within the scope of the present disclosure.

Claims

1. 1. A physical layer circuit for interfacing with a communication bus of a wired local area network, said physical layer circuit comprising: a variable delay driver operably coupled to the communication bus including a shared transmission medium; The variable delay driver includes: a plurality of sub-drivers operatively coupled in parallel between a driver input of the variable delay driver and a driver output of the variable delay driver, the variable delay driver being configured to provide a driven transmit signal comprising a driven version of a transmit data signal at the driver output; one or more delay elements operably coupled between the driver input and one or more of the plurality of sub-drivers to deliver the transmit data signal to at least two of the sub-drivers at different times to control a slew rate of the driven transmit signal at the driver output.

2. The physical layer circuit of claim 1 , wherein at least one of the plurality of sub-drivers includes an input stage and an intermediate stage.

3. 3. The physical layer circuit of claim 2, wherein the input stage includes transistors that switch on and off faster than transistors in the middle stage.

4. 3. The physical layer circuit of claim 2, wherein the intermediate stage includes transistors capable of withstanding a higher voltage difference at their terminals than the transistors of the input stage.

5. The physical layer circuit of claim 1 further comprising a receiver circuit operably coupled to the communication bus.

6. The physical layer circuit of claim 5 , wherein the receiver circuit includes a detection circuit.

7. The physical layer circuit of claim 6 , wherein the detection circuitry is configured to detect short circuits, open circuits, or both in the communication bus.

8. The physical layer circuit of claim 5 , wherein the receiver circuit includes at least one receive amplifier.

9. 6. The physical layer circuit of claim 5, further comprising a common mode dimmer configured to protect the receiver circuit from common mode interference.

10. 10. The physical layer circuit of claim 9, wherein the common mode dimmer includes a differential amplifier operably coupled to a common mode dimmer cell, the differential amplifier configured to drive the common mode dimmer cell to pull down common mode interference and pull up common mode interference at the receiver circuit.

11. 2. The physical layer circuit of claim 1, further comprising a common mode choke operatively coupled between said variable delay driver and said communication bus.

12. 2. The physical layer circuit of claim 1, further comprising a Manchester encoder operably coupled to the driver input.

13. 1. A physical layer circuit for interfacing with a communication bus of a wired local area network, said circuit comprising: a receiver circuit operably coupled to the communications bus, the communications bus including a shared transmission medium; a common mode dimmer operably coupled to the receiver circuit and to the communication bus, the common mode dimmer configured to protect the receiver circuit from common mode interference, the common mode dimmer comprising: A differential amplifier; a common mode dimmer cell operably coupled to the differential amplifier.

14. The circuit of claim 13 , wherein the communication bus is operatively coupled to an inverting input of the differential amplifier.

15. 15. The circuit of claim 14, wherein the communication bus is operably coupled to the inverting input of the differential amplifier through two pairs of resistors.

16. 14. The circuit of claim 13, further comprising a voltage reference circuit operably coupled to a non-inverting input of the differential amplifier, the voltage reference circuit configured to provide a reference voltage to the non-inverting input of the differential amplifier.

17. 17. The circuit of claim 16, wherein the common mode dimmer is configured to maintain a voltage level in the receiver circuitry below the reference voltage.

18. 14. The circuit of claim 13, wherein the common mode dimmer cell includes two pairs of transistors, each pair of the two pairs of transistors coupled in series between a first power rail potential node and a second power rail potential node, a first power rail potential associated with the first power rail potential node that is higher than a second power rail potential associated with the second power rail potential node.

19. 20. The circuit of claim 18, wherein drains of a first pair of transistors of the two pairs of transistors are operably coupled to a first input terminal of the common mode dimmer and drains of a second pair of transistors of the two pairs of transistors are operably coupled to a second input terminal of the common mode dimmer.

20. 20. The circuit of claim 18, wherein the gates of the N-type metal oxide semiconductor transistors of the two pairs of transistors are operably coupled to an inverting output of the differential amplifier.

21. 20. The circuit of claim 18, wherein a gate of a P-type metal-oxide-semiconductor (PMOS) transistor of the two pairs of transistors is operably coupled to a gate of another PMOS transistor, the other PMOS transistor being operably coupled in series with an N-type metal-oxide-semiconductor (NMOS) transistor between the first power rail potential node and the second power rail potential node, the gate of the NMOS transistor being operably coupled to a non-inverting output of the differential amplifier.

22. The circuit of claim 13 further comprising a transmit circuit including a variable delay driver operably coupled to the communication bus.

23. 14. The circuit of claim 13, further comprising one or more resistors coupled between the common mode dimmer and the communication bus.

24. 1. A physical layer circuit for interfacing with a communication bus of a wired local area network, said circuit comprising: a variable delay driver operably coupled to the communication bus including a shared transmission medium, the variable delay driver configured to control a slew rate of a driven transmission signal at a driver output; a receiver circuit operably coupled to the communication bus; a common mode dimmer operably coupled to the receiver circuitry and to the communication bus, the common mode dimmer configured to protect the receiver circuitry from common mode interference; the variable delay driver is further configured to control an amplitude of a voltage signal at a driver output of the variable delay driver; The variable delay driver includes a plurality of sub-drivers; a circuit comprising: at least one of the plurality of sub-drivers including at least one variable current source configured to control an amount of current provided to the at least one of the plurality of sub-drivers, thereby controlling an amplitude of a voltage signal at a driver output of the variable delay driver.

25. 25. The circuit of claim 24, further comprising a common mode choke coupled between the communication bus and the variable delay driver, the common mode dimmer, and the receiver circuit, the common mode choke configured to suppress the common mode interference on the communication bus.

26. 25. The circuit of claim 24, further comprising a Manchester encoder operably coupled to a driver input of the variable delay driver.

27. 25. The circuit of claim 24, further comprising one or more capacitors operably coupled between the communication bus and the variable delay driver, the receiver circuit, and the common mode dimmer, the one or more capacitors configured to isolate the variable delay driver, the receiver circuit, and the common mode dimmer from a DC voltage on the communication bus.

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