Display substrate and display device

Abstract

A display substrate and a display device are provided, the display substrate comprising: a base substrate, a pixel circuit layer having a plurality of pixel driving circuits, a first conductive layer, a first planar layer, and a second conductive layer, the second conductive layer comprising a plurality of conductive portions, the plurality of conductive portions comprising first conductive portions, the first conductive portions comprising at least one conductive portion adjacent to each other in a first direction and a sealed ring portion separated from each other in the second conductive layer, each light-emitting element group comprising a first light-emitting element having a first anode whose orthogonal projection on the base substrate overlaps with the orthogonal projection of the sealed ring portion on the base substrate, and the plurality of conductive portions further comprising a second conductive portion adjacent to the first conductive portion and whose orthogonal projection on the base substrate overlaps with the orthogonal projection of the first anode on the base substrate, thereby effectively improving color cast in the display substrate.

Description

Technical Field

[0001] This application claims the priority of PCT International Application No. PCT / CN2020 / 081154 filed on March 25, 2020, and hereby incorporates by reference in its entirety the content disclosed in the above Chinese patent application as part of this application.

[0002] Embodiments of the present disclosure relate to a display substrate and a display device.

Background Art

[0003] With the continuous development of display technology, organic light-emitting diode (OLED) display technology has been applied to various electronic devices due to its advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed.

[0004] On the other hand, with the continuous development of organic light-emitting diode display technology, the requirements for the performance of organic light-emitting diode display products, such as power, color crosstalk, brightness, and stability, are increasing.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of the present disclosure provide a display substrate and a display device. On the one hand, the sealed annular part can ensure that the flatness of the first anode is high, thereby ensuring that the light emission intensities in different directions of the first anode are consistent, and further effectively improving the color crosstalk phenomenon. On the other hand, since the sealed annular part has a hollow design, the light transmittance of the display substrate can be improved, and it is advantageous for the under-screen fingerprint recognition device to receive signals.

[0006] At least one embodiment of the present disclosure includes a base substrate, a plurality of pixel driving circuits having semiconductor layers, a first conductive layer located on one side of the semiconductor layer away from the base substrate, a first flat layer located on one side of the first conductive layer away from the base substrate, a second conductive layer located on one side of the first flat layer away from the first conductive layer, a second flat layer located on one side of the second conductive layer away from the base substrate, and a plurality of light-emitting element groups located on one side of the second flat layer away from the second conductive layer. The second conductive layer includes a plurality of conductive portions arranged along a first direction, and the size of the second direction intersecting the first direction is larger than the size of each of the first directions. The plurality of conductive portions include a first conductive portion having a sealed annular portion separated from at least one of the adjacent conductive portions in the first direction by the second conductive layer. Each of the light-emitting element groups includes a first light-emitting element having a first anode whose orthographic projection on the base substrate overlaps the orthographic projection of the sealed annular portion on the base substrate. The plurality of conductive portions further include a second conductive portion adjacent to the first conductive portion and having an orthographic projection on the base substrate overlapping the orthographic projection of the first anode on the base substrate, and a display substrate is further provided.

[0007] For example, in the display substrate provided by an embodiment of the present disclosure, the size of the sealed annular portion in the first direction is at least larger than the size of a part of the first conductive portion in the first direction. The plurality of pixel driving circuits include a first pixel driving circuit having a semiconductor pattern in the semiconductor layer. The orthographic projection of the first conductive portion on the base substrate overlaps the orthographic projection of the semiconductor pattern of the first pixel driving circuit on the base substrate. The first pixel driving circuit includes a driving transistor. The first conductive layer has the same potential as the gate of the driving transistor and includes a first conductive pattern that forms a gate potential metal together with the gate of the driving transistor. The orthographic projection of the hollow region inside the sealed annular portion on the base substrate overlaps the gate potential metal.

[0008] For example, in the display substrate provided according to an embodiment of the present disclosure, the inside of the sealed annular portion has a hollow region, the first conductive portion has a plurality of the hollow regions arranged along the second direction, and the shapes and sizes of two adjacent hollow regions are substantially the same.

[0009] For example, in the display substrate provided according to an embodiment of the present disclosure, the first light-emitting element includes an effective light-emitting region, and an orthographic projection of a straight line passing through the center of the effective light-emitting region of the first light-emitting element and extending along the second direction on the base substrate is between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the second conductive portion on the base substrate.

[0010] For example, in the display substrate provided according to an embodiment of the present disclosure, each of two edges of the sealed annular portion in the first direction overlaps with an orthographic projection of anodes of a plurality of light-emitting elements in the light-emitting element group on the base substrate, and the hollow region of the sealed annular portion and an orthographic projection of the effective light-emitting regions of the plurality of light-emitting elements on the base substrate are separately arranged.

[0011] For example, in the display substrate provided according to an embodiment of the present disclosure, the first conductive layer further includes a conductive metal configured to supply power to the pixel driving circuit, the first flat layer includes a conductive metal via, the conductive portion is electrically connected to the conductive metal by the conductive metal via, the first pixel driving circuit further includes a first light-emitting control transistor and a storage capacitor having a first electrode block and a second electrode block located on a side away from the base substrate of the first electrode block, and the conductive metal is electrically connected to the source of the first light-emitting control transistor and the second electrode block respectively.

[0012] For example, in the display substrate provided according to an embodiment of the present disclosure, an orthographic projection of the base substrate of the sealed annular portion on the base substrate and an orthographic projection of the first electrode block on the base substrate overlap, the second electrode block includes an opening whose orthographic projection on the base substrate overlaps with the orthographic projection of the first electrode block on the base substrate, and the orthographic projection of the sealed annular portion on the base substrate also overlaps with the orthographic projection of the opening on the base substrate.

[0013] For example, in the display substrate provided according to an embodiment of the present disclosure, the first pixel driving circuit further includes a data writing transistor, a compensation transistor, a reset transistor, an anode initialization transistor, and a second light emission control transistor, the display substrate further includes a reset signal line connected to a gate of the reset transistor, a gate line connected to a gate of the compensation transistor, a light emission control line connected to a gate of the first light emission control transistor, and an initialization signal line connected to a source of the reset transistor, and each of the orthographic projections of the sealed annular portion on the base substrate overlaps with the orthographic projections of the reset signal line, the gate line, and the initialization signal line on the base substrate.

[0014] For example, in the display substrate provided according to an embodiment of the present disclosure, one end of the first conductive pattern is electrically connected to a gate of the driving transistor through the opening, and the other end of the first conductive pattern is electrically connected to a source or a drain of the compensation transistor.

[0015] For example, in the display substrate provided according to an embodiment of the present disclosure, the sealed annular portion includes a first portion and a second portion arranged along the first direction, and a third portion and a fourth portion arranged along the second direction, the first portion, the third portion, the second portion, and the fourth portion are connected end to end to form the sealed annular portion, and the orthographic projections of the first portion and the second portion on the base substrate overlap with the orthographic projection of the second electrode block on the base substrate.

[0016] For example, in the display substrate provided according to an embodiment of the present disclosure, the orthographic projection of the base substrate of the first portion on the base substrate and the orthographic projection of the first conductive pattern on the base substrate overlap, the shapes of both the first conductive pattern and the first portion are elongated, and the extending direction of the long side of the first conductive pattern is the same as the extending direction of the long side of the first portion.

[0017] For example, in the display substrate provided according to an embodiment of the present disclosure, the first conductive layer further includes a second conductive pattern respectively connected to the initialization signal line and the source of the reset transistor, and a third conductive pattern, the second conductive layer further includes an anode connection portion, the third conductive pattern is connected to the drain of the second light emission control transistor and the anode connection portion, the orthographic projection of the third portion on the base substrate overlaps with the orthographic projection of the initialization signal line on the base substrate, the orthographic projection of the third portion on the base substrate overlaps with the orthographic projection of the second conductive pattern on the base substrate, and the orthographic projection of the fourth portion on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate.

[0018] For example, in the display substrate provided according to an embodiment of the present disclosure, the orthographic projection of the hollow region on the base substrate overlaps with the orthographic projection of the initialization signal line on the base substrate, the orthographic projection of the hollow region on the base substrate overlaps with the orthographic projection of the second conductive pattern on the base substrate, and the orthographic projection of the hollow region on the base substrate overlaps with the orthographic projection of the second electrode block on the base substrate.

[0019] For example, in the display substrate provided according to an embodiment of the present disclosure, the plurality of light-emitting element groups are arranged along the first direction to form a plurality of light-emitting element rows, and are arranged along the second direction to form a plurality of light-emitting element columns. Each of the light-emitting element groups includes one first light-emitting element, one second light-emitting element, one third light-emitting element, and one fourth light-emitting element. The first anode includes a main body portion. The orthographic projection of the effective light-emitting region of the first light-emitting element on the base substrate is located inside the orthographic projection of the main body portion of the first anode on the base substrate, and the main body portion of the first anode and the first anode have at least partially the same boundary. The first conductive portion and the second conductive portion included in the plurality of conductive portions are respectively located on both sides of the effective light-emitting region of the first light-emitting element in the first direction. The distance from the orthographic projection of the sealed annular portion on the base substrate to the orthographic projection of the center of the effective light-emitting region of the first light-emitting element on the base substrate is substantially the same as the distance from the orthographic projection of the second conductive portion on the base substrate to the orthographic projection of the center of the effective light-emitting region of the first light-emitting element on the base substrate.

[0020] For example, in the display substrate provided according to an embodiment of the present disclosure, the orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the light-emitting control line of the first pixel driving circuit on the base substrate. At a position adjacent to the center of the hollow region in the second direction, one fourth light-emitting element is installed, where the orthographic projection of the anode on the base substrate overlaps with the orthographic projections of the gate line, the reset signal line, and the initialization signal line on the base substrate.

[0021] For example, in the display substrate provided according to an embodiment of the present disclosure, the orthographic projection of the gate line on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate. In one of the pixel driving circuits, the orthographic projections of the first electrode block and the second electrode block on the base substrate are located between the orthographic projection of the gate line on the base substrate and the orthographic projection of the light emission control line on the base substrate. The orthographic projection of the reset signal line on the base substrate is located between the orthographic projection of the gate line on the base substrate and the orthographic projection of the initialization signal line on the base substrate. The light emission control line, the first electrode block, the gate line, the reset signal line, and the initialization signal line are arranged along the second direction.

[0022] For example, in the display substrate provided according to an embodiment of the present disclosure, the plurality of pixel driving circuits further include a second gate electrode layer located on a side of the first conductive layer close to the base substrate. The second electrode block is located in the second gate electrode layer, and at least two of the second electrode blocks are connected to the second gate electrode layer.

[0023] For example, in the display substrate provided according to an embodiment of the present disclosure, the orthographic projections of the effective light emission regions of the first light emitting element and the second light emitting element on the base substrate do not overlap with the orthographic projection of the conductive portion on the base substrate. The second light emitting element is configured to emit green light. The orthographic projection of the center of the effective light emission region of the fourth light emitting element on the base substrate overlaps with the orthographic projection of the conductive portion on the base substrate. The overlapping portion of the conductive portion and the orthographic projection of the center of the effective light emission region of the fourth light emitting element on the base substrate is a solid portion. The fourth light emitting element is configured to emit blue light.

[0024] For example, in the display substrate provided according to an embodiment of the present disclosure, the second light-emitting element includes a second anode, and an orthographic projection of the effective light-emitting region of the second light-emitting element on the base substrate is located inside an orthographic projection of the main body portion of the second anode on the base substrate, and the main body portion of the second anode and the second anode have at least a partially same boundary, and an overlapping area between the main body portion of the second anode and two conductive portions adjacent to the second anode in the first direction is substantially the same.

[0025] For example, in the display substrate provided according to an embodiment of the present disclosure, an orthographic projection of the hollow region on the base substrate is located between the effective light-emitting region of the first light-emitting element and the effective light-emitting region of the second light-emitting element, and the first light-emitting element and the second light-emitting element are the first light-emitting element and the second light-emitting element closest in distance in the first direction.

[0026] For example, in the display substrate provided according to an embodiment of the present disclosure, a size of an intermediate portion in the first direction of an anode of a light-emitting element configured to emit red light in the second direction is larger than a size of an edge portion in the first direction of the anode in the second direction, and a size of an intermediate portion in the first direction of an anode of a light-emitting element configured to emit blue light in the second direction is larger than a size of an edge portion in the first direction of the anode in the second direction.

[0027] For example, in the display substrate provided according to an embodiment of the present disclosure, in one of the light-emitting element groups, an orthographic projection of anodes of at least two light-emitting elements on the base substrate overlaps an orthographic projection of the opening of the second electrode block on the base substrate, and an orthographic projection of the effective light-emitting region of at least one light-emitting element on the base substrate does not overlap an orthographic projection of the first electrode block or the second electrode block on the base substrate.

[0028] For example, in the display substrate provided according to an embodiment of the present disclosure, among any of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element, the anode of the light-emitting element is connected to the pixel driving circuit corresponding to the light-emitting element through the anode hole included in the first flat layer, and the orthographic projection of the anode hole of the anode of the light-emitting element configured to emit red light on the base substrate does not overlap with the orthographic projection of the main body portion of the anode on the base substrate in the second direction, and the orthographic projection of the anode hole of the anode of the light-emitting element configured to emit red light on the base substrate does not overlap with the orthographic projection of the effective light-emitting region of the light-emitting element configured to emit red light on the base substrate in the second direction, the orthographic projection of the anode hole of the anode of the light-emitting element configured to emit blue light on the base substrate does not overlap with the orthographic projection of the main body portion of the anode on the base substrate in the second direction, and the orthographic projection of the anode hole of the anode of the light-emitting element configured to emit blue light on the base substrate does not overlap with the orthographic projection of the effective light-emitting region of the light-emitting element configured to emit blue light on the base substrate in the second direction.

[0029] For example, in the display substrate provided according to an embodiment of the present disclosure, a data line is installed between two adjacent conductive portions, and the distance between the orthographic projections of the adjacent conductive portion and the data line on the base substrate is shorter than the distance between the orthographic projections of the two adjacent conductive portions on the base substrate.

[0030] At least one embodiment of the present disclosure further provides a display device including the display substrate described in any of the above.

Brief Description of the Drawings

[0031] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. Obviously, the drawings in the following description are only some embodiments of the present disclosure and do not limit the present disclosure.

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DETAILED DESCRIPTION OF THE INVENTION

[0032] To more clearly illustrate the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments of the present disclosure described, any other embodiments that can be obtained by those skilled in the art without creative labor shall fall within the scope of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meaning that can be understood by those skilled in the art. The "first", "second", and similar terms used in the present disclosure do not indicate any order, quantity, or importance, and are only used to distinguish different components. Terms such as "comprising" or "including" mean that the elements or elements shown before the term cover the elements or elements listed after the term and their equivalents, but do not exclude other elements or elements.

[0034] A display device has many performance specifications such as power, brightness, color coordinates, etc., and color bleeding is one of the important parameters among them. Usually, there are many factors that affect the color bleeding of an organic light-emitting diode (OLED) display device. From the perspective of the design of the display substrate (the array substrate or the rear panel of the organic light-emitting diode), the flatness of the anode has a great impact on color bleeding.

[0035] FIG. 1 is a schematic partial cross-sectional view of a display substrate. FIG. 2 shows a schematic view of the display substrate shown in FIG. 1 emitting light. As shown in FIG. 1, the sub-pixels of the display substrate include a base substrate 110 arranged in sequence, a semiconductor layer 120, a first gate layer 130, a second gate layer 140, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, an anode 175, and a pixel definition layer 190. The semiconductor layer 120, the first gate layer 130, the second gate layer 140, and the first conductive layer 150 can form a pixel driving circuit including a thin-film transistor and a storage capacitor. The second conductive layer 160 includes a connection electrode 161 connected to the pixel driving circuit through a via (not shown) in the first planarization layer 241. The anode 170 is connected to the connection electrode 161 through a via 271 in the second planarization layer 242. The pixel definition layer 190 includes an opening 191 for exposing a part of the anode 170. When a subsequent organic light-emitting layer 180 is formed in the opening 191, the anode 175 can contact the organic light-emitting layer 180 to drive the organic light-emitting layer to emit light. The region defined by the opening 191 is the effective light-emitting region of the sub-pixel.

[0036] The via 271 in the second planarization layer 242 affects the flatness of the anode 175. When the distance between the via 271 and the opening 191 (i.e., the effective light-emitting region) is close, the anode 175 at the position of the opening 191 "tilts", causing the light-emitting direction of the sub-pixel to shift. When the "tilting" directions of the anodes of sub-pixels of different colors are different, the intensities of light emitted from sub-pixels of different colors (e.g., red, green, blue) in different directions do not match, resulting in a color bleeding phenomenon. For example, when observing from one side of the display device having the display substrate, the display screen turns red, but when observing from the other side of the display device, the display screen turns blue.

[0037] In contrast, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, and a plurality of light-emitting element groups. The first conductive layer is located on the base substrate. The first flat layer is located on a side of the first conductive layer away from the base substrate. The second conductive layer is located on a side of the first flat layer away from the first conductive layer. The second flat layer is located on a side of the second conductive layer away from the first flat layer. The plurality of light-emitting element groups are located on a side of the second flat layer away from the base substrate. The plurality of light-emitting element groups are arranged along a first direction to form a plurality of light-emitting element columns, and are arranged along a second direction to form a plurality of light-emitting element rows. Each of the light-emitting element groups includes one first light-emitting element, one second light-emitting element, one third light-emitting element, and one fourth light-emitting element. The second light-emitting element and the third light-emitting element are arranged along the second direction to form a light-emitting element pair. The first light-emitting element, the light-emitting element pair, and the third light-emitting element are arranged along the first direction. The first light-emitting element includes a first anode. The second light-emitting element includes a second anode. The third light-emitting element includes a third anode. The fourth light-emitting element includes a fourth anode. The second conductive layer includes a first connection electrode, a second connection electrode, a third connection electrode, and a fourth connection electrode. The second flat layer includes a first via, a second via, a third via, and a fourth via. The first anode is connected to the first connection electrode through the first via. The second anode is connected to the second connection electrode through the second via. The third anode is connected to the third connection electrode through the third via. The fourth anode is connected to the fourth connection electrode through the fourth via. A plurality of third vias corresponding to one light-emitting element row are substantially on a first straight line extending along the first direction, and an orthographic projection of the fourth via closest to the first straight line on the base substrate is located on a side close to the fourth anode corresponding to the fourth via of the first straight line.Thereby, the display substrate moves the position of the fourth via in a direction closer to the fourth anode, increasing the distance between the fourth via and the effective light-emitting region of the first light-emitting element adjacent thereto, thereby ensuring the flatness of the first anode located in the effective light-emitting region of the first light-emitting element, further avoiding the occurrence of color mixing phenomenon, shortening the distance between the fourth via and the effective light-emitting region of the fourth light-emitting element, reducing the resistance between the fourth anode located in the effective light-emitting region of the fourth light-emitting element and the fourth connection electrode, and increasing the distance between the first anode and the fourth anode, so as to avoid the short circuit between the first anode and the fourth anode caused by residues in the manufacturing process.

[0038] Hereinafter, with reference to the drawings, the display substrate and the display device provided by the embodiments of the present disclosure will be described in detail.

[0039] An embodiment of the present disclosure provides a display substrate. FIG. 3 is a schematic plan view of a display substrate according to an embodiment of the present disclosure, FIGS. 4A and 4B are schematic cross-sectional views of the display substrate in the AA direction of FIG. 3 according to an embodiment of the present disclosure, FIG. 5A is a schematic cross-sectional view of the display substrate in the BB direction of FIG. 3 according to an embodiment of the present disclosure, FIG. 5B is a schematic cross-sectional view of the display substrate in the GB direction of FIG. 3 according to an embodiment of the present disclosure, and FIG. 6 is a schematic plan view of a light-emitting element of the display substrate according to an embodiment of the present disclosure.

[0040] As shown in FIGS. 3, 4A, 4B, 5A, 5B, and 6, the display substrate 100 includes a base substrate 110, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, and a plurality of light-emitting element groups 310. The first conductive layer 150 is located on the base substrate 110. The first planarization layer 241 is located on a side of the first conductive layer 150 away from the base substrate 110. The second conductive layer 160 is located on a side of the first planarization layer 241 away from the first conductive layer 150. The second planarization layer 242 is located on a side of the second conductive layer 160 away from the first planarization layer 241. The plurality of light-emitting element groups 310 are located on a side of the second planarization layer 242 away from the base substrate 110.The plurality of light-emitting element groups 310 are arranged along the first direction to form a plurality of light-emitting element columns 320, and are arranged along the second direction to form a plurality of light-emitting element rows 330. Each of the light-emitting element groups 310 includes one first light-emitting element 311, one second light-emitting element 312, one third light-emitting element 313, and one fourth light-emitting element 314. The second light-emitting element 312 and the third light-emitting element 313 are arranged along the second direction to form a light-emitting element pair 315. The first light-emitting element 311, the light-emitting element pair 315, and the fourth light-emitting element 314 are arranged along the first direction. The first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754. The second conductive layer 160 includes a first connection electrode 1611, a second connection electrode 1612, a third connection electrode 1613, and a fourth connection electrode 1614. The second flat layer 242 includes a first via 2421, a second via 2422, a third via 2423, and a fourth via 2424. The first anode 1751 is connected to the first connection electrode 1611 through the first via 2421, the second anode 1752 is connected to the second connection electrode 1612 through the second via 2422, the third anode 1753 is connected to the third connection electrode 1613 through the third via 2423, and the fourth anode 1754 is connected to the fourth connection electrode 1614 through the fourth via 2424. The plurality of third vias 2423 corresponding to one light-emitting element row 330 are substantially on a first straight line 301 extending along the first direction. The orthographic projection of the fourth via 2424 closest to the first straight line 301 on the base substrate 110 is located on the side close to the fourth anode 1754 corresponding to the fourth via 2424 of the first straight line 301. However, the first conductive layer and the second conductive layer are sequentially stacked and provided along the direction away from the base substrate.

[0041] In the display substrate provided by the embodiments of the present disclosure, the second light-emitting element and the third light-emitting element are arranged along a second direction to form a light-emitting element pair, and the first light-emitting element, the light-emitting element pair, and the third light-emitting element are arranged along a first direction. That is, the second anode and the third anode are arranged along the second direction to form an anode pair, and the first anode, the anode pair, and the third anode are arranged along the first direction. The orthographic projection of the fourth via closest to the first straight line on the base substrate is located on the side closer to the fourth anode of the first straight line, that is, the display substrate moves the position of the fourth via in the direction closer to the fourth anode. Thereby, the display substrate has the following beneficial effects. (1) By increasing the distance between the fourth via and the effective light-emitting region of the first light-emitting element adjacent thereto, the flatness of the first anode located in the effective light-emitting region of the first light-emitting element is ensured, and further the occurrence of color bleeding phenomenon is avoided. (2) By shortening the distance between the fourth via and the effective light-emitting region of the fourth light-emitting element, the resistance between the fourth anode and the fourth connection electrode located in the effective light-emitting region of the fourth light-emitting element is reduced. (3) By increasing the distance between the first anode and the fourth anode, the short circuit between the first anode and the fourth anode due to residues in the manufacturing process can be avoided.

[0042] For example, as shown in FIGS. 5A, 5B, and 6, the display substrate moves the position of the fourth via 2424 in a direction closer to the fourth anode 1754. Accordingly, the distance between the effective light-emitting region of the first light-emitting element adjacent to the fourth via 2424 (i.e., the region defined by the opening 1951) increases. And since the fourth anode has a connection portion connected to the pixel driving circuit below it, even if the position of the fourth via 2424 is moved in a direction closer to the fourth anode 1754, it does not overlap with the effective light-emitting region of the fourth light-emitting element (i.e., the region defined by the opening 1954). At this time, there is an appropriate distance between the effective light-emitting region of the first light-emitting element adjacent to the fourth via 2424 and the effective light-emitting region of the fourth light-emitting element. Thereby, the flatness of the first anode located in the effective light-emitting region of the first light-emitting element and the fourth anode located in the effective light-emitting region of the fourth light-emitting element can be ensured simultaneously, and furthermore, the occurrence of color bleeding phenomenon can be avoided.

[0043] For example, as shown in FIGS. 5A, 5B, and 6, by moving the position of the fourth via 2424 in a direction closer to the fourth anode 1754, the display substrate further shortens the distance between the fourth via 2424 and the effective light-emitting region of the fourth light-emitting element, thereby reducing the resistance between the fourth anode located in the effective light-emitting region of the fourth light-emitting element and the fourth connection electrode. On the other hand, by moving the position of the fourth via 2424 in a direction closer to the fourth anode 1754, the display substrate further increases the distance between the first anode 1751 and the fourth anode 1754, thereby avoiding a short circuit between the first anode 1751 and the fourth anode 1754 due to residues in the manufacturing process.

[0044] For example, the shortest distance between the orthographic projection of the first anode on the base substrate and the orthographic projection of the adjacent fourth anode on the base substrate exceeds 0.8 times the width of the effective light-emitting region of the first light-emitting element in the first direction, thereby effectively avoiding a short circuit between the first anode and the fourth anode due to residues in the manufacturing process.

[0045] For example, as shown in FIG. 6, the fourth anode 1754 includes a main body portion 1754A and a connection portion 1754B. The effective light-emitting region of the fourth light-emitting element 314 is inside the orthographic projection of the main body portion 1754A on the base substrate 110. The connection portion 1754B is connected to the corresponding fourth connection electrode 1614 via the fourth via 2424, and is located on the side closer to the main body portion 1754A of the first straight line 301, thereby effectively reducing the area of the connection portion, and thereby reducing the resistance between the fourth anode located in the effective light-emitting region of the fourth light-emitting element and the fourth connection electrode. For example, as shown in FIG. 6, the fourth anode 1754 further includes a first supplementary portion 1754C. The first supplementary portion 1754C can cover two channel regions of the compensation thin-film transistor of the corresponding pixel driving circuit, thereby enhancing the stability of the compensation thin-film transistor, extending the service life, enhancing the long-term light-emitting stability of the display substrate, and extending the service life.

[0046] In some examples, as shown in FIG. 6, the first supplementary portion 1754C protrudes from the fourth main body portion 1754A toward the third anode 1753 and is located on the side closer to the fourth main body portion 1754A of the fourth connection portion 1754B.

[0047] In some examples, as shown in FIG. 6, the first supplementary portion 1754C is connected to both the fourth main body portion 1754A and the fourth connection portion 1754B. Thereby, the display substrate makes full use of the area on the display substrate to closely arrange the first anode, the second anode, the third anode, and the fourth anode, thereby ensuring the resolution of the display substrate.

[0048] For example, as shown in FIG. 4A, the display substrate includes a base substrate 110, a semiconductor layer 120, a first insulating layer 361, a first gate layer 130, a second insulating layer 362, a second gate layer 140, an interlayer insulating layer 363, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, and a second planarization layer 242, which are sequentially arranged. The first gate layer 130 may include a gate line 131 and a first electrode block CE1, and the second gate layer may include a second gate block CE2. The orthographic projection of the first electrode block CE1 on the base substrate 110 and the orthographic projection of the second electrode block CE2 on the base substrate 110 at least partially overlap, thereby forming a storage capacitor.

[0049] For example, as shown in FIG. 4A, the first conductive layer 150 may further include a power line and a data line. The second conductive layer 160 may overlap with the power line and be electrically connected to the power line, and may include a conductive portion capable of reducing the resistance of the power line.

[0050] For example, as shown in FIG. 4B, the display substrate may further include a protective layer 364 located between the first conductive layer 150 and the first planarization layer 241. Of course, the embodiments of the present disclosure are not limited thereto, and the protective layer may not be provided on the display substrate.

[0051] In some examples, as shown in FIG. 6, a plurality of second vias 2422 corresponding to the light-emitting element rows 330 adjacent to the light-emitting element row 330 corresponding to the first straight line 301 are also substantially on the first straight line 301.

[0052] In some examples, as shown in FIG. 3, the fourth via 2424 of one light-emitting element group 310 is located on one side of the bisector along the second direction of the first anode 1751 of the light-emitting element group 310 adjacent to the light-emitting element group 310 in the second direction. For example, it is located on the side closer to the second anode 1752 of the light-emitting element group 310 where the first anode 1751 is located, of the bisector along the second direction of the first anode 1751. That is, the fourth via of one light-emitting element group is located on one side of the bisector along the second direction of the first anode of the light-emitting element group adjacent to the light-emitting element group in the second direction. In some examples, as shown in FIG. 3, in one light-emitting element group 310, the first via 2421 is located on one side of the bisector along the second direction of the first anode 1751. For example, it is located on the side closer to the third anode 1753 of the bisector along the second direction of the first anode 1751. The second via 2422 is located on the side closer to the first anode 1751 of the bisector along the second direction of the second anode 1752. The third via 2423 is located on the side closer to the first anode 1751 of the bisector along the second direction of the third anode 1753.

[0053] In some examples, as shown in FIG. 6, a plurality of fourth vias 2424 corresponding to one light-emitting element row 330 extend substantially along the first direction and are on a straight line passing through a plurality of first anodes 1751 or a plurality of first vias 2421 corresponding to the light-emitting element row 330.

[0054] In some examples, as shown in FIG. 6, a plurality of fourth vias 2424 corresponding to one light-emitting element column 320 extend substantially along the second direction and are on a second straight line passing through a plurality of first anodes 1751 or the effective light-emitting regions of a plurality of first light-emitting elements 311 corresponding to the light-emitting element column 320.

[0055] In some examples, as shown in FIG. 6, the distance from the fourth anode 1754 to the first anode 1751 closest to it is smaller than the distance from the first anode 1751 located in the same row to the fourth anode 1754 closest to it.

[0056] In some examples, as shown in FIG. 6, the light-emitting element group 310 includes a first light-emitting element group and a second light-emitting element group that are adjacent to each other in the second direction and are installed in two adjacent light-emitting element rows 330 respectively. The connection portions of the fourth anode 1754 of the first light-emitting element group and the first anode 1751 of the second light-emitting element group are both located on the same side of the bisector along the second direction of the fourth anode 1754. That is, on the same side of the bisector along the second direction of the main body portion of the fourth anode, the connection portion of the fourth anode and the connection portion of the first anode adjacent to the fourth anode in the second direction are installed.

[0057] In some examples, as shown in FIG. 6, the shape of the main body portion of the first anode 1751 includes a hexagon, and the point on the first anode 1751 closest to the fourth anode 1754 adjacent to the first anode 1751 in the second direction is the vertex of the hexagon.

[0058] In some examples, as shown in FIG. 6, two adjacent light-emitting element rows 330 are installed with a 1 / 2 pitch shift, and the pitch is equal to the distance between the centers of the effective light-emitting regions of two first light-emitting elements 311 of two light-emitting element groups 310 adjacent to each other in the first direction.

[0059] In some examples, as shown in FIG. 6, the first straight line 301 is located between two adjacent light-emitting element rows 330.

[0060] In some examples, as shown in FIGS. 5A, 5B, and 6, the orthographic projection of the first via 2421 closest to the first straight line 301 on the base substrate 110 is located on the side closer to the first anode 1751 corresponding to the first via 2421 of the first straight line 301. That is, the display substrate moves the position of the first via in a direction closer to the first anode. Thereby, the display substrate has the following beneficial effects. (1) Increase the distance between the first via and the effective light-emitting region of the fourth light-emitting element closest in the second direction, thereby ensuring the flatness of the fourth anode located in the effective light-emitting region of the adjacent fourth light-emitting element, and further avoiding the occurrence of color mixing phenomenon. (2) Shorten the distance between the first via and the effective light-emitting region of the first light-emitting element, thereby reducing the resistance between the first anode located in the effective light-emitting region of the first light-emitting element and the first connection electrode. (3) Increase the distance between the first anode and the fourth anode, thereby avoiding the short circuit between the first anode and the fourth anode due to residues in the manufacturing process. Of course, the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the first via on the base substrate may be on the first straight line.

[0061] In some examples, as shown in FIG. 6, the distance between the orthographic projection of the fourth via 2424 on the base substrate 110 and the orthographic projection of the first straight line 301 on the base substrate 110 is greater than the distance between the orthographic projection of the first via 2421 on the base substrate 110 and the orthographic projection of the first straight line 301 on the base substrate 110. That is, the offset amount of the fourth via is larger than that of the first via compared to the first straight line. Of course, the embodiments of the present disclosure are not limited thereto, and the offset amount of the fourth via may be the same as the offset amount of the first via compared to the first straight line.

[0062] In some examples, as shown in FIG. 6, there is a first shortest distance L1 between the orthographic projection of the effective light-emitting region of the second light-emitting element 312 on the base substrate 110 and the orthographic projection of the second via 2422 on the base substrate 110, and there is a second shortest distance L2 between the orthographic projection of the effective light-emitting region of the third light-emitting element 313 on the base substrate 110 and the orthographic projection of the third via 2423 on the base substrate 110. The first shortest distance L1 and the second shortest distance L2 are substantially the same. However, the fact that the first shortest distance and the second shortest distance are substantially the same not only includes the case where the first shortest distance and the second shortest distance are exactly the same, but also includes the case where the difference between the first shortest distance and the second shortest distance is less than 1 micron.

[0063] Thereby, according to the display substrate, it is possible to make the inclination degrees of the second anode located in the effective light-emitting region of the second light-emitting element and the third anode located in the effective light-emitting region of the third light-emitting element the same, but the inclination directions are opposite, so that the occurrence of the color overlapping phenomenon can be effectively avoided. However, when the second anode located in the effective light-emitting region of the second light-emitting element and the third anode located in the effective light-emitting region of the third light-emitting element are not inclined, the inclination degree of the second anode in the effective light-emitting region of the second light-emitting element and the third anode located in the effective light-emitting region of the third light-emitting element is considered to be zero. Also, the first shortest distance between the orthographic projection of the base substrate of the effective light-emitting region of the second light-emitting element and the orthographic projection of the second via on the base substrate may be the shortest distance between the edge of the orthographic projection of the base substrate of the effective light-emitting region of the second light-emitting element and the edge of the orthographic projection of the second via on the base substrate. Similarly, the second shortest distance between the orthographic projection of the base substrate of the effective light-emitting region of the third light-emitting element and the orthographic projection of the third via on the base substrate may be the shortest distance between the edge of the orthographic projection of the base substrate of the effective light-emitting region of the third light-emitting element and the edge of the orthographic projection of the third via on the base substrate.

[0064] In some examples, as shown in FIG. 6, the distance C between the orthographic projection of the fourth via 2424 on the base substrate 110 and the orthographic projection of the effective light-emitting region of the first light-emitting element 311 adjacent in the second direction on the base substrate 110 exceeds 1.2 times the width A in the first direction of the effective light-emitting region of the first light-emitting element 311 adjacent in the second direction. Thereby, the display substrate can ensure that the first anode located in the effective light-emitting region of the first light-emitting element has relatively high flatness.

[0065] In some examples, as shown in FIG. 6, the shortest distance B between the fourth via 2424 of one light-emitting element group 310 and the first anode 1751 of the adjacent light-emitting element group 310 is less than the distance E between the fourth via 2424 of the light-emitting element group 310 and the effective light-emitting region of the corresponding fourth light-emitting element 314.

[0066] In some examples, as shown in FIG. 6, the shortest distance between the fourth anode 1754 of one light-emitting element group 310 and the first anode 1751 of the light-emitting element group 310 that is closest to the fourth anode 1754 in the second direction is the distance between the vertex of the first anode 1751 of the adjacent light-emitting element group 310 and the fourth anode 1754 of the light-emitting element group 310. That is, the vertex of the first anode 1751 of the adjacent light-emitting element group 310 is the point closest to the fourth anode 1754 of the light-emitting element group 310. For example, the shape of the orthographic projection of the first anode 1751 on the base substrate 110 is hexagonal, and the above vertex is the vertex on the major axis of the hexagon.

[0067] In some examples, as shown in FIGS. 3, 4A, 4B, 5A, 5B, and 6, the display substrate 100 is located on one side away from the base substrate 110 of the first anode 1751, the second anode 1752, the third anode 1753, and the fourth anode 1754, and further includes a pixel defining layer 190 having a first opening 1951, a second opening 1952, a third opening 1953, and a fourth opening 1954. The first light-emitting element 311 includes a first light-emitting portion 1851, the second light-emitting element 312 includes a second light-emitting portion 1852, the third light-emitting element 313 includes a third light-emitting portion 1853, and the fourth light-emitting element 314 includes a fourth light-emitting portion 1854. The first opening 1951 is inside the orthographic projection of the first anode 1751 on the base substrate 110, and at least a part of the first light-emitting portion 1851 is located in the first opening 1951 to cover the exposed portion of the first anode 1751. The second opening 1952 is inside the orthographic projection of the second anode 1752 on the base substrate 110, and at least a part of the second light-emitting portion 1852 is located in the second opening 1952 to cover the exposed portion of the second anode 1752. The third opening 1953 is inside the orthographic projection of the third anode 1753 on the base substrate 110, and at least a part of the third light-emitting portion 1853 is located in the third opening 1953 to cover the exposed portion of the third anode 1753. The fourth opening 1954 is inside the orthographic projection of the fourth anode 1754 on the base substrate 110, and at least a part of the fourth light-emitting portion 1854 is located in the fourth opening 1954 to cover the exposed portion of the fourth anode 1754. The region defined by the first opening 1951 is the effective light-emitting region of the first light-emitting element 311, the region defined by the second opening 1952 is the effective light-emitting region of the second light-emitting element 312, the region defined by the third opening 1953 is the effective light-emitting region of the third light-emitting element 313, and the region defined by the fourth opening 1954 is the effective light-emitting region of the fourth light-emitting element 314.

[0068] In some examples, as shown in FIG. 6, the distance C between the orthographic projection of the fourth via 2424 on the base substrate 110 and the orthographic projection of the first opening 1951 adjacent to the second direction on the base substrate 110 exceeds 1.2 times the width A of the first opening 1951 in the first direction. Thereby, it can be ensured that the first anode located in the first opening (i.e., the portion of the first anode exposed by the first opening) of the display substrate has relatively high flatness.

[0069] In some examples, as shown in FIGS. 3, 4A, 4B, 5A, 5B, and 6, the display substrate 100 includes a first flat layer 241 and a first conductive layer 150. The first flat layer 241 is located on the side closer to the base substrate 110 of the second conductive layer 160, and the first conductive layer 150 is located on the side closer to the base substrate 110 of the first flat layer 241. The first conductive layer 150 includes a first drain 1511, a second drain 1512, a third drain 1513, and a fourth drain 1514. The first flat layer 241 includes a fifth via 2415, a sixth via 2416, a seventh via 2417, and an eighth via 2418. The first connection electrode 1611 is connected to the first drain 1511 through the fifth via 2415. The second connection electrode 1612 is connected to the second drain 1512 through the sixth via 2416. The third connection electrode 1613 is connected to the third drain 1513 through the seventh via 2417. The fourth connection electrode 1614 is connected to the fourth drain 1514 through the eighth via 2418.

[0070] In some examples, as shown in FIGS. 4A and 4B, the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654. The first drain 1511 is part of the first pixel driving circuit 2651, the second drain 1512 is part of the second pixel driving circuit 2652, the third drain 1513 is part of the third pixel driving circuit 2653, and the fourth drain 1514 is part of the fourth pixel driving circuit 2654. The first pixel driving circuit 2651 is connected to the first anode 1751 via the first connection electrode 1611 to apply a driving signal to the first anode 1751. The second pixel driving circuit 2652 is connected to the second anode 1752 via the second connection electrode 1612 to apply a driving signal to the second anode 1752. The third pixel driving circuit 2653 is connected to the third anode 1753 via the third connection electrode 1613 to apply a driving signal to the third anode 1753. The fourth pixel driving circuit 2654 is connected to the fourth anode 1754 via the fourth connection electrode 1614 to apply a driving signal to the fourth anode 1754.

[0071] FIG. 7 is a schematic diagram of the planar relationship between the second conductive layer and the anode layer of the display substrate according to an embodiment of the present disclosure. As shown in FIGS. 6 and 7, the second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, and the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the first direction. The second conductive layer 160 further includes a first conductive portion 1621, a second conductive portion 1622, a third conductive portion 1623, and a fourth conductive portion 1624 that extend along the second direction. The first conductive portion 1621 is located on one side of the anode pair 1755 away from the first anode 1751, the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755, the third conductive portion 1623 is located between the anode pair 1755 and the fourth anode 1754, and the fourth conductive portion 1624 overlaps with the fourth anode 1754. In the display substrate, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, and the fourth conductive portion 1624 that extend along the second direction are connected to the power line of the first conductive layer 150, and the resistance of the power line can be reduced.

[0072] In some examples, as shown in FIG. 7, the orthographic projection of the first conductive portion 1621 and the second conductive portion 1622 on the base substrate 110 does not overlap with the orthographic projection of the first anode 1751 on the base substrate 110, and the orthographic projection of the second conductive portion 1622 and the third conductive portion 1623 on the base substrate 110 does not overlap with the orthographic projection of the anode pair 1755 on the base substrate 110. Thereby, the first conductive portion 1621 and the second conductive portion 1622 hardly affect the flatness of the first anode 175, and the second conductive portion 1622 and the third conductive portion 1623 hardly affect the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755. Of course, the embodiments of the present disclosure are not limited thereto, and the first conductive portion, the second conductive portion, and the third conductive portion may overlap with the anode.

[0073] For example, the orthographic projections of the first conductive portion 1621 and the second conductive portion 1622 on the base substrate 110 respectively have the orthographic projections of the first anode 1751 on the base substrate 110 and the first overlapping portion and the second overlapping portion, and the areas of the first overlapping portion and the second overlapping portion are substantially the same, whereby the flatness of the first anode 1751 can be improved. Similarly, the orthographic projections of the second conductive portion 1622 and the third conductive portion 1623 on the base substrate 110 respectively have the orthographic projections of the anode pair 1755 on the base substrate 110 and the third overlapping portion and the fourth overlapping portion, and the areas of the third overlapping portion and the fourth overlapping portion are substantially the same, whereby the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755 can be improved. However, the above "substantially the same" includes the case where they are completely the same and the case where the difference between the two is less than 10% of the average value of the two.

[0074] For example, the first overlapping portion and the second overlapping portion are symmetric with respect to the bisector along the second direction of the main body portion of the first anode 1751, that is, the effective light-emitting region of the first light-emitting element 311, whereby the flatness of the effective light-emitting region of the first light-emitting element 311 can be further enhanced. The third overlapping portion and the fourth overlapping portion are symmetric with respect to the bisector along the second direction of the anode pair 1755, whereby the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755 can also be further enhanced.

[0075] In some examples, as shown in FIG. 7, the orthographic projection of the fourth conductive portion 1624 on the base substrate 110 passes through the center of the orthographic projection of the fourth anode 1754 on the base substrate 110, and the orthographic projection of the bisector along the second direction of the fourth conductive portion 1624 on the base substrate 110 overlaps with the orthographic projection of the bisector along the second direction of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110. Thereby, the flatness of the fourth anode 1754 can also be improved.

[0076] In some examples, as shown in FIG. 7, the second conductive layer 160 further includes a fifth conductive portion 1625 and a sixth conductive portion 1626 that extend along a first direction. The fifth conductive portion 1625 is connected to the second conductive portion 1622 and the third conductive portion 1623 respectively, and is located between the second anode 1752 and the third anode 1753. The sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624 respectively, and is located between the first anode 1751 and the fourth anode 1754 that are adjacent in the second direction. Thereby, the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625, and the sixth conductive portion 1626 can form a mesh structure, thereby further reducing the resistance of the power line of the first conductive layer and further improving the electrical performance of the display substrate.

[0077] In some examples, as shown in FIG. 7, the second conductive portion 1622 includes a main body portion 1622A, a spacer block 1622B, and a connection block 1622C that extend along a second direction. The spacer block 1622B is located on a side of the main body portion 1622A close to the first anode 1751, and is installed at an interval from the main body portion 1622A, and is connected to the main body portion 1622A through the connection block 1622C. Generally, since the size (i.e., width) of the first anode in the first direction is small, the distance between the first conductive portion and the main body portion of the second conductive portion is large. By installing the spacer block, the symmetry between the first conductive portion on both sides of the first anode and the second conductive portion can be improved, thereby improving the flatness of the first anode.

[0078] In some examples, the first light-emitting element is configured to emit light of a first color, the second light-emitting element and the third light-emitting element are configured to emit light of a second color, and the fourth light-emitting element is configured to emit light of a third color.

[0079] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is, the display substrate uses a pixel arrangement structure of GGRB.

[0080] One embodiment of the present disclosure further provides a display device. FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 8, the display device 400 includes the display substrate 100 described in any of the above. Thereby, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can ensure the flatness of the first anode located in the effective light-emitting region of the first light-emitting element, thereby avoiding the occurrence of color mixing phenomenon, reducing the resistance between the fourth anode located in the effective light-emitting region of the fourth light-emitting element and the fourth connection electrode, and increasing the distance between the first anode and the fourth anode, thereby avoiding the short circuit between the first anode and the fourth anode caused by residues in the manufacturing process.

[0081] For example, the display device may be a display panel, or may be an electronic product having a display function such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigator, and a digital photo frame.

[0082] On the other hand, the inventor of the present application has found that since the thickness of the second source / drain metal layer under the anode is large and unevenly distributed, the second source / drain metal layer also causes the phenomenon that the anode is not flat.

[0083] FIG. 9 is a schematic partial cross-sectional view of another display substrate, and FIG. 10 is a schematic partial cross-sectional view of another display substrate. As shown in FIG. 9, the second source / drain metal layer 160 includes a plurality of wirings 168, and there is a wiring 168 on one side below the anode 175, but there is no wiring 168 on the other side. In this case, there is a height difference on both sides of the anode 175, thereby causing the "tilt" phenomenon of the anode 175 and further causing the color bleeding phenomenon. As shown in FIG. 10, when there are wirings 168 on both sides of the anode 175 or there is no wiring 168 below the anode 175, the anode 175 can ensure a higher flatness, thereby ensuring that the light emission intensities in different directions of the anode 175 are consistent, and further effectively improving the color bleeding phenomenon.

[0084] In contrast, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer, and a plurality of light-emitting element groups. The first conductive layer is located on the base substrate. The first flat layer is located on a side of the first conductive layer away from the base substrate. The second conductive layer is located on a side of the first flat layer away from the first conductive layer. The second flat layer is located on a side of the second conductive layer away from the first flat layer. The plurality of light-emitting element groups are located on a side of the second flat layer away from the second conductive layer. The plurality of light-emitting element groups are arranged along a first direction to form a plurality of light-emitting element columns, and are arranged along a second direction to form a plurality of light-emitting element rows. Each of the light-emitting element groups includes one first light-emitting element, one second light-emitting element, one third light-emitting element, and one fourth light-emitting element. The first light-emitting element includes a first anode. The second conductive layer includes a first conductive portion and a second conductive portion extending along the second direction. The first conductive portion is located on one side of the first anode. The second conductive portion is located on a side of the first anode away from the first conductive portion. The first conductive portion includes an extending portion and an offset portion. The orthographic projection of the effective light-emitting region of the first light-emitting element on a straight line extending along the second direction is covered by the orthographic projection of the offset portion on the straight line. The orthographic projection of the offset portion on the base substrate and the orthographic projection of the first anode on the base substrate are installed at an interval. The extending portion is close to the second conductive portion, and the straight line where the edge extending along the second direction is located is the first straight line. The offset portion is installed at an interval from the first straight line and is located on a side of the first straight line away from the second conductive portion. Thereby, the first conductive portion is located on one side of the first anode, the second conductive portion is located on a side of the first anode away from the first conductive portion, and the orthographic projection of the offset portion on the base substrate and the orthographic projection of the first anode on the base substrate are installed at an interval. Therefore, the first conductive portion and the second conductive portion of the second conductive layer hardly affect the flatness of the first anode. Thereby, the first anode can ensure a higher flatness, thereby ensuring that the light-emitting intensities in different directions of the first anode are consistent, and further effectively improving the color mixing phenomenon.

[0085] Hereinafter, the display substrate and the display device provided according to the embodiments of the present disclosure will be described in detail with reference to the drawings.

[0086] One embodiment of the present disclosure provides a display substrate. FIG. 11 is a schematic plan view of another display substrate according to an embodiment of the present disclosure, FIG. 12A is a schematic cross-sectional view of the display substrate in the HH direction of FIG. 11 according to an embodiment of the present disclosure, FIG. 12B is a schematic cross-sectional view of the display substrate in the JJ direction of FIG. 11 according to an embodiment of the present disclosure, FIG. 13 is a schematic plan view of another display substrate according to an embodiment of the present disclosure, and FIG. 14 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. In order to clearly show the positional relationship between each conductive part of the second conductive layer and the anode, only the second conductive layer and the anode layer are shown in FIG. 14.

[0087] As shown in FIGS. 11-14, the display substrate 100 includes a base substrate 110, a first conductive layer 150, a first planarizing layer 241, a second conductive layer 160, a second planarizing layer 242, and a plurality of light-emitting element groups 310. The second conductive layer 160 is located on the base substrate 110, the second planarizing layer 242 is located on a side of the second conductive layer 160 away from the base substrate 110, and the plurality of light-emitting element groups 310 are located on a side of the second planarizing layer 242 away from the base substrate 110. The plurality of light-emitting element groups 310 are arranged along a first direction to form a plurality of light-emitting element columns 320, and are arranged along a second direction to form a plurality of light-emitting element rows 330. Each of the light-emitting element groups 310 includes one first light-emitting element 311, one second light-emitting element 312, one third light-emitting element 313, and one fourth light-emitting element 314. The first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754. The second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, and the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the first direction. The second conductive layer 160 includes a first conductive portion 1621 and a second conductive portion 1622 that extend along the second direction. The first conductive portion 1621 is located on a side of the first anode 1751 away from the anode pair 1755, and the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755, that is, on a side of the first anode 1751 away from the first conductive portion 1621. The first conductive portion 1621 includes an extension portion 1621A and an offset portion 1621B. The orthographic projection of the first light-emitting element 311 on a straight line extending along the second direction of the effective light-emitting region is covered by the orthographic projection of the offset portion 1621B on the straight line, that is, the orthographic projection of the effective light-emitting region of the first light-emitting element 311 on the first conductive portion 1621 is at the position of the offset portion 1621B, that is, the offset portion 1621B corresponds to the effective light-emitting region of the first light-emitting element 311.The orthographic projection of the offset portion 1621B on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 are installed at intervals. The straight line where the edge of the extending portion 1621A extends along the second direction and is close to the second conductive portion 1622 is the first straight line 302. The offset portion 1621B is installed at an interval from the first straight line 302 and is located on one side away from the second conductive portion 1622 of the first straight line 302. However, the first conductive layer and the second conductive layer are sequentially stacked and provided along the direction away from the base substrate.

[0088] In the display substrate provided by the embodiments of the present disclosure, the first conductive portion is located on one side of the first anode, the second conductive portion is located on one side away from the first conductive portion of the first anode, and the orthographic projection of the offset portion on the base substrate and the orthographic projection of the first anode on the base substrate are installed at intervals. Therefore, the first conductive portion and the second conductive portion of the second conductive layer have little influence on the flatness of the first anode, so that the first anode can ensure a higher flatness, thereby ensuring that the light emission intensities in different directions of the first anode are consistent, and further effectively improving the color bleeding phenomenon. In addition, since the offset portion is installed at an interval from the first straight line and is located on one side away from the second conductive portion of the first straight line, the offset portion is offset in the direction away from the first anode, providing space for the installation of the first anode, thereby realizing the close arrangement of the anodes and at the same time ensuring a higher flatness of the first anode.

[0089] However, the arrangement mode of the plurality of light-emitting elements may refer to the arrangement mode shown in FIG. 6, that is, two adjacent light-emitting element rows are installed with a 1 / 2 pitch shift, and the pitch is equal to the distance between the centers of the effective light-emitting regions of two first light-emitting elements in two first light-emitting element groups adjacent in the first direction.

[0090] In some examples, the first light-emitting element 311 is configured to emit light of a first color, the second light-emitting element 312 and the third light-emitting element 313 are configured to emit light of a second color, and the fourth light-emitting element 314 is configured to emit light of a third color.

[0091] In some examples, the first color is red, the second color is green, and the third color is blue.

[0092] In some examples, as shown in FIGS. 11-14, the orthographic projection of the first straight line 302 on the base substrate 110 passes through the orthographic projection of the first anode 1751 on the base substrate 110. Thereby, the display substrate can realize a close arrangement of the anodes while ensuring a higher flatness of the first anode.

[0093] In some examples, as shown in FIGS. 11-14, the straight line where the bisector extending in the second direction of the extension portion 1621A is located is the second straight line 303, and the offset portion 1621B is installed at a distance from the second straight line 303 and is located on one side away from the second conductive portion 1622 of the second straight line 303. Thereby, since the offset portion is installed at a distance from the second straight line and is located on one side away from the anode pair of the second straight line, the offset portion is offset in a direction away from the first anode, providing a space for the installation of the first anode, thereby realizing a close arrangement of the anodes while ensuring a higher flatness of the first anode.

[0094] In some examples, as shown in FIGS. 11-14, the orthographic projection of the second straight line 303 on the base substrate 110 passes through the orthographic projection of the first anode 1751 on the base substrate 110. Thereby, the display substrate can realize a close arrangement of the anodes while ensuring a higher flatness of the first anode.

[0095] In some examples, as shown in FIGS. 11-14, the first anode 1751 extends along a second direction, the second conductive portion 1622 includes a main body portion 1622A and a spacer block 1622B that extend along the second direction, an orthographic projection of the main body portion 1622A on the base substrate 110 and an orthographic projection of the first anode 1751 on the base substrate 110 are spaced apart, the spacer block 1622B is located on a side of the main body portion 1622A close to the first anode 1751, and a distance between an orthographic projection of the spacer block 1622B on the base substrate 110 and an orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110 is substantially the same as a distance between an orthographic projection of the first conductive portion 1621 on the base substrate 110 and an orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110.

[0096] In the display substrate, generally, since the size (i.e., width) of the first anode in the first direction is small, the distance between the first conductive portion and the main body portion of the second conductive portion is large, and a distance between an orthographic projection of the spacer block on the base substrate and an orthographic projection of the center of the effective light-emitting region of the first light-emitting element on the base substrate is substantially the same as a distance between an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the center of the effective light-emitting region of the first light-emitting element on the base substrate. Therefore, when the spacer block is installed, the symmetry between the first conductive portion and the second conductive portion on both sides of the first anode can be improved, and further, the flatness of the first anode can be improved.

[0097] In some examples, as shown in FIGS. 11-14, a distance between an orthographic projection of the first conductive portion 1621 on the base substrate 110 and an orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110 is less than a distance between an orthographic projection of the main body portion 1622A on the base substrate 110 and an orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110.

[0098] For example, the ratio between the distance between the orthographic projection of the first conductive portion 1621 on the base substrate 110 and the orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110, and the distance between the orthographic projection of the main body portion 1622A on the base substrate 110 and the orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110 is 1 / 3 or less.

[0099] In some examples, as shown in FIGS. 11-14, the orthographic projection of the spacer block 1622B on the base substrate 110 and the orthographic projection of the main body portion 1622A on the base substrate 110 are installed at intervals, and the second conductive portion 1622 further includes a connection portion 1622C, and the spacer block 1622B is connected to the main body portion 1622A via the connection portion 1622C. Thereby, the spacer block 1622B is connected to the main body portion 1622A via the connection portion 1622C and is not integrally formed with the main body portion 1622A, so that excessive overlap between the second conductive portion 1622 and the underlying film layer such as a semiconductor layer, a gate layer, etc. can be avoided, thereby avoiding increasing the load on the film layer under the second conductive portion 1622. Thereby, the display substrate can increase the spacer block and ensure the normal operation of each sub-pixel.

[0100] For example, as shown in FIG. 12B, the first conductive layer 150 includes a power line 151 and a data line 152 extending along a second direction, a first connection block 1541, and a second connection block 1542. The first connection block 1541 connects an initialization signal line to a corresponding source region of the pixel driving circuit, and the second connection block 1542 connects a drain region of the compensation thin film transistor to the first electrode block CE1. The first electrode block CE1 can form a storage capacitor with the second electrode block CE2 and is used as a gate for driving the thin film transistor. Therefore, since the spacer block 1622B is connected to the main body portion 1622A via the connection portion 1622C and is not integrally formed with the main body portion 1622A, excessive overlap between the second conductive portion 1622 and the second connection block 1542 can be avoided, thereby reducing the load on the second connection block 1542, that is, the load on the drain of the compensation thin film transistor and the gate of the driving thin film transistor, and further improving the performance of the display substrate. However, the pixel driving circuit used in the display substrate is a 7T1C pixel driving circuit. Of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may use other appropriate pixel driving circuit structures.

[0101] For example, as shown in FIG. 12B, the orthographic projection of the offset portion 1621B on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate are installed at an interval, and the orthographic projection of the spacer block 1622B on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 are installed at an interval. For example, as shown in FIG. 12B, the display substrate may further include a protective layer 364 located between the first conductive layer 150 and the first planar layer 241. Of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may not be provided with a protective layer.

[0102] In some examples, as shown in FIGS. 11-14, the distance between the orthographic projection of the spacer block 1622B on the base substrate 110 and the orthographic projection of the main body 1622A on the base substrate 110 exceeds the width along the first direction of the orthographic projection of the spacer block 1622B on the base substrate 110. Thereby, the display substrate can further avoid excessive overlap between the second conductive part 1622 and the lower film layers such as the semiconductor layer, the gate layer, etc., thereby avoiding increasing the load on the film layers such as the semiconductor layer, the gate layer, etc. Thereby, the display substrate can increase the spacer block and ensure the normal operation of each sub-pixel.

[0103] In some examples, as shown in FIGS. 11-14, the second conductive part 1622 includes two connection parts 1622C. The two connection parts 1622C are respectively located at both ends in the second direction of the spacer block 1622B. The spacer block 1622B, the two connection parts 1622C and the main body 1622A surround one rectangular opening. Thereby, the display substrate can further avoid excessive overlap between the second conductive part 1622 and the lower film layers such as the semiconductor layer, the gate layer, etc., thereby avoiding increasing the load on the semiconductor layer, the gate layer, etc. Thereby, the display substrate can increase the spacer block and ensure the normal operation of each sub-pixel.

[0104] In some examples, the ratio of the width of the spacer block in the first direction to the width of the main body in the first direction is 1 / 2 or less, and the ratio of the width of the spacer block in the first direction to the distance from the main body to the spacer block is 1 / 2 or less.

[0105] In some examples, the ratio of the length of the spacer block in the second direction to the length of the effective light-emitting region of the first light-emitting element in the second direction is 7 / 8 or more.

[0106] In some examples, the included angle between the central connection line of the effective light-emitting region of the first light-emitting element and the spacer block and the first direction is less than 30 degrees. For example, the included angle between the central connection line of the effective light-emitting region of the first light-emitting element and the spacer block and the first direction is zero, that is, the central connection line of the effective light-emitting region of the first light-emitting element and the spacer block is parallel to the first direction.

[0107] In some examples, the orthographic projection of the spacer block on the base substrate and the orthographic projection of the first anode on the base substrate are arranged at an interval, and the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the first anode on the base substrate are arranged at an interval.

[0108] In some examples, the overlapping area between the orthographic projection of the spacer block on the base substrate and the orthographic projection of the first anode on the base substrate is substantially the same as the overlapping area between the orthographic projection of the first conductive part on the base substrate and the orthographic projection of the first anode on the base substrate. In some examples, as shown in FIGS. 11-14, the second conductive layer 160 further includes a third conductive part 1623 and a fourth conductive part 1624 extending along the second direction. The third conductive part 1623 is located between the anode pair 1755 and the fourth anode 1754, and the fourth conductive part 1624 overlaps with the fourth anode 1754.

[0109] In some examples, as shown in FIGS. 11-14, the distance between the orthographic projection of the main body part 1622A of the second conductive part 1622 on the base substrate 110 and the orthographic projection of the bisector along the second direction of the effective light-emitting region of the second light-emitting element 312 on the base substrate 110 is substantially the same as the distance between the orthographic projection of the third conductive part 162 on the base substrate 110 and the orthographic projection of the bisector along the second direction of the effective light-emitting region of the second light-emitting element 312 on the base substrate 110. Thereby, the symmetry between the second conductive part and the third conductive part on both sides of the anode pair of the display substrate can be improved, and thereby the flatness of the second anode and the third anode can be further improved.

[0110] In some examples, as shown in FIGS. 11-14, the fourth anode 1754 extends along the second direction, and the orthographic projection of the fourth conductive part 1624 on the base substrate 110 passes through the center of the orthographic projection of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110. Thereby, even when the fourth conductive part 162 overlaps with the fourth anode 1754, since the orthographic projection of the fourth conductive part 1624 on the base substrate 110 passes through the center of the orthographic projection of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110, the fourth conductive part can ensure a higher flatness of the fourth anode, thereby ensuring that the light-emitting intensities in different directions of the fourth anode are consistent, and further effectively improving the color bleeding phenomenon.

[0111] In some examples, as shown in FIGS. 11-14, the second conductive layer 160 further includes a fifth conductive part 1625 and a sixth conductive part 1626 that extend along the first direction. The fifth conductive part 1625 is respectively connected to the main body part 1622A and the third conductive part 1623, and is located between the second anode 1752 and the third anode 1753 of the anode pair 1755. The sixth conductive part 1626 is respectively connected to the third conductive part 1623 and the fourth conductive part 1624, and is located between the first anode 1751 and the fourth anode 1754 that are adjacent in the second direction. Thereby, the first conductive part 1621, the second conductive part 1622, the third conductive part 1623, the fourth conductive part 1624, the fifth conductive part 1625, and the sixth conductive part 1626 can form a net-like structure, thereby further reducing the resistance of the power line of the first conductive layer, and further improving the electrical performance of the display substrate.

[0112] In some examples, as shown in FIGS. 11-14, the second conductive layer 160 includes a first connection electrode 1611, a second connection electrode 1612, a third connection electrode 1613, and a fourth connection electrode 1614. The second flat layer 242 includes a first via 2421, a second via 2422, a third via 2423, and a fourth via 2424. The first anode 1751 is connected to the first connection electrode 1611 via the first via 2421. The second anode 1752 is connected to the second connection electrode 1612 via the second via 2422. The third anode 1753 is connected to the third connection electrode 1613 via the third via 2423. The fourth anode 1754 is connected to the fourth connection electrode 1614 via the fourth via 2424.

[0113] In some examples, as shown in FIGS. 11-14, the first flat layer 241 is located on a side closer to the base substrate 110 of the second conductive layer 160, and the first conductive layer 150 is located on a side closer to the base substrate 110 of the first flat layer 241. The first conductive layer 150 includes a first drain 1511, a second drain 1512, a third drain 1513, and a fourth drain 1514. The first flat layer 241 includes a fifth via 2415, a sixth via 2416, a seventh via 2417, and an eighth via 2418. The first connection electrode 1611 is connected to the first drain 1511 via the fifth via 2415. The second connection electrode 1612 is connected to the second drain 1512 via the sixth via 2416. The third connection electrode 1613 is connected to the third drain 1513 via the seventh via 2417. The fourth connection electrode 1614 is connected to the fourth drain 1514 via the eighth via 2418.

[0114] In some examples, as shown in FIGS. 11-14, the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654. The first drain 1511 is part of the first pixel driving circuit 2651, the second drain 1512 is part of the second pixel driving circuit 2652, the third drain 1513 is part of the third pixel driving circuit 2653, and the fourth drain 1514 is part of the fourth pixel driving circuit 2654. The first pixel driving circuit 2651 is connected to the first anode 1751 via the first connection electrode 1611 to apply a driving signal to the first anode 1751. The second pixel driving circuit 2652 is connected to the second anode 1752 via the second connection electrode 1612 to apply a driving signal to the second anode 1752. The third pixel driving circuit 2653 is connected to the third anode 1753 via the third connection electrode 1613 to apply a driving signal to the third anode 1753. The fourth pixel driving circuit 2654 is connected to the fourth anode 1754 via the fourth connection electrode 1614 to apply a driving signal to the fourth anode 1754.

[0115] For example, the thickness range of the second conductive layer may be 0.6 - 0.8 microns, for example 0.7 microns, and the thickness range of the second flat layer may be 1.3 - 1.7 microns, for example 1.5 microns.

[0116] FIG. 15 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. To clearly show the positional relationship between each conductive portion of the second conductive layer and the anode, only the second conductive layer and the anode layer are shown in FIG. 15. As shown in FIG. 15, no spacer block is installed on the second conductive portion 1622 of the second conductive layer 160. The first conductive portion 1621 of the second conductive layer 160 includes an extension portion 1621A and an offset portion 1621B. The orthographic projection of the effective light-emitting region of the first light-emitting element 311 on the first conductive portion 1621 is at the position of the offset portion 1621B. That is, the offset portion 1621B corresponds to the effective light-emitting region of the first light-emitting element 311. The orthographic projection of the offset portion 1621B on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 are installed at intervals. The extension portion 1621A is close to the first anode 1751 and the straight line where the edge extending along the second direction is the first straight line 302. The offset portion 1621B is installed at an interval from the first straight line 302 and is located on the side away from the anode pair 1755 of the first straight line 302.

[0117] In the display substrate provided by the embodiment of the present disclosure, the first conductive portion is located on the side away from the anode pair of the first anode, the second conductive portion is located between the first anode and the anode pair, and the orthographic projection of the offset portion on the base substrate and the orthographic projection of the first anode on the base substrate are installed at intervals. Therefore, the first conductive portion and the second conductive portion of the second conductive layer hardly affect the flatness of the first anode, thereby ensuring a higher flatness of the first anode. Thereby, it can be ensured that the light-emitting intensities in different directions of the first anode are consistent, and further, the color bleeding phenomenon can be effectively improved. In addition, since the offset portion and the first straight line are installed at intervals and the offset portion is located on the side away from the anode pair of the first straight line, the offset portion is offset in the direction away from the first anode, providing space for the installation of the first anode. Thereby, a close arrangement of the anodes can be realized while ensuring a higher flatness of the first anode.

[0118] For example, as shown in FIG. 15, the first anode 1751 may include a main body portion 1751A, a connection portion 1751B, and a supplementary portion 1751C. The effective light-emitting region of the first light-emitting element is in the main body portion 1751A. The connection portion 1751B connects the first anode 1751 to the corresponding pixel driving circuit. The supplementary portion 1751C covers the potentials at the gate G1 of the driving thin-film transistor T1 and the drain D3 of the compensation thin-film transistor T3 of the corresponding pixel driving circuit, thereby stabilizing the potentials at the gate G1 of the driving thin-film transistor T1 and the drain D3 of the compensation thin-film transistor T3, further enhancing the long-term light-emitting stability of the display substrate, and extending the service life.

[0119] For example, as shown in FIG. 15, the distance range between the first anode 1751 and the offset portion 1621B may be 2.5 - 3.2 microns, for example, 2.9 microns. The distance range between the main body portion 1751A of the first anode 1751 and the second conductive portion 1622 may be 9 - 11 microns, for example, 10.5 microns. The distance range between the connection portion 1751B of the first anode 1751 and the second conductive portion 1622 may be 5 - 7 microns. The supplementary portion 1751C of the first anode 1751 and the second conductive portion 1622 may partially overlap, and the width in the first direction of the overlapping portion is less than 1 micron, for example, 0.79 micron. Since the distance between the edge of the supplementary portion close to the second conductive portion and the main body portion is large, the supplementary portion 1751C partially overlaps with the second conductive portion 1622 and hardly affects the flatness of the first anode.

[0120] One embodiment of the present disclosure further provides a display device. FIG. 16 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 16, the display device 400 includes the display substrate 100 described in any of the above. Thereby, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can ensure the flatness of the first anode located in the effective light-emitting region of the first light-emitting element, thereby avoiding the occurrence of color mixing phenomenon, reducing the resistance between the fourth anode located in the effective light-emitting region of the fourth light-emitting element and the fourth connection electrode, and increasing the distance between the first anode and the fourth anode, thereby avoiding the short circuit between the first anode and the fourth anode caused by residues in the manufacturing process.

[0121] For example, the display device may be an electronic product having a display function such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigator, a digital photo frame, etc.

[0122] On the other hand, in the manufacturing process of an organic light-emitting diode display device, usually, the light-emitting layer is manufactured by a vapor deposition process. And, in order to prevent the fine metal mask (FMM) from touching and damaging the organic light-emitting diode display substrate during the vapor deposition process, usually, spacers need to be formed on the organic light-emitting diode display substrate, and the fine metal mask needs to be placed on the spacers. In this case, the spacers support the fine metal mask, thereby protecting the organic light-emitting diode display substrate.

[0123] However, through research, the inventors of the present application generally found that the spacer is located at the middle position of the straight side of the effective light-emitting region of the sub-pixel. When performing the deposition process with a fine metal mask, the opening edge of the fine metal mask is at the middle position of the spacer. Due to reasons such as the manufacturing process, the middle position of the spacer is usually the thickest position of the spacer (i.e., the top of the spacer). The opening edge of the fine metal mask just touches the top of the spacer, thereby easily damaging the spacer or generating foreign matters such as particles. FIG. 17 is a schematic diagram of the process of depositing with a fine metal mask. As shown in FIG. 17, the opening edge 252 of the fine metal mask 250 is located at the top of the spacer 220, easily damaging the top of the spacer 220 or generating foreign matters such as particles. After the deposition process, a film layer such as a package layer is formed on the display substrate. However, defects such as cracks in the package layer are likely to occur due to the generated foreign matters such as particles, thereby causing a decrease in the stability and reliability of the product.

[0124] In contrast, the embodiments of the present disclosure further provide a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a base substrate, a light-emitting layer, and a spacer. The light-emitting layer is located on the base substrate and includes a plurality of light-emitting portions. The spacer is located on one side away from the base substrate of the light-emitting layer. The orthographic projection of the top of the spacer on the base substrate and the edge of the orthographic projection of the light-emitting portion on the base substrate are installed at an interval. Thereby, when forming the above-mentioned light-emitting portion by performing a deposition process with a fine metal mask, the orthographic projection of the opening edge of the fine metal mask on the base substrate and the orthographic projection of the top of the spacer on the base substrate are installed at an interval, thereby avoiding the opening edge of the fine metal mask from contacting the top of the spacer, avoiding the generation of foreign matters such as particles, and further improving the yield rate of the display substrate.

[0125] Hereinafter, the display substrate, the manufacturing method thereof, and the display device provided by the embodiments of the present disclosure will be described in detail with reference to the drawings.

[0126] One embodiment of the present disclosure provides a display substrate. FIG. 18 is a schematic plan view of a display substrate according to an embodiment of the present disclosure, and FIG. 19 is a schematic cross-sectional view of the display substrate in the CC direction of FIG. 18 according to an embodiment of the present disclosure.

[0127] As shown in FIGS. 18 and 19, the display substrate 100 includes a base substrate 110, a light-emitting layer 180, and a spacer 220. The light-emitting layer 180 is located on the base substrate 110 and includes a plurality of light-emitting portions 185. The spacer 220 is located on one side of the base substrate 110 where the light-emitting layer 180 is located. There is a gap between the orthographic projection of the uppermost portion 225 of the spacer 220 on the base substrate 110 and the edge of the orthographic projection of the light-emitting portion 185 on the base substrate 110. Here, the uppermost portion of the spacer refers to the portion away from the base substrate of the spacer, that is, the portion with a large thickness. Also, the above-mentioned "installed with a gap" means that there is a predetermined gap between the orthographic projection of the uppermost portion of the spacer away from the base substrate on the base substrate and the orthographic projection of the light-emitting portion on the base substrate, and they do not overlap or contact each other.

[0128] In the manufacturing process of the display substrate provided by the embodiments of the present disclosure, when the light-emitting portion 185 is formed by performing a vapor deposition process with the fine metal mask 250, as shown in FIG. 19, the orthographic projection of the opening edge 252 of the fine metal mask 250 on the base substrate 110 and the orthographic projection of the top portion 225 of the spacer 220 on the base substrate 110 are installed at intervals, thereby avoiding the opening edge 252 of the fine metal mask 250 from contacting the top portion 225 of the spacer 220 and also avoiding the generation of foreign matters such as particles. For example, as shown in FIG. 11, the opening edge 252 of the fine metal mask 250 is located at the edge portion of the spacer 220, and since the thickness of the edge portion of the spacer 220 is less than the thickness of the top portion 225 of the spacer 220, the opening edge 252 of the fine metal mask 250 is in a suspended state and does not contact the spacer 220, thereby avoiding the generation of foreign matters such as particles caused by damage. Thereby, the display substrate can improve the stability, reliability, and product yield rate of the display substrate.

[0129] In some examples, as shown in FIG. 19, the size of the spacer 220 in the direction perpendicular to the base substrate 110 at the middle portion is larger than the size of the spacer 220 in the direction perpendicular to the base substrate 110 at the edge portion. That is, the thickness of the middle portion of the spacer 220 is larger than the thickness of the edge portion of the spacer 220. Thereby, when the orthographic projection of the opening edge of the fine metal mask on the base substrate and the orthographic projection of the middle portion (i.e., the top portion) of the spacer on the base substrate are installed at intervals, the opening edge of the fine metal mask is in a suspended state and does not contact the spacer, so that the generation of foreign matters such as particles caused by damage can be avoided.

[0130] For example, as shown in FIG. 19, the cross-sectional shape of the spacer 220 in a plane perpendicular to the base substrate 110 may include a semi-circular shape. Of course, the embodiments of the present disclosure are not limited thereto. For example, when the cross-sectional shape of the spacer 220 is semi-circular, the range of the inclination of the semi-circular shape is 8-10 degrees.

[0131] In some examples, as shown in FIG. 18, the shape of the orthographic projection of the spacer 220 on the base substrate 110 is rectangular, and the orthographic projection of the central axis line of the spacer 220 in the length direction on the base substrate 110 and the edge of the orthographic projection of the light emitting portion 185 on the base substrate 110 are arranged at an interval. Thereby, it is possible to avoid the opening edge of the fine metal mask from contacting the uppermost portion of the spacer, and to avoid the generation of foreign matters such as particles, thereby improving the stability, reliability and product yield of the display substrate. Of course, the shape of the orthographic projection of the spacer on the base substrate in the embodiment of the present disclosure includes the above rectangle, but is not limited thereto, and other shapes may be used.

[0132] In some examples, as shown in FIG. 18, the distance between the orthographic projection of the central axis line of the spacer 220 in the length direction on the base substrate 110 and the edge of the orthographic projection of the light emitting portion 185 on the base substrate 110 is greater than 6 microns. Thereby, it is possible to effectively avoid the opening edge of the fine metal mask from contacting the uppermost portion of the spacer, and to avoid the generation of foreign matters such as particles, thereby improving the stability, reliability and product yield of the display substrate.

[0133] FIG. 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure, and FIG. 21 is a schematic cross-sectional view of the display substrate in the DD direction of FIG. 20 according to an embodiment of the present disclosure. To clearly show the relationship between the spacer and the light-emitting portion, only the base substrate, the anode layer, the light-emitting layer, and the spacer are shown in FIG. 20. As shown in FIG. 20, the orthographic projection of the uppermost portion 225 of the spacer 220 on the base substrate 110 away from the base substrate 110 and the edge of the orthographic projection of the light-emitting portion 185 on the base substrate 110 are installed at intervals. As shown in FIG. 21, when the light-emitting portion is formed by performing a vapor deposition process with a fine metal mask, the opening edge 252 of the fine metal mask 250 is in a suspended state and does not contact the spacer 220. Therefore, the display substrate can avoid the opening edge of the fine metal mask from contacting the uppermost portion of the spacer, and can also avoid the generation of foreign matters such as particles, thereby further improving the stability, reliability, and product yield of the display substrate.

[0134] In some examples, as shown in FIG. 20, a plurality of light emitting units 185 form a plurality of light emitting group columns 280 by being arranged along a first direction, and form a plurality of light emitting group rows 290 by being arranged along a second direction. Each light emitting group 1850 includes one first light emitting unit 1851, one second light emitting unit 1852, one third light emitting unit 1853, and one fourth light emitting unit 1854. Two adjacent light emitting group rows 290 are arranged with a 1 / 2 pitch shift. The pitch is equal to the distance between the centers of the two first light emitting units 1851 of two adjacent light emitting groups 1850 in the first direction. The second light emitting unit 1852 and the third light emitting unit 1853 are arranged along the second direction to form a light emitting pair 1855. The first light emitting unit 1851, the light emitting pair 1855, and the fourth light emitting unit 1854 are arranged along the first direction. As shown in FIG. 20, the orthographic projection of the uppermost part 225 of the spacer 220 on the base substrate 110 is located between the orthographic projection of the first light emitting unit 1851 of one light emitting group 1850 on the base substrate 110, the orthographic projection of the third light emitting unit 1853 on the base substrate 110, and the orthographic projections of the second light emitting unit 1852 and the fourth light emitting unit 1854 of another adjacent light emitting group 1850 in the second direction on the base substrate 110. Thereby, it can be ensured that both the orthographic projection of the uppermost part 225 of the spacer 220 on the base substrate 110 and the orthographic projections of the first light emitting unit 1851, the second light emitting unit 1852, the third light emitting unit 1853, and the fourth light emitting unit 1854 on the base substrate 110 are installed at intervals, and the space on the display substrate can be fully utilized.

[0135] For example, the first direction and the second direction are substantially perpendicular. However, the fact that the first direction and the second direction are substantially perpendicular includes not only the case where the included angle between the first direction and the second direction is 90 degrees, but also the case where the range of the included angle between the first direction and the second direction is 85 - 95 degrees.

[0136] For example, as shown in FIG. 20, in the display substrate 100, the two light-emitting groups 1850 adjacent in the second direction may be the first light-emitting group 1850A and the second light-emitting group 1850B, and the orthographic projection of the uppermost part 225 of the spacer 220 on the base substrate 110 is the orthographic projection of the first light-emitting part 1851 of the first light-emitting group 1850A on the base substrate 110, the orthographic projection of the third light-emitting part 1853 of the first light-emitting group 1850A on the base substrate 110, the orthographic projection of the second light-emitting part 1852 of the second light-emitting group 1850B on the base substrate 110, and the orthographic projection of the fourth light-emitting part 1854 of the second light-emitting group 1850B on the base substrate 110. Thereby, it can be ensured that the orthographic projection of the uppermost part 225 of the spacer 220 on the base substrate 110 and the orthographic projections of the first light-emitting part 1851, the second light-emitting part 1852, the third light-emitting part 1853, and the fourth light-emitting part 1854 on the base substrate 110 are all installed at intervals, and the space on the display substrate can be fully utilized.

[0137] For example, the orthographic projection of the spacer 220 on the base substrate 110 may be a rectangle with a length of 20 microns and a width of 9.5 microns. In this case, the distance range between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the third anode 1753 of the first light-emitting group 1850A on the base substrate 110 may be 8.5 - 9.5 microns, for example, 8.9 microns, and the distance range between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the fourth anode 1754 of the second light-emitting group 1850B on the base substrate 110 may be 6 - 7 microns, for example, 6.3 microns.

[0138] For example, the distance range between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the third light-emitting part 1853 of the first light-emitting group 1850A on the base substrate 110 may be 0 microns, and they may even overlap each other. The distance range between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the second light-emitting part 1852 of the second light-emitting group 1850B on the base substrate 110 may be 0 microns, and they may even overlap each other.

[0139] In some examples, as shown in FIGS. 20 and 21, the display substrate 100 further includes an anode layer 170 and a pixel defining layer 190. The anode layer 170 is located between the base substrate 110 and the spacer 220, and the pixel defining layer 190 is located on a side of the anode layer 170 close to the spacer 220. The anode layer 170 includes a plurality of anodes 175, and the pixel defining layer 190 includes a plurality of openings 195 to expose the plurality of anodes 175. The plurality of anodes 175 are installed corresponding to the plurality of light emitting portions 185, the plurality of openings 195 are installed corresponding to the plurality of light emitting portions 185, and the plurality of openings 195 include a plurality of opening groups 1950. Each of the opening groups 1950 includes one first opening 1951, one second opening 1952, one third opening 1953, and one fourth opening 1954. The plurality of anodes 175 are installed corresponding to the plurality of light emitting portions 185, and the plurality of anodes 175 include a plurality of anode groups 1750. Each of the anode groups 1750 includes one first anode 1751, one second anode 1752, one third anode 1753, and one fourth anode 1754. The first light emitting portion 1851 covers at least partially the first anode 1751 located and exposed within the first opening 1951, the second light emitting portion 1852 covers at least partially the second anode 1752 located and exposed within the second opening 1952, the third light emitting portion 1853 covers at least partially the third anode 1753 located and exposed within the third opening 1953, and the fourth light emitting portion 1854 covers at least partially the fourth anode 1754 located and exposed within the fourth opening 1954.

[0140] For example, as shown in FIGS. 20 and 21, the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 may partially overlap.

[0141] For example, as shown in FIGS. 20 and 21, the first virtual straight line is parallel to the length direction of the spacer 220 and passes through the center of the spacer 220. The shape of the orthographic projection of the first opening 1951 on the base substrate 110 is substantially elliptical. The range of the ratio between the distance from the vertex in the major axis direction of the ellipse to the first virtual straight line and the shortest distance from the first opening 1951 to the first virtual straight line is 1.5 - 1.

[0142] For example, the distance range between the first opening 1951 and the second opening 1952 is 20 - 25 microns, the distance between the first opening 1951 and the third opening 1953 is also 20 - 25 microns, and the distance range between the first opening 1951 and the fourth opening 1954 is also 20 - 25 microns. Of course, the embodiments of the present disclosure are not limited thereto, and the distance between each opening may be determined according to the size of the actual product.

[0143] In some examples, as shown in FIGS. 20 and 21, the orthographic projection of the spacer 220 on the base substrate 110 and the spacer block of the first opening 1951 on the base substrate 110 are provided. Thereby, in the manufacturing process of the display substrate provided by the embodiments of the present disclosure, when forming the above light-emitting part by performing a vapor deposition process with a fine metal mask, the display substrate can avoid the opening edge of the fine metal mask contacting the top of the spacer, and can also avoid the generation of foreign matters such as particles.

[0144] For example, as shown in FIGS. 20 and 21, the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the first opening 1951 on the base substrate 110 are installed at intervals.

[0145] In some examples, as shown in FIGS. 20 and 21, the shape of the orthographic projection of the first opening 1951 on the base substrate 110 is substantially elliptical, the shape of the orthographic projection of the spacer 220 on the base substrate 110 is rectangular, and the range of the included angle between the major axis direction of the shape of the orthographic projection of the first opening 1951 on the base substrate 110 and the extending direction of the orthographic projection of the spacer 220 on the base substrate 110 is 20 - 70 degrees.

[0146] In some examples, as shown in FIGS. 20 and 21, the display substrate 100 is located on a side closer to the base substrate 110 of the anode layer 170 and further includes a pixel circuit layer 260 having a plurality of pixel driving circuits 265. The plurality of pixel driving circuits 265 are installed corresponding to the plurality of anodes 175, and each anode 175 is electrically connected to the corresponding pixel driving circuit 265. The first anode 1751 includes a main body portion 1751A and a connection portion 1751B connected to the main body portion 1751A. The orthographic projection of the first opening 1951 on the base substrate 110 is inside the orthographic projection of the main body portion 1751A on the base substrate 110, and the connection portion 1751B is electrically connected to the corresponding pixel driving circuit 265.

[0147] In some examples, as shown in FIGS. 20 and 21, the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the connection portion 1751B on the base substrate 110 at least partially overlap. Thereby, the display substrate can avoid the opening edge of the fine metal mask contacting the top of the spacer, and at the same time avoid the generation of foreign matters such as particles, and can fully utilize the space on the display substrate.

[0148] In some examples, as shown in FIGS. 20 and 21, the connection portion 1751B is located at a position close to the third anode 1753 of the same light-emitting group 1850 of the main body portion 1751A and the fourth anode 1754 of the light-emitting group 1850 adjacent in the second direction.

[0149] In some examples, the region defined by the first opening 1951 is the first effective light-emitting region of the first sub-pixel, the region defined by the second opening 1952 is the second effective light-emitting region of the second sub-pixel, the region defined by the third opening 1953 is the third effective light-emitting region of the third sub-pixel, and the region defined by the fourth opening 1954 is the fourth effective light-emitting region of the fourth sub-pixel. Thereby, the plurality of light-emitting groups, the plurality of opening groups, and the plurality of anode groups respectively correspond to the plurality of pixel structures.

[0150] In some examples, the first light-emitting part is configured to emit light of a first color, the second light-emitting part and the third light-emitting part are connected, and are configured to emit light of a second color, and the fourth light-emitting part is configured to emit light of a third color.

[0151] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is, the display substrate uses a pixel arrangement structure of GGRB.

[0152] FIG. 22 is a schematic cross-sectional view of a display substrate in the EE direction according to an embodiment of the present disclosure. As shown in FIG. 22, in the actual manufacturing process, the light-emitting parts 185 (for example, the first light-emitting layer 1851 and the fourth light-emitting layer 1854) formed by the fine metal mask diffuse to form thin diffusion parts (for example, diffusion parts 1851A and 1854A). As a result, the size of the finally obtained light-emitting layer 185 is larger than the size of the opening of the fine metal mask, and as a result, it overlaps with the spacer 220, and further adjacent light-emitting parts come into contact with or overlap each other. In this case, the above-mentioned light-emitting layer is a part where the thickness of the light-emitting layer is equal to or greater than the thickness of the diffusion part and does not include the diffusion part.

[0153] An embodiment of the present disclosure further provides a display device. FIG. 23 is a schematic view of a display device according to an embodiment of the present disclosure. As shown in FIG. 23, the display device 400 includes the display substrate 100 described in any of the above. Thereby, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can avoid the opening edge 252 of the fine metal mask contacting the top of the spacer during the manufacturing process, and can avoid the generation of foreign matters such as particles, thereby improving the stability, reliability and product yield rate of the display substrate.

[0154] For example, the display device may be an electronic product having a display function such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigator, a digital photo frame, etc.

[0155] One embodiment of the present disclosure further provides a method for manufacturing a display substrate. FIG. 24 is a method for manufacturing a display substrate according to an embodiment of the present disclosure. As shown in FIG. 24, the method for manufacturing the display substrate includes the following steps S101-S103.

[0156] Step S101: Form a pixel definition layer having a plurality of openings on a base substrate.

[0157] For example, the base substrate may be a quartz substrate, a glass substrate, a plastic substrate, etc., the pixel definition layer may be manufactured by a vapor deposition process, and the plurality of openings may be manufactured by an etching process. Of course, the embodiments of the present disclosure are not limited thereto.

[0158] Step S102: Form a spacer on a side of the pixel definition layer away from the base substrate.

[0159] For example, the spacer and the pixel definition layer can be formed together through a half-tone mask or a gray-tone mask by using the same film layer, thereby omitting the mask process and reducing costs. For example, first, form a layer structure for forming a pixel definition layer and a spacer on a base substrate, and then, using a half-tone mask or a gray-tone mask, form a first photoresist pattern having a completely retained portion, a partially retained portion, and a completely removed portion on a side of the layer structure away from the base substrate. Use the first photoresist pattern to perform etching (for example, a wet etching process) on the layer structure, remove the layer structure corresponding to the completely removed portion to form a plurality of openings in the pixel definition layer, and then perform an ashing process on the first photoresist pattern to remove the partially retained portion to form a second photoresist pattern. Use the second photoresist pattern to further etch the layer structure to form a spacer on the layer structure corresponding to the completely retained portion and form a pixel definition layer on the layer structure corresponding to the partially retained portion. Of course, the embodiments of the present disclosure are not limited thereto, and the spacer may be formed independently.

[0160] Step S103: Place a mask plate on one side away from the base substrate of the spacer, and use the mask plate as a mask to deposit a light-emitting material into a plurality of openings to form a light-emitting layer having a plurality of light-emitting portions. The mask plate is provided with a plurality of mask openings, and there is a gap between the orthographic projection of the uppermost base substrate away from the base substrate of the spacer and the edge of the orthographic projection of the opening of the mask on the base substrate.

[0161] In the manufacturing process of the display substrate provided by the embodiments of the present disclosure, when placing a mask plate on one side away from the base substrate of the spacer and using the mask plate as a mask to deposit a light-emitting material into a plurality of openings to form a light-emitting layer having a plurality of light-emitting portions, there is a gap between the orthographic projection of the opening edge of the mask plate on the base substrate and the orthographic projection of the uppermost base substrate of the spacer on the base substrate. Thereby, it is possible to avoid the opening edge of the mask plate from contacting the uppermost portion of the spacer, and it is possible to avoid the generation of foreign matters such as particles. Thereby, the manufacturing method of the display substrate can improve the stability, reliability, and product yield of the display substrate.

[0162] In some examples, the mask plate is a fine metal mask (FMM).

[0163] In some examples, the shape of the orthographic projection of the base substrate of the spacer is rectangular, and there is a gap between the orthographic projection of the central axis line in the length direction of the spacer on the base substrate and the edge of the orthographic projection of the light-emitting portion on the base substrate. Thereby, the manufacturing method of the display substrate can avoid the opening edge of the fine metal mask from contacting the uppermost portion of the spacer, and can avoid the generation of foreign matters such as particles, thereby improving the stability, reliability, and product yield of the display substrate.

[0164] In some examples, the orthographic projection of the spacer on the base substrate and the edge of the orthographic projection of the light-emitting part on the base substrate are arranged at intervals. Thereby, the display substrate can further avoid the opening edge of the fine metal mask from contacting the top of the spacer, and can avoid the generation of foreign matters such as particles, thereby further improving the stability, reliability and product yield of the display substrate.

[0165] FIGS. 25-27 are schematic plan views of a mask plate group according to an embodiment of the present disclosure. As shown in FIGS. 25-27, the mask plate group includes a first mask plate 510, a second mask plate 520, and a third mask plate 530. The first mask plate 510 includes a plurality of first mask openings 412 each for forming the first light-emitting part 1851. The second mask plate 520 includes a plurality of second mask openings 422 each for forming the second light-emitting part 1852 and the third light-emitting part 1853. That is, the second light-emitting part 1852 and the third light-emitting part 1853 are formed through the same mask opening. The third mask plate 530 includes a plurality of third mask openings 432 each for forming the fourth light-emitting part 1854.

[0166] For example, as shown in FIGS. 25-27, in the method for manufacturing the display substrate, in step S103, as shown in FIG. 25, a first mask plate 510 is placed on one side of the spacer 220 away from the base substrate 110, and a light-emitting material is deposited into a plurality of openings 1951 using the first mask plate 510 as a mask to form a plurality of first light-emitting portions 1851; a step of removing the first mask plate 510; as shown in FIG. 26, a second mask plate 520 is placed on one side of the spacer 220 away from the base substrate 110, and a light-emitting material is deposited into a plurality of openings 1951 and 1952 using the second mask plate 520 as a mask to form a plurality of second light-emitting portions 1852 and a plurality of third light-emitting portions 1853; a step of removing the second mask plate 520; as shown in FIG. 27, a third mask plate 530 is placed on one side of the spacer 220 away from the base substrate 110, and a light-emitting material is deposited into a plurality of openings 1954 using the third mask plate 530 as a mask to form a plurality of fourth light-emitting portions 1854.

[0167] For example, as shown in FIGS. 25-27, there is a gap between the orthographic projection on the uppermost base substrate 110 away from the base substrate 110 of the spacer 220 and the edge of the orthographic projection on the base substrate 110 of the first light-emitting portion 1851 or the fourth light-emitting portion 1854.

[0168] On the one hand, with the continuous development of organic light-emitting diode (OLED) display technology, the requirements for display effects are becoming increasingly high. Through research, the inventors of the present application have found that there are many factors affecting the display effect of an organic light-emitting diode display device. The load of the gate layer affects the charging time of the pixel driving circuit, and the charging time of the pixel driving circuit has a great impact on the display effect. Usually, the load of the gate layer mainly consists of the loads of the gate line and the reset signal line. On the other hand, the load of the data line (or source line) is directly related to the power of the IC. The greater the load of the data line, the higher the requirements for the IC driver, and thereby, the greater the power of the IC. Therefore, by controlling the load between the gate line and the reset signal line and the load on the data line, the display effect of the organic light-emitting diode display device can be improved, and the power of the organic light-emitting diode display device can be reduced.

[0169] In contrast, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a first gate layer, a second gate layer, and a first conductive layer. The first gate layer is located on the base substrate, the second gate layer is located on a side of the first gate layer away from the base substrate, the first conductive layer is located on a side of the second gate layer away from the base substrate. The first gate layer includes a reset signal line extending along a first direction and a first electrode block. The second gate layer includes a second electrode block to form a storage capacitor with the first electrode block. The first conductive layer includes a power line extending along a second direction. The reset signal line and the power line have a first overlapping region, and the second electrode block and the power line have a second overlapping region. The width of the power line located in the first overlapping region is less than the width of the power line located in the second overlapping region. The first direction and the second direction intersect. Thereby, by reducing the width of the power line in the first overlapping region where the reset signal line and the power line overlap, the display substrate can reduce the load of the reset signal line, thereby lengthening the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0170] Hereinafter, a display substrate and a display device provided according to an embodiment of the present disclosure will be described in detail with reference to the drawings.

[0171] An embodiment of the present disclosure provides a display substrate. FIG. 28A is a partial schematic view of another display substrate according to an embodiment of the present disclosure, FIG. 28B is a partial schematic view of another display substrate according to an embodiment of the present disclosure, and FIG. 29 is a schematic cross-sectional view of the display substrate in the FF direction of FIG. 28A according to an embodiment of the present disclosure. In order to clearly show the stacked structure of each film layer of the pixel driving circuit structure in the display substrate, the anode layer and the second conductive layer are omitted in FIG. 28B.

[0172] As shown in FIGS. 28A, 28B, and 29, the display substrate 100 includes a base substrate 110, a first gate layer 130, a second gate layer 140, and a first conductive layer 150. The first gate layer 130 is located on the base substrate 110, the second gate layer 140 is located on one side of the first gate layer 130 away from the base substrate 110, and the first conductive layer 150 is located on one side of the second gate layer 140 away from the base substrate 110. The first gate layer 130 includes a reset signal line 131 extending along a first direction and a first electrode block CE1. The second gate layer 140 includes a second electrode block CE2 configured to form a storage capacitor with the first electrode block CE1. The first conductive layer 150 includes a power line 151 extending along a second direction. The reset signal line 131 and the power line 151 have a first overlapping region 351, and the second electrode block CE2 and the power line 151 have a second overlapping region 352. The width of the power line 151 located in the first overlapping region 351 is less than the width of the power line 151 located in the second overlapping region 352. That is, the width of the power line 151 in the first overlapping region 351 is reduced. The first direction and the second direction intersect, for example, are perpendicular to each other. However, the width of the power line refers to the size of the power line in the first direction, and correspondingly, the length of the power line refers to the size of the power line in the second direction.

[0173] In the display substrate provided by the embodiments of the present disclosure, when the width of the power line in the first overlapping region where the reset signal line and the power line overlap is reduced, the overlapping area between the reset signal line and the power line can be reduced, thereby reducing the magnitude of the parasitic capacitance between the reset signal line and the power line. Thereby, when the width of the power line in the first overlapping region where the reset signal line and the power line overlap is reduced, the display substrate can reduce the load of the reset signal line, thereby lengthening the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0174] In some examples, the first conductive layer may be the first source / drain metal layer, and the display substrate may further include a second conductive layer, that is, a second source / drain metal layer. However, in order to clearly show the film layer structure on the display substrate, the second conductive layer (the second source / drain metal layer) is not shown in the display substrate shown in FIG. 28A. Of course, the embodiments of the present disclosure are not limited thereto, and the display substrate may be a single-layer source / drain metal layer display substrate without a second conductive layer.

[0175] In some examples, the width of the power line 151 located in the first overlapping region 351 is less than the average width of the power line 151.

[0176] In some examples, as shown in FIGS. 28A and 28B, the width of the power line 151 in the first overlapping region 351 is less than 5 / 7 of the maximum width of the power line 151. Thereby, the display substrate can effectively reduce the load of the reset signal line.

[0177] In some examples, as shown in FIG. 28B, the power line 151 includes a main body extension 151A and a reduction portion 151B. The width of the reduction portion 151B is less than the width of the main body extension 151A, and the orthographic projection of the reduction portion 151B on the base substrate 110 overlaps with the orthographic projection of the reset signal line 131 on the base substrate 110.

[0178] In some examples, as shown in FIGS. 28A and 28B, the first gate layer 130 further includes a gate line 132 extending along a first direction, and the gate line 132 and the power line 151 have a third overlapping region 353. The width of the power line 151 in the third overlapping region 353 is less than the width of the power line 151 located in the second overlapping region 352. That is, the width of the power line in the third overlapping region is also reduced. Thereby, by reducing the width of the power line in the second overlapping region where the gate line and the power line overlap, the display substrate can reduce the load of the gate line, thereby further lengthening the charging time of the pixel driving circuit, and further improving the display effect of the display substrate.

[0179] In some examples, the width of the power line 151 in the third overlapping region 353 is less than the average width of the power line 151.

[0180] In some examples, as shown in FIGS. 28A and 28B, the width of the power line 151 in the third overlapping region 353 is less than 5 / 7 of the maximum width of the power line 151. Thereby, the display substrate can effectively reduce the load of the reset signal line.

[0181] In some examples, as shown in FIG. 28B, the power line 151 includes a main body extension 151A and a reduction part 151B. The width of the reduction part 151B is less than the width of the main body extension 151A, and the orthographic projection of the reduction part 151B on the base substrate 110 overlaps with the orthographic projection of the gate line 132 on the base substrate 110.

[0182] In some examples, as shown in FIGS. 28A and 28B, the first conductive layer 150 further includes data lines 152 extending along a second direction. The data lines 152 and the reset signal lines 131 have a fourth overlapping region 354, and the width of the reset signal lines 131 in the fourth overlapping region 354 is less than the average width of the reset signal lines 131. In the display substrate, reducing the width of the reset signal lines in the fourth overlapping region can reduce the overlapping area between the reset signal lines and the data lines, thereby reducing the magnitude of the parasitic capacitance between the reset signal lines and the data lines. Thereby, by reducing the width of the reset signal lines in the fourth overlapping region, the display substrate can reduce the load of the data lines, thereby reducing the driving power and further reducing the power of the display substrate. However, the width of the reset signal lines refers to the size of the reset signal lines in the second direction, and correspondingly, the length of the reset signal lines refers to the size of the reset signal lines in the first direction.

[0183] In some examples, as shown in FIGS. 28A and 28B, the width of the reset signal lines 131 in the fourth overlapping region 354 is less than 3 / 4 of the maximum width of the reset signal lines 131. Thereby, the display substrate can effectively reduce the load of the data lines.

[0184] In some examples, as shown in FIGS. 28A and 28B, the display substrate 100 further includes a semiconductor layer 120 located on a side closer to the base substrate 110 of the first gate layer 130. The second gate layer 140 includes an initialization signal line 141 extending along the first direction. The data line 152 and the initialization signal line 141 have a fifth overlapping region 355, and the initialization signal line 141 and the semiconductor layer 120 have a sixth overlapping region 356. The width of the initialization signal line 141 located in the fifth overlapping region 355 is less than the width of the initialization signal line 141 located in the sixth overlapping region 356. In the display substrate, when the width of the initialization signal line in the fifth overlapping region is decreased, the overlapping area between the initialization signal line and the data line can be decreased, thereby decreasing the magnitude of the parasitic capacitance between the initialization signal line and the data line. Thereby, by decreasing the width of the initialization signal line in the fifth overlapping region, the display substrate can further reduce the load of the data line, thereby reducing the driving power and further reducing the power of the display substrate. However, the width of the initialization signal line is the size of the initialization signal line in the second direction, and correspondingly, the length of the initialization signal line is the size of the initialization signal line in the first direction.

[0185] In some examples, the width of the initialization signal line 141 located in the fourth overlapping region 354 is less than the average width of the initialization signal line 141.

[0186] For example, as shown in FIG. 28B, the orthographic projection of the reduced portion 151B overlapping the reset signal line 131 on the base substrate 110 also overlaps the orthographic projection of the initialization signal line 141 on the base substrate 110.

[0187] In some examples, as shown in FIG. 28B, the power line 151 includes a main body extension portion 151A and a reduced portion 151B. The width of the reduced portion 151B is less than the width of the main body extension portion 151A, and the orthographic projection of the reduced portion 151B on the base substrate 110 does not overlap the orthographic projection of the semiconductor layer 110 on the base substrate 110.

[0188] In some examples, as shown in FIG. 28B, the second gate layer 140 further includes a conductive block 143, the body extension 151A is connected to the conductive block 143, the orthographic projection of the base substrate 110 and the orthographic projection of the semiconductor layer 110 on the base substrate 110 partially overlap, and a reduced portion 151B and a connection portion 151C adjacent to the reduced portion 151B in the second direction are provided.

[0189] For example, as shown in FIG. 28B, the connection portion 151C may be located between two reduced portions 151B.

[0190] In some examples, as shown in FIGS. 28A and 28B, the width of the initialization signal line 141 in the fourth overlapping region 354 is less than 3 / 4 of the maximum width of the initialization signal line 151. Thereby, the display substrate can effectively reduce the load of the data line.

[0191] For example, the semiconductor layer 120 may use a silicon-based semiconductor material such as polycrystalline silicon. Of course, the embodiments of the present disclosure are not limited thereto, and the semiconductor layer may further use a semiconductor material.

[0192] FIGS. 30A - 30D are schematic plan views of a plurality of film layers of a display substrate according to an embodiment of the present disclosure, and FIG. 31 is an equivalent schematic diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure.

[0193] For example, as shown in FIG. 30A, the semiconductor layer 120 includes a first unit 121, a second unit 122, a third unit 123, a fourth unit 124, a fifth unit 125, a sixth unit 126, and a seventh unit 127. The first unit 121 includes a first channel region C1, a first source region S1 and a first drain region D1 located on both sides of the first channel region C1. The second unit 122 includes a second channel region C2, a second source region S2 and a second drain region D2 located on both sides of the second channel region C2. The third unit 123 includes a third channel region C3, a third source region S3 and a third drain region D3 located on both sides of the third channel region C3. The fourth unit 124 includes a fourth channel region C4, a fourth source region S4 and a fourth drain region D4 located on both sides of the fourth channel region C4. The fifth unit 125 includes a fifth channel region C5, a fifth source region S5 and a fifth drain region S5 located on both sides of the fifth channel region C5. The sixth unit 126 includes a sixth channel region C6, a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6. The seventh unit 127 includes a seventh channel region C7, a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region C7.

[0194] For example, as shown in FIGS. 30A and 31, the sixth drain region D6 is connected to the third drain region D3. The third source region S3, the first drain region D1 and the fifth source region S5 are connected to the first node N1. The first source region S1, the second drain region D2 and the fourth drain region D4 are connected to the second node N2. The fifth drain region D5 is connected to the seventh drain region D7.

[0195] For example, as shown in FIG. 30B, the first gate layer 130 includes a reset signal line 131 extending along a first direction, a gate line 132 extending along the first direction, a first electrode block CE1, and a transmission control line 133 extending along the first direction.

[0196] For example, as shown in FIG. 30C, the second gate layer 140 includes an initialization signal line 141 extending along a first direction, a second electrode block CE2, and a conductive block 143. For example, the conductive block 143 is connected to a power line, thereby reducing the resistance of the power line.

[0197] As shown in FIG. 31, the sixth source region S6 and the seventh source region S7 are connected to the initialization signal line 141, and the first electrode block CE1 and the second electrode block CE2 can form a storage capacitor Cst.

[0198] For example, as shown in FIG. 30D, the first conductive layer 150 includes a power line 151 and a data line 152 extending along a second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543. The first connection block 1541 connects the initialization signal line 141 to the sixth source region S6 and the seventh source region S7, the second connection block 1542 connects the third drain region D3 to the first electrode block CE1, and the third connection block 1543 is connected to the fifth drain region D5 and can be connected to the corresponding anode as a drain.

[0199] For example, as shown in FIG. 31, the second source region S2 is connected to the data line 152, and the fourth source region S4 is connected to the power line 151. Thereby, the first unit 121, the second unit 122, the third unit 123, the fourth unit 124, the fifth unit 125, the sixth unit 126, and the seventh unit 127 of the semiconductor layer 120 can form the reset signal line 131 and the gate line 132 and the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, the sixth thin film transistor T6, and the seventh thin film transistor T7.

[0200] The following schematically describes one operation mode of the pixel driving circuit shown in FIG. 31. First, when a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the remaining current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 via the seventh thin film transistor T7, thereby suppressing the light emission caused by the remaining current flowing through the anode of each sub-pixel. Then, when a reset signal is transmitted to the reset signal line 131 and an initialization signal is transmitted to the initialization signal line 141, the sixth thin film transistor T6 is turned on, and an initialization voltage Vint is applied to the first gate of the first thin film transistor T1 and the first electrode block CE1 of the storage capacitor Cst via the sixth thin film transistor T6, thereby initializing the first gate and the storage capacitor Cst. When the first gate is initialized, the first thin film transistor T1 can be turned on.

[0201] After that, when a gate signal is transmitted to the gate line 132 and a data signal is transmitted to the data line 152, both the second thin film transistor T2 and the third thin film transistor T3 are turned on, and a data voltage Vd is applied to the first gate via the second thin film transistor T2 and the third thin film transistor T3. In this case, the voltage applied to the first gate is the compensation voltage Vd + Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0202] After that, the power supply line 151 applies a driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst and a compensation voltage Vd + Vth to the first electrode block CE1, stores the charge corresponding to the difference in the voltages applied to the two electrodes of the storage capacitor Cst in the storage capacitor Cst, and the first thin film transistor T1 is conducting for a predetermined time.

[0203] Thereafter, when applying a transmission control signal to the transmission control line 133, both the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, and the fourth thin film transistor T4 applies a driving voltage Vel to the fifth thin film transistor T5. When the driving voltage Vel passes through the first thin film transistor T1 conducted by the storage capacitor Cst, a driving current Id flows through the first drain region D3 of the first thin film transistor T1 due to the difference between the corresponding driving voltage Vel and the voltage applied to the first gate through the storage capacitor Cst. The driving current Id is applied to each sub-pixel through the fifth thin film transistor T5, whereby the light emitting layer of each sub-pixel emits light.

[0204] In some examples, as shown in FIGS. 29 and 31, the display substrate 100 further includes a first flat layer 241, a second conductive layer 160, a second flat layer 242, and an anode 175. The first flat layer 241 is located on one side of the first conductive layer 150 away from the base substrate 110. The second conductive layer 160 is located on one side of the first flat layer 241 away from the first conductive layer 150 and includes a connection electrode 161. The second flat layer 242 is located on one side of the second conductive layer 160 away from the first flat layer 241. The anode 175 is located on one side of the second flat layer 242 away from the second conductive layer 160. The first flat layer 241 includes a first via H1, and the connection electrode 161 is connected to the fifth drain region S5 through the first via H1. The second flat layer 242 includes a second via H2, and the anode 175 is connected to the connection electrode 161 through the second via H2.

[0205] An embodiment of the present disclosure further provides a display device. FIG. 32 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 32, the display device 400 includes the display substrate 100 described in any of the above. Thereby, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can reduce the load of the gate layer, thereby lengthening the charging time of the pixel driving circuit and further improving the display effect of the display substrate.

[0206] For example, the display device may be an electronic product having a display function such as a television, a computer, a laptop computer, a tablet computer, a mobile phone, a navigator, a digital photo frame, or the like.

[0207] On the other hand, the long-term light emission stability of an organic light-emitting diode (OLED) display device is also an important specification or index of the organic light-emitting diode display device. Through research, the inventor of the present application found that there are many factors affecting the long-term light emission stability of the organic light-emitting diode display device. In addition to the service life of the light-emitting material itself, the operating state of the thin-film transistor in the pixel driving circuit also has a certain impact on both the light emission luminance and the long-term light emission stability.

[0208] In contrast, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a pixel circuit layer, and an anode layer. The pixel circuit layer is located on the base substrate and includes a plurality of pixel driving circuits. The anode layer is located on a side away from the base substrate of the pixel circuit layer and includes a plurality of anodes. The plurality of pixel driving circuits are installed in a one-to-one correspondence with the plurality of anodes, each including a functional thin-film transistor. The first pixel driving circuit and the second pixel driving circuit are installed adjacent to each other. The orthographic projection of the channel region of the functional thin-film transistor in the first pixel driving circuit and the orthographic projection of the channel region of the functional thin-film transistor in the second pixel driving circuit on the base substrate both overlap with the orthographic projection of the anode corresponding to the first pixel driving circuit on the base substrate. Thereby, the display substrate simultaneously shields the channel region of the functional thin-film transistor in the first pixel driving circuit and the channel region of the functional thin-film transistor in the second pixel driving circuit through the anode, thereby enhancing the stability of the functional thin-film transistor and extending its service life, and thereby enhancing the long-term light emission stability of the display substrate and extending its service life.

[0209] Hereinafter, the display substrate and the display device provided by the embodiments of the present disclosure will be described in detail with reference to the drawings.

[0210] One embodiment of the present disclosure provides a display substrate. FIG. 33 is a partial schematic diagram of a display substrate according to an embodiment of the present disclosure, FIG. 34 is a schematic cross-sectional view of the display substrate in the KK direction of FIG. 33 according to an embodiment of the present disclosure, FIG. 35A is a schematic cross-sectional view of the display substrate in the MM direction of FIG. 33 according to an embodiment of the present disclosure, FIG. 35B is a schematic cross-sectional view of the display substrate in the NN direction of FIG. 33 according to an embodiment of the present disclosure, and FIG. 35C is a schematic cross-sectional view of the display substrate in the QQ direction of FIG. 33 according to an embodiment of the present disclosure.

[0211] As shown in FIGS. 33 and 34, the display substrate 100 includes a base substrate 110, a pixel circuit layer 260, and an anode layer 170. The pixel circuit layer 260 is located on the base substrate 110 and includes a plurality of pixel driving circuits 265. The anode layer 170 is located on a side away from the base substrate 110 of the pixel circuit layer 260 and includes a plurality of anodes 175. The plurality of pixel driving circuits 265 are installed in a one-to-one correspondence with the plurality of anodes 175. Each pixel driving circuit 256 includes a functional thin film transistor such as a compensation thin film transistor T3. The plurality of pixel driving circuits 265 include a first pixel driving circuit 2657 and a second pixel driving circuit 2658 that are installed adjacent to each other. The orthographic projection of the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the orthographic projection of the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 both overlap with the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110. However, the "first" and "second" in the first pixel driving circuit and the second pixel driving circuit are only used to distinguish the two pixel driving circuits literally, and the specific structures of the two pixel driving circuits are the same. Also, the functional thin film transistor may be other thin film transistors in the pixel driving circuit.

[0212] In the display substrate provided by an embodiment of the present disclosure, since the orthographic projections of the channel regions of the compensation thin-film transistors T3 in the first pixel driving circuit 2657 and the channel regions of the compensation thin-film transistors T3 in the second pixel driving circuit 2658 on the base substrate 110 both overlap with the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110, the anode 175 corresponding to the first pixel driving circuit 2657 can partially or completely block the channel regions of the compensation thin-film transistors T3 in the first pixel driving circuit 2657 and the channel regions of the compensation thin-film transistors T3 in the second pixel driving circuit 2658. Thereby, the display substrate can enhance the stability of the compensation thin-film transistors T3 in the first pixel driving circuit and the compensation thin-film transistors T3 in the second pixel driving circuit 2658, extend the service life, thereby enhancing the long-term light-emitting stability of the display substrate and extending the service life. FIGS. 30A-30D are schematic plan views of a plurality of film layers of a display substrate according to an embodiment of the present disclosure, and FIG. 31 is an equivalent schematic diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure. The pixel driving circuit uses a 7T1C pixel driving structure. In the light-emitting stage, the voltage of the N3 node can control the on / off state of the first thin-film transistor T1 (i.e., the driving thin-film transistor), and the stability of the first thin-film transistor T1 directly affects the long-term light-emitting stability of the organic light-emitting diode display device. In the charging stage, the charging voltage of the N3 node is related to the states of the third thin-film transistor T3 (i.e., the compensation thin-film transistor), the first thin-film transistor T1, and the second thin-film transistor T2. Usually, thin-film transistors are particularly sensitive to light. When the thin-film transistors (especially the channel regions) are exposed to light, the characteristics of the thin-film transistors are likely to drift, affecting the normal operation of the pixel driving circuit. The embodiments of the present disclosure block the channel regions of the compensation thin-film transistors through the anode, enhance the stability of the compensation thin-film transistors, and can extend the service life, thereby enhancing the long-term light-emitting stability of the display substrate and extending the service life.

[0213] In some examples, as shown in FIGS. 33 to 35C, the channel regions of the compensation thin film transistors T3 in the first pixel driving circuit 2657 and the channel regions of the compensation thin film transistors T3 in the second pixel driving circuit 2658 are both in the orthographic projection on the base substrate 110 of the anode 175 corresponding to the first pixel driving circuit 2657 (i.e., the fourth anode 1754). The anode 175 corresponding to the first pixel driving circuit 2657 can completely shield the channel regions of the compensation thin film transistors T3 in the first pixel driving circuit 2657 and the channel regions of the compensation thin film transistors T3 in the second pixel driving circuit 2658, thereby further enhancing the stability of the compensation thin film transistors, extending the service life, further enhancing the long-term light emission stability of the display substrate, and extending the service life.

[0214] In some examples, as shown in FIG. 30A, the compensation thin film transistor T3 may be a thin film transistor with a double gate structure, thereby improving the reliability of the compensation thin film transistor. The channel region of the compensation thin film transistor T3 includes a first channel region C1 and a second channel region C2 that are spaced apart, and the compensation thin film transistor T3 further includes a common electrode SE located between the first channel region C1 and the second channel region C2. As shown in FIGS. 33 to 35B, the orthographic projections on the base substrate 110 of the common electrodes SE of the compensation thin film transistors T3 in the first pixel driving circuit 2657 and the common electrodes SE of the compensation thin film transistors T3 in the second pixel driving circuit 2658 both overlap with the orthographic projection on the base substrate 110 of the anode 175 corresponding to the first pixel driving circuit 2657. Thereby, the anode 175 corresponding to the first pixel driving circuit 2657 can partially or completely shield the common electrodes SE of the compensation thin film transistors T3 in the first pixel driving circuit 2657 and the common electrodes SE of the compensation thin film transistors T3 in the second pixel driving circuit 2658, thereby further enhancing the stability of the compensation thin film transistors, extending the service life, further enhancing the long-term light emission stability of the display substrate, and extending the service life.

[0215] FIG. 36 is a schematic plan view of another display substrate according to an embodiment of the present disclosure. As shown in FIG. 36, the plurality of anodes 175 includes a plurality of anode groups 1750, and each anode group 1750 includes one first anode 1751, one second anode 1752, one third anode 1753, and one fourth anode 1754. However, the first anode, the second anode, the third anode, and the fourth anode may be anodes of sub-pixels having different shapes and different colors. Of course, the embodiments of the present disclosure are not limited thereto, and at least two of the first anode, the second anode, the third anode, and the fourth anode may be anodes of sub-pixels having the same shape and the same color.

[0216] In some examples, as shown in FIG. 36, a plurality of anodes 175 form a plurality of anode group columns 380 by being arranged along a first direction, and a plurality of anode group rows 390 by being arranged along a second direction. Each anode group 1750 includes one first anode 1751, one second anode 1752, one third anode 1753, and one fourth anode 1754. Two adjacent anode group rows 390 are arranged with a 1 / 2 pitch shift, and the pitch is equal to the distance between the centers of the two first anodes 1751 of two adjacent anode groups 1750 in the first direction. The second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, and the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the second direction. Thereby, the display substrate provides a pixel arrangement structure, thereby improving the display effect of a display device using the display substrate. However, the anode group provided by the embodiments of the present disclosure includes, but is not limited to, the above pixel arrangement structure. Also, the center of the first anode is the center of the main body of the first anode, that is, the effective light-emitting region of the first light-emitting element corresponding to the first anode. For example, the first direction and the second direction are substantially perpendicular. However, the fact that the first direction and the second direction are substantially perpendicular includes not only the case where the included angle between the first direction and the second direction is 90 degrees, but also the case where the range of the included angle between the first direction and the second direction is 85-95 degrees.

[0217] In some examples, as shown in FIG. 33, the first pixel driving circuit 2657 and the second pixel driving circuit 2658 are installed along the first direction. The fourth anode 1754 in one anode group 1750 is installed corresponding to and electrically connected to the first pixel driving circuit 2657, and the second anode 1752 in another anode group 1750 is installed corresponding to and electrically connected to the second pixel driving circuit 2658.

[0218] In some examples, as shown in FIGS. 33, 34, and 36, the display substrate 100 further includes a pixel defining layer 190 that is located on a side away from the base substrate 110 of the anode layer 170 and includes a plurality of openings 195. The plurality of openings 195 include a plurality of opening groups 1950. Each of the opening groups 1950 includes one first opening 1951, one second opening 1952, one third opening 1953, and one fourth opening 1954. The first opening 1951 is installed corresponding to the first anode 1751 and exposes the first anode 1751. The second opening 1952 is installed corresponding to the second anode 1752 and exposes the second anode 1752. The third opening 1953 is installed corresponding to the third anode 1753 and exposes the third anode 1753. The fourth opening 1954 is installed corresponding to the fourth anode 1754 and exposes the fourth anode 1754.

[0219] As shown in FIGS. 33 and 36, the first anode 1751 includes a first main body portion 1751A and a first connection portion 1751B. The orthographic projection of the first opening 1951 on the base substrate 110 is inside the orthographic projection of the first main body portion 1751A on the base substrate 110. The first connection portion 1751B is connected to the pixel driving circuit 265 corresponding to the first anode 1751. The second anode 1752 includes a second main body portion 1752A and a second connection portion 1752B. The orthographic projection of the second opening 1952 on the base substrate 110 is inside the orthographic projection of the second main body portion 1752A on the base substrate 110. The second connection portion 1752B is connected to the pixel driving circuit 265 corresponding to the second anode 1752. The third anode 1753 includes a third main body portion 1753A and a third connection portion 1753B. The orthographic projection of the third opening 1953 on the base substrate 110 is inside the orthographic projection of the third main body portion 1753A on the base substrate 110. The third connection portion 1753B is connected to the pixel driving circuit 265 corresponding to the third anode 1753. The fourth anode 1754 includes a fourth main body portion 1754A and a fourth connection portion 1754B. The orthographic projection of the fourth opening 1954 on the base substrate 110 is inside the orthographic projection of the fourth main body portion 1754A on the base substrate 110. The fourth connection portion 1754B is connected to the pixel driving circuit 265 (for example, the first pixel driving circuit 2657) corresponding to the fourth anode 1754.

[0220] In some examples, as shown in FIGS. 33 and 36, the shape of the first main body portion 1751A is substantially the same as the shape of the first opening 1951, the shape of the second main body portion 1752A is substantially the same as the shape of the second opening 1952, the shape of the third main body portion 1753A is substantially the same as the shape of the third opening 1953, and the shape of the fourth main body portion 1754A is substantially the same as the shape of the fourth opening 1954. For example, when the shape of the fourth opening 1954 is hexagonal, the shape of the fourth main body portion 1754A is also hexagonal. Of course, the shapes of the fourth opening and the fourth main body portion are not limited to hexagonal, and may be other shapes such as an ellipse.

[0221] For example, as shown in FIGS. 33-36, the fourth anode 1754 further includes a first supplementary portion 1754C, and the orthographic projections of the first channel region C31 and the second channel region C32 of the compensation thin film transistor T3 in the first pixel driving circuit 2657 corresponding to the fourth anode 1754 on the base substrate 110 overlap with the orthographic projections of the first supplementary portion 1754C on the base substrate 110, respectively. On the display substrate, by increasing the first supplementary portion on the fourth anode, the two channel regions of the compensation thin film transistor in the pixel driving circuit corresponding to the fourth anode can be covered, thereby enhancing the stability of the compensation thin film transistor and extending its service life, and thereby enhancing the long-term light emission stability of the display substrate and extending its service life.

[0222] In some examples, as shown in FIGS. 33-36, the first supplementary portion 1754C protrudes from the fourth main body portion 1754A to the third anode 1753 and is located on the side of the fourth connection portion 1754B close to the fourth main body portion 1754A. In some examples, as shown in FIGS. 33-36, the first supplementary portion 1754C is connected to both the fourth main body portion 1754A and the fourth connection portion 1754B. Thereby, the display substrate makes full use of the area on the display substrate to closely arrange the first anode, the second anode, the third anode, and the fourth anode, thereby ensuring the resolution of the display substrate.

[0223] For example, as shown in FIG. 35A, the orthographic projection of the first supplementary portion 1754C on the base substrate 110 partially overlaps with the orthographic projection of the common electrode SE of the compensation thin film transistor T3 on the base substrate 110.

[0224] For example, as shown in FIG. 35A, the orthographic projection of the first supplementary portion 1754C on the base substrate 110 covers the orthographic projection of the second channel region C32 of the compensation thin film transistor T3 on the base substrate 110.

[0225] For example, as shown in FIG. 35A, the orthographic projection of the fourth main body portion 1754A on the base substrate 110 covers the drain region D3 of the compensation thin film transistor T3. For example, as shown in FIG. 35C, the first conductive layer 150 includes a second connection block 1542 for connecting the drain region of the compensation thin film transistor to the first electrode block CE1. The first electrode block CE1 can form a storage capacitor with the second electrode block CE2 and can be used as the gate of the driving thin film transistor at the same time. The connection portion 1752B of the second anode 1752 extends in a direction away from the third anode 1753 and overlaps with the second connection block 1542, and further covers the second connection block 1542. Therefore, the connection portion 1752 can stabilize the potential on the gate of the driving thin film transistor and the drain of the compensation thin film transistor, thereby further improving the long-term light emission stability of the display substrate and extending the service life.

[0226] FIG. 37A is a partial schematic view of another display substrate according to an embodiment of the present disclosure, and FIG. 37B is a partial schematic view of another display substrate according to an embodiment of the present disclosure. In order to clearly show the shape of each anode, only the anode layer is shown in FIG. 37B.

[0227] As shown in FIGS. 37A and 37B, the fourth anode 1754 further includes a second supplementary portion 1754D, and the orthographic projection of the second channel region C2 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 overlaps with the orthographic projection of the second supplementary portion 1754D on the base substrate 110. By adding the second supplementary portion to the fourth anode, the fourth anode can partially and more completely cover the second channel region C2 of the compensation thin film transistor T3 in the second pixel driving circuit 2658, thereby improving the stability of the compensation thin film transistor and extending the service life, thereby improving the long-term light emission stability of the display substrate and extending the service life.

[0228] In some examples, as shown in FIGS. 37A and 37B, the second supplementary portion 1754D protrudes from the fourth main body portion 1754A in the first direction to the first anode 1751 within the anode group 1750 adjacent thereto.

[0229] However, as shown in FIGS. 37A and 37B, the orthographic projection of the first channel region C1 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 is inside the orthographic projection of the fourth main body portion 1754A on the base substrate 110.

[0230] In some examples, as shown in FIGS. 37A and 37B, the orthographic projection of the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 on the base substrate 110 overlaps with the orthographic projection of the first supplementary portion 1754C on the base substrate 110, and the orthographic projection of the common electrode SE of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 overlaps with the orthographic projection of the fourth main body portion 1754A of the fourth anode 1754 corresponding to the first pixel driving circuit 2657 on the base substrate 110.

[0231] In some examples, as shown in FIGS. 37A and 37B, the orthographic projection of the channel region of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 on the base substrate 110 is inside the orthographic projection of the first main body portion 1751A on the base substrate 110.

[0232] In some examples, as shown in FIG. 31, the pixel driving circuit 265 further includes a driving thin film transistor T1 whose gate G1 is connected to the drain D3 of the compensation thin film transistor T3. As shown in FIG. 37A, the first anode 1751 further includes a third supplementary portion 1751C, which protrudes from the first main body portion 1751A to the third anode 1753, and the orthographic projection on the base substrate 110 of the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 is inside the orthographic projection on the base substrate 110 of the third supplementary portion 1751C. Thereby, the display substrate stabilizes the potentials at the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3 through the third supplementary portion 1751C, thereby further enhancing the long-term light emission stability of the display substrate and extending the service life.

[0233] In some examples, as shown in FIGS. 37A and 37B, the orthographic projection on the base substrate 110 of the first channel region C31 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 is inside the orthographic projection on the base substrate 110 of the third main body portion 1753A.

[0234] In some examples, as shown in FIGS. 37A and 37B, the third anode 1753 further includes a fourth supplementary portion 1753C, and the orthographic projection on the base substrate 110 of the second channel region C32 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 is inside the orthographic projection on the base substrate 110 of the fourth supplementary portion 1753C. Thereby, the main body portion of the third anode and the fourth supplementary portion partially or completely block the first channel region C31 and the second channel region C32 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753, thereby enhancing the stability of the compensation thin film transistor and extending the service life, and thereby enhancing the long-term light emission stability of the display substrate and extending the service life.

[0235] In some examples, as shown in FIGS. 33 and 34, the pixel circuit layer 260 further includes a semiconductor layer 120, a first gate layer 130, a second gate layer 140, and a first conductive layer 150. The first gate layer 130 is located on a side away from the base substrate 110 of the semiconductor layer 120. The second gate layer 140 is located on a side away from the base substrate 110 of the first gate layer 130. The first conductive layer 150 is located on a side away from the base substrate 110 of the second gate layer 140.

[0236] For example, as shown in FIG. 30A, the semiconductor layer 120 includes a plurality of pixel driving units 1200, which are installed corresponding to a plurality of anodes 175. Each pixel driving unit 1200 includes a first unit 121, a second unit 122, a third unit 123, a fourth unit 124, a fifth unit 125, a sixth unit 126, and a seventh unit 127. The first unit 121 includes a first channel region C1, a first source region S1 and a first drain region D1 located on both sides of the first channel region C1. The second unit 122 includes a second channel region C2, a second source region S2 and a second drain region D2 located on both sides of the second channel region C2. The third unit 123 includes a third channel region C3, a third source region S3 and a third drain region D3 located on both sides of the third channel region C3. The fourth unit 124 includes a fourth channel region C4, a fourth source region S4 and a fourth drain region D4 located on both sides of the fourth channel region C4. The fifth unit 125 includes a fifth channel region C5, a fifth source region S5 and a fifth drain region S5 located on both sides of the fifth channel region C5. The sixth unit 126 includes a sixth channel region C6, a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6. The seventh unit 127 includes a seventh channel region C7, a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region C7.

[0237] For example, as shown in FIGS. 30A and 31, the sixth drain region D6 is connected to the third drain region D3, the third source region S3, the first drain region D1, and the fifth source region S5 are connected to the first node N1, the first source region S1, the second drain region D2, and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 is connected to the seventh drain region D7.

[0238] For example, as shown in FIG. 30B, the first gate layer 130 includes a reset signal line 131 extending along a first direction, a gate line 132 extending along the first direction, a first electrode block CE1, and a transmission control line 133 extending along the first direction. The reset signal line 131 overlaps with the seventh channel region C7 and the sixth channel region C6, forms the seventh unit 127 and the sixth unit 126, and the seventh thin film transistor T7 and the sixth thin film transistor T6. The gate line 132 overlaps with the third channel region C3 and the second channel region C2 respectively, forms the third unit 123 and the second unit 122, and the third thin film transistor T3 and the second thin film transistor T2. The first electrode block CE1 overlaps with the first channel region C1, forms the first unit 121 and the first thin film transistor T1. The transmission control line 133 overlaps with the fourth channel region C4 and the fifth channel region C5, forms the fourth unit 124 and the fifth unit 125, and the fourth thin film transistor T4 and the fifth thin film transistor T5. Therefore, the third thin film transistor T3 is a compensation thin film transistor.

[0239] For example, as shown in FIG. 30B, the reset signal line 131, the gate line 132, and the transmission control line 133 all extend along the first direction, and the reset signal line 131, the gate line 132, the first electrode block CE1, and the transmission control line 133 are arranged along a second direction.

[0240] For example, as shown in FIG. 30C, the second gate layer 140 includes an initialization signal line 141 extending along a first direction, a second electrode block CE2, and a conductive block 143. For example, the conductive block 143 is connected to a power supply line, thereby reducing the resistance of the power supply line. Further, the initialization signal line 141 is connected to a seventh source region S7 and a first source region S1, and an orthographic projection of the second electrode block CE2 on the base substrate 110 and an orthographic projection of the first electrode block CE1 on the base substrate 110 at least partially overlap to form a storage capacitor Cst. However, the conductive block can also perform a predetermined light shielding role, and only a part of the leftmost conductive block in FIG. 33 is shown, and the shape of the leftmost conductive block in FIG. 33 is the same as the shapes of the other conductive blocks.

[0241] For example, as shown in FIG. 30D, the first conductive layer 150 includes a power supply line 151 and a data line 152 extending along a second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543. The data line 152 is connected to a second source region S2, the fourth source region S4 is connected to the power supply line 151, the first connection block 1541 connects the initialization signal line 141 to a sixth source region S6 and a seventh source region S7, the second connection block 1542 connects a third drain region D3 to the first electrode block CE1, the third connection block 1543 is connected to a fifth drain region D5, and can be connected to a corresponding anode as a drain.

[0242] The following schematically describes one operation mode of the pixel driving circuit shown in FIG. 31. First, when a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the remaining current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 via the seventh thin film transistor T7, thereby suppressing the light emission caused by the remaining current flowing through the anode of each sub-pixel. Then, when a reset signal is transmitted to the reset signal line 131 and an initialization signal is transmitted to the initialization signal line 141, the sixth thin film transistor T6 is turned on, and an initialization voltage Vint is applied to the first gate of the first thin film transistor T1 and the first electrode block CE1 of the storage capacitor Cst via the sixth thin film transistor T6, thereby initializing the first gate and the storage capacitor Cst. When the first gate is initialized, the first thin film transistor T1 can be turned on.

[0243] After that, when a gate signal is transmitted to the gate line 132 and a data signal is transmitted to the data line 152, both the second thin film transistor T2 and the third thin film transistor T3 are turned on, and a data voltage Vd is applied to the first gate via the second thin film transistor T2 and the third thin film transistor T3. In this case, the voltage applied to the first gate is the compensation voltage Vd + Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0244] Thereafter, the power supply line 151 applies a driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst and a compensation voltage Vd + Vth to the first electrode block CE1, stores the charge corresponding to the difference in the voltages applied to the two electrodes of the storage capacitor Cst in the storage capacitor Cst, and the first thin film transistor T1 conducts for a predetermined time.

[0245] Thereafter, when a transmission control signal is applied to the transmission control line 133, both the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, and the fourth thin film transistor T4 is made to apply a driving voltage Vel to the fifth thin film transistor T5. When the driving voltage Vel passes through the first thin film transistor T1 turned on by the storage capacitor Cst, a driving current Id flows through the first drain region D3 of the first thin film transistor T1 due to the difference between the corresponding driving voltage Vel and the voltage applied to the first gate via the storage capacitor Cst. The driving current Id is applied to each sub-pixel via the fifth thin film transistor T5, whereby the light-emitting layer of each sub-pixel emits light.

[0246] In some examples, as shown in FIGS. 33 and 34, the display substrate 100 further includes a first flat layer 241, a second conductive layer 160, a second flat layer 242, and an anode 175. The first flat layer 241 is located on a side of the first conductive layer 150 away from the base substrate 110. The second conductive layer 160 is located on a side of the first flat layer 241 away from the first conductive layer 150 and includes a connection electrode 161. The second flat layer 242 is located on a side of the second conductive layer 160 away from the first flat layer 241. The anode 175 is located on a side of the second flat layer 242 away from the second conductive layer 160. The first flat layer 241 includes a first via H1, and the connection electrode 161 is connected to the sixth drain region S6 through the first via H1. The second flat layer 242 includes a second via H2, and the anode 175 is connected to the connection electrode 161 through the second via H2.

[0247] In some examples, as shown in FIGS. 33, 34, and 36, the display substrate 100 further includes a light-emitting layer 180 located on a side away from the base substrate 110 of the anode layer 170 and including a plurality of light-emitting portions 185. The plurality of light-emitting portions 185 include a plurality of light-emitting groups 1850. Each light-emitting group 1850 includes one first light-emitting portion 1851, one second light-emitting portion 1852, one third light-emitting portion 1853, and one fourth light-emitting portion 1854. The first light-emitting portion 1851 at least partially covers the first anode 1751 located in and exposed from the first opening 1951. The second light-emitting portion 1852 at least partially covers the second anode 1752 located in and exposed from the second opening 1952. The third light-emitting portion 1753 at least partially covers the third anode 1753 located in and exposed from the third opening 1953. The fourth light-emitting portion 1854 at least partially covers the fourth anode 1754 located in and exposed from the fourth opening 1954. The first light-emitting portion 1851 is configured to emit light of a first color. The second light-emitting portion 1852 and the third light-emitting portion 1853 are configured to emit light of a second color. The fourth light-emitting portion 1854 is configured to emit light of a third color.

[0248] For example, the first color is red (R), the second color is green (G), and the third color is blue (B). That is, the display substrate uses a GGRB pixel arrangement structure.

[0249] For example, as shown in FIG. 34, the overlapping area between the first conductive portion 1621 located on a side away from the second anode 1752 of the first anode 1751 and the power line 151 in the first conductive layer 150 is less than the overlapping area between the second conductive portion 1622 located on a side closer to the second anode 1752 of the first anode 1751 and the power line 151 in the first conductive layer 150.

[0250] One embodiment of the present disclosure further provides a display device. FIG. 38 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 38, the display device 400 includes the display substrate 100 described above. Thereby, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can enhance the stability of the compensation thin film transistor and extend its service life, thereby enhancing the long-term light emission stability of the display substrate and extending its service life.

[0251] For example, the display device may be an electronic product having a display function, such as a television, a computer, a notebook computer, a tablet computer, a mobile phone, a navigator, a digital photo frame, etc.

[0252] One embodiment of the present disclosure further provides a display substrate. FIG. 39 is a schematic diagram of a display substrate according to an embodiment of the present disclosure, FIG. 40 is a schematic cross-sectional view of the display substrate along the TT line of FIG. 39 according to an embodiment of the present disclosure, and FIG. 41 is a schematic diagram of a second conductive layer and an anode layer of the display substrate according to an embodiment of the present disclosure.

[0253] As shown in FIGS. 39-41, the display substrate includes a base substrate 110, a pixel circuit layer 610, a first conductive layer 150, a first planarization layer 241, a second conductive layer 160, a second planarization layer 242, and a plurality of light-emitting element groups 310. The pixel circuit layer 610 includes a plurality of pixel driving circuits 265 having a semiconductor layer 120. The first conductive layer 150 is located on a side of the semiconductor layer 120 away from the base substrate 110. The first planarization layer 241 is located on a side of the first conductive layer 150 away from the semiconductor layer 120. The second conductive layer 160 is located on a side of the first planarization layer 241 away from the first conductive layer 150. The second planarization layer 242 is located on a side of the second conductive layer 162 away from the base substrate 110. The plurality of light-emitting element groups 310 are located on a side of the second planarization layer 242 away from the second conductive layer 162. The second conductive layer 160 includes a plurality of conductive portions 162 arranged along a first direction, and the size of each conductive portion 162 in a second direction intersecting the first direction is larger than the size in the first direction. The plurality of conductive portions 162 include a first conductive portion 1622 including a sealed annular portion 1622E having a hollow region 1622H.

[0254] As shown in FIGS. 39-41, each light-emitting element group 310 includes a first light-emitting element 311 having a first anode 1751 whose orthographic projection on the base substrate 110 overlaps with the orthographic projection of the sealed annular portion 1622E on the base substrate 110. The plurality of conductive portions 162 further include a second conductive portion 1621 adjacent to the first conductive portion 1622 and whose orthographic projection on the base substrate 110 overlaps with the orthographic projection of the first anode 1751 on the base substrate 110.

[0255] In the display substrate provided by the embodiments of the present disclosure, when the sealed annular portion 1622E is provided, the first anode 1751 can overlap with the sealed annular portion 1622E and the second conductive portion 1621 at the same time, thereby maintaining the flatness of the first anode 1751 and avoiding the occurrence of color shading due to inclination. In addition, since the sealed annular portion 1622E has a hollow design, the light transmittance of the display substrate can be improved, which is advantageous for the screen fingerprint recognition device to receive signals.

[0256] In some examples, as shown in FIGS. 39 - 41, the sealed annular portion 1622E is separated from at least one conductive portion 162 adjacent in the first direction and the second conductive layer 160, and the size in the first direction is at least larger than the size in the first direction of at least a part of the first conductive portion 1622. The plurality of pixel driving circuits 265 include a first pixel driving circuit 2651 having a semiconductor pattern in the semiconductor layer 120. The orthographic projection of the first conductive portion 1622 on the base substrate 110 overlaps with the orthographic projection of the semiconductor pattern of the first pixel driving circuit 2651 on the base substrate 110. The first pixel driving circuit 2651 includes a driving transistor T1. The first conductive layer 150 includes a first conductive pattern 1542 having the same potential as the gate of the driving transistor T3 and constituting a gate potential metal together with the gate of the driving transistor T1. The orthographic projection of the hollow region 1622H inside the sealed annular portion 1622E on the base substrate 110 overlaps with the orthographic projection of the gate potential metal on the base substrate.

[0257] In the display substrate provided by the embodiments of the present disclosure, on the one hand, the sealed annular portion 1622E can ensure a higher flatness of the first anode 1751, thereby ensuring that the light emission intensities of the first anode 1751 in different directions are consistent, and further effectively improving the color bleeding phenomenon. On the other hand, since the orthographic projection of the hollow region 1622H inside the sealed annular portion 1622E on the base substrate 110 overlaps with the orthographic projection of the gate potential metal on the base substrate, the reset speed and charging speed of the gate of the driving transistor can be improved.

[0258] In some examples, as shown in FIGS. 39 - 41, the inside of the sealed annular portion 1622E is provided with a hollow region 1622H. The first conductive portion 1622 has a plurality of hollow regions 1622H arranged along the second direction, and the shapes and sizes of two adjacent hollow regions 1622H are substantially the same. Since the first conductive portion 1622 may correspond to a plurality of first anodes 1751, it has a plurality of hollow regions 1622H.

[0259] In some examples, as shown in FIGS. 39-41, the first light-emitting element 311 includes an effective light-emitting region, and the orthographic projection of the straight base substrate 110 passing through the center of the effective light-emitting region of the first light-emitting element 311 and extending along the second direction is located between the orthographic projections of the first conductive portion 1622 and the second conductive portion 1621 on the base substrate 110.

[0260] In some examples, as shown in FIGS. 39-41, the two edges of the sealed annular portion 1622E in the first direction overlap with the orthographic projections of the anodes of a plurality of light-emitting elements in the light-emitting element group respectively, and the hollow region 1622H of the sealed annular portion 1622E is separated from the orthographic projection of the effective light-emitting regions of the plurality of light-emitting elements on the base substrate 110 (that is, they are installed at intervals). Thereby, on the one hand, the display substrate can make full use of the space on the display substrate, and on the other hand, the adverse effects of the light-emitting elements on the display can be avoided.

[0261] In some examples, as shown in FIGS. 39-41, the first conductive layer 150 further includes a conductive metal 152 configured to supply power to the pixel driving circuit 265, the first flat layer 241 includes a conductive metal via 241S, and the conductive portion 162 is electrically connected to the conductive metal 152 through the power line via 241S. The first pixel driving circuit 2651 further includes a first light-emitting control transistor T4 and a storage capacitor Cst. The storage capacitor includes a first electrode block CE1 and a second electrode block CE2 located on one side away from the base substrate 110 of the first electrode block CE1. The conductive metal 152 is electrically connected to the source of the first light-emitting control transistor T4 and the second electrode block CE2 respectively. Thereby, the display substrate can reduce the resistance of the conductive metal through the plurality of conductive portions of the second conductive layer, reduce the voltage drop, and improve the uniformity of the entire display panel.

[0262] In some examples, as shown in FIGS. 39 - 41, the orthographic projection of the sealed annular portion 1622E on the base substrate 110 overlaps with the orthographic projection of the first electrode block CE1 on the base substrate 110. The second electrode block CE2 is provided with an opening 620 whose orthographic projection on the base substrate 110 overlaps with the orthographic projection of the first electrode block CE1 on the base substrate 110. The orthographic projection of the sealed annular portion 1622E on the base substrate 110 also overlaps with the orthographic projection of the opening 620 on the base substrate 110. Thereby, by shielding the electrodes of the capacitor, it is possible to avoid the capacitor being excessively exposed to light, stabilize the potential of the capacitor, and play a role in increasing the charge and discharge speed.

[0263] In some examples, as shown in FIGS. 39 - 41, the first pixel driving circuit 2651 further includes a data writing transistor T2, a compensation transistor T3, a reset transistor T6, an anode initialization transistor T7, and a second light emission control transistor T5. The display substrate further includes a reset signal line 131 connected to the gates of the reset transistor T6 and the anode initialization transistor T7 respectively, a gate line 132 connected to the gates of the compensation transistor T3 and the data writing transistor T2 respectively, a light emission control line 133 connected to the gates of the first light emission control transistor T4 and the second light emission control transistor T5 respectively, and an initialization signal line 141 connected to the sources of the reset transistor T6 and the anode initialization transistor T7 respectively. The orthographic projection of the sealed annular portion 1622E on the base substrate 110 overlaps with the orthographic projections of the reset signal line 131, the gate line 132, and the initialization signal line 133 on the base substrate 110 respectively. Since the sealed annular portion is hollow, the overlapping area with the reset signal line 131, the gate line 132, and the initialization signal line 133 is relatively small, and interference with the potentials of these signal lines can be avoided. However, for the schematic diagram of the layered structure of the above pixel driving circuit and the connection relationship of each transistor, reference can be made to the relevant descriptions in FIGS. 30A - 30D and FIG. 31.

[0264] In some examples, as shown in FIGS. 39 - 41, one end of the first conductive pattern 1542 is electrically connected to the gate of the driving transistor T1 through the opening 620, and the other end of the first conductive pattern 1542 is electrically connected to the drain or source of the compensation transistor T3. Thereby, the first conductive pattern 1542 has the same potential as the gate of the driving transistor T1.

[0265] In some examples, as shown in FIGS. 39 - 41, the sealed annular portion 1622E includes a first portion 631 and a second portion 632 arranged along a first direction, and a third portion 633 and a fourth portion 634 arranged along a second direction. The first portion 631, the third portion 633, the second portion 632, and the fourth portion 634 form the sealed annular portion 1622E end - to - end, and the orthographic projection of the first portion 631 and the second portion 632 on the base substrate 110 overlaps with the orthographic projection of the second electrode block CE2 on the base substrate 110. Thereby, the capacitance of the storage capacitor Cst can be increased.

[0266] For example, the orthographic projection of the third portion 633 on the base substrate 110 overlaps with the orthographic projection of the second electrode block CE2 on the base substrate 110, thereby further increasing the capacitance of the storage capacitor Cst.

[0267] In some examples, as shown in FIGS. 39 - 41, the orthographic projection of the first portion 631 on the base substrate 110 overlaps with the orthographic projection of the first conductive pattern 1542 on the base substrate 110. Both the first conductive pattern 1542 and the shape of the first conductive pattern 1542 are elongated, and the extending direction of the long side of the first conductive pattern 1542 is the same as the extending direction of the long side of the first portion 631. By making the extending directions of the first portion and the first conductive pattern the same, the overlapping area between the two can be made as small as possible, thereby reducing the load on the gate of the driving transistor, and thereby improving the reset speed and charging speed of the driving transistor gate.

[0268] In some examples, as shown in FIGS. 39-41, the first conductive layer 150 further includes a second conductive pattern 1541 that is connected to the initialization signal line 141 and the source of the reset transistor T6, respectively. The orthographic projection of the third portion 633 on the base substrate 110 overlaps with the orthographic projection of the initialization signal line 141 on the base substrate 110. The orthographic projection of the third portion 633 on the base substrate 110 overlaps with the orthographic projection of the second conductive pattern 1541 on the base substrate 110. The orthographic projection of the fourth portion 634 on the base substrate 110 overlaps with the orthographic projection of the first conductive pattern 1542 on the base substrate 110.

[0269] In some examples, as shown in FIGS. 39-41, the orthographic projection of the hollow region 1622H on the base substrate 110 overlaps with the orthographic projection of the initialization signal line 141 on the base substrate 110. The orthographic projection of the hollow region 1622H on the base substrate 110 overlaps with the orthographic projection of the second conductive pattern 1541 on the base substrate 110. The orthographic projection of the hollow region 1622H on the base substrate 110 overlaps with the orthographic projection of the second electrode block CE2 on the base substrate 110.

[0270] In some examples, as shown in FIGS. 39-41, the display substrate further includes a second flat layer 242 located on one side away from the base substrate 110 of the second conductive layer 160, and a plurality of light-emitting element groups 310 located on one side away from the second conductive layer 160 of the second flat layer 242. The plurality of light-emitting element groups 310 are arranged along a first direction to form a plurality of light-emitting element columns 320, and are arranged along a second direction to form a plurality of light-emitting element rows 330. Each of the light-emitting element groups 310 includes one first light-emitting element 311, one second light-emitting element 312, one third light-emitting element 313, and one fourth light-emitting element 314. The second light-emitting element 312 and the third light-emitting element 313 are arranged along the second direction to form a light-emitting element pair 315. The first light-emitting element 311, the light-emitting element pair 315, and the fourth light-emitting element 314 are arranged along the first direction. The first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 includes a fourth anode 1754. The second conductive layer 160 includes a first connection electrode 1611, a second connection electrode 1612, a third connection electrode 1613, and a fourth connection electrode 1614. The second flat layer 242 includes a first via 2421, a second via 2422, a third via 2423, and a fourth via 2424. The first anode 1751 is connected to the first connection electrode 1611 through the first via 2421, the second anode 1752 is connected to the second connection electrode 1612 through the second via 2422, the third anode 1753 is connected to the third connection electrode 1613 through the third via 2423, and the fourth anode 1754 is connected to the fourth connection electrode 1614 through the fourth via 2424.

[0271] In some examples, the first anode 1751 includes a main body portion, and the orthographic projection of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110 is located inside the orthographic projection of the main body portion of the first anode 1751 on the base substrate 110, and has a boundary that is at least partially the same as that between the main body portion of the first anode 1751 and the first anode 1751. The second anode 1752 includes a main body portion, and the orthographic projection of the effective light-emitting region of the second light-emitting element 312 on the base substrate 110 is located inside the orthographic projection of the main body portion of the second anode 1752 on the base substrate 110, and has a boundary that is at least partially the same as that between the main body portion of the second anode 1752 and the second anode 1752. The third anode 1753 includes a main body portion, and the orthographic projection of the effective light-emitting region of the third light-emitting element 313 on the base substrate 110 is located inside the orthographic projection of the main body portion of the third anode 1753 on the base substrate 110, and has a boundary that is at least partially the same as that between the main body portion of the third anode 1753 and the third anode 1753. The fourth anode 1754 includes a main body portion, and the orthographic projection of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110 is located inside the orthographic projection of the main body portion of the fourth anode 1754 on the base substrate 110, and has a boundary that is at least partially the same as that between the main body portion of the fourth anode 1754 and the fourth anode 1754.

[0272] In some examples, the plurality of conductive portions 162 includes a second conductive portion 1621, and the first conductive portion 1621 and the second conductive portion 1622 are respectively located on both sides in the first direction of the effective light-emitting region of the first light-emitting element 311. The distance between the orthographic projection of the sealed annular portion 1622E on the base substrate 110 and the orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110 is substantially the same as the distance between the orthographic projection of the second conductive portion 1621 on the base substrate 110 and the orthographic projection of the center of the effective light-emitting region of the first light-emitting element 311 on the base substrate 110. Thereby, a higher flatness of the first anode 1751 can be ensured by the sealed annular portion 1622E, thereby ensuring that the light-emitting intensities of the first anode 1751 in different directions are consistent, and further effectively improving color bleeding.

[0273] In some examples, as shown in FIGS. 39-41, the orthographic projection of the first anode 1751 on the base substrate 110 overlaps with the orthographic projection of the light emission control line 133 of the first pixel driving circuit 2651 on the base substrate 110. When the first anode overlaps with the light emission control line, the connection electrode located at the first anode of the second conductive layer is moved downward, and further, the center of the third conductive pattern in the first conductive layer overlaps with the light emission control line, ensuring the flatness of the third conductive pattern and improving the effectiveness of the via connection.

[0274] In some examples, as shown in FIGS. 39-41, one fourth light emitting element 314 is installed at a position adjacent to the center of the hollow region 1622H in the second direction, and the orthographic projection of the fourth light emitting element 314 (for example, the fourth anode 1754 of the fourth light emitting element 314) on the base substrate 110 overlaps with the orthographic projections of the gate line 132, the reset signal line 131, and the initialization signal line 141 on the base substrate 110.

[0275] In some examples, as shown in FIGS. 39-41, the first conductive layer 151 further includes a third conductive pattern 1543, the second conductive layer 160 further includes an anode connection portion 161, that is, the above connection electrode, and the third conductive pattern 1543 is connected to the drain of the second light emission control transistor T5 and the anode connection portion 161.

[0276] In some examples, as shown in FIGS. 39-41, the orthographic projection of the gate line 132 on the base substrate 110 overlaps with the orthographic projection of the first conductive pattern 1542 on the base substrate 110.

[0277] In some examples, as shown in FIGS. 39-41, the orthographic projection of the first electrode block CE1 and the second electrode block CE2 on the base substrate 110 is located between the orthographic projection of the gate line 132 on the base substrate 110 and the orthographic projection of the emission control line 133 on the base substrate 110. That is, the orthographic projection of the storage capacitor Cst on the base substrate 110 is located between the orthographic projection of the gate line 132 on the base substrate 110 and the orthographic projection of the emission control line 133 on the base substrate 110, thereby enabling rational utilization of space.

[0278] In some examples, as shown in FIGS. 39-41, the orthographic projection of the reset signal line 131 on the base substrate 110 is located between the orthographic projection of the gate line 132 on the base substrate 110 and the orthographic projection of the initialization signal line 141 on the base substrate 110. And in one pixel driving circuit 265, the emission control line 133, the first electrode block CE1, the gate line 132, the reset signal line 131, and the initialization signal line 141 are arranged along the second direction, thereby enabling rational utilization of the space on the display substrate.

[0279] In some examples, as shown in FIGS. 39-41, the plurality of pixel driving circuits 265 include a second gate layer 140, the second electrode block CE2 is located in the second gate layer 140, and at least two second electrode blocks CE2 are connected in the first direction. That is, at least two second electrode blocks CE2 located in the second gate layer 140 are electrically connected to each other, thereby improving the uniformity of the storage capacitors of different sub-pixels of the entire display panel.

[0280] In some examples, as shown in FIGS. 39-41, the orthographic projections of the effective emission regions of the first light-emitting element 311 and the second light-emitting element 312 on the base substrate 110 do not overlap with the orthographic projection of the conductive portion 162 on the base substrate 110. Thereby, the adverse effect on the flatness of the first light-emitting element 311 and the second light-emitting element 312 caused by the conductive portion can be avoided. For example, the second light-emitting element 312 is configured to emit green light.

[0281] In some examples, as shown in FIGS. 39-41, the orthographic projection of the center of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110 overlaps with the orthographic projection of the conductive portion 162 on the base substrate 110. The overlapping portion of the conductive portion 162 and the orthographic projection of the center of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110 is a solid portion. Thereby, even if the effective light-emitting region of the fourth light-emitting element 314 overlaps with the conductive portion 162, the orthographic projection of the center of the effective light-emitting region of the fourth light-emitting element 314 on the base substrate 110 overlaps with the orthographic projection of the conductive portion 162 on the base substrate 110, and an adverse effect of the conductive portion on the flatness of the fourth light-emitting element 314 can be avoided. For example, the fourth light-emitting element 314 is configured to emit blue light. However, the above-mentioned "solid portion" means that the portion does not include a hollow.

[0282] In some examples, as shown in FIGS. 39-41, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, the overlapping area between the main body portion of the second anode 1752 and the two conductive portions 162 adjacent to the second anode 1752 in the first direction is substantially the same, and the overlapping area between the main body portion of the third anode 1753 and the two conductive portions 162 adjacent to the second anode 1753 in the first direction is substantially the same. Thereby, the flatness of the second anode and the third anode can be further improved.

[0283] In some examples, as shown in FIGS. 39-41, the orthographic projection of the hollow region 1622H on the base substrate 110 is located between the effective light-emitting region of the first light-emitting element 311 and the effective light-emitting region of the second light-emitting element 312. Thereby, the hollow region avoids the effective light-emitting region and can avoid color bleeding due to the recess of the anode in the effective light-emitting region. However, the above-mentioned first light-emitting element and second light-emitting element are the first light-emitting element and second light-emitting element that are closest in distance in the first direction.

[0284] In some examples, as shown in FIGS. 39 - 41, the size of the intermediate portion of the anode (for example, the first anode) of a light - emitting element configured to emit red light in the first direction in the second direction is larger than the size of the edge portion of the anode in the first direction in the second direction. For example, the shape of the anode is a substantially long hexagon. The size of the intermediate portion of the anode (for example, the fourth anode) of a light - emitting element configured to emit blue light in the first direction in the second direction is larger than the size of the edge portion of the anode in the first direction in the second direction. Thereby, the display substrate can make full use of the space between different anodes, and under the same process accuracy, maximize the areas of the anodes of the light - emitting elements configured to emit red light and the light - emitting elements configured to emit blue light.

[0285] In some examples, as shown in FIGS. 39 - 41, in one group of light - emitting elements, the orthographic projection of the anodes 175 of at least two light - emitting elements on the base substrate 110 overlaps with the orthographic projection of the apertures of the second electrode block CE2 on the base substrate 110. Thus, by blocking the apertures of the second electrode block, the gate of the driving transistor can be further blocked, and the gate of the driving transistor can be prevented from being overly exposed to light. The orthographic projection of the effective light - emitting region of at least one of the light - emitting elements 311, 312, 313, or 314 on the base substrate 110 does not overlap with the orthographic projection of the first electrode block CE1 or the second electrode block CE2 on the base substrate 110. Thereby, the protrusion of the effective light - emitting region due to the capacitor can be avoided, and color mixing can be avoided.

[0286] In some examples, in any of the light - emitting elements among the first light - emitting element 311, the second light - emitting element 312, the third light - emitting element 313, and the fourth light - emitting element 314, the first flat layer 241 has an anode hole, and the anode of the light - emitting element is connected to the pixel driving circuit corresponding to the light - emitting element through the anode hole.

[0287] In some examples, as shown in FIGS. 39-41, the orthographic projection of the anode hole (e.g., the first via 2421) of the anode (e.g., the first anode 1751) of the light-emitting element configured to emit red light on the base substrate 110 does not overlap with the orthographic projection of the main body of the anode on the base substrate in the second direction, and the orthographic projection of the anode hole of the anode on the base substrate 110 does not overlap with the orthographic projection of the effective light-emitting region of the light-emitting element configured to emit red light on the base substrate 110 in the second direction, thereby avoiding the adverse effect on the flatness of the first light-emitting element caused by the anode hole of the anode of the light-emitting element configured to emit red light.

[0288] In some examples, as shown in FIGS. 39-41, the orthographic projection of the anode hole (e.g., the fourth via 2424) of the anode (e.g., the fourth anode 1754) of the light-emitting element configured to emit blue light on the base substrate 110 does not overlap with the orthographic projection of the main body of the anode on the base substrate in the second direction, and the orthographic projection of the anode hole of the anode on the base substrate 110 does not overlap with the orthographic projection of the effective light-emitting region of the light-emitting element configured to emit red light on the base substrate 110 in the second direction, thereby avoiding the adverse effect on the flatness of the first light-emitting element caused by the anode hole of the anode of the light-emitting element configured to emit red light.

[0289] In some examples, as shown in FIGS. 39-41, a data line 152 is disposed between two adjacent conductive portions 162, and the distance between the orthographic projection of the adjacent conductive portions 162 and the data line 152 on the base substrate 110 is less than the distance between the orthographic projections of the two adjacent conductive portions 162 on the base substrate 110.

[0290] One embodiment of the present disclosure further provides a display device. FIG. 42 is a schematic diagram of a display device according to an embodiment of the present disclosure. As shown in FIG. 42, the display device 400 includes the display substrate 100 described in any of the above. Accordingly, the display device has beneficial effects corresponding to the beneficial effects of the display substrate. For example, the display device can enhance the stability of the compensation thin-film transistors and extend the service life, thereby enhancing the long-term light-emitting stability of the display substrate and extending the service life.

[0291] For example, the display device may be an electronic product having a display function such as a television, a computer, a laptop computer, a tablet computer, a mobile phone, a navigator, a digital photo frame, etc.

[0292] Note that (1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to normal designs. (2) The features of the same embodiment and different embodiments of the present disclosure can be combined with each other as long as there is no contradiction.

[0293] The specific embodiments of the present disclosure have been described above, but they do not limit the protection scope of the present disclosure, and the patent scope of the present disclosure should conform to the scope of the appended patent claims.

Claims

1. A display substrate, comprising: a base substrate; a plurality of pixel driving circuits having semiconductor layers; a first conductive layer located on a side of the semiconductor layer away from the base substrate; a first flat layer located on a side of the first conductive layer away from the base substrate; a second conductive layer located on a side of the first flat layer away from the first conductive layer; a second flat layer located on a side of the second conductive layer away from the base substrate; a plurality of light emitting element groups located on a side of the second flat layer away from the second conductive layer; the second conductive layer includes a plurality of conductive portions arranged along a first direction, and the size of the second conductive layer in a second direction intersecting the first direction is larger than the size of the second conductive layer in the first direction; the plurality of conductive portions includes a first conductive portion having a sealed annular portion separated from at least one adjacent conductive portion in the first direction by the second conductive layer; each of the light emitting element groups includes a first light emitting element having a first anode whose orthographic projection on the base substrate overlaps the orthographic projection of the sealed annular portion on the base substrate; the plurality of conductive portions further includes a second conductive portion adjacent to the first conductive portion and whose orthographic projection on the base substrate overlaps the orthographic projection of the first anode on the base substrate; A display substrate.

2. The size of the sealed annular portion in the first direction is at least larger than the size of a part of the first conductive portion in the first direction; the plurality of pixel driving circuits includes a first pixel driving circuit having a semiconductor pattern in the semiconductor layer, and the orthographic projection of the first conductive portion on the base substrate overlaps the orthographic projection of the semiconductor pattern of the first pixel driving circuit on the base substrate; the first pixel driving circuit includes a driving transistor; The first conductive layer has the same potential as the gate of the driving transistor, and includes a first conductive pattern that forms a gate potential metal together with the gate of the driving transistor, and an orthographic projection of the hollow region inside the sealed annular portion on the base substrate overlaps with the gate potential metal. The display substrate according to claim 1.

3. The inside of the sealed annular portion has a hollow region. The first conductive portion has a plurality of the hollow regions arranged along the second direction, and the shapes and sizes of two adjacent hollow regions are substantially the same. The display substrate according to claim 1.

4. The first light-emitting element includes an effective light-emitting region. An orthographic projection of a straight line passing through the center of the effective light-emitting region of the first light-emitting element and extending along the second direction on the base substrate is between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the second conductive portion on the base substrate. The display substrate according to any one of claims 1 to 3.

5. Each of the two edges of the sealed annular portion in the first direction overlaps with the orthographic projection of the anodes of a plurality of light-emitting elements in the light-emitting element group on the base substrate, and the hollow region of the sealed annular portion and the orthographic projection of the effective light-emitting regions of the plurality of light-emitting elements on the base substrate are separately installed. The display substrate according to any one of claims 2 to 3.

6. The first conductive layer further includes a conductive metal configured to supply power to the pixel driving circuit. The conductive portion is electrically connected to the conductive metal by a conductive metal via included in the first flat layer. The first pixel driving circuit further includes a first light-emitting control transistor and a storage capacitor having a first electrode block and a second electrode block located on one side of the first electrode block away from the base substrate. The conductive metal is electrically connected to the source of the first light emission control transistor and the second electrode block, respectively. The display substrate according to claim 2.

7. The orthographic projection of the sealed annular portion on the base substrate overlaps with the orthographic projection of the first electrode block on the base substrate. The second electrode block includes an opening whose orthographic projection on the base substrate overlaps with the orthographic projection of the first electrode block on the base substrate, and the orthographic projection of the sealed annular portion on the base substrate also overlaps with the orthographic projection of the opening on the base substrate. The display substrate according to claim 6.

8. The first pixel driving circuit further includes a data writing transistor, a compensation transistor, a reset transistor, an anode initialization transistor, and a second light emission control transistor. The display substrate is a reset signal line connected to the gate of the reset transistor, a gate line connected to the gate of the compensation transistor, a light emission control line connected to the gate of the first light emission control transistor, and an initialization signal line connected to the source of the reset transistor, and further includes each of the orthographic projections of the sealed annular portion on the base substrate overlaps with the orthographic projections of the reset signal line, the gate line, and the initialization signal line on the base substrate. The display substrate according to claim 7.

9. One end of the first conductive pattern is electrically connected to the gate of the driving transistor through the opening. The other end of the first conductive pattern is electrically connected to the source or drain of the compensation transistor. The display substrate according to claim 8.

10. The sealed annular portion includes a first portion and a second portion arranged along the first direction, and a third portion and a fourth portion arranged along the second direction. The first portion, the third portion, the second portion, and the fourth portion are connected end to end to form the sealed annular portion, and the orthographic projection of the first portion and the second portion on the base substrate overlaps with the orthographic projection of the second electrode block on the base substrate. The display substrate according to claim 8.

11. The orthographic projection of the first portion on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate. Both the shape of the first conductive pattern and the first portion are elongated, and the extending direction of the long side of the first conductive pattern is the same as the extending direction of the long side of the first portion. The display substrate according to claim 10.

12. The first conductive layer further includes a second conductive pattern respectively connected to the initialization signal line and the source of the reset transistor, and a third conductive pattern. The second conductive layer further includes an anode connection portion. The third conductive pattern is connected to the drain of the second light emission control transistor and the anode connection portion. The orthographic projection of the third portion on the base substrate overlaps with the orthographic projection of the initialization signal line on the base substrate, the orthographic projection of the third portion on the base substrate also overlaps with the orthographic projection of the second conductive pattern on the base substrate, and the orthographic projection of the fourth portion on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate. The display substrate according to claim 10.

13. The orthographic projection of the base substrate of the hollow region overlaps with the orthographic projection of the initialization signal line on the base substrate, and also overlaps with the orthographic projection of the second conductive pattern on the base substrate, and also overlaps with the orthographic projection of the second electrode block on the base substrate. The display substrate according to claim 12.

14. The plurality of light-emitting element groups are arranged along the first direction to form a plurality of light-emitting element columns, and are arranged along the second direction to form a plurality of light-emitting element rows. Each of the light-emitting element groups includes one of the first light-emitting elements, one second light-emitting element, one third light-emitting element, and one fourth light-emitting element. The first anode includes a main body portion, and the orthographic projection of the effective light-emitting region of the first light-emitting element on the base substrate is located inside the orthographic projection of the main body portion of the first anode on the base substrate, and the main body portion of the first anode and the first anode have at least partially the same boundary. The first conductive portion and the second conductive portion included in the plurality of conductive portions are respectively located on both sides of the effective light-emitting region of the first light-emitting element in the first direction, and the distance from the orthographic projection of the sealed annular portion on the base substrate to the orthographic projection of the center of the effective light-emitting region of the first light-emitting element on the base substrate is substantially the same as the distance from the orthographic projection of the second conductive portion on the base substrate to the orthographic projection of the center of the effective light-emitting region of the first light-emitting element on the base substrate. The display substrate according to any one of claims 8 to 13.

15. The orthographic projection of the first anode on the base substrate overlaps with the orthographic projection of the light-emitting control line of the first pixel driving circuit on the base substrate, and at a position adjacent to the center of the hollow region in the second direction, there is installed one fourth light-emitting element where the orthographic projection of the anode on the base substrate overlaps with the orthographic projections of the gate line, the reset signal line, and the initialization signal line on the base substrate. The display substrate according to claim 13.

16. The orthographic projection of the gate line on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate, In one of the pixel driving circuits, the orthographic projections of the first electrode block and the second electrode block on the base substrate are located between the orthographic projection of the gate line on the base substrate and the orthographic projection of the light emission control line on the base substrate, The orthographic projection of the reset signal line on the base substrate is located between the orthographic projection of the gate line on the base substrate and the orthographic projection of the initialization signal line on the base substrate, The light emission control line, the first electrode block, the gate line, the reset signal line, and the initialization signal line are arranged along the second direction. The display substrate according to claim 12.

17. The plurality of pixel driving circuits further include a second gate electrode layer located on a side of the first conductive layer close to the base substrate, and the second electrode block is located in the second gate electrode layer. At least two of the second electrode blocks are connected in the second gate electrode layer. The display substrate according to any one of claims 14 to 16.

18. The orthographic projections of the effective light emission regions of the first light emitting element and the second light emitting element on the base substrate do not overlap with the orthographic projection of the conductive portion on the base substrate, and the second light emitting element is configured to emit green light. The orthographic projection of the center of the effective light emission region of the fourth light emitting element on the base substrate overlaps with the orthographic projection of the conductive portion on the base substrate. The orthographic projection of the conductive portion and the center of the effective light emission region of the fourth light emitting element on the base substrate has a solid overlapping portion, and the fourth light emitting element is configured to emit blue light. The display substrate according to claim 14.

19. The second light-emitting element includes a second anode, and an orthographic projection of an effective light-emitting region of the second light-emitting element on the base substrate is located inside an orthographic projection of a main body portion of the second anode on the base substrate, and the main body portion of the second anode and the second anode have at least a partially same boundary. An overlapping area between the main body portion of the second anode and two conductive portions adjacent to each other in the first direction of the second anode is substantially the same. The display substrate according to claim 14 or 18.

20. An orthographic projection of the hollow region on the base substrate is located between the effective light-emitting region of the first light-emitting element and the effective light-emitting region of the second light-emitting element, and the first light-emitting element and the second light-emitting element are the first light-emitting element and the second light-emitting element having the closest distance in the first direction. The display substrate according to any one of claims 14 and 18 to 19.

21. A size of an intermediate portion in the first direction of an anode of a light-emitting element configured to emit red light in a second direction is larger than a size of an edge portion in the first direction of the anode in the second direction. A size of an intermediate portion in the first direction of an anode of a light-emitting element configured to emit blue light in a second direction is larger than a size of an edge portion in the first direction of the anode in the second direction. The display substrate according to any one of claims 14 to 19.

22. In one light-emitting element group, an orthographic projection of anodes of at least two light-emitting elements on the base substrate overlaps an orthographic projection of the opening of the second electrode block on the base substrate, and an orthographic projection of an effective light-emitting region of at least one light-emitting element on the base substrate does not overlap an orthographic projection of the first electrode block or the second electrode block on the base substrate. The display substrate according to any one of claims 14 to 19.

23. In any one of the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element, the anode of the light-emitting element is connected to a pixel driving circuit corresponding to the light-emitting element through an anode hole included in the first flat layer. The orthographic projection of the anode hole of the anode of the light-emitting element configured to emit red light on the base substrate and the orthographic projection of the main body portion of the anode on the base substrate do not overlap in the second direction, and the orthographic projection of the anode hole of the anode of the light-emitting element configured to emit red light on the base substrate and the orthographic projection of the effective light-emitting region of the light-emitting element configured to emit red light on the base substrate do not overlap in the second direction. The orthographic projection of the anode hole of the anode of the light-emitting element configured to emit blue light on the base substrate and the orthographic projection of the main body portion of the anode on the base substrate do not overlap in the second direction, and the orthographic projection of the anode hole of the anode of the light-emitting element configured to emit blue light on the base substrate and the orthographic projection of the effective light-emitting region of the light-emitting element configured to emit blue light on the base substrate do not overlap in the second direction. The display substrate according to claim 18.

24. A data line is provided between two adjacent conductive portions, and the distance between the orthographic projections of the adjacent conductive portions and the data line on the base substrate is shorter than the distance between the orthographic projections of the two adjacent conductive portions on the base substrate. The display substrate according to any one of claims 1 to 23.

25. Comprising the display substrate according to any one of claims 1 to 24, A display device.

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