Display system, and electronic device

Abstract

Provided is a high definition display system having high display quality. This display system has a first layer and a display part. The display part is located in a region overlapping the first layer. The first layer has a semiconductor substrate that uses silicon as a material therefor, and a plurality of first transistors and a plurality of second transistors each including silicon in a channel forming region are formed on the semiconductor substrate. The first layer has a first circuit and a second circuit, the first circuit has a driving circuit for driving the display part, and the second circuit has a storage device, a GPU, and an EL correction circuit. The display part has pixels, and each pixel has a light emitting device including organic EL and is electrically connected to the driving circuit. The storage device has a function of holding image data, the GPU has a function of decoding the image data read from the storage device, and the EL correction circuit has a function of correcting light emitted by the light emitting device.

Description

Technical Field

[0001] One aspect of the present invention relates to a display system and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.

Background Art

[0003] There is a demand for a display device applicable to XR (a general term for VR, AR, etc.) such as VR (Virtual Reality) and AR (Augmented Reality). Specifically, for example, in order to enhance the sense of reality and immersion, it is desired that the display device has high definition and high color reproducibility.

[0004] In addition, examples of what can be applied to the display device include a liquid crystal display device, a light-emitting device including a light-emitting device such as organic EL (Electro Luminescence) and a light-emitting diode (LED: Light Emitting Diode). Patent Document 1 discloses a high pixel number and high definition display device including a light-emitting device including organic EL.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] As described above, as a device for XR, a display device with high display quality is required. Further, as a display device for XR, for example, it is necessary to be provided in a glasses-type housing or a goggle-type housing, and thus it is necessary to reduce the size of the display device to approximately 2 inches or less in diagonal, 1 inch or less in diagonal, etc.

[0007] In addition, the display device requires peripheral circuits such as a driver circuit, a storage device for storing an image to be displayed in advance, a digital-to-analog conversion circuit (DAC), and a decoder for restoring an encoded image. Further, when enhancing the display quality, it is preferable to be provided with a circuit for correcting image data. Therefore, when providing these peripheral circuits, the housing size may increase and the burden on the wearer of the housing may increase. Also, when the number of peripheral circuits increases, the access of signals between pixels and peripheral circuits in the display device increases, and thus the access time and power consumption may also increase.

[0008] One aspect of the present invention is to provide a display device with reduced circuit area as one of the problems. Or, one aspect of the present invention is to provide a display device with reduced power consumption as one of the problems. Or, one aspect of the present invention is to provide a display device with high display quality as one of the problems. Or, one aspect of the present invention is to provide a novel semiconductor device as one of the problems. Or, one aspect of the present invention is to provide a system having any of the above-described semiconductor devices as one of the problems.

[0009] Note that the problems of one aspect of the present invention are not limited to the problems listed above. The problems listed above do not prevent the existence of other problems. Other problems are those not mentioned in this item as described below. Problems not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention solves at least one of the problems listed above and other problems. Note that one aspect of the present invention does not need to solve all of the problems listed above and other problems.

Means for Solving the Problems

[0010] (1) One aspect of the present invention is a display system having a first layer and a display unit. The display unit is located in a region overlapping the first layer. The first layer has a semiconductor substrate made of silicon, and the first layer has a plurality of first transistors and a plurality of second transistors including silicon in a channel formation region. The first layer has a first circuit and a second circuit. The first circuit has a source driver circuit and a gate driver circuit each including a first transistor. The second circuit has a storage device, a CPU, a GPU, an EL correction circuit, a timing controller, and a high-frequency circuit each including a second transistor. The display unit has pixels, and each pixel has a light-emitting device including an organic EL. Each pixel is electrically connected to the source driver circuit and the gate driver circuit. The storage device has a function of holding image data. The CPU has a function of transmitting a control signal to one or more selected from the storage device, the GPU, the EL correction circuit, the timing controller, and the high-frequency circuit. The GPU has a function of decoding the image data read from the storage device. The source driver circuit has a function of transmitting the decoded image data to the pixels. The EL correction circuit has a function of correcting the luminance of the light emitted by the light-emitting device. The timing controller has a function of increasing or decreasing the frame rate at which an image is displayed on the display unit. The high-frequency circuit has a function of converting an electrical signal generated by any one of the CPU, the GPU, and the storage device into an RF signal and transmitting it to the outside, and a function of converting an RF signal acquired from the outside into an electrical signal and transmitting it to any one of the CPU, the GPU, and the storage device.

[0011] (2) Alternatively, one aspect of the present invention is a display system having a first layer and a display unit. The display unit is located in a region overlapping the first layer. The first layer has a semiconductor substrate made of silicon, and the first layer has a plurality of first transistors including silicon in a channel formation region and a plurality of second transistors. The first layer has a first circuit and a second circuit. The first circuit has a source driver circuit and a gate driver circuit each including a first transistor. The second circuit has a storage device, a GPU, an EL correction circuit, and a timing controller each including a second transistor. The display unit has pixels, and each pixel has a light-emitting device including an organic EL. Each pixel is electrically connected to the source driver circuit and the gate driver circuit. The storage device has a function of holding image data, the GPU has a function of decoding the image data read from the storage device, the source driver circuit has a function of transmitting the decoded image data to the pixels, the EL correction circuit has a function of correcting the luminance of the light emitted by the light-emitting device, and the timing controller has a function of increasing or decreasing the frame rate at which an image is displayed on the display unit.

[0012] (3) Alternatively, one aspect of the present invention is a display system having a first layer, a second layer, and a display unit. The display unit is located in a region overlapping the first layer, and the second layer is located in a region overlapping the first layer. The first layer has a semiconductor substrate made of silicon, and the first layer has a plurality of first transistors and a plurality of second transistors including silicon in a channel formation region. The second layer has a plurality of third transistors including a metal oxide in a channel formation region. The first layer has a first circuit and a second circuit. The first circuit has a source driver circuit and a gate driver circuit each including a first transistor, and the second circuit has a storage device, a GPU, an EL correction circuit, and a timing controller each including a second transistor. The third transistor functions as a transistor included in the storage device included in the first layer. The display unit has pixels, and each pixel has a light-emitting device including an organic EL. Each pixel is electrically connected to the source driver circuit and the gate driver circuit. The storage device has a function of holding image data, the GPU has a function of decoding the image data read from the storage device, the source driver circuit has a function of transmitting the decoded image data to the pixels, the EL correction circuit has a function of correcting the luminance of the light emitted by the light-emitting device, and the timing controller has a function of increasing or decreasing the frame rate at which an image is displayed on the display unit.

[0013] (4) Alternatively, in one aspect of the present invention, in the above (3), the second layer may have a memory cell.

[0014] (5) Alternatively, in one aspect of the present invention, in any one of the above (2) to (4), the second circuit may have a CPU including a second transistor. Further, it is preferable that the CPU has a function of transmitting a control signal to one or two or more selected from the storage device, the GPU, the EL correction circuit, and the timing controller.

[0015] (6) Alternatively, in one aspect of the present invention, in any one of (1) to (5) above, the GPU may be configured to perform operations of an artificial neural network and correct the image displayed on the display unit based on the result of the operations.

[0016] (7) Alternatively, one aspect of the present invention is an electronic device having any one of the display systems of (1) to (6) above and a housing.

[0017] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the same circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip equipped with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device may be a semiconductor device itself or may have a semiconductor device.

[0018] Also, in this specification and the like, when it is described that X and Y are connected, it is assumed that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected, as disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. It is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0019] As an example of the case where X and Y are electrically connected, one or more elements that enable electrical connection between X and Y (for example, switches, transistors, capacitive elements, inductors, resistive elements, diodes, display devices, light-emitting devices, loads, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch has a function of becoming a conductive state (on state) or a non-conductive state (off state) and controlling whether to allow current to flow or not.

[0020] As an example of the case where X and Y are functionally connected, one or more circuits that enable functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. Note that, as an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, it is considered that X and Y are functionally connected.

[0021] Note that when it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, when they are connected with another element or another circuit interposed between X and Y) and the case where X and Y are directly connected (that is, when they are connected without another element or another circuit interposed between X and Y).

[0022] Also, for example, it can be expressed as "X, Y, the source (or the first terminal, etc.) of the transistor, and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to Y via the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are provided in this connection order." By stipulating the connection order in the circuit configuration using an expression method similar to these examples, the source (or the first terminal, etc.) of the transistor and the drain (or the second terminal, etc.) can be distinguished to determine the technical scope. Note that these expression methods are just examples and are not limited to these expression methods. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0023] Note that even if components that are independent on the circuit diagram are shown to be electrically connected, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring component and the electrode component. Therefore, the electrically connected in this specification includes such a case where one conductive film has the functions of multiple components within its scope.

[0024] In addition, in this specification and the like, the "resistive element" can be, for example, a circuit element having a resistance value higher than 0 Ω, a wiring having a resistance value higher than 0 Ω, and the like. Therefore, in this specification and the like, the "resistive element" includes a wiring having a resistance value, a transistor through which current flows between the source and the drain, a diode, a coil, and the like. Therefore, the term "resistive element" may sometimes be replaced with terms such as "resistance", "load", and "region having a resistance value". Conversely, the terms "resistance", "load", and "region having a resistance value" may sometimes be replaced with terms such as "resistive element". As the resistance value, for example, it can be preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and still more preferably 10 mΩ or more and 1 Ω or less. Also, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0025] In addition, in this specification and the like, the "capacitive element" can be, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, and the like. Also, terms such as "capacitive element", "parasitic capacitance", and "gate capacitance" may sometimes be replaced with terms such as "capacitance". Conversely, the term "capacitance" may sometimes be replaced with terms such as "capacitive element", "parasitic capacitance", and "gate capacitance". Also, the term "pair of electrodes" of "capacitance" may sometimes be replaced with "pair of conductors", "pair of conductive regions", "pair of regions", and the like. Note that the capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Also, for example, it may be 1 pF or more and 10 μF or less.

[0026] Also, in this specification and the like, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as the source or the drain are the input / output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the levels of the potentials applied to the three terminals of the transistor, one of the two input / output terminals becomes the source and the other becomes the drain. Therefore, in this specification and the like, the terms source and drain may be interchangeable with each other. Further, in this specification and the like, when explaining the connection relationship of the transistor, the notations "one of the source or the drain" (or the first electrode, or the first terminal), "the other of the source or the drain" (or the second electrode, or the second terminal) are used. Note that depending on the structure of the transistor, in addition to the three terminals described above, it may have a back gate. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as the first gate, and the other of the gate or the back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable with each other. Also, when the transistor has three or more gates, in this specification and the like, each gate may be referred to as the first gate, the second gate, the third gate, and so on.

[0027] For example, in this specification and the like, as an example of a transistor, a transistor having a multi-gate structure with two or more gate electrodes can be used. When a multi-gate structure is adopted, since the channel formation regions are connected in series, a structure in which a plurality of transistors are connected in series is formed. Therefore, by the multi-gate structure, it is possible to reduce the off-current and improve the breakdown voltage (improve the reliability) of the transistor. Alternatively, by the multi-gate structure, when operating in the saturation region, even if the voltage between the drain and the source changes, the current between the drain and the source does not change much, and voltage-current characteristics with a flat slope can be obtained. Utilizing voltage-current characteristics with a flat slope, an ideal current source circuit or an active load having a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0028] Also, on a circuit diagram, even when a single circuit element is illustrated, the circuit element may have a plurality of circuit elements. For example, when one resistor is described on the circuit diagram, it shall include the case where two or more resistors are electrically connected in series. Further, for example, when one capacitor is described on the circuit diagram, it shall include the case where two or more capacitors are electrically connected in parallel. Further, for example, when one transistor is described on the circuit diagram, it shall include the case where two or more transistors are electrically connected in series and the gates of the respective transistors are electrically connected. Similarly, for example, when one switch is described on the circuit diagram, it shall include the case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel, and the gates of the respective transistors are electrically connected.

[0029] Also, in this specification and the like, a node can be rephrased as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. according to the circuit configuration or device structure. Also, it is possible to rephrase a terminal, wiring, etc. as a node.

[0030] Also, in this specification and the like, "voltage" and "electric potential" can be appropriately rephrased. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earthing potential), "voltage" can be rephrased as "electric potential". Note that the ground potential does not necessarily mean 0V. Also, electric potential is relative, and when the reference potential changes, the potential applied to a wiring, the potential applied to a circuit, etc., and the potential output from a circuit, etc. also change.

[0031] Also, in this specification and the like, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, in the case where both of two wirings are described as "functioning as a wiring that supplies a high-level potential", the respective high-level potentials provided by the two wirings do not have to be equal to each other. Similarly, in the case where both of two wirings are described as "functioning as a wiring that supplies a low-level potential", the respective low-level potentials provided by the two wirings do not have to be equal to each other.

[0032] "Current" refers to the phenomenon of charge movement (electrical conduction). For example, the description "electrical conduction of a positive charge carrier is occurring" can be rephrased as "electrical conduction of a negative charge carrier is occurring in the opposite direction". Therefore, in this specification and the like, "current" shall refer to the phenomenon of charge movement (electrical conduction) associated with the movement of carriers, unless otherwise specified. The carriers mentioned here include electrons, holes, anions, cations, complex ions, etc., and the carriers vary depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, vacuum, etc.). Also, the "direction of current" in wiring, etc., is defined as the direction in which the carrier becomes a positive charge and is described with a positive current amount. In other words, the direction in which the carrier becomes a negative charge is the opposite direction of the current direction and is expressed with a negative current amount. Therefore, in this specification and the like, when there is no specification regarding the positive or negative of the current (or the direction of the current), descriptions such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A", etc. Also, descriptions such as "a current is input to element A" can be rephrased as "a current is output from element A", etc.

[0033] Also, in this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, in one of the embodiments of this specification and the like, the component referred to as "first" may be the component referred to as "second" in other embodiments or in the claims. Also, for example, in one of the embodiments of this specification and the like, the component referred to as "first" may be omitted in other embodiments or in the claims.

[0034] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" may be used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and the like, and can be appropriately rephrased according to the situation. For example, in the expression "the insulator located on the upper surface of the conductor", by rotating the orientation of the shown drawing by 180 degrees, it can be rephrased as "the insulator located on the lower surface of the conductor".

[0035] Also, the terms "above" or "below" do not limit the positional relationship between components to be directly above or directly below and in direct contact. For example, in the expression "electrode B on insulating layer A", it is not necessary for electrode B to be formed directly in contact on insulating layer A, and those including other components between insulating layer A and electrode B are not excluded.

[0036] In addition, in this specification and the like, terms such as "film" and "layer" can be interchanged with each other according to the situation. For example, the term "conductive layer" may be changed to the term "conductive film". Or, for example, the term "insulating film" may be changed to the term "insulating layer". Or, in some cases, or according to the situation, it is possible to replace the terms such as "film" and "layer" with other terms without using them. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" may be changed to the term "insulator".

[0037] In addition, in this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the term "electrode" or "wiring" also includes cases where a plurality of "electrodes" or "wirings" are integrally formed. Also, for example, a "terminal" may be used as part of "wiring" or "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", etc. are integrally formed. Therefore, for example, an "electrode" can be part of "wiring" or "terminal", and for example, a "terminal" can be part of "wiring" or "electrode. Also, terms such as "electrode", "wiring", "terminal", etc. may be replaced by terms such as "region" depending on the case.

[0038] In addition, in this specification and the like, terms such as "wiring", "signal line", "power line", etc. can be interchanged with each other depending on the case or according to the situation. For example, the term "wiring" may be changed to the term "signal line" in some cases. Also, for example, the term "wiring" may be changed to terms such as "power line" in some cases. Also, vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring" in some cases. Terms such as "power line" may be changed to terms such as "signal line" in some cases. Also, vice versa, terms such as "signal line" may be changed to terms such as "power line" in some cases. Also, the term "potential" applied to the wiring may be changed to terms such as "signal" depending on the case or according to the situation. Also, vice versa, terms such as "signal" may be changed to the term "potential" in some cases.

[0039] In this specification and the like, impurities in a semiconductor refer to, for example, components other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic% are impurities. When impurities are contained, for example, the density of defect levels in the semiconductor may increase, the carrier mobility may decrease, and the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, etc. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. Specifically, when the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 15 elements, etc. (however, oxygen and hydrogen are not included).

[0040] In this specification and the like, a switch refers to something that can be in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not an electric current flows. Or, a switch refers to something that has a function of selecting and switching the path through which an electric current flows. Therefore, a switch may have two or three or more terminals through which an electric current flows, in addition to the control terminal. As an example, an electrical switch, a mechanical switch, etc. can be used. That is, a switch only needs to be able to control an electric current and is not limited to a specific one.

[0041] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these. When a transistor is used as a switch, the "conducting state" of the transistor refers to, for example, a state where the source electrode and the drain electrode of the transistor can be considered to be electrically short-circuited, or a state where a current can flow between the source electrode and the drain electrode. Also, the "non-conducting state" of the transistor refers to a state where the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When operating a transistor simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a switch using MEMS (Micro-Electro-Mechanical Systems) technology. The switch has electrodes that can be mechanically moved, and by moving the electrodes, it controls conduction and non-conduction to operate.

[0043] Also, in this specification etc., a device fabricated using a metal mask or an FMM (Fine Metal Mask, high-precision metal mask) may be referred to as a device with an MM (Metal Mask) structure. Also, in this specification etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (Metal Maskless) structure.

[0044] In addition, in this specification and the like, a structure in which light-emitting devices of various colors (here, blue (B), green (G), and red (R)) create or paint different light-emitting layers may be referred to as an SBS (Side By Side) structure. Also, in this specification and the like, a light-emitting device capable of emitting white light may be referred to as a white light-emitting device. Note that a white light-emitting device can be combined with a coloring layer (e.g., a color filter) to form a full-color display device.

[0045] In addition, light-emitting devices can be broadly classified into a single structure and a tandem structure. A device with a single structure has one light-emitting unit between a pair of electrodes, and it is preferable that the light-emitting unit includes one or more light-emitting layers. To obtain white light, light-emitting layers can be selected such that the light emission of each of the two or more light-emitting layers is in a complementary color relationship. For example, by making the light emission color of the first light-emitting layer and the light emission color of the second light-emitting layer be in a complementary color relationship, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to a light-emitting device having three or more light-emitting layers.

[0046] A device with a tandem structure has two or more light-emitting units between a pair of electrodes, and it is preferable that each light-emitting unit includes one or more light-emitting layers. To obtain white light, a configuration can be adopted such that light from the light-emitting layers of the plurality of light-emitting units is combined to obtain white light. Note that the configuration for obtaining white light is the same as that of the single structure. In a device with a tandem structure, it is preferable to provide an intermediate layer such as a charge generation layer between the plurality of light-emitting units.

[0047] In addition, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with the light-emitting device having an SBS structure, the light-emitting device having an SBS structure can consume less power than the white light-emitting device. When it is desired to keep the power consumption low, it is preferable to use the light-emitting device having an SBS structure. On the other hand, the white light-emitting device is preferable because its manufacturing process is simpler than that of the light-emitting device having an SBS structure, so that the manufacturing cost can be reduced or the manufacturing yield can be increased.

[0048] In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Further, "substantially parallel" or "approximately parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Further, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, "substantially perpendicular" or "approximately perpendicular" means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Advantages of the Invention

[0049] According to one aspect of the present invention, a display device with a reduced circuit area can be provided. Or, according to one aspect of the present invention, a display device with reduced power consumption can be provided. Or, according to one aspect of the present invention, a display device with high display quality can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to one aspect of the present invention, a system having any of the above-mentioned semiconductor devices can be provided.

[0050] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are the effects not mentioned in this item as described below. The effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification, drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

Brief Description of Drawings

[0051] FIG. 1A is a diagram showing a configuration example of a display device, and FIG. 1B is a diagram showing a configuration example of a display system. FIG. 2 is a block diagram showing a configuration example of a display system. FIG. 3A is a diagram showing a configuration example of a display device, and FIG. 3B is a diagram showing a configuration example of a display system. FIG. 4 is a block diagram showing a configuration example of a display system. FIGS. 5A to 5G are circuit diagrams showing configuration examples of memory cells. FIG. 6 is a block diagram showing a configuration example of a display system. FIGS. 7A and 7B are schematic cross-sectional views showing configuration examples of a display system. FIG. 8 is a block diagram showing a configuration example of a display system. FIGS. 9A and 9B are diagrams showing configuration examples of a display system. FIG. 10 is a diagram showing a configuration example of a display system. FIGS. 11A and 11B are diagrams showing configuration examples of a display system. FIG. 12 is a diagram showing a configuration example of a display system. FIG. 13 is a block diagram showing a configuration example of a display system. FIGS. 14A and 14B are schematic cross-sectional views showing configuration examples of a display device or a display system. FIGS. 15A to 15C are diagrams showing configuration examples of a light-emitting device. FIG. 16 is a schematic cross-sectional view showing a configuration example of a display device or a display system. FIGS. 17A and 17B are schematic cross-sectional views showing a configuration example of a transistor. FIGS. 18A and 18B are schematic cross-sectional views showing a configuration example of a transistor. FIG. 19 is a schematic cross-sectional view showing a configuration example of a display device or a display system. FIG. 20 is a schematic cross-sectional view showing a configuration example of a display device or a display system. FIG. 21A is a diagram for explaining the classification of the crystal structure of IGZO, FIG. 21B is a diagram for explaining the XRD spectrum of crystalline IGZO, and FIG. 21C is a diagram for explaining the selected area electron diffraction pattern of crystalline IGZO. FIGS. 22A to 22F are diagrams showing a configuration example of an electronic device. FIGS. 23A and 23B are diagrams showing a configuration example of a display module. FIGS. 24A and 24B are diagrams showing a configuration example of an electronic device. FIGS. 25A to 25C are diagrams showing a configuration example of an electronic device. FIGS. 26A to 26D are diagrams showing a configuration example of an electronic device.

DETAILED DESCRIPTION OF THE INVENTION

[0052] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS), and the like. For example, when a metal oxide is included in the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplification action, a rectification action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor. Further, when referred to as an OS transistor, it can be paraphrased as a transistor having a metal oxide or an oxide semiconductor.

[0053] In addition, in this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Further, metal oxides containing nitrogen may be referred to as metal oxynitrides.

[0054] In addition, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form an aspect of the present invention. Also, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0055] Note that the content described in one embodiment (even a part of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment (even a part of the content), the content described in one or more other embodiments (even a part of the content).

[0056] Note that the content described in the embodiments refers to the content described using various figures in each embodiment or the content described using the text described in the specification.

[0057] Note that the figure (even a part of it) described in one embodiment can be combined with at least one of another part of the figure, another figure (even a part of it) described in the same embodiment, and the figure (even a part of it) described in one or more other embodiments to form more figures.

[0058] The embodiments described in this specification are described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and scope thereof. Therefore, the present invention is not construed as being limited to the described contents of the embodiments. In the configuration of the invention of the embodiments, the same reference numerals are commonly used for the same parts or parts having the same functions among different drawings, and repeated descriptions thereof may be omitted. Also, in perspective views and the like, for the sake of clarity of the drawings, descriptions of some components may be omitted.

[0059] In this specification and the like, when the same reference numerals are used for a plurality of elements, in particular, when it is necessary to distinguish them, identification symbols such as “_1”, “[n]”, “[m,n]” may be appended to the reference numerals for description. Also, in the drawings and the like, when identification symbols such as “_1”, “[n]”, “[m,n]” are appended to the reference numerals, when there is no need to distinguish them in this specification and the like, the identification symbols may not be described.

[0060] Also, in the drawings of this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0061] (Embodiment 1) In this embodiment, a display device and a display system according to an aspect of the present invention will be described.

[0062] <Configuration Example of Display Device> FIG. 1A is a diagram schematically showing a display device according to an aspect of the present invention. The display device 100 shown in FIG. 1A includes a display unit DSP and a circuit unit SIC. Further, the display device 100 has a configuration in which the circuit unit SIC is formed on a substrate, and the display unit DSP is further formed on the circuit unit SIC.

[0063] The display unit DSP has an area for displaying an image in the display device 100, and has a function of displaying an image based on a data signal transmitted from the circuit unit SIC. Further, the display unit DSP can have a configuration in which pixels are regularly arranged. For example, the pixels arranged in the display unit DSP may be arranged in a matrix. Also, the arrangement of a plurality of pixels in the display unit DSP may be a stripe type arrangement, a mosaic type arrangement, or a delta type arrangement. Therefore, in the present embodiment, the display unit DSP may be referred to as a pixel array. Note that there is no particular limitation on the screen ratio (aspect ratio) of the display unit DSP. For example, the display unit DSP can correspond to various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0064] The circuit unit SIC has a peripheral circuit DRV including a source driver circuit, a gate driver circuit, a digital-to-analog conversion circuit, and a level shifter in the display device 100. That is, the peripheral circuit DRV functions as a drive circuit for causing the display unit DSP to display an image.

[0065] The circuit section SIC can be configured, for example, by providing transistors, capacitors, etc. on a substrate. As the substrate, a semiconductor substrate (e.g., a single crystal substrate) made of silicon, germanium, etc. can be used. In addition to semiconductor substrates, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having a stainless steel foil, a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film can be used. Examples of the glass substrate include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of the flexible substrate, the laminated film, the base film, etc. include the following. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Or, as an example, there is a synthetic resin such as acrylic. Or, as an example, there are polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Or, as an example, there are polyamide, polyimide, aramid, epoxy resin, an inorganic vapor deposition film, or papers. In addition, when the manufacturing process of the display device 100 includes heat treatment, it is preferable to select a material with high heat resistance as the substrate.

[0066] In addition, in the present embodiment, the substrate included in the circuit section SIC will be described as a semiconductor substrate made of silicon or the like.

[0067] By using, for example, a semiconductor substrate made of silicon as the substrate included in the circuit unit SIC, transistors included in the peripheral circuit DRV can be formed on the semiconductor substrate. At this time, the transistor becomes a transistor including silicon in the channel formation region (hereinafter referred to as an Si transistor). Since the Si transistor has a high field-effect mobility, a large on-current can flow through it. As a result, it becomes possible to increase the driving speed of the peripheral circuit DRV, widen the range of the signal, and so on.

[0068] Also, when using a material having single-crystalline silicon as the circuit unit SIC, the size of the circuit unit SIC can be set to a diagonal size of 0.1 inches or more and 5 inches or less, preferably 0.5 inches or more and 3 inches or less in diagonal, and more preferably 1 inch or more and 2 inches or less in diagonal. Since the display unit DSP is provided above the circuit unit SIC, the size of the display unit DSP can be determined according to the size of the circuit unit SIC. Also, the amount of light emitted from the display unit DSP depends on the size of the display unit DSP. For example, when the size of the circuit unit SIC is 1 inch in diagonal, it is preferable because about four times the amount of light can be extracted from the display unit DSP compared to the case of a size of 0.5 inches in diagonal.

[0069] <Configuration example of the display system> Next, a display system according to an aspect of the present invention will be described.

[0070] FIG. 1B is a diagram schematically showing a display system according to an aspect of the present invention. The display system 200 shown in FIG. 1B is different from the display device 100 in that a functional circuit MFNC is provided in the circuit unit SIC of the display device 100 in FIG. 1A. Therefore, for the description of the display unit DSP and the peripheral circuit DRV in the display system 200 of FIG. 1B, the description of the display device 100 in FIG. 1A is referred to.

[0071] In addition, in this specification and the like, the display system refers to a configuration in which a functional circuit is provided in a display device. Also, since the display system is configured to display an image, it is assumed that the display system can be referred to as a display device.

[0072] The functional circuit MFNC can be provided with, for example, a storage device in which image data to be displayed on the display unit DSP is stored, a decoder for restoring the encoded image data, a GPU (Graphics Processing Unit) for processing the image data, a power supply circuit, a correction circuit, a CPU (Central Processing Unit), and the like.

[0073] As a specific configuration example, FIG. 2 shows a block diagram of the display system 200.

[0074] In addition, in FIG. 2, thick wirings (for example, wiring GL, wiring SL, and wiring BSL) are described as a plurality of wirings or bus wirings.

[0075] In the display system 200 of FIG. 2, as an example, a plurality of pixels PX are arranged in a matrix in the display unit DSP. As the pixel PX, for example, at least one of a light-emitting device including a liquid crystal display device, a light-emitting device including an organic EL, and a light-emitting diode such as a micro LED can be applied. In this embodiment, the pixel PX of the display unit DSP is described as being applied with a light-emitting device including an organic EL. Also, each of the plurality of pixels PX may be a pixel that emits different colors instead of the same color. For example, the plurality of pixels PX may be pixels that emit three colors of red, green, and blue. Therefore, in this specification and the like, the pixel may be described as a sub-pixel in some cases.

[0076] Also, in the display system 200 of FIG. 2, the peripheral circuit DRV included in the circuit unit SIC has, as an example, a source driver circuit 11, a digital-to-analog conversion circuit 12, a gate driver circuit 13, and a level shifter 14.

[0077] Also, in the display system 200 of FIG. 2, as an example, the functional circuit MFNC included in the circuit unit SIC includes a storage device 21, a GPU (AI accelerator) 22, an EL correction circuit 23, a timing controller 24, a CPU (NoffCPU (registered trademark)) 25, a sensor controller 26, and a power supply circuit 27.

[0078] Also, in the display system 200 of FIG. 2, as an example, a bus wiring BSL is electrically connected to each of the circuits included in the peripheral circuit DRV and the circuits included in the functional circuit MFNC.

[0079] The source driver circuit 11 has a function of transmitting image data to the pixel PX included in the display unit DSP, for example. Therefore, the source driver circuit 11 is electrically connected to the pixel PX via the wiring SL.

[0080] The digital-to-analog conversion circuit 12 has a function of converting image data digitally processed by, for example, a GPU and an EL correction circuit described later into analog data. The image data converted into analog data is transmitted to the display unit DSP via the source driver circuit 11. Note that the digital-to-analog conversion circuit 12 may be included in the source driver circuit 11, or the image data may be transmitted in the order of the source driver circuit 11, the digital-to-analog conversion circuit 12, and the display unit DSP.

[0081] The gate driver circuit 13 has a function of selecting the pixel PX that is the transmission destination of the image data in the display unit DSP, for example. Therefore, the gate driver circuit 13 is electrically connected to the pixel PX via the wiring GL.

[0082] The level shifter 14 has a function of converting the signal input to the source driver circuit 11, the digital-to-analog conversion circuit 12, the gate driver circuit 13, etc. to an appropriate level, for example.

[0083] The memory device 21 has a function of storing image data to be displayed on the display unit DSP as an example. Note that the memory device 21 can be configured to store the image data as digital data or analog data.

[0084] Also, when storing image data in the memory device 21, it is preferable that the memory device 21 is a non-volatile memory. In this case, for example, an NAND type memory or the like can be applied as the memory device 21.

[0085] Also, when storing temporary data generated by the GPU 22, the EL correction circuit 23, the CPU 25, etc. in the memory device 21, it is preferable that the memory device 21 is a volatile memory. In this case, for example, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), etc. can be applied as the memory device 21.

[0086] The GPU 22 has a function of performing processing for drawing the image data read from the memory device 21 on the display unit DSP as an example. In particular, since the GPU 22 is configured to perform pipeline processing in parallel, the image data to be displayed on the display unit DSP can be processed at high speed. Also, the GPU 22 can also have a function as a decoder for decoding the encoded image.

[0087] In addition, the functional circuit MFNC may include a plurality of circuits that can enhance the display quality of the display unit DSP. As such a circuit, for example, a correction circuit (color adjustment, light adjustment) may be provided that detects color unevenness in the image displayed on the display unit DSP and corrects the color unevenness to obtain an optimal image. Further, when a liquid crystal display device is applied to the pixels of the display unit DSP, a gamma correction circuit may be provided in the functional circuit MFNC. Further, when a light-emitting device using an organic EL is applied to the pixels of the display unit DSP, an EL correction circuit for correcting the variation in the luminance of the EL element may be provided in the functional circuit MFNC. In the present embodiment, since the pixels PX of the display unit DSP are described as being applied with a light-emitting device including an organic EL, the functional circuit MFNC includes, as an example, an EL correction circuit 23. As the organic EL included in the display unit DSP, for example, a structure (SBS, Side By Side structure) in which red (R), green (G), and blue (B) are independently provided, or a tandem structure (a structure in which a plurality of colors such as R, G, and B are connected in series via an intermediate layer (charge generation layer)), and a coloring layer (for example, a color filter) can be combined. By using a tandem structure, a light-emitting device capable of high-brightness emission can be obtained. The luminance of the light emitted from the display unit DSP can be, for example, 500 cd / m 2 or more, preferably 1000 cd / m 2 or more and 10000 cd / m 2 or less, more preferably 2000 cd / m 2 or more and 5000 cd / m 2 or less.

[0088] In addition, artificial intelligence may be used for the image correction described above. For example, the current flowing through the display device provided in the pixel (or the voltage applied to the display device) is monitored and acquired, the image displayed on the display unit DSP is acquired by an image sensor or the like, the current (or voltage) and the image are treated as input data for an artificial intelligence operation (for example, an artificial neural network or the like), and the output result may be used to determine whether or not the image needs to be corrected.

[0089] In addition, the operations of artificial intelligence can be applied not only to image correction but also to the up-conversion process of image data. By performing the up-conversion process on the image data with low resolution according to the resolution of the display unit DSP, a high-quality image can be displayed on the display unit DSP.

[0090] Note that the operations of artificial intelligence described above can be performed using the GPU22 included in the functional circuit MFNC. That is, various correction operations can be performed using the GPU22. Examples of the various correction operations include color unevenness correction and up-conversion. Also, as shown in FIG. 2, the GPU22 may be configured to include a circuit 22a for color unevenness correction and a circuit 22b for up-conversion.

[0091] In this specification and the like, the GPU that performs the operations of artificial intelligence is referred to as an AI accelerator. That is, in this specification and the like, the GPU provided in the functional circuit MFNC may be replaced with an AI accelerator for explanation.

[0092] As an example, the timing controller 24 has a function of increasing or decreasing the frame rate at which the display unit DSP displays an image. For example, when the display unit DSP is to display a still image, the display system 200 can be driven with the frame rate lowered by the timing controller 24. Also, for example, when the display unit DSP is to display a moving image, the display system 200 can be driven with the frame rate increased by the timing controller 24. That is, by providing the timing controller 24 in the display system 200, the frame rate can be changed according to whether it is a still image or a moving image. In particular, when the display unit DSP is to display a still image, since it can be operated with the frame rate lowered, the power consumption of the display system 200 can be reduced.

[0093] The CPU 25 has, for example, functions for performing general-purpose processes such as execution of an operating system, control of data, various calculations, and execution of programs. In the display system 200, the CPU 25 has a role of performing instructions such as, for example, a write operation or a read operation of image data in the storage device 21, a correction operation of image data, and an operation on a sensor described later. Further, for example, the CPU 25 may have a function of transmitting a control signal to one or two or more selected from the storage device 21, the GPU 22, the EL correction circuit 23, the timing controller 24, a high-frequency circuit, circuits included in the functional circuit MFNC, and the like.

[0094] Further, the CPU 25 may have a circuit for temporarily backing up data (hereinafter referred to as a backup circuit). The backup circuit preferably can hold the data even if the supply of the power voltage stops, for example. For example, when a still image is displayed on the display unit DSP, the CPU 25 can stop its function until an image different from the current still image is displayed. Therefore, by temporarily evacuating the data being processed in the CPU 25 to the backup circuit and then stopping the supply of the power voltage to the CPU 25 to stop the CPU 25, the dynamic power consumption in the CPU 25 can be reduced. In this specification and the like, a CPU having a backup circuit is referred to as a NoffCPU.

[0095] The sensor controller 26 has, for example, a function of controlling a sensor. In FIG. 2, a wiring SNCL is shown as a wiring for electrically connecting to the sensor.

[0096] The sensor can be, for example, a touch sensor provided above, below, or inside the display unit DSP.

[0097] In addition, as the sensor, for example, an illuminance sensor can be used. In particular, by obtaining the intensity of external light illuminating the display unit DSP with an illuminance sensor, the brightness (luminance) of the image displayed on the display unit DSP can be changed according to the external light. For example, when the external light is bright, the luminance of the image displayed on the display unit DSP can be increased to enhance the visibility of the image. Conversely, when the external light is dim, the luminance of the image displayed on the display unit DSP can be decreased to reduce power consumption.

[0098] As an example, the power supply circuit 27 has a function of generating a voltage to be supplied to circuits included in the peripheral circuit DRV, circuits included in the functional circuit MFNC, pixels included in the display unit DSP, and the like. Note that the power supply circuit 27 may have a function of selecting a circuit to which a voltage is to be supplied. For example, during a period when a still image is being displayed on the display unit DSP, the power supply circuit 27 can reduce the overall power consumption of the display system 200 by stopping the voltage supply to the CPU 25, GPU 22, and the like.

[0099] <Modification Example 1 of Display Device and Display System> By the way, in FIG. 1B, transistors included in the peripheral circuit DRV and the functional circuit MFNC are transistors formed on a semiconductor substrate. In the present embodiment, an example is shown in which transistors are formed on a semiconductor substrate made of silicon and the peripheral circuit DRV and the functional circuit MFNC include Si transistors. However, in a display device or a display system according to an aspect of the present invention, transistors having characteristics different from those of Si transistors can be applied to FIGS. 1A and 1B.

[0100] For example, a display device according to an aspect of the present invention may have a configuration (display device 100A) in which a layer OSC is formed between a circuit unit SIC and a display unit DSP as shown in FIG. 3A. Further, for example, a display system according to an aspect of the present invention may have a configuration (display system 200A) in which a layer OSC is formed between a circuit unit SIC and a display unit DSP as shown in FIG. 3B, similar to FIG. 3A.

[0101] The layer OSC can be configured to include, for example, OS transistors. The channel formation region of the OS transistor has the metal oxide described in Embodiment 4. The metal oxide can be, for example, one or a plurality of materials selected from indium, element M (aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc. In particular, by including a metal oxide composed of indium, gallium, and zinc in the semiconductor layer of the OS transistor, the bandgap of the semiconductor layer can be increased. Therefore, the off-current of the OS transistor can be reduced.

[0102] Since the OS transistor can be formed not only on a semiconductor substrate but also on an insulator substrate, a conductor substrate, and further on a conductive film, an insulating film, and a semiconductor film, it can be easily provided on a semiconductor substrate (on the circuit portion SIC) on which an Si transistor is formed.

[0103] In addition, the layer OSC may have circuit elements such as capacitors in addition to OS transistors. Also, the layer OSC may have a circuit inside.

[0104] By providing the layer OSC on the circuit portion SIC, the OS transistors included in the layer OSC can be used in the circuit formed by the circuit portion SIC. Therefore, in the circuit, the characteristic of the small off-current of the OS transistor can be utilized.

[0105] The OS transistors included in the layer OSC can be applied, for example, as switches for performing power gating. Specifically, for example, the switch can be provided in the circuits included in the peripheral circuit DRV and the functional circuit MFNC. When temporarily stopping the circuit, by turning off the switch, the supply of the power supply voltage from the power supply circuit 27 and the like to the circuit can be stopped.

[0106] The OS transistors included in the layer OSC can be applied, for example, as write transistors included in the memory cells of the memory device 21. By applying the OS transistors to the write transistors included in the memory cells, the leakage current (off-current) between the source and drain of the write transistors can be reduced, so that the data written in the memory cells can be retained for a long time. As a result, the interval of the refresh operation of the data held in the memory cells can be lengthened, and thus the power consumption of the display system 200 can be reduced.

[0107] Also, the layer OSC may be provided with a storage device for temporarily storing data handled by circuits included in the peripheral circuit DRV, circuits included in the functional circuit MFNC, and the like. For example, as shown in the block diagram of the display system 200A in FIG. 4, a storage device MDV may be provided in the layer OSC. Also, the storage device MDV shown in FIG. 4 shows an example in which a plurality of memory cells MC are arranged in a matrix. Also, as an example, the functional circuit MFNC of the display system 200A in FIG. 4 is provided with a memory control circuit 31 that performs operations such as writing, reading, and erasing data in the memory cell MC.

[0108] The memory control circuit 31 has, for example, a word line driver circuit, a bit line driver circuit, etc. for the memory cells MC included in the storage device MDV. Therefore, the memory cells MC included in the layer OSC and the memory control circuit 31 are electrically connected by the wiring ML.

[0109] <<Configuration Example 1 of Memory Cell>> Next, a circuit configuration example of a memory cell applicable to the memory cell MC will be described. For the memory cell MC, for example, a memory cell of a memory circuit called DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark) or NOSRAM (Dynamic Oxide Semiconductor Random Access Memory) (registered trademark) can be applied.

[0110] FIG. 5A shows an example of the circuit configuration of a DOSRAM memory cell. The memory cell MC1 has a transistor M1 and a capacitor CA. Note that the transistor M1 has a front gate (sometimes simply called a gate) and a back gate.

[0111] The first terminal of the transistor M1 is electrically connected to the first terminal of the capacitor CA, the second terminal of the transistor M1 is electrically connected to the wiring BIL, the gate of the transistor M1 is electrically connected to the wiring WOL, and the back gate of the transistor M1 is electrically connected to the wiring BGL. The second terminal of the capacitor CA is electrically connected to the wiring CVL.

[0112] The transistor M1 functions as a write transistor in the memory cell MC1. Also, as described above, the transistor M1 is, as an example, an OS transistor.

[0113] Also, the wiring BIL, the wiring WOL, the wiring CAL, and the wiring BGL correspond to the wiring ML in the display system 200A of FIG. 4.

[0114] The wiring BIL functions as a bit line as an example, and the wiring WOL functions as a word line as an example. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA as an example. Note that it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CVL during data writing and reading.

[0115] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0116] In the memory cell MC1 of FIG. 5A, the back gate of the transistor M1 is configured to be electrically connected to the wiring BGL. However, for the purpose of increasing the on-current of the transistor M1, the memory cell MC1 may be configured such that the gate and the back gate of the transistor M1 are electrically connected. Further, in the memory cell MC1 of FIG. 5A, the transistor M1 may not be provided with a back gate.

[0117] Writing and reading of data are performed by applying a high-level potential to the wiring WOL, turning on the transistor M1, and making the connection between the wiring BIL and the first terminal of the capacitor CA conductive.

[0118] Specifically, data writing is performed by applying a potential corresponding to the data to be written to the wiring BIL and writing the potential to the first terminal of the capacitor CA via the transistor M1. After data writing, a low-level potential is applied to the wiring WOL to turn off the transistor M1, so that the potential can be held in the memory cell MC1.

[0119] Also, for data reading, first, the wiring BIL is precharged to an appropriate potential, for example, a potential intermediate between a low-level potential and a high-level potential, and then the wiring BIL is electrically floated. Then, thereafter, a high-level potential is applied to the wiring WOL to turn on the transistor M1 and change the potential of the wiring BIL. Since the change in the potential of the wiring BIL is determined according to the potential written to the first terminal of the capacitor CA, the data held in the memory cell MC1 can be read from the changed potential of the wiring BIL.

[0120] Also, the memory cell MC1 described above is not limited to the circuit configuration shown in FIG. 5A, and the circuit configuration of the memory cell MC1 may be appropriately changed.

[0121] FIG. 5B shows an example of the circuit configuration of a memory cell of NOSRAM. The memory cell MC2 includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a front gate (which may be simply referred to as a gate) and a back gate.

[0122] The transistor M2 functions as a write transistor in the memory cell MC2. As described above, this write transistor is, for example, an OS transistor.

[0123] Also, the transistor M3 functions as a read transistor in the memory cell MC2. This read transistor is, as described above, an OS transistor. In this operation example, the transistor M3 operates in the saturation region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistor M3 are appropriately biased to voltages within the range of operating in the saturation region.

[0124] Incidentally, at least one of the transistor M2 and the transistor M3 may be a Si transistor. That is, a transistor that is to be a Si transistor included in the memory cell MC2 can be formed in the circuit portion SIC, and the remaining transistors included in the memory cell MC2 can be formed as OS transistors in the layer OSC.

[0125] The first terminal of transistor M2 is electrically connected to the first terminal of capacitor CB. The second terminal of transistor M2 is electrically connected to wiring WBL. The gate of transistor M2 is electrically connected to wiring WOL. The back gate of transistor M2 is electrically connected to wiring BGL. The second terminal of capacitor CB is electrically connected to wiring CAL. The first terminal of transistor M3 is electrically connected to wiring RBL. The second terminal of transistor M3 is electrically connected to wiring SOL. The gate of transistor M3 is electrically connected to the first terminal of capacitor CB.

[0126] Also, wiring RBL, wiring WBL, wiring WOL, wiring CAL, wiring BGL, and wiring SOL correspond to wiring ML in display system 200A of FIG. 4.

[0127] Wiring WBL functions as a write bit line. Wiring RBL functions as a read bit line. Wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitor CB. During data retention, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to wiring CAL. During data writing and data reading, it is preferable to apply a high-level potential to wiring CAL.

[0128] Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased. Similar to transistor M1 in FIG. 5A, transistor M2 may be configured such that the gate and the back gate of transistor M2 are electrically connected, or may be configured without a back gate.

[0129] Data writing is performed by applying a high-level potential to wiring WOL, turning on transistor M2, and making the connection between wiring WBL and the first terminal of capacitor CB conductive. Specifically, when transistor M2 is in the on state, a potential corresponding to the information to be recorded is applied to wiring WBL, and this potential is written to the first terminal of capacitor CB and the gate of transistor M3. Thereafter, by applying a low-level potential to wiring WOL and turning off transistor M2, the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3 are retained.

[0130] Data reading is performed by applying a predetermined potential to wiring SOL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3, the potential of wiring RBL electrically connected to the first terminal of transistor M3 is read, whereby the potential held at the first terminal of capacitor CB (or the gate of transistor M3) can be read. That is, the information written in this memory cell can be read from the potential held at the first terminal of capacitor CB (or the gate of transistor M3).

[0131] Also, the memory cell MC2 described above is not limited to the circuit configuration shown in FIG. 5B, and the circuit configuration of the memory cell MC2 may be appropriately changed. For example, a configuration in which wiring WBL and wiring RBL are combined into a single wiring BIL may be used. A circuit configuration example of such a memory cell is shown in FIG. 5C. Memory cell MC2A has a configuration in which wiring WBL and wiring RBL of memory cell MC2 are a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to wiring BIL. That is, memory cell MC2A has a configuration in which it operates with a single wiring BIL as both the write bit line and the read bit line.

[0132] <<Example Configuration of Memory Cell 2>> In addition, as memory cells of a memory circuit other than DOSRAM and NOSRAM that can be applied to the memory cell MC of the layer OSC, for example, MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), phase change memory (sometimes referred to as PCM, PRAM, etc.), and ferroelectric memory can be mentioned. The circuit configurations of these will be described below.

[0133] The memory cell MC3 shown in FIG. 5D is an example of STT-MRAM (Spin Transfer Torque-Magnetoresistive Random Access Memory).

[0134] The memory cell MC3 includes a transistor M10 and an MTJ (magnetic tunnel junction) element ME.

[0135] As the transistor M10, for example, an OS transistor can be applied in the same manner as the transistors M1 and M2.

[0136] The MTJ element ME includes a layer FL having a free layer, a layer TIS having a tunnel insulator, and a layer RL having a fixed layer, and the layer FL and the layer RL overlap via the layer TIS.

[0137] The first terminal of the transistor M10 is electrically connected to the layer RL of the MTJ element ME, the second terminal of the transistor M10 is electrically connected to the wiring SL, and the gate of the transistor M10 is electrically connected to the wiring WL. The layer FL of the MTJ element ME is electrically connected to the wiring BL.

[0138] Also, the wiring BL, the wiring WL, and the wiring SL correspond to the wiring ML in the display system 200A of FIG. 4.

[0139] The wiring BL functions as a write bit line or a read bit line for the memory cell MC3 as an example.

[0140] The wiring WL functions as a word line for the memory cell MC3 as an example.

[0141] The wiring SL functions as a wiring for applying a fixed voltage as an example. As the fixed voltage, for example, a low-level potential can be used.

[0142] Although not shown in the drawings, not only STT-MRAM but also SOT-MRAM (Spin Orbit Torque-Magnetoresistive Random Access Memory) can be applied to the memory cell MC in the layer OSC.

[0143] The memory cell MC4 shown in FIG. 5E is an example of ReRAM (Resistive Random Access Memory).

[0144] The memory cell MC4 includes a transistor M10 and a resistance change element RM.

[0145] As the transistor M10, for example, an OS transistor can be applied in the same manner as the transistors M1 and M2.

[0146] As shown in FIG. 5E, the memory cell MC4 has a configuration in which the MTJ element ME of the memory cell MC3 in FIG. 5D is replaced with a resistance change element RM. In the memory cell MC in FIG. 5E, it is assumed that the first terminal of the resistance change element RM is electrically connected to the first terminal of the transistor M10, and the second terminal of the resistance change element RM is electrically connected to the wiring BL.

[0147] Also, the wiring BL, the wiring WL, and the wiring SL correspond to the wiring ML in the display system 200A of FIG. 4.

[0148] The wiring BL functions as a write bit line or a read bit line for the memory cell MC4 as an example.

[0149] The wiring WL functions as a word line for the memory cell MC4 as an example.

[0150] The wiring SL functions as a wiring for applying a constant voltage as an example. As the constant voltage, for example, a reference potential can be used.

[0151] The memory cell MC5 shown in FIG. 5F is an example of a memory circuit having a phase change memory.

[0152] The memory cell MC5 has a transistor M10 and a phase change memory PCM1.

[0153] As the transistor M10, for example, an OS transistor can be applied in the same manner as the transistor M1 and the transistor M2.

[0154] The phase change memory PCM1 has, as an example, an electrode TE, a phase change layer CHL, and an electrode BE, and is electrically connected in the order of the electrode TE, the phase change layer CHL, and the electrode BE.

[0155] Further, as the phase change layer CHL, for example, chalcogenide glass can be applied. In the present embodiment, the phase change layer CHL will be described as being made of chalcogenide glass.

[0156] It is preferable that the areas of contact between the electrode TE and the phase change layer CHL and between the electrode BE and the phase change layer CHL are different from each other. For example, in FIG. 5F, the contact area between the electrode TE and the phase change layer CHL is shown to be larger than the contact area between the electrode BE and the phase change layer CHL. By reducing the contact area between the electrode BE and the phase change layer CHL, heat can be locally applied to the phase change layer CHL, so that a phase change is more likely to occur in the phase change layer CHL near the electrode BE than in the phase change layer CHL near the electrode TE.

[0157] As shown in FIG. 5F, the memory cell MC5 has a configuration in which the MTJ element ME of the memory cell MC3 in FIG. 5D is replaced with the phase change memory PCM1. In the memory cell MC of FIG. 5F, it is assumed that the electrode BE of the phase change memory PCM1 is electrically connected to the first terminal of the transistor M10, and the electrode TE of the phase change memory PCM1 is electrically connected to the wiring BL.

[0158] Also, the wiring BL, the wiring WL, and the wiring SL correspond to the wiring ML in the display system 200A of FIG. 4.

[0159] The wiring BL functions as a write bit line or a read bit line for the memory cell MC5 as an example.

[0160] The wiring WL functions as a word line for the memory cell MC5 as an example.

[0161] The wiring SL functions as a wiring for applying a constant voltage as an example. As the constant voltage, for example, a low level potential can be used.

[0162] The memory cell MC6 shown in FIG. 5G is an example of a FeRAM (Ferroelectric Random Access Memory).

[0163] The memory cell MC6 includes a transistor M11 and a ferroelectric capacitor FEA.

[0164] As the transistor M11, for example, an OS transistor can be applied in the same manner as the transistors M1 and M2.

[0165] The first terminal of the transistor M11 is electrically connected to the wiring BL, the second terminal of the transistor M11 is electrically connected to the first terminal of the ferroelectric capacitor FEA, and the gate of the transistor M11 is electrically connected to the wiring WL. Also, the second terminal of the ferroelectric capacitor FEA is electrically connected to the wiring FCA.

[0166] Also, the wiring BL, wiring WL, and wiring FCA correspond to the wiring ML in the display system 200A of FIG. 4.

[0167] As an example, the wiring BL functions as a wiring for transmitting data written to the memory cell MC6.

[0168] As an example, the wiring WL functions as a wiring for selecting the memory cell MC6 to which data is to be written.

[0169] As an example, when writing data to the memory cell MC6, the wiring FCA functions as a wiring for applying a variable potential that causes polarization in a ferroelectric material included in the ferroelectric capacitor FEA.

[0170] Here, a ferroelectric material included in the ferroelectric capacitor FEA will be described.

[0171] As the ferroelectric material, it is preferably hafnium oxide, for example. Also, when hafnium oxide is used as the dielectric included in the ferroelectric capacitor FEA, the film thickness of hafnium oxide is preferably 10 nm or less, more preferably 5 nm or less, and even more preferably 2 nm or less.

[0172] Alternatively, as the ferroelectric material, other than hafnium oxide, zirconium oxide, hafnium zirconium oxide (HfZrO X(Let X be a real number greater than 0)) Metal oxides such as these can be mentioned. Or, as a material that can have ferroelectricity, there is a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of atoms of element J1 can be set as appropriate. For example, the number of hafnium atoms and the number of atoms of element J1 may be 1:1 or in the vicinity thereof. Or, as a material that can have ferroelectricity, there are materials such as those obtained by adding element J2 (here, element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set as appropriate. For example, the number of zirconium atoms and the number of atoms of element J2 may be 1:1 or in the vicinity thereof. Also, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate, etc. may be used.

[0173] Also, as a material that can have ferroelectricity, aluminum scandium nitride (Al 1-a Sc a N b(a is a real number greater than 0 and less than 0.5, and b is a value of 1 or in its vicinity.), Al-Ga-Sc nitride, Ga-Sc nitride, etc. can be mentioned. Further, examples of materials that can have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen. Here, element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Also, element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. Note that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Also, a metal oxide having element M1 and nitrogen may have ferroelectricity even if it does not contain element M2. Further, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitride. Note that element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate. Note that since the above metal nitride contains at least a Group 13 element and nitrogen which is a Group 15 element, the metal nitride may be called a ferroelectric of Group III-V, a ferroelectric of Group III nitride, etc.

[0174] Further, examples of materials that can have ferroelectricity include perovskite oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 having a κ-alumina type structure.

[0175] In addition, as a material that may have ferroelectricity, for example, it can be a mixture or compound composed of a plurality of materials selected from the materials listed above. Alternatively, as a material that may have ferroelectricity, it can be a laminated structure composed of a plurality of materials selected from the materials listed above. By the way, materials such as those listed above may change in crystal structure (characteristics) not only depending on film formation conditions but also by various processes. Therefore, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric, but also a material that may have ferroelectricity or a material that can be made to have ferroelectricity. In addition, ferroelectrics shall include not only materials that exhibit ferroelectricity but also materials that may have ferroelectricity.

[0176] Among them, as a material that may have ferroelectricity, hafnium oxide or a material having hafnium oxide and zirconium oxide is preferable because it can have ferroelectricity even when processed into a thin film of several nm. Here, the film thickness of the material that may have ferroelectricity can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm or more and 9 nm or less). For example, it is preferable to make the film thickness 8 nm or more and 12 nm or less. By forming a ferroelectric layer that can be thinned, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and a semiconductor device can be formed by combining the capacitive element with a semiconductor element such as a miniaturized transistor. In this specification and the like, a material that may have ferroelectricity formed into a layer may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification and the like.

[0177] In addition, as a material that may have ferroelectricity, HfZrO XWhen using this method, it is preferable to form a film using the atomic layer deposition (ALD) method, particularly the thermal ALD method. Further, when forming a film of a material that can have ferroelectricity using the thermal ALD method, it is suitable to use a material that does not contain hydrocarbon (also referred to as HC) as a precursor. When either one or both of hydrogen and carbon are contained in a material that can have ferroelectricity, it may inhibit the crystallization of the material that can have ferroelectricity. For this reason, as described above, by using a precursor that does not contain hydrocarbon, it is preferable to reduce the concentration of either one or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be given as a precursor that does not contain hydrocarbon. In addition, when using a material having hafnium oxide and zirconium oxide (HfZrO x ) as a material that can have ferroelectricity, at least one of HfCl4 and ZrCl4 may be used as a precursor.

[0178] In addition, when forming a film using a material that can have ferroelectricity, by thoroughly removing impurities in the film, here at least one or more of hydrogen, hydrocarbon, and carbon, a film having high-purity genuine ferroelectricity can be formed. Note that the film having high-purity genuine ferroelectricity and the high-purity genuine oxide semiconductor shown in the embodiments described later have very high manufacturing process compatibility. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0179] In addition, when using HfZrO as a material that can have ferroelectricity X it is preferable to alternately form hafnium oxide and zirconium oxide in a composition of 1:1 using the thermal ALD method.

[0180] In addition, when forming a film of a material that can have ferroelectricity using the thermal ALD method, H2O or O3 can be used as an oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, the oxidizing agent for the thermal ALD method may contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0181] Also, the crystal structure of the material that can have ferroelectricity is not particularly limited. For example, as the crystal structure of the material that can have ferroelectricity, any one or more selected from the cubic system, tetragonal system, orthorhombic system, and monoclinic system may be used. In particular, as the material that can have ferroelectricity, having an orthorhombic crystal structure is preferable because ferroelectricity is exhibited. Alternatively, as the material that can have ferroelectricity, a composite structure having an amorphous structure and a crystal structure may also be used.

[0182] In the memory cell MC6 of FIG. 5G, although the FeRAM using the ferroelectric capacitor FEA has been described as an example, as the memory cell MC applicable to the layer OSC, a memory cell using an FTJ (Ferroelectric Tunnel Junction, or Ferroelectric Transportation Junction) element and / or a FeFET (Ferroelectric FET) may be used (not shown).

[0183] As described above, by configuring the display device, that is, by providing the peripheral circuit DRV below the display unit DSP, the routing of the wiring between the display unit DSP and the peripheral circuit DRV can be made shorter than before, so the time required for transmitting image data and the like can be shortened. Also, since the length of the wiring can be made shorter than before, the power consumption of the display device can be reduced.

[0184] Moreover, by providing a layer OSC between the display unit DSP and the circuit unit SIC, the influence of the heat generated in the circuit unit SIC on the display unit DSP can be mitigated. In particular, when the display elements included in the display unit DSP have low resistance to heat, by adopting the configurations shown in FIGS. 3A, 3B, 4, etc., the lifespan of the display elements included in the display unit DSP can be extended. Also, by providing a cooling mechanism below the circuit unit SIC, the influence of the heat generated in the circuit unit SIC can be reduced (not shown). Examples of such a cooling mechanism include a heat sink using a material with high thermal conductivity, a water-cooled heat sink using cooling water, a fan, etc.

[0185] <Modification Example 2 of Display Device and Display System> Also, in FIG. 4, an example is shown in which a storage device MDV is provided in the layer OSC between the circuit unit SIC and the display unit DSP. However, in the layer OSC, circuits, devices, etc. other than the storage device may be provided. For example, a part of the circuits included in the peripheral circuit DRV and / or the functional circuit MFNC may be formed in the layer OSC.

[0186] The display system 200B in FIG. 6 shows an example in which a part of the circuits of the peripheral circuit DRV in the display system 200A in FIG. 4 is formed in the layer OSC. Note that in FIG. 6, there is a part where the wiring SL and the wiring GL intersect, but the two wirings are not directly connected to each other.

[0187] The display system 200B in FIG. 6 shows an example in which a part of the peripheral circuit DRV in the display system 200A in FIG. 4 is formed in the circuit unit SIC as the circuit DRVa, and the remainder of the peripheral circuit DRV in the display system 200A in FIG. 4 is formed in the layer OSC as the circuit DRVb. Specifically, the display system 200B has a configuration in which the circuit DRVa includes a source driver circuit 11 and a digital-to-analog conversion circuit 12, and the circuit DRVb includes a gate driver circuit 13 and a level shifter 14.

[0188] The OS transistor has higher electrical resistance than the Si transistor. Therefore, by using the OS transistor for the transistor formed in the layer OSC, the circuits included in the layer OSC (for example, the gate driver circuit 13, the level shifter 14, etc.) can obtain high resistance against voltage. For this reason, by forming the said circuit in the layer OSC, the electrical load applied to the said circuit can be reduced.

[0189] <Modification Example 3 of Display Device and Display System> Although the display system 200 shown in FIG. 1B has a configuration in which the peripheral circuit DRV and the functional circuit MFNC are included in the circuit section SIC, the display system according to one aspect of the present invention has a configuration in which the functional circuit MFNC is provided in the circuit section SIC, and the driving of the display section DSP may be performed by an external circuit of the display system 200.

[0190] For example, the display system according to one aspect of the present invention can have the configuration shown in FIG. 7A. The display system 200C has a display section DSP and a circuit section SIC, and the circuit section SIC has a functional circuit MFNC. Further, the display section DSP is electrically connected to the circuit section CHP, and the circuit section CHP has a peripheral circuit DRV. The circuit section CHP can be, for example, an external driver IC.

[0191] In addition, as a method of mounting the circuit section CHP on the display system 200C, for example, there are a COG (Chip On Glass) method, a COF (Chip On Film) method, and the like.

[0192] In the display system 200C, the transistors included in the display section DSP and the circuit section SIC can be, for example, Si transistors. In addition to Si transistors, OS transistors may also be used.

[0193] Further, the display system 200C may have a configuration in which the circuit section CHP and the circuit section SIC are electrically connected, as shown in FIG. 7B, instead of a configuration in which the circuit section CHP and the display section DSP are electrically connected.

[0194] Further, an example of the specific configuration of the display system 200C shown in FIG. 7A or FIG. 7B is shown in FIG. 8. Note that in FIG. 8, the bus wiring BSL of the functional circuit MFNC included in the display system 200C and the bus wiring of the circuit section CHP are electrically connected.

[0195] As described above, in the display system 200 of FIG. 1B, the peripheral circuit DRV for driving the display unit DSP may be provided outside the display system 200 as a driver IC or the like, instead of being provided in the circuit section SIC.

[0196] As described in this embodiment, by configuring a display device or a display system, that is, by providing the peripheral circuit DRV and the functional circuit MFNC below the display unit DSP, in addition to reducing the transmission time of image data and power consumption, a correction circuit, a GPU, etc. can also be provided without increasing the circuit area. Thereby, the display quality of the display unit DSP can be improved. Also, since the circuit area does not increase, it becomes less likely to be restricted by the size etc. in the housing of the electronic device described in later embodiments.

[0197] By the way, in a conventional display device (for example, a display device using Si transistors), the pixel array and the peripheral circuit are provided on the same plane. However, by applying an OS transistor to the transistors of the display device, miniaturization of the pixel circuit and the peripheral circuit becomes possible. Thereby, the area of the pixel circuit and the peripheral portion (sometimes called a frame) of the pixel circuit can be reduced. For example, in a conventional display device for XR (for example, a display device using Si transistors), the resolution is generally 3000 ppi or less, but by applying an OS transistor to the display device for XR, a resolution of 5000 ppi or more can be realized.

[0198] Also, consider the luminance of the light-emitting device when an organic EL-containing light-emitting device is used for the pixels of the display device. When a constant current source is configured with an Si transistor, since the Si transistor has a low breakdown voltage, realistically, in a display device with 3000 ppi, only up to 2 the following luminance can be output. On the other hand, when a constant current source is configured with an OS transistor, since the OS transistor has a high breakdown voltage, for example, in a display device with 5000 ppi or more and 7000 ppi or less, generally up to 2 the luminance before and after can be output.

[0199] Also, for example, in the display system 200 of FIG. 1B, when the semiconductor substrate of the circuit section SIC is silicon, the system (interface, converter, driver, memory, CPU, GPU) can be incorporated with a technology node of 6 nm to 7 nm. Thereby, the area of the circuit constituting the display system 200 can be reduced.

[0200] As described above, the contents of the display system using an Si transistor or OSLSI are summarized in the following table. In this specification, etc., OSLSI refers to an integrated circuit in which an OS transistor is further formed above the Si transistors formed on a semiconductor substrate.

[0201] [Table 1]

[0202] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0203] (Embodiment 2) In this embodiment, the configuration of a display system including a high-frequency (RF) circuit will be described.

[0204] FIG. 9A is a diagram schematically showing a display system according to an aspect of the present invention. The display system 200D shown in FIG. 9A is configured such that a high-frequency circuit 41 is provided in a functional circuit MFNC included in a circuit section SIC of the display system 200 of FIG. 1B. Note that FIG. 9A also shows a device EXDV that performs wireless communication with the high-frequency circuit 41.

[0205] In addition, in the present embodiment, although the display system 200D and the device EXDV are separately described, the display system according to an aspect of the present invention can include an external device that performs wireless communication with the display system. That is, the display system according to an aspect of the present invention may include the device EXDV.

[0206] The high-frequency circuit 41 includes, for example, an antenna, a duplexer, a low-noise amplifier, a power amplifier, a local oscillator, a down-conversion mixer, an up-conversion mixer, a band-pass filter, an analog-to-digital conversion circuit, and the like.

[0207] In particular, since the high-frequency circuit 41 has a duplexer, the RF signal path for transmission and the RF signal path for reception can be electrically separated. Therefore, the antenna provided in the high-frequency circuit 41 can be a single antenna that is shared by the transmission antenna and the reception antenna. Thereby, the circuit board area of the display system 200D can be further reduced.

[0208] In the present embodiment, the high-frequency circuit 41 has a function of converting an electrical signal generated by any one of the circuits (for example, a CPU, a GPU, a storage device, etc.) included in the first layer into an RF signal and transmitting it to the outside of the display system 200D. Further, the high-frequency circuit 41 has a function of converting an RF signal acquired from the outside into an electrical signal and transmitting it to any one of the circuits (for example, a CPU, a GPU, a storage device, etc.) included in the first layer.

[0209] Note that various electronic devices and the like can be applied as the device EXDV. For example, when the device EXDV exists outside the housing provided in the display system 200D, the device EXDV can be, for example, a speaker (including earphones, headphones, etc.), a portable information terminal such as a smartphone, a wearable information terminal, a tablet-type information terminal, a desktop-type information terminal, a server, an electronic device such as an IoT (Internet of Things)-equipped device, and the like.

[0210] For example, as shown in FIG. 10, the display system 200D may be used as the display unit of an electronic device HMD that is a head-mounted display, and the device EXDV may be the device EXDV1 that is a server existing on the cloud computing CLD. Further, the device EXDV may be the device EXDV2 that is a portable information terminal (for example, a smartphone, etc.). Further, the device EXDV may be the device EXDV3 that is a wearable information terminal.

[0211] By providing the high-frequency circuit 41 in the functional circuit MFNC of the display system 200D, as shown in FIG. 10, wireless communication can be performed with electronic devices such as a server, a portable information terminal, and a wearable information terminal. Thereby, the image data transmitted from the device EXDV1, the device EXDV2, etc. can be received by the high-frequency circuit 41 of the display system 200D of the electronic device HMD, and the image data can be displayed on the display unit DSP of the display system 200D.

[0212] Furthermore, the information communicated between the display system 200D and the device EXDV is not limited to image data. For example, as shown in FIG. 11A, a user wearing the electronic device HMD (which may also be a person not wearing the electronic device HMD) may use the finger FG to use the device EXDV2 or the device EXDV3 as an input interface to transmit an RF signal for operating the display system 200D from the device EXDV2 or the device EXDV3 to the display system 200D. At this time, the display unit of the device EXDV2 or the device EXDV3 may be set to a non-display state, and on the display unit DSP of the display system 200D of the electronic device HMD, an image that would originally be displayed on the display unit of the device EXDV2 or the device EXDV3 by AR may be displayed so as to be superimposed. Specifically, as an example, as shown in FIG. 11A, the display unit of the device EXDV2 or the device EXDV3 actually operated by the finger FG is in a non-display state, and on the display unit DSP of the display system 200D of the electronic device HMD, a display image DPC such that an operation screen is projected on the device EXDV2 or the device EXDV3 may be displayed.

[0213] Also, for example, as shown in FIG. 11B, a user wearing the electronic device HMD may transmit an RF signal for operating the device EXDV2 or the device EXDV3 from the electronic device HMD to the device EXDV2 or the device EXDV3 by moving their own hand HND. At this time, it is preferable that the electronic device HMD includes an imaging device, an infrared sensor, etc. for recognizing the movement of the hand HND. Further, a sensor device for recognizing movement may be worn on the hand HND (including fingers FG, wrist, etc.), and the electronic device HMD may recognize the movement of the hand HND by receiving sensing information from the sensor device. Thereby, even when the device EXDV2 or the device EXDV3 is away from the user wearing the electronic device HMD, the user can operate the device EXDV2 or the device EXDV3. Specifically, for example, as shown in FIG. 11B, the display unit DSP of the display system 200D of the electronic device HMD can display a display image DPC in which the external scenery of the electronic device HMD, the operation area OPA, and the icon ICN within the operation area OPA are synthesized. At this time, by performing an operation with a gesture such as touching the icon ICN with the hand HND (finger FG in FIG. 11B), the device EXDV2 or the device EXDV3 can be remotely operated.

[0214] Also, in the case of FIG. 11A or FIG. 11B, as the image projected on the display unit DSP of the display system 200D of the electronic device HMD, it may be an image that the device EXDV2 or the device EXDV3 originally displays instead of the external scenery of the electronic device HMD. Further, it is preferable that the image is displayed in 4K2K, more preferably in 8K4K, and even more preferably in 16K8K.

[0215] In addition, the communication between the display system 200D and the device EXDV may be performed via a wireless repeater. Thereby, the display system 200D can communicate not only with electronic devices existing near the display system 200D but also with electronic devices existing at a distance. Also, in this case, in order to transmit large-capacity data, shorten the delay time, and increase the communication speed, it is preferable to use the communication standard of the fifth generation (5G). Note that in 5G (the fifth-generation mobile communication system), for example, communication frequencies such as the 3.7 GHz band, 4.5 GHz band, and 28 GHz band are used.

[0216] Since semiconductor devices corresponding to 5G are often manufactured using a semiconductor mainly composed of one type of element such as silicon, as in the display system 200D of FIG. 9A, the high-frequency circuit 41 included in the functional circuit MFNC can be manufactured on the semiconductor substrate (particularly a semiconductor substrate made of silicon) of the circuit section SIC.

[0217] Also, when the device EXDV is provided not outside the housing of the display system 200D but in the same housing as the display system 200D, the device EXDV may be, for example, a part of the circuits included in the functional circuit MFNC of the display system 200 of FIG. 1B.

[0218] Specifically, as shown in FIG. 9B, a part of the circuits of the functional circuit MFNC may be provided on the circuit section SIC side as the functional circuit MFNCa, and the remaining circuits of the functional circuit MFNC may be provided in the device EXDV as the functional circuit MFNCb. Also, in FIG. 9B, a high-frequency circuit 41a is provided in the functional circuit MFNCa, and a high-frequency circuit 41b is provided in the functional circuit MFNCb, and an example in which the high-frequency circuit 41a and the high-frequency circuit 41b perform wireless communication is shown. Note that in FIG. 9B, the functional circuit MFNCa and the functional circuit MFNCb are collectively referred to as the functional circuit MFNC. That is, a configuration is adopted in which wireless communication is performed inside the functional circuit MFNC shown in FIG. 9B.

[0219] By applying the configuration of the display system 200D shown in FIG. 9B, wireless communication can be performed inside the functional circuit MFNC. As a result, there is no need to provide wiring for transmitting and receiving electrical signals between the functional circuit MFNCa and the functional circuit MFNCb, so the circuit area inside the housing can be reduced.

[0220] As an example where the configuration of FIG. 9B can be applied, there is a configuration of a head-mounted display and headphones attached thereto. Specifically, as shown in FIG. 12, the display system 200D is applied to the display unit of the electronic device HMD which is a head-mounted display, and the device EXDV is applied to the headphone unit HP, and audio data is transmitted wirelessly from the high-frequency circuit 41a to the high-frequency circuit 41b, so that the headphones having the device EXDV can reproduce the audio data in accordance with the image projected on the display unit.

[0221] Also, an example of a specific configuration of the display system 200D shown in FIG. 9A or FIG. 9B is shown in FIG. 13. As shown in FIG. 13, the high-frequency circuit 41 is electrically connected to the bus wiring BSL, and the high-frequency circuit 41 can convert the RF signal RFS into an electrical signal and transmit it to a predetermined circuit such as the CPU 25, and can also convert an electrical signal from a predetermined circuit such as the CPU 25 into the RF signal RFS and transmit it to the device EXDV.

[0222] Note that FIGS. 9A, 9B, and 13 described in this embodiment have been described as an example in which the high-frequency circuit 41 is provided in the functional circuit MFNC of the circuit unit SIC of the display system 200 in FIG. 1, but one aspect of the present invention is not limited thereto. For example, one aspect of the present invention may be configured such that the high-frequency circuit 41 is provided in the functional circuit MFNC of the circuit unit SIC of the display system 200A in FIG. 3 (not shown).

[0223] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0224] (Embodiment 3) In this embodiment, the configuration of the display device or the display system described in the above embodiment will be described.

[0225] FIG. 14A is a cross-sectional view showing a configuration example of the display device shown in FIG. 1A or the display system shown in FIGS. 1B and 2. Note that in the display system in FIG. 14A, the circuit section SIC includes the transistor 170, and the display section DSP includes the transistor 180, the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B. In this specification, the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B are collectively referred to as the light-emitting device 260. FIG. 14A shows a cross-sectional view of the transistor 170 and the transistor 180 in the channel length direction.

[0226] The transistor 170 is provided on the substrate 101 and has an element isolation layer 171, a conductor 175, an insulator 174, a semiconductor region 173 formed of a part of the substrate 101, a low-resistance region 172a that functions as a source region or a drain region, and a low-resistance region 172b. Note that the transistor 170 can be applied to, for example, the source driver circuit 11 or the gate driver circuit 13 included in the peripheral circuit DRV described in the above embodiment. Further, for example, the transistor 170 can be applied to the storage device 21, the GPU 22, etc. included in the functional circuit MFNC.

[0227] Further, as the substrate 101, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0228] As an example, in the transistor 170, the upper surface and the side surface in the channel width direction of the semiconductor region 173 are covered with the conductor 175 via the insulator 174. By forming the transistor 170 in a Fin type in this manner, the effective channel width can be increased, and thus the on characteristics of the transistor 170 can be improved. Further, since the contribution of the electric field of the gate electrode can be increased, the off characteristics of the transistor 170 can be improved.

[0229] Note that the transistor 170 may be either a p-channel type or an n-channel type.

[0230] In the region where the channel of the semiconductor region 173 is formed, the region in the vicinity thereof, the source region, or the drain region, it is preferable to include a semiconductor such as a silicon-based semiconductor, and it is preferable to include single-crystalline silicon. Alternatively, it may be formed of a material having Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs or the like, the transistor 170 may be a HEMT (High Electron Mobility Transistor).

[0231] The conductor 175 that functions as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon containing an element that imparts n-type conductivity such as arsenic or phosphorus, or an element that imparts p-type conductivity such as boron, a metal material, an alloy material, or a metal oxide material.

[0232] Note that since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embedding properties, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

[0233] The element isolation layer 171 is provided to isolate a plurality of transistors formed on the substrate 101. The element isolation layer 171 can be formed using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, the mesa isolation method, or the like.

[0234] Note that the transistor 170 shown in FIG. 14A is an example, and is not limited to its structure. An appropriate transistor may be used according to the circuit configuration, driving method, and the like. For example, the transistor 170 may have a planar structure instead of a FIN type.

[0235] An insulator 116, an insulator 117, and an insulator 118 are sequentially stacked on the transistor 170 shown in FIG. 14A.

[0236] As the insulator 116 and the insulator 117, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used.

[0237] Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition. Also, in this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen in its composition.

[0238] The insulator 117 may function as a planarization film that planarizes steps generated by the transistor 170 and the like covered by the insulator 116 and the insulator 117. For example, the upper surface of the insulator 117 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0239] In addition, for the insulator 118, it is preferable to use a film having a barrier property such that hydrogen, impurities, etc. do not diffuse from the substrate 101, the transistor 170, etc. into the region above the insulator 118.

[0240] As an example of a film having a barrier property against hydrogen, silicon nitride formed by CVD method can be used. Here, when hydrogen diffuses into the circuit elements provided above the insulator 118, the characteristics of the circuit elements may deteriorate. Therefore, it is preferable to use a film that suppresses the diffusion of hydrogen between the circuit elements and the transistor 170. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

[0241] The amount of hydrogen desorption can be analyzed using, for example, temperature-programmed desorption gas analysis method (TDS). For example, the amount of hydrogen desorption of the insulator 118 is such that in the TDS analysis, in the range where the surface temperature of the film is from 50°C to 500°C, the desorption amount converted to hydrogen atoms, when converted per unit area of the insulator 118, is 10×10 15 atoms / cm 2 Hereinafter, preferably 5×10 15 atoms / cm 2 or less is sufficient.

[0242] Note that the insulator 118 preferably has a lower dielectric constant than the insulator 117. For example, the relative dielectric constant of the insulator 118 is preferably less than 4, more preferably less than 3. Also, for example, the relative dielectric constant of the insulator 118 is preferably 0.7 times or less, more preferably 0.6 times or less, of the relative dielectric constant of the insulator 117. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0243] In addition, conductors 126 and the like that connect to circuit elements (for example, transistors 180 included in the display DSP, light-emitting devices 260R to 260B, etc.) provided above the insulator 118 are embedded in the insulators 116, 117, and 118. Note that the conductor 126 has functions as a plug or a wiring. In addition, conductors having functions as plugs or wirings may be collectively given the same reference numeral in some cases. In this specification and the like, a wiring and a plug connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

[0244] As materials for each plug and wiring (conductors 126, conductor 127 to be described later, conductor 128, etc.), conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used singly or in a stacked manner. It is preferable to use high melting point materials such as tungsten and molybdenum that achieve both heat resistance and conductivity, and it is more preferable to use tungsten. Alternatively, it is preferable to form with a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0245] Note that a wiring layer may be provided in an upper layer than the insulator 118 (not shown).

[0246] In FIG. 14A, an insulator 221 is laminated above the insulator 118. The insulator 221 functions as a base film of the transistor 180.

[0247] In addition, a gate electrode of the transistor 180 or a conductor 211 that functions as a wiring is formed on the insulator 221.

[0248] In addition, an insulator 222 that functions as a gate insulating film of the transistor 180 is formed on the insulator 221 and on the conductor 211.

[0249] In addition, conductors 127 and the like for connecting to the transistor 180 and circuit elements included in the circuit section SIC are embedded in the insulators 221 and 222. Note that the conductor 127 has a function as a plug or wiring.

[0250] In addition, a semiconductor 231 is formed on the insulator 222. In FIG. 14A, the semiconductor 231 is formed to include a region overlapping with the conductor 211.

[0251] As the semiconductor 231, for example, the metal oxide described in Embodiment 4 can be applied. In addition, as the semiconductor 231, for example, semiconductor materials such as Si and Ge can be applied. Further, as the semiconductor 231, for example, compound semiconductors such as ZnSe, CdS, GaAs, InP, GaN, and SiGe can be used. Further, as the semiconductor 231, for example, carbon nanotubes and organic semiconductors can be used.

[0252] In addition, a conductor 212 is formed on the insulator 222, on the conductor 127, and on the semiconductor 231. Note that the conductor 212 is formed as a pair so as to pass through the semiconductor 231. One of the pair of conductors 212 functions as one of the source or drain of the transistor 180, and the other of the pair of conductors 212 functions as the other of the source or drain of the transistor 180. In FIG. 14A, one of the pair of conductors 212 is formed so as to be electrically connected to the conductor 127.

[0253] Note that FIG. 14A shows an example in which the conductor 127 is electrically connected to one of the source or drain of the transistor 180, but the conductor 127 may be electrically connected to the other of the source or drain of the transistor 180, or may be electrically connected to the gate of the transistor 180.

[0254] An insulator 223 and an insulator 224 are sequentially formed on the insulator 222, on the conductor 212, and on the semiconductor 231.

[0255] Next, the light-emitting devices 260R, 260G, and 260B that can be provided on the insulator 224 will be described. Each light-emitting device preferably emits a different color. In the present embodiment, as an example, the light-emitting device 260R exhibits red, the light-emitting device 260G exhibits green, and the light-emitting device 260B exhibits blue. Also, in order to simplify the distinction between the light-emitting devices, the symbols R, G, and B are attached to the light-emitting regions of the respective light-emitting devices.

[0256] An insulator 251 is formed on the insulator 224.

[0257] In addition, conductors 128 and the like for connecting to the transistor 180 and circuit elements included in the circuit unit SIC are embedded in the insulator 224 and the insulator 251. Note that the conductor 128 has a function as a plug or wiring.

[0258] On the insulator 251 and on the conductor 128, pixel electrodes 261 of the light-emitting devices 260R, 260G, and 260B are formed respectively.

[0259] In addition, an insulator 272 is provided to cover the end portions of the pixel electrode 261. The end portion of the insulator 272 is preferably tapered.

[0260] EL layers 262R, 262G, and 262B are formed on the upper surface of the pixel electrode 261 and on a part of the surface of the insulator 272. Also, during formation, the end portions of the EL layers 262R, 262G, and 262B are preferably located on the insulator 272.

[0261] In FIG. 14A, an EL layer 262R that exhibits red (R) light emission, an EL layer 262G that exhibits green (G) light emission, and an EL layer 262B that exhibits blue (B) light emission are independently provided on a plurality of pixel electrodes 261. In this way, a structure in which different light-emitting layers are formed for each color on a plurality of pixel electrodes 261 is referred to as an SBS (Side By Side) structure in this specification and the like.

[0262] Further, in the display device (display system) of FIG. 14A, although it has an SBS structure, the display device (the display system) may be configured such that a light-emitting layer that exhibits white light emission is formed continuously on a plurality of pixel electrodes 261, and a coloring layer (for example, a color filter) of red (R), green (G), and blue (B) is provided on the plurality of pixel electrodes 261. In particular, by forming a white light-emitting layer in a tandem structure described later, a white light-emitting device with high luminance and long life can be obtained.

[0263] Each of the EL layer 262R, the EL layer 262G, and the EL layer 262B may have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer (light-emitting layer) containing a light-emitting organic compound.

[0264] For example, as shown in FIG. 15A, the EL layer 262R, the EL layer 262G, and the EL layer 262B can be composed of a plurality of layers such as a layer 4420, a light-emitting layer 4411, and a layer 4430. The layer 4420 can have, for example, a layer (electron injection layer) containing a substance with high electron injection property and a layer (electron transport layer) containing a substance with high electron transport property. The light-emitting layer 4411 has, for example, a light-emitting compound. The layer 4430 can have, for example, a layer (hole injection layer) containing a substance with high hole injection property and a layer (hole transport layer) containing a substance with high hole transport property.

[0265] A configuration having the layer 4420, the light-emitting layer 4411, and the layer 4430 provided between a pair of electrodes can function as a single light-emitting unit, and the configuration of FIG. 15A is referred to as a single structure in this specification and the like.

[0266] As shown in FIG. 15B, a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0267] Further, as shown in FIG. 15C, a configuration in which a plurality of light-emitting units (EL layer 262a, EL layer 262b) are connected in series via an intermediate layer (charge generation layer) 4440 is referred to as a tandem structure in this specification. In this specification and the like, a configuration as shown in FIG. 15C is referred to as a tandem structure, but it is not limited thereto. For example, the tandem structure may be referred to as a stack structure. By adopting the tandem structure, a light-emitting device capable of high-brightness emission can be obtained.

[0268] The emission color of the light-emitting device 260 can be red, green, blue, cyan, magenta, yellow, white, etc., depending on the material constituting the EL layer 262. Further, by providing a microcavity structure to the light-emitting device 260, the color purity can be further enhanced.

[0269] It is preferable that the light-emitting device emitting white light has a configuration in which the light-emitting layer contains two or more types of light-emitting substances. To obtain white light emission, light-emitting substances may be selected such that the emission of each of the two or more light-emitting substances is in a complementary color relationship.

[0270] It is preferable that the light-emitting layer contains two or more light-emitting substances that exhibit emissions such as R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, there are two or more light-emitting substances, and the emission of each light-emitting substance preferably contains spectral components of two or more colors among R, G, and B.

[0271] Also, as shown in FIG. 14A, a gap is provided between two EL layers among light-emitting devices of different colors. Thus, it is preferable that the EL layer 262R, the EL layer 262G, and the EL layer 262B are provided so as not to be in contact with each other. Thereby, current can flow through two adjacent EL layers, and unintentional light emission (also referred to as crosstalk) can be suitably prevented. Therefore, the contrast can be enhanced, and a display device with high display quality can be realized.

[0272] The EL layer 262R, the EL layer 262G, and the EL layer 262B can be separately formed by a vacuum deposition method using a shadow mask such as a metal mask, or the like. Alternatively, they may be separately formed by a photolithography method. By using the photolithography method, a display device with high definition, which is difficult to realize when using a metal mask, can be realized.

[0273] A common electrode 263 is provided on the insulator 272, on the EL layer 262R, on the EL layer 262G, and on the EL layer 262G. The common electrode 263 is provided as a continuous layer common to each light-emitting device.

[0274] In this case, the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B are configured such that the EL layer 262R, the EL layer 262G, and the EL layer 262B are respectively provided between the pixel electrode 261 and the common electrode 263. The EL layer 262R has a light-emitting organic compound that emits light having intensity in at least the red wavelength range. Also, the EL layer 262G included in the light-emitting device 260G has a light-emitting organic compound that emits light having intensity in at least the green wavelength range. The EL layer 262B included in the light-emitting device 260B has a light-emitting organic compound that emits light having intensity in at least the blue wavelength range.

[0275] Further, as shown in FIG. 14A, the pixel electrodes 261 are provided for each light-emitting device. Here, for example, conversely, by selecting a conductive material having reflectivity for the pixel electrodes 261 and a conductive material having translucency for the common electrode 263, a top-emission type display device can be obtained.

[0276] Also, a protective layer 271 is provided on the common electrode 263 so as to cover the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B. The protective layer 271 has a function of preventing impurities such as water from diffusing into each light-emitting device from above.

[0277] The protective layer 271 can be, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used as the protective layer 271. Note that the protective layer 271 may be formed using an ALD method, a CVD method, or a sputtering method. Although the configuration including an inorganic insulating film has been exemplified as the protective layer 271, the present invention is not limited thereto. For example, the protective layer 271 may have a laminated structure of an inorganic insulating film and an organic insulating film.

[0278] As an example, the above-described light-emitting devices 260R, 260G, and 260B can be arranged in a matrix. Note that the arrangement method of the light-emitting devices is not limited to this, and an arrangement method such as a delta arrangement, a zigzag arrangement, or a pentile arrangement may be applied.

[0279] In addition, as the light-emitting devices 260R, 260G, and 260B, it is preferable to use EL elements such as OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode). Examples of the light-emitting substances included in the EL element are substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), inorganic compounds (such as quantum dot materials), and substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials).

[0280] In addition, the display device or display system according to one aspect of the present invention is not limited to the configuration of FIG. 14A. In FIG. 14A, a display device or display system using three types of color light-emitting devices has been described. However, the display device or display system according to one aspect of the present invention may be, for example, a display device or display system using a white light-emitting device and color layers of each color. In this case, as the white light-emitting device, for example, a single-layer light-emitting layer shown in FIG. 15A or FIG. 15B may be used, or a tandem light-emitting layer shown in FIG. 15C may be used.

[0281] In FIG. 14B, there is a light-emitting device 260W that exhibits white light. The light-emitting device 260W has an EL layer 262W that exhibits white light between the pixel electrode and the common electrode 263.

[0282] As the EL layer 262W, for example, a configuration in which two or more light-emitting layers are laminated so that their respective emission colors are in a complementary color relationship can be adopted. Alternatively, a stacked EL layer in which a charge generation layer is sandwiched between the light-emitting layers may be used.

[0283] FIG. 14B shows three light-emitting devices 260W arranged side by side. A coloring layer 264R is provided above the left light-emitting device 260W. The coloring layer 264R functions as a band-pass filter that transmits red light. Similarly, a coloring layer 264G that transmits green light is provided above the central light-emitting device 260W, and a coloring layer 264B that transmits blue light is provided above the right light-emitting device 260W. Thereby, the display device can display a color image.

[0284] Here, between two adjacent light-emitting devices 260W, the EL layer 262W and the common electrode 263 are separated from each other. Thereby, in two adjacent light-emitting devices 260W, current can flow through the EL layer 262W, and it is possible to preferably prevent unintentional light emission from occurring. In particular, when a stacked EL element in which a charge generation layer is provided between two light-emitting layers is used as the EL layer 262W, the higher the fineness, that is, the smaller the distance between adjacent pixels, the more significant the influence of crosstalk becomes, and there is a problem that the contrast decreases. Therefore, by adopting such a configuration, a display device having both high fineness and high contrast can be realized.

[0285] The separation of the EL layer 262W and the common electrode 263 is preferably performed by a photolithography method. Thereby, since the interval between the light-emitting devices can be narrowed, for example, compared with the case of using a shadow mask such as a metal mask, a display device with a high aperture ratio can be realized.

[0286] FIG. 16 is a cross-sectional view showing a configuration example of the display device shown in FIG. 3A or the display system shown in FIGS. 4 and 6. Note that the display system in FIG. 16 has a configuration in which the circuit section SIC includes the transistor 170, the layer OSC includes the transistor 500, and the display section DSP includes the transistor 180, the light-emitting device 260R, the light-emitting device 260G, and the light-emitting device 260B. FIG. 16 also shows cross-sectional views in the channel length direction of the transistor 170, the transistor 180, and the transistor 500.

[0287] Also, regarding the circuit section SIC and the display section DSP, since the description of FIG. 14A can be incorporated, the transistor 500 included in the layer OSC and its peripheral configuration will be described below.

[0288] An insulator 512 is formed above the insulator 118 of the circuit section SIC. The insulator 512 is preferably made of a material that is barrier against oxygen and hydrogen.

[0289] Also, as the insulator 512, for example, the same material as the insulator 116 can be used.

[0290] Also, as shown in FIGS. 17A and 17B, an insulator 514 and an insulator 516 are formed on the insulator 512.

[0291] For the insulator 514, it is preferable to use a film having a barrier property such that hydrogen and impurities do not diffuse from regions such as the substrate 101 or the region where the transistor 170 is provided to the region where the transistor 500 is provided. Therefore, for the insulator 514, for example, silicon nitride formed by CVD method can be used.

[0292] Also, as the insulator 516, for example, the same material as the insulator 116 can be used.

[0293] A transistor 500 is provided above the insulator 516.

[0294] As shown in FIGS. 17A and 17B, transistor 500 includes insulator 516 on insulator 514, conductor 503 (conductor 503a and conductor 503b) disposed to be embedded in insulator 514 or insulator 516, insulator 522 on insulator 516 and on conductor 503, insulator 524 on insulator 522, oxide 530a on insulator 524, oxide 530b on oxide 530a, conductor 542a on oxide 530b, insulator 571a on conductor 542a, conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping a part of oxide 530b, and insulator 544 disposed on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542 (conductor 542a and conductor 542b), and insulator 571 (insulator 571a and insulator 571b). Here, as shown in FIGS. 17A and 17B, insulator 552 is in contact with the upper surface of insulator 522, the side surface of insulator 524, the side surfaces of oxide 530a and oxide 530b, the side surfaces of conductor 542, the side surfaces of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Also, the upper surface of conductor 560 is arranged to be substantially flush with the upper part of insulator 554, the upper part of insulator 550, the upper part of insulator 552, and the upper surface of insulator 580. Also, insulator 574 is in contact with at least a part of the upper surface of conductor 560, the upper part of insulator 552, the upper part of insulator 550, the upper part of insulator 554, and the upper surface of insulator 580.

[0295] The insulator 580 and the insulator 544 are provided with openings that reach the oxide 530b. Inside the openings, an insulator 552, an insulator 550, an insulator 554, and a conductor 560 are arranged. Also, in the channel length direction of the transistor 500, a conductor 560, an insulator 552, an insulator 550, and an insulator 554 are provided between the insulator 571a and the conductor 542a, and between the insulator 571b and the conductor 542b. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0296] The oxide 530 preferably has an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By having the oxide 530a under the oxide 530b, diffusion of impurities from a structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0297] Note that in the transistor 500, the oxide 530 is shown as having a structure in which two layers of the oxide 530a and the oxide 530b are stacked, but the present invention is not limited to this. For example, the transistor 500 can have a configuration with a single layer of the oxide 530b or a stacked structure of three or more layers. Or, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0298] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. Also, the insulator 552, the insulator 550, and the insulator 554 function as a first gate insulator, and the insulator 522 and the insulator 524 function as a second gate insulator. Note that the gate insulator may also be referred to as a gate insulating layer or a gate insulating film. Also, the conductor 542a functions as one of the source or the drain, and the conductor 542b functions as the other of the source or the drain. Also, at least a part of the region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0299] Here, an enlarged view of the vicinity of the channel formation region in FIG. 17A is shown in FIG. 18A. By supplying oxygen to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 18A, the oxide 530b has a region 530bc that functions as a channel formation region of the transistor 500, and regions 530ba and 530bb that are provided so as to sandwich the region 530bc and function as a source region or a drain region. At least a part of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is provided in the region between the conductor 542a and the conductor 542b. The region 530ba is provided so as to overlap with the conductor 542a, and the region 530bb is provided so as to overlap with the conductor 542b.

[0300] The region 530bc that functions as a channel formation region has less oxygen deficiency (in this specification, etc., oxygen deficiency in a metal oxide may be referred to as V O (oxygen vacancy).) or a lower impurity concentration than the regions 530ba and 530bb, and thus is a high-resistance region with a low carrier concentration. Therefore, the region 530bc can be said to be of i-type (intrinsic) or substantially i-type.

[0301] In a transistor using a metal oxide, if impurities or oxygen deficiency (V O ) are present in the region where the channel in the metal oxide is formed, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, hydrogen near the oxygen deficiency (V O ) may form a defect (hereinafter, may be referred to as V O H.) in which hydrogen enters the oxygen deficiency (V O ) and generate electrons that become carriers. For this reason, if the region where the channel in the oxide semiconductor is formed contains oxygen deficiency, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists even without applying a voltage to the gate electrode and current flows through the transistor). Therefore, in the region where the channel in the oxide semiconductor is formed, impurities, oxygen deficiency, and V OH is preferably reduced as much as possible.

[0302] In addition, regions 530ba and 530bb that function as a source region or a drain region have an increased carrier concentration and are low-resistance regions due to a large amount of oxygen deficiency (V O ) or a high impurity concentration of hydrogen, nitrogen, metal elements, etc. That is, regions 530ba and 530bb are n-type regions with a high carrier concentration and low resistance as compared with region 530bc.

[0303] Here, the carrier concentration of region 530bc that functions as a channel formation region is preferably 1×10 18 cm -3 or less, more preferably less than 1×10 17 cm -3 less, even more preferably less than 1×10 16 cm -3 less, even more preferably less than 1×10 13 cm -3 less, even more preferably less than 1×10 12 cm -3 less. Note that the lower limit value of the carrier concentration of region 530bc that functions as a channel formation region is not particularly limited, but can be, for example, 1×10 -9 cm -3 .

[0304] Also, a region may be formed between region 530bc and region 530ba or region 530bb, where the carrier concentration is equal to or lower than the carrier concentrations of regions 530ba and 530bb and equal to or higher than the carrier concentration of region 530bc. That is, the region functions as a junction region between region 530bc and region 530ba or region 530bb. The hydrogen concentration in the junction region may be equal to or lower than the hydrogen concentrations of regions 530ba and 530bb and equal to or higher than the hydrogen concentration of region 530bc. Also, the oxygen deficiency in the junction region may be equal to or less than the oxygen deficiencies of regions 530ba and 530bb and equal to or more than the oxygen deficiency of region 530bc.

[0305] In addition, in FIG. 18A, an example is shown in which regions 530ba, 530bb, and 530bc are formed in oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 530b but also in oxide 530a.

[0306] Also, in oxide 530, it may be difficult to clearly detect the boundaries of each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region are not limited to stepwise changes from region to region and may also change continuously within each region. That is, the closer the region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, may be.

[0307] For transistor 500, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for oxide 530 (oxide 530a and oxide 530b) including the channel formation region.

[0308] In addition, as the metal oxide that functions as a semiconductor, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large band gap in this way, the off-current of the transistor can be reduced.

[0309] As the oxide 530, for example, a metal oxide such as an In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc.) may be used. Further, as the oxide 530, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0310] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for the oxide 530b is larger than the atomic ratio of In to element M in the metal oxide used for the oxide 530a.

[0311] In this way, by disposing the oxide 530a under the oxide 530b, diffusion of impurities and oxygen from the structure formed below the oxide 530a to the oxide 530b can be suppressed.

[0312] In addition, since the oxide 530a and the oxide 530b have a common element (as the main component) other than oxygen, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered. Since the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered, the influence on carrier conduction due to interface scattering is small, and a high on-current can be obtained.

[0313] The oxide 530b preferably has crystallinity. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide 530b.

[0314] CAAC-OS has a highly crystalline and dense structure and is a metal oxide with few impurities and defects (e.g., oxygen vacancies (V O such as)). In particular, by heat-treating the metal oxide at a temperature (e.g., 400 °C or higher and 600 °C or lower) such that the metal oxide does not polycrystallize after the formation of the metal oxide, CAAC-OS can be made to have a more highly crystalline and dense structure. By thus increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0315] On the other hand, since it is difficult to confirm distinct grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0316] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may deteriorate. Also, hydrogen near an oxygen vacancy may form a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons serving as carriers. For this reason, if the region where a channel is formed in the oxide semiconductor contains oxygen vacancies, the transistor is likely to have normally-on characteristics (characteristics in which a channel exists even when no voltage is applied to the gate electrode and current flows through the transistor). Therefore, in the region where a channel is formed in the oxide semiconductor, it is preferable that impurities, oxygen vacancies, and V O H are reduced as much as possible. In other words, in the region where a channel is formed in the oxide semiconductor, it is preferable that the carrier concentration is reduced and the region is i-type (intrinsic) or substantially i-type.

[0317] On the other hand, by providing an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen deficiency and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, it may cause a decrease in the on-current of the transistor 500 or a decrease in the field-effect mobility. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0318] Therefore, in the oxide semiconductor, the region 530bc that functions as the channel formation region preferably has a reduced carrier concentration and is of i-type or substantially i-type, while the regions 530ba and 530bb that function as the source region or the drain region preferably have a high carrier concentration and are of n-type. That is, it is preferable to reduce the oxygen deficiency and V O H in the region 530bc of the oxide semiconductor and prevent an excessive amount of oxygen from being supplied to the regions 530ba and 530bb.

[0319] Therefore, in the present embodiment, while the conductor 542a and the conductor 542b are provided on the oxide 530b, microwave treatment is performed in an oxygen-containing atmosphere to reduce the oxygen deficiency and V O H in the region 530bc. Here, the microwave treatment refers to, for example, a treatment using a device having a power source for generating high-density plasma using microwaves.

[0320] By performing microwave treatment in an oxygen-containing atmosphere, oxygen gas can be made into plasma using microwaves or high-frequency waves such as RF, and the oxygen plasma can be made to act. At this time, microwaves or high-frequency waves such as RF can also be irradiated to the region 530bc. Due to the action of plasma, microwaves, etc., the V O H in the region 530bc is segmented, hydrogen H is removed from the region 530bc, and oxygen deficiency V Ocan be compensated with oxygen. That is, in region 530bc, the reaction of "V O H → H + V O " occurs, and the hydrogen concentration in region 530bc can be reduced. Therefore, the oxygen deficiency and V O H in region 530bc can be reduced, and the carrier concentration can be decreased.

[0321] Also, when performing microwave treatment in an oxygen-containing atmosphere, the actions of microwaves, high-frequency waves such as RF, and oxygen plasma are shielded by conductor 542a and conductor 542b and do not reach region 530ba and region 530bb. Furthermore, the action of oxygen plasma can be reduced by insulator 571 and insulator 580 provided to cover oxide 530b and conductor 542. As a result, during microwave treatment, reduction of V O H and excessive oxygen supply do not occur in region 530ba and region 530bb, so a decrease in carrier concentration can be prevented.

[0322] Also, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes insulator 552 or after forming the insulating film that becomes insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through insulator 552 or insulator 550 in this way, oxygen can be efficiently injected into region 530bc. Also, by arranging insulator 552 so as to be in contact with the side surface of conductor 542 and the surface of region 530bc, injection of more oxygen than necessary into region 530bc can be suppressed, and oxidation of the side surface of conductor 542 can be suppressed. Also, oxidation of the side surface of conductor 542 can be suppressed when forming the insulating film that becomes insulator 550.

[0323] In addition, the oxygen injected into region 530bc exists in various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (also referred to as O radicals, atoms, molecules, or ions having unpaired electrons). Note that the oxygen injected into region 530bc is preferably any one or more of the above-described forms, and particularly preferably oxygen radicals. Further, since the film quality of insulator 552 and insulator 550 can be improved, the reliability of transistor 500 is improved.

[0324] In this way, oxygen deficiency and V O H can be selectively removed in region 530bc of the oxide semiconductor, and region 530bc can be made into an i-type or substantially i-type. Further, supply of excessive oxygen to regions 530ba and 530bb that function as a source region or a drain region can be suppressed, and conductivity can be maintained. Thereby, fluctuations in the electrical characteristics of transistor 500 can be suppressed, and variations in the electrical characteristics of transistor 500 within the substrate surface can be reduced.

[0325] By adopting the above configuration, a semiconductor device with little variation in transistor characteristics can be provided. In addition, a semiconductor device with good reliability can be provided. Further, a semiconductor device having good electrical characteristics can be provided.

[0326] Also, as shown in FIG. 17B, in a cross-sectional view in the channel width direction of transistor 500, a curved surface may be provided between the side surface and the upper surface of oxide 530b. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as rounded).

[0327] The radius of curvature of the above-mentioned curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half of the length of the region without the above-mentioned curved surface. Specifically, the radius of curvature of the above-mentioned curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering properties of the insulator 552, the insulator 550, the insulator 554, and the conductor 560 on the oxide 530b can be improved.

[0328] The oxide 530 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Also, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Further, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0329] Also, the oxide 530b is preferably an oxide having crystallinity such as CAAC-OS. Oxides having crystallinity such as CAAC-OS have a dense structure with few impurities and defects (such as oxygen vacancies) and high crystallinity. Therefore, the extraction of oxygen from the oxide 530b by the source electrode or the drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the oxide 530b can be reduced, so the transistor 500 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0330] Here, at the junction of the oxide 530a and the oxide 530b, the lower end of the conduction band changes smoothly. In other words, it can also be said that the lower end of the conduction band at the junction of the oxide 530a and the oxide 530b changes continuously or is continuously joined. To achieve this, it is preferable to lower the density of defect levels in the mixed layer formed at the interface between the oxide 530a and the oxide 530b.

[0331] Specifically, since the oxide 530a and the oxide 530b have a common element other than oxygen as a main component, a mixed layer with a low density of defect levels can be formed. For example, when the oxide 530b is an In-M-Zn oxide, as the oxide 530a, an In-M-Zn oxide, an M-Zn oxide, an oxide of the element M, an In-Zn oxide, an indium oxide, or the like may be used.

[0332] Specifically, as the oxide 530a, a metal oxide having a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof may be used. Also, as the oxide 530b, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof may be used. The vicinity of the composition includes a range of ±30% of the desired atomic ratio. Also, as the element M, it is preferable to use gallium.

[0333] Note that when forming a film of a metal oxide by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide, and may be the atomic ratio of the sputtering target used for forming the metal oxide.

[0334] Also, as shown in FIG. 17A and the like, by providing an insulator 552 formed of aluminum oxide or the like in contact with the upper surface and side surfaces of the oxide 530, indium contained in the oxide 530 may be unevenly distributed at the interface between the oxide 530 and the insulator 552 and in the vicinity thereof. As a result, the vicinity of the surface of the oxide 530 has an atomic ratio close to that of indium oxide or an atomic ratio close to that of In-Zn oxide. By increasing the atomic ratio of indium in the vicinity of the surface of the oxide 530, particularly the oxide 530b, in this way, the field-effect mobility of the transistor 500 can be improved.

[0335] By configuring the oxide 530a and the oxide 530b as described above, the density of defect levels at the interface between the oxide 530a and the oxide 530b can be lowered. Therefore, the influence on carrier conduction due to interface scattering is reduced, and the transistor 500 can obtain a large on-current and high frequency characteristics.

[0336] At least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, it is preferable to use an insulating material having a function of suppressing the diffusion of impurities (the above impurities are difficult to permeate) such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms for at least one of the insulator 512, the insulator 514, the insulator 544, the insulator 571, the insulator 574, the insulator 576, and the insulator 581. Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate).

[0337] In this specification, the barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier property means a function of suppressing the diffusion of the corresponding substance (also referred to as low permeability). Or, it means a function of capturing and fixing the corresponding substance (also referred to as gettering).

[0338] As the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride can be used. For example, as the insulators 512, 544, and 576, it is preferable to use silicon nitride or the like having higher hydrogen barrier properties. Further, for example, as the insulators 514, 571, 574, and 581, it is preferable to use aluminum oxide or magnesium oxide or the like having a high function of capturing and fixing hydrogen. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Or, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film or the like disposed outside the insulator 581 to the transistor 500 side. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 524 or the like to the substrate side through the insulators 512 and 514. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 580 or the like above the transistor 500 through the insulator 574 or the like. In this way, it is preferable to form a structure in which the transistor 500 is surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0339] Here, as the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581, it is preferable to use an oxide having an amorphous structure. For example, AlO x (where x is an arbitrary number greater than 0), or MgO y (where y is an arbitrary number greater than 0), etc., it is preferable to use metal oxides. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a transistor 500 and a semiconductor device having good characteristics and high reliability can be fabricated.

[0340] Also, the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 preferably have an amorphous structure, but a region with a polycrystalline structure may be formed partially. Also, the insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 may have a multilayer structure in which a layer with an amorphous structure and a layer with a polycrystalline structure are laminated. For example, a laminated structure in which a layer with a polycrystalline structure is formed on a layer with an amorphous structure may also be used.

[0341] The film formation of insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 may be performed, for example, using a sputtering method. Since the sputtering method does not need to use a molecule containing hydrogen as a film formation gas, the hydrogen concentration of insulator 512, insulator 514, insulator 544, insulator 571, insulator 574, insulator 576, and insulator 581 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, etc. may be appropriately used.

[0342] Also, there may be cases where it is preferable to lower the resistivity of insulator 512, insulator 544, and insulator 576. For example, by setting the resistivity of insulator 512, insulator 544, and insulator 576 to approximately 1×10 13 Ωcm, in a process using plasma or the like in the semiconductor device manufacturing process, insulator 512, insulator 544, and insulator 576 may be able to relax the charge-up of conductor 503, conductor 542, conductor 560, etc. The resistivity of insulator 512, insulator 544, and insulator 576 is preferably 1×10 10 Ωcm or more and 1×10 15 Ωcm or less.

[0343] Also, insulator 516, insulator 574, insulator 580, and insulator 581 preferably have a lower dielectric constant than insulator 514. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as insulator 516, insulator 580, and insulator 581, silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. may be appropriately used.

[0344] Also, as an example, insulator 581 is preferably an insulator that functions as an interlayer film, a planarization film, etc.

[0345] The conductor 503 is arranged to overlap with the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. Also, a part of the conductor 503 may be embedded in the insulator 514.

[0346] The conductor 503 has a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and the side wall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the upper part of the conductor 503b is substantially the same as the height of the upper part of the conductor 503a and the height of the upper part of the insulator 516.

[0347] Here, for the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0348] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 through the insulator 524 or the like. Also, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 503a, it is possible to suppress the oxidation of the conductor 503b and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, it is preferable to use titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, as the conductor 503a, the above conductive material may be a single layer or a laminate. For example, the conductor 503a may use titanium nitride.

[0349] Also, for the conductor 503b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductor 503b may use tungsten.

[0350] The conductor 503 may function as a second gate electrode. In this case, by independently changing the potential applied to the conductor 503 without linking it to the potential applied to the conductor 560, the threshold voltage (Vth) of the transistor 500 can be controlled. In particular, by applying a negative potential to the conductor 503, it is possible to increase the Vth of the transistor 500 and reduce the off-current. Therefore, applying a negative potential to the conductor 503 can make the drain current smaller when the potential applied to the conductor 560 is 0V than when no negative potential is applied.

[0351] Note that if the oxide 530 is highly pure and intrinsic, with impurities removed as much as possible from the oxide 530, it may be possible to turn off the transistor 500 normally (make the threshold voltage of the transistor 500 greater than 0V) without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied.

[0352] Also, the electrical resistivity of the conductor 503 is designed in consideration of the potential applied to the conductor 503, and the film thickness of the conductor 503 is set according to the electrical resistivity. Also, the film thickness of the insulator 516 is made substantially the same as that of the conductor 503. Here, it is preferable to reduce the film thicknesses of the conductor 503 and the insulator 516 within the range allowed by the design of the conductor 503. By reducing the film thickness of the insulator 516, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, so that the diffusion of the impurities into the oxide 530 can be reduced.

[0353] Note that the conductor 503 may be provided to be larger than the size of the region that does not overlap with the conductors 542a and 542b of the oxide 530 when viewed from above. In particular, as shown in FIG. 17B, the conductor 503 preferably extends also in a region outside the end portions in the channel width direction of the oxides 530a and 530b. That is, it is preferable that the conductor 503 and the conductor 560 overlap with each other via an insulator outside the side surfaces of the oxide 530 in the channel width direction. By having such a configuration, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560 functioning as the first gate electrode and the electric field of the conductor 503 functioning as the second gate electrode. In this specification, the structure of a transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is referred to as a surrounded channel (S-channel) structure.

[0354] Note that in this specification and the like, an S-channel structure transistor refers to a structure of a transistor in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Further, the S-channel structure disclosed in this specification and the like is different from a Fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to increase the resistance to the short channel effect, in other words, to obtain a transistor in which the short channel effect hardly occurs.

[0355] By setting the transistor 500 to normally-off and having the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be regarded as having a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By setting the transistor 500 to an S-Channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be made to cover the entire bulk of the oxide 530. In other words, by setting the transistor 500 to an S-Channel structure, a GAA structure, or an LGAA structure, a so-called Bulk-Flow type can be achieved in which the carrier path is used throughout the bulk. By adopting a Bulk-Flow type transistor structure, it becomes possible to improve the current density flowing through the transistor, and thus it can be expected to improve the on-current of the transistor or increase the field-effect mobility of the transistor.

[0356] Also, as shown in FIG. 17B, the conductor 503 is extended to also function as a wiring. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor functioning as a wiring is provided under the conductor 503. Also, the conductor 503 does not necessarily need to be provided one by one for each transistor. For example, a configuration may be adopted in which the conductor 503 is shared by a plurality of transistors.

[0357] Note that in the transistor 500, the conductor 503 is shown as a configuration in which the conductor 503a and the conductor 503b are stacked, but the present invention is not limited to this. For example, the conductor 503 may be provided as a single layer or a stacked structure of three or more layers.

[0358] The insulator 522 and the insulator 524 function as gate insulators.

[0359] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (for example, at least one of a hydrogen atom, a hydrogen molecule, etc.). Further, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of an oxygen atom, an oxygen molecule, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0360] As the insulator 522, an insulator containing one or both oxides of aluminum and hafnium, which are insulating materials, may be used. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses the release of oxygen from the oxide 530 to the substrate side and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 500 to the oxide 530. Therefore, by providing the insulator 522, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 500 and suppress the generation of oxygen vacancies in the oxide 530. Further, it is possible to suppress the reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530.

[0361] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to the above insulator. Alternatively, these insulators may be nitrided. Further, the insulator 522 may be used by laminating silicon oxide, silicon oxynitride or silicon nitride on these insulators.

[0362] In addition, as the insulator 522, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, etc. may be used in a single layer or a laminate. As the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator functioning as the gate insulator, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Also, as the insulator 522, substances with high dielectric constants such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. may be used in some cases.

[0363] As the insulator 524 in contact with the oxide 530, for example, silicon oxide, silicon oxynitride, etc. may be appropriately used.

[0364] Also, during the manufacturing process of the transistor 500, it is preferable to perform a heat treatment in a state where the surface of the oxide 530 is exposed. The heat treatment may be performed, for example, at 100°C or higher and 600°C or lower, more preferably at 350°C or higher and 550°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. Thereby, oxygen can be supplied to the oxide 530 to reduce the oxygen vacancies (V O ). Also, the heat treatment may be performed under reduced pressure. Or, after performing the heat treatment in an atmosphere of nitrogen gas or an inert gas, in order to supplement the desorbed oxygen, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Or, after performing the heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, the heat treatment may be continuously performed in an atmosphere of nitrogen gas or an inert gas.

[0365] Note that by performing an oxygen addition treatment on the oxide 530, the oxygen vacancies in the oxide 530 are repaired by the supplied oxygen, in other words, "V OThe reaction of "+O→null" can be promoted. Further, by reacting the oxygen supplied to the hydrogen remaining in the oxide 530, the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide 530 recombines with oxygen vacancies to form V O The formation of H can be suppressed.

[0366] Note that the insulator 522 and the insulator 524 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. Further, the insulator 524 may be formed in an island shape by overlapping with the oxide 530a. In this case, the insulator 544 is configured to be in contact with the side surface of the insulator 524 and the upper surface of the insulator 522.

[0367] The conductor 542a and the conductor 542b are provided in contact with the upper surface of the oxide 530b. The conductor 542a and the conductor 542b each function as a source electrode or a drain electrode of the transistor 500.

[0368] As the conductor 542 (the conductor 542a and the conductor 542b), for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one aspect of the present invention, a nitride containing tantalum is particularly preferred. Further, for example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. These materials are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0369] In addition, hydrogen contained in the oxide 530b or the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductor 542a and the conductor 542b, hydrogen contained in the oxide 530b or the like easily diffuses into the conductor 542a or the conductor 542b, and the diffused hydrogen may combine with nitrogen possessed by the conductor 542a or the conductor 542b. That is, hydrogen contained in the oxide 530b or the like may be absorbed by the conductor 542a or the conductor 542b.

[0370] Also, it is preferable that a curved surface is not formed between the side surface and the upper surface of the conductor 542. By using the conductor 542 in which the curved surface is not formed, the cross-sectional area of the conductor 542 in the cross-section in the channel width direction can be increased. Thereby, the conductivity of the conductor 542 can be increased, and the on-current of the transistor 500 can be increased.

[0371] The insulator 571a is provided in contact with the upper surface of the conductor 542a, and the insulator 571b is provided in contact with the upper surface of the conductor 542b. The insulator 571 preferably functions as at least an oxygen barrier insulating film. Therefore, the insulator 571 preferably has a function of suppressing the diffusion of oxygen. For example, the insulator 571 preferably has a function of suppressing the diffusion of oxygen more than the insulator 580. As the insulator 571, for example, a nitride containing silicon such as silicon nitride may be used. Further, the insulator 571 preferably has a function of capturing impurities such as hydrogen. In that case, as the insulator 571, an insulator having an amorphous structure, such as aluminum oxide or magnesium oxide, may be used. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 may be preferable because hydrogen can be captured or fixed more effectively. Thereby, a transistor 500 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0372] The insulator 544 is provided so as to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing hydrogen and fixing hydrogen. In that case, the insulator 544 preferably includes silicon nitride or an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide. Further, for example, as the insulator 544, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used.

[0373] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be wrapped with an insulator having barrier properties against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. Thereby, it is possible to suppress the direct oxidation of the conductor 542 by oxygen contained in the insulator 524 and the insulator 580, an increase in resistivity, and a reduction in on-current.

[0374] The insulator 552 functions as a part of the gate insulator. As the insulator 552, a barrier insulating film against oxygen is preferably used. As the insulator 552, an insulator that can be used for the above-described insulator 574 may be used. As the insulator 552, an insulator containing one or both of aluminum oxide and hafnium oxide is preferably used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In the present embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 becomes an insulator having at least oxygen and aluminum.

[0375] As shown in FIG. 17B, the insulator 552 is provided in contact with the upper surface and side surfaces of the oxide 530b, the side surface of the oxide 530a, the side surface of the insulator 524, and the upper surface of the insulator 522. That is, the region overlapping with the conductors 560 of the oxide 530a, the oxide 530b, and the insulator 524 is covered with the insulator 552 in the cross-section in the channel width direction. Thereby, when heat treatment or the like is performed, the desorption of oxygen by the oxides 530a and 530b can be blocked by the insulator 552 having a barrier property against oxygen. Therefore, the formation of oxygen vacancies (Vo) in the oxides 530a and 530b can be reduced. Thereby, the oxygen vacancies (Vo) and V O H formed in the region 530bc can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved and the reliability can be enhanced.

[0376] Conversely, even if an excessive amount of oxygen is contained in the insulator 580 and the insulator 550 or the like, the supply of the oxygen to the oxides 530a and 530b can be suppressed. Therefore, the excessive oxidation of the regions 530ba and 530bb through the region 530bc, which causes a decrease in the on-current or a decrease in the field-effect mobility of the transistor 500, can be suppressed.

[0377] As shown in FIG. 17A, the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 571, the insulator 544, and the insulator 580, respectively. Therefore, the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface can be reduced. Thereby, the decrease in the on-current or the decrease in the field-effect mobility of the transistor 500 can be suppressed.

[0378] In addition, the insulator 552 needs to be provided in an opening formed in the insulator 580 or the like together with the insulator 554, the insulator 550, and the conductor 560. When miniaturizing the transistor 500, it is preferable that the film thickness of the insulator 552 is thin. The film thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and is preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower limit values and upper limit values can be combined with each other. In this case, the insulator 552 only needs to have a region with the above-described film thickness in at least a part thereof. Further, the film thickness of the insulator 552 is preferably thinner than the film thickness of the insulator 550. In this case, the insulator 552 only needs to have a region with a film thickness thinner than that of the insulator 550 in at least a part thereof.

[0379] In order to form the insulator 552 with a thin film thickness as described above, it is preferable to form the film using the ALD method. The ALD method includes a thermal ALD method in which the reaction of a precursor and a reactant is performed only with thermal energy, a PEALD (Plasma Enhanced ALD) method using a plasma-excited reactant, and the like. In the PEALD method, it may be preferable because film formation at a lower temperature is possible by using plasma.

[0380] The ALD method utilizes the self-control property which is a property of atoms and can deposit atoms one by one, so that extremely thin film formation is possible, film formation on a structure with a high aspect ratio is possible, film formation with few defects such as pinholes is possible, film formation with excellent coverage is possible, film formation at a low temperature is possible, and the like. Therefore, the insulator 552 can be formed with a good coverage on the side surface of the opening formed in the insulator 580 or the like with the above-described thin film thickness.

[0381] Note that some of the precursors used in the ALD method contain carbon and the like. Therefore, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film-forming methods. The quantification of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0382] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. As the insulator 550, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having pores, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. In this case, the insulator 550 is an insulator having at least oxygen and silicon.

[0383] Similar to the insulator 524, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 550 is reduced. The film thickness of the insulator 550 preferably has a lower limit of 1 nm or more, or 0.5 nm or more, and an upper limit of 15 nm or less, or 20 nm or less. Note that the above-described lower limit and upper limit can be combined with each other. In this case, the insulator 550 may have a region with the above-described film thickness at least partially.

[0384] In FIGS. 17A and 17B and the like, a configuration in which the insulator 550 is a single layer is shown, but the present invention is not limited to this, and a laminated structure of two or more layers may be used. For example, as shown in FIG. 18B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0385] As shown in FIG. 18B, when the insulator 550 has a two-layer stacked structure, the lower-layer insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper-layer insulator 550b is preferably formed using an insulator having a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 530. Further, it is possible to suppress the oxidation of the conductor 560 by the oxygen contained in the insulator 550a. For example, the insulator 550a may be provided using a material that can be used for the above-described insulator 550, and the insulator 550b may preferably use an insulator containing one or both of aluminum oxide and hafnium oxide. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In the present embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b becomes an insulator having at least oxygen and hafnium. Further, the film thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more as a lower limit value, and preferably 3.0 nm or less, or 5.0 nm or less as an upper limit value. Note that the above-described lower limit value and upper limit value can be combined with each other. In this case, the insulator 550b only needs to have a region with the above-described film thickness in at least a part thereof.

[0386] Note that when silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may use an insulating material that is a high-k material having a high relative dielectric constant. By forming the gate insulator into a stacked structure of the insulator 550a and the insulator 550b, a stacked structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to thin the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator. Thus, the breakdown voltage of the insulator 550 can be increased.

[0387] The insulator 554 functions as part of the gate insulator. As the insulator 554, it is preferable to use a barrier insulating film against hydrogen. Thereby, impurities such as hydrogen contained in the conductor 560 can be prevented from diffusing into the insulator 550 and the oxide 530b. As the insulator 554, an insulator that can be used for the above-described insulator 576 may be used. For example, silicon nitride formed by the PEALD method may be used as the insulator 554. In this case, the insulator 554 becomes an insulator having at least nitrogen and silicon.

[0388] Also, the insulator 554 may further have a barrier property against oxygen. Thereby, diffusion of oxygen contained in the insulator 550 into the conductor 560 can be suppressed.

[0389] Also, the insulator 554 needs to be provided in an opening formed in the insulator 580 or the like together with the insulator 552, the insulator 550, and the conductor 560. In order to miniaturize the transistor 500, the film thickness of the insulator 554 is preferably thin. The film thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more as a lower limit value, and preferably 3.0 nm or less or 5.0 nm or less as an upper limit value. Note that the above-described lower limit value and upper limit value can be combined with each other. In this case, the insulator 554 may have a region having a film thickness as described above at least in part. Also, the film thickness of the insulator 554 is preferably thinner than the film thickness of the insulator 550. In this case, the insulator 554 may have a region having a film thickness thinner than that of the insulator 550 at least in part.

[0390] The conductor 560 functions as the first gate electrode of the transistor 500. The conductor 560 preferably has a conductor 560a and a conductor 560b disposed on the conductor 560a. For example, the conductor 560a is preferably disposed so as to wrap the bottom surface and the side surface of the conductor 560b. Also, as shown in FIGS. 17A and 17B, the height position of the upper part of the conductor 560 is substantially the same as the height position of the upper part of the insulator 550. Note that in FIGS. 17A and 17B, the conductor 560 is shown as a two-layer structure of the conductor 560a and the conductor 560b, but the conductor 560 can have a single-layer structure or a laminated structure of three or more layers other than the two-layer structure.

[0391] For the conductor 560a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0392] In addition, since the conductor 560a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 560b by oxygen contained in the insulator 550 and a decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0393] In addition, since the conductor 560 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, for the conductor 560b, a conductive material mainly composed of tungsten, copper, or aluminum can be used. Also, the conductor 560b can have a laminated structure. Specifically, for example, the conductor 560b can have a laminated structure of titanium, titanium nitride, and the above conductive material.

[0394] In the transistor 500, the conductor 560 is self-aligned to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this way, it is possible to surely arrange the conductor 560 in the region between the conductors 542a and 542b without alignment.

[0395] Also, as shown in FIG. 17B, in the channel width direction of the transistor 500, when the bottom surface of the insulator 522 is used as a reference, the height of the bottom surface of the region of the conductor 560 where the conductor 560 and the oxide 530b do not overlap is preferably lower than the height of the bottom surface of the oxide 530b. By configuring the conductor 560 that functions as a gate electrode to cover the side surface and the upper surface of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can easily act on the entire channel formation region of the oxide 530b. Therefore, the on-current of the transistor 500 can be increased and the frequency characteristics can be improved. The difference between the height of the bottom surface of the conductor 560 in the region where the oxides 530a and 530b and the conductor 560 do not overlap and the height of the bottom surface of the oxide 530b, when the bottom surface of the insulator 522 is used as a reference, is preferably 0 nm or more, 3 nm or more, or 5 nm or more as a lower limit value, and preferably 20 nm or less, 50 nm or less, or 100 nm or less as an upper limit value. Note that the above-described lower limit value and upper limit value can be combined with each other.

[0396] The insulator 580 is provided on the insulator 544, and an opening is formed in the region where the insulator 550 and the conductor 560 are provided. Also, the upper surface of the insulator 580 may be planarized.

[0397] The insulator 580 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator 580 is preferably provided using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because regions containing oxygen that desorb upon heating can be easily formed.

[0398] Preferably, the impurity concentrations such as water and hydrogen in the insulator 580 are reduced. For example, as the insulator 580, oxides containing silicon such as silicon oxide and silicon oxynitride may be appropriately used.

[0399] The insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 580, and preferably has a function of capturing impurities such as hydrogen. Further, the insulator 574 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 574, an insulator having an amorphous structure, for example, an insulator such as aluminum oxide may be used. In this case, the insulator 574 becomes an insulator having at least oxygen and aluminum. By providing the insulator 574 having a function of capturing impurities such as hydrogen in contact with the insulator 580 within the region sandwiched between the insulator 512 and the insulator 581, impurities such as hydrogen contained in the insulator 580 and the like can be captured, and the amount of hydrogen in the region can be made a constant value. In particular, using aluminum oxide having an amorphous structure as the insulator 574 may be preferable because hydrogen can be captured or fixed more effectively. Thereby, a transistor 500 having good characteristics and high reliability, and a semiconductor device can be manufactured.

[0400] The insulator 576 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 580. The insulator 576 is disposed on the insulator 574. As the insulator 576, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon oxynitride. For example, silicon nitride formed by a sputtering method may be used as the insulator 576. By forming the insulator 576 by a sputtering method, a silicon nitride film with high density can be formed. Further, as the insulator 576, silicon nitride formed by a PEALD method or a CVD method may be laminated on the silicon nitride formed by a sputtering method.

[0401] Also, one of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540a that functions as a plug, and the other of the first terminal or the second terminal of the transistor 500 is electrically connected to the conductor 540b. Note that the conductor 540a, the conductor 540b, etc. may function as wirings for electrically connecting to the upper display unit DSP or the lower circuit unit SIC. In this specification etc., the conductor 540a and the conductor 540b will be collectively referred to as the conductor 540.

[0402] The conductor 540a is provided, as an example, in a region that overlaps with the conductor 542a. Specifically, in the region that overlaps with the conductor 542a, openings are formed in the insulator 571, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 shown in FIG. 17A, and the conductor 540a is provided inside the opening. Also, the conductor 540b is provided, as an example, in a region that overlaps with the conductor 542b. Specifically, in the region that overlaps with the conductor 542b, openings are formed in the insulator 571, the insulator 544, the insulator 580, the insulator 574, the insulator 576, and the insulator 581 shown in FIG. 17A, and the conductor 540b is provided inside the opening.

[0403] Furthermore, as shown in FIG. 17A, an insulator 541a may be provided between the side surface of the opening in the region overlapping the conductor 542a and the conductor 540a as an insulator having a barrier property against impurities. Similarly, an insulator 541b may be provided between the side surface of the opening in the region overlapping the conductor 542b and the conductor 540b as an insulator having a barrier property against impurities. In this specification and the like, the insulator 541a and the insulator 541b are collectively referred to as the insulator 541.

[0404] It is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 540a and the conductor 540b. Also, the conductor 540a and the conductor 540b may have a laminated structure.

[0405] Also, when the conductor 540 has a laminated structure, for the first conductor disposed in the vicinity of the insulator 574, the insulator 576, the insulator 581, the insulator 580, the insulator 544, and the insulator 571, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminated form. Further, it is possible to suppress impurities such as water and hydrogen contained in the upper layer than the insulator 576 from mixing into the oxide 530 through the conductor 540a and the conductor 540b.

[0406] As the insulators 541a and 541b, a barrier insulating film that can be used for the insulator 544 or the like may be used. For example, as the insulators 541a and 541b, insulators such as silicon nitride, aluminum oxide, and silicon oxynitride may be used. Since the insulators 541a and 541b are provided in contact with the insulator 574, the insulator 576, and the insulator 571, it is possible to suppress impurities such as water and hydrogen contained in the insulator 580 from mixing into the oxide 530 through the conductors 540a and 540b. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. Also, it is possible to prevent oxygen contained in the insulator 580 from being absorbed by the conductors 540a and 540b.

[0407] When the insulators 541a and 541b are formed in a laminated structure as shown in FIG. 17A, it is preferable to use a combination of a first insulator in contact with the inner wall of the opening of the insulator 580 or the like and a second insulator inside thereof, which are a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0408] For example, aluminum oxide formed by ALD may be used as the first insulator, and silicon nitride formed by PEALD may be used as the second insulator. By adopting such a configuration, oxidation of the conductor 540 can be suppressed, and furthermore, the mixing of hydrogen into the conductor 540 can be reduced.

[0409] Note that in the transistor 500, a configuration in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are laminated is shown, but the present invention is not limited to this. For example, the insulator 541 may be provided in a single layer or a laminated structure of three or more layers. Also, in the transistor 500, a configuration in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are laminated is shown, but the present invention is not limited to this. For example, the conductor 540 may be provided in a single layer or a laminated structure of three or more layers.

[0410] Note that the structure of the transistor included in the semiconductor device according to one aspect of the present invention is not limited to the transistor 500 shown in FIGS. 16, 17A, and 17B. The structure of the transistor included in the semiconductor device according to one aspect of the present invention may be changed according to the situation.

[0411] Also, in the present embodiment, the transistor 180 included in the display unit DSP is a transistor having a bottom gate structure, but one aspect of the present invention is not limited thereto. For example, as shown in FIG. 19, the display device (display system) shown in FIG. 14A may have the same configuration as the OS transistor applicable to the transistor 180 included in the display unit DSP. Further, the display device (display system) shown in FIG. 19 may be provided with a layer OSC as shown in the display device (display system) shown in FIG. 20, similar to the display device (display system) shown in FIG. 16. That is, the display system according to one aspect of the present invention can have a configuration having a plurality of stacked OS transistors.

[0412] As described above, by providing the circuit unit SIC and the display unit DSP above the circuit unit SIC, a display device or a display system having functions such as an image processing function, an image correction function, a variable frame rate function, and a function using artificial intelligence (in this specification, the display device or the display system is referred to as an ultra-high-definition OLED system display) can be configured. Further, by providing a layer OSC between the circuit unit SIC and the circuit unit SIC, a transistor different from the transistor formed on the semiconductor substrate included in the circuit unit SIC can be provided, so that the design width can be widened in the peripheral circuit DRV and the functional circuit MFNC included in the circuit unit SIC. In addition, by providing a circuit in the layer OSC, an increase in the circuit area of the ultra-high-definition OLED system display can be prevented.

[0413] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0414] (Embodiment 4) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0415] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Further, it may contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0416] <Classification of crystal structure> First, the classification of the crystal structure in the oxide semiconductor will be described with reference to FIG. 21A. FIG. 21A is a diagram for explaining the classification of the crystal structure of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0417] As shown in FIG. 21A, the oxide semiconductor is roughly classified into "Amorphous", "Crystalline", and "Crystal". Further, "completely amorphous" is included in "Amorphous". Further, CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) are included in "Crystalline" (excluding single crystal and poly crystal). Note that single crystal, poly crystal, and completely amorphous are excluded from the classification of "Crystalline". Further, single crystal and poly crystal are included in "Crystal".

[0418] Note that the structure within the thick frame shown in FIG. 21A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). That is, the structure can be rephrased as a structure that is energetically unstable "Amorphous" and completely different from "Crystal".

[0419] Note that the crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD: X-Ray Diffraction) spectrum. Here, the XRD spectrum obtained by grazing-incidence XRD (GIXD) measurement of the CAAC-IGZO film classified as "Crystalline" is shown in FIG. 21B (the vertical axis represents the intensity in arbitrary units (a.u.)). Note that the GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in FIG. 21B may be simply referred to as the XRD spectrum. Note that the composition of the CAAC-IGZO film shown in FIG. 21B is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. Also, the thickness of the CAAC-IGZO film shown in FIG. 21B is 500 nm.

[0420] As shown in FIG. 21B, peaks indicating clear crystallinity are detected in the XRD spectrum of the CAAC-IGZO film. Specifically, in the XRD spectrum of the CAAC-IGZO film, a peak indicating c-axis orientation is detected in the vicinity of 2θ = 31°. Note that, as shown in FIG. 21B, the peak in the vicinity of 2θ = 31° is asymmetric about the angle at which the peak intensity was detected.

[0421] In addition, the crystal structure of the film or substrate can be evaluated by the diffraction pattern (also referred to as the nano beam electron diffraction pattern) observed by the nano beam electron diffraction method (NBED). The diffraction pattern of the CAAC-IGZO film is shown in FIG. 21C. FIG. 21C is a diffraction pattern observed by NBED in which the electron beam is incident parallel to the substrate. Note that the composition of the CAAC-IGZO film shown in FIG. 21C is in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio]. In the nano beam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0422] As shown in FIG. 21C, in the diffraction pattern of the CAAC-IGZO film, a plurality of spots indicating c-axis orientation are observed.

[0423] [Structure of Oxide Semiconductor] Note that when focusing on the crystal structure, the oxide semiconductor may be classified differently from that in FIG. 21A. For example, the oxide semiconductor can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include the above-described CAAC-OS and nc-OS. The non-single crystal oxide semiconductor also includes a polycrystalline oxide semiconductor, a pseudo-amorphous oxide semiconductor (a-like OS: amorphous-like oxide semiconductor), an amorphous oxide semiconductor, and the like.

[0424] Here, the details of the above-described CAAC-OS, nc-OS, and a-like OS will be described.

[0425] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystal regions, and the plurality of crystal regions have their c-axes oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. Also, a crystal region is a region having periodicity in the atomic arrangement. When the atomic arrangement is regarded as a lattice arrangement, the crystal region is also a region where the lattice arrangements are aligned. Further, CAAC-OS has a region where a plurality of crystal regions are connected in the a-b plane direction, and this region may have strain. The strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangements are aligned and another region where the lattice arrangements are aligned in the region where the plurality of crystal regions are connected. That is, CAAC-OS is an oxide semiconductor with c-axis orientation and no obvious orientation in the a-b plane direction.

[0426] Each of the plurality of crystal regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystal region is composed of one minute crystal, the maximum diameter of the crystal region is less than 10 nm. Also, when a crystal region is composed of a number of minute crystals, the size of the crystal region may be on the order of several tens of nm.

[0427] Also, in an In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M,Zn) layer) are laminated. Indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. The In layer may also contain Zn. The layered structure is observed as a lattice image, for example, in a high-resolution TEM image.

[0428] When performing structural analysis on a CAAC-OS film using, for example, an XRD apparatus, in the out-of-plane XRD measurement using θ / 2θ scan, a peak indicating c-axis orientation is detected at 2θ = 31° or in its vicinity. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type and composition of the metal elements constituting CAAC-OS.

[0429] Also, for example, in the electron diffraction pattern of a CAAC-OS film, a plurality of bright spots (spots) are observed. Note that one spot and another spot are observed at point-symmetric positions with the spot of the incident electron beam transmitted through the sample (also referred to as the direct spot) as the center of symmetry.

[0430] When observing the crystal region from the above specific direction, the lattice arrangement within the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. Also, in the above distortion, there may be a lattice arrangement such as a pentagon or a heptagon. Note that in CAAC-OS, even in the vicinity of the distortion, a clear grain boundary cannot be confirmed. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is considered to be because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal atoms.

[0431] Note that a crystal structure in which a clear grain boundary is confirmed is called a so-called polycrystal. Grain boundaries can become recombination centers and are likely to cause a decrease in the on-current of a transistor and a decrease in the field-effect mobility due to carrier capture. Therefore, CAAC-OS in which a clear grain boundary is not confirmed is one of the crystalline oxides having a crystal structure suitable for the semiconductor layer of a transistor. Note that for forming CAAC-OS, a configuration having Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are preferable because they can suppress the generation of grain boundaries more than In oxide.

[0432] CAAC-OS is an oxide semiconductor with high crystallinity and no distinct grain boundaries being confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is less likely to occur. Also, since the crystallinity of an oxide semiconductor may decrease due to impurity incorporation, defect generation, etc., CAAC-OS can also be said to be an oxide semiconductor with few impurities, defects (such as oxygen deficiencies), etc. Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. For this reason, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. Also, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, it becomes possible to expand the degree of freedom in the manufacturing process.

[0433] [nc-OS] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In other words, nc-OS has minute crystals. Note that since the size of the minute crystals is, for example, 1 nm or more and 10 nm or less, particularly 1 nm or more and 3 nm or less, the minute crystals are also called nanocrystals. Also, nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis is performed on an nc-OS film using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scan. Also, when electron beam diffraction (also called limited field electron beam diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more) is performed on the nc-OS film, a diffraction pattern like a halo pattern is observed. On the other hand, when electron beam diffraction (also called nanobeam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than that of the nanocrystals (for example, 1 nm or more and 30 nm or less) is performed on the nc-OS film, an electron beam diffraction pattern in which a plurality of spots are observed in a ring-shaped region centered on a direct spot may be obtained.

[0434] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a loose or low-density region. That is, the a-like OS has lower crystallinity compared to the nc-OS and the CAAC-OS. Also, the a-like OS has a higher hydrogen concentration in the film compared to the nc-OS and the CAAC-OS.

[0435] [[Constitution of Oxide Semiconductor]] Next, the details of the above-described CAC-OS will be described. Note that the CAC-OS relates to the material constitution.

[0436] [CAC-OS] The CAC-OS is, for example, a configuration of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element is in a state of being mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 3 nm or less, or in the vicinity thereof, which is also referred to as a mosaic state or a patch state.

[0437] Furthermore, the CAC-OS is a configuration in which the material is separated into a first region and a second region to form a mosaic state, and the first region is distributed in the film (hereinafter, also referred to as a cloud state). That is, the CAC-OS is a composite metal oxide having a configuration in which the first region and the second region are mixed.

[0438] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0439] Specifically, the above-mentioned first region is a region mainly composed of indium oxide, indium zinc oxide, etc. Also, the above-mentioned second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. That is, the above-mentioned first region can be rephrased as a region mainly composed of In. Also, the above-mentioned second region can be rephrased as a region mainly composed of Ga.

[0440] Note that there may be cases where no clear boundary can be observed between the above-mentioned first region and the above-mentioned second region.

[0441] For example, in the CAC-OS of In-Ga-Zn oxide, it can be confirmed by EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) that the region mainly composed of In (the first region) and the region mainly composed of Ga (the second region) are unevenly distributed and have a mixed structure.

[0442] When using CAC-OS in a transistor, the conductivity resulting from the first region and the insulating property resulting from the second region act complementarily, enabling the function of switching (turning on / off) to be imparted to the CAC-OS. That is, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximally enhanced. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching operation can be realized.

[0443] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0444] <Transistor having an oxide semiconductor> Subsequently, the case of using the above oxide semiconductor in a transistor will be described.

[0445] By using the above oxide semiconductor in a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0446] It is preferable to use an oxide semiconductor with a low carrier concentration in the transistor. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 or less, preferably 1×10 15 cm -3 or less, more preferably 1×10 13 cm -3 or less, even more preferably 1×10 11 cm -3 or less, still more preferably 1×10 10 cm -3 less, and 1×10 -9 cm-3 The above is the case. When reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be decreased and the density of defect levels may be decreased. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as highly pure intrinsic or substantially highly pure intrinsic. Note that an oxide semiconductor with a low carrier concentration may be referred to as a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0447] In addition, since an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0448] In addition, the time required for the charges trapped in the trap levels of the oxide semiconductor to disappear is long, and they may behave like fixed charges. Therefore, the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap levels may become unstable.

[0449] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0450] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0451] In an oxide semiconductor, when silicon or carbon, which is one of the group 14 elements, is contained, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are 2×10 18 atoms / cm 3 or less, preferably 2×10 17atoms / cm 3 Shall be as follows.

[0452] In addition, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less.

[0453] In addition, in the oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as the semiconductor tends to have normally-on characteristics. Or, in the oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to less than 5 × 10 19 atoms / cm 3 preferably less than 5 × 10 18 atoms / cm 3 more preferably 1 × 10 18 atoms / cm 3 or less, even more preferably 5 × 10 17 atoms / cm 3 or less.

[0454] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, electrons, which are carriers, may be generated. Also, a part of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that the hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 .

[0455] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be imparted.

[0456] Note that this embodiment can be appropriately combined with other embodiments described in this specification.

[0457] (Embodiment 5) In this embodiment, as an example of an electronic device according to one aspect of the present invention, an example of a head-mounted display to which at least one of a display device and a display system is applied will be described.

[0458] FIGS. 22A and 22B show the appearance of a head-mounted display 8300.

[0459] The head-mounted display 8300 includes a housing 8301, a display unit 8302, operation buttons 8303, and a band-shaped fixture 8304.

[0460] The operation button 8303 has functions such as a power button. In addition to the operation button 8303, there may be other buttons.

[0461] Also, as shown in FIG. 22C, a lens 8305 may be provided between the display unit 8302 and the position of the user's eyes. With the lens 8305, the user can enlarge the display unit 8302, enhancing the sense of presence. At this time, as shown in FIG. 22C, a dial 8306 for changing the position of the lens for visibility adjustment may be provided.

[0462] At least one of the display device and the display system according to an aspect of the present invention can be applied to the display unit 8302. Since at least one of the display device and the display system according to an aspect of the present invention has extremely high definition, even when enlarged using the lens 8305 as shown in FIG. 22C, a more realistic image can be displayed without the user visually recognizing the pixels.

[0463] FIGS. 22A to 22C show an example in the case of having one display unit 8302. By adopting such a configuration, the number of components can be reduced.

[0464] The display unit 8302 can display two images, an image for the right eye and an image for the left eye, side by side in two regions on the left and right. Thereby, a stereoscopic image using binocular parallax can be displayed.

[0465] Also, an image visible to both eyes may be displayed across the entire area of the display unit 8302. Thereby, since a panoramic image can be displayed across both ends of the visual field, the sense of reality is enhanced.

[0466] Here, it is preferable that the head-mounted display 8300 has a mechanism for changing the curvature of the display unit 8302 to an appropriate value according to the size of the user's head or the position of the eyes, etc. For example, the user may adjust the curvature of the display unit 8302 by operating a dial 8307 for adjusting the curvature of the display unit 8302. Alternatively, a sensor (such as a camera, a contact sensor, a non-contact sensor, etc.) for detecting the size of the user's head or the position of the eyes, etc. may be provided on the housing 8301, and it may have a mechanism for adjusting the curvature of the display unit 8302 based on the detection data of the sensor.

[0467] Also, when using the lens 8305, it is preferable to provide a mechanism for adjusting the position and angle of the lens 8305 in synchronization with the curvature of the display unit 8302. Alternatively, the dial 8306 may have a function of adjusting the angle of the lens.

[0468] FIGS. 22E and 22F show an example including a drive unit 8308 for controlling the curvature of the display unit 8302. The drive unit 8308 is fixed to at least a part of the display unit 8302. The drive unit 8308 has a function of deforming the display unit 8302 by deforming or moving the part fixed to the display unit 8302.

[0469] FIG. 22E is a schematic diagram when a user 8310 with a relatively large head size wears the housing 8301. At this time, the shape of the display unit 8302 is adjusted by the drive unit 8308 so that the curvature is relatively small (the radius of curvature is large).

[0470] On the other hand, FIG. 22F shows a case where a user 8311 with a smaller head size than the user 8310 wears the housing 8301. Also, the user 8311 has a narrower distance between both eyes compared to the user 8310. At this time, the shape of the display unit 8302 is adjusted by the drive unit 8308 so that the curvature of the display unit 8302 is large (the radius of curvature is small). In FIG. 22F, the position and shape of the display unit 8302 in FIG. 22E are shown by a dashed line.

[0471] In this way, the head-mounted display 8300 can provide an optimal display for various users of all ages and genders by having a mechanism for adjusting the curvature of the display unit 8302.

[0472] Also, by changing the curvature of the display unit 8302 according to the content displayed on the display unit 8302, a high sense of presence can be given to the user. For example, shaking can be expressed by vibrating the curvature of the display unit 8302. In this way, various effects can be produced according to the scenes in the content, and a new experience can be provided to the user. Further, at this time, by interlocking with the vibration module provided in the housing 8301, a display with a higher sense of presence becomes possible.

[0473] Note that the head-mounted display 8300 may have two display units 8302 as shown in FIG. 22D.

[0474] By having two display units 8302, the user can view one display unit for each eye. Thereby, even when performing three-dimensional display or the like using parallax, a high-resolution video can be displayed. Further, the display unit 8302 is curved in an arc shape centered approximately on the user's eyes. Thereby, since the distance from the user's eyes to the display surface of the display unit becomes constant, the user can view a more natural video. Also, even when the luminance and chromaticity of the light from the display unit change depending on the viewing angle, since the user's eyes are positioned in the normal direction of the display surface of the display unit, the influence can be substantially ignored, so a more realistic video can be displayed.

[0475] Note that the present embodiment can be appropriately combined with other embodiments shown in this specification.

[0476] (Embodiment 6) In this embodiment, a display module that can be manufactured using at least one of a display device and a display system according to an aspect of the present invention will be described.

[0477] The display module 6000 shown in FIG. 23A has a display device 6006, a frame 6009, a printed circuit board 6010, and a battery 6011 to which an FPC 6005 is connected between an upper cover 6001 and a lower cover 6002.

[0478] For example, at least one of a display device and a display system manufactured using an aspect of the present invention can be used for the display device 6006. With the display device 6006, a display module with extremely low power consumption can be realized.

[0479] The upper cover 6001 and the lower cover 6002 can be appropriately changed in shape and dimensions according to the size of the display device 6006.

[0480] The display device 6006 may have a function as a touch panel.

[0481] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0482] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0483] FIG. 23B is a schematic cross-sectional view of a display module 6000 including an optical touch sensor.

[0484] The display module 6000 has a light emitting portion 6015 and a light receiving portion 6016 provided on the printed circuit board 6010. Further, it has a pair of light guide portions (light guide portion 6017a, light guide portion 6017b) in a region surrounded by the upper cover 6001 and the lower cover 6002.

[0485] The display device 6006 is provided overlapping the printed circuit board 6010 and the battery 6011 with the frame 6009 therebetween. The display device 6006 and the frame 6009 are fixed to the light guide part 6017a and the light guide part 6017b.

[0486] The light 6018 emitted from the light emitting part 6015 passes through the upper part of the display device 6006 by the light guide part 6017a and reaches the light receiving part 6016 through the light guide part 6017b. For example, when the light 6018 is blocked by a detected object such as a finger or a stylus, a touch operation can be detected.

[0487] A plurality of light emitting parts 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving parts 6016 are provided at positions facing the light emitting parts 6015. Thereby, information on the position where the touch operation is performed can be acquired.

[0488] As the light emitting part 6015, a light source such as an LED element can be used, and in particular, a light source that emits infrared rays is preferably used. As the light receiving part 6016, a photoelectric element that receives the light emitted from the light emitting part 6015 and converts it into an electrical signal can be used. Preferably, a photodiode capable of receiving infrared rays can be used.

[0489] By the light guide part 6017a and the light guide part 6017b that transmit the light 6018, the light emitting part 6015 and the light receiving part 6016 can be arranged below the display device 6006, and it is possible to suppress external light from reaching the light receiving part 6016 and causing the touch sensor to malfunction. In particular, when a resin that absorbs visible light and transmits infrared rays is used, malfunction of the touch sensor can be more effectively suppressed.

[0490] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0491] (Embodiment 7) In this embodiment, an example of an electronic device to which at least one of a display device and a display system according to an aspect of the present invention can be applied will be described.

[0492] The electronic device 6500 shown in FIG. 24A is a portable information terminal that can be used as a smartphone.

[0493] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display unit 6502 has a touch panel function.

[0494] At least one of the display device and the display system according to an aspect of the present invention can be applied to the display unit 6502.

[0495] FIG. 24B is a schematic cross-sectional view including an end portion of the housing 6501 on the microphone 6506 side.

[0496] A protective member 6510 having translucency is provided on the display surface side of the housing 6501, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in a space surrounded by the housing 6501 and the protective member 6510.

[0497] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0498] Also, in a region outside the display unit 6502, a part of the display panel 6511 is folded back. An FPC 6515 is connected to the folded-back portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0499] The display panel 6511 can be, for example, a flexible display panel. Therefore, an extremely lightweight electronic device can be realized. Further, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while suppressing the thickness of the electronic device. Further, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, a narrow bezel electronic device can be realized.

[0500] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0501] (Embodiment 8) In this embodiment, an electronic device including at least one of a display device and a display system manufactured using one aspect of the present invention will be described.

[0502] The electronic devices exemplified below include at least one of a display device and a display system according to one aspect of the present invention in the display unit. Therefore, it is an electronic device with a high resolution realized. Further, it can be an electronic device that achieves both a high resolution and a large screen.

[0503] One aspect of the present invention has a display device and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0504] The electronic device according to one aspect of the present invention may have a secondary battery, and it is preferable that the secondary battery can be charged using non-contact power transmission.

[0505] Examples of the secondary battery include lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) using a gel electrolyte, nickel metal hydride batteries, nickel cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel zinc batteries, silver zinc batteries, and the like.

[0506] An electronic device according to one aspect of the present invention may have an antenna. By receiving a signal with the antenna, it is possible to display video, information, etc. on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for wireless power transmission.

[0507] On the display unit of the electronic device according to one aspect of the present invention, it is possible to display a video having a resolution such as full high vision, 4K2K, 8K4K, 16K8K, or higher.

[0508] Examples of the electronic device include, in addition to electronic devices having a relatively large screen such as a television device, a notebook personal computer, a monitor device, a digital signage, a pachinko machine, and a game machine, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio playback device, and the like.

[0509] The electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of an inner wall or an outer wall of a building such as a house or a building, or an interior or exterior of an automobile or the like.

[0510] FIG. 25A is a view showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0511] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000.

[0512] Note that the lens 8006 and the housing of the camera 8000 may be integrated.

[0513] The camera 8000 can perform imaging by pressing the shutter button 8004 or touching the display unit 8002 that functions as a touch panel.

[0514] The housing 8001 has a mount with electrodes and can connect a finder 8100, a strobe device, etc.

[0515] The finder 8100 has a housing 8101, a display unit 8102, and buttons 8103.

[0516] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The finder 8100 can display images and the like received from the camera 8000 on the display unit 8102.

[0517] The button 8103 functions as a power button or the like.

[0518] At least one of the display device and the display system according to an aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the finder 8100. Note that the camera 8000 may have a built-in finder.

[0519] FIG. 25B is a diagram showing the appearance of an information terminal 5900 which is an example of a wearable terminal. The information terminal 5900 has a housing 5901, a display unit 5902, operation buttons 5903, a lens 5904, a band 5905, etc.

[0520] By applying at least one of the display device and the display system described in the above embodiment to the wearable terminal, a high-quality image can be displayed on the display unit 5902.

[0521] FIG. 25C is a diagram showing the appearance of a portable game machine 5200 which is an example of a game machine. The portable game machine 5200 has a housing 5201, a display unit 5202, buttons 5203, etc.

[0522] In addition, the video of the portable game machine 5200 can be output by a display device such as a television device, a personal computer display, a game display, a head-mounted display.

[0523] By applying at least one of the display device and the display system described in the above embodiment to the portable game machine 5200, a high-quality image can be displayed on the display unit 5202. In addition, a portable game machine 5200 with low power consumption can be realized. Further, due to the low power consumption, heat generation from the circuit can be reduced, so that the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0524] FIG. 26A is a view showing the appearance of the head-mounted display 8200.

[0525] The head-mounted display 8200 includes a mounting part 8201, a lens 8202, a main body 8203, a display part 8204, a cable 8205, etc. Further, a battery 8206 is built in the mounting part 8201.

[0526] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 is provided with a wireless receiver or the like, and can display the received video information on the display part 8204. Further, the main body 8203 is provided with a camera, and information on the movement of the user's eyeball or eyelid can be used as input means.

[0527] Further, the mounting part 8201 may be provided with a plurality of electrodes capable of detecting an electric current flowing along with the movement of the user's eyeball at a position where it touches the user, and may have a function of recognizing the line of sight. Further, it may have a function of monitoring the user's pulse by the electric current flowing through the electrodes. Further, the mounting part 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display part 8204, a function of changing the video displayed on the display part 8204 in accordance with the movement of the user's head, and the like.

[0528] At least one of the display device and the display system according to an aspect of the present invention can be applied to the display part 8204.

[0529] FIG. 26B, FIG. 26C, and FIG. 26D are diagrams showing the appearance of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0530] The user can view the display of the display unit 8302 through the lenses 8305. It is preferable to arrange the display unit 8302 in a curved manner because the user can feel a high sense of immersion. In addition, by viewing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the configuration is not limited to providing one display unit 8302, and two display units 8302 may be provided, with one display unit arranged for each eye of the user.

[0531] Note that at least one of the display device and the display system according to an aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to an aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in FIG. 26D, a more realistic image can be displayed without the user being able to visually recognize the pixels.

[0532] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

Description of Reference Numerals

[0533] DSP: Representation unit, OSC: Layer, SIC: Circuit unit, CHP: Circuit unit, DRV: Peripheral circuit, MFNC: Functional circuit, MFNCa: Functional circuit, MFNCb: Functional circuit, DRVa: Circuit, DRVb: Circuit, MDV: Memory device, PX: Pixel, MC: Memory cell, GL: Wiring, SL: Wiring, SNCL: Wiring, ML: Wiring, BSL: Bus wiring, MC1: Memory cell, MC2: Memory cell, MC2A: Memory cell, MC3: Memory cell, MC4: Memory cell, MC5: Memory cell, MC6: Memory cell, M1: Transistor, M2: Transistor, M3: Transistor, M10: Transistor, M11: Transistor, CA: Capacitance, CB: Capacitance, ME: MTJ element, FL: Layer, TIS: Layer, RL: Layer, RM: Resistance change element, PCM1: Phase change memory, TE: Electrode, CHL: Phase change layer, BE: Electrode, FEA: Ferroelectric capacitor, WOL: Wiring, BIL: Wiring, CVL: Wiring, BGL: Wiring, CAL: Wiring, RBL: Wiring, WBL: Wiring, SOL: Wiring, WL: Wiring, BL: Wiring, FCA: Wiring, HMD: Electronic device, EXDV: Device, EXDV1: Device, EXDV2: Device, EXDV3: Device, RFS: RF signal, CLD: Cloud computing, HP: Headphone unit, FG: Finger, HND: Hand, DPC: Display image, OPA: Operation area, ICN: Icon, 11: Source driver circuit, 12: Digital-to-analog conversion circuit, 13: Gate driver circuit, 14: Level shifter, 21: Memory device, 22: GPU, 22a: Circuit, 22b: Circuit, 23: EL correction circuit, 24: Timing controller, 25: CPU, 26: Sensor controller, 27: Power supply circuit, 31: Memory control circuit, 41: High-frequency circuit, 41a: High-frequency circuit, 41b: High-frequency circuit, 100: Display device, 100A: Display device, 101: Substrate, 116: Insulator, 117: Insulator, 118: Insulator, 126: Conductor, 127: Conductor, 128: Conductor, 170: Transistor, 171: Element isolation layer, 172a: Low-resistance region, 172b: Low-resistance region, 173: Semiconductor region, 174: Insulator, 175: Conductor, 180: Transistor, 200: Display system, 200A: Display system, 200B: Display system, 200C: Display system, 200D: Display system, 211: Conductor, 212: Conductor, 221: Insulator, 222: Insulator, 223: Insulator, 224: Insulator, 231: Semiconductor,251: Insulator, 260R: Light-emitting device, 260G: Light-emitting device, 260B: Light-emitting device, 260W: Light-emitting device, 261: Pixel electrode, 262R: EL layer, 262G: EL layer, 262B: EL layer, 262W: EL layer, 262a: EL layer, 262b: EL layer, 263: Common electrode, 264R: Coloring layer, 264G: Coloring layer, 264B: Coloring layer, 271: Protective layer, 272: Insulator, 500: Transistor, 503: Conductor, 503a: Conductor, 503b: Conductor, 512: Insulator, 514: Insulator, 516: Insulator, 522: Insulator, 524: Insulator, 530: Oxide, 530a: Oxide, 530b: Oxide, 530ba: Region, 530bb: Region, 530bc: Region, 540: Conductor, 540a: Conductor, 540b: Conductor, 541: Insulator, 541a: Insulator, 541b: Insulator, 542: Conductor, 542a: Conductor, 542b: Conductor, 544: Insulator, 550: Insulator, 550a: Insulator, 550b: Insulator, 552: Insulator, 554: Insulator, 560: Conductor, 560a: Conductor, 560b: Conductor, 571: Insulator, 571a: Insulator, 571b: Insulator, 574: Insulator, 576: Insulator, 580: Insulator, 581: Insulator, 4411: Light-emitting layer, 4412: Light-emitting layer, 4413: Light-emitting layer, 4420: Layer, 4430: Layer, 5200: Portable game machine, 5201: Housing, 5202: Display unit, 5203: Button, 5900: Information terminal, 5901: Housing, 5902: Display unit, 5903: Operation button, 5904: Fuse, 5905: Band, 6000: Display module, 6001: Upper cover, 6002: Lower cover, 6005: FPC, 6006: Display device, 6009: Frame, 6010: Printed circuit board, 6011: Battery, 6015: Light-emitting part, 6017a: Light guide part, 6017b: Light guide part, 6018: Light, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6510: Protective member, 6511: Display panel, 6512: Optical member, 6513: Touch sensor panel, 6515: FPC, 6516: IC, 6517: Printed circuit board, 6518: Battery, 8000: Camera, 8001: Housing, 8002: Display unit, 8003: Operation button, 8004: Shutter button, 8006: Lens,8100: Finder, 8101: Housing, 8102: Display unit, 8103: Button, 8200: Head-mounted display, 8201: Mounting part, 8202: Lens, 8203: Main body, 8204: Display unit, 8205: Cable, 8206: Battery, 8300: Head-mounted display, 8301: Housing, 8302: Display unit, 8303: Operation button, 8304: Fixture, 8305: Lens, 8306: Dial, 8307: Dial, 8308: Driving unit, 8310: User, 8311: User,

Claims

1. It has a first layer, a second layer, and a display unit, The display unit is located in an area overlapping the first layer, The second layer is located in an area overlapping the first layer, The first layer has a semiconductor substrate made of silicon, The first layer has a plurality of first transistors and a plurality of second transistors that include the silicon in a channel formation region, The second layer has a plurality of third transistors that include a metal oxide in a channel formation region, The first layer has a first circuit and a second circuit, The first circuit has a source driver circuit and a gate driver circuit, each of which includes the first transistor, The second circuit has a memory device, a GPU, an EL correction circuit, and a timing controller, each of which includes the second transistor, The third transistor functions as a transistor included in the memory device included in the first layer, The display unit has pixels, The pixel has a light-emitting device including organic EL, The pixel is electrically connected to the source driver circuit and the gate driver circuit, The memory device has a function of holding image data, The GPU has a function of decoding the image data read from the memory device, The source driver circuit has a function of transmitting the decoded image data to the pixel, The EL correction circuit has a function of correcting the luminance of light emitted by the light-emitting device, The timing controller has a function of increasing or decreasing the frame rate at which an image is displayed on the display unit. A display system.

2. In claim 1, The second layer has memory cells. A display system. **Claim 3** In claim 1 or claim 2, the second circuit has a CPU including the second transistor, and the CPU has a function of transmitting a control signal to one or more selected from the storage device, the GPU, the EL correction circuit, and the timing controller. A display system. **Claim 4** In claims 1 to 3, the GPU has a function of performing an operation of an artificial neural network and correcting an image displayed on the display unit based on the result of the operation. A display system. **Claim 5** In claims 1 to 4, the metal oxide is indium oxide. A display system. **Claim 6** An electronic device having the display system according to any one of claims 1 to 5 and a housing. An electronic device.

Images