Signal generation device, signal generation method, and computer program

Abstract

A signal generating device comprising a digital signal processing unit, a plurality of sub digital analog converting units that convert each of a plurality of digital signals output by the digital signal processing unit into an analog signal, and an analog multiplexer that multiplexes the analog signal output by each of the plurality of sub digital analog converting units to generate a broad-band signal, wherein the digital signal processing unit includes: a band dividing unit that divides an input signal by a frequency width that is a common divisor of the Nyquist frequencies of the plurality of sub digital analog converting units and the clock frequency of the analog multiplexer to generate N (N is the partition function) divided signals; a spectrum folding unit that, where the N divided signals generated by the band dividing unit diverge on respective paths, generates N folded divided signals corresponding to the N divided signals by folding back the diverged N divided signals on the frequency axis to take the complex conjugate; a filter that uses the N divided signals and the N folded divided signals as input to generate N composite signals; and a band synthesizing unit that uses the N composite signals as input to generate a plurality of digital signals corresponding to the sub digital analog converting units.　

Description

Technical Field

[0001] The present invention relates to a signal generation device, a signal generation method, and a computer program.

Background Art

[0002] High-quality high-speed signal generation technology for increasing the capacity of optical transmission has been attracting attention. As such a technology, for example, a signal generation device has been proposed that divides a target input signal into low frequency and high frequency, and pre-equalizes the divided signal and the complex conjugate signal of the divided signal by MIMO (Multiple Input Multiple Output) processing (see, for example, Patent Document 1).

[0003] FIG. 3 is a diagram showing a configuration example of a conventional signal generation device 100. The signal generation device 100 includes a band division unit 611, a spectrum folding unit 612, a filter 613, a plurality of SubDACs (Sub Digital Analog Converters) 121, 122, and an analog multiplexer 131. In the band division unit 611, the input signal is divided into low frequency and high frequency. The spectrum folding unit 612 generates a complex conjugate signal of the divided signal. The filter 613 takes each divided signal and each complex conjugate signal as inputs, and generates a plurality of composite signals to be transmitted to the plurality of SubDACs 121, 122. The SubDACs 121, 122 convert the plurality of composite signals output from the filter 613 into a plurality of analog signals. The analog multiplexer 131 takes the plurality of analog signals as inputs and generates a high-speed signal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the signal generation method by a conventional signal generation device, in a driving condition where aliasing occurs in the output signal of the SubDAC (for example, when driving the SubDAC at a sampling frequency at which the Nyquist frequency is smaller than the analog band of the SubDAC), it is impossible to compensate for the interference of the aliasing image due to the zero-time hold of the SubDAC, and there is a problem that the frequency domain cannot be fully utilized in the generation of a broadband signal.

[0006] FIG. 4 and FIG. 5 are diagrams for explaining problems in a conventional signal generation device. In FIG. 4 and FIG. 5, the sampling frequency of the SubDAC is 126 GS / s (Giga sample per second), and the frequency of the clock input to the analog multiplexer is 42 GHz. As shown in FIG. 4, in the case of a driving condition where aliasing occurs in the output signal of the SubDAC, the maximum frequency becomes 84 GHz, and it can be seen that the maximum frequency is limited. Therefore, the sampling frequency of the SubDAC cannot be fully utilized. As shown in FIG. 5, when there is aliasing in the SubDAC, interference occurs in the target high-speed signal due to the aliasing component.

[0007] In view of the above circumstances, an object of the present invention is to provide a technology capable of fully utilizing the frequency domain to generate a high-speed signal.

Means for Solving the Problem

[0008] One aspect of the present invention includes a digital signal processing unit, a plurality of sub-digital-to-analog conversion units that each convert a plurality of digital signals output from the digital signal processing unit into analog signals, and an analog multiplexer that multiplexes the analog signals output from each of the plurality of sub-digital-to-analog conversion units to generate a broadband signal. The digital signal processing unit includes a band division unit that divides an input signal into frequency bands each having a frequency width that is a common divisor of the Nyquist frequency of the plurality of sub-digital-to-analog conversion units and the clock frequency of the analog multiplexer, and generates N (where N is the number of divisions) divided signals; a spectrum folding unit that branches the N divided signals generated by the band division unit on the path, folds the branched N divided signals on the frequency axis, and takes the complex conjugate to generate N folded divided signals corresponding to the N divided signals; a filter that takes the N divided signals and the N folded divided signals as inputs and generates N composite signals; and a band synthesis unit that takes the N composite signals as inputs and generates a plurality of digital signals corresponding to each sub-digital-to-analog conversion unit.

[0009] One aspect of the present invention is a signal generation method, in which a digital signal processing unit divides an input signal into frequency bands each having a frequency width that is a common divisor of the Nyquist frequency of a plurality of sub-digital-to-analog conversion units and the clock frequency of an analog multiplexer, and generates N (where N is the number of divisions) divided signals; the digital signal processing unit branches the N divided signals generated on the path, folds the branched N divided signals on the frequency axis, and takes the complex conjugate to generate N folded divided signals corresponding to the N divided signals; the digital signal processing unit takes the N divided signals and the N folded divided signals as inputs and generates N composite signals; the digital signal processing unit takes the N composite signals as inputs and generates a plurality of digital signals corresponding to each sub-digital-to-analog conversion unit; the plurality of sub-digital-to-analog conversion units each convert a plurality of digital signals output from the digital signal processing unit into analog signals; and the analog multiplexer multiplexes the analog signals output from each of the plurality of sub-digital-to-analog conversion units to generate a broadband signal.

[0010] One aspect of the present invention is a computer program for causing a computer to function as the above-described signal generation device.

Effects of the Invention

[0011] According to the present invention, it becomes possible to generate a high-speed signal by sufficiently utilizing the frequency domain.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a specific example of the functional configuration of a signal generation device 10 in the present invention. The signal generation device 10 includes a digital signal processing unit 11, a plurality of SubDACs 12-1 and 12-2, and an analog multiplexer 13. In the example shown in FIG. 1, the case where the number of SubDACs 12 is two is illustrated, but it is applicable when the number of SubDACs 12 is three or more.

[0014] The digital signal processing unit 11 performs digital signal processing on the input signal z(t) to generate digital signals to be sent to each of the SubDACs 12-1 and 12-2 so that a desired analog signal can be obtained as the final output signal c(t) according to the characteristics of the analog multiplexer 13.

[0015] SubDAC12-1 and SubDAC12-2 convert a plurality of digital signals output from the digital signal processing unit 11 into analog signals respectively. For example, SubDAC12-1 converts the digital signal output from the digital signal processing unit 11 into an analog signal a(t), and SubDAC12-2 converts the digital signal output from the digital signal processing unit 11 into an analog signal b(t). In the present invention, SubDAC12-1 and SubDAC12-2 are driven at a sampling frequency at which the Nyquist frequency is smaller than the analog bandwidth of SubDAC12-1 and SubDAC12-2.

[0016] The analog multiplexer 13 multiplexes the analog signals a(t) and b(t) output from SubDAC12-1 and SubDAC12-2 respectively to generate an output signal c(t) which is a broadband signal. Specific configuration examples of the analog multiplexer 13 include a configuration using the analog multiplexer shown in FIG. 2 of Patent Document 1, a configuration using a mixer and a combiner shown in FIG. 3 of Patent Document 1, an IQ modulator type configuration including a mixer, a combiner, and a 90-degree phase shifter shown in FIG. 4 of Patent Document 1, etc.

[0017] In this example, as the configuration of the analog multiplexer 13, a configuration using an analog multiplexer will be described. The analog multiplexer is a switch (selector) circuit that outputs each analog signal output from each SubDAC12 while switching at a high speed with a clock frequency f clk .

[0018] The digital signal processing unit 11 includes a band division unit 111, a spectrum folding unit 112, a filter 113, and a band synthesis unit 114.

[0019] The band division unit 111 divides the Nyquist frequencies of SubDAC12-1 and SubDAC12-2 and the input clock (clock frequency f clk) For each frequency width of a number represented by the greatest common divisor with , the input signal is divided to generate a plurality of divided signals. In the example shown in this embodiment, assume that the sampling frequencies Fs of SubDAC12-1 and 12-2 are 126 GS / s, and the input clock of analog multiplexer 13 is 42 GHz. Note that the sampling frequencies of SubDAC12-1 and 12-2 and the input clock of analog multiplexer 13 are not limited to the above example.

[0020] In the case of the above example, the Nyquist frequency of SubDAC12-1 and 12-2 is Fs / 2 = 63. In this case, the greatest common divisors of the Nyquist frequency of SubDAC12-1 and 12-2 and the input clock of analog multiplexer 13 are "1" and "21". For example, the band division unit 111 divides the input signal for each frequency width of 21 GHz, which is the greatest common divisor, to generate a plurality of divided signals (for example, in the example of FIG. 1, divided signals C0, C1, C2, C3, C4, C5). In this way, the band division unit 111 divides the input signal into N parts to generate N divided signals. N is the number obtained by dividing the sampling frequency Fs (for example, 126) of SubDAC12-1 and 12-2 by a number represented by the greatest common divisor (for example, 21). In the following description, N = 6 will be used for explanation. Note that, as an example, the configuration in which the band division unit 111 divides the input signal for each frequency width of the greatest common divisor is shown. However, if there are a plurality of greatest common divisors other than "1", the band division unit 111 may divide the input signal for each frequency width of other greatest common divisors as long as they are greatest common divisors other than "1".

[0021] The spectrum folding unit 112 generates a plurality of folded divided signals (for example, divided signals ~C0, ~C1, ~C2, ~C3, ~C4, ~C5) corresponding to the plurality of divided signals by folding the plurality of divided signals (for example, divided signals C0, C1, C2, C3, C4, C5) generated by the band division unit 111 about DC (Direct Current) on the frequency axis and taking the complex conjugate. Note that ~ is placed above the character (for example, C).

[0022] Filter 113 takes as inputs a plurality of divided signals C0, C1, C2, C3, C4, C5 generated by the band division unit 111 and a plurality of folded divided signals ~C0, ~C1, ~C2, ~C3, ~C4, ~C5 generated by the spectrum folding unit 112, and outputs a plurality of composite signals A L , A M , A H , B L , B M , B H and generates them. Filter 113 is a 2N×N (for example, 12×6) filter. For example, the filter 113 shown in FIG. 1 is composed of 2N×N convolution operation units (not shown) and N addition units 116-1 to 116-N (addition units 116-1 to 116-6).

[0023] The 2N×N convolution operation units multiply an independently set response function to the input plurality of divided signals or the plurality of folded divided signals. In FIG. 1, for the sake of drawing relationship, the description of the 2N×N convolution operation units is omitted, but the plurality of divided signals and the plurality of folded divided signals input to the filter 113 are multiplied by the response function by the 2N×N convolution operation units and then input to all the addition units 116-1 to 116-N (addition units 116-1 to 116-6).

[0024] When N = 6, the filter 113 is configured as a 12-input 6-output filter and includes 72 convolution operation units and 6 addition units 116-1 to 116-6. The plurality of divided signals and the plurality of folded divided signals input to the filter 113 are each branched into N paths and the response function is multiplied by the N convolution operation units provided in the N paths.

[0025] For example, when the split signal C0 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the first to sixth convolution operation units provided in the six paths. Similarly, when the split signal C1 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the seventh to twelfth convolution operation units provided in the six paths. Similarly, when the split signal C2 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the thirteenth to eighteenth convolution operation units provided in the six paths. Similarly, when the split signal C3 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the nineteenth to twenty-fourth convolution operation units provided in the six paths. Similarly, when the split signal C4 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the twenty-fifth to thirtieth convolution operation units provided in the six paths. Similarly, when the split signal C5 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the thirty-first to thirty-sixth convolution operation units provided in the six paths.

[0026] When the folded split signal ~C0 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the 37th to 42nd convolution operation units provided in the six paths. Similarly, when the folded split signal ~C1 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the 43rd to 48th convolution operation units provided in the six paths. Similarly, when the folded split signal ~C2 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the 49th to 54th convolution operation units provided in the six paths. Similarly, when the folded split signal ~C3 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the 55th to 60th convolution operation units provided in the six paths. Similarly, when the folded split signal ~C4 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the 61st to 66th convolution operation units provided in the six paths. Similarly, when the folded split signal ~C5 is input to the filter 113, it is branched into six paths, and the response function is multiplied by the 67th to 72nd convolution operation units provided in the six paths.

[0027] In FIG. 1, a configuration is illustrated in which the response function is multiplied by the split signal C0 and input to all the adder units 116-1 to 116-6. However, for other split signals (for example, split signals C1, C2, C3, C4, C5) and a plurality of folded split signals (for example, split signals ~C0, ~C1, ~C2, ~C3, ~C4, ~C5), the response function is similarly multiplied by any one of the 2N×N convolution operation units and input to all the adder units 116-1 to 116-6.

[0028] Based on the above-described case of N = 6, the addition unit 116-1 receives the divided signal C0 multiplied by the response function by the first convolution operation unit, the divided signal C1 multiplied by the response function by the seventh convolution operation unit, the divided signal C2 multiplied by the response function by the thirteenth convolution operation unit, the divided signal C3 multiplied by the response function by the nineteenth convolution operation unit, the divided signal C4 multiplied by the response function by the twenty-fifth convolution operation unit, the divided signal C5 multiplied by the response function by the thirty-first convolution operation unit, the folded divided signal ~C0 multiplied by the response function by the thirty-seventh convolution operation unit, the folded divided signal ~C1 multiplied by the response function by the forty-third convolution operation unit, the folded divided signal ~C2 multiplied by the response function by the forty-ninth convolution operation unit, the folded divided signal ~C3 multiplied by the response function by the fifty-fifth convolution operation unit, the folded divided signal ~C4 multiplied by the response function by the sixty-first convolution operation unit, and the folded divided signal ~C5 multiplied by the response function by the sixty-seventh convolution operation unit. In this way, N divided signals and N folded divided signals are input to one addition unit 116.

[0029] The addition units 116-1 to 116-6 add the divided signal multiplied by the response function by the convolution operation unit and the folded divided signal to generate a composite signal. For example, the addition unit 116-1 adds N divided signals multiplied by the response function by the (6k + 1)-th (k is 0 to (2N - 1)) convolution operation unit and N folded divided signals to generate the composite signal A L Similarly, the addition unit 116-2 adds N divided signals multiplied by the response function by the (6k + 2)-th convolution operation unit and N folded divided signals to generate the composite signal A M Similarly, the addition unit 116-3 adds N divided signals multiplied by the response function by the (6k + 3)-th convolution operation unit and N folded divided signals to generate the composite signal A H Similarly, the addition unit 116-4 adds N divided signals multiplied by the response function by the (6k + 4)-th convolution operation unit and N folded divided signals to generate the composite signal B Lto generate. Similarly, the adder 116-5 adds the N divided signals multiplied by the response function by the (6k + 5)-th convolution operation unit and the N folded divided signals to generate the composite signal B M to generate. Similarly, the adder 116-6 adds the N divided signals multiplied by the response function by the (6k + 6)-th convolution operation unit and the N folded divided signals to generate the composite signal B H to generate.

[0030] Thus, the filter 113 is a filter that obtains a composite signal by multiplying a plurality of divided signals and a plurality of folded divided signals by independently settable response functions and then superimposing them.

[0031] Here, the response functions used for convolution by the 2N×N convolution operation units are calculated as coefficients such that the output signal c(t) approaches the input signal z(t) when output via the analog multiplexer 13.

[0032] The band synthesis unit 114 inputs a plurality of composite signals A L , A M , A H , B L , B M , B H and generates a plurality of digital signals corresponding to SubDACs 12-1 and 12-2 respectively. The band synthesis unit 114 is composed of a first band synthesis unit 115-1 and a second band synthesis unit 115-2. The first band synthesis unit 115-1 synthesizes the bands of the composite signals A L , A M , A H generated by the respective adders 116-1 to 116-3 to generate a first composite signal 15-1 for output to SubDAC 12-1. The second band synthesis unit 115-2 synthesizes the bands of the composite signals B L , B M , B H generated by the respective adders 116-4 to 116-6 to generate a second composite signal 15-2 for output to SubDAC 12-2.

[0033] Figure 2 is a diagram for explaining the operating principle of the present invention. In Figure 2, an example is shown where the sampling frequency of SubDAC12 is 126 GS / s and the clock frequency of analog multiplexer 13 is 42 GHz. As shown in Figure 2, alias components are generated symmetrically with respect to the Nyquist frequency of 63 GHz. A shown in Figure 2 L ,A M ,A H ,B L ,B M ,B H represents a composite signal, ~A L ,~A M ,~A H ,~B L ,~B M ,~B H (~ is placed above A and B) represents a signal obtained by taking the complex conjugate of the composite signal. "L", "M", "H" with subscripts of "A" and "B" represent Low, High, and Middle, respectively.

[0034] As described above, by considering a 21 GHz × 6 segment band, it becomes possible to digitally cancel alias components through a 12 × 12 matrix operation including folded split signals and obtain a desired signal. As a result, it becomes possible to operate as a 252 GS / s DAC (the upper limit is 210 GS / s in the conventional configuration without aliases).

[0035] By solving the simultaneous equations from the relationships shown in Figure 2 and obtaining A L ,A M, A H ,B L ,B M ,B H , it is possible to calculate desired C0, C1, C2, C3, C4, C5, C6 even when an alias signal is generated from subDAC12.

[0036] According to the signal generation device 10 configured as described above, the digital signal processing unit 11 divides the input signal into a plurality of divided signals for each frequency width that is a common divisor of the Nyquist frequencies of the plurality of SubDACs 12 and the clock frequency of the analog multiplexer 13, and the plurality of divided signals are branched on the path. By folding back the branched plurality of divided signals on the frequency axis and taking the complex conjugate, a plurality of folded-back divided signals corresponding to the plurality of divided signals are generated. Using the plurality of divided signals and the plurality of folded-back divided signals as inputs, a plurality of composite signals are generated, and using the plurality of composite signals as inputs, a plurality of digital signals corresponding to each SubDAC 12 are generated.

[0037] In this way, the signal generation device 10 divides the input signal into sub-bands having a bandwidth that is a common divisor of the Nyquist frequency (half of the sampling frequency) of the SubDAC 12 and the clock frequency input to the analog multiplexer 13, pre-equalizes the sub-band signal and its complex conjugate signal by MIMO processing, and assigns the equalized sub-band signal to each band of the SubDAC 12, thereby enabling compensation for interference caused by aliasing images, digitally canceling the aliasing components by matrix operations including the inverted signal, and obtaining a desired signal. Therefore, it becomes possible to generate a high-speed signal by effectively utilizing the frequency band of the SubDAC 12.

[0038] A part of the functional units of the signal generation device 10 in the above-described embodiment may be realized by a computer. In that case, a program for realizing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed to realize it. Here, the "computer system" is assumed to include hardware such as an OS and peripheral devices.

[0039] In addition, the "computer-readable recording medium" refers to a portable medium such as a flexible disk, a magneto-optical disk, a ROM (Read Only Memory), a CD-ROM, etc., and a storage device such as a hard disk built into a computer system. Furthermore, the "computer-readable recording medium" also includes those that dynamically hold a program for a short period of time, like a communication line when transmitting a program via a network such as the Internet or a communication line such as a telephone line, and those that hold a program for a certain period of time, like the volatile memory inside a computer system that serves as a server or a client in that case. Also, the above program may be for realizing a part of the functions described above, and may further be realized in combination with a program already recorded in the computer system for realizing the functions described above, or may be realized using a programmable logic device such as an FPGA (Field-Programmable Gate Array).

[0040] As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and designs and the like within the scope not departing from the gist of the present invention are also included.

Industrial Applicability

[0041] The present invention can be applied to the technology of generating high-speed signals.

Explanation of Signs

[0042] 10… Signal generation device, 11… Digital signal processing unit, 12-1, 12-2… SubDAC, 13… Analog multiplexer, 111… Band division unit, 112… Spectrum folding unit, 113… Filter, 114… Band synthesis unit, 115-1… First band synthesis unit, 115-2… Second band synthesis unit

Claims

1. A digital signal processing unit, a plurality of sub-digital-to-analog conversion units that respectively convert a plurality of digital signals output from the digital signal processing unit into analog signals, an analog multiplexer that multiplexes the analog signals output from each of the plurality of sub-digital-to-analog conversion units to generate a broadband signal, comprising: the digital signal processing unit divides an input signal into N (N is the number of divisions) divided signals for each frequency width that is a common divisor of the Nyquist frequency of the plurality of sub-digital-to-analog conversion units and the clock frequency of the analog multiplexer, and a band division unit that generates the divided signals; the N divided signals generated by the band division unit are branched on the path, and by folding the branched N divided signals on the frequency axis and taking the complex conjugate, an N-folded divided signal corresponding to the N divided signals is generated. A spectrum folding unit; a filter that takes the N divided signals and the N folded divided signals as inputs and generates N composite signals; including a band synthesis unit that takes the N composite signals as inputs and generates a plurality of digital signals corresponding to each sub-digital-to-analog conversion unit, the band synthesis unit is composed of a plurality of band synthesis units that generate digital signals for each sub-digital-to-analog conversion unit, each band synthesis unit generates a digital signal for each sub-digital-to-analog conversion unit by synthesizing the bands of different composite signals, a signal generation device.

2. A digital signal processing unit, a plurality of sub-digital-to-analog conversion units that respectively convert a plurality of digital signals output from the digital signal processing unit into analog signals, an analog multiplexer that multiplexes the analog signals output from each of the plurality of sub-digital-to-analog conversion units to generate a broadband signal, comprising: the digital signal processing unit divides an input signal into N (N is the number of divisions) divided signals for each frequency width that is a common divisor of the Nyquist frequency of the plurality of sub-digital-to-analog conversion units and the clock frequency of the analog multiplexer, and a band division unit that generates the divided signals; the N divided signals generated by the band division unit are branched on the path, and by folding the branched N divided signals on the frequency axis and taking the complex conjugate, an N-folded divided signal corresponding to the N divided signals is generated. A spectrum folding unit; A filter that takes the N split signals and the N folded split signals as inputs and generates N composite signals, including a band synthesis unit that takes the N composite signals as inputs and generates a plurality of digital signals corresponding to each sub-digital-to-analog conversion unit, the filter is composed of 2N×N convolution operation units and N addition units, the 2N×N convolution operation units take the N split signals and the N folded split signals as inputs, multiply the input N split signals and the N folded split signals by a response function, the N addition units output the N composite signals obtained by adding the N split signals multiplied by the response function and the N folded split signals multiplied by the response function to the band synthesis unit, a signal generation device.

3. The Nyquist frequency of the plurality of sub-digital-to-analog conversion units is greater than the clock frequency of the analog multiplexer. The signal generation device according to claim 1 or 2.

4. The digital signal processing unit divides an input signal into N (N is the number of divisions) split signals for each frequency width of the greatest common divisor of the Nyquist frequencies of the plurality of sub-digital-to-analog conversion units and the clock frequency of the analog multiplexer, the digital signal processing unit branches the generated N split signals on the path, and generates N folded split signals corresponding to the N split signals by folding the branched N split signals on the frequency axis and taking the complex conjugate, the digital signal processing unit takes the N split signals and the N folded split signals as inputs and generates N composite signals, the digital signal processing unit takes the N composite signals as inputs and generates a plurality of digital signals corresponding to each sub-digital-to-analog conversion unit, a plurality of sub-digital-to-analog conversion units respectively convert the plurality of digital signals output from the digital signal processing unit into analog signals, the analog multiplexer multiplexes the analog signals output from each of the plurality of sub-digital-to-analog conversion units to generate a broadband signal, the digital signal processing unit includes a plurality of band synthesis units that generate digital signals for each sub-digital-to-analog conversion unit, each band synthesis unit generates a digital signal for each sub-digital-to-analog conversion unit by synthesizing the bands of different composite signals, a signal generation method.

5. The digital signal processing unit divides the input signal into N (N is the number of divisions) divided signals for each frequency width that is a common divisor of the Nyquist frequencies of the plurality of sub-digital-to-analog conversion units and the clock frequency of the analog multiplexer, the digital signal processing unit branches the generated N divided signals on the path, and generates N folded divided signals corresponding to the N divided signals by folding the branched N divided signals on the frequency axis and taking the complex conjugate, the digital signal processing unit takes the N divided signals and the N folded divided signals as inputs, and generates N composite signals, the digital signal processing unit takes the N composite signals as inputs, and generates a plurality of digital signals corresponding to each sub-digital-to-analog conversion unit, a plurality of sub-digital-to-analog conversion units respectively convert the plurality of digital signals output from the digital signal processing unit into analog signals, the analog multiplexer multiplexes the analog signals output from each of the plurality of sub-digital-to-analog conversion units to generate a broadband signal, the digital signal processing unit includes 2N×N convolution operation units and N addition units, the 2N×N convolution operation units take the N divided signals and the N folded divided signals as inputs, and multiply the input N divided signals and the N folded divided signals by a response function, the N addition units output N composite signals obtained by adding the N divided signals multiplied by the response function and the N folded divided signals multiplied by the response function, A signal generation method.

6. A computer program for causing a computer to function as the signal generation device according to any one of claims 1 to 3.

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