LED drive circuit and LED display device

Abstract

The embodiment of the present application provides an LED driving circuit and an LED display device, the LED driving circuit includes a first component area, which includes a first driving channel group and a second driving channel group, the first driving channel group and the second driving channel group are symmetrically distributed, and the first driving channel group and the second driving channel group each include the same number of driving channels, and a second component area where an analog ground pad is installed, which is connected to the substrate of the driving channel through a metal line. The present application can effectively reduce the noise inside the chip, improve the output current matching accuracy between each channel, and obtain good current consistency, which contributes to ensuring good display effect of the LED display.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to a Chinese patent application bearing application number 2020115026300 and entitled "LED Driving Circuit," filed with the China Patent Office on December 17, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of integrated circuits, and in particular to LED driving circuits and LED displays. [Background technology]

[0003] With the increasing interest in science and technology and the environment, LEDs (light emitting diodes) are widely used in the field of information display due to their advantages such as high efficiency, safety, and long lifespan. LED displays are also developing rapidly, and higher requirements are being placed on the display quality of LED displays. The quality of LED display driver chips plays an important and decisive role in the display quality of LED displays. Currently, most mainstream LED display driver chips on the market use a multi-channel constant current output architecture to meet the driving requirements of a large number of LED dots. In addition to the multi-channel output, the application requirements of cascaded connection result in low current consistency between the rows and columns of each LED dot, which significantly affects the display effect. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present application is to provide an LED driving circuit and an LED display device. [Means for solving the problem]

[0005] An embodiment of the present application provides an LED driving circuit, which includes: a first component area including a first drive channel group and a second drive channel group, where the first drive channel group and the second drive channel group have a symmetrical distribution and the first drive channel group and the second drive channel group each include the same number of drive channels; and a second component area where an analog ground pad is provided, the analog ground pad being connected to a substrate of the drive channels via a metal line.

[0006] Optionally, the drive channel includes a common source device module located adjacent to the symmetry axis of the first drive channel group and the second drive channel group, a common gate device module adjacent to the common source device module, an electrostatic protection module adjacent to the common gate device module, an operational amplifier module adjacent to the electrostatic protection module, and a blanking module adjacent to the operational amplifier module and located at an edge of the driver chip.

[0007] Optionally, a common source device module of the first drive channel group is adjacent to a common source device module of the second drive channel group.

[0008] Optionally, the common source device module, common gate device module, electrostatic protection module, operational amplifier module and blanking module in the first drive channel group are arranged in order from right to left, and the common source device module, common gate device module, electrostatic protection module, operational amplifier module and blanking module in the second drive channel group are arranged in order from left to right.

[0009] Optionally, the first component area further includes a plurality of output terminal pads, each corresponding to one of the driving channels, disposed adjacent to the common gate device module and the electrostatic protection module.

[0010] Optionally, the number of the output terminal pads is sixteen.

[0011] Optionally, the first component area further includes a plurality of power ground pads, each corresponding to four of the drive channels, located on a symmetry axis between the first drive channel group and the second drive channel group.

[0012] Optionally, the number of the power ground pads is four.

[0013] Optionally, the number of said metal lines is even, and said metal lines exhibit a symmetrical distribution.

[0014] Optionally, the metal lines include a first metal line distributed to the left of the output terminal pad of the first drive channel group and connected to the substrate of the first drive channel group, a second metal line distributed between the output terminal pad and the power ground pad of the first drive channel group and connected to the substrate of the first drive channel group, a third metal line distributed between the output terminal pad and the power ground pad of the second drive channel group and connected to the substrate of the second drive channel group, and a fourth metal line distributed to the right of the output terminal pad of the second drive channel group and connected to the substrate of the second drive channel group.

[0015] Optionally, the common source device module includes a first field effect transistor, the common gate device module includes a second field effect transistor, and the operational amplifier module includes an amplifier.

[0016] Selectively, the source of the first field effect transistor is grounded, the gate of the first field effect transistor is connected to a first voltage input terminal, the drain of the first field effect transistor is connected to the source of the second field effect transistor, the drain of the second field effect transistor is connected to an output terminal of the circuit, the gate of the second field effect transistor is connected to an output terminal of the amplifier, the first input terminal of the amplifier is connected to a second voltage input terminal, and the second input terminal of the amplifier is connected to the source of the second field effect transistor.

[0017] Optionally, the first field effect transistor and the second field effect transistor are both NMOS transistors.

[0018] Optionally, the first drive channel group and the second drive channel group each include eight of the drive channels.

[0019] Optionally, an analog power pad is further provided in the second component area.

[0020] An embodiment of the present application further provides an LED display device including any of the above LED driving circuits. [Brief explanation of the drawings]

[0021] In order to more clearly explain the technical solutions of the embodiments of the present application, the following briefly introduces the drawings that need to be used in the embodiments of the present application. The following drawings only show some embodiments of the present application, so they should not be considered as limiting the scope, and it should be understood that those skilled in the art can obtain other related drawings based on these drawings without paying creative labor.

[0022] [Figure 1] 1 is a schematic diagram of an LED driving circuit according to an embodiment of the present application; [Figure 2] 1 is a schematic diagram of an LED driving circuit according to an embodiment of the present application; [Figure 3]FIG. 1 is a schematic diagram of a constant current source circuit in a drive channel of an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0023] The technical solutions in the embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.

[0024] In the description of the examples of this application, the terms "first," "second," etc. are used merely to distinguish the description and do not indicate sequence numbers, and should not be understood as indicating or suggesting relative importance.

[0025] In describing embodiments of the present application, the terms "comprise", "include", and the like refer to the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or sets thereof.

[0026] In describing the embodiments of the present application, the terms "horizontal," "vertical," "suspended," etc. do not necessarily mean that the component is absolutely horizontal or suspended, and may be slightly tilted. For example, "horizontal" simply means that the direction is more horizontal than "vertical," and does not necessarily mean that the structure is completely horizontal, and may be slightly tilted.

[0027] In describing the embodiments of the present application, the orientations or positional relationships indicated by the terms "upper," "lower," "left," "right," "front," "rear," "inner," "outer," etc. are orientations or positional relationships shown in the drawings or orientations or positional relationships in which the products of the present application are normally disposed when in use, and are merely intended to facilitate explanation of the present application. They do not indicate or imply that a specified device or element must have a particular orientation or be constructed or operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application.

[0028] In describing the embodiments of the present application, unless otherwise clearly specified and limited, the terms "mounting," "installing," "providing," "connecting," and "configuring" should be understood in a broad sense. For example, they may refer to a fixed connection, a detachable connection, or an integral structure. They may refer to a mechanical connection or an electrical connection. They may refer to a direct connection, an indirect connection via an intermediate medium, or an internal communication between two devices, elements, or components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application according to the specific circumstances.

[0029] 1 is a schematic diagram of an LED driving circuit according to an embodiment of the present application. The driving chip 1 includes a first component area 100 and a second component area 200. The first component area 100 and the second component area 200 are both rectangular, with the bottom edge of the first component area 100 aligned with the bottom edge of the driving chip 1, the left edge of the first component area 100 aligned with the left edge of the driving chip 1, and the right edge of the first component area 100 aligned with the right edge of the driving chip 1. The second component area 200 is located above the first component area 100, with the top edge of the second component area 200 aligned with the top edge of the driving chip 1, the left edge of the second component area 200 aligned with the left edge of the driving chip 1, and the right edge of the second component area 200 aligned with the right edge of the driving chip 1.

[0030] The first component area 100 includes a first drive channel group 110 and a second drive channel group 120, where the first drive channel group 110 and the second drive channel group 120 have a symmetrical distribution, and the first drive channel group 110 and the second drive channel group 120 each have the same number of drive channels 300. Optionally, the first drive channel group 110 includes eight drive channels 300, and the second drive channel group 120 also includes eight drive channels 300, where the drive channels 300 in the first drive channel group 110 and the drive channels 300 in the second drive channel group 120 have a symmetrical distribution. It can be understood that in actual applications, the first drive channel group and the second drive channel group may include more or fewer drive channels, and the above eight is merely a specific example and should not be considered limiting.

[0031] An analog ground pad 210 (AVSS PAD) is disposed in the second component area 200, and the analog ground pad 210 is connected to the substrate 150 of the drive channel 300 in the first component area 100 via a metal line 400. Optionally, the substrate 150 is a P substrate. An analog power supply pad 220 (AVDD PAD) is further disposed in the second component area 200, and optionally, the analog ground pad 210 and the analog power supply pad 220 are both disposed close to the top edge of the second component area 200 and located near the symmetry axis between the first drive channel group 110 and the second drive channel group 120. Optionally, the number of metal lines 400 is even, and the metal lines 400 have a symmetrical distribution.

[0032] 2, which shows a schematic diagram of an LED driving circuit according to an embodiment of the present application, the driving chip 1 includes a first component area 100 and a second component area 200, the first component area 100 includes a first driving channel group 110 and a second driving channel group 120 that are symmetrically arranged, and the first driving channel group 110 and the second driving channel group 120 each include the same number of driving channels 300.

[0033] The drive channel 300 includes a common source device module 310, a common gate device module 320, an electrostatic protection module 330, an operational amplifier module 340, and a blanking module 350, wherein the common source device module 310 is located on the drive chip 1 and is adjacent to the symmetry axis of the first drive channel group 110 and the second drive channel group 120, the common gate device module 320 is adjacent to the common source device module 310, the electrostatic protection module 330 is adjacent to the common gate device module 320, the operational amplifier module 340 is adjacent to the electrostatic protection module 330, the blanking module 350 is adjacent to the operational amplifier module 340, and the blanking module 350 is located at the edge of the drive chip 1.

[0034] The common source device module 310 is located near the axis of symmetry of the first drive channel group 110 and the second drive channel group 120, and the common source device module 310 of the first drive channel group 110 is adjacent to the common source device module 310 of the second drive channel group 120.

[0035] Optionally, the common source device module 310 may be installed at the middle position of the driver chip 1, and in the first driver channel group 110, the common source device module 310, the common gate device module 320, the electrostatic protection module 330, the operational amplifier module 340, and the blanking module 350 of the driver channel 300 are arranged in order from right to left, and in the second driver channel group 120, the common source device module 310, the common gate device module 320, the electrostatic protection module 330, the operational amplifier module 340, and the blanking module 350 of the driver channel 300 are arranged in order from left to right.

[0036] In the first component area 100, all the driving channels 300 are arranged in the same location, and the common source device modules 310 that have the greatest impact on the mismatch in the driving channels 300 are all arranged in the middle position of the driving chip 1, thereby effectively reducing device mismatch, improving the output current matching accuracy between each driving channel 300, and achieving good current consistency.

[0037] The first component area 100 further includes a plurality of output terminal pads 130 (OUT PAD), each corresponding to each drive channel 300, and the output terminal pads 130 are located adjacent to the common gate device module 320 and electrostatic protection module 330 of the corresponding drive channel 300. Optionally, the first drive channel group 110 and the second drive channel group 120 each include eight drive channels 300, and the first component area 100 includes 16 output terminal pads 130.

[0038] The first component area 100 further includes a plurality of power ground pads 140 (OVSS PADs), each corresponding to four drive channels 300, and the power ground pads 140 are located on the symmetry axis of the first drive channel group 110 and the second drive channel group 120. Optionally, the first drive channel group 110 and the second drive channel group 120 each include eight drive channels 300, and the first component area 100 includes four power ground pads 140.

[0039] The analog ground pad 210 of the second component area 200 is connected to the substrate 150 of the drive channel 300 in the first component area 100 via a metal line 400. The metal line 400 includes a first metal line 410, a second metal line 420, a third metal line 430, and a fourth metal line 440, of which the first metal line 410 is distributed to the left of the output terminal pad 130 of the first drive channel group 110, the second metal line 420 is distributed between the power ground pad 140 and the output terminal pad 130 of the first drive channel group 110, and the first metal line 410 and the second metal line 420 are connected to the substrate 150 of the first drive channel group 110. The third metal line 430 is used to connect to the substrate 150 of the second drive channel group 110, the third metal line 430 is distributed between the power ground pad 140 and the output terminal pad 130 of the second drive channel group 120, and the fourth metal line 440 is distributed to the right of the output terminal pad 130 of the second drive channel group 120, and the third metal line 430 and the fourth metal line 440 are used to connect the substrate 150 of the second drive channel group 120.

[0040] In the first component area 100, the operating current of each driving channel 300 is usually several milliamperes to tens of milliamperes. In the related art, the substrate 150 of the driving channel 300 is connected to the power ground pad 140. The current source in the driving channel 300 constantly switches its switch state under the control of display data, which causes large noise in the power ground pad 140 and leads to large noise in the substrate potential of the entire driving chip 1, which further affects the performance of the analog shared part in the second component area 200. The internal noise is also one of the causes of device mismatch.

[0041] In the embodiment of the present application, the analog ground pads 210 of the second component area 200 are respectively connected to the substrate 150 of each driving channel 300 through metal lines 400, and the metal lines 400 directly introduce the ground potential to the contact portion of the substrate 150 of the first component area 100, thereby effectively reducing the internal noise of the driving chip 1.

[0042] Alternatively, the layout structure of the driver chip 1 can be suitable for a common anode product of driving an LED display, and can also be suitable for a common cathode product of driving an LED display.

[0043] Optionally, the common source device module 310 includes a first field effect transistor 311, the common gate device module 320 includes a second field effect transistor 321, and the operational amplifier module 340 includes an amplifier 341. The electrostatic protection module 330 includes an ESD device (Electro-Static Discharge, electrostatic resistor).

[0044] 3, a schematic diagram of a constant current source circuit in a driving channel 300 according to an embodiment of the present application is shown, which includes a first field effect transistor 311, a second field effect transistor 321, and an amplifier 341. The first field effect transistor 311 and the second field effect transistor 321 are both NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0045] The source of the first field effect transistor 311 is grounded, the gate of the first field effect transistor 311 is connected to a first voltage input terminal, the drain of the first field effect transistor 311 is connected to a source of the second field effect transistor 321, the drain of the second field effect transistor 321 is connected to an output terminal of the circuit, the gate of the second field effect transistor 321 is connected to an output terminal of the amplifier 341, the first input terminal of the amplifier 341 is connected to a second voltage input terminal, and the second input terminal of the amplifier 341 is connected to the source of the second field effect transistor 321.

[0046] In LED display devices such as LED displays, a PWM (Pulse Width Modulation) constant current source driver chip provides a constant drive current. Since the number of gray levels displayed on the LED display device is equal to the number of gray scale clocks GCLK contained in the PWM signal, the precision of the drive current of each driver channel affects the final display effect. In the above constant current source circuit, the precision of the current mainly depends on the offset voltage of the first field effect transistor 311 and the offset voltage of the amplifier 341.

[0047] Based on the above LED driving circuit, an embodiment of the present application further provides an LED display device, which includes the above LED driving circuit, and the LED display device may be, for example, an LED display, and can be applied to any electronic device requiring an LED display.

[0048] The above are only examples provided in this application, which are only intended to illustrate the technical solutions of this application, and are not intended to limit this application. For those skilled in the art, any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should fall within the scope of protection of this application.

[0049] [Industrial Applicability] The technical solution proposed in this application reduces the internal noise of the chip and improves the matching accuracy of the output current between each channel, thereby achieving good current consistency and ensuring a good display effect of the LED display. [Explanation of symbols]

[0050] 1 - driver chip, 100 - first component area, 110 - first driver channel group, 120 - second driver channel group, 130 - output terminal pad, 140 - power ground pad, 150 - substrate, 200 - second component area, 210 - analog ground pad, 220 - analog power pad, 300 - driver channel, 310 - common source device module, 311 - first field effect transistor, 320 - common gate device module, 321 - second field effect transistor, 330 - electrostatic protection module, 340 - operational amplifier module, 341 - amplifier, 350 - blanking module, 400 - metal line, 410 - first metal line, 420 - second metal line, 430 - third metal line, 440 - fourth metal line.

Claims

1. An LED drive circuit, a first component area including a first drive channel group and a second drive channel group, the first drive channel group and the second drive channel group exhibiting a symmetrical distribution, and the first drive channel group and the second drive channel group each including the same number of drive channels; a second component area in which an analog ground pad is located, the analog ground pad being connected to the substrate of the drive channel via a metal line; each of the drive channels includes a first field effect transistor, a second field effect transistor, and an amplifier; a gate of the first field effect transistor connected to a first voltage input terminal; the source of the first field effect transistor is grounded; the second field effect transistor is connected between the drain of the first field effect transistor and a corresponding output terminal for supplying an output current; the gate of the second field effect transistor is connected to the output terminal of the amplifier; a first input terminal of the amplifier connected to a second voltage input terminal; a second input terminal of the amplifier connected to the source of the second field effect transistor; In each of the drive channels, the first field effect transistor is positioned closer to a line of symmetry between the first drive channel group and the second drive channel group than the second field effect transistor and the amplifier; In the first component area, the metal lines include a first metal line, a second metal line, a third metal line, and a fourth metal line extending parallel to the symmetry axis between the first drive channel group and the second drive channel group, respectively; the LED driving circuit further includes a plurality of output terminal pads and a plurality of power ground pads; the output terminal pad corresponding to the first driving channel is distributed between the first metal line and the second metal line; the output terminal pad corresponding to the second driving channel is distributed between the third metal line and the fourth metal line; the axis of symmetry between the first group of drive channels and the second group of drive channels, the plurality of power ground pads, and the first field effect transistor in each of the drive channels are disposed between the second metal line and the third metal line.

2. The drive channel includes: a common source device module located adjacent to an axis of symmetry of the first group of drive channels and the second group of drive channels; a common gate device module adjacent to the common source device module; an electrostatic protection module adjacent to the common gate device module; an operational amplifier module adjacent to the electrostatic protection module; a blanking module disposed adjacent to the operational amplifier module and at an edge of the driver chip; the common source device module includes the first field effect transistor; the common gate device module includes the second field effect transistor; 2. The LED driver circuit of claim 1, wherein the operational amplifier module includes the amplifier.

3. 3. The LED driver circuit of claim 2, wherein a common source device module of the first drive channel group is adjacent to a common source device module of the second drive channel group.

4. 4. The LED driving circuit according to claim 2, wherein the common source device module, the common gate device module, the electrostatic protection module, the operational amplifier module, and the blanking module in the first driving channel group are arranged in order from right to left, and the common source device module, the common gate device module, the electrostatic protection module, the operational amplifier module, and the blanking module in the second driving channel group are arranged in order from left to right.

5. In the first component area, the plurality of output terminal pads include: The LED driving circuit according to any one of claims 2 to 4, characterized in that each of the driving channels corresponds to a respective one of the common gate device modules and the electrostatic protection module, and is installed adjacent to the common gate device module and the electrostatic protection module.

6. 6. The LED driving circuit according to claim 5, wherein the number of the output terminal pads is 16.

7. In the first component area, the plurality of power ground pads include:

7. The LED driving circuit according to claim 5, wherein each of the first and second driving channel groups corresponds to four of the driving channels and is arranged on a symmetrical axis between the first and second driving channel groups.

8. 8. The LED driving circuit according to claim 7, wherein the number of the power ground pads is four.

9. 9. The LED driving circuit according to claim 1, wherein the number of the metal lines is an even number, and the metal lines exhibit a symmetrical distribution.

10. The first metal wire is distributed to the left of the output terminal pad of the first drive channel group and connected to a substrate of the first drive channel group; the second metal line is distributed between the output terminal pad and the power ground pad of the first drive channel group and is connected to a substrate of the first drive channel group; the third metal line is distributed between the output terminal pad and the power ground pad of the second drive channel group and is connected to a substrate of the second drive channel group; 8. The LED driving circuit of claim 7, wherein the fourth metal line is distributed to the right of the output terminal pad of the second driving channel group and connected to a substrate of the second driving channel group.

11. 2. The LED driving circuit according to claim 1, wherein the first field effect transistor and the second field effect transistor are both NMOS transistors.

12. 12. The LED driving circuit according to claim 1, wherein the first driving channel group and the second driving channel group each include eight of the driving channels.

13. 13. The LED driving circuit according to claim 1, wherein an analog power supply pad is further provided in the second component area.

14. An LED display device comprising the LED drive circuit according to any one of claims 1 to 13.

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