Selection of training data for neural networks

Abstract

To provide an apparatus, a system, and a technique to automatically select training data.SOLUTION: According to at least one embodiment, training data is automatically selected on the basis of, for example, meta data associated with the training data.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] At least one embodiment relates to processing resources used to select training data, for example, processors or computing resources used to select training data for training one or more neural networks according to various novel techniques described herein. [Background technology]

[0002] Selecting training data for training a neural network is a nontrivial task in many situations. In various cases, selecting training data for training a neural network can require significant computing resources, especially when the amount of data from which to select increases. Therefore, there is room for improvement in techniques for selecting training data. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 illustrates an example system for curating scenes, according to at least one embodiment. [Figure 2] FIG. 1 illustrates an example of a scene and metadata, according to at least one embodiment. [Figure 3] FIG. 1 illustrates an example of the results of a system for curating scenes, according to at least one embodiment. [Figure 4] FIG. 10 illustrates another example of results of a system for curating scenes, according to at least one embodiment. [Figure 5] FIG. 1 illustrates an example process of a system for curating a scene, according to at least one embodiment. [Figure 6A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 6B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 7]FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 8] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 9A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 9B] 9B illustrates example camera locations and fields of view for the autonomous vehicle of FIG. 9A, according to at least one embodiment. [Figure 9C] FIG. 9B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 9A, according to at least one embodiment. [Figure 9D] 9B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 9A, according to at least one embodiment. [Figure 10] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 11] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 12] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 13] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14A] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14B] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14C] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14D] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 14E] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 14F] FIG. 1 illustrates a shared programming model, according to at least one embodiment. [Figure 15]FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 16A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 16B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor, according to at least one embodiment. [Figure 17A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 17B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 18] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 19A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 19B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 19C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 19D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 20] FIG. 1 illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment. [Figure 21] FIG. 1 illustrates a graphics processor according to at least one embodiment. [Figure 22] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 23] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 24] FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 25]FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 26] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 27] FIG. 1 illustrates at least a portion of a graphics processor according to one or more embodiments. [Figure 28] FIG. 1 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment. [Figure 29] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 30A] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 30B] FIG. 1 illustrates thread execution logic including an array of processing elements of a graphics processor core, according to at least one embodiment. [Figure 31] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 32] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 33] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one implementation. [Figure 34] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. [Figure 35] FIG. 1 is an exemplary data flow diagram of an advanced computing pipeline, according to at least one embodiment. [Figure 36] FIG. 1 is a system diagram of an exemplary system for training, calibrating, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment. [Figure 37]FIG. 36 includes an exemplary illustration of an advanced computing pipeline 3610A for processing imaging data, according to at least one embodiment. [Figure 38A] FIG. 10 is an exemplary data flow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment. [Figure 38B] FIG. 1 is an exemplary data flow diagram of a virtual device supporting a CT scanner, according to at least one embodiment. [Figure 39A] FIG. 1 is a data flow diagram of a process for training a machine learning model, according to at least one embodiment. [Figure 39B] FIG. 1 is an exemplary diagram of a client-server architecture for enhancing an annotation tool with pre-trained annotation models, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0004] In at least one embodiment, given a set of labeled scenes and a target distribution of various category metadata surrounding the scenes, the system samples up to a given number of curated scenes from a set of unlabeled scenes, such that the final distribution of the union of the labeled and curated scenes optimally approximates the target distribution. In at least one embodiment, a scene refers to a collection of data. In at least one embodiment, a scene is an image. In at least one embodiment, a scene is a collection of sensor data. In at least one embodiment, a scene is generated or otherwise captured by one or more systems using various sensor hardware, such as at least image capture hardware, video capture hardware, audio capture hardware, location sensing hardware, weather detection hardware, and / or variations thereof. In at least one embodiment, a scene encapsulates sensor data being collected at a given time using one or more systems, such as those of a vehicle.

[0005] In at least one embodiment, one or more systems annotate a scene with metadata to indicate various conditions or otherwise associate the scene with metadata. In at least one embodiment, the one or more systems generate the metadata using various sensor hardware. In at least one embodiment, the metadata indicates one or more Operational Design Domain (ODD) values. In at least one embodiment, an ODD refers to an indication of conditions under which one or more systems, such as a vehicle, operate, and the ODD can be one or more values ​​corresponding to one or more particular conditions. In at least one embodiment, an ODD corresponds to a particular category corresponding to an aspect of the environment in which the one or more systems operate. In at least one embodiment, as an illustrative example, a road surface ODD can have a first value corresponding to dry conditions or a second value corresponding to wet conditions, and the ODD can be set to the first value indicating that the road surface conditions are dry or set to the second value indicating that the road surface conditions are wet. In at least one embodiment, as an illustrative example, a scene is associated with metadata indicating a lighting ODD having a value indicative of bright ambient lighting conditions, indicating that the scene was captured in lighting conditions that are bright ambient lighting conditions.

[0006] In at least one embodiment, one or more labeling entities label a scene, and the labeled scene is used to train one or more neural networks. In at least one embodiment, the one or more labeling entities label the scene by generating one or more labels that indicate various features, analyses, and / or variations of the scene. In at least one embodiment, the one or more labeling entities generate one or more labels in any suitable context, such as synthetically generated (e.g., generated from a computer model or rendering), realistically generated (e.g., designed and generated from real-world data), machine-automated (e.g., using feature analysis and learning to extract features from data and then generate labels), human-annotated (e.g., a labeler or annotation expert who determines labels), and / or variations thereof. In at least one embodiment, as an illustrative example, a scene is an image depicting objects, and one or more labels for the scene indicate the location of the objects, the classification of the objects, the analysis of the objects, and / or variations thereof.

[0007] In at least one embodiment, a system for curating scenes samples a set of unlabeled scenes at most a given number of curated scenes, given a set of labeled scenes and a target distribution of various category metadata surrounding the scenes, such that the final distribution of the union of the labeled and curated scenes optimally approximates the target distribution. In at least one embodiment, the target distribution indicates one or more target proportions of scenes with one or more specific ODD values. In at least one embodiment, the one or more systems calculate the target distribution based on one or more neural networks. In at least one embodiment, as an illustrative example, one or more systems determine that a neural network for classifying images for training requires training data including 30% labeled scenes in low natural light conditions and 70% labeled scenes in bright natural light conditions, and the one or more systems calculate a target distribution of scenes indicating a target percentage of 30% of scenes having an illumination ODD value indicative of low natural light conditions and a target percentage of 70% of scenes having an illumination ODD value indicative of bright natural light conditions.

[0008] In at least one embodiment, a system for curating scenes automatically selects scenes from a set of unlabeled scenes. In at least one embodiment, the system for curating scenes selects scenes at regular time intervals or based on any suitable event or trigger. In at least one embodiment, the system for curating scenes selects scenes from the set of unlabeled scenes to form curated scenes such that one or more percentages of scenes in the union of the curated scenes and the set of labeled scenes approximate one or more target percentages of the target distribution. In at least one embodiment, the system for curating scenes partitions the scenes in the set of unlabeled scenes into buckets, each bucket corresponding to a particular combination of ODD values. In at least one embodiment, the system for curating scenes selects scenes from each bucket. In at least one embodiment, the system for curating scenes utilizes one or more equation solvers to determine the number of scenes to select from each bucket. In at least one embodiment, the system for curating scenes utilizes various algorithms to ensure diversity among the scenes selected from each bucket. In at least one embodiment, the selected scenes, also referred to as curated scenes, are then labeled and used to train one or more neural networks.

[0009] In the above and following descriptions, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concepts may be practiced without one or more of these specific details.

[0010] In at least one embodiment, the techniques described herein achieve various technical advantages, including, but not limited to, the ability to automatically select scenes for training from any number of scenes to approximate a target distribution, the ability to efficiently select scenes for training by grouping scenes by metadata, the ability to select a variety of scenes for training one or more neural networks, and various other technical advantages.

[0011] 1 illustrates an example system 100 for curating scenes, according to at least one embodiment. In at least one embodiment, the system 110 for curating scenes includes an automated curation algorithm 112 and a scene selector 114. In at least one embodiment, the system 110 for curating scenes outputs curated scenes 116 based on the labeling budget 102, the target distribution 104, the labeled scenes 106, and the unlabeled scenes 108. In at least one embodiment, the system 110 for curating scenes selects or otherwise curates scenes from the unlabeled scenes 108 to output the curated scenes 116.

[0012] In at least one embodiment, the labeling budget 102 is a numeric value that indicates the number of scenes to select (e.g., curate) and is implemented using data types such as integers, floating point numbers, characters, strings, and / or variations thereof. In at least one embodiment, the labeling budget 102 is a number that indicates the number of scenes to select (e.g., curate), N scenes, also referred to as curated scenes, auto-curated scenes, selected scenes, and / or variations thereof. ac In at least one embodiment, labeling budget 102 is any suitable value from any suitable range of values. In at least one embodiment, labeling budget 102 is determined by one or more systems in connection with one or more neural network training processes.

[0013] In at least one embodiment, target distribution 104 is a set of data that indicates one or more target proportions of a scene and is implemented using a data structure such as an array, a list, and / or variations thereof. In at least one embodiment, target distribution 104 is a set of data that indicates one or more target proportions of a scene and is implemented using a data structure such as an array, a list, and / or variations thereof. c , where each term is expressed as a condition on the ODD metadata and a target percentage of the scene that should satisfy said condition. In at least one embodiment, each term corresponds to one or more specific ODD values. In at least one embodiment, as an illustrative example, the target distribution 104 is N c The values ​​are specified through the table below with a =5 term, although any variation thereof may be utilized. [Table 1] Here, the target distribution 104 may be a target percentage of scenes having a "road_surface" ODD value of 0.7 or 70%, a target percentage of scenes having a "road" ODD value of 0.3 or 30%, a target percentage of scenes having a "lighting" ODD value of 0.3 or 30%, a target percentage of scenes having a "moonlight" or "dark" value, a target percentage of scenes having a "lighting" ODD value of 0.4 or 40%, a target percentage of scenes having a "lighting" ODD value of 0.3 or 30%, a target percentage of scenes having a "bright_natural" value, and a target percentage of scenes having a "lighting" ODD value of 0.3 or 30%. Specifying a target percentage of scenes having ODD values, and continuing with the above example, the set of scenes approximating target distribution 104 includes 70% of scenes having "Road" ODD values ​​of "Dry" values, 30% of scenes having "Road" ODD values ​​of "Wet" values, 30% of scenes having "Lighting" ODD values ​​of "Moonlight" or "Dark" values, 40% of scenes having "Lighting" ODD values ​​of "Bright Natural" values, and 30% of scenes having "Lighting" ODD values ​​of "Low Natural" values, each scene having a "Road" ODD value and / or a "Lighting" ODD value. In at least one embodiment, target distribution 104 is determined by one or more systems in conjunction with one or more neural network training processes. In at least one embodiment, target distribution 104 indicates any suitable target percentages of any suitable terms. In at least one embodiment, an ODD such as those described herein may include any suitable ODD, which may be one of any suitable values ​​corresponding to any suitable condition, such as a weather ODD, a road type ODD, a traffic condition ODD, an environmental condition ODD, a time of day ODD, a speed ODD, and / or variations thereof.

[0014] In at least one embodiment, a scene, also referred to as an asset, is an image in any suitable image format (e.g., a red-green-blue (RGB) image, a black and white (B / W) figure, a grayscale image, an RGB-depth (RGB-D) image, and / or variations thereof) that can be stored or otherwise encoded using any suitable image file format that encodes image data (e.g., a bitmap image file, a Joint Photographic Experts Group (JPEG) file, a Scalable Vector Graphics (SVG) file, and / or variations thereof). In at least one embodiment, a scene is a frame of video. In at least one embodiment, labeled scenes 106, also referred to as a set of labeled scenes, is a collection of data that includes one or more labeled scenes. In at least one embodiment, each scene in labeled scenes 106 is associated with one or more labels. In at least one embodiment, labeled scenes 106 include one or more scenes that have been labeled by one or more labeling entities. In at least one embodiment, labeled scene 106 includes one or more scenes that have been labeled and are utilized to train one or more neural networks. l A scene consists of a number of labeled scenes, denoted as S l The ODD value and various metadata (e.g., timestamp data, location data, etc.) are included.

[0015] In at least one embodiment, unlabeled scene 108, referred to as a set of unlabeled scenes, is a collection of data that includes one or more unlabeled scenes. In at least one embodiment, one or more scenes in unlabeled scene 108 are generated or otherwise captured by one or more systems using at least various sensor hardware. In at least one embodiment, one or more scenes in unlabeled scene 108 are one or more frames of video captured in a video capture session, which may refer to one or more particular time intervals and / or locations at which the video is captured. In at least one embodiment, as an illustrative example, unlabeled scene 108 includes a first scene and a second scene, where the first scene is a frame of video and the second scene is a subsequent frame of the video. In at least one embodiment, unlabeled scene 108 includes N u The number of unlabeled scenes denoted as S u , which includes ODD values ​​and various metadata (e.g., timestamp data, location data, etc.). In at least one embodiment, each scene in unlabeled scenes 108 is associated with metadata indicating one or more ODD values. In at least one embodiment, one or more systems generate the metadata for each scene, as described in further detail with respect to FIG. 2. In at least one embodiment, labeled scenes 106 and / or unlabeled scenes 108 are referred to as a set of training data, a plurality of training data, training data, and / or variations thereof.

[0016] In at least one embodiment, system 110 for curating scenes is a collection of one or more hardware and / or software computing resources having instructions that, when executed, select one or more scenes based on a labeling budget, a target distribution, labeled scenes, and / or unlabeled scenes. In at least one embodiment, system 110 for curating scenes is a software program executing on computer hardware, an application executing on computer hardware, a software module, and / or variations thereof. In at least one embodiment, one or more processes of system 110 for curating scenes are performed by any suitable system or unit (e.g., a graphics processing unit (GPU), a parallel processing unit (PPU), a central processing unit (CPU)) in any suitable manner, including sequentially, in parallel, and / or variations thereof.

[0017] In at least one embodiment, the system 110 for curating scenes acquires or otherwise receives the labeling budget 102, the target distribution 104, the labeled scenes 106, and the unlabeled scenes 108 from one or more systems. In at least one embodiment, the one or more systems determine the labeling budget 102, the target distribution 104, the labeled scenes 106, and / or the unlabeled scenes 108 through one or more training processes. In at least one embodiment, the system 110 for curating scenes organizes the scene metadata for each labeled scene 106 and / or unlabeled scene 108 into a Boolean value indicating whether the particular scene satisfies each of the term conditions, N corresponding to the number of term conditions (e.g., as indicated by the target distribution 104). cIn at least one embodiment, as an illustrative example, target distribution 104 indicates at least a term condition for the "road" ODD value of a "dry" value, and a scene vector includes at least a Boolean value corresponding to the term condition, the Boolean value being true if the scene metadata indicates a "road" ODD value of a "dry" value, or false if the scene metadata indicates a "road" ODD value that is not a "dry" value.

[0018] In at least one embodiment, the system for curating scenes 110 calculates a vector for each scene in the labeled scenes 106 and / or the unlabeled scenes 108. In at least one embodiment, the system for curating scenes 110 forms a set of scenes by concatenating row vectors (e.g., each row corresponds to a vector for a scene). In at least one embodiment, the system for curating scenes 110 calculates a set of scenes by concatenating row vectors (e.g., each row corresponds to a vector for a scene). l Let S be the labeled scene 106 denoted by l ×N c In at least one embodiment, the system 110 for curating a scene converts S u The unlabeled scene 108 denoted by S u ×N c In at least one embodiment, the system 110 for curating a scene converts the target distribution 104 into a matrix of N values ​​in the interval [0,1] or any suitable interval, indicating the target proportion of each term. c (e.g., each value in the vector corresponds to a particular target percentage of a term). In at least one embodiment, the element of the vector denoted by C at an index position denoted by i is denoted by C(i), C[i], and / or variations thereof. In at least one embodiment, the system for curating scenes 110 outputs one or more vectors and / or matrices to an automated curation algorithm 112.

[0019] In at least one embodiment, the automated curation algorithm 112 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, implement one or more processes for calculating one or more numbers of scenes to select from one or more groups of scenes, also referred to as buckets. In at least one embodiment, the automated curation algorithm 112 is a software program executing on computer hardware, an application executing on computer hardware, a software module, and / or variations thereof, which may be part of the system for curating scenes 110. In at least one embodiment, the automated curation algorithm 112 implements one or more algorithms for curating scenes.

[0020] In at least one embodiment, a scene can share ODD metadata with one or more other scenes. In at least one embodiment, a scene can have one or more ODD values ​​that are the same as one or more other scenes. In at least one embodiment, the automated curation algorithm 112 defines buckets, referred to as groups, where each bucket corresponds to a particular combination of one or more ODD values ​​and / or terms. In at least one embodiment, a bucket, also referred to as a group, scene bucket, linear programming (LP) bucket, and / or variations thereof, is a collection of data. In at least one embodiment, the automated curation algorithm 112 defines buckets according to the origin of the terms, i Denoted by N bIn at least one embodiment, the automated curation algorithm 112 determines whether a scene of the unlabeled scenes 108 should be assigned to a particular bucket based on the particular combination of one or more ODD values ​​and / or terms to which the particular bucket corresponds, and the automated curation algorithm 112 assigns the scene to the particular bucket if the scene has the particular combination of one or more ODD values ​​and / or terms, or does not assign the scene to the particular bucket if the scene does not have the particular combination of one or more ODD values ​​and / or terms.

[0021] In at least one embodiment, the maximum number of buckets is equal to:

number

[0022] In at least one embodiment, the number of buckets depends only on the target distribution and is on the order of hundreds for 10 terms, while the number of unlabeled scenes may be on the order of tens of millions. u The scenes are assigned to buckets using indexing on the matrix, such as Pandas Hierarchical indexing, or any suitable indexing scheme. In at least one embodiment, Pandas refers to the Pandas software library in the Python programming language or any suitable programming language. In at least one embodiment, the auto-curation algorithm 112, which keeps only unique indexes, assigns the scenes to buckets. u Make the matrix smaller, dimension N b ×N c S with b In at least one embodiment, a bucket is referred to as a group, a subset of training data, a collection of assets, and / or variations thereof.

[0023] In at least one embodiment, the auto-curation algorithm 112 buckets the scenes and i In at least one embodiment, the auto-curation algorithm 112 determines the number of scenes, also referred to as the number of assets, to put in each bucket, S ac In at least one embodiment, the auto-curation algorithm 112, which disregards the current set of labeled scenes (e.g., labeled scenes 106), utilizes the following equation, also referred to as the linear formulation, although any variation thereof may be utilized:

number

[0000] . In at least one embodiment, the automated curation algorithm 112 expresses the budget constraint through the following equation, although any variation thereof may be utilized:

number

[0024] In at least one embodiment, the complexity of solving one or more formulas and / or equations such as those described herein is

number

[0025] In at least one embodiment, the absolute value of the above equation cannot be expressed in linear form. In at least one embodiment, the automated curation algorithm 112 utilizes a set of auxiliary variables (e.g., positive real numbers) denoted by Q(i), and for each term denoted by i, the automated curation algorithm 112 utilizes a constraint denoted by the following equation, any variation of which may be utilized:

number

number

[0026] In at least one embodiment, one or more systems improve upon the above equation by using the L2 norm, or any suitable norm, to measure the distance between the distributions, which penalizes large differences between the actual and target proportions of each term, and a quadratic formulation is defined through the following equation, although any variation thereof may be utilized:

number

[0027] In at least one embodiment, the automated curation algorithm 112 utilizes the current distribution of labeled scenes 106. In at least one embodiment, the automated curation algorithm 112 utilizes the current distribution through a reparameterization of the target term, as shown by the following equation, although any variation thereof may be utilized:

number

[0028] In at least one embodiment, the automatic curation algorithm 112 utilizes one or more equation solvers to solve linear and / or quadratic formulations, such as those described herein. In at least one embodiment, the automatic curation algorithm 112 utilizes a linear programming (LP) solver. In at least one embodiment, the automatic curation algorithm 112 utilizes a solver such as a Gurobi solver, a GLOP solver, a CBC solver, and / or any suitable solver. In at least one embodiment, the automatic curation algorithm 112 outputs, based at least in part on the one or more solvers, a set of scene buckets and a number of scenes to sample for each bucket, also referred to as the number of assets, to sample for each bucket. In at least one embodiment, the number of scenes to sample for a particular bucket indicates the number of scenes to sample, select, or otherwise curate from the particular bucket. In at least one embodiment, the automatic curation algorithm 112 outputs to the scene selector 114 data indicating a set of scene buckets (e.g., one or more ODD values ​​and / or terms to which each bucket corresponds, and characteristics of each bucket, such as which scenes from the unlabeled scenes 108 are in or otherwise assigned to each bucket) and the number of scenes to sample from each bucket in the set of scene buckets (e.g., for each bucket in the set of scene buckets, a first number from the first bucket, a second number from the second bucket, and so on).

[0029] In at least one embodiment, the scene selector 114 is a collection of one or more hardware and / or software computing resources having instructions that, when executed, implement one or more processes for selecting one or more scenes from one or more buckets of scenes. In at least one embodiment, the scene selector 114 is a software program executing on computer hardware, an application executing on computer hardware, a software module, and / or variations thereof, which may be part of the system 110 for curating scenes. In at least one embodiment, the scene selector 114 selects several scenes from each bucket based at least in part on the output of the automatic curation algorithm 112. In at least one embodiment, the process of selecting scenes is also referred to as scene curating, scene sampling, scene picking, and / or variations thereof.

[0030] In at least one embodiment, the scene selector 114 utilizes one or more algorithms to independently sample scenes from each LP bucket to ensure a desired diversity among the scenes. In at least one embodiment, the scene selector 114 utilizes one or more algorithms that allow for different diversity requirements among the selected scenes. In at least one embodiment, the scene selector 114 utilizes one or more algorithms, such as one or more core set algorithms. In at least one embodiment, the scene selector 114 implements one or more processes of the following algorithms, although any variations thereof may be utilized:

number

[0031] In at least one embodiment, the scene selector 114 selects one or more scenes from each bucket through one or more algorithms, such as those described herein, and the selected scenes collectively form the curated scenes 116. In at least one embodiment, the curated scenes 116 are a collection of data including one or more selected scenes, also referred to as auto-curated scenes, auto-selected training data, curated scenes, and / or variations thereof, that have been selected, curated, or otherwise sampled by the scene selector 114 ... ac The number of automatically curated scenes (e.g., S u (picked from) ac In at least one embodiment, S l ∪S ac The distribution of an element is optimally close to a target distribution. In at least one embodiment, an element being optimally close to another element refers to a situation where there is a minimum distance, which may be defined as a distance below a specified threshold, between the element and the other element. In at least one embodiment, the distribution of an element is optimally close to another distribution (e.g., a target distribution) such that one or more proportions of the element are optimally close to one or more proportions (e.g., one or more target proportions) exhibited by the other distribution.

[0032] In at least one embodiment, the curated scene 116 can then be labeled by one or more labeling entities and used to train one or more neural networks. In at least one embodiment, the system for curating scenes 110 obtains one or more labels for the curated scene 116 from one or more labeling entities (e.g., by providing the curated scene 116 to the one or more labeling entities) and uses the one or more labels to train one or more neural networks. In at least one embodiment, the scene label indicates any suitable information, data, analysis, and / or variations thereof associated with the scene. In at least one embodiment, the scene label indicates a neural network result, such as a neural network object detection result (e.g., a bounding box or other indicator of the location of an object within a scene), an object classification result (e.g., a classification or other indicator of the classification of an object within a scene), a segmentation result (e.g., a segmentation map indicating the location of an object within a scene), or any suitable result. In at least one embodiment, the labels indicate any suitable ground truth data associated with one or more neural networks.

[0033] In at least one embodiment, the curated scenes 116 can be part of labeled scenes (e.g., labeled scenes 106) for a subsequent scene curation process of the system for curating scenes 110. In at least one embodiment, the system for curating scenes 110 selects scenes based on time intervals or any suitable event. In at least one embodiment, the system for curating scenes 110 selects scenes to determine curated scenes 116 based at least in part on the labeling budget 102, the target distribution 104, the labeled scenes 106, and the unlabeled scenes 108, the system for curating scenes 110 labels the curated scenes 116, and adds the labeled curated scenes 116 to the labeled scenes 106 for a subsequent scene curation process, and so on, which may utilize the same or different labeling budget 102, the same or different target distribution 104, the same or different labeled scenes 106, and / or the same or different unlabeled scenes 108.

[0034] In at least one embodiment, the system for curating a scene 110 automatically performs one or more processes, such as those described herein. In at least one embodiment, an automatic process refers to a process that, once initialized or otherwise initiated, does not require intervention from a user or other entity. In at least one embodiment, the system for curating a scene 110, upon obtaining one or more of the labeling budget 102, the target distribution 104, the labeled scene 106, and the unlabeled scene 108, performs one or more processes, such as those described herein, to output the curated scene 116. In at least one embodiment, the system for curating a scene 110 is implemented using a set of instructions that, when executed, cause one or more processes of the system for curating a scene 110 to be performed automatically.

[0035] In at least one embodiment, the techniques described herein may be scene-specific; however, it should be noted that the techniques described herein are applicable to any suitable data that can be labeled and have associated metadata, such as a segment (e.g., a collection of a scene over a certain time interval), or any suitable asset. In at least one embodiment, a system for curating a scene selects data for any suitable training and / or learning process, such as an unsupervised learning process, a self-supervised learning process, and / or variations thereof. In at least one embodiment, as an illustrative example, a system for curating a scene obtains a labeling budget indicating the number of data elements to select, a target distribution indicating one or more target percentages of data elements with one or more particular metadata values, a set of labeled data elements, and a set of unlabeled data elements, and the system selects data elements from the set of unlabeled data elements through various techniques, such as those described herein, such that the distribution of the union of the selected data elements and the set of labeled data elements approximates and / or optimally approaches the target distribution.

[0036] 2 illustrates an example scene and metadata 200, according to at least one embodiment. In at least one embodiment, the scene 202 and metadata 204 conform to those described elsewhere in this disclosure.

[0037] In at least one embodiment, scene 202 is generated or otherwise captured by one or more systems using various sensor hardware, such as at least image capture hardware, video capture hardware, audio capture hardware, location sensing hardware, weather detection hardware, and / or variations thereof. In at least one embodiment, one or more systems use the various sensor hardware to associate scene 202 with various data, such as the time, date, conditions, and / or location at which scene 202 was captured and / or other information associated with scene 202. In at least one embodiment, scene 202 encapsulates sensor data that has been collected at a given time using one or more systems, such as that of a vehicle. In at least one embodiment, the vehicle is any suitable vehicle, such as a motor vehicle, a watercraft, an aircraft, a spacecraft, and / or variations thereof. In at least one embodiment, scene 202 is captured by one or more systems of the vehicle. In at least one embodiment, scene 202 is an image. In at least one embodiment, scene 202 is a frame of video.

[0038] In at least one embodiment, one or more systems annotate or otherwise associate scene 202 with metadata 204 to indicate various conditions. In at least one embodiment, metadata 204 is a collection of data that indicates various information about scene 202. In at least one embodiment, metadata 204 is textual data. In at least one embodiment, metadata 204 is associated with scene 202 in any suitable manner, such as through one or more files that encode or otherwise store scene 202, a mapping that associates metadata 204 with scene 202, and / or variations thereof. In at least one embodiment, metadata 204 indicates one or more ODD values. In at least one embodiment, ODD refers to an indication of a condition under which one or more systems, such as a vehicle, operate or otherwise function, and the ODD may be one or more values ​​corresponding to one or more particular conditions. In at least one embodiment, ODD values ​​are referred to as metadata values, metadata conditions, conditions, and / or variations thereof. In at least one embodiment, ODDs correspond to particular categories that correspond to an aspect of the environment in which one or more systems operate or otherwise function.

[0039] 2, metadata 204 indicates a road surface ODD (e.g., shown as "road_surface") having a value indicating a dry condition (e.g., shown as "dry"), indicating that scene 202 was captured in a road surface condition that is a dry condition. In at least one embodiment, referring to FIG. 2, metadata 204 indicates a lighting ODD (e.g., shown as "lighting") having a value indicating a bright natural condition (e.g., shown as "bright_natural"), indicating that scene 202 was captured in a lighting condition that is a bright natural condition.

[0040] In at least one embodiment, metadata 204 is generated by one or more systems about scene 202 in any suitable manner. In at least one embodiment, metadata 204 is generated by one or more systems that capture scene 202. In at least one embodiment, scene 202 is captured by one or more systems and provided to one or more other systems that generate metadata 204. In at least one embodiment, one or more systems generate metadata 204 by utilizing data associated with scene 202, such as at least Global Positioning System (GPS) coordinates of the location where scene 202 was captured, the time scene 202 was captured, and / or variations thereof, which may indicate various conditions of scene 202, such as daytime, nighttime, lighting conditions, and / or variations thereof. In at least one embodiment, one or more systems generate metadata 204 by utilizing map data based on location data associated with scene 202, which may indicate various conditions of scene 202, such as road conditions, weather conditions, location conditions, and / or variations thereof. In at least one embodiment, one or more systems generate metadata 204 by utilizing at least one human labeler who analyzes scene 202 and / or video containing scene 202 to determine metadata 204.

[0041] 3 illustrates an example result 300 of a system for curating a scene, according to at least one embodiment. In at least one embodiment, and with reference to FIG. 3, the "initial formulation" is the following equation, although any variation thereof may be utilized:

number

number

[0042] In at least one embodiment, with reference to FIG. 3 , an “alternative formulation” refers to a linear formulation utilized by a system for curating scenes, such as that described in connection with FIG. 1 . In at least one embodiment, with reference to FIG. 3 , one or more systems utilize the same set of 1k labeled scenes, the same target distribution, and varying numbers of unlabeled and auto-curated scenes. In at least one embodiment, the gap is defined as the sum of absolute differences between the final distribution and the target distribution across all terms. In at least one embodiment, the initial gap is 2.26 or any suitable value. In at least one embodiment, with reference to FIG. 3 , one or more systems utilize the same data for both formulations. In at least one embodiment, after solution, both formulations result in the same or similar final gap, but the time it takes to reach a solution is significantly different.

[0043] 4 illustrates another example result 400 of a system for curating a scene, according to at least one embodiment. In at least one embodiment, with reference to FIG. 4, a "quasi-linear formulation (L1)" refers to a linear formulation utilized by a system for curating a scene, such as that described in connection with FIG. 1. In at least one embodiment, with reference to FIG. 4, a "quadratic formulation (L2^2)" refers to a quadratic formulation utilized by a system for curating a scene, such as that described in connection with FIG. 1. In at least one embodiment, with reference to FIG. 4, in both cases, problem-solving time is negligible (e.g., << 1 second).

[0044] FIG. 5 illustrates an example process 500 of a system for curating a scene, according to at least one embodiment. In at least one embodiment, some or all of process 500 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) collectively executed by hardware, software, or a combination thereof on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program comprising a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some computer-readable instructions usable to perform process 500 are not stored using only transitory signals (e.g., propagating transitory electrical or electromagnetic transmissions). In at least one embodiment, non-transitory computer-readable media does not necessarily include non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver of a transitory signal.

[0045] In at least one embodiment, process 500 is performed by one or more systems, such as those described in this disclosure. In at least one embodiment, the one or more systems include any suitable system having one or more collections of hardware and / or software resources having instructions that, when executed, perform various scene and / or data curation processes, such as those described herein. In at least one embodiment, process 500 is performed by a system for curating scenes. In at least one embodiment, one or more processes of process 500 are performed in any suitable order, including sequentially, in parallel, and / or variations thereof, and using any suitable processing unit, such as a CPU, a GPU, a PPU, and / or variations thereof. In at least one embodiment, the system performs one or more processes of process 500 automatically, without requiring intervention by a user or other entity.

[0046] In at least one embodiment, a system implementing at least a portion of process 500 includes executable code for obtaining 502 at least a labeling budget, a target distribution, a set of labeled scenes, and a set of unlabeled scenes. In at least one embodiment, the labeling budget, the target distribution, the set of labeled scenes, and the set of unlabeled scenes are provided from any suitable entity or system, such as a training framework. In at least one embodiment, the set of labeled scenes and / or the set of unlabeled scenes are referred to as training data. In at least one embodiment, the system obtains the training data from one or more systems, such as one or more image and / or video capture systems of a vehicle, a medical device (e.g., a medical imaging device), an autonomous device (e.g., a robot), and / or any suitable system. In at least one embodiment, the training data is part of one or more training datasets. In at least one embodiment, the training data includes one or more images, one or more frames of one or more videos, sensor data, and / or any suitable data. In at least one embodiment, the labeling budget indicates a target number of scenes to select or otherwise curate. In at least one embodiment, the target distribution indicates one or more target proportions for one or more terms. In at least one embodiment, the target distribution indicates one or more probability distributions for one or more terms.

[0047] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least calculating 504 one or more buckets corresponding to one or more terms. In at least one embodiment, the system determines the one or more terms based on a target distribution indicative of the one or more terms. In at least one embodiment, the target distribution is specified as a set of numbers of terms, with each term expressed as a condition on the ODD metadata and a target percentage of the scene that should satisfy the condition. In at least one embodiment, each term corresponds to one or more specific ODD values. In at least one embodiment, the system calculates one or more buckets, each bucket corresponding to one or more ODD values ​​and / or terms. In at least one embodiment, a bucket is a collection of data associated with an identifier or other indicator (e.g., indicative of one or more ODD values ​​and / or terms corresponding to the bucket).

[0048] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least assigning 506 scenes of a set of unlabeled scenes to one or more buckets. In at least one embodiment, the system assigns scenes to buckets based on a particular combination of one or more ODD values ​​and / or terms to which the particular bucket corresponds, and the system assigns a scene to the particular bucket if the scene has the particular combination of one or more ODD values ​​and / or terms, or does not assign a scene to the particular bucket if the scene does not have the particular combination of one or more ODD values ​​and / or terms. In at least one embodiment, the system analyzes training data (e.g., a set of unlabeled scenes) to calculate or otherwise assign one or more scenes to one or more buckets. In at least one embodiment, the system assigns each scene of the set of unlabeled scenes to a particular bucket.

[0049] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least calculating 508 one or more numbers of scenes to select from one or more buckets. In at least one embodiment, the system utilizes an equation solver to calculate one or more numbers of scenes, also referred to as assets, to sample, select, or otherwise curate from one or more buckets. In at least one embodiment, the system utilizes quadratic formulations, linear formulations, and / or variants thereof, and equation solvers, such as those described herein, to calculate one or more numbers of scenes. In at least one embodiment, an equation solver, also referred to as a solver, includes any suitable equation solver, such as one or more LP solvers, mathematical solvers, simultaneous equation solvers, and / or variants thereof. In at least one embodiment, a solver refers to a collection of one or more hardware and / or software computing resources having instructions that, when executed, solve or otherwise process one or more equations, expressions, formulas, and / or variants thereof to calculate one or more results. In at least one embodiment, the solver is a software program executing on computer hardware, an application executing on computer hardware, a software module, and / or variations thereof. In at least one embodiment, the system inputs various data associated with the labeling budget, the target distribution, the set of labeled scenes, and the set of unlabeled scenes into the equation solver to calculate one or more numbers of scenes to select from one or more buckets.

[0050] In at least one embodiment, the one or more numbers of scenes to select from one or more buckets indicate the number of scenes to select from each bucket (e.g., a first number for a first bucket, etc.). In at least one embodiment, the system calculates the one or more numbers of scenes such that a distribution of one or more scenes represented by the one or more numbers of scenes and / or one or more scenes in the set of labeled scenes matches a target distribution, approximates a target distribution, and / or is optimally close to a target distribution (e.g., one or more proportions of the one or more scenes represented by the one or more numbers of scenes and / or the one or more scenes in the set of labeled scenes matches, approximates, and / or is optimally close to one or more target proportions of the target distribution). In at least one embodiment, the particular proportions of one or more scenes correspond to particular one or more ODD values ​​and indicate the proportion of the one or more scenes having the particular one or more ODD values. In at least one embodiment, the proportion is expressed through a percentage, a decimal, and / or any suitable representation.

[0051] In at least one embodiment, a system performing at least a portion of process 500 includes executable code for at least selecting 510 a set of curated scenes from one or more buckets. In at least one embodiment, the system automatically selects the set of curated scenes from one or more buckets. In at least one embodiment, automatic selection refers to one or more scene selection processes that do not require intervention from a user or other entity. In at least one embodiment, the system automatically selects the set of curated scenes from one or more buckets based at least in part on the calculated number or numbers of scenes to select from the one or more buckets without requiring intervention from a user or other entity. In at least one embodiment, the system selects the set of curated scenes from one or more buckets such that the number or numbers of scenes to select from the one or more buckets match or approximate the calculated number or numbers of scenes to select from the one or more buckets. In at least one embodiment, the system selects the set of curated scenes using one or more algorithms, such as those described in connection with FIG. 1 . In at least one embodiment, the system selects scenes based at least in part on the distance (e.g., temporal distance and / or spatial distance) between the scenes. In at least one embodiment, the system selects a first scene from a particular bucket and a second scene from the particular bucket based at least in part on the distance between the first scene and the second scene.

[0052] In at least one embodiment, the set of curated scenes is referred to as selected training data, automatically selected training data, training data, and / or variations thereof. In at least one embodiment, the set of curated scenes is used in various validation and test datasets for one or more neural networks and / or other suitable systems. In at least one embodiment, the system obtains one or more labels for one or more scenes in the set of curated scenes. In at least one embodiment, the system provides the set of curated scenes to one or more labeling entities to obtain the one or more labels. In at least one embodiment, the system trains one or more neural networks using the set of curated scenes and the one or more labels. In at least one embodiment, the one or more neural networks include any suitable neural network, such as an object detection neural network, an object classification neural network, a segmentation neural network, and / or variations thereof, that may be used in various systems, such as vehicle systems, medical systems, and / or variations thereof.

[0053] In at least one embodiment, the system trains one or more neural networks by causing the one or more neural networks to process training data to calculate one or more results and updating the one or more neural networks based at least in part on the one or more results and one or more labels associated with the training data. In at least one embodiment, the system trains one or more neural networks by calculating a loss based on a difference between the one or more results and the one or more labels and updating the one or more neural networks to minimize the loss. In at least one embodiment, the system trains one or more neural networks until the calculated loss of the one or more neural networks is below a specified threshold, which may be any suitable value. In at least one embodiment, the system trains any suitable neural network, such as an object detection neural network, an object classification neural network, a segmentation neural network, and / or any suitable neural network, using a set of curated scenes. In at least one embodiment, a neural network trained using the set of curated scenes can generate, based on one or more images depicting one or more objects, output data indicative of one or more results based on the one or more images and / or the one or more objects.

[0054] In at least one embodiment, the system trains one or more neural networks such that the one or more neural networks generate output data having one or more attributes. In at least one embodiment, the output data includes one or more results of the one or more neural networks, such as object detection results (e.g., bounding boxes or other indicia of the location of objects depicted in a scene), object classification results (e.g., classifications or other indicia of classifications of objects depicted in a scene), segmentation results (e.g., segmentation maps indicating the location of objects depicted in a scene), or any suitable results. In at least one embodiment, the one or more attributes include data associated with the output data, such as one or more accuracy values ​​indicating one or more levels of accuracy of the output data, one or more confidence values ​​indicating one or more levels of confidence in the output data, and / or any suitable data associated with the output of the neural network. In at least one embodiment, the accuracy value is a numerical value indicative of the level of accuracy of the output, as may be determined by the one or more neural networks or other system. In at least one embodiment, the confidence value is a number that indicates the confidence level of the output (e.g., the probability that the output is accurate), as may be determined by one or more neural networks or other systems.

[0055] In at least one embodiment, the system trains one or more neural networks using the set of curated scenes such that the one or more neural networks generate output data having one or more particular attributes (e.g., a particular accuracy level and / or a particular confidence level). In at least one embodiment, a target distribution is calculated such that, when training data selected based at least in part on the target distribution is used to train the one or more neural networks, the one or more neural networks generate output data having one or more particular attributes (e.g., a particular accuracy level and / or a particular confidence level). In at least one embodiment, one or more systems determine that one or more neural networks have an accuracy level and / or confidence level that is less than a specified threshold for one or more tasks, and the one or more systems calculate or otherwise obtain a target distribution such that, when training data selected based at least in part on the target distribution is used to train the one or more neural networks, the one or more neural networks will have an accuracy level and / or confidence level that is greater than and / or equal to the specified threshold for the one or more tasks.

[0056] In at least one embodiment, as an illustrative example, a system determines that an object detection neural network has an accuracy level and / or confidence level below a specified threshold when detecting objects in images captured in low-light conditions. Continuing with the illustrative example, in at least one embodiment, the system derives or otherwise calculates a target distribution based on the determination, the target distribution indicating a target proportion of scenes having an ODD value indicative of low-light conditions that is greater than one or more other target proportions in the target distribution. Continuing with the illustrative example, in at least one embodiment, the system derives a set of curated scenes based at least in part on the target distribution, derives one or more labels for the set of curated scenes, and uses the one or more labels and the set of curated scenes to train the object detection neural network such that the object detection neural network has an accuracy level and / or confidence level greater than and / or equal to the specified threshold when detecting objects in images captured in low-light conditions.

[0057] Logic of inference and training Figure 6A illustrates inference and / or training logic 615 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 615 are provided below in conjunction with Figures 6A and / or 6B.

[0058] In at least one embodiment, the inference and / or training logic 615 may include, without limitation, code and / or data storage 601 for storing forward and / or output weights, and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that are trained and / or used to infer in one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software for controlling the timing and / or sequence of logic loaded with weights and / or other parameter information, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weights or other parameter information into processor ALUs based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 601 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 601 may be included with other on-chip or off-chip data storage, including L1, L2, or L3 cache of a processor, or system memory.

[0059] In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 601 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 601 is internal or external to a processor, or whether it includes DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0060] In at least one embodiment, the inference and / or training logic 615 may include, without limitation, code and / or data storage 605 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more aspects of the embodiment. In at least one embodiment, the code and / or data storage 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more aspects of the embodiment while backpropagating input / output data and / or weight parameters during training and / or inference using one or more aspects of the embodiment. In at least one embodiment, training logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software for controlling timing and / or ordering, and code and / or data storage 605 may be loaded with weights and / or other parameter information to configure logic including integer and / or floating point units (collectively arithmetic logic units (ALUs)).

[0061] In at least one embodiment, code, such as graph code, causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache, or system memory. In at least one embodiment, any portion of code and / or data storage 605 may be internal or external to one or more processors, or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 605 is internal or external to the processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0062] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be a combined storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0063] In at least one embodiment, the inference and / or training logic 615 may include one or more arithmetic logic units (“ALUs”) 610, including, without limitation, integer and / or floating point units, for performing logical and / or arithmetic operations based at least in part on or indicated by the training and / or inference code (e.g., graph code), the results of which may generate activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 620, which are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, the activations stored in activation storage 620 are generated according to linear algebra and / or matrix-based calculations performed by ALU 610 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 605 and / or data storage 601 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyper-parameters, any or all of which may be stored in code and / or data storage 605, or code and / or data storage 601, or in another storage, on-chip or off-chip.

[0064] In at least one embodiment, ALU 610 is included within one or more processors or other hardware logic devices or circuits, while in other embodiments, ALU 610 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 610 may be included within an execution unit of a processor or may otherwise be included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing unit, graphics processing unit, fixed function unit, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may share processors or other hardware logic devices or circuits, while in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic devices or circuits and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0065] In at least one embodiment, activation storage 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 620 is internal or external to a processor, for example, or whether it includes DRAM, SRAM, flash memory, or some other type of storage, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in neural network inference and / or training, or any combination of these factors.

[0066] In at least one embodiment, the inference and / or training logic 615 shown in Figure 6A may be used in conjunction with an application specific integrated circuit ("ASIC") such as Google's TensorFlow® processing unit, Graphcore™'s inference processing unit (IPU), or Intel Corp's Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, the inference and / or training logic 615 shown in Figure 6A may be used in conjunction with other hardware such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or field programmable gate arrays ("FPGAs").

[0067] FIG. 6B illustrates inference and / or training logic 615, according to at least one embodiment. In at least one embodiment, inference and / or training logic 615 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, inference and / or training logic 615 illustrated in FIG. 6B may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as Google's TensorFlow® processing unit, Graphcore™'s inference processing unit (IPU), or Intel Corp.'s Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, inference and / or training logic 615 illustrated in FIG. 6B may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or field programmable gate arrays ("FPGAs"). In at least one embodiment, inference and / or training logic 615 includes, without limitation, code and / or data storage 601 and code and / or data storage 605, which may be used to store code (e.g., graph code), weight and / or bias values, gradient information, momentum values, and / or other parameter or hyper-parameter information. In at least one embodiment shown in FIG. 6B , code and / or data storage 601 and code and / or data storage 605 are each associated with dedicated computational resources, such as computation hardware 602 and computation hardware 606, respectively. In at least one embodiment, computation hardware 602 and computation hardware 606 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, with the results stored in activation storage 620.

[0068] In at least one embodiment, each of code and / or data storage 601 and 605 and corresponding computational hardware 602 and 606 corresponds to a different layer of a neural network, such that activations resulting from one “storage / computation pair 601 / 602” of code and / or data storage 601 and computational hardware 602 are provided as input to a “storage / computation pair 605 / 606” of the next code and / or data storage 605 and computational hardware 606 to reflect the conceptual organization of the neural network. In at least one embodiment, storage / computation pairs 601 / 602 and 605 / 606 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 615 after or in parallel with storage / computation pairs 601 / 602 and 605 / 606.

[0069] In at least one embodiment, one or more systems illustrated in Figures 6A-6B are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in Figures 6A-6B are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in Figures 6A-6B are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in Figures 6A-6B are utilized to implement one or more systems and / or processes, such as those described in connection with Figures 1-5.

[0070] Neural network training and deployment FIG. 7 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 706 is trained using a training dataset 702. In at least one embodiment, the training framework 704 is the PyTorch framework, while in other embodiments, the training framework 704 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 704 trains the untrained neural network 706 and enables it to be trained using processing resources described herein to generate a trained neural network 708. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0071] In at least one embodiment, the untrained neural network 706 is trained using supervised learning, where the training dataset 702 includes inputs paired with desired outputs, or the training dataset 702 includes inputs with known outputs, and the outputs of the neural network 706 are manually scored. In at least one embodiment, the untrained neural network 706 is trained in a supervised manner, processing inputs from the training dataset 702 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through the untrained neural network 706. In at least one embodiment, the training framework 704 adjusts the weights that control the untrained neural network 706. In at least one embodiment, the training framework 704 includes tools to monitor how well the untrained neural network 706 is converging toward a model, such as the trained neural network 708, that is suitable for generating correct answers, such as in the results 714, based on input data, such as the new dataset 712. In at least one embodiment, the training framework 704 iteratively trains the untrained neural network 706 while adjusting weights to refine the output of the untrained neural network 706 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, the training framework 704 trains the untrained neural network 706 until the untrained neural network 706 reaches a desired accuracy. In at least one embodiment, the trained neural network 708 can then be deployed to perform any number of machine learning operations.

[0072] In at least one embodiment, the untrained neural network 706 is trained using unsupervised learning, where the untrained neural network 706 attempts to train itself using unlabeled data. In at least one embodiment, the training dataset 702 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 706 can learn groupings within the training dataset 702 and determine how individual inputs relate to the untrained dataset 702. In at least one embodiment, unsupervised training can be used to generate a self-organizing map for the trained neural network 708, which can perform operations useful for reducing the dimensionality of the new dataset 712. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new dataset 712 that deviate from the normal patterns of the new dataset 712.

[0073] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training dataset 702. In at least one embodiment, the training framework 704 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 708 to adapt to a new dataset 712 without forgetting the knowledge instilled in the trained neural network 708 during initial training.

[0074] In at least one embodiment, training framework 704 is a framework that operates in conjunction with a software development toolkit, such as the OpenVINO (Open Visual Inference and Neural network Optimization) toolkit, which in at least one embodiment is a toolkit such as that developed by Intel Corporation of Santa Clara, California.

[0075] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications, particularly neural network applications, for various tasks and operations such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variations thereof.

[0076] In at least one embodiment, OpenVINO supports neural network models for a variety of tasks and operations, such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., human and / or object), monocular depth estimation, image inpainting, style transfer, action recognition, colorization, and / or variations thereof.

[0077] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as a model optimizer. In at least one embodiment, the model optimizer is a command-line tool that facilitates the transition between training and deployment of neural network models. In at least one embodiment, the model optimizer optimizes neural network models for execution on various devices and / or processing units, such as GPUs, CPUs, PPUs, GPGPUs, and / or variations thereof. In at least one embodiment, the model optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the model optimizer reduces the number of layers in the model. In at least one embodiment, the model optimizer removes layers of the model used for training. In at least one embodiment, the model optimizer performs various neural network operations, such as modifying inputs to the model (e.g., resizing inputs to the model), modifying the size of inputs to the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalizing, standardizing, quantifying (e.g., converting model weights from a first representation, such as floating point, to a second representation, such as integer), and / or variations thereof.

[0078] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as an inference engine. In at least one embodiment, the inference engine is a C++ library or any suitable programming language library. In at least one embodiment, the inference engine is utilized to infer input data. In at least one embodiment, the inference engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the inference engine implements one or more API functions to process intermediate representations, configure input and / or output formats, and / or execute models on one or more devices.

[0079] In at least one embodiment, OpenVINO provides various functions for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems utilizing one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions for, for example, running a first portion of code on a CPU and a second portion of the code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions for executing one or more layers of a neural network on one or more devices (e.g., running a first set of layers on a first device, such as a GPU, and a second set of layers on a second device, such as a CPU).

[0080] In at least one embodiment, OpenVINO includes various functionality similar to functionality associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or variations thereof. In at least one embodiment, one or more CUDA programming model operations are executed using OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0081] In at least one embodiment, one or more systems illustrated in FIG. 7 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 7 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 7 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 7 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0082] Data Center 8 illustrates an exemplary data center 800 in which at least one embodiment may be used. In at least one embodiment, data center 800 includes a data center infrastructure layer 810, a framework layer 820, a software layer 830, and an application layer 840.

[0083] 8, in at least one embodiment, data center infrastructure layer 810 may include a resource orchestrator 812, grouped computing resources 814, and node computing resources (“node CRs”) 816(1) through 816(N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, node CRs 816(1) through 816(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 818(1) through 818(N) (e.g., dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 816(1)-816(N) may be a server having one or more of the computing resources described above.

[0084] In at least one embodiment, grouped computing resources 814 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). In at least one embodiment, separate groups of node CRs within grouped computing resources 814 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0085] In at least one embodiment, resource orchestrator 812 may configure or otherwise control one or more nodes CR 816(1)-816(N) and / or grouped computing resources 814. In at least one embodiment, resource orchestrator 812 may include a software design infrastructure (“SDI”) management entity for data center 800. In at least one embodiment, resource orchestrator 812 may include hardware, software, or some combination thereof.

[0086] 8 , framework layer 820 includes a job scheduler 822, a configuration manager 824, a resource manager 826, and a distributed file system 828. In at least one embodiment, framework layer 820 may include a framework for supporting software 832 in software layer 830 and / or one or more applications 842 in application layer 840. In at least one embodiment, software 832 or application 842 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 820 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter “Spark”), which can use distributed file system 828 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 822 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 800. In at least one embodiment, configuration manager 824 may be capable of configuring different tiers, such as software tier 830, as well as framework tier 820, which includes Spark and distributed file system 828 to support large-scale data processing. In at least one embodiment, resource manager 826 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 828 and job scheduler 822. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 814 in data center infrastructure tier 810.In at least one embodiment, resource manager 826 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 812.

[0087] In at least one embodiment, software 832 included in software layer 830 may include software used by nodes CR 816(1)-816(N), grouped computing resources 814, and / or at least a portion of distributed file system 828 of framework layer 820. In at least one embodiment, the one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0088] In at least one embodiment, applications 842 included in application layer 840 may include one or more types of applications used by at least a portion of nodes CR 816(1)-816(N), grouped computing resources 814, and / or distributed file system 828 of framework layer 820. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, training or inference software, applications including machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), and machine learning applications, or other machine learning applications used in conjunction with one or more embodiments.

[0089] In at least one embodiment, any of configuration manager 824, resource manager 826, and resource orchestrator 812 may implement any number and types of self-corrective actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-corrective actions may enable a data center operator of data center 800 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0090] In at least one embodiment, data center 800 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 800. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 800 by using weight parameters calculated by one or more training techniques described herein.

[0091] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0092] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 8 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0093] In at least one embodiment, one or more systems illustrated in FIG. 8 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 8 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 8 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 8 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0094] Autonomous Vehicles 9A illustrates an example of an autonomous vehicle 900 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 900 (alternatively referred to herein as "vehicle 900") may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 900 may be a semi-tractor trailer truck for hauling cargo. In at least one embodiment, the vehicle 900 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0095] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In at least one embodiment, vehicle 900 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 900 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0096] In at least one embodiment, vehicle 900 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 900 may include a propulsion system 950 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 950 may be coupled to a drive train of vehicle 900, which may include, without limitation, a transmission to enable propulsion of vehicle 900. In at least one embodiment, propulsion system 950 may be controlled in response to receiving a signal from a throttle / accelerator 952.

[0097] In at least one embodiment, a steering system 954, which may include without limitation a steering wheel, is used to steer the vehicle 900 (e.g., along a desired path or route) when the propulsion system 950 is operating (e.g., when the vehicle 900 is moving). In at least one embodiment, the steering system 954 may receive signals from a steering actuator 956. In at least one embodiment, the steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 946 may be used to operate the vehicle brakes in response to receiving signals from a brake actuator 948 and / or brake sensor.

[0098] In at least one embodiment, controller 936, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 9A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 900. For example, in at least one embodiment, controller 936 may send signals to operate vehicle brakes via brake actuators 948, steering system 954 via steering actuators 956, and propulsion system 950 via throttle / accelerator 952. In at least one embodiment, controller 936 may include one or more on-board (e.g., integrated) computing devices that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 900. In at least one embodiment, controller 936 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functionalities, two or more controllers may handle a single functionality, and / or some combination thereof.

[0099] In at least one embodiment, controller 936 provides signals to control one or more components and / or systems of vehicle 900 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system ("GNSS") sensors 958 (e.g., global positioning system sensors), RADAR sensors 960, ultrasonic sensors 962, LIDAR sensors 964, inertial measurement units ("IMUs"). 9A ), a long-range camera (not shown in FIG. 9A ), a mid-range camera (not shown in FIG. 9A ), a speed sensor 944 (e.g., for measuring the speed of the vehicle 900), a vibration sensor 942, a steering sensor 940, a brake sensor (e.g., as part of a brake sensor system 946), and / or other types of sensors.

[0100] In at least one embodiment, one or more of the controllers 936 may receive input (e.g., represented by input data) from an instrument cluster 932 of the vehicle 900 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 934, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 900. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 9A )), location data (e.g., the location of vehicle 900 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by controller 936, etc. For example, in at least one embodiment, HMI display 934 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0101] In at least one embodiment, vehicle 900 further includes a network interface 924, which may use a wireless antenna 926 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 924 may be capable of communicating over a Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") network, etc. Additionally, in at least one embodiment, the wireless antenna 926 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area network (LON) protocols such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area network ("LPWAN") protocols such as LoRaWAN, SigFox, etc.

[0102] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 9A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0103] 9B illustrates example camera locations and fields of view for the autonomous vehicle 900 of FIG. 9A according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are an example example and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on the vehicle 900.

[0104] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 900. In at least one embodiment, the camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0105] In at least one embodiment, one or more of the cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more of the cameras (e.g., all of the cameras) may simultaneously record and provide image data (e.g., video).

[0106] In at least one embodiment, one or more cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from inside the vehicle 900 (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate matches the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. In at least one embodiment, for side view cameras, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0107] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 900 may be used for a surroundings view to facilitate identification of the path and obstacles ahead and, in conjunction with controller 936 and / or one or more of the control SoCs, may assist in providing information essential for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the ADAS functions similar to LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0108] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 970 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While FIG. 9B shows only one wide-angle camera 970, in other embodiments, there may be any number (including zero) of wide-angle cameras on the vehicle 900. In at least one embodiment, any number of long-range cameras 998 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range cameras 998 may also be used for object detection and classification, as well as basic object tracking.

[0109] In at least one embodiment, any number of stereo cameras 968 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 968 may include an integrated control unit with a scalable processing unit, which may provide a programmable logic gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 900 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 968 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 900 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 968 may be used in addition to or instead of those described herein.

[0110] In at least one embodiment, cameras having a field of view that includes a portion of the environment to the sides of vehicle 900 (e.g., side view cameras) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 974 (e.g., four surrounding cameras as shown in FIG. 9B ) may be disposed on vehicle 900. In at least one embodiment, surrounding cameras 974 may include, without limitation, any number and combination of wide-angle cameras, fisheye cameras, 360-degree cameras, and / or the like. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of vehicle 900. In at least one embodiment, vehicle 900 may use three surrounding cameras 974 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0111] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 900 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras that are also suitable as front cameras as described herein (e.g., long-range camera 998 and / or mid-range camera 976, stereo camera 968, infrared camera 972, etc.).

[0112] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 9B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0113] FIG. 9C is a block diagram illustrating an example system architecture for the autonomous vehicle 900 of FIG. 9A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 900 of FIG. 9C is shown connected via a bus 902. In at least one embodiment, the bus 902 may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, the CAN may be a network internal to the vehicle 900 used to help control various features and functions of the vehicle 900, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 902 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 902 may be read to determine steering angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 902 may be an ASIL B compliant CAN bus.

[0114] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or instead of CAN. In at least one embodiment, there may be any number of buses forming bus 902, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or to provide redundancy. For example, a first bus may be used for collision avoidance functions and a second bus may be used for actuation control. In at least one embodiment, each bus of bus 902 may communicate with one of the components of vehicle 900, and two or more buses of bus 902 may communicate with corresponding components. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 904 (e.g., SoC 904(A) and SoC 904(B)), each of the controllers 936, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 900) and may be connected to a common bus, such as a CAN bus.

[0115] In at least one embodiment, vehicle 900 may include one or more controllers 936, such as those described herein with respect to FIG. 9A . In at least one embodiment, controller 936 may be used for a variety of functions. In at least one embodiment, controller 936 may be coupled to any of a variety of other components and systems of vehicle 900 and may be used for control of vehicle 900, artificial intelligence of vehicle 900, infotainment of vehicle 900, and / or other functions.

[0116] In at least one embodiment, vehicle 900 may include any number of SoCs 904. In at least one embodiment, each of SoCs 904 may include, without limitation, a central processing unit ("CPU") 906, a graphics processing unit ("GPU") 908, a processor 910, a cache 912, an accelerator 914, a data store 916, and / or other components and features not shown. In at least one embodiment, SoC 904 may be used to control vehicle 900 in a variety of platforms and systems. For example, in at least one embodiment, SoC 904 may be incorporated into a system (e.g., that of vehicle 900) having a high-definition ("HD") map 922 that can obtain map refreshes and / or updates via a network interface 924 from one or more servers (not shown in FIG. 9C ).

[0117] In at least one embodiment, CPU 906 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 906 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 906 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 906 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 megabytes (MB) of L2 cache). In at least one embodiment, CPU 906 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 906 to be active at any given time.

[0118] In at least one embodiment, one or more of the CPUs 906 may implement power management functions, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to conserve dynamic power; each core clock may be gated when such core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPUs 906 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0119] In at least one embodiment, GPU 908 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 908 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 908 may use an extended tensor instruction set. In at least one embodiment, GPU 908 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 908 may include at least eight streaming microprocessors. In at least one embodiment, GPU 908 may use a compute application programming interface (API). In at least one embodiment, the GPU 908 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA model).

[0120] In at least one embodiment, one or more of the GPUs 908 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 908 may be fabricated on Fin field-effect transistor ("FinFET") circuitry. In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0121] In at least one embodiment, one or more of the GPUs 908 may include high bandwidth memory (“HBM”) and / or a 16 GB HBM2 memory subsystem, providing, in some examples, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or instead of the HBM memory.

[0122] In at least one embodiment, the GPU 908 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the GPU 908 to directly access the page tables of the CPU 906. In at least one embodiment, when the GPU 908 memory management unit ("MMU") experiences a GPU miss, an address translation request may be sent to the CPU 906. In at least one embodiment, in response, one of the CPUs 906 may look up the virtual-to-physical address mapping in its own page table and send the translation back to the GPU 908. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 906 and the GPU 908 memory, thereby simplifying programming the GPU 908 and porting applications to the GPU 908.

[0123] In at least one embodiment, GPU 908 may include any number of access counters that can record the frequency of GPU 908's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0124] In at least one embodiment, one or more of the SoCs 904 may include any number of caches 912, including those described herein. For example, in at least one embodiment, the caches 912 may include a level 3 (“L3”) cache available to both the CPU 906 and the GPU 908 (e.g., connected to both the CPU 906 and the GPU 908). In at least one embodiment, the caches 912 may include a write-back cache that can record line state through the use of a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more of memory, depending on the embodiment, although smaller cache sizes may also be used.

[0125] In at least one embodiment, one or more of the SoCs 904 may include one or more accelerators 914 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 904 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 908 and offload some of the GPU 908's tasks (e.g., freeing up more cycles for the GPU 908 to perform other tasks). In at least one embodiment, the accelerators 914 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, the CNN may include a region-based, i.e., regional convolutional neural network (“RCNN”), and Faster RCNN (e.g., used for object detection), or other types of CNN.

[0126] In at least one embodiment, accelerator 914 (e.g., a hardware-accelerated cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, the DLAs may include, without limitation, one or more tensor processing units (“TPUs”), which may be further configured to provide tens of trillions of operations per second for deep learning applications and inference. In at least one embodiment, the TPUs may be accelerators configured and optimized for performing image processing functions (e.g., CNN, RCNN, etc.). In at least one embodiment, the DLAs may be further optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the design of the DLAs allows for improved performance per millimeter over typical general-purpose GPUs, and typically greatly exceeds the performance of CPUs. In at least one embodiment, the TPU may execute several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, CNNs for object identification and detection using data from a camera sensor, CNNs for distance estimation using data from a camera sensor, CNNs for emergency vehicle detection and identification using data from a microphone, CNNs for face recognition and vehicle owner identification using data from a camera sensor, and / or CNNs for security and / or safety events.

[0127] In at least one embodiment, the DLA may perform any function of the GPU 908, and a designer may target either the DLA or the GPU 908 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 908 and / or accelerator 914.

[0128] In at least one embodiment, accelerator 914 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 938, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”) processors, and / or any number of vector processors.

[0129] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0130] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 906. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0131] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0132] In at least one embodiment, each of the vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of the vector processors may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a common computer vision algorithm on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on an image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0133] In at least one embodiment, the accelerator 914 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 914. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0134] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used.

[0135] In at least one embodiment, one or more of the SoCs 904 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0136] In at least one embodiment, accelerator 914 has a variety of applications for autonomous driving. In at least one embodiment, PVAs can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA performance is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, PVAs perform well even with small data sets for semi-dense or dense regular computations that may require low-latency, low-power, and predictable run times. In at least one embodiment, PVAs can be designed to run traditional computer vision algorithms, such as in vehicle 900, because they may be effective for object detection and integer arithmetic.

[0137] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0138] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0139] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence measure allows the system to make further decisions regarding which detections should be considered positive detections rather than false detections. In at least one embodiment, the system may set a threshold for confidence and consider only detections above the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as, among others, the bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 966 that correlates with the orientation of the vehicle 900, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 964 or a RADAR sensor 960).

[0140] In at least one embodiment, one or more of the SoCs 904 may include a data store 916 (e.g., memory). In at least one embodiment, the data store 916 may be on-chip memory of the SoC 904, which may store neural networks executed on the GPU 908 and / or DLA. In at least one embodiment, the capacity of the data store 916 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 916 may comprise an L2 or L3 cache.

[0141] In at least one embodiment, one or more of the SoCs 904 may include any number of processors 910 (e.g., embedded processors). In at least one embodiment, the processors 910 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 904 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage thermal and temperature sensors of the SoC 904, and / or manage the power state of the SoC 904. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 904 may use the ring oscillator to detect the temperature of the CPU 906, GPU 908, and / or accelerator 914. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 904 in a low power state, and / or place the vehicle 900 in a driver-safety shutdown mode (e.g., bring the vehicle 900 to a safety shutdown).

[0142] In at least one embodiment, processor 910 may further include a set of embedded processors that can serve as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM.

[0143] In at least one embodiment, processor 910 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0144] In at least one embodiment, the processor 910 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operation. In at least one embodiment, the processor 910 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 910 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0145] In at least one embodiment, processor 910 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that performs video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 970, surround camera 974, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 904 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading, without limitation, to activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain features are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0146] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0147] In at least one embodiment, the video image combiner may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image combiner may also be used to combine user interfaces when the operating system desktop is in use, eliminating the need for the GPU 908 to continually render new surfaces. In at least one embodiment, the video image combiner may be used to offload the GPU 908 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0148] In at least one embodiment, one or more of the SoCs 904 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 904 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0149] In at least one embodiment, one or more SoCs of SoC 904 may further include peripherals, audio encoders / decoders ("codecs"), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. In at least one embodiment, SoC 904 may be used to process data from cameras (e.g., connected via a gigabit multimedia serial link and an Ethernet channel), data from sensors (e.g., LIDAR sensor 964, RADAR sensor 960, etc., which may be connected via an Ethernet channel), data from bus 902 (e.g., vehicle 900 speed, steering wheel position, etc.), data from GNSS sensor 958 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 904 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from CPU 906.

[0150] In at least one embodiment, the SoC 904 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and providing a platform for a flexible and reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 904 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 914, when combined with the CPU 906, GPU 908, and data store 916, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0151] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language such as C to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0152] Embodiments described herein enable multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Levels 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN running on the DLA or a separate GPU (e.g., GPU 920) may include text and word recognition to enable the neural network to read and understand traffic signs, including signs for which it was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0153] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: Flashing Indicates Icy Conditions" in conjunction with a light may be interpreted separately or collectively by several neural networks. In at least one embodiment, such a warning sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Indicates Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be run simultaneously, such as within the DLA and / or on the GPU 908.

[0154] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from a camera sensor to identify the presence of an authorized driver and / or owner of vehicle 900. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves such vehicle. In this manner, SoC 904 provides security against theft and / or carjacking.

[0155] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 996 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 904 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 958. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when operating in North America, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program for executing an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 962 until the emergency vehicle has passed.

[0156] In at least one embodiment, vehicle 900 may include a CPU 918 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 904 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 918 may include, for example, an X86 processor. CPU 918 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 904 and / or monitoring the status and health of controller 936 and / or infotainment system on a chip ("infotainment SoC") 930.

[0157] In at least one embodiment, vehicle 900 may include a GPU 920 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 904 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, GPU 920 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 900.

[0158] In at least one embodiment, vehicle 900 may further include a network interface 924, which may include, without limitation, a wireless antenna 926 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 924 may be used to enable wireless connectivity to Internet cloud services (e.g., servers and / or other network devices), with other vehicles, and / or with computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 90 and another vehicle and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 900 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 900). In at least one embodiment, such aforementioned functionality may be part of a cooperative adaptive cruise control function of the vehicle 900.

[0159] In at least one embodiment, the network interface 924 may include an SoC that provides modulation and demodulation functionality and enables the controller 936 to communicate over a wireless network. In at least one embodiment, the network interface 924 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, the frequency conversion may be performed in any technically feasible manner. For example, the frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0160] In at least one embodiment, vehicle 900 may further include a data store 928, which may include, without limitation, off-chip (e.g., not on SoC 904) storage. In at least one embodiment, data store 928 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash memory, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0161] In at least one embodiment, vehicle 900 may further include GNSS sensors 958 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 958 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0162] In at least one embodiment, vehicle 900 may further include a RADAR sensor 960. In at least one embodiment, RADAR sensor 960 may be used by vehicle 900 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, RADAR sensor 960 may use a CAN bus and / or bus 902 for control (e.g., to transmit data generated by RADAR sensor 960) and to access object tracking data, and in some examples, may have access to an Ethernet channel to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 960 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 960 are pulse-Doppler RADAR sensors.

[0163] In at least one embodiment, the RADAR sensor 960 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250 m (meter) range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 960 may help distinguish between static and moving objects and may be used by the ADAS system 938 to provide emergency braking assistance and forward collision warning. In at least one embodiment, the sensors 960 included in the long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the center four antennas may generate a focused beam pattern designed to record the surroundings of vehicle 900 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting the lane of vehicle 900.

[0164] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 960 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots toward the rear and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 938 to provide blind spot detection and / or lane change assistance.

[0165] In at least one embodiment, vehicle 900 may further include ultrasonic sensors 962. In at least one embodiment, ultrasonic sensors 962, which may be located at front, rear, and / or side locations of vehicle 900, may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 962 may be used, and different ultrasonic sensors 962 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 962 may operate at functional safety level ASIL B.

[0166] In at least one embodiment, vehicle 900 may include a LIDAR sensor 964. In at least one embodiment, LIDAR sensor 964 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor 964 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 900 may include multiple LIDAR sensors 964 (e.g., two, four, six, etc.), which may use an Ethernet channel (e.g., to provide data to a Gigabit Ethernet switch).

[0167] In at least one embodiment, the LIDAR sensor 964 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 964 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, the LIDAR sensor 964 may include a small device that can be integrated into the front, rear, side, and / or corner locations of the vehicle 900. In at least one embodiment, the LIDAR sensor 964 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 964 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0168] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. In at least one embodiment, the 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 900 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 900 to the object. In at least one embodiment, the flash LIDAR allows a highly accurate, undistorted image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 900. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light as a 3D range point cloud and co-registered intensity data.

[0169] In at least one embodiment, vehicle 900 may further include an IMU sensor 966. In at least one embodiment, IMU sensor 966 may be positioned at the center of a rear axle of vehicle 900. In at least one embodiment, IMU sensor 966 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, multiple magnetic compasses, and / or other types of sensors. In at least one embodiment, such as in a six-axis application, IMU sensor 966 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a nine-axis application, IMU sensor 966 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0170] In at least one embodiment, the IMU sensor 966 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 966 enables the vehicle 900 to estimate its heading by directly observing velocity changes and correlating them from the GPS to the IMU sensor 966 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 966 and the GNSS sensor 958 may be combined into a single integrated unit.

[0171] In at least one embodiment, vehicle 900 may include microphones 996 located in and / or around vehicle 900. In at least one embodiment, microphones 996 may be used for, among other things, detection and identification of emergency vehicles.

[0172] In at least one embodiment, vehicle 900 may further include any number of camera types, including stereo cameras 968, wide-angle cameras 970, infrared cameras 972, perimeter cameras 974, long-range cameras 998, mid-range cameras 976, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 900. In at least one embodiment, the types of cameras used vary depending on vehicle 900. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 900. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 900 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may support, by way of example and not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera may be as described in more detail herein above with respect to Figures 9A and 9B.

[0173] In at least one embodiment, vehicle 900 may further include a vibration sensor 942. In at least one embodiment, vibration sensor 942 may measure vibration of a component of vehicle 900, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 942 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0174] In at least one embodiment, vehicle 900 may include an ADAS system 938. In at least one embodiment, ADAS system 938 may include, in some examples, without limitation, an SoC. In at least one embodiment, the ADAS systems 938 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0175] In at least one embodiment, the ACC system may use a RADAR sensor 960, a LIDAR sensor 964, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle directly in front of the vehicle 900 and automatically adjusts the speed of the vehicle 900 to maintain a safe distance from the vehicle in front. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 900 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0176] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by network interface 924 and / or wireless antenna 926 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, V2V communication provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 900 and in the same lane), while I2V communication provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 900 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0177] In at least one embodiment, the FCW system is designed to alert drivers to hazards so that such drivers can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0178] In at least one embodiment, an AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0179] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 900 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variation of the LDW system. In at least one embodiment, the LKA system provides steering input or brake control to correct the vehicle 900 if the vehicle 900 begins to stray from its lane.

[0180] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 960 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0181] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 900. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 960 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to provide feedback to the driver, such as a display, speaker, and / or vibration components.

[0182] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 900 itself determines whether to follow the results from the primary computer (e.g., the first controller of the controllers 936) or the secondary computer (e.g., the second controller of the controllers 1136). For example, in at least one embodiment, the ADAS system 938 may be a backup and / or secondary computer for transmitting perceptual information to a rationality module of the backup computer. In at least one embodiment, a rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 938 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0183] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers provide conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0184] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary computer and the secondary computer. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 904.

[0185] In at least one embodiment, the ADAS system 938 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and a neural network may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides consistent overall results, the supervisory MCU may have greater confidence that the overall results are correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0186] In at least one embodiment, the output of the ADAS system 938 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 938 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0187] In at least one embodiment, vehicle 900 may further include an infotainment SoC 930 (e.g., an in-vehicle infotainment system (IVI)). While illustrated and described as an SoC, infotainment system SoC 930, in at least one embodiment, may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 930 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, reverse parking assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 900. For example, infotainment SoC 930 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 934, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 930 may also be used to provide information (e.g., visual and / or auditory) to a user of vehicle 900, such as information from ADAS system 938, autonomous driving information such as vehicle maneuver plans, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0188] In at least one embodiment, infotainment SoC 930 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 930 may communicate with other devices, systems, and / or components of vehicle 900 via bus 902. In at least one embodiment, infotainment SoC 930 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 936 (e.g., vehicle 900's primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 930 may place vehicle 900 in a driver-safety shutdown mode, as described herein.

[0189] In at least one embodiment, vehicle 900 may further include an instrument cluster 932 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 932 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 932 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 930 and instrument cluster 932. In at least one embodiment, instrument cluster 932 may be included as part of infotainment SoC 930, or vice versa.

[0190] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 9C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0191] 9D is a diagram of a system for communicating between a cloud-based server and the autonomous vehicle 900 of FIG. 9A , according to at least one embodiment. In at least one embodiment, the system may include any number and type of vehicles, including, without limitation, a server 978, a network 990, and a vehicle 900. In at least one embodiment, the server 978 may include, without limitation, multiple GPUs 984(A)-984(H) (collectively referred to herein as GPUs 984), PCIe switches 982(A)-982(D) (collectively referred to herein as PCIe switches 982), and / or CPUs 980(A)-980(B) (collectively referred to herein as CPUs 980). In at least one embodiment, the GPUs 984, CPUs 980, and PCIe switches 982 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 988 developed by NVIDIA, and / or a PCIe connection 986. In at least one embodiment, the GPUs 984 are connected to each other via NVLink and / or NVS switch SoCs, and the GPUs 984 and PCIe switches 982 are connected via PCIe interconnects. While eight GPUs 984, two CPUs 980, and four PCIe switches 982 are shown, this is not intended to be limiting. In at least one embodiment, each of the servers 978 may include any number of GPUs 984, CPUs 980, and / or PCIe switches 982 in any combination, including, but not limited to, 8, 16, 32, and / or more GPUs 984.

[0192] In at least one embodiment, server 978 may receive image data from vehicles over network 990 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 978 may transmit neural network 992, updated or otherwise configured neural network 1192, and / or map information 994, including, without limitation, information regarding traffic and road conditions, to vehicles over network 990. In at least one embodiment, updates to map information 994 may include, without limitation, updates to HD map 922, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 992 and / or map information 994 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 978 and / or other servers).

[0193] In at least one embodiment, server 978 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 990) and / or used by server 978 to remotely monitor the vehicle.

[0194] In at least one embodiment, server 978 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 978 may include a deep learning supercomputer and / or dedicated AI computer powered by GPU 984, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 978 may also include a deep learning infrastructure using a CPU-powered data center.

[0195] In at least one embodiment, the deep learning infrastructure of server 978 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 900. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 900, such as a series of images and / or objects that vehicle 900 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 900; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 900 has failed, server 978 may send a signal to vehicle 900 instructing the fail-safe computer of vehicle 900 to take control, notify the occupants, and complete a safe stopping maneuver.

[0196] In at least one embodiment, server 978 may include a GPU 984 and one or more programmable inference accelerators (e.g., NVIDIA TensorRT3 devices). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 615 is used to execute one or more embodiments. Details regarding hardware structure 615 are provided herein in conjunction with FIG. 6A and / or FIG. 6B.

[0197] In at least one embodiment, one or more systems illustrated in Figures 9A-9D are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in Figures 9A-9D are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in Figures 9A-9D are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in Figures 9A-9D are utilized to implement one or more systems and / or processes, such as those described in connection with Figures 1-5.

[0198] Computer Systems 10 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof, formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1000 may include components such as, without limitation, processor 1002 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1000 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1000 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux), embedded software, and / or graphical user interfaces may also be used.

[0199] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0200] In at least one embodiment, computer system 1000 may include, without limitation, a processor 1002, which may include one or more execution units 1008 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1000 is a single-processor desktop or server system, while in other embodiments, computer system 1000 may be a multiprocessor system. In at least one embodiment, processor 1002 may include, without limitation, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1002 may be coupled to a processor bus 1010, which may transmit digital signals between processor 1002 and other components within computer system 1000.

[0201] In at least one embodiment, processor 1002 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1004. In at least one embodiment, processor 1002 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1002. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1006 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and instruction pointer registers.

[0202] In at least one embodiment, processor 1002 also includes an execution unit 1008, including, without limitation, logic for performing integer and floating-point operations. In at least one embodiment, processor 1002 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1008 may include logic for a packed instruction set 1009. In at least one embodiment, including a packed instruction set 1009, along with associated circuitry for executing the instructions, in a general-purpose processor's instruction set allows operations used by many multimedia applications to be performed using packed data in processor 1002. In at least one embodiment, many multimedia applications can be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0203] In at least one embodiment, the execution unit 1008 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, and other types of logic circuitry. In at least one embodiment, the computer system 1000 may include, without limitation, a memory 1020. In at least one embodiment, the memory 1020 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or another memory device. In at least one embodiment, the memory 1020 may store instructions 1019 and / or data 1021 represented by data signals that may be executed by the processor 1002.

[0204] In at least one embodiment, a system logic chip may be coupled to the processor bus 1010 and the memory 1020. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1016, and the processor 1002 may communicate with the MCH 1016 via the processor bus 1010. In at least one embodiment, the MCH 1016 may provide a high-bandwidth memory path 1018 to the memory 1020 for storing instructions and data, as well as for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1016 may route data signals between the processor 1002, the memory 1020, and other components of the computer system 1000, and may bridge data signals between the processor bus 1010, the memory 1020, and a system I / O interface 1022. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1016 may be coupled to memory 1020 via a high-bandwidth memory path 1018, and the graphics / video card 1012 may be coupled to the MCH 1016 via an accelerated graphics port (“AGP”) interconnect 1014.

[0205] In at least one embodiment, computer system 1000 may use system I / O interface 1022, a proprietary hub interface bus, to couple MCH 1016 to I / O controller hub (“ICH”) 1030. In at least one embodiment, ICH 1030 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1020, a chipset, and processor 1002. Examples may include, without limitation, an audio controller 1029, a firmware hub ("flash BIOS") 1028, a wireless transceiver 1026, data storage 1024, a legacy I / O controller 1023 including a user input and keyboard interface 1025, a serial expansion port 1027 such as a Universal Serial Bus ("USB") port, and a network controller 1034. In at least one embodiment, data storage 1024 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0206] In at least one embodiment, Figure 10 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 10 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in Figure 10 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1000 may be interconnected using a compute express link (CXL) interconnect.

[0207] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 10 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0208] In at least one embodiment, one or more systems illustrated in FIG. 10 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 10 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 10 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 10 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0209] 11 is a block diagram illustrating an electronic device 1100 for utilizing a processor 1110, according to at least one embodiment. In at least one embodiment, electronic device 1100 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0210] In at least one embodiment, electronic device 1100 may include a processor 1110 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices, without limitation. 2 The devices may be coupled using a bus or interface such as a C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 11 illustrates a system including interconnected hardware devices or “chips,” while in other embodiments, FIG. 11 may illustrate an exemplary SoC. In at least one embodiment, the devices illustrated in FIG. 11 may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of FIG. 11 may be interconnected using a Compute Express Link (CXL) interconnect.

[0211] In at least one embodiment, FIG. 11 illustrates a display 1124, a touch screen 1125, a touch pad 1130, a Near Field Communications unit ("NFC") 1145, a sensor hub 1140, a thermal sensor 1146, an Express Chipset ("EC") 1135, a Trusted Platform Module ("TPM") 1138, a BIOS / firmware / flash memory ("BIOS,FW flash") 1122, a DSP 1160, a drive 1120, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1150, a Bluetooth unit 1152, a wireless wide area network unit ("WWAN") 1154, a Bluetooth module 1154, a Bluetooth-enabled device ("BMD") 1156, a Bluetooth-enabled device ("BMD") 1158, a Bluetooth-enabled device ("BMD") 1158, a Bluetooth-enabled device ("BMD") 1159, a Bluetooth-enabled device ("BMD") 1160, a Bluetooth-enabled device ("BMD") 1161, a Bluetooth-enabled device ("BMD") 1162, a Bluetooth-enabled device ("BMD") 1163, a Bluetooth-enabled device ("BMD") 1164, a Bluetooth-enabled device ("BMD") 1165, a Bluetooth-enabled device ("BMD") 1166, a Bluetooth-enabled device ("BMD") 1167, a Bluetooth-enabled device ("BMD") 1168, a Bluetooth-enabled device ("BMD") 1169, a Bluetooth-enabled device ("BMD") 1170, a Bluetooth-enabled device ("BMD") 1172, a Bluetooth-enabled device ("BMD") 1174, a Bluetooth-enabled device ("BMD") 1176, a Bluetooth-enabled device ( The memory may include a memory card (RAM) 1156, a Global Positioning System (GPS) unit 1155, a camera such as a USB 3.0 camera ("USB 3.0 camera") 1154, and / or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1115, for example, implemented to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0212] In at least one embodiment, other components may be communicatively coupled to the processor 1110 via the components described herein. In at least one embodiment, an accelerometer 1141, an ambient light sensor (“ALS”) 1142, a compass 1143, and a gyroscope 1144 may be communicatively coupled to the sensor hub 1140. In at least one embodiment, a thermal sensor 1139, a fan 1137, a keyboard 1136, and a touchpad 1130 may be communicatively coupled to the EC 1135. In at least one embodiment, a speaker 1163, headphones 1164, and a microphone (“mic”) 1165 may be communicatively coupled to an audio unit (“audio codec and class D amplifier”) 1162, which may be communicatively coupled to the DSP 1160. In at least one embodiment, audio unit 1162 may include, for example, without limitation, an audio coder / decoder ("codec") and a Class D amplifier. In at least one embodiment, SIM card ("SIM") 1157 may be communicatively coupled to WWAN unit 1156. In at least one embodiment, components such as WLAN unit 1150 and Bluetooth unit 1152, as well as WWAN unit 1156, may be implemented in a Next Generation Form Factor ("NGFF").

[0213] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 11 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0214] In at least one embodiment, one or more systems illustrated in FIG. 11 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 11 are utilized to cause one or more neural networks to be trained using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 11 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 11 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0215] 12 illustrates a computer system 1200 according to at least one embodiment. In at least one embodiment, the computer system 1200 is configured to implement the various processes and methods described throughout this disclosure.

[0216] In at least one embodiment, computer system 1200 includes at least one central processing unit ("CPU") 1202 connected to a communication bus 1210 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1200 includes main memory 1204 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 1204, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 1222 provides an interface with other computing devices and networks for receiving data from other systems and transmitting data to other systems by computer system 1200.

[0217] In at least one embodiment, computer system 1200 includes, without limitation, input device(s) 1208, a parallel processing system 1212, and a display device 1206, which may be implemented using a conventional cathode ray tube ("CRT"), a liquid crystal display ("LCD"), a light emitting diode ("LED") display, a plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 1208, such as a keyboard, a mouse, a touch pad, a microphone, or the like. In at least one embodiment, each of the modules described herein may be located on a single semiconductor platform to form a processing system.

[0218] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 12 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0219] In at least one embodiment, one or more systems illustrated in FIG. 12 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 12 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 12 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 12 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0220] 13 illustrates a computer system 1300 according to at least one embodiment. In at least one embodiment, computer system 1300 may include, without limitation, a computer 1310 and a USB stick 1320. In at least one embodiment, computer 1310 may include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1310 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0221] In at least one embodiment, USB stick 1320 includes, without limitation, a processing unit 1330, a USB interface 1340, and USB interface logic 1350. In at least one embodiment, processing unit 1330 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1330 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1330 comprises an application specific integrated circuit (“ASIC”) optimized to perform any quantity and type of operations related to machine learning. For example, in at least one embodiment, processing unit 1330 is a tensor processing unit (“TPC”) optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing unit 1330 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0222] In at least one embodiment, USB interface 1340 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 1340 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1340 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1350 may include any amount and type of logic that enables processing unit 1330 to interface with a device (e.g., computer 1310) via USB connector 1340.

[0223] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in the system of Figure 13 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0224] In at least one embodiment, one or more systems illustrated in FIG. 13 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 13 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 13 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 13 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0225] FIG. 14A illustrates an exemplary architecture in which multiple GPUs 1410(1)-1410(N) are communicatively coupled to multiple multi-core processors 1405(1)-1405(M) via high-speed links 1440(1)-1440(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1440(1)-1440(N) support communication throughputs of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, the values ​​of which may vary from figure to figure.

[0226] Additionally, in at least one embodiment, two or more of the GPUs 1410 are interconnected via high-speed links 1429(1)-1429(2), which may be implemented using similar or different protocols / links as used for high-speed links 1440(1)-1440(N). Similarly, two or more of the multi-core processors 1405 may be connected via high-speed link 1428, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communications between the various system components shown in FIG. 14A may be achieved using similar protocols / links (e.g., via a common interconnect fabric).

[0227] In one embodiment, each multi-core processor 1405 is communicatively coupled to processor memory 1401(1)-1401(M) via memory interconnect 1426(1)-1426(M), respectively, and each GPU 1410(1)-1410(N) is communicatively coupled to GPU memory 1420(1)-1420(N) via GPU memory interconnect 1450(1)-1450(N), respectively. In at least one embodiment, memory interconnects 1426 and 1450 may utilize similar or different memory access technologies. By way of example, and not limitation, processor memory 1401(1)-1401(M) and GPU memory 1420 may be volatile memory such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memory such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of processor memory 1401 may be volatile memory and other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0228] As described herein, the various multicore processors 1405 and GPUs 1410 may each be physically coupled to specific memories 1401, 1420, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as an "effective address" space) is distributed among various physical memories. For example, processor memories 1401(1) through 1401(M) may each have 64 GB of system memory address space, and GPU memories 1420(1) through 1420(N) may each have 32 GB of system memory address space, resulting in this example in a total of 256 GB of addressable memory when M=2 and N=4. Other values ​​of N and M are possible.

[0229] 14B shows further details of the interconnection between multi-core processor 1407 and graphics acceleration module 1446 according to one example embodiment. In at least one embodiment, graphics acceleration module 1446 may include one or more GPU chips integrated on a line card that is coupled to processor 1407 via high-speed link 1440 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1446 may alternatively be integrated on a package or chip with processor 1407.

[0230] In at least one embodiment, the processor 1407 includes multiple cores 1460A-1460D, each having a translation lookaside buffer (“TLB”) 1461A-1461D and one or more caches 1462A-1462D. In at least one embodiment, the cores 1460A-1460D may include various other components, not shown, for executing instructions and processing data. In at least one embodiment, the caches 1462A-1462D may comprise level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1456 may be included in the caches 1462A-1462D and shared by the set of cores 1460A-1460D. For example, one embodiment of the processor 1407 includes 24 cores, each with its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, the processor 1407 and graphics acceleration module 1446 are coupled to system memory 1414, which may include processor memories 1401(1) through 1401(M) of FIG. 14A.

[0231] In at least one embodiment, coherence is maintained for data and instructions stored in the various caches 1462A-1462D, 1456, and system memory 1414 through inter-core communication via coherence bus 1464. In at least one embodiment, for example, each cache may have associated cache coherence logic / circuitry for communicating via coherence bus 1464 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via coherence bus 1464 to monitor cache accesses.

[0232] In at least one embodiment, proxy circuit 1425 communicatively couples graphics acceleration module 1446 to coherence bus 1464 to enable graphics acceleration module 1446 to participate in cache coherence protocols as a peer of cores 1460A-1460D. In particular, in at least one embodiment, interface 1435 provides a connection to proxy circuit 1425 via high-speed link 1440, and interface 1437 connects graphics acceleration module 1446 to high-speed link 1440.

[0233] In at least one embodiment, the accelerator integrated circuit 1436 provides cache management, memory access, content management, and interrupt management services on behalf of the multiple graphics processing engines 1431(1)-1431(N) of the graphics acceleration module 1446. In at least one embodiment, the graphics processing engines 1431(1)-1431(N) may each comprise a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1431(1)-1431(N) may alternatively comprise different types of graphics processing engines within a GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, graphics acceleration module 1446 may be a GPU having multiple graphics processing engines 1431(1)-1431(N), or the graphics processing engines 1431(1)-1431(N) may be individual GPUs integrated into a common package, line card, or chip.

[0234] In at least one embodiment, accelerator integrated circuitry 1436 includes a memory management unit (MMU) 1439 for performing various memory management functions, such as virtual-to-physical memory translation (also referred to as effective-to-real memory translation), and a memory access protocol for accessing system memory 1414. In at least one embodiment, MMU 1439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, cache 1438 may store commands and data for efficient access by graphics processing engines 1431(1)-1431(N). In at least one embodiment, data stored in cache 1438 and graphics memory 1433(1)-1433(M) is kept coherent with core caches 1462A-1462D, 1456 and system memory 1414, possibly using fetch unit 1444. As noted, this may be accomplished via proxy circuitry 1425 (e.g., sending updates to and receiving updates from cache 1438 regarding modifications / accesses of cache lines in processor caches 1462A-1462D, 1456) on behalf of cache 1438 and memory 1433(1)-1433(M).

[0235] In at least one embodiment, a set of registers 1445 stores context data for threads executed by graphics processing engines 1431(1)-1431(N), and a context management circuit 1448 manages thread contexts. For example, the context management circuit 1448 may perform save and restore operations to save and restore the context of various threads during a context switch (e.g., where a first thread is saved and a second thread is saved so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 1448 may store current register values ​​in a designated area of ​​memory (e.g., identified by a context pointer). Then, when returning to the context, the context management circuit 2248 may restore the register values. In at least one embodiment, the interrupt management circuit 1447 receives and processes interrupts received from system devices.

[0236] In at least one embodiment, virtual / effective addresses from the graphics processing engine 1431 are translated to real / physical addresses in the system memory 1414 by the MMU 1439. In at least one embodiment, the accelerator integration circuit 1436 supports multiple (e.g., four, eight, or sixteen) graphics accelerator modules 1446 and / or other accelerator devices. In at least one embodiment, the graphics accelerator modules 1446 may be dedicated to a single application executing on the processor 1407 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment exists in which the resources of the graphics processing engines 1431(1)-1431(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources may be subdivided into "slices," which are allocated to different VMs and / or applications based on the processing requirements and priorities associated with the VMs and / or applications.

[0237] In at least one embodiment, the accelerator integrated circuitry 1436 acts as a bridge to the system for the graphics acceleration module 1446, providing address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuitry 1436 may provide a virtualization facility for a host processor to manage virtualization, interrupts, and memory management for the graphics processing engines 1431(1)-1431(N).

[0238] In at least one embodiment, the hardware resources of graphics processing engines 1431(1)-1431(N) are explicitly mapped into the real address space seen by host processor 1407, allowing any host processor to directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuitry 1436 is to physically separate graphics processing engines 1431(1)-1431(N) so that they appear to the system as independent units.

[0239] In at least one embodiment, one or more graphics memories 1433(1) through 1433(M) are each coupled to a respective one of the graphics processing engines 1431(1) through 1431(N), where N = M. In at least one embodiment, the graphics memories 1433(1) through 1433(M) store instructions and data being processed by the respective graphics processing engines 1431(1) through 1431(N). In at least one embodiment, the graphics memories 1433(1) through 1433(M) may be volatile memory such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory such as 3D XPoint or Nano-Ram.

[0240] In at least one embodiment, to reduce data traffic over high-speed link 1440, biasing techniques are used to ensure that the data stored in graphics memory 1433(1)-1433(M) is data that will be used most frequently by graphics processing engines 1431(1)-1431(N), and preferably data that is used (at least frequently) by cores 1460A-1460D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and therefore preferably not needed by graphics processing engines 1431(1)-1431(N)) in caches 1462A-1462D, 1456, and system memory 1414.

[0241] 14C shows another exemplary embodiment in which accelerator integration circuitry 1436 is integrated within processor 1407. In at least this embodiment, graphics processing engines 1431(1)-1431(N) communicate directly with accelerator integration circuitry 1436 via high-speed link 1440 (which again may be any form of bus or interface protocol) via interface 1437 and interface 1435. In at least one embodiment, accelerator integration circuitry 1436 may perform operations similar to those described with respect to FIG. 14B, but may potentially operate at a higher throughput given its proximity to coherence bus 1464 and caches 1462A-1462D, 1456. In at least one embodiment, the accelerator integrated circuitry supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuitry 1436 and a programming model controlled by the graphics acceleration module 1446.

[0242] In at least one embodiment, graphics processing engines 1431(1)-1431(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1431(1)-1431(N) to achieve virtualization within a VM / partition.

[0243] In at least one embodiment, graphics processing engines 1431(1)-1431(N) may be shared by multiple VM / application partitions. In at least one embodiment, the sharing model may use a system hypervisor to virtualize graphics processing engines 1431(1)-1431(N) to allow access by each operating system. In at least one embodiment, in a single-partition system without a hypervisor, graphics processing engines 1431(1)-1431(N) are owned by the operating system. In at least one embodiment, the operating system may virtualize graphics processing engines 1431(1)-1431(N) to provide access to each process or application.

[0244] In at least one embodiment, graphics acceleration module 1446 or individual graphics processing engines 1431(1)-1431(N) selects a process element using a process handle. In at least one embodiment, the process element is stored in system memory 1414 and is addressable using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to a host process when registering the host process's context with graphics processing engines 1431(1)-1431(N) (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the low-order 16 bits of the process handle may be the offset of the process element within the process element linked list.

[0245] FIG. 14D illustrates an exemplary accelerator integration slice 1490. In at least one embodiment, a "slice" comprises a designated portion of the processing resources of accelerator integration circuitry 1436. In at least one embodiment, application effective address space 1482 in system memory 1414 stores process element 1483. In at least one embodiment, process element 1483 is stored in response to a GPU call 1481 from an application 1480 executing on processor 1407. In at least one embodiment, process element 1483 contains the process state of the corresponding application 1480. In at least one embodiment, work descriptor (WD) 1484 contained in process element 1483 can be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1484 is a pointer to a job request queue in application effective address space 1482.

[0246] In at least one embodiment, graphics acceleration module 1446 and / or individual graphics processing engines 1431(1)-1431(N) may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process state and sending WD 1484 to graphics acceleration module 1446 to start a job in a virtualized environment.

[0247] In at least one embodiment, the dedicated process programming model is implementation specific, in which a single process owns the graphics acceleration module 1446 or an individual graphics processing engine 1431. In at least one embodiment, if the graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integration circuitry 1436 for the owning partition when the graphics acceleration module 1446 is allocated, and the operating system initializes the accelerator integration circuitry 1436 for the owning process.

[0248] In at least one embodiment, in operation, WD fetch unit 1491 in accelerator integrated slice 1490 fetches the next WD 1484, which contains an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 1446. In at least one embodiment, as shown, data from WD 1484 may be stored in register 1445 and used by MMU 1439, interrupt management circuit 1447, and / or context management circuit 1448. For example, one embodiment of MMU 1439 includes segment / page walk circuitry for accessing segment / page table 1486 within OS virtual address space 1485. In at least one embodiment, interrupt management circuit 1447 may process interrupt events 1492 received from graphics acceleration module 1446. In at least one embodiment, when performing graphics operations, effective addresses 1493 generated by graphics processing engines 1431(1)-1431(N) are translated into real addresses by MMU 1439.

[0249] In at least one embodiment, registers 1445 may be replicated for each graphics processing engine 1431(1)-1431(N) and / or graphics acceleration module 1446 and initialized by a hypervisor or operating system. In at least one embodiment, each of these replicated registers may be included in accelerator integration slice 1490. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. [Table 3]

[0250] Exemplary registers that may be initialized by the operating system are shown in Table 2. [Table 4]

[0251] In at least one embodiment, each WD 1484 is specific to a particular graphics acceleration module 1446 and / or graphics processing engine 1431(1)-1431(N). In at least one embodiment, WD 1484 may contain all the information that graphics processing engine 1431(1)-1431(N) needs to do its work, or may be a pointer to a memory location where an application has set up a command queue for work to be completed.

[0252] 14E shows further details of an exemplary embodiment of the sharing model. This embodiment includes a hypervisor real address space 1498 in which a process element list 1499 is stored. In at least one embodiment, the hypervisor real address space 1498 is accessible through a hypervisor 1496 that virtualizes the graphics acceleration module engine of the operating system 1495.

[0253] In at least one embodiment, a shared programming model allows all or a subset of processes from all or a subset of partitions in a system to use the graphics acceleration module 1446. In at least one embodiment, there are two programming models in which the graphics acceleration module 1446 is shared by multiple processes and partitions: timeslice shared and graphics-directed shared.

[0254] In at least one embodiment, in this model, system hypervisor 1496 owns graphics acceleration module 1446 and makes its functionality available to all operating systems 1495. In at least one embodiment, in order for graphics acceleration module 1446 to support virtualization by system hypervisor 1496, graphics acceleration module 1446 may conform to certain requirements, such as: (1) application job requests must be autonomous (i.e., no state needs to be maintained between jobs) or graphics acceleration module 1446 must provide a mechanism for saving and restoring context; (2) application job requests must be guaranteed by graphics acceleration module 1446 to complete in a specified amount of time, including any translation errors, or graphics acceleration module 1446 must provide the ability to preempt job processing; and (3) graphics acceleration module 1446 must ensure fairness between processes when operating in a specified shared programming model.

[0255] In at least one embodiment, application 1480 must make a system call to operating system 1495 with a graphics acceleration module type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the acceleration function targeted by the system call. In at least one embodiment, the graphics acceleration module type may be a system-specific value. In at least one embodiment, the WD is formatted specifically for graphics acceleration module 1446 and may be in the form of graphics acceleration module 1446 commands, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure for describing the work to be performed by graphics acceleration module 1446.

[0256] In at least one embodiment, the AMR value is the AMR state to use for the current process. In at least one embodiment, the value passed to the operating system is the same as the application setting the AMR. In at least one embodiment, if an embodiment of the accelerator integrated circuit 1436 (not shown) and the graphics acceleration module 1446 does not support a User Authorization Mask Override Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR to the hypervisor call. In at least one embodiment, the hypervisor 1496 may optionally apply the current Authorization Mask Override Register (AMOR) value before placing the AMR in the process element 1483. In at least one embodiment, the CSRP is one of the registers 1445 that contains the effective address of an area in the application's effective address space 1482 for the graphics acceleration module 1446 to save and restore context state. In at least one embodiment, this pointer is optional if no state needs to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be pinned system memory.

[0257] Upon receiving the system call, the operating system 1495 may verify that the application 1480 is registered and authorized to use the graphics acceleration module 1446. In at least one embodiment, the operating system 1495 then calls the hypervisor 1496 with the information shown in Table 3. [Table 5]

[0258] In at least one embodiment, upon receiving the hypervisor call, the hypervisor 1496 verifies that the operating system 1495 is registered and authorized to use the graphics acceleration module 1446. In at least one embodiment, the hypervisor 1496 then places the process element 1483 into a process element linked list of the corresponding graphics acceleration module 1446 type. In at least one embodiment, the process element may include the information shown in Table 4. [Table 6]

[0259] In at least one embodiment, the hypervisor initializes registers 1445 of multiple accelerator integrated slices 1490.

[0260] As shown in FIG. 14F, at least one embodiment uses unified memory that is addressable via a common virtual memory address space used to access physical processor memories 1401(1)-1401(N) and GPU memories 1420(1)-1420(N). In this embodiment, operations performed on GPUs 1410(1)-1410(N) utilize the same virtual / effective memory address space as those used to access processor memories 1401(1)-1401(M), and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1401(1), a second portion is allocated to second processor memory 1401(N), a third portion is allocated to GPU memory 1420(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of the processor memory 1401 and GPU memory 1420, allowing either processor or GPU to access either physical memory, with virtual addresses mapped to physical memory.

[0261] In at least one embodiment, bias / coherence management circuits 1494A-1494E in one or more of MMUs 1439A-1439E ensure cache coherence between caches of one or more host processors (e.g., 1405) and caches of GPU 1410 and implement biasing techniques to indicate physical memory in which certain types of data should be stored. In at least one embodiment, multiple instances of bias / coherence management circuits 1494A-1494E are shown in FIG. 14F, although bias / coherence circuits may be implemented within the MMUs of one or more host processors 1405 and / or within accelerator integration circuit 1436.

[0262] One embodiment enables GPU memory 1420 to be mapped as part of system memory and accessible using shared virtual memory (SVM) techniques, but without the performance penalty associated with full system cache coherence. In at least one embodiment, having GPU memory 1420 accessible as system memory without cumbersome cache coherence overhead provides a beneficial operating environment for GPU offload. In at least one embodiment, this configuration enables host processor 1405 software to set up operands and access computation results without the overhead of traditional I / O DMA data copies. In at least one embodiment, such traditional copies require driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, being able to access GPU memory 1420 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the presence of significant streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1410. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can be useful in determining the effectiveness of GPU offloading.

[0263] In at least one embodiment, the selection of the GPU bias and the host processor bias is determined by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granular structure containing one or two bits per GPU-attached memory page (e.g., controlled at memory page granularity). In at least one embodiment, the bias table may be implemented in a stolen memory range of one or more GPU memories 1420, with or without a bias cache in the GPU 1410 (e.g., for caching frequently / recently used entries of the bias table). Alternatively, in at least one embodiment, the bias table may be maintained entirely within the GPU.

[0264] In at least one embodiment, a bias table entry associated with each access to GPU-biased memory 1420 is accessed prior to the actual access to the GPU memory, resulting in the following actions: In at least one embodiment, a local request from the GPU 1410 to find its page in the GPU bias is forwarded directly to the corresponding GPU memory 1420. In at least one embodiment, a local request from the GPU to find its page in the host bias is forwarded to the processor 1405 (e.g., via a high-speed link as described herein). In at least one embodiment, a request from the processor 1405 to find the requested page in the host processor bias completes the request similar to a normal memory read. Alternatively, a request directed to a GPU-biased page may be forwarded to the GPU 1410. In at least one embodiment, the GPU may then migrate the page to the host processor bias if it is not currently using the page. In at least one embodiment, the bias state of a page can be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, simply a hardware-based mechanism.

[0265] In at least one embodiment, one mechanism for changing the bias state utilizes an API call (e.g., OpenCL) that calls the GPU's device driver, which sends a message (or queues a command descriptor) to the GPU to change the bias state and, for some transitions, directs the GPU to perform a cache flushing operation in the host. In at least one embodiment, a cache flushing operation is used for transitions from host processor 1405 bias to GPU bias, but not for transitions in the opposite direction.

[0266] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages non-cacheable by the host processor 1405. In at least one embodiment, to access these pages, the processor 1405 may request access from the GPU 1410, and the GPU 1410 may or may not immediately grant the access. Thus, in at least one embodiment, to reduce communication between the processor 1405 and the GPU 1410, it is beneficial for GPU-biased pages to be requested by the GPU but not by the host processor 1405, and vice versa.

[0267] To implement one or more embodiments, a hardware structure 615 is used, details regarding the hardware structure 615 may be provided herein in conjunction with Figures 6A and / or 6B.

[0268] In at least one embodiment, one or more systems illustrated in Figures 14A-14F are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in Figures 14A-14F are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in Figures 14A-14F are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in Figures 14A-14F are utilized to implement one or more systems and / or processes, such as those described in connection with Figures 1-5.

[0269] 15 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0270] 15 is a block diagram illustrating an exemplary system-on-chip integrated circuit 1500 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1500 includes one or more application processors 1505 (e.g., a CPU), at least one graphics processor 1510, and may further include an image processor 1515 and / or a video processor 1520, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1500 includes a USB controller 1525, a UART controller 1530, an SPI / SDIO controller 1535, and an I / O controller 1540. 22S / I 2 The integrated circuit 1500 may include peripheral or bus logic including a HDMI™ controller 1540. In at least one embodiment, the integrated circuit 1500 may include a display device 1545 coupled to one or more of a high-definition multimedia interface (HDMI™) controller 1550 and a mobile industry processor interface (MIPI) display interface 1555. In at least one embodiment, storage may be provided by a flash memory subsystem 1560 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1565 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 1570.

[0271] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with FIGURES 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 1500 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0272] In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to cause one or more neural networks to be trained using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 15 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0273] 16A-16B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0274] 16A-16B are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein. FIG. 16A illustrates an exemplary graphics processor 1610 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. FIG. 16B illustrates a further exemplary graphics processor 1640 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, the graphics processor 1610 of FIG. 16A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1640 of FIG. 16B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 1610, 1640 can be a variation of the graphics processor 1510 of FIG. 15.

[0275] In at least one embodiment, graphics processor 1610 includes a vertex processor 1605 and one or more fragment processors 1615A-1615N (e.g., 1615A, 1615B, 1615C, 1615D-1615N-1, and 1615N). In at least one embodiment, graphics processor 1610 can execute different shader programs through separate logic, such that vertex processor 1605 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1615A-1615N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 1605 executes the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, fragment processors 1615A-1615N use the primitive and vertex data generated by vertex processor 1605 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processors 1615A-1615N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0276] In at least one embodiment, graphics processor 1610 further includes one or more memory management units (MMUs) 1620A-1620B, caches 1625A-1625B, and circuit interconnects 1630A-1630B. In at least one embodiment, one or more MMUs 1620A-1620B provide virtual-to-physical address mapping for graphics processor 1610, including vertex processor 1605 and / or fragment processors 1615A-1615N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 1625A-1625B. In at least one embodiment, one or more MMUs 1620A-1620B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1505, image processor 1515, and / or video processor 1520 of Figure 15, allowing each processor 1505-1520 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1630A-1630B enable graphics processor 1610 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0277] In at least one embodiment, graphics processor 1640 includes one or more shader cores 1655A-1655N (e.g., 1655A, 1655B, 1655C, 1655D, 1655E, 1655F-1655N-1, and 1655N) as shown in FIG. 16B, which provide a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1640 includes an inter-core task manager 1645 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1655A-1655N, and a tiling unit 1658 for accelerating tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0278] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with FIGURES 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuits 16A and / or 16B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0279] In at least one embodiment, one or more systems shown in Figures 16A-16B are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems shown in Figures 16A-16B are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems shown in Figures 16A-16B are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems shown in Figures 16A-16B are utilized to implement one or more systems and / or processes, such as those described in connection with Figures 1-5.

[0280] 17A-17B illustrate further exemplary graphics processor logic according to embodiments described herein. FIG. 17A illustrates a graphics core 1700, which, in at least one embodiment, may be included in graphics processor 1510 of FIG. 15, or, in at least one embodiment, may be integrated shader cores 1655A-1655N, as in FIG. 16B. FIG. 17B illustrates a highly parallel general-purpose graphics processing unit ("GPGPU") 1730 suitable for incorporation into a multi-chip module in at least one embodiment.

[0281] In at least one embodiment, graphics core 1700 includes a shared instruction cache 1702, a texture unit 1718, and a cache / shared memory 1720, which are common to execution resources within graphics core 1700. In at least one embodiment, graphics core 1700 may include multiple slices 1701A-1701N, or partitions per core, and a graphics processor may include multiple instances of graphics core 1700. In at least one embodiment, slices 1701A-1701N may include supporting logic, including local instruction caches 1704A-1704N, thread schedulers 1706A-1706N, thread dispatchers 1708A-1708N, and sets of registers 1710A-1710N. In at least one embodiment, slices 1701A-1701N may include a set of additional functional units (AFUs 1712A-1712N), floating point units (FPUs 1714A-1714N), integer arithmetic logic units (ALUs 1716A-1716N), address calculation units (ACUs 1713A-1713N), double precision floating point units (DPFPUs 1715A-1715N), and matrix processing units (MPUs 1717A-1717N).

[0282] In at least one embodiment, the FPUs 1714A-1714N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 1715A-1715N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 1716A-1716N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 1717A-1717N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In at least one embodiment, the MPUs 1717A-1717N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support general matrix-matrix multiplication (GEMM) acceleration. In at least one embodiment, AFUs 1712A-1712N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0283] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with FIGURES 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in graphics core 1700 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0284] FIG. 17B illustrates a general-purpose processing unit (GPGPU) 1730, which, in at least one embodiment, can be configured to enable highly parallel computational operations by an array of graphics processing units. In at least one embodiment, the GPGPU 1730 can be directly linked to other instances of the GPGPU 1730 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 1730 includes a host interface 1732 for enabling connection to a host processor. In at least one embodiment, the host interface 1732 is a PCI Express interface. In at least one embodiment, the host interface 1732 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 1730 receives commands from the host processor and, using a global scheduler 1734, distributes execution threads associated with those commands to a set of compute clusters 1736A-1736H. In at least one embodiment, the compute clusters 1736A-1736H share a cache memory 1738. In at least one embodiment, the cache memory 1738 can act as a higher level cache for the cache memories within the compute clusters 1736A-1736H.

[0285] In at least one embodiment, GPGPU 1730 includes memory 1744A-1744B coupled to compute clusters 1736A-1736H via a set of memory controllers 1742A-1742B. In at least one embodiment, memory 1744A-1744B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0286] In at least one embodiment, compute clusters 1736A-1736H each include a set of graphics cores, such as graphics core 1700 of FIG. 17A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 1736A-1736H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0287] In at least one embodiment, multiple instances of GPGPU 1730 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 1736A-1736H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 1730 communicate through host interface 1732. In at least one embodiment, GPGPU 1730 includes I / O hub 1739, which couples GPGPU 1730 to GPU link 1740, which enables direct connection to other instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 1730. In at least one embodiment, GPU link 1740 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1730 are located in separate data processing systems and communicate via a network device accessible via host interface 1732. In at least one embodiment, GPU link 1740 can be configured to allow connection to a host processor in addition to, or instead of, host interface 1732.

[0288] In at least one embodiment, the GPGPU 1730 can be configured to train a neural network. In at least one embodiment, the GPGPU 1730 can be used within an inference platform. In at least one embodiment, when the GPGPU 1730 is used for inference, the GPGPU 1730 may include fewer compute clusters 1736A-1736H than when the GPGPU 1730 is used to train a neural network. In at least one embodiment, the memory technology associated with memories 1744A-1744B may be different between the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1730 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0289] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, the inference and / or training logic 615 may be used in the GPGPU 1730 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0290] In at least one embodiment, one or more systems shown in Figures 17A-17B are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems shown in Figures 17A-17B are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems shown in Figures 17A-17B are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems shown in Figures 17A-17B are utilized to implement one or more systems and / or processes, such as those described in connection with Figures 1-5.

[0291] 18 is a block diagram illustrating a computing system 1800 according to at least one embodiment. In at least one embodiment, computing system 1800 includes a processing subsystem 1801 having one or more processors 1802 and system memory 1804 that communicate via an interconnection path that may include a memory hub 1805. In at least one embodiment, memory hub 1805 may be a separate component within a chipset component or may be integrated within one or more processors 1802. In at least one embodiment, memory hub 1805 is coupled to an I / O subsystem 1811 via communication link 1806. In at least one embodiment, I / O subsystem 1811 includes an I / O hub 1807 that can enable computing system 1800 to receive input from one or more input devices 1808. In at least one embodiment, I / O hub 1807 can enable a display controller, which may be included in one or more processors 1802 and provide output to one or more display devices 1810A. In at least one embodiment, the one or more display devices 1810A coupled to I / O hub 1807 can include local, internal, or embedded display devices.

[0292] In at least one embodiment, processing subsystem 1801 includes one or more parallel processors 1812 coupled to memory hub 1805 via a bus or other communication link 1813. In at least one embodiment, communication link 1813 may use one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 1812 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of the parallel processors 1812 form a graphics processing subsystem that can output pixels to one of one or more display devices 1810A coupled via I / O hub 1807. In at least one embodiment, parallel processor 1812 also includes a display controller and display interface (not shown) that allows direct connection to one or more display devices 1810B.

[0293] In at least one embodiment, a system storage unit 1814 may be connected to an I / O hub 1807 to provide a storage mechanism for the computing system 1800. In at least one embodiment, an I / O switch 1816 may be used to provide an interface mechanism to enable communication between the I / O hub 1807 and other components, such as a network adapter 1818 and / or a wireless network adapter 1819, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 1820. In at least one embodiment, the network adapter 1818 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1819 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0294] In at least one embodiment, computing system 1800 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may be connected to I / O hub 1807. In at least one embodiment, communication paths interconnecting the various components of FIG. 18 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0295] In at least one embodiment, parallel processor 1812 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, parallel processor 1812 incorporates circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 1800 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor 1812, memory hub 1805, processor 1802, and I / O hub 1807 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 1800 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1800 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0296] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, the inference and / or training logic 615 may be used in the system of Figure 1800 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0297] In at least one embodiment, one or more systems illustrated in FIG. 18 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 18 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 18 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 18 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0298] Processor 19A illustrates a parallel processor 1900 according to at least one embodiment. In at least one embodiment, various components of parallel processor 1900 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 1900 is a variation of one or more parallel processors 1812 shown in FIG. 18 according to an example embodiment.

[0299] In at least one embodiment, parallel processor 1900 includes parallel processing units 1902. In at least one embodiment, parallel processing units 1902 include I / O units 1904 that enable communication with other devices, including other instances of parallel processing units 1902. In at least one embodiment, I / O units 1904 may be directly connected to other devices. In at least one embodiment, I / O units 1904 are connected to other devices through the use of a hub or switch interface, such as memory hub 1905. In at least one embodiment, the connection between memory hub 1905 and I / O units 1904 forms communication link 1913. In at least one embodiment, I / O units 1904 are connected to host interface 1906 and memory crossbar 1916, where host interface 1906 receives commands directed to the execution of processing operations and memory crossbar 1916 receives commands directed to the execution of memory operations.

[0300] In at least one embodiment, when host interface 1906 receives command buffers via I / O unit 1904, host interface 1906 can direct work operations to front end 1908 to execute these commands. In at least one embodiment, front end 1908 is coupled to scheduler 1910, which is configured to distribute commands or other work items to processing cluster array 1912. In at least one embodiment, scheduler 1910 ensures that processing cluster array 1912 is properly configured and in a valid state before tasks are distributed to clusters in processing cluster array 1912. In at least one embodiment, scheduler 1910 is implemented via firmware logic running on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 1910 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularity, enabling rapid preemption and context switching of threads executing in processing array 1912. In at least one embodiment, host software can initiate scheduling workloads through one of multiple graphics processing paths in processing cluster array 1912. In at least one embodiment, the workload can then be automatically distributed across processing cluster array clusters 1912 by scheduler 1910 logic in a microcontroller that includes scheduler 1910.

[0301] In at least one embodiment, processing cluster array 1912 can include up to “N” processing clusters (e.g., cluster 1914A, cluster 1914B through cluster 1914N), where “N” represents a positive integer (which may be a different integer “N” than used in other figures). In at least one embodiment, each cluster 1914A through 1914N of processing cluster array 1912 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1910 can allocate work to clusters 1914A through 1914N of processing cluster array 1912 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1910 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 1912. In at least one embodiment, different clusters 1914A-1914N of processing cluster array 1912 may be allocated to process different types of programs or perform different types of calculations.

[0302] In at least one embodiment, processing cluster array 1912 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1912 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 1912 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0303] In at least one embodiment, the processing cluster array 1912 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1912 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1912 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1902 may transfer data from system memory via the I / O unit 1904 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1922) during processing and then written back to system memory.

[0304] In at least one embodiment, when graphics processing is performed using parallel processing unit 1902, scheduler 1910 may be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 1914A-1914N of processing cluster array 1912. In at least one embodiment, portions of processing cluster array 1912 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 1914A-1914N may be stored in a buffer so that the intermediate data can be transmitted between clusters 1914A-1914N for further processing.

[0305] In at least one embodiment, the processing cluster array 1912 can receive processing tasks to be performed via a scheduler 1910, which receives commands defining the processing tasks from the front end 1908. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 1910 can be configured to fetch the index corresponding to the task or can receive the index from the front end 1908. In at least one embodiment, the front end 1908 can be configured to ensure that the processing cluster array 1912 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0306] In at least one embodiment, each of one or more instances of parallel processing unit 1902 can be coupled to parallel processor memory 1922. In at least one embodiment, parallel processor memory 1922 can be accessed via memory crossbar 1916, which can receive memory requests from processing cluster array 1912 as well as I / O unit 1904. In at least one embodiment, memory crossbar 1916 can access parallel processor memory 1922 via memory interface 1918. In at least one embodiment, memory interface 1918 can include multiple partition units (e.g., partition unit 1920A, partition unit 1920B through partition unit 1920N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 1922. In at least one embodiment, the number of partition units 1920A-1920N is configured to be equal to the number of memory units, such that a first partition unit 1920A has a corresponding first memory unit 1924A, a second partition unit 1920B has a corresponding memory unit 1924B, and an Nth partition unit 1920N has a corresponding Nth memory unit 1924N. In at least one embodiment, the number of partition units 1920A-1920N does not have to be equal to the number of memory units.

[0307] In at least one embodiment, memory units 1924A-1924N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1924A-1924N may also include 3D stacked memory, including, but not limited to, high bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of parallel processor memory 1922, render targets, such as frame buffers or texture maps, may be stored across memory units 1924A-1924N, allowing partition units 1920A-1920N to write portions of each render target in parallel. In at least one embodiment, local instances of parallel processor memory 1922 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0308] In at least one embodiment, any one of the clusters 1914A-1914N of the processing cluster array 1912 can process data that is to be written to any one of the memory units 1924A-1924N in the parallel processor memory 1922. In at least one embodiment, the memory crossbar 1916 can be configured to forward the output of each cluster 1914A-1914N to any partition unit 1920A-1920N or to another cluster 1914A-1914N that can perform further processing operations on the output. In at least one embodiment, each cluster 1914A-1914N can communicate with a memory interface 1918 through the memory crossbar 1916 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1916 has connections to memory interface 1918 for communicating with I / O unit 1904, as well as connections to local instances of parallel processor memory 1922, allowing processing units in different processing clusters 1914A-1914N to communicate with system memory or other memory not local to parallel processing unit 1902. In at least one embodiment, memory crossbar 1916 can use virtual channels to separate traffic streams between clusters 1914A-1914N and partition units 1920A-1920N.

[0309] In at least one embodiment, multiple instances of parallel processing unit 1902 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1902 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 1902 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 1902 or parallel processor 1900 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0310] FIG. 19B is a block diagram of a partition unit 1920 according to at least one embodiment. In at least one embodiment, partition unit 1920 is an instance of one of partition units 1920A-1920N of FIG. 19A. In at least one embodiment, partition unit 1920 includes an L2 cache 1921, a frame buffer interface 1925, and a raster operations unit (ROP) 1926. In at least one embodiment, L2 cache 1921 is a read / write cache configured to execute load and store operations received from memory crossbar 1916 and ROP 1926. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 1921 to frame buffer interface 1925 for processing. In at least one embodiment, updates are also sent to the frame buffer via frame buffer interface 1925 for processing. In at least one embodiment, frame buffer interface 1925 interfaces with one of the memory units of a parallel processor memory, such as memory units 1924A-1924N (eg, in parallel processor memory 1922) of FIG.

[0311] In at least one embodiment, ROP1926 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, ROP1926 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP1926 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a number of compression algorithms. In at least one embodiment, the type of compression performed by ROP1926 may be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0312] In at least one embodiment, ROP 1926 is included within each processing cluster (e.g., clusters 1914A-1914N of FIG. 19A ) rather than within partition unit 1920. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 1916. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 1810 of FIG. 18 , may be routed for further processing by processor 1802, or may be routed for further processing by one of the processing entities in parallel processor 1900 of FIG. 19A .

[0313] FIG. 19C is a block diagram of a processing cluster 1914 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 1914A-1914N of FIG. 19A. In at least one embodiment, processing cluster 1914 may be configured to execute multiple threads in parallel, where a "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0314] In at least one embodiment, the operation of the processing cluster 1914 may be controlled via a pipeline manager 1932, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1932 receives instructions from the scheduler 1910 of FIG. 19A and manages the execution of those instructions via the graphics multiprocessor 1934 and / or the texture unit 1936. In at least one embodiment, the graphics multiprocessor 1934 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 1914. In at least one embodiment, one or more instances of the graphics multiprocessor 1934 may be included within the processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 may process data, and a data crossbar 1940 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1932 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed via the data crossbar 1940.

[0315] In at least one embodiment, each graphics multiprocessor 1934 in a processing cluster 1914 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0316] In at least one embodiment, instructions sent to a processing cluster 1914 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, the thread groups execute a common program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 1934. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 1934. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in the graphics multiprocessor 1934. In at least one embodiment, if a thread group includes more threads than the number of processing engines in the graphics multiprocessor 1934, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on the graphics multiprocessor 1934.

[0317] In at least one embodiment, the graphics multiprocessor 1934 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1934 can forgo the internal cache and use cache memory (e.g., L1 cache 1948) within the processing cluster 1914. In at least one embodiment, each graphics multiprocessor 1934 can also access an L2 cache within a partition unit (e.g., partition units 1920A-1920N in FIG. 19A ), which may be shared among all processing clusters 1914 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1934 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 1902 may be used as global memory. In at least one embodiment, processing cluster 1914 may include multiple instances of graphics multiprocessor 1934 and share common instructions and data, which may be stored in L1 cache 1948.

[0318] In at least one embodiment, each processing cluster 1914 may include an MMU 1945 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1945 may reside within memory interface 1918 of FIG. 19A . In at least one embodiment, MMU 1945 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses of tiles and optionally cache line indexes. In at least one embodiment, MMU 1945 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 1934 or L1 1948 cache, or processing cluster 1914. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0319] In at least one embodiment, processing cluster 1914 may be configured such that each graphics multiprocessor 1934 is coupled to a texture unit 1936 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 1934 and, as needed, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1934 outputs processed tasks to data crossbar 1940 to provide the processed tasks to another processing cluster 1914 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1916. In at least one embodiment, a pre-ROP 1942 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1934 and direct the data to the ROP units, which may be located within partition units (e.g., partition units 1920A-1920N in FIG. 19A ) as described herein. In at least one embodiment, the pre-ROP 1942 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0320] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with FIGURES 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in graphics processing cluster 1914 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0321] 19D illustrates a graphics multiprocessor 1934 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1934 couples with a pipeline manager 1932 of a processing cluster 1914. In at least one embodiment, the graphics multiprocessor 1934 has an execution pipeline including, but not limited to, an instruction cache 1952, an instruction unit 1954, an address mapping unit 1956, a register file 1958, one or more general-purpose graphics processing unit (GPGPU) cores 1962, and one or more load / store units 1966. In at least one embodiment, the GPGPU cores 1962 and the load / store units 1966 are coupled to a cache memory 1972 and a shared memory 1970 via a memory and cache interconnect 1968.

[0322] In at least one embodiment, instruction cache 1952 receives a stream of instructions to execute from pipeline manager 1932. In at least one embodiment, instructions are cached in instruction cache 1952 and dispatched for execution by instruction unit 1954. In at least one embodiment, instruction unit 1954 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group assigned to a different execution unit within GPGPU core 1962. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 1956 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 1966.

[0323] In at least one embodiment, register file 1958 provides a set of registers to the functional units of graphics multiprocessor 1934. In at least one embodiment, register file 1958 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU core 1962, load / store unit 1966) of graphics multiprocessor 1934. In at least one embodiment, register file 1958 is partitioned among each of the functional units, such that each functional unit is allocated a dedicated portion of register file 1958. In at least one embodiment, register file 1958 is partitioned among the different warps being executed by graphics multiprocessor 1934.

[0324] In at least one embodiment, GPGPU cores 1962 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for graphics multiprocessor 1934. In at least one embodiment, GPGPU cores 1962 may have similar or different architectures. In at least one embodiment, a first portion of GPGPU core 1962 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may perform IEEE 754-2008 standard floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, graphics multiprocessor 1934 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangular copy or pixel-blending operations. In at least one embodiment, one or more of GPGPU cores 1962 may also include fixed or special-function logic.

[0325] In at least one embodiment, GPGPU core 1962 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, GPGPU core 1962 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can execute in parallel via a single SIMD8 logical unit.

[0326] In at least one embodiment, memory and cache interconnect 1968 is an interconnect network connecting each functional unit of graphics multiprocessor 1934 to register file 1958 and shared memory 1970. In at least one embodiment, memory and cache interconnect 1968 is a crossbar interconnect that allows load / store unit 1966 to perform load and store operations between shared memory 1970 and register file 1958. In at least one embodiment, register file 1958 can operate at the same frequency as GPGPU cores 1962, and therefore data transfers between GPGPU cores 1962 and register file 1958 can have very low latency. In at least one embodiment, shared memory 1970 can be used to enable communication between threads executing in functional units within graphics multiprocessor 1934. In at least one embodiment, cache memory 1972 can be used, for example, as a data cache to cache texture data communicated between the functional units and texture unit 1936. In at least one embodiment, shared memory 1970 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 1962 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 1972.

[0327] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into a package or chip as a core or may be communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. Regardless of how the GPU is connected, in at least one embodiment, the processor core may allocate work to such GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0328] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with FIGURES 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in graphics multiprocessor 1934 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0329] In at least one embodiment, one or more systems illustrated in Figures 19A-19D are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in Figures 19A-19D are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in Figures 19A-19D are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in Figures 19A-19D are utilized to implement one or more systems and / or processes, such as those described in connection with Figures 1-5.

[0330] FIG. 20 illustrates a multi-GPU computing system 2000, according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2000 may include a processor 2002 coupled to multiple general-purpose graphics processing units (GPGPUs) 2006A-D via a host interface switch 2004. In at least one embodiment, the host interface switch 2004 is a PCI Express switch device that couples the processor 2002 to a PCI Express bus, via which the processor 2002 can communicate with the GPGPUs 2006A-D. In at least one embodiment, the GPGPUs 2006A-D can be interconnected via a set of high-speed point-to-point GPU-to-GPU links 2016. In at least one embodiment, the GPU-to-GPU links 2016 are connected to each of the GPGPUs 2006A-D via dedicated GPU links. In at least one embodiment, the P2P GPU link 2016 allows direct communication between each of the GPGPUs 2006A-D without requiring communication via the host interface bus 2004 to which the processor 2002 is connected. In at least one embodiment, when there is GPU-to-GPU traffic directed to the P2P GPU link 2016, the host interface bus 2004 remains available to allow access to system memory or to communicate with other instances of the multi-GPU computing system 2000, for example, via one or more network devices. In at least one embodiment, the GPGPUs 2006A-D are connected to the processor 2002 via the host interface switch 2004, and in at least one embodiment, the processor 2002 includes direct support for the P2P GPU link 2016 and can be directly connected to the GPGPUs 2006A-D.

[0331] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, the inference and / or training logic 615 may be used in the multi-GPU computing system 2000 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0332] In at least one embodiment, one or more systems illustrated in FIG. 20 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 20 are utilized to train one or more neural networks using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 20 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 20 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0333] 21 is a block diagram of a graphics processor 2100 according to at least one embodiment. In at least one embodiment, graphics processor 2100 includes a ring interconnect 2102, a pipeline front end 2104, a media engine 2137, and graphics cores 2180A-2180N. In at least one embodiment, ring interconnect 2102 couples graphics processor 2100 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2100 is one of multiple processors integrated within a multi-core processing system.

[0334] In at least one embodiment, graphics processor 2100 receives batches of commands via ring interconnect 2102. In at least one embodiment, the incoming commands are interpreted by command streamer 2103 of pipeline front end 2104. In at least one embodiment, graphics processor 2100 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2180A-2180N. In at least one embodiment, for 3D geometry processing commands, command streamer 2103 supplies the commands to geometry pipeline 2136. In at least one embodiment, for at least some media processing commands, command streamer 2103 supplies the commands to video front end 2134, which is coupled to media engine 2137. In at least one embodiment, the media engine 2137 includes a Video Quality Engine (VQE) 2130 for video and image post-processing and a Multi-Format Encode / Decode (MFX) 2133 engine that provides hardware-accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2136 and the media engine 2137 each spawn execution threads for thread execution resources provided by at least one graphics core 2180.

[0335] In at least one embodiment, graphics processor 2100 includes scalable thread execution resources characterized by graphics cores 2180A-2180N (which may be modular and sometimes referred to as core slices), with each modular core 2180A-2180N having multiple sub-cores 2150A-2150N, 2160A-2160N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 2100 can have any number of graphics cores 2180A. In at least one embodiment, graphics processor 2100 includes a graphics core 2180A having at least a first sub-core 2150A and a second sub-core 2160A. In at least one embodiment, graphics processor 2100 is a low-power processor having a single sub-core (e.g., 2150A). In at least one embodiment, graphics processor 2100 includes multiple graphics cores 2180A-2180N, each including a set of first sub-cores 2150A-2150N and a set of second sub-cores 2160A-2160N. In at least one embodiment, each of the first sub-cores 2150A-2150N includes at least a first set of execution units 2152A-2152N and media / texture samplers 2154A-2154N. In at least one embodiment, each of the second sub-cores 2160A-2160N includes at least a second set of execution units 2162A-2162N and samplers 2164A-2164N. In at least one embodiment, each sub-core 2150A-2150N, 2160A-2160N shares a set of shared resources 2170A-2170N. In at least one embodiment, the shared resources include shared cache memory and pixel operating logic.

[0336] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 615 are provided herein in conjunction with Figures 6A and / or 6B. In at least one embodiment, inference and / or training logic 615 may be used in graphics processor 2100 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0337] In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to implement a system for curating a scene. In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to cause one or more neural networks to be trained using training data that is automatically selected based at least in part on metadata associated with the training data. In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to generate output data using one or more neural networks based at least in part on the automatically selected training data, such that the output data has one or more attributes. In at least one embodiment, one or more systems illustrated in FIG. 21 are utilized to implement one or more systems and / or processes, such as those described in connection with FIGS. 1-5.

[0338] FIG. 22 is a block diagram illustrating the micro-architecture of a processor 2200 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2200 may execute instructions, including x86 instructions, ARM instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2200 may include registers for storing packed data, such as 64-bit wide MMX™ registers in a microprocessor enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 2200 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0339] In at least one embodiment, processor 2200 includes an in-order front end (“front end”) 2201 that fetches instructions to be executed and prepares them for later use in the processor pipeline. In at least one embodiment, front end 2201 may include several units. In at least one embodiment, instruction prefetcher 2226 fetches instructions from memory and provides them to instruction decoder 2228, which decodes or interp...

Claims

1. one or more circuits for training one or more neural networks using training data, the one or more circuits automatically selecting the training data based at least in part on metadata associated with the training data; the one or more circuits further comprising: Obtain multiple training data sets, processing the plurality of training data into a set of groups based at least in part on the metadata; automatically selecting the training data from the plurality of training data based at least in part on the set of groups; the one or more circuits for selecting the training data further automatically select the training data using one or more equation solvers to calculate one or more numbers of assets for one or more subsets of the training data. Processor.

2. The processor of claim 1 , wherein a first group of the set of groups corresponds to a first combination of metadata values.

3. the one or more circuits further comprising: obtaining one or more labels corresponding to the training data; training the one or more neural networks using at least the one or more labels and the training data; The processor of claim 1 .

4. The processor of claim 1 , wherein the training data comprises one or more images captured from one or more vehicles.

5. The processor of claim 1 , wherein the metadata indicates one or more operational design domain (ODD) values.

6. one or more computers having one or more processors for training one or more neural networks using training data, the one or more processors automatically selecting the training data to cause the one or more neural networks to generate output data having one or more attributes; the one or more processors further comprising: obtaining a set of training data and associated metadata; analyzing the set of training data to calculate one or more subsets of training data based at least in part on the associated metadata; using one or more equation solvers to calculate one or more numbers of assets for one or more subsets of the training data; system.

7. 7. The system of claim 6, wherein the one or more processors are further configured to automatically select the training data from one or more subsets of the training data based at least in part on one or more numbers of the assets.

8. The system of claim 6 , wherein the one or more numbers of the assets are based at least in part on one or more target percentages.

9. The system of claim 6 , wherein the training data comprises one or more images captured from one or more medical devices.

10. The system of claim 6 , wherein the output data comprises one or more classifications of one or more objects depicted in one or more images.

11. The system of claim 10 , wherein the one or more attributes include one or more accuracy values ​​corresponding to the one or more classifications.

12. One or more circuits that use one or more neural networks to generate output data based at least in part on training data, the one or more circuits automatically selecting the training data based at least in part on metadata associated with the training data. Equipped with the one or more circuits further automatically select the training data using one or more equation solvers to calculate one or more numbers of assets for one or more subsets of the training data, the one or more equation solvers being based at least in part on a linear formulation; Processor.

13. the one or more circuits further comprising: obtaining one or more images depicting one or more objects; using the one or more neural networks to generate the output data based on the one or more images; The processor of claim 12.

14. the one or more neural networks include one or more object detection neural networks; The processor of claim 13 , wherein the output data comprises data indicative of one or more locations of the one or more objects.

15. The processor of claim 12 , wherein the metadata indicates one or more conditions of the training data.

16. The processor of claim 12 , wherein the training data includes sensor data.

17. one or more computers having one or more processors that use one or more neural networks to generate output data based at least in part on training data, the one or more processors automatically selecting the training data such that the output data has one or more attributes; the one or more processors further automatically select the training data using one or more solvers to calculate one or more numbers of assets for one or more subsets of the training data, the one or more solvers being based at least in part on a quadratic formulation; system.

18. 20. The system of claim 17, wherein the one or more processors further use the one or more neural networks to generate the output data based at least in part on a set of images.

19. 20. The system of claim 17, wherein the output data comprises one or more results of the one or more neural networks.

20. 20. The system of claim 19, wherein the one or more attributes indicate one or more confidence values ​​for the one or more results.

21. The system of claim 17 , wherein the training data comprises one or more frames of one or more videos.

22. 1. A machine-readable medium storing a set of instructions that, when executed by one or more processors, cause the one or more processors to at least: training one or more neural networks using training data, and automatically selecting the training data based at least in part on metadata associated with the training data; automatically selecting the training data using one or more equation solvers to calculate one or more numbers of assets for one or more subsets of the training data; Machine-readable medium.

23. The set of instructions, when executed by the one or more processors, causes the one or more processors to: Obtaining a distribution specified as one or more terms; automatically selecting the training data based at least in part on one or more proportions indicated by the one or more terms. further comprising the instruction:

23. The machine-readable medium of claim 22, wherein the term represents a condition on the metadata and a target percentage of scenes that satisfy the condition.

24. The set of instructions, when executed by the one or more processors, causes the one or more processors to: obtaining one or more sets of assets corresponding to one or more operational design domain (ODD) values ​​indicated by the metadata; selecting a first asset from a first set of assets; calculating one or more distances between the first asset and the first set of assets; selecting a second asset based at least in part on the one or more distances; 23. The machine-readable medium of claim 22, further comprising instructions, wherein the training data comprises the first asset and the second asset.

25. 25. The machine-readable medium of claim 24, wherein the one or more distances are based on a temporal distance or a spatial distance.

26. 23. The machine-readable medium of claim 22, wherein the training data is selected based at least in part on labeled training data used to train the one or more neural networks.

27. The set of instructions, when executed by the one or more processors, causes the one or more processors to: providing the training data to one or more labeling entities to obtain one or more labels; causing the one or more neural networks to process the training data to calculate one or more results; updating the one or more neural networks based at least in part on the one or more results and the one or more labels; 23. The machine-readable medium of claim 22, further comprising instructions.

28. 23. The machine-readable medium of claim 22, wherein the training data comprises one or more images captured from one or more autonomous devices.

Images