Display Device and Driving Method Thereof

Abstract

To provide a display device and a driving method for the display device capable of reducing the time required for pixel sensing.SOLUTION: The display device includes: a display panel 50 on which a plurality of pixels PX are arranged; a data driving section 20 that applies a sensing data voltage to the plurality of pixels PX and outputs a characteristic value sensed in response to the sensing data voltage as sensing data; and a timing control section 10 that compensates video data on the basis of the sensing data and transmits the compensated video data and a control signal to the data driving section 20. The timing control section 10 applies a first sensing data voltage to the plurality of pixels PX in a normal sensing driving mode and applies a second sensing data voltage higher than the first sensing data voltage to the plurality of pixels PX in an overdriving sensing driving mode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a display device and a driving method thereof.

[0002] 2. Description of the Related Art With the development of an information society, various needs for display devices for displaying images are increasing, and various types of display devices such as liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs) are being used.

[0003] A driving transistor provided in a pixel of a display device has characteristic values ​​such as a threshold voltage and mobility, and the characteristic values ​​may change as the pixel deteriorates with an increase in driving time. In order to compensate for the change in the characteristic values, a compensation method may be applied in which the display device is driven in a sensing mode to sense the characteristic values ​​of the pixels, and then data applied to the pixels is compensated based on the sensed values. Summary of the Invention Problem to be solved

[0004] The embodiments provide a display device and a driving method thereof that reduce the time required for sensing pixels.

[0005] The embodiments provide a display device and a driving method thereof that can optimize the design of a data driver and improve the reliability of compensation based on pixel sensing.

[0006] According to one embodiment, a display device may include a display panel having a plurality of pixels arranged thereon, a data driver that applies sensing data voltages to the plurality of pixels and outputs characteristic values ​​sensed in response to the sensing data voltages as sensing data, and a timing controller that compensates image data based on the sensing data and transmits the compensated image data and a control signal to the data driver.

[0007] The timing controller may apply a first sensing data voltage to the plurality of pixels in a normal sensing driving mode, and may apply a second sensing data voltage higher than the first sensing data voltage to the plurality of pixels in an overdriving sensing driving mode.

[0008] The timing controller may calculate a gain value and an offset value for compensating for the image data based on the sensing data, and transmit the gain-compensated image data and the offset value to the data driver.

[0009] The data driver may compensate the image data received from the timing controller based on the received offset value.

[0010] The data driver may include a receiver for receiving the image data from the timing controller, a shift register for outputting a sampling signal in response to the control signal, a latch for latching and outputting the image data in response to the sampling signal, a digital-to-analog converter for converting the image data output from the latch into an analog data voltage, an output buffer for supplying the data voltage output from the digital-to-analog converter to the plurality of pixels via a data line, and an offset compensator for converting the offset value provided from the timing controller into an analog offset voltage and providing the analog offset voltage to the digital-to-analog converter.

[0011] The digital-to-analog converter may include a resistor string that divides a first gamma reference voltage and a second gamma reference voltage to output a plurality of gamma gray scale voltages, and a switch unit that outputs a gamma gray scale voltage corresponding to the image data output from the latch among the plurality of gamma gray scales, and the offset compensator may be connected to an output terminal of the switch unit.

[0012] The control signal may include 2-bit data indicating the normal sensing driving mode, the overdriving sensing driving mode, and the sensing precharge driving mode.

[0013] The timing control unit may apply a sensing data voltage to the plurality of pixels during an initialization period, sense the sensing voltage during a sampling period when the sensing voltage is charged to the pixels during a tracking period, and apply a second sensing data voltage to the plurality of pixels during the initialization period and apply the first sensing data voltage lower than the second sensing data voltage to the plurality of pixels during the sampling period in the overdriving sensing mode.

[0014] In the sensing pre-charge driving mode, the timing controller may apply a pre-charge data voltage lower than the first sensing data voltage to the plurality of pixels during a pre-charge period, and apply the first sensing data voltage to the plurality of pixels during the initialization period.

[0015] The control signal may include an offset value for compensating for an offset of the image data in the over-driving sensing mode, and an offset value for compensating for the offset of the image data in the sensing pre-charge driving mode.

[0016] According to one embodiment, a display device may include a display panel having a plurality of pixels arranged thereon, a data driver that applies sensing data voltages to the plurality of pixels and outputs characteristic values ​​sensed in response to the sensing data voltages as sensing data, and a timing controller that compensates image data based on the sensing data and transmits the compensated image data and a control signal to the data driver.

[0017] The timing control unit may calculate a gain value and an offset value for compensating the image data based on the sensing data, and transmit the gain-compensated image data and the offset value to the data driver, and the data driver may compensate the image data received from the timing control unit based on the received offset value.

[0018] The data driver may include a receiver for receiving the image data from the timing controller, a shift register for outputting a sampling signal in response to the control signal, a latch for latching and outputting the image data in response to the sampling signal, a digital-to-analog converter for converting the image data output from the latch into an analog data voltage, an output buffer for supplying the data voltage output from the digital-to-analog converter to the plurality of pixels via a data line, and an offset compensator for converting the offset value provided from the timing controller into an analog offset voltage and providing the analog offset voltage to the digital-to-analog converter.

[0019] The timing controller may transmit a sensing driving mode and the offset value according to the sensing driving mode to the data driver.

[0020] The data driver may apply a first sensing data voltage to the plurality of pixels in a normal sensing driving mode, and may apply a second sensing data voltage higher than the first sensing data voltage to the plurality of pixels in an overdriving sensing driving mode.

[0021] According to an embodiment, a driving method of a display device includes applying a second sensing data voltage to the plurality of pixels during an initialization period, charging the pixels with a sensing voltage during a tracking period, applying a first sensing data voltage to the pixels during a sampling period, sensing the sensing voltage, and outputting sensing data, and compensating image data applied to the plurality of pixels based on the sensing data, wherein the second sensing data voltage may be set higher than the first sensing data voltage.

[0022] The step of compensating the image data may include the steps of the timing control unit calculating a gain value and an offset value for compensating the image data based on the sensing data, compensating the image data based on the gain value, and transmitting the gain-compensated image data and the offset value to the data driver.

[0023] The step of compensating the image data may further include the step of the data driver compensating the image data received from the timing controller based on the received offset value. [Effects of the Invention]

[0024] The display device and driving method thereof according to the embodiment may shorten the threshold voltage sensing time by overdriving the sensing data voltage during the sensing process and supplying it to the pixel.

[0025] The display device and the driving method thereof according to the embodiment can reduce the sensing time, thereby reducing the mass production time and improving the production yield of products.

[0026] The display device and driving method thereof according to the embodiment may reduce the design complexity of the data driver by compensating for the gain value of the image data using the timing controller.

[0027] The display device and the driving method thereof according to the embodiment can reduce the influence of noise in the compensation of the image data by compensating for the offset value of the image data using the data driver, thereby improving the reliability of sensing. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a block diagram showing a display device according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating sensing timing according to one embodiment. [Figure 3] FIG. 3 is a circuit diagram of one embodiment of the pixel shown in FIG. [Figure 4] FIG. 4 is a diagram illustrating a compensation circuit according to one embodiment. [Figure 5] FIG. 5 is a diagram illustrating a method for sensing the threshold voltage of a driving transistor according to an embodiment. [Figure 6] FIG. 6 is a diagram illustrating a method for sensing the threshold voltage of a driving transistor according to another embodiment. [Figure 7] FIG. 7 is a timing diagram illustrating signals applied from the timing controller to the data driver according to an embodiment. [Figure 8] FIG. 8 is a timing diagram showing a change in the sensing data voltage in the normal sensing driving mode. [Figure 9] FIG. 9 is a timing diagram showing a change in the sensing data voltage in the over-driving sensing driving mode. [Figure 10] FIG. 10 is a timing diagram showing a change in the sensing data voltage in the sensing precharge driving mode. [Figure 11] FIG. 11 is a block diagram showing the structure of a data driver according to an embodiment. [Figure 12] FIG. 12 is a circuit diagram showing the DAC and output buffer shown in FIG. Specific details for implementing the invention

[0029] Hereinafter, examples will be described with reference to the drawings. In this specification, when a component (or region, layer, portion, etc.) is referred to as being "on," "connected," or "bonded" to another component, this means that it may be directly connected / bonded to the other component, or that a third component may be disposed therebetween.

[0030] The same reference numerals refer to the same elements. In the drawings, the thickness, ratio, and dimensions of the elements are exaggerated for the purpose of effectively explaining the technical contents. "And / or" includes all one or more combinations that can define the related configuration.

[0031] Terms such as "first," "second," etc. may be used to describe various components, but the components are not limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be designated a "second component," and similarly, a second component may be designated a "first component," without departing from the scope of the present embodiment. A singular term includes a plural term unless the context clearly dictates otherwise.

[0032] Terms such as "under," "below," "on," and "above" are used to describe the relative relationships of features shown in the drawings. These terms are relative concepts and are described with reference to the directions shown in the drawings.

[0033] The use of terms such as "comprises" or "having" is intended to specify the presence of any feature, number, step, operation, component, part, or combination thereof stated in the specification, and is to be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] FIG. 1 is a block diagram showing a display device according to an embodiment.

[0035] Referring to FIG. 1, the display device (1) includes a timing control unit (10), a data driver (20), a gate driver (30), a power supply unit (40) and a display panel (50).

[0036] The timing control unit 10 receives control signals and video data transmitted from an external system (e.g., a host) and generates a source control signal (DCS) and a gate control signal (GCS). The control signals may include a data enable signal, a horizontal sync signal, a vertical sync signal, and a main clock.

[0037] The gate control signal (GCS) may include scan timing control signals such as a gate start pulse, a gate shift clock, and a gate output enable signal, etc. The source control signal (DCS) may include data timing control signals such as a source sampling clock, a polarity control signal, and a source output enable signal, etc.

[0038] The timing control unit 10 may be disposed on a control printed circuit board connected to a source printed circuit board, to which the data driver 20 is bonded, via a connection medium such as a flexible flat cable (FFC) or a flexible printed circuit (FPC). For example, the timing control unit 10 may be connected to the data driver 20 via an embedded clock PP interface (EPI) wiring pair to transmit and receive data.

[0039] The data driver 20 converts the digital image data (DATA) provided by the timing controller 10 into an analog data signal according to the source control signal (DCS), and applies the analog data signal to the corresponding pixel (PX) via the data line (DL).

[0040] In one embodiment, the data driver 20 may be further connected to the pixel PX via a readout line RVL. The data driver 20 may provide a reference voltage to the pixel PX via the readout line RVL or sense the state of the pixel PX based on an electrical signal fed back from the pixel PX. In this embodiment, the timing controller 10 compensates the image data based on the sensing data Vsen acquired through the data driver 20 to generate compensated image data. The image data may be compensated for one or more of the threshold voltage, mobility, and / or operating point voltage of the organic light emitting diode (OLED) of the pixel PX. By supplying the compensated image data to the data driver 20, image quality degradation such as unevenness of the display panel 50 can be improved.

[0041] The data driver 20 may be configured as a source drive circuit or a source drive IC. The data driver 20 may be connected to a bonding pad of the display panel 50 using a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed on the display panel 50, or may be integrated into the display panel 50 in some cases.

[0042] The gate driver 30 may output scan signals sequentially through the gate lines GL for each horizontal period in one frame in response to gate control signals GCS provided from the timing controller 10. Thus, pixel rows connected to each gate line GL are turned on for each horizontal period. Data signals may be applied to pixel rows turned on by the gate lines GL during one horizontal period.

[0043] In one embodiment, the gate driver 30 may be further connected to the pixel PX via a sensing line SL, and the gate driver 30 may apply a sensing signal to the pixel PX via the sensing line SL during a period for sensing the pixel PX.

[0044] The gate driver 30 may be configured as a stage circuit connected to each of the gate lines GL, or may be configured as a GIP (Gate In Panel) mounted on the display panel 50 as shown in the figure. The gate driver 30 may include a shift register or a level shifter.

[0045] The power supply 40 converts an externally input voltage into a high voltage (ELVDD) and a low voltage (ELVSS), which are standard power supplies used inside the display device 1, and outputs them to the components via power lines PL1 and PL2. The power supply 40 may be disposed on a control printed circuit board on which the timing control unit 10 is disposed. Such a power supply 40 may be called a power management integrated circuit (PMIC).

[0046] A plurality of pixels (PX) (also called sub-pixels) are arranged on the display panel 50. The pixels (PX) may be arranged in a matrix on the display panel 50, for example. The pixels (PX) arranged in one pixel row are connected to the same gate line (GL), and the pixels (PX) arranged in one pixel column are connected to the same data line (DL). The pixels (PX) can emit light at a brightness corresponding to a data signal supplied via the data line (DL).

[0047] In one embodiment, each pixel (PX) can display any of the colors red, green, and blue. In another embodiment, each pixel (PX) can display any of the colors cyan, magenta, and yellow. In various embodiments, each pixel (PX) can also display any of the colors red, green, blue, and white.

[0048] The timing control unit 10, the data driver 20, the gate driver 30, and the power supply unit 40 may be configured as separate integrated circuits (ICs), or may be configured as an integrated circuit in which at least some of them are combined.

[0049] FIG. 2 is a diagram illustrating sensing timing according to one embodiment.

[0050] 2, when a power-on signal is generated, the display device 1 according to one embodiment can sense the characteristic value of the driving transistor in each pixel PX arranged on the display panel 50. This sensing process is called an "on-sensing process."

[0051] In addition, when a power-off signal is generated, the display device 1 can sense the characteristic values ​​of the driving transistors in each pixel PX arranged on the display panel 50 before an off-sequence such as power shutdown is performed. This sensing process is called an "off-sensing process."

[0052] The display device 1 can also sense the characteristic values ​​of the drive transistors in each pixel PX arranged on the display panel 50 during each blank time while the display is being driven, from when a power-on signal is generated until when a power-off signal is generated. This sensing process is called a "real-time sensing process." This real-time sensing process can be performed during each blank time during active time, based on the vertical synchronization signal.

[0053] FIG. 3 is a circuit diagram of one embodiment of the pixel shown in FIG.

[0054] Referring to FIG. 3, a pixel (PX) may include an organic light emitting diode (OLED), a driving transistor (DRT) for driving the organic light emitting diode (OLED), a first transistor (T1) for transmitting a data voltage to a first node (N1) corresponding to a gate node of the driving transistor (DRT), and a storage capacitor (Cst) for maintaining a data voltage corresponding to an image signal voltage or a voltage corresponding thereto for one frame time.

[0055] An organic light-emitting diode (OLED) may include a first electrode (e.g., an anode electrode or a cathode electrode), an organic layer, and a second electrode (e.g., a cathode electrode or an anode electrode). A base voltage (ELVSS) may be applied to the second electrode of the organic light-emitting diode (OLED).

[0056] The drive transistor (DRT) supplies a drive current to the organic light emitting diode (OLED) to drive the organic light emitting diode (OLED). The drive transistor (DRT) has a first node (N1), a second node (N2), and a third node (N3). The first node (N1) of the drive transistor (DRT) may be electrically connected to the source node or the drain node of the first transistor (T1) as a gate node. The second node (N2) of the drive transistor (DRT) may be electrically connected to the first electrode of the organic light emitting diode (OLED) as a source node or a drain node. The third node (N3) of the drive transistor (DRT) may be a drain node or a source node to which a drive voltage (ELVDD) is applied.

[0057] The first transistor T1 is electrically connected between the data line DL and the first node N1 of the drive transistor DRT, and receives a scan signal SCAN at its gate node. The first transistor T1 is turned on by the scan signal SCAN to transfer a data voltage Vdata supplied from the data line DL to the first node N1 of the drive transistor DRT.

[0058] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT.

[0059] As the driving time of the pixel (PX) increases, degradation of circuit elements such as the organic light emitting diode (OLED) and the driving transistor (DRT) may progress, which may change the inherent characteristic values ​​of the circuit elements such as the organic light emitting diode (OLED) and the driving transistor (DRT). Here, the characteristic values ​​may include the threshold voltage of the organic light emitting diode (OLED), the threshold voltage of the driving transistor (DRT), the mobility of the driving transistor (DRT), etc.

[0060] Changes in the characteristic values ​​of circuit elements can cause changes in the brightness of the corresponding pixel (PX). In addition, the degree of change in characteristic values ​​between circuit elements can vary depending on the degree of deterioration of the pixel (PX). Differences in characteristic values ​​can cause uneven brightness between pixels.

[0061] To prevent such a problem, the pixel (PX) according to one embodiment may include a compensation circuit that can sense a characteristic value for the pixel (PX) and compensate for changes in the characteristic value.

[0062] Referring to FIG. 3, the pixel (PX) may further include a second transistor (T2). The second transistor (T2) is electrically connected between a second node (N2) of the drive transistor (DRT) and a readout line (RVL) that supplies a reference voltage (Vref), and may be controlled by receiving a sensing signal (SENSE), which is a type of scan signal, at its gate node. The second transistor (T2) is turned on by the sensing signal (SENSE) and applies the reference voltage (Vref), supplied via the readout line (RVL), to the second node (N2) of the drive transistor (DRT). The second transistor (T2) may also be used as one of the voltage sensing paths for the second node (N2) of the drive transistor (DRT).

[0063] In one embodiment, the scan signal (SCAN) and the sensing signal (SENSE) may be separate scan signals, in which case the scan signal (SCAN) and the sensing signal (SENSE) may be applied to the gate node of the first transistor (T1) and the gate node of the second transistor (T2) via different gate lines.

[0064] In another embodiment, the scan signal (SCAN) and the sensing signal (SENSE) may be the same scan signal, in which case the scan signal (SCAN) and the sensing signal (SENSE) may be commonly applied to the gate node of the first transistor (T1) and the gate node of the second transistor (T2) via the same gate line.

[0065] FIG. 4 is a diagram illustrating a compensation circuit according to one embodiment.

[0066] Referring to FIG. 4, the display device (1) may include a sensing unit (220) that generates and outputs sensing data (Vsen) by sensing the voltage of the pixel (PX), a compensation unit (110) that determines a characteristic value of the pixel (PX) using the sensing data (Vsen) and performs a compensation process to compensate for the determined characteristic value, and a memory unit (120) that stores preset initial compensation data (or initial compensation value) and the compensation value generated by the compensation unit (110).

[0067] The sensing unit 220 may be implemented by including at least one analog-to-digital converter (ADC) 223 (FIG. 11). The sensing unit 220 may be provided within the data driver 20 as shown. The sensing data Vsen output from the sensing unit 220 may have, for example, a Low Voltage Differential Signaling (LVDS) data format.

[0068] The compensation unit 110 and the memory unit 120 may be provided inside the timing control unit 10. The memory unit 120 may receive and store the sensing data Vsen from the sensing unit 220 and transmit the stored sensing data Vsen to the compensation unit 110. In another embodiment, the compensation unit 110 may directly receive the sensing data Vsen, calculate a compensation value, and then store the compensation value and the sensing data Vsen in the memory unit 120.

[0069] The memory unit 120 may store preset initial compensation data, or may store sensing data (Vsen) applied from the sensing unit 220 or a compensation value calculated by the compensation unit 110.

[0070] The display device (1) may include an initialization switch (SPRE) that controls the on / off of the readout line (RVL), and a sampling switch (SAM) that controls the connection between the readout line (RVL) and the sensing unit (220).

[0071] The initialization switch (SPRE) can control the voltage application state of the second node (N2) of the drive transistor (DRT) so that the second node (N2) of the drive transistor (DRT) in the pixel (PX) is in a voltage state that reflects the characteristic value of a desired circuit element. When the initialization switch (SPRE) is turned on, the reference voltage (Vref) is supplied to the readout line (RVL) and applied to the second node (N2) of the drive transistor (DRT) via the second transistor (T2) that is turned on.

[0072] The sampling switch (SAM) is turned on to electrically connect the readout line (RVL) to the sensing unit 220. The sampling switch (SAM) may be controlled to be turned on when the second node (N2) of the drive transistor (DRT) in the pixel (PX) reaches a voltage state that reflects a desired characteristic value of a circuit element. When the sampling switch (SAM) is turned on, the sensing unit 220 can sense the voltage of the connected readout line (RVL).

[0073] When the sensing unit 220 senses the voltage of the readout line RVL, if the second transistor T2 is turned on and the resistance component of the drive transistor DRT can be ignored, the voltage sensed by the sensing unit 220 may correspond to the voltage of the second node N2 of the drive transistor DRT. The voltage sensed by the sensing unit 220 may be the voltage of the readout line RVL, i.e., the voltage of the second node N2 of the drive transistor DRT.

[0074] If a line capacitor is present on the readout line (RVL), the voltage sensed by the sensing unit 220 may be the voltage charged in the line capacitor on the readout line (RVL). Here, the readout line (RVL) is also referred to as a sensing line. For example, the voltage sensed by the sensing unit 220 may be a voltage value including the threshold voltage (Vth) or threshold voltage deviation (ΔVth) of the drive transistor (DRT) (Vdata-Vth or Vdata-ΔVth, where Vdata is a sensing data voltage), or a voltage value for sensing the mobility of the drive transistor (DRT).

[0075] The sensing unit 220 converts the sensed voltage Vsen into a digital value for sensing the threshold voltage, generates and outputs sensing data Vsen including the converted digital value (sensing value). The sensing data output from the sensing unit 220 may be provided to the compensation unit 110. In some cases, the sensing data may be provided to the compensation unit 110 by the memory unit 120.

[0076] The compensating unit 110 can perform a characteristic value compensation process by determining a characteristic value (e.g., threshold voltage) of the driving transistor (DRT) in a corresponding subpixel or a change in the characteristic value (e.g., threshold voltage change) of the driving transistor (DRT) based on the sensing data (Vsen) provided from the sensing unit 220. Here, the change in the characteristic value of the driving transistor (DRT) may mean that the current sensing data (Vsen) has changed based on the previous sensing data (Vsen), or that the current sensing data (Vsen) has changed based on initial compensation data. Here, the initial compensation data may be initial setting data that is set and stored during the manufacture of the display device.

[0077] The characteristic value compensation process may include a threshold voltage compensation process for compensating for the threshold voltage of the drive transistor (DRT). The threshold voltage compensation process may include a process of calculating a compensation value for compensating for the threshold voltage or a threshold voltage deviation (threshold voltage change), and storing the calculated compensation value in the memory unit 120, or modifying corresponding image data (DATA) with the calculated compensation value. In one embodiment, the compensation value may include an offset value and a gain value for compensating for the threshold voltage or the threshold voltage deviation.

[0078] The compensator 110 may change the image data (DATA) through a threshold voltage compensation process and provide the compensated image data (MDATA) to the data driver 20. For example, the compensator 110 may compensate the image data (DATA) by applying a determined offset value and a determined gain value to the image data (DATA).

[0079] In another embodiment, the compensator 110 may operate as a gain compensator that compensates for the image data (DATA) using a gain value. In this embodiment, the compensator 110 may transmit the gain-compensated image data (MDATA) to the data driver 20 without compensating for the offset value of the image data (DATA). Alternatively, the compensator 110 may transmit the offset value determined by sensing the pixel PX to the data driver 20. The data driver 20 may apply an offset compensation value to the gain-compensated image data (MDATA) transmitted from the timing controller 10 using an offset compensator 217 (see FIGS. 11 and 12) provided therein, thereby ultimately generating a data voltage (VDATA) in which both the gain and offset values ​​are compensated.

[0080] In this way, when the timing control unit 10 determines a gain value for compensating for the image data and compensates for the image data using the determined gain value, a gain value calculation unit is not required in the data driver 20, which reduces the design complexity and enables the implementation of an optimized data driver 20. Furthermore, by performing final compensation for the offset value in the data driver 20, it is possible to solve the problem of reduced compensation reliability due to noise when the timing control unit 10 compensates for the offset.

[0081] The data supply unit 210 of the data driver 20 supplies the data voltage Vdata, which has been compensated for the gain and offset, to the corresponding pixel PX, thereby performing pixel characteristic value compensation (threshold voltage compensation). This pixel characteristic value compensation reduces or prevents brightness deviation between pixels PX, thereby improving image quality.

[0082] The threshold voltage sensing driving for the driving transistor (DRT) will be briefly described below.

[0083] 5 and 6 are diagrams illustrating a method for sensing the threshold voltage of a driving transistor according to another embodiment of the present invention.

[0084] 4 and 5, threshold voltage sensing driving for the driving transistor (DRT) can be performed in a sensing process including an initialization period (T1), a tracking period (T2), and a sampling period (T3).

[0085] The initialization period T1 is a period during which the first node N1 and the second node N2 of the driving transistor DRT are initialized. During the initialization period T1, the initialization switch SPRE is turned on. Also, a scan signal SCAN and a sensing signal SENSE may be applied to turn on the first transistor T1 and the second transistor T2. As a result, the first node N1 and the second node N2 of the driving transistor DRT are initialized to the first sensing data voltage V1 and the reference voltage Vref, respectively (VN1=Vdata, VN2=Vref).

[0086] The tracking period T2 is a period during which the pixel PX is charged with a sensing voltage, during which the voltage VN2 of the second node N2 of the drive transistor DRT is changed until the voltage of the second node N2 of the drive transistor DRT reaches a threshold voltage or a voltage state that reflects a change therein. That is, the tracking period T2 is a step of tracking the voltage of the second node N2 of the drive transistor DRT, which can reflect the threshold voltage or a change therein. During the tracking period T2, the initialization switch SPRE is turned off or the second transistor T2 is turned off, causing the second node N2 of the drive transistor DRT to float. This causes the voltage VN2 of the second node N2 of the drive transistor DRT to rise.

[0087] The voltage (VN2) at the second node (N2) of the driving transistor (DRT) rises and then gradually decreases until it saturates. The saturated voltage at the second node (N2) of the driving transistor (DRT) may correspond to the difference between the first sensing data voltage (V1) and the threshold voltage (Vth) or the difference between the first sensing data voltage (V1) and the threshold voltage deviation (ΔVth).

[0088] When the voltage (VN2) at the second node (N2) of the drive transistor (DRT) is saturated, a sampling period (T3) may occur. The sampling period (T3) is a period for measuring the threshold voltage of the drive transistor (DRT) or a voltage reflecting a change therein, and is a step in which the sensing unit 220 senses the sensing voltage charged to the pixel (PX), i.e., the voltage of the readout line (RVL). During this sampling period (T3), the sampling switch (SAM) is turned on, and the sensing unit 220 is connected to the readout line (RVL) to sense the voltage of the readout line (RVL), i.e., the voltage (VN2) at the second node (N2) of the drive transistor (DRT).

[0089] The voltage (Vsen) sensed by the sensing unit 220 may be a voltage (V1-Vth) obtained by subtracting a threshold voltage (Vth) from the first sensing data voltage (V1), or a voltage (V1-ΔVth) obtained by subtracting a threshold voltage deviation (ΔVth) from the first sensing data voltage (V1). Here, the threshold voltage (Vth) may be a positive threshold voltage or a negative threshold voltage.

[0090] The sensing of the threshold voltage of the driving transistor (DRT) as described above takes a relatively long time because it requires a long voltage saturation time of the second node (N2) of the driving transistor (DRT). Therefore, the sensing of the threshold voltage of the driving transistor (DRT) can be performed by an off-sensing process while the display is not being driven after a power-off signal is generated by a user input, for example, and while the user does not intend to watch.

[0091] 6, in another embodiment, the second sensing data voltage V2 may be a voltage greater than the first sensing data voltage V1 applied in the embodiment of FIG. 5. In this case, the second sensing data voltage V2 may be determined by applying a predetermined gain value to the first sensing data voltage V1. For example, the second sensing data voltage V2 may be determined by multiplying the first sensing data voltage V1 by the predetermined gain value (V2=V1×gain). The gain value may be an integer greater than 1 and may be set to be the same or different for each pixel PX.

[0092] In such an over-driving sensing drive, the first sensing data voltage (V1) may also be applied during the sampling period (T3) to stabilize the sensing voltage. That is, in the over-driving sensing drive, the over-driven second sensing data voltage (V2) is applied to the pixel (PX) during the initialization period (T1) and the tracking period (T2) to accelerate the saturation time, and then during the sampling period (T3), the sensing data voltage is lowered to the first sensing data voltage (V1) to measure the stabilized sensing voltage.

[0093] As described above, the voltage saturation time can be significantly reduced by overdriving the sensing data voltage V1 by a predetermined gain value. That is, when a relatively high sensing data voltage is applied, the voltage VN2 of the second node N2 is saturated within a relatively short time, as shown in FIG. 6, and as a result, the threshold voltage sensing time can be reduced.

[0094] The over-driving sensing drive and the resulting gain value can be instructed by a control signal transmitted from the timing control unit 10 to the data driver 20. For example, the over-driving sensing drive and the resulting sensing data voltage (e.g., gain value) can be transmitted from the timing control unit 10 to the data driver 20 via an EPI line pair.

[0095] Figure 7 is a timing diagram showing signals applied from a timing controller to a data driver according to an embodiment. Figure 8 is a timing diagram showing changes in a sensing data voltage in a normal sensing driving mode. Figure 9 is a timing diagram showing changes in a sensing data voltage in an over-driving sensing driving mode. Figure 10 is a timing diagram showing changes in a sensing data voltage in a sensing pre-charge driving mode.

[0096] Referring to FIG. 7, the timing control unit 10 can transmit the clock training pattern CT, the control data ctrl, and the image data DATA to the data driver 20 in sequence.

[0097] The clock training pattern (CT) is a clock signal for synchronizing the operation timing of the timing control unit (10) and the data driver (20), and may be a square wave signal. The image data (DATA) may include grayscale values ​​for each of the R, G, and B colors.

[0098] The control data (ctrl) may include information indicating the start of the control data (ctrl), information indicating the start position of the video data (DATA), information indicating the rising time and pulse width of the source output enable signal, etc. The control data (ctrl) may also include source control data and gate control data.

[0099] The control data (ctrl) may further include a control packet that controls various functions that can be implemented by the data driver 20. The control packet may indicate the above information using a low or high level. In one embodiment, information corresponding to bits that make up the control packet may be defined as shown in Table 1.

[0100] [Table 1] In the control packet of Table 1, the over-driving sensing driving mode may be indicated by 2-bit data included in the control A packet (CTR_A, first control packet). Specifically, the second and third bits of the control A packet (CTR_A) are control signals that indicate the over-driving sensing driving and a specific over-driving sensing driving mode.

[0101] At this time, the over-driving sensing mode according to the value of the 2-bit data constituting the over-driving sensing control signal can be defined as shown in Table 2.

[0102] [Table 2] When the 2-bit data of the over-driving sensing control signal is '00', the normal sensing driving mode is applied, when it is '10', the over-driving sensing driving mode is applied, and when it is '11', the sensing pre-charge driving mode is applied. The sensing data voltage can be set by the over-driving sensing control signal as described above.

[0103] Referring to FIG. 8, in the normal sensing mode, the sensing data voltage is set to a first sensing data voltage (V1). Referring to FIG. 9, in the over-driving sensing mode, the sensing data voltage may be set to a second sensing data voltage (V2) higher than the first sensing data voltage (V1). Referring to FIG. 10, in the sensing pre-charge mode, a pre-charge data voltage (V3) may be applied during a predetermined pre-charge period before the initialization period (T1), and then the first sensing data voltage (V1) may be applied. In this pre-charge mode, by pre-charging the voltage (VN2) of the second node (N2) in the pixel (PX) with the predetermined pre-charge data voltage (V3), the time it takes for the voltage (VN2) of the second node (N2) to saturate can be reduced.

[0104] In the control packets in Table 1, an offset value (offset) for video data (DATA) in the over driving sensing driving mode may be indicated via a control B packet (CTR_B, second control packet). For example, the offset may be indicated by 10-bit data included in the control B packet (CTR_B). Specifically, bits 2 to 11 of the control B packet (CTR_B) may indicate a first offset value (offset), and bits 12 to 21 may indicate a second offset value (offset).

[0105] The offset value (offset) is determined by sensing the characteristic value of the driving transistor (DT) in the pixel (PX) and can be transmitted to the data driver 20 through a control packet. The data driver 20 obtains the offset from the control packet and applies the obtained offset to the image data (DATA) transmitted in the form of RGB data to generate compensated image data (MDATA).

[0106] Furthermore, in the control packets of Table 1, an offset value (offset) for video data (DATA) in the sensing precharge driving mode may be indicated via a control C packet (CTR_C, third control packet). For example, the offset may be indicated by 10-bit data included in the control C packet (CTR_C). Specifically, bits 2 to 11 of the control C packet (CTR_C) may indicate a first offset, and bits 12 to 21 may indicate a second offset.

[0107] FIG. 11 is a block diagram showing the structure of a data driver according to an embodiment.

[0108] Referring to FIG. 11, the data driver 20 includes a data supply unit 210, a sensing unit 220, a current source 230, and the like.

[0109] The data supply unit 210 includes a receiving unit 211, a shift register 212, a first latch 213, a second latch 214, a digital-analog converter (DAC) 215, and an output buffer 216.

[0110] The receiver 211 receives signals from the timing controller 10 via various interface technologies, such as an LVDS interface, EPI, DP, or eDP interface, and recovers and outputs video data (DATA) and source control signals (SSP, SSC, SOE) from the received signals. In one embodiment, the video data (MDATA) received through the receiver 211 may be video data whose gain is compensated for by pixel sensing. The source control signals (SSP, SSC, SOE) may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). The source start pulse (SSP) controls the start point of data sampling in the source driver IC. The source sampling clock (SSC) is a clock signal that controls the data sampling operation within the source driver IC based on a rising or polling edge. The source output enable signal (SOE) controls the output of the source driver IC.

[0111] The receiver 211 may be configured to include a serial-parallel converter, etc. In one embodiment, the receiver 211 may receive a control packet from the timing controller 10 via an EPI interface, etc., and obtain control information for overdriving sensing operation from the control packet.

[0112] The shift register 212 outputs a sampling signal in response to a source start pulse (SSP) and a source sampling clock (SSC) provided from the timing control unit 10.

[0113] The first latch 213 sequentially latches the digital image data (DATA) in response to the sampling signal sequentially input from the shift register 212, and then outputs the data in parallel latch form. The first latch 213 simultaneously outputs the image data (DATA) of one horizontal line sampled in response to the source output enable signal (SOE).

[0114] The second latch 214 latches the data input from the first latch 213 and then outputs the latched image data DATA simultaneously with the second latch 214 of another source drive IC during the logic low period of the source output enable signal SOE.

[0115] The DAC 215 receives the gamma gradation voltage GV and converts one horizontal line of image data MDATA into a data voltage Vdata using the gamma gradation voltage GV. That is, the DAC 215 converts the digital image data MDATA into an analog data voltage Vdata. The output buffer 216 supplies the data voltage Vdata output from the DAC 215 to the data line DL in response to a source output enable signal SOE.

[0116] In one embodiment, the data provider 210 may further include an offset compensator 217. The offset compensator 217 recovers an offset from a control packet received from the timing controller 10 via the receiver 211, converts the recovered digital offset into an analog form, and provides the analog form to the DAC 215.

[0117] In one embodiment, the offset value (offset) may be transmitted from the timing control unit 10 to the second latch 214 and output from the second latch 214 to the offset compensator 217. However, this embodiment is not limited to this.

[0118] The offset compensator 217 may convert the digital offset value into an analog voltage and output it to the DAC 215. The offset compensator 217 may include a DAC for this purpose. In this case, the offset value is applied to the data voltage Vdata output from the DAC 215, thereby generating a finally compensated data voltage Vdata.

[0119] The sensing unit (220) includes a current-voltage conversion unit (221), a noise removal unit (222), and an ADC (223).

[0120] The current-to-voltage converter 221 converts an input current for each channel from the display panel 50 or the current source 230 into a voltage by current integration and outputs the voltage as a voltage sensing value. The noise eliminator 222 eliminates noise sensed through an adjacent channel from the actual sensing value for each channel of the current-to-voltage converter 221 using the current source 230, and outputs a channel sensing value. The ADC 223 converts the channel sensing value supplied from the noise eliminator 222 or the pixel sensing value supplied from the current-to-voltage converter 221 bypassing the noise eliminator 222 into digital data and outputs the digital data to the timing controller 10 as sensing data (Vsen).

[0121] Meanwhile, although the current source 230 is provided within the data driver 20 in the illustrated embodiment, this embodiment is not limited thereto, that is, in other embodiments, the current source 230 may be a current source provided separately outside the data driver 20.

[0122] FIG. 12 is a circuit diagram showing the DAC and output buffer shown in FIG.

[0123] Referring to FIG. 12, the DAC (215) includes a resistor string (RS) and a switch section (SW).

[0124] The resistor string (RS) includes a plurality of resistors (R1 to Ri, where i is a natural number), and the plurality of resistors (R1 to Ri) are connected in series between first and second gamma reference voltages (VGR1, VGR2). The resistor string (RS) receives the first and second gamma reference voltages (VGR1, VGR2), and a plurality of gamma gray scale voltages (GV) may be output through nodes between the plurality of resistors (R1 to Ri).

[0125] The switch unit (SW) may include a plurality of switches. Each switch is connected to a node between the plurality of resistors (R1 to Ri) and may receive a gamma gradation voltage (GV). The switch unit (SW) may convert the image data (DATA) output from the second latch 214 into a corresponding one of the gamma gradation voltages (GV) and output the converted data. In one embodiment, the switches may be configured with transistors.

[0126] The output buffer 216 may include an amplifier (amp) for amplifying or compensating the data voltage (Vdata) output from the DAC 215. The output buffer 216 may output the gamma gradation voltage (GV) output to the switch unit (SW) as a data voltage (Vdate) to the data line (DL).

[0127] In one embodiment, an offset compensator 217 may be connected to the output terminal of the switch unit (SW). The offset compensator 217 may obtain an offset value (offset) from a control packet transmitted from the timing controller 10. The offset compensator 217 may convert the digital offset value (offset) into an analog offset voltage and apply it to the output terminal of the switch unit (SW). At the output terminal of the switch unit (SW), the gamma gray scale voltage (GV) may be combined with the offset voltage and output as a data voltage (Vdata).

[0128] Although the present invention has been described above with reference to the accompanying drawings, those skilled in the art will understand that the technical configuration of the present invention described above can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and not limiting. At the same time, the scope of the present invention is defined by the claims that follow rather than the above detailed description. Furthermore, all modifications and variations derived from the meaning and scope of the claims and their equivalents should be construed as being within the scope of the present invention. [Explanation of symbols]

[0129] 1:Display device 10: Timing control section 20: Data driver 30: Gate driver 40: Power supply section 50: Display panel

Claims

1. a display panel in which a plurality of pixels are arranged; a data driver that applies sensing data voltages to the pixels and outputs characteristic values ​​sensed in response to the sensing data voltages as sensing data; and a timing controller for compensating image data based on the sensing data and transmitting the compensated image data and a control signal to the data driver; the data driver applies a first sensing data voltage to the plurality of pixels in a normal sensing driving mode, and applies a second sensing data voltage higher than the first sensing data voltage to the plurality of pixels in an overdriving sensing driving mode; the timing controller calculates a gain value and an offset value for compensating the image data based on the sensing data, and transmits the gain-compensated image data and the offset value to the data driver; The data driver a receiving unit that receives the video data from the timing control unit; a shift register that outputs a sampling signal in response to the control signal; a latch that latches and outputs the video data in response to the sampling signal; a digital-to-analog converter that converts the video data output from the latch into an analog data voltage; an output buffer that supplies the analog data voltage output from the digital-to-analog converter to the plurality of pixels via a data line; an offset compensator for converting the offset value provided by the timing controller into an analog offset voltage and providing the analog offset voltage to the digital-to-analog converter; Display device.

2. The display device of claim 1 , wherein the data driver compensates the image data received from the timing controller based on the received offset value.

3. The digital-to-analog converter a resistor string that divides the first gamma reference voltage and the second gamma reference voltage to output a plurality of gamma gradation voltages; a switch unit that outputs a gamma gradation voltage corresponding to the image data output from the latch among the plurality of gamma gradation voltages; The display device of claim 1 , wherein the offset compensator is connected to an output terminal of the switch unit.

4. the control signal includes 2-bit data instructing the normal sensing driving mode, the overdriving sensing driving mode, and the sensing precharge driving mode; the sensing precharge driving mode is a mode in which the timing controller applies a precharge data voltage lower than the first sensing data voltage to the plurality of pixels during a precharge period, and applies the first sensing data voltage to the plurality of pixels during an initialization period. The display device according to claim 1 .

5. The timing control unit applying a sensing data voltage to the plurality of pixels during an initialization period, and sensing the sensing voltage when the sensing voltage is charged to the pixels during a tracking period; 5. The display device of claim 4, wherein in the over-driving sensing driving mode, a second sensing data voltage is applied to the plurality of pixels during the initialization period, and the first sensing data voltage lower than the second sensing data voltage is applied to the plurality of pixels during the sampling period.

6. 5. The display device of claim 4, wherein the control signal includes an offset value for compensating for an offset of the image data in the overdriving sensing driving mode and an offset value for compensating for the offset of the image data in the sensing precharge driving mode.

7. a display panel in which a plurality of pixels are arranged; a data driver that applies sensing data voltages to the pixels and outputs characteristic values ​​sensed in response to the sensing data voltages as sensing data; and a timing controller for compensating image data based on the sensing data and transmitting the compensated image data and a control signal to the data driver; the timing controller calculates a gain value and an offset value for compensating the image data based on the sensing data, and transmits the gain-compensated image data and the offset value to the data driver; the data driver compensates for the image data received from the timing controller based on the received offset value; The data driver a receiving unit that receives the video data from the timing control unit; a shift register that outputs a sampling signal in response to the control signal; a latch that latches and outputs the video data in response to the sampling signal; a digital-to-analog converter that converts the video data output from the latch into an analog data voltage; an output buffer that supplies the data voltage output from the digital-to-analog converter to the plurality of pixels via a data line; and an offset compensator for converting the offset value provided by the timing controller into an analog offset voltage and providing the analog offset voltage to the digital-to-analog converter; Display device.

8. The display device of claim 7 , wherein the timing controller transmits a sensing driving mode and the offset value according to the sensing driving mode to the data driver.

9. 9. The display device of claim 8, wherein the data driver applies a first sensing data voltage to the plurality of pixels in a normal sensing driving mode, and applies a second sensing data voltage higher than the first sensing data voltage to the plurality of pixels in an overdriving sensing driving mode.

10. 10. The method of claim 1, further comprising: a display panel having a plurality of pixels arranged thereon; a data driver applying a data voltage to the plurality of pixels; and a timing controller controlling the data driver, applying a second sensing data voltage to the plurality of pixels during an initialization period; charging the pixel with a sensing voltage during a tracking period; applying a first sensing data voltage to the pixel during a sampling period, sensing the sensing voltage, and outputting sensing data; and Compensating image data applied to the plurality of pixels based on the sensing data; The second sensing data voltage is set higher than the first sensing data voltage.

11. The step of compensating the video data includes: the timing control unit calculating a gain value and an offset value for compensating the image data based on the sensing data; compensating the video data based on the gain value; and 11. The method of claim 10, further comprising transmitting the gain-compensated image data and the offset value to the data driver.

12. The step of compensating the video data includes: The method of claim 11 , further comprising: the data driver compensating the image data received from the timing controller based on the received offset value.

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