Display panel and display device

Abstract

To provide a display panel and a display device that efficiently control a pixel circuit including a plurality of light emitting elements by using a mode control unit.SOLUTION: A display device according to one embodiment of the present specification may comprise: a mode control unit that is configured to generate a first control signal and a second control signal by using a gate-off voltage and a gate-on voltage; a gate driving circuit that is configured to generate a light emission signal; a first pixel circuit that includes a driving transistor, a first transistor receiving the first control signal, a second transistor receiving the second control signal, a third transistor receiving a provision of the light emission signal, a first light emitting element connected to the first transistor, and a second light emitting element connected to the second transistor; a first lens to be disposed on the first light emitting element; and a second lens to be disposed on the second light emitting element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display panel and a display device. [Background technology]

[0002] As technology advances in modern society, display devices are used in a variety of ways to provide information to users. Display devices range from electronic boards that simply transmit visual information in one direction to various electronic devices that require more advanced technology to confirm user input and provide information corresponding to the confirmed input.

[0003] For example, a display device may be included in a vehicle and provide various information to the driver and passengers of the vehicle. However, the display device of the vehicle must display content appropriately so as not to interfere with the operation of the vehicle. For example, the display device must limit the display of content that may distract the driver while driving the vehicle. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the embodiments of the present specification is to provide a display device and a display panel that efficiently controls pixel circuits including a plurality of light-emitting elements using a mode control unit.

[0005] However, the problems to be solved in this specification are not limited to those mentioned above, and other technical problems can be inferred from the following examples. [Means for solving the problem]

[0006] A display device according to an embodiment of the present specification may include a mode control unit that generates a first control signal and a second control signal using a gate-off voltage and a gate-on voltage, a gate driving circuit that generates an emission signal, a driving transistor, a first transistor that receives the first control signal, a second transistor that receives the second control signal, a third transistor that receives the emission signal, a first pixel circuit including a first light-emitting element connected to the first transistor and a second light-emitting element connected to the second transistor, a first lens arranged on the first light-emitting element, and a second lens arranged on the second light-emitting element.

[0007] A display panel according to one embodiment of the present specification may include a mode control unit that generates a first control signal and a second control signal using a gate-off voltage and a gate-on voltage, a gate driving circuit that generates an emission signal, a driving transistor, a first transistor that receives the first control signal, a second transistor that receives the second control signal, a third transistor that receives the emission signal, a first pixel circuit including a first light-emitting element connected to the first transistor and a second light-emitting element connected to the second transistor, a first lens arranged on the first light-emitting element, and a second lens arranged on the second light-emitting element.

[0008] Further details of the embodiments are included in the detailed description and drawings.

[0009] The display device and display panel according to the present specification can efficiently control pixel circuits including a plurality of light-emitting elements using a mode controller, and can vary the sizes of a common area and a control area by controlling signals provided to the plurality of light-emitting elements using the mode controller.

[0010] However, the effects obtained from this specification are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those having ordinary skill in the art to which this specification pertains from the description below. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is an example of a display device according to an embodiment of the present specification. [Figure 2] FIG. 1 is a functional block diagram of a display device according to an embodiment of the present specification. [Figure 3] 1 illustrates an example of a pixel circuit of a display device according to an embodiment of the present specification. [Figure 4] 1 illustrates an example pixel array of a display device according to an embodiment of the present disclosure. [Figure 5] 1 illustrates an example of a pixel circuit of a display device according to an embodiment of the present specification. [Figure 6] 1 illustrates an example of a pixel circuit of a display device according to an embodiment of the present specification. [Figure 7] 1 illustrates an example of a lens arrangement included in a display device according to an embodiment of the present disclosure. [Figure 8] An example of the II' cross section of FIG. 7 is shown. [Figure 9] An example of a cross section taken along line II-II' in FIG. 7 is shown. [Figure 10] FIG. 2 is a diagram illustrating a gate drive circuit of a display device according to an embodiment of the present specification. [Figure 11] 1 is a diagram illustrating a display device according to an embodiment of the present specification; [Figure 12] 1 is a diagram illustrating a display device according to an embodiment of the present specification; [Figure 13] 1 is a diagram illustrating a display device according to an embodiment of the present specification; [Figure 14] 2 is a diagram illustrating a circuit connection relationship of a display device according to an embodiment of the present disclosure; FIG. [Figure 15] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present specification. [Figure 16] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present specification. [Figure 17] FIG. 10 is a diagram illustrating a display device according to another embodiment of the present specification. [Figure 18]10 is a diagram illustrating a circuit connection relationship of a display device according to another embodiment of the present disclosure; DETAILED DESCRIPTION OF THE INVENTION

[0012] The terms used in the examples are currently commonly used and general terms that have been selected as much as possible while taking into consideration the functions in the present disclosure, but this may change depending on the intentions of engineers in the field, precedents, the emergence of new technologies, etc. In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, the meanings thereof will be described in detail in the relevant description section. Therefore, the terms used in the present disclosure should be defined based on the meanings of the terms and the overall content of the present disclosure, rather than simply by the names of the terms.

[0013] Throughout the specification, when a part is said to "comprise" a certain element, this does not mean that it excludes other elements, but that it may further include other elements, unless specifically stated to the contrary.

[0014] The expression "at least one of a, b, and c" used throughout this specification can encompass "a alone," "b alone," "c alone," "a and b," "a and c," "b and c," or "all of a, b, and c." Advantages and features of the present specification, and methods for achieving them, will become apparent with reference to the examples described below in detail in conjunction with the accompanying figures.

[0015] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments in this specification are merely examples, and the embodiments of this specification are not limited to the details shown in the drawings. Furthermore, in the description of the embodiments, if it is determined that a detailed description of related publicly known technology may unnecessarily obscure the gist of the embodiments, the detailed description will be omitted.

[0016] When terms such as "comprise," "have," and "consist of" are used in this specification, other parts may be added. When an element is expressed in the singular, it also includes the plural unless otherwise expressly stated. In addition, when analyzing elements, it is interpreted as including a margin of error even if there is no other explicit statement.

[0017] When describing the positional relationship between two parts, for example, by using "on," "on top," "under," "next to," etc., one or more other parts may be disposed between the two parts. When an element or layer is described as "on" another element or layer, this includes all cases where another layer or other element is interposed between the other element or layer.

[0018] Furthermore, although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0019] The area, length, or thickness of each structure described in the specification is shown for convenience of explanation and is not necessarily limited to the area and thickness of the structure shown in this specification.

[0020] The features of the various embodiments of this specification may be partially or fully combined or combined with each other, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of each other or in conjunction with each other.

[0021] The terms described below are defined in consideration of the functions in the implementation of this specification, and may vary depending on the intentions of users or operators, customs, etc. Therefore, the definitions must be determined based on the contents of this specification as a whole.

[0022] The transistors constituting the pixel circuits of this specification can include at least one of oxide thin film transistors (Oxide TFTs), amorphous silicon TFTs (a-Si TFTs), and low temperature polysilicon (LTPS) TFTs.

[0023] The following embodiments will be described focusing on organic light emitting display devices. However, the embodiments of the present invention are not limited to organic light emitting display devices and may also be applied to inorganic light emitting display devices containing inorganic light emitting materials. For example, the embodiments of the present invention may also be applied to quantum dot display devices.

[0024] The terms "first," "second," "third," etc. are used to distinguish between configurations in each embodiment, and the embodiments are not limited to these terms. Therefore, it should be made clear that the same term may refer to different configurations depending on the embodiment.

[0025] Hereinafter, examples of the present specification will be described with reference to the drawings.

[0026] FIG. 1 is an example of a display device according to one embodiment of the present specification.

[0027] In an embodiment, the display device 100 may be disposed in at least a portion of a vehicle dashboard. The vehicle dashboard may include components disposed in front of the front seats (e.g., driver's seat, passenger seat) of the vehicle. For example, the vehicle dashboard may include input components for operating various functions (e.g., air conditioning, audio system, navigation system) inside the vehicle.

[0028] In an embodiment, the display device 100 is disposed on a dashboard of a vehicle and can operate as an input unit for operating at least some of the various functions of the vehicle. The display device 100 can provide various information about the vehicle, such as vehicle driving information (e.g., current vehicle speed, remaining fuel amount, mileage), information about vehicle parts (e.g., damage level of vehicle tires), etc.

[0029] In an embodiment, the display device 100 may be disposed across the driver's seat and passenger seat, which are disposed in the front seats of a vehicle. Users of the display device 100 may include the driver of the vehicle and a passenger sitting in the passenger seat. Both the driver and the passenger of the vehicle may use the display device 100.

[0030] In the embodiment, the display device 100 shown in FIG. 1 may be only a part thereof. The display device 100 shown in FIG. 1 may be a part of a display panel among various components included in the display device 100. Specifically, for example, the display device 100 shown in FIG. 1 may be a part of a display area and a part of a non-display area of ​​the display panel. Of the components of the display device 100, components other than those shown in FIG. 1 may be implemented inside (or at least in part of) a vehicle.

[0031] FIG. 2 is a functional block diagram of a display device according to an embodiment of the present specification.

[0032] The display device according to an embodiment of the present specification may be an electroluminescent display device. The electroluminescent display device may be an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (QLD) display device, or an inorganic light emitting diode (ILD) display device.

[0033] Referring to FIG. 2, the display device may include a display panel (DP), a data driver (DD), a gate driver (GD), a timing controller (TC), and a power supply unit (PU).

[0034] In an embodiment, the display panel (DP) may generate an image to be provided to a user, for example, the display panel (DP) may generate and display an image to be provided to a user through a pixel area (PA) in which pixel circuits are arranged.

[0035] The data driver (DD), gate driver (GD), timing controller (TC), and power supply unit (PU) can provide signals for the operation of each pixel area (PA) through signal wiring, which can include, for example, data lines (DL), gate lines (GL), and power supply voltage lines (PL) shown in FIG.

[0036] As an example, the data driver (DD) can apply a data signal to each pixel area (PA) via a data line (DL), the gate driver (GD) can apply a data signal to each pixel area (PA) via a gate line (GL), and the power supply unit (PU) can supply a power supply voltage to each pixel area (PA) via a power supply voltage supply line (PL).

[0037] The timing controller (TC) can control the data driver (DD) and the gate driver (GD). For example, the timing controller (TC) realigns externally input digital video data to match the resolution of the display panel (DP) and supplies the data driver (DD).

[0038] The data driver (DD) can convert digital video data input from the timing controller (TC) into analog data voltages based on a data control signal and supply the analog data voltages to a plurality of data lines.

[0039] The gate driver (GD) can generate scan signals and emission signals (or emission control signals) based on gate control signals. The gate driver (GD) can include a scan driver and an emission signal driver. The scan driver can generate scan signals in a row sequential manner to drive at least one scan line connected to each row of pixels and supply them to the scan lines. The emission signal driver can generate emission signals in a row sequential manner to drive at least one emission signal line connected to each row of pixels and supply them to the emission signal lines.

[0040] According to an embodiment, the gate driver (GD) may be arranged on the display panel (DP) in a GIP (Gate-driver In Panel) manner. For example, the gate driver (GD) may be divided into a plurality of parts and arranged on at least two sides of the display panel (DP).

[0041] The display area (AA) of the display panel (DP) may include multiple pixel areas (or pixels, or pixel circuits) (PA). The pixel area (PA) may include sub-pixels arranged at each intersection of multiple data lines (e.g., data lines (DL) in FIG. 3) and multiple gate lines (e.g., gate lines (GL) in FIG. 3). Each sub-pixel included in one pixel area (PA) may emit a different color. For example, the pixel area (PA) may implement blue, red, and green using three sub-pixels. However, without being limited thereto, the pixel area (PA) may include additional sub-pixels for implementing a specific color (e.g., white or yellow) in some cases.

[0042] In the pixel area (PA), a region that realizes blue may be called a blue sub-pixel region, a region that realizes red may be called a red sub-pixel region, and a region that realizes green may be called a green sub-pixel region.

[0043] In the embodiment, the pixel area (PA) may include a plurality of sub-pixels. Each of the plurality of sub-pixels may be divided into a first lens area and a second lens area that provide different viewing angles. For example, the pixel area (PA) may include a first lens area that provides light to a first range to form a first viewing angle and a second lens area that provides light to a second range to form a second viewing angle. The first range may be wider than the second range.

[0044] The non-display area (BZ) can be arranged along the periphery of the display area (AA). Various components for driving pixel circuits arranged in the pixel area (PA) can be arranged in the non-display area (BZ). For example, at least a part of a gate driver (GD) can be arranged in the non-display area (BZ). The non-display area (BZ) can be called a bezel area.

[0045] 3 shows an example of a pixel circuit of a display device according to an embodiment of the present specification. The pixel area (PA) can include multiple sub-pixels each exhibiting a different color and a pixel circuit corresponding to each of the multiple sub-pixels. Fig. 3 shows an example of a pixel circuit for one sub-pixel arranged in the pixel area (PA).

[0046] Referring to FIG. 3, the pixel circuit may include a plurality of transistors (DT, ST, ET1, ET2), a capacitor (Cst), and a plurality of light emitting elements 310 and 320.

[0047] The driving transistor DT and the capacitor Cst may be connected to the switching transistor ST, and a first electrode of the driving transistor DT may be connected to the power supply line PL.

[0048] The switching transistor (ST) may be connected to the gate line (GL) and receive a gate signal. The switching transistor (ST) may be turned on or off according to the gate signal. A first electrode of the switching transistor (ST) may be connected to the data line (DL). A second electrode of the switching transistor (ST) may be connected to the gate electrode of the driving transistor (DT). In this case, when the switching transistor (ST) is turned on, a data signal may be supplied to the gate electrode of the driving transistor (DT) via the switching transistor (ST).

[0049] The capacitor (Cst) can be disposed between the gate electrode and the second electrode of the driving transistor (DT). The capacitor (Cst) can maintain a signal, such as a data signal, applied to the gate electrode of the driving transistor (DT) for one frame.

[0050] According to the embodiment, the driving transistor (DT), the switching transistor (ST), and the capacitor (Cst) may be referred to as a driving part (DC) as components for driving the light emitting elements (e.g., the first light emitting element 310, the second light emitting element 320) to emit light, but are not limited to such a term.

[0051] The first light emitting element 310 may be connected to a first transistor ET1 that is turned on or off according to a first control signal S(k). The second light emitting element 320 may be connected to a second transistor ET2 that is turned on or off according to a second control signal P(k).

[0052] In this case, the first light emitting element 310 or the second light emitting element 320 may be connected to other components of the pixel circuit, such as a drive transistor (DT), depending on the mode. The mode may be specified by a user input or may be determined when a predetermined condition is met. For example, when a predetermined first condition is met, the first light emitting element 310 may emit light in response to a first control signal (S(k)). When a predetermined second condition is met, the second light emitting element 320 may emit light in response to a second control signal (P(k)). The first condition may include a condition predetermined for driving the first mode. The second condition may include a condition predetermined for driving the second mode.

[0053] The multiple transistors (DT, ST, ET1, ET2) in Figure 3 may include at least one of amorphous silicon, polycrystalline silicon, and an oxide semiconductor such as IGZO. The first electrode or the second electrode of the transistor may be a source electrode or a drain electrode. For example, the first electrode may be a source electrode and the second electrode may be a drain electrode. As another example, the first electrode may be a drain electrode and the second electrode may be a source electrode.

[0054] 4 shows an example of a pixel array of a display device according to an embodiment of the present disclosure, and illustrates an example of coupling a gate driving circuit and a pixel circuit.

[0055] 4, a pixel array of a display panel (e.g., the display panel (DP) of FIG. 2) may include a plurality of horizontal pixel lines (L1, L2, L3, L4). Each of the horizontal pixel lines (L1, L2, L3, L4) may include a plurality of pixels (PXL) horizontally adjacent to each other and commonly connected to a gate line (e.g., the scan line 410, the first light-emitting signal line 420). Here, the pixels (PXL) may include the sub-pixels of FIG. 2.

[0056] Here, each of the horizontal pixel lines (L1, L2, L3, L4) may refer to a plurality of pixels (PXL) arranged in one line, which are realized by horizontally adjacent pixels (PXL). The pixel array may include a first power supply line 430 that supplies a high potential power supply voltage (ELVDD) to the pixels (PXL) and a second power supply line 440 that supplies a reference voltage (Vref) to the pixels (PXL). In addition, the pixels (PXL) may be connected to a third power supply line 435 that supplies a low potential power supply voltage (ELVSS) to the pixels (PXL).

[0057] In the embodiment, the gate lines may include a scan line 410 to which a scan signal (Scan) is supplied and an emission signal line 420 to which an emission signal (EM1) is supplied. For example, any one horizontal pixel line (Ln, n=1 to 4) may include any one scan line 410(n) and any one emission signal line 420(n).

[0058] The pixel (PXL) can emit at least one color. For example, the pixel (PXL) can emit any one of red, green, blue, and white. The pixel (PXL) can constitute one unit pixel, and the color realized by the unit pixel can be determined by the emission ratio of red, green, blue, and white. Each pixel (PXL) can be connected to a scan line 410, an emission signal line 420, a first power supply line 430, a second power supply line 440, and a data line 450.

[0059] 5 and 6 show an example of a pixel circuit of a display device according to an embodiment of the present specification. Figures 5 and 6 show an example of a pixel circuit of a unit pixel (PXL) included in a pixel array.

[0060] 5, pixel circuit 500 may include eight transistors and one capacitor. At least some of the eight transistors included in pixel circuit 500 may be n-type transistors or p-type transistors. In the case of p-type transistors, a low-level voltage of each drive signal may represent a voltage that turns on the TFT, and a high-level voltage of each drive signal may represent a voltage that turns off the TFT.

[0061] Here, the low-level voltage may correspond to a pre-specified voltage lower than the high-level voltage. For example, the low-level voltage may include a voltage in the range of -8V to -12V, and the high-level voltage may correspond to a pre-specified voltage higher than the low-level voltage. For example, the high-level voltage may include a voltage in the range of 6V to 8V. According to an embodiment, the low-level voltage may be referred to as a first voltage, and the high-level voltage may be referred to as a second voltage. In such a case, the first voltage may be lower than the second voltage.

[0062] The first electrode or second electrode of a transistor described below may refer to a source electrode or a drain electrode. However, the terms first electrode and second electrode are merely terms used to distinguish between the electrodes and do not limit what each electrode corresponds to. Also, the first electrode for each electrode may not refer to the same electrode. For example, the first electrode of the first transistor (T1) may refer to the source electrode of the first transistor (T1), and the first electrode of the sixth transistor (T6) may refer to the drain electrode of the sixth transistor (T6).

[0063] In an embodiment, the driving transistor (DT) may be connected to a first transistor (T1) connected to the first light-emitting element (ED1) and a second transistor (T2) connected to the second light-emitting element (ED2). For example, the second electrode of the driving transistor (DT) may be connected to the first transistor (T1) and the second transistor (T2).

[0064] In this embodiment, the drive transistor (DT) may be connected to a first power supply line 517 that provides a high potential power supply voltage (ELVDD). For example, a first electrode of the drive transistor (DT) may be connected to the first power supply line 517. When the drive transistor (DT) is turned on, the high potential power supply voltage (ELVDD) provided via the first power supply line 517 may be transferred from the first electrode to the second electrode of the drive transistor (DT).

[0065] In the embodiment, the first transistor (T1) may be connected to at least one of the first light emitting element (ED1), the second transistor (T2), the 4-1st transistor (T41), the fifth transistor (T5), and the driving transistor (DT).

[0066] In one embodiment, a first electrode of the first transistor (T1) may be connected to at least one of the driving transistor (DT), the second transistor (T2), and the fifth transistor (T5). A second electrode of the first transistor (T1) may be connected to at least one of the fourth-first transistor (T41) and the first light-emitting element (ED1). A gate electrode of the first transistor (T1) may be connected to a first control line 510. The first transistor (T1) may be turned on or off by a first control signal (S(k)) provided via the first control line 510. When the first transistor (T1) is turned on, a voltage via the driving transistor (DT) may be input to the first light-emitting element (ED1) (e.g., the anode electrode of the first light-emitting element (ED1)).

[0067] Here, the first control signal (S(k)) may include a kth first control signal supplied to the kth column corresponding to the pixel circuit 500 being arranged in the kth column (k is a positive integer). The first control signal (S(k)) is provided by the mode controller and may control the driving (or emission) of the first light emitting element (ED1) where the first lens is arranged.

[0068] In the embodiment, the second transistor (T2) may be connected to at least one of the second light emitting element (ED2), the first transistor (T1), the fifth transistor (T5), the fourth-2nd transistor (T42), and the driving transistor (DT).

[0069] In one embodiment, a first electrode of the second transistor (T2) may be connected to at least one of the driving transistor (DT), the first transistor (T1), and the fifth transistor (T5). A second electrode of the second transistor (T2) may be connected to at least one of the second light-emitting element (ED2) and the fourth-second transistor (T42). A gate electrode of the second transistor (T2) may be connected to a second control line 520. The second transistor (T2) may be turned on or off by a second control signal (P(k)) provided via the second control line 520. When the second transistor (T2) is turned on, a voltage via the driving transistor (DT) may be input to the second light-emitting element (ED2) (e.g., the anode electrode of the second light-emitting element (ED2)).

[0070] In an embodiment, each of the first light-emitting element (ED1) and the second light-emitting element (ED2) may include a light-emitting diode. For example, each of the first light-emitting element (ED1) and the second light-emitting element (ED2) may be configured with an organic light-emitting diode.

[0071] Here, the second control signal (P(k)) may include a kth second control signal supplied to the kth column corresponding to the pixel circuit 500 being arranged in the kth column. The second control signal (P(k)) is provided by the mode controller and may control the driving (or emission) of the second light emitting element (ED2) in which the second lens is arranged.

[0072] In the embodiment, a first lens may be disposed above the first light-emitting element (ED1). The viewing angle of the region where the first light-emitting element (ED1) is disposed due to the first lens may correspond to a first value. For example, the viewing angle of the region where the first light-emitting element (ED1) is disposed may be equal to or greater than the first value. A second lens may be disposed above the second light-emitting element (ED2). The viewing angle of the region where the second light-emitting element (ED2) is disposed due to the second lens may correspond to a second value. The second value may be smaller than the first value. For example, the viewing angle of the region where the second light-emitting element (ED2) is disposed may be equal to or less than the second value.

[0073] In one embodiment, assuming that the pixel circuit 500 is disposed adjacent to the passenger seat, the region where the first light emitting element ED1 of the pixel circuit 500 is disposed may have a first viewing angle that provides light to a range corresponding to the passenger seat and the driver's seat next to the passenger seat. The region where the second light emitting element ED2 is disposed may have a second viewing angle that provides light to a range corresponding to the passenger seat.

[0074] In the embodiment, the third transistor T3 may be connected to at least one of the 4-1 transistor T41, the 4-2 transistor T42, the sixth transistor T6, and the capacitor C1. For example, a first electrode of the third transistor T3 may be connected to the sixth transistor T6 and the capacitor C1. A second electrode of the third transistor T3 may be connected to the 4-1 transistor T41 and the 4-2 transistor T42. A gate electrode of the third transistor T3 may be connected to an emission signal line 515 that supplies an emission signal EM(n). The emission signal EM(n) may correspond to the nth emission signal EM(n) supplied to the nth row, where n is a positive integer, since the pixel circuit 500 is arranged in the nth pixel row. The third transistor T3 may be turned on or off according to the emission signal EM(n). A second electrode of the third transistor T3 may be connected to a reference voltage line 511, for example, the second power supply line 440 in FIG. 4, that supplies a reference voltage Vref.

[0075] In this embodiment, the 4-1 transistor T41 may be connected to at least one of the first transistor T1, the third transistor T3, and the first light emitting element ED1. For example, a first electrode of the 4-1 transistor T41 may be connected to the third transistor T3. A second electrode of the 4-1 transistor T41 may be connected to the first transistor T1 and the first light emitting element ED1. A gate electrode of the 4-1 transistor T41 may be connected to the n-1th scan line 513. Thus, the 4-1 transistor T41 may receive the n-1th scan signal (Scan(n-1)) and be turned on or off according to the n-1th scan signal (Scan(n)).

[0076] In the embodiment, the 4-2nd transistor T42 may be connected to at least one of the second transistor T2, the third transistor T3, and the second light-emitting element ED2. For example, a first electrode of the 4-2nd transistor T42 may be connected to the third transistor T3. A second electrode of the 4-2nd transistor T42 may be connected to the second transistor T2 and the second light-emitting element ED2. A gate electrode of the 4-2nd transistor T42 may be connected to the n-1th scan line 513. Thus, the 4-2nd transistor T42 may receive the n-1th scan signal (Scan(n-1)) and be turned on or off according to the n-1th scan signal (Scan(n)).

[0077] In this embodiment, the fifth transistor T5 may be connected to at least one of the driving transistor DT, the 4-1st transistor T41, the 4-2nd transistor T42, the capacitor C1, the first transistor T1, and the second transistor T2. For example, the first electrode of the fifth transistor T5 may be connected to the driving transistor DT and the capacitor C1. The second electrode of the fifth transistor T5 may be connected to the driving transistor DT, the first transistor T1, and the second transistor T2. The gate electrode of the fifth transistor T5 may be connected to the n-1th scan line 513 that supplies a scan signal (Scan) in the n-1th row. The fifth transistor T5 may receive the n-1th scan signal (Scan(n-1)) and be turned on or off according to the n-1th scan signal (Scan(n-1)).

[0078] In this embodiment, the sixth transistor T6 may be connected to at least one of the third transistor T3 and the capacitor C1. For example, a first electrode of the sixth transistor T6 may be connected to the third transistor T3 and the capacitor C1. A second electrode of the sixth transistor T6 may be connected to a data line 516 that supplies a data voltage Vdata. A gate electrode of the sixth transistor T6 may be connected to an nth scan line 518 that supplies an nth scan signal Scan(n). The sixth transistor T6 may receive the nth scan signal Scan(n) and may be turned on or off according to the nth scan signal Scan(n). When the sixth transistor T6 is turned on, the data voltage Vdata may be transferred from the second electrode to the first electrode.

[0079] In the embodiment, the first light emitting element (ED1) and / or the second light emitting element (ED2) may be connected to a third power line 519 that supplies a low potential power supply voltage (ELVSS), for example, the third power line 435 in FIG. 4. For example, the cathode electrode of the first light emitting element (ED1) and the cathode electrode of the second light emitting element (ED2) may be connected to the third power line 519 and be supplied with the low potential power supply voltage (ELVSS).

[0080] According to an embodiment, the low potential power supply voltage may include ground (or ground voltage, 0V (volt)). For example, the cathode electrode of the first light emitting element ED1 and the cathode electrode of the second light emitting element ED2 may be supplied with a voltage corresponding to ground.

[0081] Figure 6 shows a pixel circuit 600 according to an embodiment different from that shown in Figure 5. Below, content that overlaps with that described in Figure 5 may be omitted. The pixel circuit 600 of Figure 6 may include nine transistors and one capacitor. At least some of the nine transistors included in the pixel circuit 600 may be n-type transistors or p-type transistors.

[0082] 6, the pixel circuit 600 may include a seventh transistor (T7). The seventh transistor (T7) may be connected to at least one of the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the driving transistor (DT). For example, a first electrode of the seventh transistor (T7) may be connected to at least one of the fifth transistor (T5) and the driving transistor (DT). A second electrode of the seventh transistor (T7) may be connected to at least one of the first transistor (T1) and the second transistor (T2).

[0083] In this embodiment, the gate electrode of the seventh transistor (T7) may be connected to an emission signal line 610 that provides an emission signal (EM(n)). The seventh transistor (T7) may be turned on or off based on the emission signal (EM(n)). When the seventh transistor (T7) is turned on, a voltage (or current) may be provided from the first electrode to the second electrode of the seventh transistor (T7).

[0084] FIG. 7 shows a plan view of a portion of a display device according to an embodiment of the present specification. FIG. 7 shows a plan view of a pixel area (PA) when three subpixels are arranged in the pixel area (PA). FIG. 8 shows a cross section taken along line I-I' in FIG. 7, and FIG. 9 shows a cross section taken along line II-II' in FIG. 7. Below, FIGS. 7 to 9 will be looked at together.

[0085] 7, the pixel area (PA) may include a blue sub-pixel area (BPA) that implements blue, a red sub-pixel area (RPA) that implements red, and a green sub-pixel area (GPA) that implements green. According to an embodiment, the blue sub-pixel area (BPA) may correspond to a first sub-pixel, the red sub-pixel area (RPA) may correspond to a second sub-pixel, and the green sub-pixel area (GPA) may correspond to a third sub-pixel. Each of the sub-pixels may be associated with a pixel circuit. A pixel circuit corresponding to each of the sub-pixels may be disposed.

[0086] The pixel area (PA) may include first lens areas (BWE, RWE, GWE) and second lens areas (BNE, RNE, GNE) that provide different viewing angles. The second lens area (BNE, RNE, GNE) of each pixel area (PA) may operate independently of the first lens area (BWE, RWE, GWE) of the corresponding pixel area (PA). For example, each pixel area (PA) may include a first light-emitting element 310 (e.g., the first light-emitting element 310 in FIG. 2 ) located on the first lens area (BWE, RWE, GWE) of the corresponding pixel area (PA) and a second light-emitting element 320 (e.g., the second light-emitting element 320 in FIG. 2 ) located on the second lens area (BNE, RNE, GNE) of the corresponding pixel area (PA).

[0087] The first light emitting element 310 may emit light exhibiting a specific color. For example, the first light emitting element 310 may include a first lower electrode 311, a first light emitting layer 312, and a first upper electrode 313, which are sequentially stacked on a substrate 10. The substrate 10 may include an insulating material. The substrate 10 may include a transparent material. For example, the substrate 10 may include glass or plastic.

[0088] The first lower electrode 311 may include a conductive material. The first lower electrode 311 may include a material having high reflectivity. For example, the first lower electrode 311 may include a metal such as aluminum (Al) or silver (Ag). The first lower electrode 311 may have a multi-layer structure. For example, the first lower electrode 311 may have a structure in which a reflective electrode made of a metal is located between transparent electrodes made of a transparent conductive material such as ITO or IZO.

[0089] The first light-emitting layer 312 can generate light with a brightness corresponding to the voltage difference between the first lower electrode 311 and the first upper electrode 313. For example, the first light-emitting layer 312 can include an emission material layer (EML) containing a light-emitting material. The light-emitting material can include an organic material, an inorganic material, or a hybrid material.

[0090] The first light-emitting layer 312 may have a multi-layer structure, for example, the first light-emitting layer 312 may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0091] The first upper electrode 313 may include a conductive material. The first upper electrode 313 may include a different material from the first lower electrode 311. The transmittance of the first upper electrode 313 may be higher than the transmittance of the first lower electrode 311. For example, the first upper electrode 313 may be a transparent electrode made of a transparent conductive material such as ITO or IZO. As a result, in the display device according to the embodiment of the present specification, light generated by the first light emitting layer 312 can be emitted through the first upper electrode 313.

[0092] The second light emitting element 320 may embody the same color as the first light emitting element 310. The second light emitting element 320 may have the same structure as the first light emitting element 310. For example, the second light emitting element 320 may include a second lower electrode 321, a second light emitting layer 322, and a second upper electrode 323, which are sequentially stacked on the substrate 10.

[0093] The second lower electrode 321 may correspond to the first lower electrode 311, the second light emitting layer 322 may correspond to the first light emitting layer 312, and the second upper electrode 323 may correspond to the first upper electrode 313. For example, the second lower electrode 321 may be formed for the second light emitting element 320 with the same structure as the second lower electrode 311, and the same applies to the second light emitting layer 322 and the second upper electrode 323. For example, the first light emitting element 310 and the second light emitting element 320 may be formed to have the same structure. However, this is not limited thereto, and in some cases, at least a portion of the configuration of the first light emitting element 310 and the second light emitting element 320 may be formed differently.

[0094] In an embodiment, the second light emitting layer 322 may be spaced apart from the first light emitting layer 312. As a result, in the display device according to the embodiment of the present disclosure, light emission due to leakage current may be prevented.

[0095] In the display device according to the embodiments of the present specification, only one of the first light-emitting layer 312 and the second light-emitting layer 322 can generate light according to a user's selection or a pre-specified condition.

[0096] In the embodiment, the first light emitting element 310 and the second light emitting element 320 of the pixel region (PA) may be located on a driving portion (e.g., driving portion DC in FIG. 3) of the corresponding pixel region (PA). For example, at least one insulating layer (e.g., device buffer layer 110, gate insulating layer 120, interlayer insulating layer 130, lower passivation layer 140, overcoat layer 150) may be located on the substrate 10, and the first light emitting element 310 and the second light emitting element 320 of each pixel region (PA) may be located on one of the insulating layers. As a result, in the display device according to the embodiment of the present specification, the first light emitting element 310 and the second light emitting element 320 of each pixel region (PA) may be prevented from being unnecessarily connected to the driving portion DC of the corresponding pixel region (PA).

[0097] In the embodiment, a buffer film 110, a gate insulating film 120, an interlayer insulating film 130, a lower protective film 140, and an overcoat layer 150 may be stacked on the substrate 10. The buffer film 110 may include an insulating material. For example, the buffer film 110 may include an inorganic insulating material such as silicon oxide (SiO) and silicon nitride (SiN). The buffer film 110 may have a multi-layer structure. For example, the buffer film 110 may include silicon nitride (SiN X ) and silicon oxide (SiO X ) can have a laminated structure of films made of

[0098] In an embodiment, the buffer film 110 may be located between the element substrate 10 and the driving portions DC of each pixel area (PA). The buffer film 110 may prevent contamination by the substrate 10 during the formation process of the driving portions DC. For example, the upper surface of the substrate 10 facing the driving portions DC of each pixel area (PA) may be covered with the buffer film 110. The driving portions DC of each pixel area (PA) may be located on the buffer film 110.

[0099] In an embodiment, the gate insulating film 120 may include an insulating material. For example, the gate insulating film 120 may include an inorganic insulating material such as silicon dioxide (SiO) and silicon nitride (SiN). The gate insulating film 120 may include a material having a high dielectric constant. For example, the gate insulating film 120 may include a high-K material such as hafnium oxide (HfO). The gate insulating film 120 may have a multi-layer structure.

[0100] The gate insulating film 120 may be located on the buffer film 110. The gate insulating film 120 may extend between the semiconductor layer and the gate electrode of the transistor. For example, the gate electrodes of the driving transistor (DT) and the switching transistor (ST) may be insulated from the semiconductor layers of the driving transistor (DT) and the switching transistor (ST) by the gate insulating film 120. The gate insulating film 120 may cover the first semiconductor layer and the second semiconductor layer of each pixel area (PA). The gate electrodes of the driving transistor (DT) and the switching transistor (ST) may be located on the gate insulating film 120.

[0101] The interlayer insulating film 130 may include an insulating material. For example, the interlayer insulating film 130 may include an inorganic insulating material such as silicon dioxide (SiO) and silicon nitride (SiN). The interlayer insulating film 130 may be positioned on the gate insulating film 120. The interlayer insulating film 130 may extend between the gate electrode and source electrode and between the gate electrode and drain electrode of each of the driving transistor (DT) and the switching transistor (ST). For example, the source electrode and drain electrode of each of the driving transistor (DT) and the switching transistor (ST) may be insulated from the gate electrode by the interlayer insulating film 130. The interlayer insulating film 130 may cover the gate electrodes of each of the driving transistor (DT) and the switching transistor (ST). The source electrode and drain electrode of each pixel area (PA) may be positioned on the interlayer insulating film 130. The gate insulating film 120 and the interlayer insulating film 130 may expose the source region and drain region of each semiconductor layer located in each pixel area (PA).

[0102] In the embodiment, the lower passivation layer 140 may include an insulating material. For example, the lower passivation layer 140 may include an inorganic insulating material such as silicon dioxide (SiO) and silicon nitride (SiN). The lower passivation layer 140 may be positioned on the interlayer insulating layer 130. The lower passivation layer 140 may prevent damage to the driving portion DC due to external moisture and impact. The lower passivation layer 140 may extend along surfaces of the driving transistor (DT) and the switching transistor (ST) facing the substrate 10. The lower passivation layer 140 may contact the interlayer insulating layer 130 outside the driving portion DC located in each pixel area (PA).

[0103] The overcoat layer 150 may include an insulating material. The overcoat layer 150 may include a material different from that of the lower passivation layer 140. For example, the overcoat layer 150 may include an organic insulating material. The overcoat layer 150 may be positioned on the lower passivation layer 140. The overcoat layer 150 may eliminate steps caused by the driving portions DC of each pixel area (PA). For example, the upper surface of the overcoat layer 150 facing the device substrate 10 may be a flat surface.

[0104] In an embodiment, the first transistor (ET1) may be electrically connected between the drain electrode of the driving transistor (DT) and the first lower electrode 311 of the first light-emitting element 310. The second transistor (ET2) may be electrically connected between the drain electrode of the driving transistor (DT) and the second lower electrode 321 of the second light-emitting element 320.

[0105] The first transistor (ET1) may include a first semiconductor layer 211, a first gate electrode 213, a first source electrode 215, and a first drain electrode 217. The first transistor (ET1) may have the same structure as the switching transistor (ST) and the driving transistor (DT). For example, the first semiconductor layer 211 may be located between the buffer film 110 and the gate insulating film 120, and the first gate electrode 213 may be located between the gate insulating film 120 and the interlayer insulating film 130. The first source electrode 215 and the first drain electrode 217 may be located between the interlayer insulating film 130 and the lower passivation film 140. The first gate electrode 213 may overlap a channel region of the first semiconductor layer 211. The first source electrode 215 may be electrically connected to a source region of the first semiconductor layer 211. The first drain electrode 217 may be electrically connected to a drain region of the first semiconductor layer 211.

[0106] In an embodiment, the second transistor (ET2) may include a second light emitting semiconductor layer 221, a second light emitting gate electrode 223, a second light emitting source electrode 225, and a second light emitting drain electrode 227. For example, the second light emitting semiconductor layer 221 may be located in the same layer as the first semiconductor layer 211, the second light emitting gate electrode 223 may be located in the same layer as the first gate electrode 213, and the second light emitting source electrode 225 and the second light emitting drain electrode 227 may be located in the same layer as the first source electrode 215 and the first drain electrode 217.

[0107] In an embodiment, the first transistor (ET1) can be formed simultaneously with the switching transistor (ST) and the drive transistor (DT). The first transistor (ET1) can be formed simultaneously with the second transistor (ET2).

[0108] The first light emitting element 310 and the second light emitting element 320 of each pixel area (PA) may be located on the overcoat layer 150 of the corresponding pixel area (PA). For example, the first lower electrode 311 of the first light emitting element 310 may be electrically connected to the first drain electrode 217 (or the first source electrode 215) of the first transistor (ET1) through a contact hole penetrating the lower passivation layer 140 and the overcoat layer 150, and the second lower electrode 321 of the second light emitting element 320 may be electrically connected to the second drain electrode 227 (or the second source electrode 225) of the second transistor (ET2) through a contact hole penetrating the lower passivation layer 140 and the overcoat layer 150.

[0109] The second lower electrode 321 of each pixel region (PA) may be spaced apart from the first lower electrode 311 of the corresponding pixel region (PA). For example, a bank insulating layer 160 may be located between the first lower electrode 311 and the second lower electrode 321 of each pixel region (PA). The bank insulating layer 160 may include an insulating material. For example, the bank insulating layer 160 may include an organic insulating material. The bank insulating layer 160 may include a different material from the overcoat layer 150.

[0110] The second lower electrode 321 of each pixel area (PA) may be insulated from the first lower electrode 311 of the corresponding pixel area (PA) by the bank insulating film 160. For example, the bank insulating film 160 may cover an end of the first lower electrode 311 and an end of the second lower electrode 321 located in each pixel area (PA). As a result, the display device may provide a user with an image based on the first lens area (BWE, RWE, GWE) of each pixel area (PA) where the first light emitting element 310 is located or an image based on the second lens area (BNE, RNE, GNE) of each pixel area (PA) where the second light emitting element 320 is located.

[0111] The first light emitting layer 312 and the first upper electrode 313 of the first light emitting element 310 located in each pixel area (PA) may be stacked on a portion of the corresponding first lower electrode 311 exposed by the bank insulating film 160. The second light emitting layer 322 and the second upper electrode 323 of the second light emitting element 320 located in each pixel area (PA) may be stacked on a portion of the corresponding second lower electrode 321 exposed by the bank insulating film 160. For example, the bank insulating film 160 may divide each pixel area (PA) into first light emitting areas (BE1, RE1, GE1) from which light is emitted by the first light emitting element 310 and second light emitting areas (BE2, RE2, GE2) from which light is emitted by the second light emitting element 320. The size of the divided second light emitting areas (BE2, RE2, GE2) in each pixel area (PA) may be smaller than the size of the first light emitting areas (BE1, RE1, GE1).

[0112] The second upper electrode 323 of each pixel region (PA) may be electrically connected to the first upper electrode 313 of the corresponding pixel region (PA). For example, the voltage applied to the second upper electrode 323 of the second light emitting element 320 located in each pixel region (PA) may be the same as the voltage applied to the first upper electrode 313 of the first light emitting element 310 located in the corresponding pixel region (PA). The second upper electrode 323 of each pixel region (PA) may include the same material as the first upper electrode 313 of the corresponding pixel region (PA). For example, the second upper electrode 323 of each pixel region (PA) may be formed simultaneously with the first upper electrode 313 of the corresponding pixel region (PA). The second upper electrode 323 of each pixel region (PA) may extend onto the bank insulating film 160 and directly contact the first upper electrode 313 of the corresponding pixel region (PA). The brightness of the first lens area (BWE, RWE, GWE) and the second lens area (BNE, RNE, GNE) located within each pixel area (PA) can be controlled by the driving current generated in the corresponding pixel area (PA).

[0113] An encapsulating member 800 may be positioned on the first light emitting element 310 and the second light emitting element 320 of each pixel area (PA). The encapsulating member 800 may prevent damage to the light emitting elements 310 and 320 due to external moisture and impact. The encapsulating member 800 may have a multi-layer structure. For example, the encapsulating member 800 may include a first encapsulating layer 810, a second encapsulating layer 820, and a third encapsulating layer 830, which are stacked in order. The embodiments of the present specification are not limited thereto. The first encapsulating layer 810, the second encapsulating layer 820, and the third encapsulating layer 830 may include an insulating material. The second encapsulating layer 820 may include a different material from the first encapsulating layer 810 and the third encapsulating layer 830. For example, the first encapsulating layer 810 and the third encapsulating layer 830 may be inorganic encapsulating layers including an inorganic insulating material, and the second encapsulating layer 820 may include an organic encapsulating layer including an organic insulating material. This makes it possible to more effectively prevent the light emitting elements 310 and 320 of the display device from being damaged by external moisture and impact.

[0114] A first lens 510 and a second lens 520 may be positioned on the sealing member 800 of each pixel area (PA).

[0115] The first lens 510 may be located on the first lens region (BWE, RWE, GWE) of each pixel region (PA). For example, light generated by the first light emitting element 310 of each pixel region (PA) may be emitted through the first lens 510 of the corresponding pixel region (PA). The first lens 510 may have a shape that does not restrict light in at least one lateral direction. For example, the planar shape of the first lens 510 located in each pixel region (PA) may have a bar shape extending in a first direction.

[0116] In this case, the traveling direction of light emitted from the first lens region (BWE, RWE, GWE) of the pixel region (PA) may not be limited to the first direction. For example, content (or an image) provided through the first lens region (BWE, RWE, GWE) of the pixel region (PA) may be shared with the user and people nearby in the first direction. When content is provided through the first lens region (BWE, RWE, GWE), this mode may be referred to as a first mode, as it provides content in a first viewing angle range that is wider than the second viewing angle range provided by the second lens region (BNE, RNE, GNE).

[0117] The second lens 520 may be located on the second lens area (BNE, RNE, GNE) of each pixel area (PA). Light generated by the second light-emitting element 320 of the pixel area (PA) may be emitted through the second lens 520 of the corresponding pixel area (PA). The second lens 520 may limit the traveling direction of the passing light to a first direction and / or a second direction. For example, the planar shape of the second lens 520 located in the pixel area (PA) may have a circular shape. In this case, the traveling direction of the light emitted from the second lens area (BNE, RNE, GNE) of the pixel area (PA) may be limited to the first direction and the second direction. In other words, the content provided by the second lens area (BNE, RNE, GNE) of the pixel area (PA) does not need to be shared with people around the user. When content is provided through the second lens area (BNE, RNE, GNE), it can be called the second mode, which is a mode that provides content in a second viewing angle range that is narrower than the first viewing angle range provided by the first lens area (BWE, RWE, GWE).

[0118] The first light-emitting regions (BE1, RE1, GE1) included in the first lens regions (BWE, RWE, GWE) of each pixel region (PA) may have a shape corresponding to the first lens 510 located on the first lens region (BWE, RWE, GWE) of the corresponding pixel region (PA). For example, the planar shape of the first light-emitting regions (BE1, RE1, GE1) defined in the first lens regions (BWE, RWE, GWE) of each pixel region (PA) may have a bar shape extending in a first direction. The first lens 510 located on the first lens regions (BWE, RWE, GWE) of the pixel region (PA) may have a larger size than the first light-emitting regions (BE1, RE1, GE1) included in the first lens regions (BWE, RWE, GWE) of the corresponding pixel region (PA). This may improve the efficiency of light emitted from the first light-emitting regions (BE1, RE1, GE1) of the pixel region (PA).

[0119] The second light-emitting regions (BE2, RE2, GE2) included in the second lens regions (BNE, RNE, GNE) of each pixel region (PA) may have a shape corresponding to the second lens 520 located on the second lens region (BNE, RNE, GNE) of the corresponding pixel region (PA). For example, the planar shape of the second light-emitting regions (BE2, RE2, GE2) included in the second lens regions (BNE, RNE, GNE) of the pixel region (PA) may be circular. The second lenses 520 located on the second lens regions (BNE, RNE, GNE) of the pixel region (PA) may have a size larger than the second light-emitting regions (BE2, RE2, GE2) included in the second lens regions (BNE, RNE, GNE) of the corresponding pixel region (PA). For example, the planar shape of the second light-emitting regions (BE2, RE2, GE2) located in the second lens regions (BNE, RNE, GNE) of each pixel region (PA) may be concentric with the planar shape of the second lens 520 located on the second lens region (BNE, RNE, GNE) of the corresponding pixel region (PA). In this case, the efficiency of light emitted from the second light-emitting regions (BE2, RE2, GE2) of the pixel region (PA) can be improved.

[0120] In an embodiment, the first lens area (BWE, RWE, GWE) of the pixel area (PA) may include one first light-emitting area (BE1, RE1, GE1), and the second lens area (BNE, RNE, GNE) of the pixel area (PA) may include multiple second light-emitting areas (BE2, RE2, GE2).

[0121] In an embodiment, one first lens 510 may be disposed on the first lens region (BWE, RWE, GWE) of the pixel region (PA). Multiple second lenses 520 may be disposed on the second lens region (BNE, RNE, GNE) of the pixel region (PA).

[0122] In one embodiment, the second light-emitting regions (BE2, RE2, GE2) included in the second lens regions (BNE, RNE, GNE) of the pixel region (PA) can be driven separately for each subpixel region. The second light-emitting regions included in one subpixel region (e.g., the second light-emitting region (BE2), the second light-emitting region (RE2), or the second light-emitting region (GE2)) can be driven simultaneously.

[0123] In the embodiment, one second lower electrode 321 may be disposed on the second lens region (BNE, RNE, GNE) of each pixel region (PA). Between the second light-emitting regions (BE2, RE2, GE2), a bank insulating film 160 may be disposed between the second lower electrode 321 and the second light-emitting layer 322. Between the second light-emitting regions (BE2), between the second light-emitting regions (RE2), and / or between the second light-emitting regions (GE2), the bank insulating film 160 may be disposed between the second lower electrode 321 and the second light-emitting layer 322. Between the second light-emitting regions (BE2, RE2, GE2) of each second lens region (BNE, RNE, GNE), the second light-emitting layer 322 may be separated from the second lower electrode 321 by the bank insulating film 160. In this case, the light-emitting efficiency of the second light-emitting regions (BE2, RE2, GE2) may be improved.

[0124] In an embodiment, the area of ​​each of the second light-emitting regions (BE2, RE2, GE2) located in the second lens region (BNE, RNE, GNE) of the pixel region (PA) may be set to a specific value. For example, the areas of each of the second light-emitting regions (BE2, RE2, GE2) located in the second lens region (BNE, RNE, GNE) may be implemented to be equal to each other. The area of ​​each of the second light-emitting regions (BE2, RE2, GE2) located in the second lens region (BNE, RNE, GNE) of the pixel region (PA) may be the same as the area of ​​the second light-emitting region (BE2, RE2, GE2) included in the second lens region (BNE, RNE, GNE) of an adjacent pixel region (PA).

[0125] In an embodiment, the number of second light-emitting regions may vary for each subpixel region (RPA, GPA, BPA). For example, the number of second light-emitting regions (BE2) defined in the second lens region (BNE) of the blue subpixel region (BPA) may be greater than the number of second light-emitting regions (RE2) defined in the second lens region (RNE) of the red subpixel region (RPA). The number of second light-emitting regions (RE2) defined in the second lens region (RNE) of the red subpixel region (RPA) may be greater than the number of second light-emitting regions (GE2) defined in the second lens region (GNE) of the green subpixel region (GPA). In this case, the efficiency deviation of the second light-emitting element 320 located in the second lens region (BNE, RNE, GNE) of the pixel region (PA) can be compensated for by the number of second light-emitting regions (BE2, RE2, GE2) defined in the second lens region (BNE, RNE, GNE) of each pixel region (PA).

[0126] In an embodiment, the sizes of the first light-emitting regions (BE1, RE1, GE1) in each sub-pixel region (RPA, GPA, BPA) may be different from each other. For example, the first light-emitting region (BE1) in the blue sub-pixel region (BPA) may have a different size from the first light-emitting region (RE1) in the red sub-pixel region (RPA), and may have a different size from the first light-emitting region (GE1) in the green sub-pixel region (GPA). The size of the first light-emitting region (BE1) in the blue sub-pixel region (BPA) may be larger than the size of the first light-emitting region (RE1) in the red sub-pixel region (RPA). The size of the first light-emitting region (RE1) in the red sub-pixel region (RPA) may be larger than the size of the first light-emitting region (GE1) in the green sub-pixel region (GPA). As a result, in the display device according to the embodiments of this specification, the efficiency deviation of the first light-emitting element 310 located on the first lens region (BWE, RWE, GWE) of each pixel region (PA) can be compensated for by the size of the first light-emitting region (BE1, RE1, GE1) defined within the first lens region (BWE, RWE, GWE) of each pixel region (PA).

[0127] In the embodiment, a lens protection layer 600 may be positioned on the first lens 510 and the second lens 520 of the pixel area (PA). The lens protection layer 600 may include an insulating material. For example, the lens protection layer 600 may include an organic insulating material. The refractive index of the lens protection layer 600 may be smaller than the refractive index of the first lens 510 and the second lens 520 positioned in each pixel area (PA). As a result, in the display device according to the embodiment of the present specification, light passing through the first lens 510 and the second lens 520 of each pixel area (PA) may not be reflected toward the substrate 10 due to the difference in refractive index between the lens protection layer 600 and the lens protection layer 600.

[0128] 10 is a diagram showing a gate drive circuit of a display device according to an embodiment of the present specification. Fig. 10 shows a functional block diagram of an emission driver 1000 included in the gate drive circuit. The emission driver 1000 can generate a light emission signal (e.g., light emission signal (EM(n))).

[0129] Referring to FIG. 10, the emission driver 1000 may be implemented as a gate shift register consisting of a plurality of stages (e.g., a first stage (ST1), a second stage (ST2), a third stage (ST3), and a fourth stage (ST4)). The stages may be formed in a gate-in-panel (GIP) manner, in which the stages are arranged within a panel. However, the present invention is not limited to this, and the stages may also be arranged separately from the panel.

[0130] In the embodiment, each of the multiple stages (ST1 to ST4) can be activated in sequence in response to a start signal to output a light emission signal. The first stage (ST1) can refer to the stage arranged at the top of the emission driver. The second stage (ST2) to fourth stage (ST4) can refer to the stages arranged in sequence following the first stage (ST1).

[0131] In this embodiment, the first stage (ST1) is activated by an external start signal (EVST), and the second stage (ST2) and the remaining stages (e.g., the third stage (ST3) and the fourth stage (ST4)) can be activated according to a signal from the previous stage, such as a light-emitting signal. The signal from the previous stage that activates the operation of the next stage can be a carry signal (CRY) as an internal start signal. Here, the "previous stage" can refer to a stage located above a reference stage that generates a light-emitting signal whose phase is earlier than the light-emitting signal output from the reference stage.

[0132] In this embodiment, the plurality of stages (ST1 to ST4) receive an external start signal (EVST), a first clock signal (ECLK1), and a second clock signal (ECLK2) from a level shifter (not shown) to output light-emitting signals. The external start signal (EVST), the first clock signal (ECLK1), and the second clock signal (ECLK2) can all swing between a gate-off voltage (VGH) and a gate-on voltage (VGL). The gate-off voltage may be higher or lower than the gate-on voltage depending on the type of transistor. For example, if the transistor to which the gate-off voltage is input is an n-type, the gate-off voltage may be higher than the gate-on voltage. Alternatively, if the transistor to which the gate-off voltage is input is a p-type, the gate-off voltage may be lower than the gate-on voltage.

[0133] In the embodiments of the present specification, the gate-off voltage (VGH) may be referred to as a gate high voltage, and the gate-on voltage (VGL) may be referred to as a gate low voltage, but is not limited thereto, and the gate-off voltage (VGH) may be referred to as a gate low voltage, and the gate-on voltage (VGL) may be referred to as a gate high voltage depending on the type of transistor.

[0134] An external start signal (EVST) is input to the first stage (ST1), and a first clock signal (ECLK1) and a second clock signal (ECLK2) may be input to all stages (ST1 to ST4, ...). The first clock signal (ECLK1) and the second clock signal (ECLK2) may have opposite phases. According to an embodiment, in order for each stage connected in a cascade configuration to operate normally, the input positions of the first clock signal (ECLK1) and the second clock signal (ECLK2) may be set to be opposite in odd-numbered stages and even-numbered stages. For example, if the first clock signal (ECLK1) is input to a first terminal and the second clock signal (ECLK2) is input to a second terminal in odd-numbered stages, the first clock signal (ECLK1) may be input to a second terminal and the second clock signal (ECLK2) may be input to a first terminal in even-numbered stages.

[0135] In the embodiment, each of the stages (ST1 to ST4, ...) can activate the operation of the node (Q) by a start signal applied to the start terminal for each frame. Here, activating a node can mean applying a gate low voltage (VGL) or a voltage equivalent thereto to the node. Inactivating a node can mean applying a gate high voltage (VGH) or a voltage equivalent thereto to the node. The gate low voltage (VGL) can be referred to as a gate-on voltage, and the gate high voltage (VGH) can be referred to as a gate-off voltage.

[0136] According to the embodiment, as shown in the figure, each stage (ST1 to ST4, ...) can receive a gate high potential voltage (VGH) and a gate low potential voltage (VGL) from an external power supply unit. The gate high potential voltage (VGH) can be preset to any one value between 20V and 30V, for example, and the gate low potential voltage (VGL) can be preset to any one value between -10V and 0V, but is not limited thereto.

[0137] In an embodiment, the gate low potential voltage (VGL) can be provided via a first voltage line providing a voltage of a first value. According to an embodiment, the first voltage line can be referred to as a low potential line. The gate high potential voltage (VGH) can be provided via a second voltage line providing a voltage of a second value higher than the first value. According to an embodiment, the second voltage line can be referred to as a high potential line.

[0138] The gate driving circuit according to the embodiment of the present specification may further include a scan driver. The scan driver may generate scan signals (e.g., n-th scan signal (Scan(n)), n-1-th scan signal (Scan(n-1))). The scan driver may correspond to the emission driver of FIG. 10. For example, the scan driver may include configurations corresponding to the functional block diagrams of the emission drivers.

[0139] In an embodiment, the scan driver and the emission driver may be connected in parallel. The scan driver and the emission driver may be connected in parallel and arranged vertically or horizontally, but are not limited thereto.

[0140] 11 to 13 are diagrams illustrating a display device according to an embodiment of the present specification. Figures 11 and 12 show how to change the size of a first region that operates in a first mode and a second region that operates in either the first mode or the second mode. Figure 13 shows the flow of signals resulting from changes in the regions of Figures 11 and 12.

[0141] 11, a display device 1100 may include a mode control unit 1110, a gate driving circuit 1120, a pixel circuit 1150, a first lens, and a second lens. The first lens and the second lens may be disposed on the pixel circuit for each pixel circuit.

[0142] In the embodiment, the mode controller 1110 may generate a first control signal (S(k)) (k is a natural number) and a second control signal (P(k)) using a gate-off voltage (VGH) and a gate-on voltage (VGL). For example, when the mode controller 1110 operates a pixel circuit to which the first control signal (S(k)) is supplied in a first mode, the mode controller 1110 may control the first control signal (S(k)) to correspond to the gate-on voltage (VGL) and the second control signal (P(k)) to correspond to the gate-off voltage (VGH) and provide the control signal. When the mode controller 1110 operates a pixel circuit to which the first control signal (S(k)) is supplied in a second mode, the mode controller 1110 may control the first control signal (S(k)) to correspond to the gate-off voltage (VGH) and the second control signal (P(k)) to correspond to the gate-on voltage (VGL) and provide the control signal.

[0143] According to an embodiment, the display device 1100 may further include a power supply unit that generates a gate-off voltage (VGH) and a gate-on voltage (VGL). In this case, the gate-off voltage (VGH) and the gate-on voltage (VGL) may be generated by the power supply unit and provided to the mode control unit 1110. The gate-off voltage (VGH) and the gate-on voltage (VGL) may also be provided to the gate driving circuit 1120.

[0144] In an embodiment, the gate drive circuit 1120 can generate a light-emitting signal, such as the light-emitting signal (EM(n)) in FIGS. 5 and 6. The gate drive circuit 1120 can generate the light-emitting signal using a gate-off voltage (VGH) and a gate-on voltage (VGL). The gate drive circuit 1120 can provide the light-emitting signal to the pixel circuit 1150.

[0145] In this embodiment, the gate driving circuit 1120 may be arranged on at least one side of the active area 1130 in which the pixel circuits 1150 are arranged. For example, the gate driving circuit 1120 may be divided into two parts as shown in the figure and arranged to face each other on the left and right sides of the active area 1130. However, this is not limiting, and the gate driving circuit 1120 may be arranged in at least a portion of the edge of the active area 1130.

[0146] In the embodiment, the gate driving circuit 1120 may be connected to the mode control unit 1110 and / or the power supply unit. For example, the gate driving circuit 1120 may be connected to the power supply unit and receive a gate-off voltage (VGH) and a gate-on voltage (VGL) from the power supply unit. The gate driving circuit 1120 may generate signals related to driving the pixel circuit 1150, such as light-emitting signals and / or scan signals, using the gate-off voltage (VGH) and the gate-on voltage (VGL). The gate driving circuit 1120 may provide the generated signals to the pixel circuit 1150.

[0147] In an embodiment, the active area 1130 may include an area that emits light by disposing the pixel circuit 1150. Although Fig. 11 shows an example in which the pixel circuit 1150 is disposed within the active area 1130, the present invention is not limited to this, and the active area may also be disposed within the pixel circuit 1150, or other configurations may be included within the active area.

[0148] In an embodiment, the active area 1130 may include a first area 1101 and a second area 1102. The first area 1101 may include an area that can operate in a first mode. The second area 1102 may include an area that can operate in either the first mode or the second mode. For example, the first area 1101 may include an area that is fixed to operate in the first mode. The second area 1102 may include an area that can dynamically operate in either the first mode or the second mode based on a user input.

[0149] Here, the first mode may include a mode having a first viewing angle when emitting light. The second mode may include a mode having a second viewing angle when emitting light. The second viewing angle may be smaller than the first viewing angle. In this case, light may be provided to a wider area in the first mode than in the second mode.

[0150] 11 is a diagram showing an example in which a first region 1101 has a larger area than a second region 1102. For example, the first region 1101 may include four pixel circuits 1111 to 1114. The second region 1102 may include two pixel circuits 1115 and 1116. The pixel circuits 1111 to 1116 included in the first region 1101 and the second region 1102 may be separated from each other and connected to a mode control unit 1110.

[0151] In an embodiment, the display device 1100 may include an inactive area in addition to the active area 1130. The inactive area may correspond to an area surrounding the active area 1130. According to an embodiment, the active area 1130 may be a display area, and the inactive area may be a non-display area, but is not limited to such terms.

[0152] In an embodiment, the mode control unit 1110 can provide control signals to the pixel circuits 1150. The mode control unit 1110 can provide control signals to each of the pixel circuits 1150, such as a first control signal (S(k)) and a second control signal (P(k)).

[0153] 11, the first control signals provided to the first to sixth pixel circuits 1111 to 1116 can be referred to as the 1-1 control signal (S(1)), the 1-2 control signal (S(2)), the 1-3 control signal (S(3)), the 1-4 control signal (S(4)), the 1-5 control signal (S(5)), and the 1-6 control signal (S(6)) in the order in which the pixel circuits are arranged. The second control signals provided to the first to sixth pixel circuits 1111 to 1116 can be referred to as the 2-1 control signal (P(1)), the 2-2 control signal (P(2)), the 2-3 control signal (P(3)), the 2-4 control signal (P(4)), the 2-5 control signal (P(5)), and the 2-6 control signal (P(6)) in the order in which the pixel circuits are arranged.

[0154] In the embodiment, the mode control unit 1110 can control the mode operation of the pixel circuits 1150 by providing a first control signal (S(k), k=1 to 6) or a second control signal (P(k), k=1 to 6) via a control line 1151 connected to each of the pixel circuits 1150. For example, the mode control unit 1110 can provide a first control signal to a pixel circuit that is to operate in a first mode, and a second control signal to a pixel circuit that is to operate in a second mode. In this way, the mode control unit 1110 can control the mode operation of the pixel circuits 1150.

[0155] In an embodiment, operation in the first mode or the second mode can be determined by a region including pixel circuits, e.g., the first region or the second region, and user input. For example, pixel circuits included in the first region can operate in the first mode. Pixel circuits included in the second region can operate in the first mode or the second mode depending on user input.

[0156] In one embodiment, the first pixel circuit 1111 to the fourth pixel circuit 1114 can be included in the first region 1101. Each of the first pixel circuits 1111 to the fourth pixel circuits 1114 can be provided with a first lens and a second lens. By providing the first pixel circuits 1111 to the fourth pixel circuits 1114 in the first region 1101, the first pixel circuits 1111 to the fourth pixel circuits 1114 can operate in a first mode. In this case, the first pixel circuits 1111 to the fourth pixel circuits 1114 can emit light through a first lens corresponding to the first mode. For example, the first pixel circuits 1111 to the fourth pixel circuits 1114 can emit light using a first light-emitting element under the first lens, such as the first light-emitting element (ED1) in FIG. 5. While the first pixel circuits 1111 to the fourth pixel circuits 1114 are included in the first region, the second light-emitting element under the second lens, such as the second light-emitting element (ED2) in FIG. 5, may not operate.

[0157] In one embodiment, the first pixel circuit 1111 may be connected to a first control line 1151 that provides a first control signal (S(1)). The first pixel circuit 1111 may receive the first control signal (S(1)) via the first control line 1151.

[0158] According to the embodiment, the first pixel circuit 1111 to the fourth pixel circuit 1114 included in the first region 1101 can operate in the same manner as the above-described first pixel circuit 1111. For example, as shown in the figure, the second pixel circuit 1112 to the fourth pixel circuit 1114 are each connected to a corresponding first control line, for example, the 1-2 control line to the 1-4 control line, and can receive the 1-2 control signal (S(2)) to the 1-4 control signal (S(4)) from each.

[0159] In one embodiment, the fifth pixel circuit 1115 and the sixth pixel circuit 1116 can be included in the second region 1102. A first lens and a second lens can be disposed above the fifth pixel circuit 1115 and the sixth pixel circuit 1116, respectively. By disposing the fifth pixel circuit 1115 and the sixth pixel circuit 1116 in the second region 1102, the fifth pixel circuit 1115 and the sixth pixel circuit 1116 can operate in a first mode or a second mode. In such a case, the fifth pixel circuit 1115 and the sixth pixel circuit 1116 can emit light through the first lens corresponding to the first mode or the second lens corresponding to the second mode. For example, when operating in the first mode, the fifth pixel circuit 1115 and the sixth pixel circuit 1116 can emit light using a first light-emitting element under the first lens, such as the first light-emitting element (ED1) in FIG. 5 . When operating in the second mode, the fifth pixel circuit 1115 and the sixth pixel circuit 1116 can emit light using the second light-emitting element under the second lens, for example, the second light-emitting element (ED2) in FIG.

[0160] In the embodiment, the pixel circuits 1150, for example, the first pixel circuit 1111 to the sixth pixel circuit 1116, can operate in a first mode in which the viewing angle corresponds to a first value based on the first control signal (S(k), k=1 to 6) corresponding to the gate-on voltage (VGL) and the second control signal (P(k), k=1 to 6) corresponding to the gate-off voltage (VGH). The pixel circuits 1150, for example, the fifth pixel circuit 1115 and the sixth pixel circuit 1116, can operate in a second mode in which the viewing angle corresponds to a second value based on the first control signal (S(5), S(6)) corresponding to the gate-off voltage (VGH) and the second control signal (P(5), P(6)) corresponding to the gate-on signal.

[0161] 11 shows the pixel circuits 1150 arranged in the same row for ease of explanation, but is not limited to this. The pixel circuits 1150 can be arranged in a matrix to form a row and a column. For examples of pixel circuits arranged in a matrix, see FIGS. 14 and 18.

[0162] In an embodiment, the display device 100 is disposed in at least a portion of a vehicle and can provide at least one content. The vehicle can include a driving area where a user who controls the vehicle is located and a general area where the user's passengers are located. The first area 1101 or the pixel circuits included in the first pixel area 1101 (e.g., the first pixel circuit 1111, the second pixel circuit 1112, the third pixel circuit 1113, and the fourth pixel circuit 1114) can be disposed adjacent to the driving area. The second area 1102 or the pixel circuits included in the second area 1102 (e.g., the fifth pixel circuit 1115 and the sixth pixel circuit 1116) can be disposed adjacent to the general area.

[0163] In one embodiment, when the first region 1101 operates in a first mode and the second region operates in a second mode, the first region 1101 can provide content (or light) to all users around the display device 1100. Meanwhile, the second region 1102 can provide content to users within a specific distance range from the display device 1100. The range in which content is provided by the second region 1102 may be narrower than the range in which content is provided by the first region 1101.

[0164] Fig. 12 is a diagram showing an example in which the sizes of the first area 1101 and the second area 1102 in Fig. 11 are variable. Hereinafter, in Fig. 12, content that overlaps with the content explained in Fig. 11 may be omitted.

[0165] 12, a display device 1200 may be divided into a first region 1201 and a second region 1202. In an embodiment, the active area of ​​the display device 1200 may include the first region 1201 and the second region 1202.

[0166] The first region 1201 may include a region operating in a first mode, and the second region 1202 may include a region operating in either the first mode or the second mode. The first region 1201 in Figure 12 may have a reduced area compared to the first region 1101 in Figure 11. The second region 1202 in Figure 12 may have an increased area compared to the second region 1102 in Figure 12. As an example, the first region 1201 may include two pixel circuits. The second region 1202 may include four pixel circuits.

[0167] In the embodiment of the present specification, the mode control unit 1210 may control the mode of each pixel circuit by connecting to each pixel circuit arranged in the display device 1200 .

[0168] In one embodiment of the present specification, the mode control unit 1201 may control the pixel circuits included in the first region 1201 to operate in the first mode by reducing the area of ​​the first region 1201. The pixel circuits included in the first region 1201 may not operate in the second mode based on the control of the mode control unit 1201. For example, the mode control unit 1201 may provide signals for operating in the first mode, e.g., first control signals (S(1), S(2)), to the pixel circuits included in the first region 1201 so that the first light-emitting element is turned on. The mode control unit 1201 may provide signals for operating in the second mode, e.g., second control signals (P(1), P(2)), so that the second light-emitting element is turned off.

[0169] In one embodiment, mode control unit 1201 can control pixel circuits included in second region 1202 to operate in the first mode or the second mode by increasing the area of ​​second region 1202. Mode control unit 1201 can provide signals for operating in the first mode or the second mode, for example, first control signals (S(3) to S(6)) or second control signals (P(3) to P(6)), to the pixel circuits included in second region 1202 based on an input.

[0170] In one example, the input related to the operation of the first mode or the second mode may include a pre-specified input provided by a user of the display device 1200. In another example, the input may include an input generated depending on a state of the display device 1200. For example, the input may include an input generated in response to a state in which the display device 1200 is moving or a state in which the moving speed of the display device 1200 exceeds a predetermined speed. In this case, information regarding the state in which the display device 1200 is moving or a state in which the moving speed of the display device 1200 exceeds a pre-specified speed may be acquired via another component included in the display device 1200, such as a sensor.

[0171] For example, when the display device 1200 detects a moving state, an input for operating in the second mode may be generated and provided to the mode control unit. As another example, when a state in which the moving speed of the display device 1200 exceeds a certain value is detected, an input for operating in the second mode may be generated and provided to the mode control unit.

[0172] FIG. 13 shows an example of signals provided by the mode control unit when the sizes of the first and second regions are changed from FIG. 11 to FIG.

[0173] In the embodiment, the mode control unit, for example, the mode control unit 1110 in FIG. 11 or the mode control unit 1210 in FIG. 12, can control the first control signal (S(k), k=1 to 6) and the second control signal (P(k), k=1 to 6) using the gate-off voltage (VGH) and the gate-on voltage (VGL). For example, the mode control unit can control the pixel circuit to operate in the first mode or the second mode by controlling the first control signal (S(k)) and the second control signal (P(k)) so that they correspond to the gate-off voltage (VGH) or the gate-on voltage (VGL), respectively.

[0174] In the embodiment, assuming that all transistors included in the pixel circuit are p-type, the mode controller may provide a first control signal (S(k)) corresponding to a gate-on voltage (VGL) to a first control line connected to the pixel circuit included in the first region. The mode controller may provide a second control signal (P(k)) corresponding to a gate-off voltage (VGH) to a second control line connected to the pixel circuit included in the first region. In this case, the transistor to which the first control signal (S(k)) is input may be turned on, and the transistor to which the second control signal (P(k)) is input may be turned off. The pixel circuit included in the first region may operate in the first mode by emitting light from a first light emitting element (LED1) connected to a transistor to which the first control signal (S(k)) is input, for example, the first transistor (T1) of FIG. 5.

[0175] In the embodiment, assuming that all transistors included in the pixel circuit are p-type, the mode controller 1110, 1210 may provide a first control signal (S(k)) corresponding to a gate-off voltage (VGH) to a first control line connected to the pixel circuit included in the second region. The mode controller 1110, 1210 may provide a second control signal (P(k)) corresponding to a gate-on voltage (VGL) to a second control line connected to the pixel circuit included in the second region. In this case, the transistor to which the first control signal (S(k)) is input may be turned off, and the transistor to which the second control signal (P(k)) is input may be turned on. The pixel circuit included in the second region may operate in the second mode by emitting light from a second light emitting element (LED2) connected to a transistor to which the second control signal (P(k)) is input, for example, the second transistor (T2) of FIG. 5.

[0176] Referring to FIG. 13, the mode control units 1110 and 1210 can individually control the 1-1 to 1-6 control signals (S(1) to S(6)) and the 2-1 to 2-6 control signals (P(1) to P(6)).

[0177] 11, when the first to fourth pixel circuits 1111 to 1114 are included in the first region 1101, the mode control unit 1110 can control the 1-1 to 1-4 control signals (S(1) to S(4)) to correspond to the gate-on signal (VGL). The mode control unit 1110 can control the 2-1 to 2-4 control signals (P(1) to P(4)) to correspond to the gate-off voltage (VGH).

[0178] For example, when the fifth and sixth pixel circuits 1115 and 1116 are included in the second region 1102 and operate in the second mode, the mode control unit 1110 may control the first-fifth and first-sixth control signals (S(5) to S(6)) to correspond to the gate-off voltage (VGH). The mode control unit 1110 may control the second-fifth and second-sixth control signals (P(5) to P(6)) to correspond to the gate-on voltage (VGL).

[0179] As another example, when the fifth and sixth pixel circuits 1115 and 1116 are included in the second region 1102 and operate in the first mode, the mode control unit 1110 may control the first-fifth and first-sixth control signals (S(5) to S(6)) to correspond to the gate-on voltage (VGL). The mode control unit 1110 may control the second-fifth and second-sixth control signals (P(5) to P(6)) to correspond to the gate-off voltage (VGH).

[0180] In an embodiment, the mode control units 1110 and 1210 may receive a region change input. For example, the mode control units 1110 and 1210 may receive a region change input that changes the first region 1101 of FIG. 11 to the first region 1201 of FIG. 12 and changes the second region 1102 of FIG. 11 to the second region 1202 of FIG. 12. If the time point at which the region change input is received corresponds to the first viewpoint 1310, the mode control unit may change the first control signal (S(k)) and / or the second control signal (P(k)) of at least some of the first to sixth pixel circuits 1111 to 1116 based on the first viewpoint 1310.

[0181] As an example, as shown in FIG. 12, the mode control unit 1210 may receive a region change input to cause the first region 1201 to include the first pixel circuit and the second pixel circuit and the second region 1202 to include the third to sixth pixel circuits. The region change input may further include an input to cause the second region to operate in a second mode. In this case, the mode control unit 1210 may control the 1-1 and 1-2 control signals (S(1) to S(2)) of the first pixel circuit and the second pixel circuit to correspond to the gate-on voltage (VGL). The mode control unit 1210 may control the 2-1 and 2-2 control signals (P(1) to P(2)) to correspond to the gate-off voltage (VGH). The mode control unit may control the 1-3 to 1-6 control signals (S(3) to S(6)) of the third to sixth pixel circuits to correspond to the gate-off voltage (VGH). The mode control unit 1210 can control the 2-3 and 2-6 control signals (P(3) to P(6)) to correspond to the gate-on voltage (VGL).

[0182] 13, a mode controller according to an embodiment of the present disclosure may provide first control signals (e.g., 1-1 control signal to 1-6 control signal) and second control signals (e.g., 2-1 control signal to 2-6 control signal) to each pixel circuit. The mode controller may provide the first control signals and the second control signals to the pixel circuits via different lines. As a result, the display device may vary the first and second regions by controlling the first and second control signals for each pixel circuit.

[0183] The display device according to the embodiments of the present specification may provide signals for controlling the first and second light emitting elements through a mode control unit, thereby minimizing the size of a bezel in which a gate driving circuit of the display device is disposed.

[0184] According to an embodiment, the mode control unit can be disposed on a printed circuit board. The printed circuit board can be made of a flexible material. In one embodiment, the printed circuit board can be bent to accommodate the size of the lower bezel and bend to the rear surface of the display panel. In one embodiment, the mode control unit can be mounted on the printed circuit board together with other components of the display device, such as a data driver and / or a timing controller.

[0185] 14 is a diagram illustrating a circuit connection relationship of a display device according to an embodiment of the present disclosure. For convenience of explanation, FIG. 14 exemplarily illustrates a first pixel circuit 1401, a second pixel circuit 1402, an eleventh pixel circuit 1411 arranged in the same column as the first pixel circuit 1401, and a twelfth pixel circuit 1412 arranged in the same column as the second pixel circuit 1402.

[0186] 14, the first pixel circuit 1401 and the second pixel circuit 1402 may be arranged in the nth row, i.e., row n. The eleventh pixel circuit 1411 and the twelfth pixel circuit 1412 may be arranged in the n+1th row. The first pixel circuit 1401 and the eleventh pixel circuit 1411 may be arranged in the kth column, i.e., column k. The second pixel circuit 1402 and the twelfth pixel circuit 1412 may be arranged in the k+1th column.

[0187] In this embodiment, the first pixel circuit 1401 , the second pixel circuit 1402 , the eleventh pixel circuit 1411 , and the twelfth pixel circuit 1412 may be connected to a mode control unit 1420 and a gate driving circuit 1430 .

[0188] In one embodiment, the first pixel circuit 1401 and the second pixel circuit 1402 may be connected to a first stage of the gate drive circuit 1430. For example, the third transistor (T3) and the seventh transistor (T7) of the first pixel circuit 1401 and the second pixel circuit 1402 may be connected to the first stage of the gate drive circuit 1430. The first stage may be configured to provide a first light-emitting signal (EM1) corresponding to the nth row. The eleventh pixel circuit 1411 and the twelfth pixel circuit 1412 may be connected to a second stage of the gate drive circuit 1430. For example, the third transistor (T3) and the seventh transistor (T7) of the eleventh pixel circuit 1411 and the twelfth pixel circuit 1412 may be connected to the second stage of the gate drive circuit 1430. The second stage may be configured to provide a second light-emitting signal (EM2) corresponding to the n+1th row.

[0189] In one embodiment, the first pixel circuit 1401 and the second pixel circuit 1402 can be connected in parallel. For example, the first pixel circuit 1401 and the second pixel circuit 1402 can be connected in parallel to a first light-emitting signal line that provides a first light-emitting signal (EM1). The third transistor (T3) and the seventh transistor (T7) of the first pixel circuit 1401 and the second pixel circuit 1402 can be connected in parallel to the first light-emitting signal line. The eleventh pixel circuit 1411 and the twelfth pixel circuit 1412 can be connected in parallel. For example, the eleventh pixel circuit 1411 and the twelfth pixel circuit 1412 can be connected in parallel to a second light-emitting signal line that provides a second light-emitting signal (EM2). The third transistor (T3) and the seventh transistor (T7) of the eleventh pixel circuit 1411 and the twelfth pixel circuit 1412 can be connected in parallel to the second light-emitting signal line.

[0190] In one embodiment, the first pixel circuit 1401 and the eleventh pixel circuit 1411 may be connected to a first controller of the mode controller 1420. The first controller may include a configuration for providing a first-1 control signal (S(1)) and / or a second-1 control signal (P(1)). The second pixel circuit 1402 and the twelfth pixel circuit 1412 may be connected to a second controller of the mode controller 1420. The second controller may include a configuration for providing a first-2 control signal (S(2)) and a second-2 control signal (P(2)).

[0191] Here, the first controller can control the 1-1 control signal (S(1)) and / or the 2-1 control signal (P(1)) using the gate-off voltage (VGH) and the gate-on voltage (VGL). The second controller can control the 1-2 control signal (S(2)) and / or the 2-2 control signal (P(2)) using the gate-off voltage (VGH) and the gate-on voltage (VGL).

[0192] In one embodiment, the first pixel circuit 1401 and the eleventh pixel circuit 1411 can be connected in parallel. For example, the first pixel circuit 1401 and the eleventh pixel circuit 1411 can be connected in parallel to a first control line or a first controller that provides the first-1 control signal (S(1)). The first transistor (T1) of each of the first pixel circuit 1401 and the eleventh pixel circuit 1411 can be connected in parallel to a first control line or a first controller that provides the first-1 control signal (S(1)). The first pixel circuit 1401 and the eleventh pixel circuit 1411 can be connected in parallel to a first control line or a first controller that provides the second-1 control signal (P(1)). The second transistor (T2) of each of the first pixel circuit 1401 and the eleventh pixel circuit 1411 can be connected in parallel to a first control line or a first controller that provides the second-1 control signal (P(1)).

[0193] In one embodiment, the second pixel circuit 1402 and the twelfth pixel circuit 1412 can be connected in parallel. For example, the second pixel circuit 1402 and the twelfth pixel circuit 1412 can be connected in parallel to a first-second control line or a second controller that provides a first-second control signal (S(2)). The second pixel circuit 1402 and the twelfth pixel circuit 1412 can be connected in parallel to a second-second control line or a second controller that provides a second-second control signal (P(2)).

[0194] The mode control unit 1420 according to the embodiment of the present specification can individually or independently control the pixel circuits by being connected to each of the pixel circuits, for example, the first pixel circuit 1401, the second pixel circuit 1402, the eleventh pixel circuit 1411, and the twelfth pixel circuit 1412, as shown in the figure. Thus, when the mode control unit receives change information for the first region or the second region, it can control the operation of each pixel circuit to correspond to the change information.

[0195] In the embodiment, the sizes of the first and second regions of the display device can be changed horizontally. In this regard, it has been confirmed through Figures 11 to 14 that the pixel circuits arranged in each column can be connected to the same control line. The mode control unit can vary the sizes (or ranges) of the first and second regions by arranging and connecting the first and second control lines for each column.

[0196] In another embodiment, the first and second regions of the display device may have a fixed size and may be switched between each other. For example, the first region may be switched to the second region and the second region may be switched to the first region to operate the display device. For more detailed explanations, see Figures 15 to 18.

[0197] 15 to 17 are diagrams illustrating a display device according to another embodiment of the present specification. Figures 15 and 16 show an example of switching between a first region operating in a first mode and a second region operating in either the first mode or the second mode. Figure 17 shows a signal flow corresponding to the region switching in Figures 15 and 16.

[0198] 15, a first region 1501 can operate in a first mode, and a second region 1502 can operate in a second mode. Each of the first region 1501 and the second region 1502 can include a plurality of pixel circuits.

[0199] In this embodiment, when the plurality of pixel circuits included in the first region 1501 are a first pixel circuit 1531 and a second pixel circuit 1532, the first pixel circuit 1531 and the second pixel circuit 1532 may be connected to a first-first control line 1511 that provides a first-first control signal (S(1)). The first pixel circuit 1531 and the second pixel circuit 1532 may be connected to a second-first control line 1521 that controls a second-first control signal (P(1)).

[0200] In an embodiment, when the plurality of pixel circuits included in the second region 1502 are a third pixel circuit 1533 and a fourth pixel circuit 1534, the third pixel circuit 1533 and the fourth pixel circuit 1534 may be connected to a first-second control line 1512 that provides a first-second control signal (S(2)). The third pixel circuit 1533 and the fourth pixel circuit 1534 may be connected to a second-second control line 1522 that controls a second-second control signal (P(2)).

[0201] In this embodiment, the mode control unit 1510 can control the pixel circuits arranged in the first region 1501 using a 1-1 control signal (S(1)) and a 2-1 control signal (P(1)). The mode control unit 1510 can control the pixel circuits arranged in the second region 1502 using a 1-2 control signal (S(2)) and a 2-2 control signal (P(2)).

[0202] 15, the operations of pixel circuits arranged in the first region 1501, such as the first pixel circuit 1531 and the second pixel circuit 1532, can be controlled together (or identically, simultaneously, or organically). The operations of pixel circuits arranged in the second region 1502, such as the third pixel circuit 1533 and the fourth pixel circuit 1534, can be controlled together. For signals provided by the mode control unit 1610, see FIG. 17.

[0203] As in the embodiment of FIG. 15 , the sizes of the first region 1501 and the second region 1502 may be fixed. The first region 1501 may include a region that operates in a first mode. The first region 1501 may include, but is not limited to, a region disposed adjacent to the driver's seat. The second region 1502 may include a region that operates in the first mode and / or the second mode. The second region 1502 may include, but is not limited to, a region disposed adjacent to the passenger seat.

[0204] Figure 16 shows an example of switching the first region 1501 and the second region 1502 of Figure 15 with each other. The first region 1601 of Figure 16 can include a third pixel circuit 1633 and a fourth pixel circuit 1634. The second region 1602 can include a first pixel circuit 1631 and a second pixel circuit 1632.

[0205] In this embodiment, the mode control unit 1610 can operate the first region 1601 in the first mode. The mode control unit 1610 can operate the second region 1602 in the first mode or the second mode. The signals provided by the mode control unit 1610 can be seen in FIG. 17.

[0206] Figure 17 shows an example of a signal provided by the mode control unit when the positions of the first and second regions are changed from Figure 15 to Figure 16. In the following, the overlapping content with the above content may be omitted.

[0207] 17, a mode control unit, for example, mode control unit 1510 of FIG. 15 or mode control unit 1610 of FIG. 16, can control a first control signal and a second control signal using a gate-off voltage (VGH) and a gate-on voltage (VGL). In the following description, it is assumed that the transistors to which the first control signal (e.g., 1-1 control signal (S(1)), 1-2 control signal (S(2))) and the second control signal (e.g., 2-1 control signal (P(1)), 2-2 control signal (P(2))) are input are p-type. However, the present invention is not limited to this.

[0208] In the embodiment, the mode controller 1510 may provide a first control signal (S(1)) corresponding to a gate-on voltage (VGL) to a first control line, e.g., a first-1 control line 1511 in FIG. 15, connected to pixel circuits included in the first region, e.g., the first region 1501 in FIG. 15. The mode controller 1510 may provide a second control signal (P(1)) corresponding to a gate-off voltage (VGH) to a second control line, e.g., a second-1 control line 1521 in FIG. 15, connected to pixel circuits included in the first region. In this case, a transistor receiving the first-1 control signal (S(1)) may be turned on, and a transistor receiving the second-1 control signal (P(1)) may be turned off. As a result, the first region may operate in a first mode in which the viewing angle is maintained. The first mode may include a mode having a viewing angle of a first value. A second mode, which will be described later, may include a mode having a second value, which is a viewing angle narrower (or smaller) than the first value.

[0209] The mode controller 1510 may provide a first control line, e.g., a first-2 control line 1512 in FIG. 15, connected to pixel circuits included in the second region, e.g., the second region 1502 in FIG. 15, with a first control signal (S(2)) corresponding to a gate-off voltage (VGH). The mode controller may provide a second control line, e.g., a second-2 control line 1522 in FIG. 15, connected to pixel circuits included in the second region with a second-2 control signal (P(2)) corresponding to a gate-on voltage (VGL). In this case, a transistor receiving the first-2 control signal (S(2)) may be turned off, and a transistor receiving the second-2 control signal (P(2)) may be turned on. This allows the second region to operate in a second mode in which the viewing angle is limited.

[0210] In an embodiment, the mode control units 1510 and 1610 may receive a region change input. For example, the mode control units 1510 and 1610 may receive an input to swap the first region 1501 and the second region 1502 in FIG. 15. If the time point at which the region change input is received corresponds to the first viewpoint 1710, the mode control units 1510 and 1610 may change the first control signal and / or the second control signal provided to the first region and the second region based on the first viewpoint 1710.

[0211] For example, when the mode control unit 1510, 1610 receives a region change input, it can change the 1-1 control signal (S(1)) provided to the first region 1501 of Fig. 15 to correspond to the gate-off voltage (VGH) and change the 2-1 control signal (P(1)) to correspond to the gate-on voltage (VGL). Also, in response to receiving the region change input, the mode control unit 1510, 1610 can change the 1-2 control signal (S(2)) provided to the second region 1502 of Fig. 15 to correspond to the gate-on voltage (VGL) and change the 2-2 control signal (P(2)) to correspond to the gate-off voltage (VGH).

[0212] 18 is a diagram illustrating a circuit connection relationship of a display device according to another embodiment of the present disclosure. For convenience of explanation, FIG. 18 exemplarily illustrates pixel circuits arranged in the second region 1502 of FIG. 15. In FIG. 18, content overlapping with FIG. 14 may be omitted.

[0213] Referring to FIG. 18, pixel circuits arranged in one region can provide a first control signal (e.g., 1-2 control signal (S(2))) and a second control signal (e.g., 2-2 control signal (P(2))).

[0214] In this embodiment, the mode controller 1820 may provide a first control signal or a second control signal to pixel circuits included in the same region through the same line. For example, a first pixel circuit 1801, a second pixel circuit 1802, a third pixel circuit 1811, and a fourth pixel circuit 1812 may be connected to a first-second control line 1831. A transistor for controlling a first light-emitting element ED1 included in each pixel circuit, for example, a first transistor T1, may be connected to the first-second control line 1831. The first pixel circuit 1801, the second pixel circuit 1802, the third pixel circuit 1811, and the fourth pixel circuit 1812 may be connected to a second-second control line 1832. A transistor for controlling a second light-emitting element ED2 included in each pixel circuit, for example, a second transistor T2, may be connected to the second-second control line 1832.

[0215] As shown in FIG. 18, a first control line (e.g., 1-2 control line 1831) for providing a first control signal and a second control line (e.g., 2-2 control line 1832) for providing a second control signal are connected to the pixel circuits included in the first region or the pixel circuits included in the second region, respectively, so that the mode control unit 1820 can control the modes of the pixel circuits included in one region at a time.

[0216] A display device according to an embodiment of the present specification may include a mode control unit that generates a first control signal and a second control signal using a gate-off voltage and a gate-on voltage, a gate driving circuit that generates an emission signal, a driving transistor, a first transistor that receives the first control signal, a second transistor that receives the second control signal, a third transistor that receives the emission signal, a first pixel circuit including a first light-emitting element connected to the first transistor and a second light-emitting element connected to the second transistor, a first lens arranged on the first light-emitting element, and a second lens arranged on the second light-emitting element.

[0217] According to some embodiments of the present disclosure, the gate driving circuit may generate the light emitting signal using the gate-off voltage and the gate-on voltage, and the display device may further include a power supply unit that generates the gate-off voltage and the gate-on voltage.

[0218] According to some embodiments of the present specification, a viewing angle of a region where the first light-emitting element is arranged by a first lens may correspond to a first value. A viewing angle of a region where the second light-emitting element is arranged by a second lens may correspond to a second value smaller than the first value. A first pixel circuit may operate in a first mode in which the viewing angle corresponds to the first value based on a first control signal corresponding to a gate-on signal and a second control signal corresponding to a gate-off signal. A first pixel circuit may operate in a second mode in which the viewing angle corresponds to the second value based on a first control signal corresponding to the gate-off signal and a second control signal corresponding to a gate-on signal.

[0219] According to some embodiments of the present disclosure, the display device may further include a second pixel circuit arranged in the same row as the first pixel circuit, and the mode control unit may provide a first control signal and a second control signal to the first pixel circuit and the second pixel circuit, respectively.

[0220] According to some embodiments of the present disclosure, a display device may be disposed in at least a portion of a vehicle to provide at least one content. The vehicle may include a driving area where a user controlling the vehicle is located and a general area where passengers of the user are located. A first pixel circuit may be disposed adjacent to the driving area, and the second pixel circuit may be disposed adjacent to the general area.

[0221] According to some embodiments of the present specification, the first control signal provided to the first pixel circuit may include a 1-1 control signal, and the second control signal provided to the first pixel circuit may include a 2-1 control signal. The first control signal provided to the second pixel circuit may include a 1-2 control signal, and the second control signal provided to the second pixel circuit may include a 2-2 control signal. Based on the 1-1 control signal corresponding to the gate-on signal and the 1-2 control signal corresponding to the gate-off signal, the first pixel circuit may operate in a first mode, and the second pixel circuit may operate in a second mode. Based on the 1-1 control signal and the 1-2 control signal each corresponding to the gate-on signal, the first pixel circuit and the second pixel circuit may operate in the first mode.

[0222] According to some embodiments of the present disclosure, the mode controller may control the first and second control signals based on a user input, and each of the first and second light-emitting elements may include a light-emitting diode.

[0223] A display panel according to one embodiment of the present specification may include a mode control unit that generates a first control signal and a second control signal using a gate-off voltage and a gate-on voltage, a gate driving circuit that generates an emission signal, a driving transistor, a first transistor that receives the first control signal, a second transistor that receives the second control signal, a third transistor that receives the emission signal, a first pixel circuit including a first light-emitting element connected to the first transistor and a second light-emitting element connected to the second transistor, a first lens arranged on the first light-emitting element, and a second lens arranged on the second light-emitting element.

[0224] According to some embodiments of the present specification, a gate driving circuit may generate the light-emitting signal using the gate-off voltage and the gate-on voltage. A viewing angle of an area where the first light-emitting element is arranged by the first lens may correspond to a first value, and a viewing angle of an area where the second light-emitting element is arranged by the second lens may correspond to a second value smaller than the first value. The first pixel circuit may operate in a first mode in which the viewing angle corresponds to the first value based on the first control signal corresponding to the gate-on signal and the second control signal corresponding to the gate-off signal. The first pixel circuit may operate in a second mode in which the viewing angle corresponds to the second value based on the first control signal corresponding to the gate-off signal and the second control signal corresponding to the gate-on signal.

[0225] According to some embodiments of the present disclosure, the display device may further include a second pixel circuit arranged in the same row as the first pixel circuit. A mode controller may provide a first control signal and a second control signal to the first pixel circuit and the second pixel circuit, respectively. The mode controller may control the first control signal and the second control signal based on a user input.

[0226] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to these embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are intended to illustrate, rather than limit, the technical concept of the present specification, and the scope of the technical concept of the present specification is not limited by these embodiments. Therefore, the above-described embodiments should be understood to be illustrative in all respects and not limiting. The scope of protection of the present specification should be interpreted by the scope of the following claims, and all technical concepts within the scope equivalent thereto should be interpreted as being included in the scope of the present specification. [Explanation of symbols]

[0227] DP: Display panel TC: Timing controller DD: Data Driver GD: Gate driver PA: Pixel area PU: Power supply unit AA:Display area BZ: Hidden area 310: First light-emitting element 320: Second light-emitting element

Claims

1. a mode control unit that generates a first control signal and a second control signal using a gate-off voltage and a gate-on voltage; a gate drive circuit that generates a light-emitting signal for driving the pixel circuit; a first display area having at least one first pixel circuit controlled by the mode control unit; and a display device including a second display area having at least one second pixel circuit controlled by the mode control unit, Each of the at least one first pixel circuit and the at least one second pixel circuit comprises: a driving transistor, a first transistor receiving the first control signal, a second transistor receiving the second control signal, a third transistor receiving the light emitting signal, a first light emitting element connected to the first transistor, and a second light emitting element connected to the second transistor; a first lens disposed on the first light-emitting element; and a second lens disposed on the second light-emitting element; Including, a viewing angle of an area where the first light-emitting element is arranged is determined by the first lens and corresponds to a first value, and a viewing angle of an area where the second light-emitting element is arranged is determined by the second lens and corresponds to a second value smaller than the first value; the mode control unit is configured to provide a 1-1 control signal, which is the first control signal, and a 2-1 control signal, which is the second control signal, to the at least one first pixel circuit in the first display area, and to provide a 1-2 control signal, which is the first control signal, and a 2-2 control signal, which is the second control signal, to the at least one second pixel circuit in the second display area; the at least one first pixel circuit operates in a first mode for emitting light through the first lens based on receiving the first-1 control signal which is the gate-on voltage and the second-1 control signal which is the gate-off voltage; the at least one second pixel circuit operates in a second mode for emitting light through the second lens based on receiving the first-2 control signal that is the gate-off voltage and the second-2 control signal that is the gate-on voltage.

2. the gate drive circuit generates the light-emitting signal using the gate-off voltage and the gate-on voltage; Each of the at least one first pixel circuit and the at least one second pixel circuit comprises: a fourth-1st transistor connected between a reference voltage line and the first light-emitting element; and a fourth-2 transistor connected between the reference voltage line and the second light emitting element; 2. The display device according to claim 1, wherein the 4-1 transistor and the 4-2 transistor are controlled by the same scan signal.

3. The display device of claim 2 , further comprising a power supply unit that generates the gate-off voltage and the gate-on voltage.

4. The first lens has a planar shape that is a bar shape extending in one direction, The display device according to claim 1 , wherein the second lens has a circular planar shape.

5. 5. The display device of claim 4, wherein the at least one first pixel circuit operates in the second mode based on the first-1 control signal corresponding to the gate-off voltage and the second-1 control signal corresponding to the gate-on voltage.

6. A display device as described in Claim 4, wherein the at least one second pixel circuit operates in the first mode based on the first-2 control signal corresponding to the gate-on voltage and the second-2 control signal corresponding to the gate-off voltage.

7. The display device according to claim 1 , wherein the at least one second pixel circuit is arranged in the same row as the at least one first pixel circuit.

8. The display device of claim 7 , wherein the display device is disposed on at least a portion of a vehicle and provides at least one content to a user.

9. the vehicle includes a driving area in which a user controlling the vehicle is located, and a passenger area in which a passenger of the user is located; The display device of claim 8 , wherein the first pixel circuit is disposed adjacent to the driving area, and the second pixel circuit is disposed adjacent to the passenger area.

10. A display device as described in claim 1, wherein each of the at least one first pixel circuit and each of the at least one second pixel circuit operates in the second mode based on the second-1 control signal corresponding to the gate-on voltage and the second-2 control signal corresponding to the gate-on voltage.

11. A display device as described in claim 1, wherein each of the at least one first pixel circuit and each of the at least one second pixel circuit operates in the first mode based on each of the first-1 control signal and the first-2 control signal corresponding to the gate-on voltage.

12. The display device of claim 1 , wherein the mode control unit controls the first control signal and the second control signal based on a user input.

13. The display device of claim 1 , wherein each of the first light-emitting element and the second light-emitting element includes a light-emitting diode.

14. a mode control unit that generates a first control signal and a second control signal using a gate-off voltage and a gate-on voltage; a gate drive circuit that generates a light-emitting signal for driving the pixel circuit; a first display area having at least one first pixel circuit controlled by the mode control unit; and a display panel including a second display area having at least one second pixel circuit controlled by the mode control unit, Each of the at least one first pixel circuit and the at least one second pixel circuit comprises: a driving transistor, a first transistor receiving the first control signal, a second transistor receiving the second control signal, a third transistor receiving the light emitting signal, a first light emitting element connected to the first transistor, a second light emitting element connected to the second transistor, a 4-1 transistor connected between a reference voltage line and the first light emitting element, and a 4-2 transistor connected between the reference voltage line and the second light emitting element; a first lens disposed on the first light-emitting element; and a second lens disposed on the second light-emitting element; wherein the 4-1 transistor and the 4-2 transistor are controlled by the same scan signal; The first lens has a planar shape that is a bar shape extending in one direction, the second lens has a circular planar shape, a viewing angle of an area where the first light-emitting element is arranged is determined by the first lens and corresponds to a first value, and a viewing angle of an area where the second light-emitting element is arranged is determined by the second lens and corresponds to a second value smaller than the first value; the mode control unit is configured to provide a 1-1 control signal, which is the first control signal, and a 2-1 control signal, which is the second control signal, to the at least one first pixel circuit in the first display area, and to provide a 1-2 control signal, which is the first control signal, and a 2-2 control signal, which is the second control signal, to the at least one second pixel circuit in the second display area; the at least one first pixel circuit operates in a first mode for emitting light through the first lens based on receiving the first-1 control signal which is the gate-on voltage and the second-1 control signal which is the gate-off voltage; the at least one second pixel circuit operates in a second mode for emitting light through the second lens based on receiving the first-2 control signal that is the gate-off voltage and the second-2 control signal that is the gate-on voltage.

15. The display panel according to claim 14 , wherein the gate drive circuit generates the light-emitting signal using the gate-off voltage and the gate-on voltage.

16. the at least one second pixel circuit operates in the first mode based on the first-2 control signal corresponding to the gate-on voltage and the second-2 control signal corresponding to the gate-off voltage; 15. The display panel of claim 14, wherein the at least one first pixel circuit operates in the second mode based on the first-1 control signal corresponding to the gate-off voltage and the second-1 control signal corresponding to the gate-on voltage.

17. The display panel of claim 14 , wherein the at least one second pixel circuit is arranged in the same row as the at least one first pixel circuit.

18. The display panel of claim 14 , wherein the mode control unit controls the first control signal and the second control signal based on a user input.

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