Ultrasound diagnostic equipment

Abstract

To reliably secure a prescribed waiting time between control data when setting the control data serially.SOLUTION: An ultrasonic diagnostic device includes an equipment part and a control part. The equipment part includes hardware equipment used for ultrasonic image diagnosis and a hardware timer. The control part is connected to the equipment part and transmits control data to the hardware equipment. When transmitting second control data after an elapse of a prescribed time interval from the first control data, the control part counts the prescribed time interval in cooperation with the hardware timer with the transmission of the first control data as a trigger, and transmits the second control data with the completion of counting of the prescribed time interval as a trigger.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments disclosed in this specification and the drawings relate to an ultrasound diagnostic device. [Background technology]

[0002] In an ultrasound diagnostic device, when the CPU (Central Processing Unit) sequentially sets control data (such as a power-on sequence) for various hardware devices, a predetermined time interval (wait time) may be inserted between the control data. In this case, the CPU uses a software timer to insert the wait time between the control data.

[0003] Recent CPUs have improved power management, and will transition to a stopped state (hibernation) if they are not used for a certain period of time. When a CPU attempts to set control data in a hardware device while in a stopped state, it takes time to transition from a stopped state to an operational state, and there are cases where the waiting time cannot be secured. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-301812 Summary of the Invention [Problem to be solved by the invention]

[0005] One of the problems to be solved by the embodiments disclosed in this specification and the drawings is to ensure a predetermined waiting time between control data when setting control data sequentially. However, the problems to be solved by the embodiments disclosed in this specification and the drawings are not limited to the above problem. Problems corresponding to the effects of each configuration shown in the embodiments described below can also be positioned as other problems. [Means for solving the problem]

[0006] An ultrasound diagnostic apparatus according to an embodiment includes an equipment unit and a control unit. The equipment unit includes hardware devices used for ultrasound image diagnosis and a hardware timer. The control unit is connected to the equipment unit and transmits control data to the hardware devices. When transmitting second control data after a predetermined time interval has elapsed since first control data, the control unit counts the predetermined time interval in cooperation with the hardware timer, triggered by the transmission of the first control data, and transmits the second control data upon completion of counting the predetermined time interval. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an ultrasonic diagnostic apparatus according to this embodiment. [Figure 2] FIG. 2 is a diagram showing the flow of control data within the ultrasound diagnostic apparatus. [Figure 3] FIG. 3 is a diagram illustrating an example of a control data setting process according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a control data setting process according to the second embodiment. [Figure 5] FIG. 5 is a diagram illustrating an example of a process of setting multiple pieces of control data according to the third embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of a control data setting process according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of an ultrasound diagnostic apparatus will be described in detail with reference to the drawings.

[0009] FIG. 1 is a diagram showing an example of the configuration of an ultrasound diagnostic apparatus 100 according to this embodiment. As shown in FIG. 1, the ultrasound diagnostic apparatus 100 includes a main body unit 10 and a host unit 20. The main body unit 10 and the host unit 20 are mounted in a housing of the ultrasound diagnostic apparatus 100. The main body unit 10 houses multiple hardware devices used in ultrasound image diagnosis. The main body unit 10 includes, as hardware devices, a transmission circuit 12, a reception circuit 13, a transmission / reception control circuit 14, a signal processing circuit 15, a memory 16, and a power supply circuit 17. The host unit 20 is a computer that controls the main body unit 10 for ultrasound image diagnosis. The host unit 20 is connected to the main body unit 10 via a cable or a backplane. An ultrasound probe 11 is detachably attached to the main body unit 10. Furthermore, a biological information collector 200 is detachably attached to the host unit 20. The ultrasound probe 11 and the biological information collector 200 are also examples of hardware devices used in ultrasound image diagnosis.

[0010] Figure 2 is a diagram showing the flow of control data within the ultrasound diagnostic apparatus 100. The arrows in Figure 2 represent the flow of control data. The dotted lines in Figure 2 represent electrical connection relationships. The control data according to this embodiment is data transmitted from the host control circuit 21 to various hardware devices, and refers to data related to the setting of control parameters for the hardware devices.

[0011] As shown in FIGS. 1 and 2, the ultrasonic probe 11 transmits and receives ultrasonic waves. The ultrasonic probe 11 includes, for example, multiple transducers, a matching layer, an acoustic lens, and a backing material. The multiple transducers generate ultrasonic waves based on drive signals supplied from a transmission circuit 12. The matching layer serves to match impedance between the multiple transducers and the living body. The acoustic lens is made of a flexible material, such as silicone rubber, and focuses the ultrasonic waves into a beam. The backing material prevents the ultrasonic waves from propagating backward in the direction of radiation from the multiple transducers. When ultrasonic waves are transmitted from the ultrasonic probe 11 to a subject, the transmitted ultrasonic waves are reflected successively by discontinuous surfaces of acoustic impedance in the subject's body tissue, received by the multiple transducers, and converted into electrical signals (echo signals). The amplitude of the echo signal depends on the difference in acoustic impedance at the discontinuous surfaces from which the ultrasonic waves are reflected. Furthermore, when a transmitted ultrasonic pulse is reflected by the surface of a moving blood flow or a heart wall, the echo signal undergoes a frequency shift due to the Doppler effect, depending on the velocity component of the moving object in the direction of ultrasonic transmission. The ultrasonic probe 11 operates in accordance with control data relating to probe control parameters supplied from the transmission / reception control circuit 14. For example, if the number of transducers in the ultrasonic probe 11 is greater than the number of channels in the transmission circuit 12 and the reception circuit 13, the probe control parameters correspond to hardware switch control data for switching the transducers in the ultrasonic probe 11. If the ultrasonic probe 11 is a mechanical probe that is swung by a motor, the probe control parameters correspond to motor control data.

[0012] The transmission circuit 12 is an electrical circuit that supplies drive signals to the ultrasonic probe 11. The transmission circuit 12 generates drive signals so that desired ultrasonic pulses are transmitted from the ultrasonic probe 11 in accordance with control data related to transmission control parameters, such as the pulse repetition frequency (PRF), transmission position information, transmission aperture, and transmission delay, supplied from the transmission / reception control circuit 14. Specifically, the transmission circuit 12 is realized by a trigger generation circuit, a delay circuit, a pulser circuit, and the like. The trigger generation circuit repeatedly generates rate pulses for forming transmission ultrasonic waves at a predetermined rate frequency. The delay circuit provides each rate pulse generated by the trigger generation circuit with a delay time for each of the multiple transducers required to focus the ultrasonic waves generated from the ultrasonic probe 11 into a beam and determine the transmission directivity. The pulser circuit applies drive signals (drive pulses) to the multiple transducers provided in the ultrasonic probe 11 at a timing based on the rate pulse. The transmission direction from the surfaces of the multiple transducers can be arbitrarily adjusted by changing the delay time provided for each rate pulse using the delay circuit. The transmission control parameters are a type of control parameter.

[0013] The receiving circuit 13 is an electrical circuit that performs various signal processing on the echo signals supplied from the ultrasonic probe 11 to generate received signals. The receiving circuit 13 generates digital signals (beam data) corresponding to scan lines from the echo signals obtained from the ultrasonic probe 11 in accordance with control data related to reception control parameters such as receive aperture information and receive delay supplied from the transmission / reception control circuit 14. Specifically, the receiving circuit 13 is realized by a preamplifier, an A / D converter, a demodulator, a beamformer (adder), and the like. The preamplifier amplifies the echo signals received by the ultrasonic probe 11 for each channel and performs gain correction processing. The A / D converter converts the gain-corrected echo signals into digital signals. The demodulator demodulates the digital signals. For example, the beamformer applies a delay time required to determine the receive directivity to the demodulated digital signals and adds up the multiple digital signals with the applied delay time. The beamformer's addition processing generates beam data in which reflection components from a direction corresponding to the receive directivity are emphasized. The receive control parameters are a type of control parameter.

[0014] The transmission / reception control circuit 14 has a processor that controls the main body 10. The transmission / reception control circuit 14 transmits and sets various control data to the ultrasonic probe 11, the transmission circuit 12, the reception circuit 13, the signal processing circuit 15, the memory 16, the power supply circuit 17, etc. in accordance with commands from the host control circuit 21. At this time, the transmission / reception control circuit 14 may temporarily store various control parameters in the memory 16, read them out from the memory 16 at an appropriate timing, and transmit them to the ultrasonic probe 11, the transmission circuit 12, the reception circuit 13, the signal processing circuit 15, the memory 16, the power supply circuit 17, etc.

[0015] Specifically, the transmit / receive control circuit 14 receives control data related to transmit / receive control parameters, such as the image mode, number of beams, frame rate, and diagnostic depth, instructed by the host control circuit 21, and determines the PRF based on the transmit / receive control parameters. The transmit / receive control circuit 14 transmits control data related to transmit / receive position information, transmit aperture, transmit delay, and other transmit control parameters stored in the memory 16 to the transmit circuit 12. The transmit / receive control circuit 14 transmits control data related to receive control parameters, such as receive aperture information and receive delay, stored in the memory 16 to the receive circuit 13. The transmit / receive control circuit 14 transmits control data related to signal processing control parameters, such as digital filter processing conditions, stored in the memory 16 to the signal processing circuit 15. The transmit / receive control circuit 14 transfers the beam data received from the signal processing circuit 15 to a storage device 23 under the control of the host control circuit 21.

[0016] The memory 16 is a storage device that temporarily stores various control data from the transmission / reception control circuit 14. The memory 16 stores control data related to various control parameters that are transferred to and set by the transmission circuit 12, the reception circuit 13, and the signal processing circuit 15 based on information such as various ultrasound scan modes, the connected ultrasound probe 11, and the number of parallel simultaneous receptions. The control parameters of the control data stored here include, for example, frame information, vector information, beam information, transmitting element positions, transmission delay, transmission aperture, receiving element positions, reception delay, reception aperture, header information, digital filter coefficients, etc. The memory 16 can be configured using semiconductor memory elements such as ROM (Read Only Memory), RAM (Random Access Memory), EEPROM (Registered Trademark), flash memory, etc., a hard disk, etc.

[0017] The power supply circuit 17 supplies power to hardware devices connected to or housed in the main body 10, such as the ultrasonic probe 11, the transmission circuit 12, the reception circuit 13, the transmission / reception control circuit 14, the signal processing circuit 15, the memory 16, and the hardware timer 31. In the present embodiment, as an example, the power supply circuit 17 supplies power to the ultrasonic probe 11, the transmission circuit 12, the reception circuit 13, the signal processing circuit 15, the memory 16, and the hardware timer 31 via the transmission / reception control circuit 14. The power supply circuit 17 operates in accordance with control data related to power supply control parameters such as the type of image mode and the transmission voltage value in each image mode, which are supplied from the transmission / reception circuit 14. Any type of image mode used in general ultrasound image diagnosis can be applied, and examples include B-mode, C-mode, and PW-mode.

[0018] The hardware timer 31 is a hardware device that counts time based on a clock signal having a fixed period generated by a crystal oscillator or a divided signal of the clock signal. As shown in Fig. 1, the hardware timer 31 is provided in the transmission / reception control circuit 14, which functions as a control data setting destination or a repeater. The hardware timer 31 may be provided in any hardware device connected to or housed in the main body 10, such as the ultrasound probe 11, the transmission circuit 12, the reception circuit 13, the signal processing circuit 15, or the memory 16, which is a control data setting destination.

[0019] The host unit 20 has hardware devices such as a host control circuit 21, an image generation circuit 22, a storage device 23, a display device 24, an operation device 25, and a power supply circuit 26.

[0020] The host control circuit 21 is a processor that controls the ultrasonic diagnostic apparatus 100. For example, the host control circuit 21 controls the entire ultrasonic diagnostic apparatus 100 based on a diagnostic mode set by the operation device 25 and various control data. The host control circuit 21 includes, for example, a CPU (hereinafter referred to as a host CPU) 51 and a memory such as a ROM or RAM (hereinafter referred to as a host memory) 52. The host CPU 51 and the host memory 52 are attached to a motherboard that complies with an arbitrary standard.

[0021] The host CPU 51 has a power management function. Examples of the host CPU 51 include a CPU conforming to standards such as commercially available ATX (Advanced Technology Extended) or ATX developed for ultrasound diagnostic equipment. Specifically, the host CPU 51 includes a CPU core 53, a chipset 54, and a power control circuit 55. The CPU core 53 reads and interprets various software programs stored in the host memory 52, etc., and executes various processes described in the software programs. An example of the software program is an image diagnosis program for performing ultrasound image diagnosis. By executing the image diagnosis program, the CPU core 53 transmits a series of control data to various hardware devices via the chipset 54. The CPU core 53 can also execute another software program, such as a software timer that counts time.

[0022] The chipset 54 is an integrated circuit that controls data transmission between the CPU core 53 and an external bus (not shown). The external bus is a data transmission path (bus) that transmits and receives various data between the CPU core 53 and peripheral devices such as the main body 10, the image generation circuit 22, the storage device 23, the display device 24, the operation device 25, the power supply circuit 26, and the biological information collector 200.

[0023] The power control circuit 55 is an integrated circuit that monitors and controls the operation of each device in the ultrasound diagnostic apparatus 100 in order to reduce power consumption. This function is called a power management function. By realizing the power management function, the power control circuit 55 controls the supply of power from the power supply circuit 26 of the host unit 20 to various hardware devices of the host unit 20, such as the image generation circuit 22, the storage device 23, the display device 24, the operation device 25, the biological information collector 200, the host memory 52, the CPU core 53, and the chipset 54, depending on the usage status of the hardware devices.

[0024] The configuration of the host CPU 51 is not limited to the above configuration, and the host CPU 51 may also include other components such as a register, a memory control device, a GPU (Graphical Processing Unit), and the like.

[0025] The image generation circuit 22 is a processor that generates an ultrasound image. The image generation circuit 22 scan-converts the beam data stored in the storage device 23 to generate a two-dimensional or three-dimensional B-mode image or a color Doppler image.

[0026] The storage device 23 is configured with a large-capacity HDD (Hard Disk Drive), SSD (Solid State Drive), flash memory, etc. As one example, the storage device 23 stores beam data supplied from the transmission and reception control circuit 14. As another example, the storage device 23 stores ultrasound images and additional information supplied from the image generation circuit 22.

[0027] The display device 24 is any display such as a liquid crystal display, an organic EL display, an LED display, a plasma display, a CRT display, etc. As one example, the display device 24 displays an ultrasound image output from the image generation circuit 22. As another example, the display device 24 displays various diagnostic parameters.

[0028] The operation device 25 is a man-machine interface that accepts various instructions from an operator. Specifically, the operation device 25 is a mouse, a keyboard, a panel switch, a slider switch, a trackball, a rotary encoder, an operation panel, and a touch command screen (TCS). The operation device 25 inputs various diagnostic modes and various parameters associated with the diagnostic modes to the ultrasound diagnostic apparatus 100.

[0029] The power supply circuit 26 supplies power to hardware devices housed in or connected to the host unit 20, such as the host control circuit 21, the image generation circuit 22, the storage device 23, the display device 24, the operation device 25, and the biometric information collector 200. In this embodiment, as an example, the power supply circuit 26 supplies power to the image generation circuit 22, the storage device 23, the display device 24, the operation device 25, and the biometric information collector 200 via the host control circuit 21.

[0030] The biological information collector 200 is connected to the host unit 20 via wire or wireless communication so as to be able to communicate with the host unit 20. The biological information collector 200 collects biological information such as the blood pressure and pulse rate of the subject. The biological information collector 200 is provided with a hardware timer 201. The configuration of the hardware timer 201 is the same as that of the hardware timer 31. The biological information collector 200 may be connected to the main body unit 10.

[0031] The main body unit 10 and the biological information collector 200 can be classified as a device unit. The device unit has hardware devices and hardware timers used for ultrasound image diagnosis. The hardware devices include an ultrasound probe 11, a transmission circuit 12, a reception circuit 13, a transmission / reception control circuit 14, a signal processing circuit 15, a memory 16, a power supply circuit 17, a hardware timer 31, and a biological information collector 200. The hardware timers include the hardware timer 31 included in the transmission / reception control circuit 14 and the hardware timer 201 included in the biological information collector 200. The host unit 20 is connected to the device unit and transmits control data to the hardware devices.

[0032] The ultrasound diagnostic apparatus 100 according to this embodiment will be described in detail below.

[0033] As described above, the host control circuit 21 transmits a series of control data sequences to various hardware devices housed in or connected to the ultrasound diagnostic apparatus 100. The host control circuit 21 and the main body unit 10 are connected by an external bus capable of high-speed communication. For example, a PCI_Express (hereinafter referred to as PCIe), which enables high-speed serial communication, is used as such an external bus. Meanwhile, the hardware devices within the main body unit 10, the main body unit 10 and the ultrasound probe 11, and the host unit 20 and the biological information collector 200 are connected by low-speed serial communication, which has a lower data transfer rate than PCIe. Therefore, when the host control circuit 21 transmits a series of control data sequences to the hardware devices of the main body unit 10, it is necessary to provide a predetermined time interval (hereinafter referred to as a wait time) between the control data sequences to avoid congestion of the control data.

[0034] To reduce power consumption, the power management function of the power control circuit 55 reduces or stops the power supply to hardware devices housed in or connected to the host control circuit 21 when the hardware devices are not in use or are used infrequently. Even if the power supply is resumed to transition from a stopped (hibernated) state to an operational state, it takes time for the hardware devices to transition to a stable, operational state. During the transition from the stopped (hibernated) state to the operational state, the hardware devices must wait for control data to be set. This transition period affects the waiting time between successive control data. Therefore, the changed waiting time must be corrected. The waiting time between control data varies depending on the hardware device being controlled, but is often set to a value ranging from a few usecs to a few msec.

[0035] Here, two specific examples of problems with the control data setting process are presented. Specific Example 1: The biometric information collector 200 is an independent microcomputer-controlled device. When power is supplied or released from the power supply circuit 26, the microcomputer in the biometric information collector 200 starts up. The transition time from a stopped state to an operational state takes several usec to several msec. If the host control circuit 21 sends a biometric information collection start command before the microcomputer has fully started up, the biometric information collector 200 may lose the command. Specific Example 2: As described above, the host control circuit 21 and the main unit 10 are connected via a high-speed PCIe interface, but the hardware devices within the main unit are connected using a communication method with a slower data transfer rate than PCIe communication. When reading or writing data over a slow communication channel, a waiting time is required until the communication is completed, taking the communication speed into consideration. However, if the next access is made without waiting for this time, the data being transferred may be changed or the read value may be incorrect, potentially causing the hardware device to malfunction.

[0036] Here, referring to FIG. 6, problems with the control data setting process according to a comparative example of the present embodiment will be described. FIG. 6 is a diagram showing the flow of the control data setting process according to the comparative example. More specifically, FIG. 6 shows the flow when a series of control data D1 and control data D2 are set in a hardware device of the ultrasound diagnostic apparatus 100 after a waiting time WT. The hardware device may be any device housed in or connected to the ultrasound diagnostic apparatus 100, such as the ultrasound probe 11, the transmission circuit 12, the reception circuit 13, the transmission / reception control circuit 14, the signal processing circuit 15, the memory 16, the power supply circuit 17, or the biological information collector 200. The host CPU 51 is described separately for devices in a stopped state and devices in an operable state. A chipset 54 is described as an example of a device in a stopped state, and software is described as an example of a device in an operable state. Since the software is implemented by the CPU core 53 of the host CPU 51, the CPU core 53 is referred to as hardware.

[0037] When the operator issues an instruction to change the mode of the ultrasound diagnostic apparatus via the operation device 25, the CPU core 53 executes software such as an image diagnostic program. The chipset 54 cannot instantly return from a stopped state to an operational state due to the power control circuit 55, and is assumed to be in a transitional period from a stopped state to an operational state. To transmit the control data D1 to the target hardware device, the software first transmits a setting command for the control data D1 to the chipset 54 (step SZ1). Because the chipset 54 is not in an operational state, it cannot transmit the control data D1 to the hardware device. After step SZ1, the host CPU software starts counting the waiting time WT using a software timer (step SZ2). For example, a sleep function in C language is used as the software timer. After step SZ2, the chipset 54 is assumed to return to an operational state.

[0038] When the chipset 54 returns to an operable state, it transmits the control data D1 to the target hardware device via an external bus such as PCIe in accordance with the setting command. When the hardware device receives the control data D1, the control data D1 is set in the hardware device. When the software completes counting the waiting time WT (step SZ4), it supplies a setting command for the control data D2 to the chipset 54 (step SZ5), and the chipset 54 supplies the control data D2 to the target hardware device via an external bus such as PCIe in accordance with the setting command, and sets the control data D2 in the hardware device.

[0039] As described above, in the comparative example, the CPU core 53 attempts to ensure the waiting time WT by using a software timer. Because it takes time to transition from a stopped state to an operational state, a time lag may occur between the time when the software issues a setting command for the control data D1 (step SZ1) and the time when the chipset 54 or the like actually executes the command and transmits it to a hardware device such as the main unit 10 via an external bus such as PCIe (step SZ3). Meanwhile, after issuing the setting command (step SZ1), the software counts the waiting time WT (step SZ2). Therefore, the time interval between the time when the control data D1 is actually transmitted to the hardware device (step SZ3) and the time when the control data D2 is transmitted to the hardware device (step SZ6) is shorter than the waiting time WT. This may cause the hardware device to malfunction.

[0040] The ultrasound diagnostic device 100 according to this embodiment includes a main unit 10 and a host control circuit 21. The main unit 10 includes hardware devices used for ultrasound image diagnosis and a hardware timer 31. When transmitting second control data after a predetermined waiting time has elapsed since the transmission of first control data, the host control circuit 21 counts the predetermined waiting time in cooperation with the hardware timers 31, 201, triggered by the transmission of the first control data, and transmits the second control data upon completion of counting the predetermined waiting time. This configuration attempts to ensure a sufficient waiting time. An example of the control data setting process according to this embodiment will be described in detail below. For the sake of specificity, the following description assumes that the hardware device to which the control data is set is the transmission / reception control circuit 14 of the main unit 10, or the ultrasound probe 11, transmission circuit 12, reception circuit 13, signal processing circuit 15, memory 16, power supply circuit 17, etc., connected to the transmission / reception control circuit 14, and that the hardware timer is the hardware timer 31 provided in the transmission / reception control circuit 14. This embodiment is equally applicable to other hardware devices and other hardware timers.

[0041] Example 1 The host control circuit 21 according to the first embodiment counts the waiting time WT through cooperation between the hardware timer 31 and the software timer. More specifically, the host control circuit 21 counts the waiting time WT based on the time count by the software timer and polling of the hardware timer 31. Note that the hardware timer 31 according to the first embodiment is assumed to be a counter that measures, for example, 1 usec or 1 msec. The hardware timer 31 is configured to count by incrementing.

[0042] 3 is a diagram illustrating an example of a control data setting process according to the first embodiment. The setting process in FIG. 3 illustrates a process of setting a series of control data D1 and control data D2 in a hardware device. Before step SA1, the chipset 54 of the host CPU 51 is in a stopped state by the power control circuit 55, and in response to a mode change instruction from the operator via the operation device 25, the power control circuit 55 starts to restore the chipset 54 to an operable state. However, it is assumed that the chipset 54 is in the middle of transitioning from the stopped state to an operable state at the start of step SA1. It is assumed that the CPU core 53 is in an operable state at the start of step SA1.

[0043] 3, first, the software (CPU core 53) of the host CPU 51 of the host control circuit 21 sends a setting command for the control data D1 to the chipset 54 in order to send the control data D1 to the hardware device as the setting destination in accordance with an instruction from the operator via the operation device 25 (step SA1). At the time of step SA1, the chipset 54 is not in an operable state and is therefore unable to send the control data D1 to the hardware device.

[0044] After step SA1 is performed, the software starts counting the waiting time WT using a software timer (step SA2). The waiting time WT is set in advance according to the types of the control data D1 and D2.

[0045] When step SA2 is performed, the software transmits a request command for time information HT1 from the hardware timer 31 to the chipset (step SA3). It is assumed that the chipset 54 has not yet returned to an operable state at the time of step SA3 and has not been able to transmit the request for time information HT1 to the hardware device.

[0046] After step SA3, it is assumed that the chipset 54 returns to an operable state. When the chipset 54 returns to an operable state, it transmits control data D1 to the hardware device in accordance with the setting command of step SA1 (step SA4). When the hardware device receives the control data D1, the control data D1 is set in the hardware device.

[0047] Furthermore, in accordance with the request command of step SA3, the chipset 54 requests time information HT1 from the hardware timer 31 (step SA5). In response to the request, the hardware timer 31 supplies the time at which the request was received or a time close to that time as time information HT1 to the chipset (step SA6). The time information HT1 can be considered the same as the time at which the control data D1 was transmitted to the hardware device. The chipset 54 supplies the time information HT1 to the software (step SA7). The software holds the time information HT1.

[0048] Thereafter, the software completes counting the waiting time WT by the software timer (step SA8). After step SA8 is performed, the software transmits a request command for time information HT2 from the hardware timer 31 to the chipset 54 (step SA9), and the chipset 54 requests the time information HT2 from the hardware timer 31 in accordance with the request command (step SA10). In response to the request, the hardware timer 31 transmits the time at which the request was received as time information HT2 to the chipset 54 (step SA11), and the chipset 54 transmits the time information HT2 to the software (step SA12).

[0049] After step SA12 is performed, the software determines whether the difference between the time information HT2 and the time information HT1 is equal to or greater than the waiting time WT (step SA13). If it is determined that the difference is not equal to or greater than the waiting time WT (step SA13: NO), the software repeats steps SA9 to SA12 and requests the latest time information HT2 from the hardware timer 31. If it is determined in step SA13 that the difference between the time information HT2 and the time information HT1 is equal to or greater than the waiting time WT (step SA13: YES), the software transmits a setting command for the control data D2 to the chipset 54 (step SA14), and the chipset 54 transmits the control data D2 to the hardware device in accordance with the request (step SA15).

[0050] This completes the control data setting process according to the first embodiment. Note that the time series shown in Fig. 3 is an example and is not limited to this. The time it takes for the chipset 54 to return from the inactive state to the active state varies depending on the situation, and the time at which the control data D1 and the time information HT1 are transmitted to the hardware device is not limited to being transmitted after the request command (step SA3) as shown in Fig. 3, but may be transmitted between the start of counting the waiting time WT (step SA2) and the request command (step SA3), or may be transmitted between the setting command (step SA1) and the start of counting the waiting time WT (step SA2).

[0051] As described above, the host control circuit 21 according to the first embodiment starts counting the waiting time WT using a software timer upon receiving control data D1 and collects time information HT1 from the hardware timer 31. Upon completion of counting the waiting time WT using the software timer, the host control circuit 21 collects time information HT2 from the hardware timer 31. If the difference between the time information HT1 and the time information HT2 is not equal to or greater than the waiting time WT, the host control circuit 21 collects the waiting time WT again upon the passage of a predetermined time. If the difference is equal to or greater than the waiting time WT, the host control circuit 21 transmits control data D2 to the hardware device. In this manner, the host control circuit 21 confirms the completion of counting the waiting time WT using the software timer and ensures the waiting time WT by polling the hardware timer 31 provided in the hardware device to which the control data D1 and D2 are supplied. This ensures that the waiting time WT is maintained between the control data D1 and D2, even immediately after the host CPU 51 transitions from a stopped state to an operational state.

[0052] Example 2 The host control circuit 21 according to the second embodiment counts the waiting time by using an interrupt triggered by the completion of counting the waiting time by the hardware timer 31. The hardware timer 31 according to the second embodiment is configured to count by decrementing. In the case of a decrement counter, the hardware timer 31 notifies the host CPU of the host control circuit 21 that the counting has been completed by sending an interrupt when the value of the hardware timer 31 reaches 0.

[0053] FIG. 4 is a diagram illustrating an example of a control data setting process according to the second embodiment. Similar to the setting process of FIG. 3, the setting process of FIG. 4 illustrates a process of setting a series of control data D1 and control data D2 in hardware devices provided in the main body 10, such as the transmission / reception control circuit 14. Before step SB1, the chipset 54 of the host CPU 51 is in a stopped state by the power control circuit 55. In response to a mode change instruction from the operator via the operation device 25, the power control circuit 55 starts restoring the chipset 54 to an operable state. However, the chipset 54 is in the process of transitioning from the stopped state to an operable state at the start of step SB1. The CPU core 53 is in an operable state at the start of step SB1.

[0054] 4, first, the software of the host CPU 51 of the host control circuit 21, in accordance with an instruction from the operator via the operation device 25, sends a setting command for the control data D1 to the chipset 54 in order to send the control data D1 to the hardware device as the setting destination (step SB1). At the time of step SB1, the chipset 54 has not yet returned to an operable state and is therefore unable to send the control data D1 to the hardware device.

[0055] When step SB1 is performed, the software sends a count command to the chipset 54 together with the waiting time WT (step SB2) in order to transmit the waiting time WT to the hardware timer 31. The chipset 54 has not yet returned to an operable state at the time of step SB2, and is therefore unable to send the count command to the hardware timer 31.

[0056] After step SB2, the chipset 54 transitions to an operable state. When the chipset 54 returns to the operable state, it transmits control data D1 to the hardware device in accordance with the setting command of step SB1 (step SB3). When the hardware device receives the control data D1, the control data D1 is set in the hardware device.

[0057] Furthermore, in accordance with the count command of step SB2, the chipset 54 transmits the waiting time WT to the hardware timer 31 to instruct it to count (step SB4). When step SB4 is performed, the hardware timer 31 starts counting the waiting time WT (step SB5). The hardware timer 31 counts by decrementing the waiting time WT. When the waiting time WT reaches 0, the hardware timer 31 completes counting the waiting time WT (step SB6).

[0058] When step SB6 is performed, the hardware timer 31 transmits completion information indicating that counting has completed to the software via the chipset 54. Specifically, the hardware timer 31 transmits the completion information to the chipset 54 (step SB7), and the chipset transmits the completion information to the software (step SB8). When step SB8 is performed, the software supplies a setting command for the control data D2 to the chipset 54 (step SB9), and the chipset 54 supplies the control data D2 to the hardware device in accordance with the request (step SB10).

[0059] This completes the process of setting the control data according to the second embodiment. The time series shown in Fig. 4 is an example and is not limiting. The time it takes for the chipset 54 to return from the inactive state to the active state varies depending on the situation, and the time at which the control data D1 is transmitted to the hardware device is not limited to after the count command (step SB2) as shown in Fig. 4, but may be between the setting command (step SB1) and the count command (step SB2).

[0060] As described above, the host control circuit 21 according to the second embodiment transmits the control data D1 to the hardware timer 31 as a trigger for transmitting the control data D1, and the hardware timer 31 starts counting the waiting time WT as a trigger for receiving the request. Upon completion of counting the waiting time WT, the hardware timer 31 transmits completion information indicating the completion of counting. Upon receiving the completion information, the host control circuit 21 transmits the control data D2 to the hardware device. In this manner, the host control circuit 21 ensures the waiting time WT by having the hardware timer 31, which is the destination of the control data D1 and D2, count the waiting time WT and then receiving an interrupt notification from the hardware timer 31 indicating that the counting has completed. This ensures the waiting time WT between the control data D1 and the control data D2, even immediately after the host CPU 51 transitions from a halted state to an operable state.

[0061] Example 3 The host control circuit 21 according to the third embodiment sets multiple types of control data sequences in hardware devices. The number of types of control data sequences may be any number equal to or greater than two. The target hardware devices may be the same device or different devices. The main body 10 according to the third embodiment has multiple hardware timers 31 as the hardware timer 31. When transmitting multiple control data sequences with multiple waiting times, the host control circuit 21 counts the multiple waiting times using the multiple hardware timers 31.

[0062] As an example, the host control circuit 21 transmits a first type control data sequence DA and a second type control data sequence DB to a single hardware device. For the control data DA, the first control data DA1 and the second control data DA2 following the first control data DA1 are set with a waiting time WTA between them, and for the control data DB, the first control data DB1 and the second control data DB2 following the first control data DB1 are set with a waiting time WTB between them.

[0063] FIG. 5 is a diagram illustrating an example of a setting process for multiple control data according to the third embodiment. As illustrated in FIG. 5, the host control circuit 21 executes the setting process according to the first embodiment in parallel for the control data sequence DA and the control data sequence DB. The hardware timer 31 for the control data sequence DA is referred to as "hardware timer A," and the hardware timer 31 for the control data sequence DB is referred to as "hardware timer B." The hardware timers A and B have different counting unit times. More specifically, the unit time of the hardware timer A is 1 usec, and the unit time of the hardware timer B is 1 msec. Before step SC1 in FIG. 5, the chipset 54 of the host CPU 51 is in a stopped state by the power control circuit 55. In response to a mode change instruction from the operator via the operation device 25, the power control circuit 55 starts restoring the chipset 54 to an operable state. However, the chipset 54 is in the process of transitioning from a stopped state to an operable state at the start of step SC1. The CPU core 53 is in an operable state at the start of step SC1. For simplicity, FIG. 5 does not distinguish between the chipset 54 and the software, but shows the host control circuit 51 that includes the chipset 54 and the software, and accordingly does not show the time lag.

[0064] 5, the host control circuit 21 supplies control data DA1 to the hardware device (step SC1). After step SC1 is performed, the host control circuit 21 starts counting the waiting time WTA using a software timer (step SC2). At the same time as counting the waiting time WTA, the host control circuit 21 requests time information HTA1 from the hardware timer A (step SC3), and the hardware timer A transmits the first time information HTA1 to the host control circuit 21 (step SC4). The host control circuit 21 holds the received first time information HTA1.

[0065] After supplying control data DA1 (step SC1), the host control circuit 21 supplies control data DB1 to the hardware device (step SD1). After step SD1 is performed, the host control circuit 21 starts counting the waiting time WTB using a software timer (step SD2). At the same time as counting the waiting time WTB, the host control circuit 21 requests time information HTB1 from hardware timer B (step SD3), and hardware timer B transmits the first time information HTB1 to the host control circuit 21 (step SD4). The host control circuit 21 holds the received first time information HTB1.

[0066] When counting the waiting time WTA is completed (step SC5), the host control circuit 21 requests time information HTA2 from hardware timer A (step SC6), and hardware timer A transmits second time information HTA2 to the host control circuit 21 (step SC7). The host control circuit 21 then determines whether the difference between time information HTA2 and time information HTA1 is equal to or greater than the waiting time WTA (step SC8). If it determines that the difference is not equal to or greater than the waiting time WTA (step SC8: NO), the host control circuit 21 repeats steps SC6 to SC7 and requests the latest time information HTA2 from the hardware timer 31. If it determines in step SC8 that the difference between time information HTA2 and time information HTA1 is equal to or greater than the waiting time WTA (step SC8: YES), the host control circuit 21 supplies control data DA2 to the hardware device (step SC9).

[0067] When counting the waiting time WTB is completed (step SD5), the host control circuit 21 requests time information HTB2 from hardware timer B (step SD6), and hardware timer B transmits second time information HTB2 to the host control circuit 21 (step SD7). The host control circuit 21 then determines whether the difference between time information HTB2 and time information HTB1 is equal to or greater than the waiting time WTB (step SD8). If it determines that the difference is not equal to or greater than the waiting time WTB (step SD8: NO), the host control circuit 21 repeats steps SD6 to SD7 and requests the latest time information HTB2 from the hardware timer 31. If it determines in step SD8 that the difference between time information HTB2 and time information HTB1 is equal to or greater than the waiting time WTB (step SD8: YES), the host control circuit 21 supplies control data DB2 to the hardware device (step SD9).

[0068] This completes the process of setting multiple control data according to the third embodiment.

[0069] The setting process for multiple control data is not limited to the above processing example. For example, the host control circuit 21 may execute the setting process according to the second embodiment in parallel for the control data series DA and the control data series DB. Although the hardware timers A and B have different unit times, they may have the same unit time. In the third embodiment, only one hardware timer may be used to count the waiting times WTA and WTB. The host control circuit 21 according to the third embodiment may execute the setting process according to the first or second embodiment in parallel for three or more types of control data series.

[0070] (Summary) The ultrasonic diagnostic device 100 according to this embodiment can solve the problem of insufficient waiting time due to delays in setting control data that occurs when using a host CPU 21 with enhanced power management, thereby avoiding or reducing malfunctions of the ultrasonic diagnostic device 100 that occur due to insufficient waiting time.

[0071] It is possible to solve the above problem by disabling or suspending power management in the host CPU 21. However, disabling power management disables the power consumption reduction function, making it impossible to meet the demand for reduced power consumption. Furthermore, suspending power management requires modifying the BIOS (Basic Input / Output System), which means that commercially available ATX cards cannot be used and a custom ATX card must be developed, increasing the development costs for the host CPU 21.

[0072] The host CPU 51 according to this embodiment can be a commercially available CPU conforming to the ATX standard, and therefore satisfies the requirements for low power consumption while also satisfying the specifications for setting control data, thereby realizing a low-cost, low-power-consumption, and stable ultrasound diagnostic device 100.

[0073] According to at least one of the embodiments described above, when control data is set in a sequential manner, a predetermined waiting time between control data can be reliably ensured.

[0074] The term "processor" used in the above description refers to a circuit such as a CPU, a GPU, an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)). A processor realizes its function by reading and executing a program stored in a memory circuit. Note that instead of storing a program in a memory circuit, the program may be directly embedded in the processor circuit. In this case, the processor realizes its function by reading and executing the program embedded in the circuit. On the other hand, if the processor is, for example, an ASIC, the program is not stored in a memory circuit, but rather the function is directly embedded in the processor circuit as a logic circuit. Note that each processor in this embodiment is not limited to being configured as a single circuit per processor, but may be configured as a single processor by combining multiple independent circuits to realize its function. Furthermore, multiple components in FIG. 1 may be integrated into a single processor to realize its function.

[0075] Although several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, and combinations of embodiments can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0076] 10 Main body 11 Ultrasound probe 12 Transmitting circuit 13 Receiving circuit 14 Transmit / receive control circuit 15 Signal processing circuit 16 memory 17 Power circuit 20 Host Club 21 Host control circuit 22 Image generation circuit 23 Storage device 24 Display equipment 25 Operating equipment 26 Power circuit 31 Hardware Timer 51 Host control circuit 52 host memory 53 CPU cores 54 chipset 55 Power control circuit 100 Ultrasound diagnostic equipment 200 Biometric Information Collector 201 Hardware Timer

Claims

1. a device section having hardware devices and a hardware timer used for ultrasound image diagnosis; a control unit connected to the device unit and transmitting control data to the hardware device; The control unit When transmitting second control data after a predetermined time interval has elapsed since the transmission of first control data, using a software timer that counts time by software as a trigger, to start counting the predetermined time interval, and collecting first time information from the hardware timer; collecting second time information from the hardware timer when the counting of the predetermined time interval using the software timer is completed; If the difference between the first time information and the second time information is not equal to or greater than the predetermined time interval, collect the second time information again; If the difference is equal to or greater than the predetermined time interval, transmitting the second control data to the hardware device. Ultrasound diagnostic equipment.

2. a device section having hardware devices and a hardware timer used for ultrasound image diagnosis; a control unit connected to the device unit and transmitting control data to the hardware device; The control unit When transmitting second control data after a predetermined time interval has elapsed since the first control data, the transmission of the first control data is triggered by transmitting a request to the hardware timer to count the predetermined time interval; the hardware timer starts counting the predetermined time interval upon receiving the request, and transmits completion information indicating that counting has been completed upon completion of counting the predetermined time interval; the control unit, upon receiving the completion information, transmits the second control data to the hardware device. Ultrasound diagnostic equipment.

3. a device section having hardware devices and a hardware timer used for ultrasound image diagnosis; a control unit connected to the device unit and transmitting control data to the hardware device; when transmitting second control data after a predetermined time interval has elapsed since the transmission of first control data, the control unit counts the predetermined time interval in cooperation with the hardware timer, triggered by the transmission of the first control data, and transmits the second control data upon completion of counting the predetermined time interval; the device unit and the control unit are connected by a first data transmission path, the hardware devices of the device unit are connected by a second data transmission path; a data transfer rate of the second data transmission path is lower than a data transfer rate of the first data transmission path; Ultrasound diagnostic equipment.

4. the device unit has a plurality of hardware timers as the hardware timer, When transmitting a plurality of control data sequences at a plurality of predetermined time intervals, the control unit counts the plurality of predetermined time intervals using the plurality of hardware timers. The ultrasonic diagnostic apparatus according to any one of claims 1 to 3.

5. The ultrasonic diagnostic apparatus according to claim 4 , wherein the plurality of hardware timers count time in a plurality of unit times.

6. 4. The ultrasonic diagnostic apparatus according to claim 1, wherein the hardware device includes any one of an ultrasonic probe, a transmitting circuit, a receiving circuit, a transmitting / receiving control circuit, a signal processing circuit, a power supply circuit, and a memory.

7. The ultrasound diagnostic apparatus according to claim 6 , wherein the hardware device includes either one of the device unit and a biological information collector connected to the control unit.

8. The ultrasonic diagnostic apparatus according to claim 1 , wherein the control unit has a power management function.

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