Video signal processing device, video signal processing method, and program

Abstract

A processing device (10A) comprises: a reception interface (11) that receives a video signal indicating a moving image; a video processing circuit (13) that generates a first signal by performing video processing of one pattern on the video signal; a capture circuit (17) that generates a second signal by capturing the video signal received by the reception interface (11); a synthesis circuit (14A) that outputs a synthesized signal obtained by synthesizing the first signal and the second signal; and a processor that (a) controls the synthesis circuit (14A) such that the first signal is outputted as the synthesized signal in a first period, (b) controls the video processing circuit (13) such that the pattern of the video processing performed by the video processing unit (13) is changed in a second period, and (c) controls the capture circuit (17) such that the second signal is generated in the period of the change and controls the synthesis circuit (14A) such that the second signal is outputted as the synthesized signal.

Description

Technical Field

[0001] The present disclosure relates to a video signal processing apparatus, a video signal processing method, and a program.

Background Art

[0002] There is a video signal processing apparatus that performs video processing on a video signal including a moving image and displays it as a video. When the video signal processing apparatus switches the video signal, there is a technique for controlling to read out the video signal written in the memory immediately before the switching (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the video signal processing apparatus switches the video processing performed on the video signal, the video signal may be muted. In that case, there is a problem that the video signal may be muted at a timing contrary to the user's intention.

[0005] The present disclosure provides a video signal processing apparatus, a video signal processing method, and a program for suppressing the muting of a video signal during a video processing switching period.

Means for Solving the Problems

[0006] The video signal processing device in this disclosure comprises: a receiving interface for receiving a video signal representing a moving image; a video processing circuit, which generates a first signal by applying one of a plurality of video processing patterns that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit for generating a second signal by capturing the video signal received by the receiving interface; a synthesis circuit for outputting a synthesized signal obtained by combining the first signal and the second signal; and a processor that (a) controls the synthesis circuit to output the first signal as the synthesized signal during a first period; (b) controls the video processing circuit to change the pattern of video processing applied by the video processing circuit during a second period which is not included in the first period; and (c) controls the capture circuit to generate the second signal and controls the synthesis circuit to output the second signal as the synthesized signal during the period of change. [Effects of the Invention]

[0007] The video signal processing device in this disclosure can suppress muting of the video signal during the video processing switching period. [Brief explanation of the drawing]

[0008] [Figure 1] This is an explanatory diagram showing the configuration of the system in the embodiment and the configuration of the display device having a processing unit. [Figure 2] This is an explanatory diagram showing a pattern table illustrating multiple video processing patterns in the embodiment. [Figure 3] This is an explanatory diagram showing a time table indicating the time required to change the video processing settings in the embodiment. [Figure 4] This is the first explanatory diagram showing the synthesis process by an adder circuit in the embodiment. [Figure 5] This is a second explanatory diagram showing the synthesis process by an adder circuit in the embodiment. [Figure 6]This is a third explanatory diagram showing the synthesis process by an adder circuit in the embodiment. [Figure 7] This is a flowchart showing the processor's processing when changing the video processing in the embodiment. [Figure 8] This is an explanatory diagram showing an example of processing in the apparatus according to the embodiment. [Figure 9] This is a flowchart showing the processor's processing when changing the video processing in a modified example 2 of the embodiment. [Figure 10] This is an explanatory diagram showing an example of processing in the apparatus in a modified example 2 of the embodiment. [Modes for carrying out the invention]

[0009] (Knowledge that forms the basis of this disclosure) The inventors have found that the following problems arise with respect to the video signal processing device described in the "Background Art" section.

[0010] There is a technology that modifies the video processing applied by a video signal processing unit to a video signal based on the signal received from the transmitting device. For example, the HDMI® (High-Definition Multimedia Interface) 2.1 standard uses the ALLM (Auto Low Latency Mode) function to modify the video processing applied by a video signal processing unit to a video signal based on the signal received from the transmitting device.

[0011] When switching the video processing applied to a video signal, the video signal processing unit may output a video signal containing noise. To suppress the display of a video signal containing noise, the video signal processing unit may mute the video signal during the video processing switching period. When the video signal processing unit changes the video processing in response to receiving a signal from a transmitting device instructing a change in video processing, the timing of that change in video processing may not be based on user instructions. As a result, the video signal may be muted at a time contrary to the user's intention, which may cause the user to feel uncomfortable.

[0012] If the video signal is muted at a timing contrary to the user's intention, it may be recognized as a degradation in the quality of the video signal provided to the user or a malfunction of the video signal processing apparatus.

[0013] The present disclosure provides a video signal processing apparatus, a video signal processing method, and a program for suppressing muting of a video signal during a video processing switching period.

[0014] Hereinafter, the invention obtained from the disclosure of this specification will be exemplified, and the effects and the like obtained from the invention will be described.

[0015] (1) A reception interface that receives a video signal indicating a moving image, a video processing circuit that generates a first signal by performing video processing of one pattern out of a plurality of patterns of video processing that the video processing circuit can perform on the video signal received by the reception interface, a capture circuit that generates a second signal by capturing the video signal received by the reception interface, and a synthesis circuit that outputs a synthesis signal obtained by synthesizing the first signal and the second signal, and a processor that controls (a) the synthesis circuit to output the first signal as the synthesis signal in a first period, (b) controls the video processing circuit to change the pattern of the video processing performed by the video processing circuit in a second period that is a period not included in the first period, and (c) controls the capture circuit to generate the second signal and controls the synthesis circuit to output the second signal as the synthesis signal during the period of the change. A video signal processing apparatus comprising:

[0016] According to the above aspect, since the capture circuit outputs the signal captured during the period when the video processing circuit switches the video processing, the output of the video signal can be maintained even during the period when the video processing circuit switches the video processing. During the period when the video processing circuit switches the video processing, since the video processing circuit does not output a signal, it is possible to avoid outputting a video signal including noise. Therefore, the video signal processing apparatus can suppress the mute of the video signal during the switching period of the video processing.

[0017] (2) The video signal processing apparatus further includes a memory, and the processor controls the capture circuit to store the second signal generated by the capture circuit in the memory. When a first time corresponding to a first delay generated in the video signal by the video processing of the first pattern before the change among the plurality of patterns is different from a second time corresponding to a second delay generated in the video signal by the video processing of the second pattern after the change among the plurality of patterns, during the change period, the synthesis circuit is controlled to output the second signal whose elapsed time since being stored in the memory is a time length between the first time and the second time. The video signal processing apparatus according to (1).

[0018] According to the above aspect, when the delay of the video processing before the change (first delay) is different from the delay of the video processing after the change (second delay), the video signal processing apparatus can output a composite signal so as to reduce the difference in delay between the second signal and the first signals before and after the change. Therefore, the video signal processing apparatus can appropriately change the delay associated with the switching of the video processing while suppressing the mute of the video signal during the switching period of the video processing. In addition, the video signal processing apparatus can also achieve the effect of reducing the discomfort of the user that may occur if the video signal is muted at a timing contrary to the user's intention.

[0019] (3) The video signal processing apparatus according to (2), wherein the processor controls the synthesis circuit such that the elapsed time since the second signal output by the synthesis circuit was stored in the memory changes from the first time to the second time during the period of change.

[0020] According to the above embodiment, when the delay of the video processing before the change (first delay) and the delay of the video processing after the change (second delay) are different, the video signal processing device can output a composite signal while gradually changing the delay times before and after the change by changing the elapsed time of the second signal read out during the change period from the first time to the second time. Therefore, the video signal processing device can appropriately change the delay associated with the switching of video processing while suppressing the muting of the video signal during the video processing switching period.

[0021] (4) The video signal processing apparatus according to any one of (1) to (3), wherein the receiving interface receives an instruction to change the video processing performed by the video processing circuit on the video signal to a lower-latency video processing, and the processor controls the receiving interface to change the video processing performed by the video processing circuit on the video signal to a lower-latency video processing when the receiving interface receives the instruction, in (b) above.

[0022] According to the above embodiment, when the video signal processing device changes the video processing applied to the video signal by the video processing circuit to a lower-latency video processing, it is possible to suppress the muting of the video signal during the video processing switching period.

[0023] (5) The video signal processing apparatus according to any one of (1) to (4), wherein the processor controls the synthesis circuit to generate and output the synthesized signal obtained by mixing the pixel values ​​included in the first signal and the pixel values ​​included in the second signal immediately before or after the period of modification.

[0024] According to the above embodiment, the video signal processing device can suppress abrupt changes in image quality by using a pixel value obtained by mixing the pixel values ​​of each signal when changing the signal output as a composite signal from one of the first signal and the second signal to the other. Therefore, the video signal processing device can suppress abrupt changes in image quality associated with switching video processing while suppressing the muting of the video signal during the video processing switching period.

[0025] (6) The video signal processing apparatus according to any one of (1) to (5), wherein the combining circuit has an OSD combining circuit that combines the second signal with the first signal as an OSD (On-Screen Display) signal.

[0026] According to the above embodiment, the video signal processing device can more easily combine the first signal and the second signal by using an OSD synthesis circuit to combine the first signal and the second signal. Therefore, the video signal processing device can more easily suppress muting of the video signal during the video processing switching period.

[0027] (7) The video signal processing apparatus according to any one of (1) to (6), wherein the synthesis circuit further comprises a mute circuit that switches whether or not to mute the first signal generated by the video processing circuit, and the processor controls the mute circuit to mute the first signal during the period of change.

[0028] According to the above embodiment, the video signal processing device can avoid outputting the first signal, which may contain noise, as a composite signal by muting the first signal during the transition period. In principle, the second signal is output as a composite signal during the transition period, so the first signal is not output as a composite signal. However, if the compositing circuit operates in violation of the above principle for some reason, it may output the first signal, which may contain noise, as a composite signal. By having the above-mentioned mute circuit in the compositing circuit, it is possible to avoid outputting the first signal, which may contain noise, as a composite signal, as described above. Therefore, the video signal processing device can suppress the muting of the video signal during the video processing transition period while suppressing the output of a video signal that may contain noise.

[0029] (8) A video signal processing method performed by a video signal processing device, the video signal processing device comprising: a receiving interface for receiving a video signal representing a moving image; a video processing circuit for generating a first signal by applying one of a plurality of video processing patterns that the video processing circuit can apply to the video signal received by the receiving interface; a capture circuit for generating a second signal by capturing the video signal received by the receiving interface; a synthesis circuit for outputting a synthesized signal obtained by synthesizing the first signal and the second signal; and a processor, wherein the video signal processing method comprises: (a) controlling the synthesis circuit in a first period to output the first signal as the synthesized signal; (b) controlling the video processing circuit in a second period which is a period not included in the first period to change the pattern of video processing applied by the video processing circuit; and (c) controlling the capture circuit to generate the second signal and the synthesis circuit to output the second signal as the synthesized signal during the period of change.

[0030] According to the above embodiment, the same effect as the above-described video signal processing device is achieved.

[0031] (9) A program that causes a computer to execute the video signal processing method described in (8).

[0032] According to the above embodiment, the same effect as the above-described video signal processing device is achieved.

[0033] The embodiments will be described in detail below, with reference to the drawings as appropriate. However, unnecessarily detailed explanations may be omitted. For example, detailed explanations of already well-known matters and redundant explanations of substantially identical configurations may be omitted. This is to avoid the following explanation becoming unnecessarily verbose and to facilitate understanding for those skilled in the art.

[0034] The inventors provide the accompanying drawings and the following description so that those skilled in the art may fully understand the disclosure, and not to limit the subject matter described in the claims.

[0035] (Embodiment) In this embodiment, a video signal processing device (also referred to as a processing device) that suppresses muting of the video signal during the video processing switching period will be described.

[0036] [1 System 1 Configuration] Figure 1 is an explanatory diagram showing the configuration of System 1 in this embodiment and the configuration of the display device 10 having the processing device 10A.

[0037] As shown in Figure 1, System 1 comprises a transmitting device 5 and a display device 10. Alternatively, System 1 can be said to comprise a transmitting device 5 and a processing device 10A.

[0038] The transmitting device 5 is a device that transmits video signals, including moving images, to the display device 10. The communication standard for the video signals transmitted by the transmitting device 5 is, for example, the HDMI® 2.1 standard. The transmitting device 5 may also transmit audio signals to the display device 10 along with the video signals.

[0039] Furthermore, the transmitting device 5 can transmit commands (also called modification commands) to the display device 10 (more specifically, the processing unit 10A) to change the video processing performed on the video signal. The transmitting device 5 can transmit modification commands as communication packets (also called modification command packets).

[0040] The modification instructions may include, for example, instructions to change the video processing performed by the display device 10 on the video signal to a lower-latency video processing or instructions to change it to a higher-latency video processing. Here, we will explain the case where the modification instruction is an instruction to change the video processing performed by the display device 10 on the video signal to a lower-latency video processing as an example.

[0041] Furthermore, "lower latency video processing" can be rephrased as video processing performed with a lower latency than the standard latency and with a shorter processing time than the standard processing time. Similarly, "higher latency video processing" can be rephrased as video processing performed with a higher latency than the standard latency and with a longer processing time than the standard processing time.

[0042] The command to change the video processing applied by the display device 10 to the video signal to a lower-latency video processing is realized, for example, by the ALLM function in the HDMI® 2.1 standard. The timing at which the transmitter 5 sends the change command is, for example, the timing at which the content of the moving image included in the video signal transmitted by the transmitter 5 changes.

[0043] Transmitter 5 is, for example, a game console. In this case, when the game console transmitter 5 switches from a normal video signal to a video signal (for example, a video signal for a fighting game) in which the delay in the user's response to the progress of the moving image has a relatively large impact on the progress of the game, it sends a change command.

[0044] The display device 10 is a device that displays the video signal transmitted by the transmitting device 5 as a moving image. The display device 10 has a processing device 10A that performs video processing on the video signal transmitted by the transmitting device 5.

[0045] The processing unit 10A is a video signal processing unit that suppresses muting of the video signal during the video processing switching period. The processing unit 10A applies video processing to the video signal and displays the processed video signal as an image on the display 16. The processing unit 10A can change the video processing applied to the video signal, and the period during which this change is made is also called the change period.

[0046] [2. Configuration of the display device 10] The display device 10 includes a receiving interface 11, a processor 12, a video processing circuit 13, a synthesis circuit 14A, a display 16, a capture circuit 17, memories 18 and 20, an audio processing circuit 21, and a speaker 22.

[0047] As an example, the synthesis circuit 14A is configured to include a mute circuit 14, an adder circuit 15, and a readout circuit 19, as shown in Figure 1.

[0048] The processing unit 10A corresponds to the part of the display device 10 that includes the receiving interface 11, the processor 12, the video processing circuit 13, the mute circuit 14, the adder circuit 15, the capture circuit 17, the memories 18 and 20, the read circuit 19, and the audio processing circuit 21.

[0049] Furthermore, some or all of the components of the display device 10, including the processor 12, video processing circuit 13, mute circuit 14, adder circuit 15, capture circuit 17, readout circuit 19, and audio processing circuit 21, may be configured as a single-chip LSI (Large Scale Integration) or the like.

[0050] [2-1 Receiving Interface 11] The receiving interface 11 is an interface device that receives a video signal representing a moving image transmitted by the transmitting device 5. The video signal representing a moving image is a signal in which multiple still images (also called frames) that make up the moving image are arranged in the time direction. The receiving interface 11 provides the received video signal to the video processing circuit 13. The components of the display device 10 process the video signal frame by frame.

[0051] When the transmitting device 5 transmits an audio signal, the receiving interface 11 receives the audio signal transmitted by the transmitting device 5 along with the video signal. The receiving interface 11 provides the received audio signal to the audio processing circuit 21.

[0052] Furthermore, the receiving interface 11 receives the modification instruction packet transmitted by the transmitting device 5. The modification instruction packet is an instruction that changes the video processing performed by the video processing circuit 13 on the video signal to a lower-latency video processing method. The transmitting device 5 provides the received modification instruction packet to the processor 12.

[0053] [2-2 Processor 12] The processor 12 is a circuit that controls the circuits of the display device 10. The processor 12 is, for example, a CPU (Central Processing Unit). The processor 12 is connected to the circuits that the display device 10 includes as components by control lines. Note that the control lines connecting the processor 12 and the circuits that the display device 10 includes as components are omitted for the sake of explanation.

[0054] The processor 12 can control the circuits of the display device 10 by executing a predetermined program. This program may be stored in the memory 20 or in another storage device. Examples of circuit control performed by the processor 12 are listed and explained below.

[0055] (1) Determination of the signal to be output as a composite signal The processor 12 determines the output signal that the synthesis circuit 14A will output as a synthesized signal. Specifically, during the first period, the processor 12 controls the synthesis circuit 14A to output the signal generated by the video processing circuit 13 (also called the first signal or main path signal) as a synthesized signal. The first period is the period not included in the second period described below.

[0056] Furthermore, the processor 12 controls the video processing circuit 13 to change the video processing pattern performed by the video processing circuit 13 during periods not included in the first period (also called the second period). The period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period. The change period is included in the second period.

[0057] Then, during the second period, the processor 12 controls the capture circuit 17 to generate a signal (also called a second signal or subpass signal) by capturing the video signal, and controls the synthesis circuit 14A to output the subpass signal as a synthesized signal. As described above, the period during the second period in which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can also be said that during the change period, the processor 12 controls the capture circuit 17 to generate a signal (also called a second signal or subpass signal) by capturing the video signal, and controls the synthesis circuit 14A to output the subpass signal as a synthesized signal.

[0058] (2) Identification of the frames to be played back in the second period The processor 12 controls the capture circuit 17 to store the subpath signal generated by the capture circuit 17 in the memory 18. In this case, if the time (also called the first time) corresponding to the delay (also called the first delay) that occurs in the video signal due to the video processing of the original pattern (also called the first pattern) among the multiple video processing patterns is different from the time (also called the second delay) that occurs in the video signal due to the video processing of the modified pattern (also called the second pattern) among the multiple video processing patterns, the processor 12 controls the synthesis circuit 14A to read out the subpath signal from the memory 18 and output it during the second period, provided that the elapsed time since it was stored in the memory 18 is the length of time between the first and second periods. As described above, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so in the above case, the processor 12 can also be said to control the synthesis circuit 14A to read out the subpath signal from the memory 18 and output it during the change period, provided that the elapsed time since it was stored in the memory 18 is the length of time between the first and second periods.

[0059] At this time, the processor 12 can control the read circuit 19 so that the elapsed time since the subpath signal read by the read circuit 19 from the memory 18 during the change period (in other words, the second period) was stored in the memory 18 changes from the first time to the second time. More specifically, the processor 12 can determine which frame the read circuit 19 will read during the second period so that the playback speed multiplier when the frame read by the read circuit 19 is played back becomes the playback speed multiplier P, and can control the read circuit 19 to read the determined frame.

[0060] The frames that processor 12 plays back in the second period are more specifically identified as follows:

[0061] First, the processor 12 uses the first delay Dpre, the second delay Dpost, and the time Tc required for the setting change to calculate the time Td from when the combining circuit 14A starts outputting the subpath signal until it stops (in other words, the time during which the combining circuit 14A is outputting the subpath signal) using the following equation (Equation 1).

[0062] Td=Tc+Dpost (formula 1)

[0063] Time Td is the time during which the combining circuit 14A outputs a sub-pass signal when no upper or lower limit is set for the playback speed multiplier P, which will be described later.

[0064] Then, the processor 12 uses time Td to calculate the playback speed multiplier (also called simply the multiplier) P of the video signal in the second period using the following equation (2).

[0065] P = 1 + (Dpre - Dpost) / Td (Equation 2)

[0066] Then, the processor 12 identifies the number Fr(n) of the nth frame (where n≧1) of the subpath signal that the read circuit 19 reads from the memory 18 during the second period using the following equation (Equation 3). In equation (3), ROUND() is a function that rounds the value in parentheses, and F0 is the number of the frame output by the adder circuit 15 immediately before the second period.

[0067] Fr(n)=F0+ROUND(P×n) (Formula 3)

[0068] Furthermore, if an upper or lower limit is set for the playback speed multiplier P, the processor 12 can recalculate the playback speed multiplier P as follows.

[0069] In other words, if the playback speed multiplier P calculated in (Equation 2) exceeds the upper limit Pmax, the playback speed multiplier P is set to the upper limit Pmax, and time Td is calculated using (Equation 4) below. Time Td is the time from when the output of the subpath signal starts until when it ends.

[0070] Td=(Dpre-Dpost) / (Pmax-1) (Equation 4)

[0071] By using the time Td shown in (Equation 4), it may be possible to reduce the discomfort that users may experience. The time Td calculated by (Equation 1) above is the minimum necessary time obtained from the time Tc required for the change process and the delay Dpost after the change. If the playback speed multiplier P obtained from this time Td becomes too high (for example, the playback speed multiplier P exceeds Pmax), a longer time Td than the time Td obtained in (Equation 1) can be obtained by calculating time Td in such a way that the playback speed multiplier P is kept at Pmax, as shown in (Equation 4) above. By using the time Td obtained in this way, it will take some time before switching back to the main path, but it has the effect of suppressing an excessive increase in playback speed.

[0072] Furthermore, if the playback speed multiplier P calculated using (Equation 2) falls below the lower limit Pmin, the playback speed multiplier P is set to the lower limit Pmin, and time Td is calculated using (Equation 5) below. Time Td is the time from the start to the end of the output of the subpath signal, as described above.

[0073] Td=(Dpre-Dpost) / (Pmin-1) (Equation 5)

[0074] By using the time Td shown in (Equation 5), it may be possible to reduce the discomfort that the user may experience, similar to the above.

[0075] For example, the upper limit Pmax can be set to around 1.1 to 1.2, and the lower limit Pmin can be set to around 0.8 to 0.9.

[0076] Furthermore, if there is a constraint that the duration of the second period be a predetermined fixed time Tf, then the upper limit Pmax and lower limit Pmin shown in (Equation 6) and (Equation 7) below can be used. Here, Dmax is the maximum difference between the delay Dpre of the video processing before modification and the delay Dpost of the video processing after modification, considering various combinations of the video processing before modification and the video processing after modification. The time Tf can be, for example, about 1 second.

[0077] Pmax=1+Dmax / Tf (Formula 6) Pmin=1-Dmax / Tf (Formula 7)

[0078] (3) Changing the settings of the video processing pattern The processor 12 modifies the settings of the video processing pattern applied to the video signal by the video processing circuit 13. Specifically, when the receiving interface 11 receives a change command packet, the processor 12 controls the video processing applied to the video signal by the video processing circuit 13 to change it to either lower-latency video processing or higher-latency video processing. Here, we will explain as an example the case in which the processor 12 controls the video processing applied to the video signal by the video processing circuit 13 to change it to lower-latency video processing when the receiving interface 11 receives a change command packet.

[0079] Furthermore, the processor 12 can control the adder 15 to generate and output a composite signal having pixel values ​​obtained by mixing the pixel values ​​included in the main pass signal frame and the pixel values ​​included in the sub-pass signal frame immediately before or after the second period. The generation of a composite signal by mixing pixel values ​​will be explained in the modified example below.

[0080] (4) Mute the main path signal The processor 12 controls the mute circuit 14 so that it mutes the main path signal during the second period.

[0081] [2-3 Video Processing Circuit 13] The video processing circuit 13 performs video processing on the video signal received by the receiving interface 11. The video processing circuit 13 then provides the processed video signal to the mute circuit 14. The video processing performed by the video processing circuit 13 on the video signal will be explained in detail later.

[0082] Specifically, the video processing circuit 13 generates a first signal (corresponding to the main path signal) by applying one of several video processing patterns that the video processing circuit 13 can apply to the video signal received by the receiving interface 11. The one video processing pattern that the video processing circuit 13 applies to the video signal can be set by the processor 12.

[0083] When the receiving interface 11 receives a change instruction packet, the video processing circuit 13, under the control of the processor 12, changes the video processing it performs to a lower-latency video processing method.

[0084] [2-4 Synthesis circuit 14A] The synthesis circuit 14A outputs a combined signal obtained by combining the main path signal and the sub-path signal. Specifically, it generates a combined signal by combining the main path signal provided by the video processing circuit 13 and the sub-path signal read from the memory 18. The synthesis circuit 14A then provides the generated combined signal to the display 16.

[0085] The synthesis circuit 14A outputs a main path signal during the first period under the control of the processor 12. Furthermore, the synthesis circuit 14A outputs a sub-path signal during the second period under the control of the processor 12. Since the second period includes a change period, it can also be said that the synthesis circuit 14A outputs a sub-path signal during the change period.

[0086] As an example, the combining circuit 14A is configured to include a mute circuit 14, an adder circuit 15, and a readout circuit 19, as shown in Figure 1. This case will be used as an example in the explanation.

[0087] When the combining circuit 14A outputs the main path signal, the mute circuit 14, the adder circuit 15, and the readout circuit 19 operate as follows.

[0088] The mute circuit 14 outputs the main path signal without muting it.

[0089] The readout circuit 19 does not read out the subpath signals.

[0090] The summing circuit 15 outputs the main pass signal as a combined signal (the opacity r of the sub-pass signal, described later, is set to 0).

[0091] Furthermore, when the combining circuit 14A outputs a sub-pass signal, the mute circuit 14, the adder circuit 15, and the readout circuit 19 operate as follows.

[0092] The mute circuit 14 mutes the main path signal.

[0093] The readout circuit 19 reads out the subpath signal.

[0094] The summing circuit 15 outputs a subpass signal as a composite signal (the opacity r of the subpass signal, described later, is set to 1).

[0095] In addition, another possible configuration of the synthesis circuit 14A is one in which the synthesis circuit 14A includes a memory and a read circuit instead of the mute circuit 14. In this case, the video signal provided by the video processing circuit 13 is stored in the memory 18, and the read circuit reads the video signal stored in the memory and provides it to the adder circuit 15.

[0096] [2-5 Mute Circuit 14] The mute circuit 14, under the control of the processor 12, switches whether or not to mute the main path signal input to the mute circuit 14. If the mute circuit 14 does not mute the input main path signal, it outputs the input main path signal as is. If the mute circuit 14 does mute the input main path signal, it outputs a video signal with all pixels set to black as the main path signal.

[0097] The mute circuit 14, under the control of the processor 12, mutes the main pass signal during the second period, thereby providing the summing circuit 15 with a video signal in which all pixels are black as the main pass signal. As described above, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period within the second period, so it can also be said that the mute circuit 14, under the control of the processor 12, mutes the main pass signal during the change period, thereby providing the summing circuit 15 with a video signal in which all pixels are black as the main pass signal.

[0098] Note that the mute circuit 14 is not essential in the display device 10. If the display device 10 does not have a mute circuit 14, the video processing circuit 13 is connected to the adder circuit 15. By setting the opacity r of the sub-pass signal (more specifically the OSD signal) to 1 in the adder circuit 15, which will be described later, the main-pass signal and the sub-pass signal can be combined in the same way as when the mute circuit 14 mutes the main-pass signal.

[0099] [2-6 Adding Circuit 15] The adder circuit 15 outputs a combined signal obtained by combining the main path signal and the sub-path signal. Specifically, the adder circuit 15 generates a combined signal by combining the main path signal provided by the mute circuit 14 and the sub-path signal provided by the readout circuit 19. The adder circuit 15 then provides the generated combined signal to the display 16.

[0100] Under the control of the processor 12, if the first time corresponding to the first delay caused in the video signal by the first pattern of video processing is different from the second time corresponding to the second delay caused in the video signal by the second pattern of video processing, the adder circuit 15 outputs a sub-pass signal during the second period in which the elapsed time since the data was stored in the memory 18 is the length of time between the first time and the second time. As described above, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so in the above case, it can also be said that the adder circuit 15 outputs a sub-pass signal during the change period in which the elapsed time since the data was stored in the memory 18 is the length of time between the first time and the second time.

[0101] The subpath signal output by the adder circuit 15 is stored in the memory 18 and is read from the memory 18 by the read circuit 19.

[0102] Furthermore, the elapsed time since the sub-pass signal output by the adder circuit 15 during the second period was stored in the memory 18 is controlled by the processor 12 so that it changes from the first time to the second time. As described above, the period during the second period in which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can also be said that the elapsed time since the sub-pass signal output by the adder circuit 15 during the change period was stored in the memory 18 is controlled by the processor 12 so that it changes from the first time to the second time.

[0103] This is based on the read circuit 19 reading the subpath signals from the memory 18 in such a way that the elapsed time since the subpath signals were stored in the memory 18 change from the first time to the second time.

[0104] The adder circuit 15, under the control of the processor 12, can generate and output a composite signal by mixing the pixel values ​​included in the main pass signal and the pixel values ​​included in the sub-pass signal immediately before or after the second period. As described above, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can also be said that the adder circuit 15 can generate and output a composite signal by mixing the pixel values ​​included in the main pass signal and the pixel values ​​included in the sub-pass signal immediately before or after the change period.

[0105] The summing circuit 15 can be implemented by an OSD (On-Screen Display) synthesis circuit. In this case, the OSD synthesis circuit, which is the summing circuit 15, synthesizes the sub-pass signal with the main-pass signal as an OSD (On-Screen Display) signal. Generally, an OSD synthesis circuit is a circuit that superimposes an image-indicating signal (also called an OSD signal), such as channel number or volume, onto the video signal that is the object of display. The opacity of the OSD signal when superimposing the OSD signal onto the video signal can be controlled within the range of 0% to 100%.

[0106] In the display device 10, the OSD synthesis circuit functions as an adder 15 by using the main pass signal as the "video signal to be displayed" and the sub-pass signal as the OSD signal. The pixel value D included in the frame of the synthesized signal output by the adder 15 is a pixel value obtained by mixing the pixel value Sm included in the frame of the main pass signal and the pixel value Ss included in the frame of the sub-pass signal according to the following equation (Equation 8). In equation (8), r is the opacity of the OSD signal. The pixel value D can also be said to be a weighted average with the weight of the pixel value Sm being (1-r) and the weight of the pixel value Ss being r.

[0107] D=Sm×(1-r)+Ss×r (Formula 8)

[0108] For example, if the opacity of the sub-pass signal, which is an OSD signal, is 0%, the combined signal output by the adder circuit 15 will be the same as the main-pass signal. This corresponds to the fact that if r=0 in (Equation 8), then (Equation 9) is obtained below.

[0109] D=Sm (formula 9)

[0110] Furthermore, for example, if the opacity of the sub-pass signal, which is an OSD signal, is 100%, the combined signal output by the adder circuit 15 will be the same as the sub-pass signal. This corresponds to the fact that if r=1 in (Equation 8), then (Equation 10) is obtained below.

[0111] D=Ss (Equation 10)

[0112] Furthermore, for example, if the opacity of the sub-pass signal, which is an OSD signal, is 50%, the pixel values ​​of the frame of the composite signal output by the summing circuit 15 will be the average of the pixel values ​​included in the frame of the main-pass signal and the pixel values ​​included in the frame of the sub-pass signal. This corresponds to the following (Equation 11) when r=0.5 in (Equation 8).

[0113] D=0.5×Sm+0.5×Ss (Formula 11)

[0114] [2-7 Display 16] The display 16 displays the combined signal provided by the summing circuit 15 as an image. The display 16 may be, for example, a liquid crystal panel or an organic electro-luminescence (OLED) panel. The image displayed by the display 16 is expected to be viewed by the user.

[0115] [2-8 Capture Circuit 17] The capture circuit 17 generates a subpath signal by capturing the video signal received by the receiving interface 11. The capture circuit 17 stores the generated subpath signal in the memory 18. The capture circuit 17 stores the subpath signal generated by capturing under the control of the processor 12 in the memory 18.

[0116] [2-9 Memory 18] Memory 18 is a storage device capable of storing video signals. Memory 18 may be a volatile storage device such as DRAM (Dynamic Random Access Memory), or a non-volatile storage device such as an HDD (Hard Disk Drive) or SSD (Solid State Drive). Subpath signals generated by the capture circuit 17 are stored in memory 18 by the capture circuit 17, and the stored subpath signals are read out by the read circuit 19.

[0117] [2-10 Readout Circuit 19] The read circuit 19 reads the subpath signal stored in the memory 18. The read circuit 19 provides the read subpath signal to the adder 15.

[0118] The read circuit 19, under the control of the processor 12, sequentially reads the frames that the processor 12 has determined to be read by the read circuit 19.

[0119] Under the control of the processor 12, if the first time corresponding to the first delay caused in the video signal by the first pattern of video processing is different from the second time corresponding to the second delay caused in the video signal by the second pattern of video processing, the read circuit 19 can read a subpath signal from the memory 18 during the second period, where the elapsed time since it was stored in the memory 18 is the length of time between the first and second times, and provide it to the adder circuit 15. As described above, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so in the above case, the read circuit 19 can also be said to read a subpath signal from the memory 18 during the change period, where the elapsed time since it was stored in the memory 18 is the length of time between the first and second times, and provide it to the adder circuit 15.

[0120] Furthermore, under the control of the processor 12, the read circuit 19 can read subpath signals from memory 18 in such a way that the elapsed time since the subpath signals were stored in memory 18 change from the first time to the second time. As described above, the period during which the video processing circuit 13 changes the video processing pattern corresponds to the change period, so it can also be said that the read circuit 19 can read subpath signals from memory 18 in such a way that the elapsed time since the subpath signals were stored in memory 18 change from the first time to the second time.

[0121] The number that identifies the frame to be read by the read circuit 19 from the memory 18 is calculated using the above (Equation 3). When the read circuit 19 does not read a frame, it does not provide anything to the adder circuit 15. In this case, the read circuit 19 may provide the adder circuit 15 with an image in which all pixels are black.

[0122] Furthermore, the read circuit 19 may perform video decompression processing on the read frame. This assumes that the capture circuit 17 has compressed the frame before storing it in memory 18. By doing so, the amount of video signal data stored in memory 18 can be reduced, thereby reducing the capacity of memory 18.

[0123] The read circuit 19 may be included in the adder circuit 15 as a function of the adder circuit 15. In other words, the adder circuit 15 may read the subpath signals stored in the memory 18.

[0124] [2-11 Memory 20] Memory 20 is a storage device capable of storing various types of information. Memory 20 is a non-volatile storage device and may be, for example, flash memory. Memory 20 stores a program read by the processor 12, information indicating the pattern of video processing (see Figure 2), and information indicating the time required to change the settings of video processing (see Figure 3).

[0125] [2-12 Audio Processing Circuit 21] The audio processing circuit 21 performs audio processing on the audio signal received by the receiving interface 11. The audio processing circuit 21 then provides the processed audio signal to the speaker 22.

[0126] The audio processing circuit 21 may include a buffer (not shown). In that case, the audio processing circuit 21 can adjust the timing of providing the processed audio signal to the speaker 22 by temporarily storing the audio signal in the buffer.

[0127] Specifically, the audio processing circuit 21 determines the number Sr(n) of the nth audio signal to be read from the buffer in the second period using the following equation (Equation 12). In equation (12), S0 is the number of the audio signal output by the audio processing circuit 21 immediately before the second period.

[0128] Sr(n)=S0+ROUND(P×n) (Equation 12)

[0129] The audio signal that the audio processing circuit 21 outputs to the speaker 22 during the second period may be an audio signal having a timestamp T as shown in (Equation 13) below. In (Equation 13), Tn is the elapsed time from the start of playback of the audio signal, and Tpast is the elapsed time from the start of the second period to the current time.

[0130] T = Tn + Dpre + Tpast × P (Equation 13)

[0131] It is assumed that the audio signal received by the receiving interface 11 has a timestamp pre-assigned. For example, if the video signal standard is MPEG2-TS, PTS (Presentation Time Stamp) can be used as the timestamp.

[0132] [2-13 Speaker 22] Speaker 22 outputs the audio signal provided by the audio processing circuit 21 as sound. The sound output by speaker 22 is expected to be heard by the user.

[0133] [3. Image Processing] The video processing performed by the video processing circuit 13 on the video signal will be explained in detail with reference to Figure 2.

[0134] Figure 2 is an explanatory diagram showing a pattern table illustrating multiple video processing patterns in this embodiment.

[0135] The pattern table shown in Figure 2 shows the type of video processing and the delay associated with each of the multiple video processing patterns. The pattern table shown in Figure 2 is stored, for example, in memory 20, and the processor 12 can read and use it as needed.

[0136] The video processing patterns are the video processing patterns that the video processing circuit 13 can apply to the video signal. Each pattern indicates whether or not the video processing that the video processing circuit 13 can apply to the video signal is applied to the video signal.

[0137] The pattern table specifically indicates whether the video processing circuit 13 performs video processing on the video signal (indicated as "on") or does not perform video processing (indicated as "off") in that pattern.

[0138] Figure 2 shows, as an example of the video processing that the video processing circuit 13 can apply to the video signal, high-definition video processing (indicated as "high-definition").

[0139] The video processing circuit 13 generally includes multiple types of video processing means for improving or enhancing the image quality of the video. Examples of multiple types of video processing means include noise reduction, sharpness correction, gradation correction, or gamma correction.

[0140] In the video processing pattern 1 shown in Figure 2 (i.e., video processing with high-quality video processing turned off), the time required for video processing is reduced compared to when all of the above-mentioned video processing methods are applied to the video signal, by not applying some of the above-mentioned video processing methods to the video signal. In this way, low-latency video processing is achieved.

[0141] On the other hand, in the video processing of Pattern 2 shown in Figure 2 (i.e., video processing with high-quality video processing enabled), video processing using all of the above-mentioned video processing means is applied to the video signal. In this way, high-quality video processing is achieved.

[0142] Furthermore, the video processing that the video processing circuit 13 can perform on the video signal is not limited to high-definition video processing, but may include other types of video processing.

[0143] Low-latency video processing can refer to video processing specifically designed for games, or in other words, video processing specifically for gameplay, and is often referred to as "game mode." On the other hand, high-quality video processing can refer to video processing for applications where low latency is not required.

[0144] The delay column indicates the delay that occurs in the video signal when the video processing circuit 13 applies the video processing pattern to the video signal. The delay is expressed in units of time, for example, but is not limited to this; it may also be expressed in units of frames. The delay expressed in units of time and the delay expressed in units of frames can be converted to each other by multiplication or division using the frame rate (fps) of the video signal. Specifically, the delay expressed in units of frames is calculated by multiplying the delay expressed in units of time by the frame rate. Conversely, the delay expressed in units of frames is calculated by dividing the delay expressed in units of frames by the frame rate.

[0145] As shown in Figure 2, Pattern 1 is a video processing pattern in which high-quality video processing is not applied to the video signal (off). Pattern 1 is a video processing pattern in which low-latency video processing is applied compared to when high-quality video processing is applied (Pattern 2). The delay that occurs in the video signal when the video processing circuit 13 applies video processing of Pattern 1 is D1.

[0146] Pattern 2 is a video processing pattern in which high-quality video processing is applied to the video signal (on). Pattern 2 is a video processing pattern in which high-latency video processing is applied compared to the case of low-latency video processing (Pattern 1). The delay that occurs in the video signal when the video processing circuit 13 applies the video processing of Pattern 2 is D2, and D2 is greater than D1.

[0147] Figure 3 is an explanatory diagram showing a time table indicating the time Tc required for changing the video processing settings in this embodiment. The time table shown in Figure 3 is stored, for example, in memory 20, and can be read and used by the processor 12 as needed.

[0148] Figure 3 shows the time Tc required to change settings for each type of video processing. The time required to change settings is the time required to set the video processing of that type as the video processing performed by the video processing circuit 13.

[0149] Figure 3 shows that T1 is the time required to set the video processing circuit 13 to perform low-latency video processing, and T2 is the time required to set the video processing circuit 13 to perform high-quality video processing.

[0150] [4 Synthesis Process] The synthesis process performed by the adder circuit 15 on the main path signal and the sub-path signal will be explained in detail with reference to Figures 4 to 6.

[0151] Figure 4 is a first explanatory diagram showing the synthesis process by the adder circuit 15 in this embodiment.

[0152] Figure 4 illustrates the concept of the synthesis process when the adder circuit 15 outputs the main path signal as the synthesized signal.

[0153] The summing circuit 15 combines the sub-pass signal with the main-pass signal with an opacity of 0% (see Figure 4(a)). In this case, r=0 in (Equation 8), and the pixel value D included in the frame of the combined signal is equal to the pixel value Sm included in the frame of the main-pass signal (see (Equation 9)).

[0154] For example, if the main pass signal contains the character image "A" and the sub-pass signal contains the character image "B", then the combined signal will contain the character image "A" (see Figure 4(b)).

[0155] Figure 5 is a second explanatory diagram showing the synthesis process by the adder circuit 15 in this embodiment.

[0156] Figure 5 illustrates the concept of the synthesis process when the adder circuit 15 outputs a subpass signal as the synthesized signal.

[0157] The summing circuit 15 combines the main pass signal with the sub-pass signal with 100% opacity (see Figure 5(a)). In this case, r=1 in (Equation 8), and the pixel value D included in the frame of the combined signal is equal to the pixel value Ss included in the frame of the sub-pass signal (see (Equation 10)).

[0158] For example, if the main pass signal contains the character image "A" and the sub-pass signal contains the character image "B", then the combined signal will contain the character image "B" (see Figure 5(b)).

[0159] Figure 6 is a third explanatory diagram showing the synthesis process by the adder circuit 15 in this embodiment.

[0160] Figure 6 illustrates the concept of the synthesis process when the adder circuit 15 outputs a frame having pixel values ​​obtained by mixing the pixel values ​​contained in the frame of the main pass signal and the pixel values ​​contained in the frame of the sub-pass signal as a composite signal.

[0161] The summing circuit 15 combines the main pass signal with the sub-pass signal with an opacity of 50% (see Figure 6(a)). In this case, by setting r=0.5 in (Equation 8), the pixel value D included in the frame of the combined signal becomes the average value of the pixel value Sm included in the frame of the main pass signal and the pixel value Ss included in the frame of the sub-pass signal (see (Equation 11)).

[0162] For example, if the main pass signal contains an image of the character "A" and the sub-pass signal contains an image of the character "B", the composite signal will contain an image in which the "A" and "B" characters are superimposed (see Figure 6(b)).

[0163] [5 Processing] The processing of System 1, configured as described above, will now be explained.

[0164] Figure 7 is a flowchart showing the processing of the processor 12 when changing the video processing in this embodiment.

[0165] In step S101, the processor 12 determines whether the receiving interface 11 has received a modification instruction packet. If it determines that the receiving interface 11 has received a modification instruction packet (Yes in step S101), it proceeds to step S102; otherwise (No in step S101), it repeats step S101. In other words, the processor 12 waits in step S101 until the receiving interface 11 receives a modification instruction packet.

[0166] In step S102, the processor 12 calculates the playback speed multiplier P of the subpath signal. The playback speed multiplier P of the subpath signal calculated by the processor 12 is used in step S105, which will be described later.

[0167] In step S103, the processor 12 controls the capture circuit 17 to start capturing the received signal and storing the captured received signal in the memory 18. The capture circuit 17 starts capturing the received signal and storing the captured received signal in the memory 18 under the control of the processor 12.

[0168] In step S104, the processor 12 waits for a time corresponding to the delay Dpre. During this waiting time, a number of frames corresponding to the delay Dpre are captured by the capture circuit 17 and stored in the memory 18.

[0169] In step S105, the processor 12 controls the readout circuit 19 to change the playback speed multiplier P of the subpath signal. The readout circuit 19 changes the playback speed multiplier P of the subpath signal under the control of the processor 12. The readout circuit 19 changing the playback speed multiplier P of the subpath signal means that the readout circuit 19 starts sequentially determining the frames to read out so that the playback speed multiplier when the frames read out by the readout circuit 19 are played back becomes the playback speed multiplier P calculated in step S102.

[0170] In step S106, the processor 12 controls the read circuit 19 to start reading the frames stored in the memory 18 as subpath signals. Under the control of the processor 12, the read circuit 19 starts reading the frames determined in step S105 from the frames stored in the memory 18 as subpath signals. The read circuit 19 provides the read subpath signals to the adder 15.

[0171] In step S106A, the processor 12 controls the adder circuit 15 to start outputting the subpath signal as a combined signal. The adder circuit 15 starts outputting the subpath signal as a combined signal under the control of the processor 12.

[0172] In step S107, the processor 12 controls the mute circuit 14 to start muting the main path signal. The mute circuit 14 starts muting the main path signal (i.e., the signal output by the video processing circuit 13) under the control of the processor 12.

[0173] Steps S105, S106, S106A, and S107 only need to be performed between the time immediately after the completion of the waiting period in step S104 and the time when the adder circuit 15 actually outputs the subpath signal as a combined signal (time t7 in the specific example described later), and the order in which these steps are performed is arbitrary.

[0174] In step S108, the processor 12 changes the settings of the video processing circuit 13. The time required to change the settings of the video processing circuit 13 is shown in Figure 3.

[0175] In step S109, the processor 12 controls the mute circuit 14 to stop muting the main path signal. The mute circuit 14 stops muting the main path signal (i.e., the signal output by the video processing circuit 13) under the control of the processor 12. The stopping of muting the main path signal occurs after waiting for a time Td from the start of the setting change of the video processing circuit 13 (step S108).

[0176] In step S110, the processor 12 controls the adder circuit 15 to start outputting the main path signal as a combined signal. Under the control of the processor 12, the adder circuit 15 starts outputting the main path signal (i.e., the signal output by the mute circuit 14) as a combined signal.

[0177] In step S111, the processor 12 controls the capture circuit 17 to stop capturing the received signal. The capture circuit 17 stops capturing the received signal under the control of the processor 12. The processor 12 also controls the read circuit 19 to stop reading the frames stored in the memory 18. The read circuit 19 stops reading the frames stored in the memory 18 under the control of the processor 12.

[0178] Steps S109, S110, and S111 only need to be performed between the time immediately after the setting change in step S108 is completed and the time when the adder circuit 15 actually outputs the main path signal as a combined signal (time t11 in the specific example described later), and the order in which these steps are performed is arbitrary.

[0179] As shown in Figure 7, the display device 10 can suppress the muting of the video signal during the video processing switching period through a series of processes.

[0180] An example of System 1's processing will be explained using a specific example of a video signal.

[0181] Figure 8 is an explanatory diagram showing an example of processing by the display device 10 in this embodiment.

[0182] Figure 8 shows an example of the processing performed by the display device 10 when the video processing circuit 13 changes its setting from applying video processing pattern 2 to the video signal to applying video processing pattern 1. The processing shown in Figure 8 is performed by the display device 10 using a pattern table (see Figure 2) and a time table (see Figure 3), for example, by performing a series of processes shown in the flowchart shown in Figure 7.

[0183] Figure 8 shows, from top to bottom, the frames received by the receiving interface 11, the frames output by the video processing circuit 13, the frames output by the mute circuit 14, the frames captured by the capture circuit 17, the frames read out by the readout circuit 19, and the frames output by the adder circuit 15. In Figure 8, the rightward direction indicates the passage of time.

[0184] Here, delays Dpre and Dpost are expressed in terms of frames. Specifically, delay Dpre is delay D1 in pattern 1, which is 3 frames. Delay Dpost is delay D2 in pattern 2, which is 1 frame.

[0185] Furthermore, let's assume that the time Tc required for the setting change is equivalent to 3 frames (i.e., 3 / frame rate). The time Td is calculated using the above (Equation 1) as follows, which is equivalent to 4 frames.

[0186] Td = 3 + 1 = 4

[0187] Furthermore, the playback speed multiplier P is calculated as 1.5 using the above (Equation 2), as shown below.

[0188] P = 1 + (3 - 1) / 4 = 1.5

[0189] Furthermore, each frame of the video signal is assigned a sequential number (···, -2, -1, 0, 1, 2, ···). The sequential number assigned to each frame of the video signal indicates the playback order of that frame, or the reception order of the receiving interface 11, and has no other meaning.

[0190] At time t0 shown in Figure 8, the receiving interface 11 receives frame #0. Since the delay Dpre is 3, the video processing circuit 13 outputs frame #-3 at time t0. The mute circuit 14 acquires frame #-3 output by the video processing circuit 13 and outputs the acquired frame #-3 without muting it. The frame output by the adder circuit 15 at time t0 is frame #-3, the same as the main path signal frame output by the mute circuit 14. Note that at time t0, the capture circuit 17 and the readout circuit 19 are not operating and therefore do not output anything.

[0191] When the receiving interface 11 receives a change command packet at time t3 (Yes in step S101), the capture circuit 17 starts capturing the received signal and storing it in memory 18 at time t4 (step S103). The frames stored in memory 18 are frames #4, #5, and #6.

[0192] Subsequently, after a waiting period equivalent to the delay Dpre (step S104), at time t7, the display device 10 performs a process to switch the signal output by the adder circuit 15 from the main path signal to the sub-path signal.

[0193] Specifically, the processor 12 sets the playback speed multiplier for the subpass signal (step S105), the readout circuit 19 starts reading frames from the memory 18 and providing them to the adder circuit 15 under the control of the processor 12 (step S106), and the adder circuit 15 also starts outputting the subpass signal as a composite signal under the control of the processor 12 (step S106A). At this time, the processor 12 sets the opacity r of the OSD signal of the adder circuit 15 to 1, so that the adder circuit 15 can output the subpass signal frame as a composite signal. The frame output by the adder circuit 15 is the subpass signal provided by the readout circuit 19, and is frame #5. Also, at time t7, the mute circuit 14 starts muting under the control of the processor 12 (step S107).

[0194] Furthermore, the fact that the frame output by the adder circuit 15 is frame #5 can be derived using (Equation 3) above as follows.

[0195] In the above equation (3), the frame output by the adder circuit 15 immediately before the second period is frame #3, so we set F0 = 3. Also, the frame that the read circuit 19 reads from memory 18 at time t7 is the first frame in the second period, so we set n = 1. Thus, the frame Fr(1) that the read circuit 19 reads from memory 18 at time t7 is calculated to be frame #5 as shown below.

[0196] Fr(1)=3+ROUND(1.5×1)=5

[0197] Subsequently, after the mute circuit 14 starts muting under the control of the processor 12, the processor 12 instructs the video processing circuit 13 to change the settings (step S108). The video processing circuit 13 changes the settings under the control of the processor 12 during time Tc.

[0198] During the second period (times t7 to t11), from time t8 onwards, the readout circuit 19 reads frames #6, #8, and #9 from memory 18 according to the playback speed multiplier P and provides them to the adder circuit 15, which then outputs the frames.

[0199] Furthermore, the fact that the frames output by the adder circuit 15 are frames #6, #8, and #9 can be derived using (Equation 3) above as follows.

[0200] In the above (Equation 3), the frames that the read circuit 19 reads from the memory 18 at times t8, t9, and t10 are the second, third, and fourth frames of the second period, respectively. Thus, the frames Fr(2), Fr(3), and Fr(4) that the read circuit 19 reads from the memory 18 at times t8, t9, and t10 are calculated to be frames #6, #8, and #9, respectively, as shown below.

[0201] Fr(2) = 3 + ROUND(1.5 × 2) = 6 Fr(3) = 3 + ROUND(1.5 × 3) = 8 Fr(4) = 3 + ROUND(1.5 × 4) = 9

[0202] Subsequently, at time t10, after the time Tc required for the setting change has elapsed since the mute circuit 14 started muting, the processor 12 instructs the video processing circuit 13 to start video processing with the changed settings. Under the control of the processor 12, the video processing circuit 13 starts video processing with the changed settings for the frame (specifically frame #10) at time t10.

[0203] At time t11, the display device 10 performs a process to switch the signal output by the adder circuit 15 from a subpath signal to a main path signal.

[0204] Specifically, the mute circuit 14 stops muting under the control of the processor 12 (step S109), and the adder circuit 15 starts outputting the frames of the main path signal as a composite signal under the control of the processor 12 (step S110). At this time, the adder circuit 15 can output the frames of the main path signal as a composite signal because the processor 12 sets the opacity r of the OSD signal of the adder circuit 15 to 0. Also, the readout circuit 19 stops reading frames under the control of the processor 12 (step S111).

[0205] The video processing circuit 13 outputs frames (frames #10 and #11) with the modified video processing applied from time t11 onwards. As described above, the video processing circuit 13 starts the modified video processing at time t10, and since Dpost=1, the video processing circuit 13 completes the video processing of frame #10 and outputs it at time t11.

[0206] As described above, the display device 10 can reproduce frames at a playback speed multiplier P during the second period, and further output a composite signal delayed by one frame relative to the received frame after the second period (i.e., from time t11 onwards). In this way, the display device 10 can continue to output the video signal even during the video processing switching period, thus suppressing the muting of the video signal.

[0207] (Modification 1 of the embodiment) In this modified example, a processing device that suppresses muting of the video signal during the video processing switching period will be described.

[0208] In the above embodiment, the display device 10 (more specifically, the processing device 10A) changed the video processing of the video processing circuit 13 in response to a change command from the transmitting device 5. However, even if there is no change command from the transmitting device 5, the processing of the video processing circuit 13 can be changed.

[0209] For example, the display device 10 can also change the video processing of the video processing circuit 13 when the user instructs the display device 10 to change the video processing through an operation menu provided by the display device 10. For example, the operation menu may include an option to turn low-latency video processing on or off. It is assumed that the user will refer to the provided operation menu and perform an operation on the display device 10 to select whether to turn low-latency video processing on or off. The display device 10 can receive the above operation from the user and change the processing of the video processing circuit 13 according to the above operation. In that case, instead of receiving a change command packet in step S101 (see Figure 7), the processor 12 can execute the processing from step S102 onwards if it receives the user's operation using the remote control light receiver or touch panel detection unit.

[0210] Thus, the change command in the present invention can be implemented by the user through operation of an operation menu, even in a configuration consisting only of the display device 10 (in other words, a configuration without the transmission device 5).

[0211] Furthermore, when a user instructs a change in video processing via the operation menu, the change command may be a command to change to low-latency video processing, or a command to change to video processing for RGB video signals.

[0212] Generally, image quality improvement methods such as noise reduction, sharpness correction, or gradation correction are image processing applied to YUV video signals, which are represented using color difference signals. However, reducing the UV signal portion, which contains color information, can reduce the required memory capacity of the memory 18. When the receiving interface 11 receives an RGB video signal output by a personal computer or the like, a mode may be provided to bypass image quality improvement methods such as noise reduction, sharpness correction, or gradation correction to prevent such reduction of color information. When a user issues a command to change to image processing for the RGB video signal using the operation menu, the above-mentioned image quality improvement methods are bypassed, which consequently changes the delay time of the video processing circuit 13.

[0213] In this case, in order to prevent the display device 10 from muting the video signal during the video processing switching period, RGB processing may be added to the types of video processing shown in Figures 2 and 3. Specifically, in the pattern table shown in Figure 2, a new video processing pattern is added that shows a combination of the on / off state of video processing for RGB video signals and the on / off state of high-quality video processing, and a delay Dx is added to each of the newly added video processing patterns. In addition, in the time table shown in Figure 3, a time T3 is added to change the video signal to apply video processing for RGB video signals.

[0214] Thus, the modification instruction in this invention also includes instructions that result in a change in the delay time of the video processing circuit 13, and does not necessarily have to be a modification instruction that instructs low-latency video processing.

[0215] (Modified example 2 of the embodiment) In this modified example, a processing device that suppresses muting of the video signal during the video processing switching period will be described. The processing device in this modified example uses an adder circuit to generate a composite signal by mixing pixel values ​​to more effectively suppress muting of the video signal during the video processing switching period.

[0216] The configuration of the display device 10 in this modified example is the same as that of the display device 10 in the above embodiment.

[0217] However, the addition circuit 15 differs from the display device 10 in the above embodiment in that it generates and outputs a composite signal by mixing the pixel values ​​included in the frame of the main pass signal and the pixel values ​​included in the frame of the sub-pass signal immediately before or after the second period. Alternatively, the addition circuit 15 may generate and output a composite signal by mixing the pixel values ​​included in the frame of the main pass signal and the pixel values ​​included in the frame of the sub-pass signal both immediately before and after the second period.

[0218] Specifically, the summing circuit 15 can create a composite signal from the N frames prior to the second period, having pixel values ​​obtained by mixing the pixel values ​​contained in the main pass signal frame and the pixel values ​​contained in the sub-pass signal frame. N is, for example, an integer between 1 and 30, but is not limited to this. In this case, the opacity r of the sub-pass signal may be set to a constant value (for example, 50%) for the N frames. Alternatively, the opacity r may be gradually changed from a relatively low value to a relatively high value for the N frames. For example, if N is 3, the opacity of the first, second, and third frames may be changed to 25%, 50%, and 75%, respectively.

[0219] Furthermore, the summing circuit 15 can make the M frames after the second period a composite signal having pixel values ​​obtained by mixing the pixel values ​​contained in the main pass signal frame and the pixel values ​​contained in the sub-pass signal frame. M is an integer between 1 and 30, for example, but is not limited to this. M may be the same as or different from N, which is the number of frames before the second period. For the M frames, the opacity r of the sub-pass signal may be set to a constant value (for example, 50%). Alternatively, for the M frames, the opacity r may be gradually changed from a relatively high value to a low value. For example, if M is 3, the opacity of the first, second, and third frames may be changed to 75%, 50%, and 25%, respectively.

[0220] Furthermore, the processor 12 identifies the number Fr(n) of the nth frame (where n≧1) of the subpath signal that the read circuit 19 reads from the memory 18 during the second period using the following equation (Equation 14). Equation (14) is used in place of Equation (3). In Equation (14), N is the number of frames output by the adder circuit 15 before the second period that are composite signals having pixel values ​​obtained by mixing the pixel values ​​included in the main path signal frames and the pixel values ​​included in the subpath signal frames. The other variables are the same as those in Equation (3).

[0221] Fr(n)=F0+N+ROUND(P×n) (Equation 14)

[0222] The processing of the display device 10 in this modified example will be explained. Here, we will explain using the example where the number of frames before the second period and the number of frames after the second period are the same N. We will also explain using the example where the opacity r for N frames is a constant value of 50%.

[0223] Figure 9 is a flowchart showing the processing of the processor 12 when changing the video processing in this modified example. In Figure 9, the same reference numerals as those used for the processing of the display device 10 in the above embodiment (see Figure 7) are used, and detailed explanations may be omitted.

[0224] When the receiving interface 11 receives a modification instruction packet transmitted by the transmitting device 5, the processor 12 controls the process to calculate the regeneration speed multiplier P of the subpath signal, start capturing the received signal and storing it in memory 18, and wait for a delay time equivalent to Dpre (steps S101 to S104).

[0225] In step S104A, the processor 12 controls the summing circuit 15 to output a composite signal obtained by combining N frames of the sub-pass signal with the main-pass signal at 50% opacity.

[0226] Subsequently, the processor 12, similar to the processor 12 in the above embodiment, starts outputting the subpath signal as a composite signal and controls the video processing circuit 13 to change its settings (steps S105 to S109).

[0227] In step S109A, the processor 12 changes the playback speed multiplier P of the subpath signal to 1 (i.e., 1x speed).

[0228] In step S109B, the processor 12 controls the summing circuit 15 to output a composite signal obtained by combining N frames of the sub-pass signal with the main-pass signal at 50% opacity.

[0229] Subsequently, the processor 12, similar to the processor 12 in the above embodiment, starts outputting the main path signal as a composite signal and stops capturing by the capture circuit 17 (steps S110 to S111).

[0230] Through the series of processes shown in Figure 9, the display device 10 suppresses muting of the video signal during the video processing switching period.

[0231] Figure 10 is an explanatory diagram showing an example of processing by the display device 10 in a modified example of this embodiment.

[0232] Figure 10 shows an example of the processing of the display device 10 when the video processing circuit 13 changes its setting from applying video processing pattern 2 to the video signal to applying video processing pattern 1, similar to Figure 8.

[0233] The display mode of the frames in Figure 10, the delays Dpre and Dpost, the times Tc and Td, and the playback speed multiplier P are the same as those in Figure 8. Furthermore, the number of frames N that form a composite signal having pixel values ​​obtained by mixing the pixel values ​​contained in the frames of the main pass signal and the pixel values ​​contained in the frames of the sub-pass signal is set to 1.

[0234] When the receiving interface 11 receives a change command packet at time t3 (Yes in step S101), at time t4, the capture circuit 17 begins capturing the received signal and storing it in memory 18 under the control of the processor 12 (step S103). The frames stored in memory 18 are frames #4, #5, and #6.

[0235] Subsequently, after waiting for a delay equivalent to Dpre (step S104), the adder circuit 15, under the control of the processor 12, outputs a composite signal (frame #4) obtained by combining one sub-path signal frame with the main-path signal from time t7 (step S104A).

[0236] Subsequently, the read circuit 19, under the control of the processor 12, begins reading a frame from the memory 18 and provides it to the adder circuit 15. The frame output by the adder circuit 15 is frame #6 (i.e., the subpath signal) provided by the read circuit 19.

[0237] Subsequently, after the mute circuit 14 starts muting (step S107), the video processing circuit 13 changes the settings under the control of the processor 12 (step S108). The setting change requires Tc (i.e., time equivalent to 3 frames).

[0238] During the second period (times t8 to t12), the readout circuit 19 reads frames #6, #7, #9, and #10 from the memory 18 according to the playback speed multiplier P and provides them to the adder circuit 15, which then outputs the frames.

[0239] Furthermore, the fact that the frames output by the adder circuit 15 are frames #6, #7, #9, and #10 can be derived using (Equation 14) above as follows.

[0240] In the above (Equation 14), the frames read by the read circuit 19 from the memory 18 at times t8, t9, t10, and t11 are the 1st, 2nd, 3rd, and 4th frames of the second period, respectively. Also, N=1. Thus, the frames Fr(1), Fr(2), Fr(3), and frame Fr(4) read by the read circuit 19 from the memory 18 at times t8, t9, t10, and t11 are calculated to be frames #6, #7, #9, and #10, respectively, as shown below.

[0241] Fr(1) = 3 + 1 + ROUND(1.5 × 1) = 6 Fr(2) = 3 + 1 + ROUND(1.5 × 2) = 7 Fr(3) = 3 + 1 + ROUND(1.5 × 3) = 9 Fr(4) = 3 + 1 + ROUND(1.5 × 4) = 10

[0242] Subsequently, under the control of the processor 12, the adder circuit 15 outputs a composite signal (frame #11) by combining one sub-pass signal frame with the main-pass signal from time t12 (step S109B). After that, the video processing circuit 13 applies the modified video processing to the received frame from time t13 onwards, and the adder circuit 15 outputs the video-processed frame (frame #12).

[0243] Also, at time t12, the mute circuit 14 stops muting under the control of the processor 12 (step S109). Also, at time t13, the capture circuit 17 stops capturing under the control of the processor 12, and the read circuit 19 stops reading under the control of the processor 12 (step S111).

[0244] As described above, the display device 10 can reproduce frames at a playback speed multiplier P during the second period, and further output a composite signal delayed by one frame relative to the received frame after the second period (i.e., after time t12). In addition, since the display device 10 outputs a composite signal having pixel values ​​obtained by mixing the pixel values ​​contained in the main pass signal frame and the pixel values ​​contained in the sub-pass signal frame before and after the second period, it is possible to suppress abrupt changes in image quality when switching the composite signal, even if the video signal formats of the main pass signal and the sub-pass signal are different (for example, when the resolution decreases during capture).

[0245] In this way, the display device 10 can suppress the muting of the video signal during the video processing switching period.

[0246] As described above, embodiments and modifications have been explained as examples of the technology in this disclosure. For this purpose, accompanying drawings and a detailed description have been provided.

[0247] Therefore, the components described in the attached drawings and detailed descriptions may include not only those components essential for solving the problem, but also components that are not essential for solving the problem, provided that the above implementation is illustrated. For this reason, the mere presence of these non-essential components in the attached drawings and detailed descriptions should not immediately be interpreted as meaning that they are essential.

[0248] Furthermore, since the embodiments described above are for illustrative purposes of the technology described herein, various modifications, substitutions, additions, omissions, etc., can be made within the scope of the claims or their equivalents. [Industrial applicability]

[0249] This disclosure can be used as a video signal processing device that applies a video processing process selected from multiple video processing methods to a video signal and outputs the result. [Explanation of Symbols]

[0250] 1 System 5. Transmitter 10 Display device 10A Processing Unit 11 Receiving Interface 12 processors 13. Video Processing Circuit 14. Mute circuit 14A synthesis circuit 15 Adding Circuit 16 displays 17 Capture Circuit 18, 20 memory 19 Readout Circuit 21 Audio Processing Circuit 22 speakers

Claims

1. A receiving interface that receives video signals showing moving images, A video processing circuit comprising: a video processing circuit that generates a first signal by applying one of a plurality of video processing patterns that the video processing circuit can apply to the video signal received by the receiving interface; A capture circuit that generates a second signal by capturing the video signal received by the receiving interface, A combining circuit that outputs a combined signal obtained by combining the first signal and the second signal, (a) During the first period, control the combining circuit so that the first signal is output as the combined signal, (b) In a second period which is not included in the first period, the video processing circuit is controlled to change the pattern of video processing performed by the video processing circuit, and (c) A processor that controls the capture circuit to generate the second signal during the period of modification, and controls the synthesis circuit to output the second signal as the synthesized signal, The aforementioned processor, Immediately before or after the period of the aforementioned change, the combining circuit is controlled to generate and output the combined signal obtained by mixing the pixel values ​​included in the first signal and the pixel values ​​included in the second signal. Video signal processing device.

2. The video signal processing device also includes memory, The aforementioned processor, The capture circuit is controlled to store the second signal generated by the capture circuit in the memory. If the first time corresponding to the first delay in the video signal caused by the video processing of the first pattern before the modification among the multiple patterns is different from the second time corresponding to the second delay in the video signal caused by the video processing of the second pattern after the modification among the multiple patterns, the synthesis circuit is controlled to output the second signal within the modification period, such that the elapsed time since it was stored in the memory is the length between the first time and the second time. The video signal processing device according to claim 1.

3. The aforementioned processor, The combining circuit is controlled such that the elapsed time since the second signal output by the combining circuit was stored in the memory changes from the first time to the second time during the aforementioned modification period. The video signal processing apparatus according to claim 2.

4. The aforementioned receiving interface is The video processing circuit receives a command to change the video processing it performs on the video signal to a lower-latency video processing, The aforementioned processor, When the receiving interface receives the command, in (b), the video processing circuit controls the video processing it performs on the video signal to change to a lower-latency video processing method. The video signal processing apparatus according to any one of claims 1 to 3.

5. The aforementioned synthesis circuit includes an OSD (On-Screen Display) synthesis circuit that synthesizes the second signal with the first signal as an OSD signal. The video signal processing apparatus according to any one of claims 1 to 3.

6. The aforementioned synthesis circuit further, The system includes a mute circuit that switches whether or not to mute the first signal generated by the video processing circuit, The aforementioned processor, During the period of the aforementioned modification, the mute circuit is controlled to mute the first signal. The video signal processing apparatus according to any one of claims 1 to 3.

7. A video signal processing method performed by a video signal processing device, The aforementioned video signal processing device is A receiving interface that receives video signals showing moving images, A video processing circuit comprising: a video processing circuit that generates a first signal by applying one of a plurality of video processing patterns that the video processing circuit can apply to the video signal received by the receiving interface; A capture circuit that generates a second signal by capturing the video signal received by the receiving interface, A combining circuit that outputs a combined signal obtained by combining the first signal and the second signal, Equipped with a processor, The aforementioned video signal processing method is performed by the processor, (a) During the first period, control the combining circuit so that the first signal is output as the combined signal, (b) In a second period which is not included in the first period, the video processing circuit is controlled to change the pattern of video processing performed by the video processing circuit. (c) During the period of the modification, the capture circuit is controlled to generate the second signal, and the synthesis circuit is controlled to output the second signal as the synthesized signal. (d) Control the combining circuit to generate and output the combined signal obtained by mixing the pixel values ​​included in the first signal and the pixel values ​​included in the second signal immediately before or after the period of the change. Video signal processing method.

8. A program that causes a computer to execute the video signal processing method described in claim 7.

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