sensor
The sensor system addresses disconnection faults by propagating detection operations and signals in both directions, ensuring continued output and robustness despite signal line disconnections, with reduced circuit size and enhanced flexibility.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOYOTA CHUO KENKYUSHO
- Filing Date
- 2022-07-27
- Publication Date
- 2026-04-28
AI Technical Summary
Existing sensor systems face issues where disconnection faults in signal lines can lead to the loss of detection signals from all sensors, rendering them inoperable.
A sensor system comprising N sensor circuits and N interface circuits with serial connections, where detection operations and output signals are propagated in both directions, allowing continued output even with disconnections, using resistors to maintain signal integrity.
Ensures robustness by allowing continued output of detection signals from sensors before a disconnection point, reducing circuit size, and enhancing design flexibility.
Smart Images
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Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to a sensor capable of enhancing robustness during disconnection.
Background Art
[0002] Patent Document 1 discloses a sensor system including a sensor array having a plurality of sensors arranged in a two-dimensional array and an X-Y decoder. By scanning the sensor array with the X-Y decoder, a plurality of sensors can be read out.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] There are cases where detection signals of a plurality of sensors are serially output using a single signal line. In this case, if a disconnection fault occurs at any part of the signal line, it may become impossible to output the detection signals of all sensors.
Means for Solving the Problems
[0005] One embodiment of a sensor disclosed herein is a sensor comprising N sensor circuits (where N is a natural number greater than or equal to 2) and N interface circuits, each corresponding to one of the N sensor circuits. The N sensor circuits have a serial connection in which the sensor output logic signal of the K-th sensor circuit (where K is a natural number greater than or equal to 1 and equal to N-1) is input as the sensor input logic signal of the K+1-th sensor circuit. The N interface circuits have a serial connection in which the interface output logic signal of the K-th interface circuit is input as the interface input logic signal of the K-1-th interface circuit. Each of the N sensor circuits is a circuit that starts a detection operation in response to the inversion of the sensor input logic signal, and ends the detection operation by inverting the sensor output logic signal after a detection time proportional to the amount detected by the sensor circuit has elapsed since the sensor input logic signal was inverted. Each of the N interface circuits is a circuit that inverts the interface output logic signal in response to the inversion of the sensor output logic signal of the corresponding sensor circuit. The detection operation of the K+1-th sensor circuit is started in response to the inversion of the sensor output logic signal of the K-th sensor circuit and the termination of the detection operation of the K-th sensor circuit. The first interface circuit outputs an interface output logic signal that continuously outputs signals indicating the N detection times detected by the Nth sensor circuit from the first sensor circuit.
[0006] This sensor allows the detection operation of the sensor circuits to be propagated to subsequent stages, such as the Kth, K+1th, and so on. Furthermore, the operation of outputting an interface output logic signal indicating the detection time can be propagated to preceding stages, such as the Kth, K-1st, and so on. The interface output logic signals indicating the detection time of all sensor circuits can be serially output from the first interface circuit. In other words, the direction of detection operation and the direction of detection signal propagation can be reversed. This allows the output of the sensor circuits preceding the disconnection to be serially output even if a disconnection occurs in the serial connection path of N sensor circuits or N interface circuits. Since a disconnection does not cause all sensor circuits to lose their detection signals, robustness in the event of a disconnection is enhanced.
[0007] The K-th interface circuit may receive the sensor output logic signal output from the K-th sensor circuit and the interface output logic signal output from the K+1-th interface circuit. The interface output logic signal output from the K-th interface circuit may also be input to the K-1-th interface circuit. In response to the sensor output logic signal of the K-th sensor circuit inverting and the detection operation of the K-th sensor circuit ending, an interface output logic signal indicating the detection time detected by the K-th sensor circuit may be output from the K-th interface circuit to the K-1-th interface circuit.
[0008] The system may further include N first resistors, each corresponding to one of the N interface circuits. Each of the N interface circuits may include a logic circuit. The input terminal of the K-th logic circuit may be connected to the output terminal of the K-th sensor circuit and the output terminal of the K+1-th logic circuit. The connection path between the input terminal of the K-th logic circuit and the output terminal of the K+1-th logic circuit may be connected to a first predetermined voltage point via the K-th first resistor.
[0009] The system may further include N second resistors, each corresponding to one of the N sensor circuits. The connection path between the output terminal of the Kth sensor circuit and the input terminal of the K+1th sensor circuit may be connected to a second predetermined voltage point via the Kth second resistor.
[0010] Each of the N sensor circuits may have a variable capacitance. The detected quantity may be the capacitance of the variable capacitance. The detection time may be a time proportional to the capacitance of the variable capacitance.
[0011] Each of the N sensor circuits may be equipped with a diode element. The detected quantity may be the reverse leakage current value of the diode element. The detection time may be a time inversely proportional to the reverse leakage current value.
[0012] Each of the N sensor circuits may be equipped with a variable resistor. The detected quantity may be the resistance value of the variable resistor. The detection time may be a time proportional to the resistance value of the variable resistor. [Brief explanation of the drawing]
[0013] [Figure 1] This is a schematic block diagram of sensor 1 in Example 1. [Figure 2] This is a circuit diagram of the sensor circuit SC(K). [Figure 3] This is a waveform diagram illustrating the operation of the sensor circuit SC(K). [Figure 4] This waveform diagram illustrates the normal operation of sensor 1. [Figure 5] This waveform diagram illustrates the operation of sensor 1 when the wire is broken. [Figure 6] Block diagram showing an overview of sensor 100 in the comparative example. [Figure 7] This is a schematic block diagram of sensor 1a according to Example 2. [Modes for carrying out the invention] [Examples]
[0014] (Configuration of Sensor 1) Figure 1 shows Sensor 1 according to Embodiment 1. Sensor 1 is an example of an A / D conversion circuit that converts various physical quantities into digital values. Sensor 1 comprises an input / output circuit IO and N sensor units SU(1) to SU(N) (where N is a natural number greater than or equal to 2).
[0015] The input / output circuit IO includes an input buffer IB, an output buffer OB, and a NOR circuit NR(0). The start signal ST, which is input to the input / output circuit IO, is input to the sensor circuit SC(1) via the input buffer IB. The start signal ST and the output signal DO(1) are input to the NOR circuit NR(0). The serial output signal Sout, which is output from the NOR circuit NR(0), is output to the outside via the output buffer OB. The input / output circuit IO inverts the serial output signal Sout when the start signal ST or the output signal DO(1) is inverted. The start signal ST is a signal that controls the on / off state of sensor 1. When the start signal ST is at a low level, sensor 1 performs detection operations. When the start signal ST is at a high level, sensor 1 stops.
[0016] The input / output circuit IO and sensor units SU(1) to SU(N) are equipped with a positive power line PL and a negative power line NL. The positive power line PL is connected to the power supply voltage section VDD and supplies the power supply voltage (e.g., 3.3V). The positive power line PL is connected to the reference voltage section GND and supplies the reference voltage (e.g., 0V).
[0017] Each of the N sensor units SU(1) to SU(N) includes sensor circuits SC(1) to SC(N), NOR circuits NR(1) to NR(N), resistance elements RD(1) to RD(N), and resistance elements RU(1) to RU(N). The NOR circuits NR(1) to NR(N) are provided corresponding to each of the sensor circuits SC(1) to SC(N). The sensor circuits SC(1) to SC(N) constitute a sensor array 20. A start signal ST is input to the first-stage sensor circuit SC(1). The output signal OS(1) output from the sensor circuit SC(1) is input to the second-stage sensor circuit SC(2). Similarly hereinafter, in the sensor array 20, the output signal of the previous-stage sensor circuit is input as the input signal of the next-stage sensor circuit. That is, it has a serial connection in which the output signal OS(K) of the K-th (K is a natural number from 1 to N - 1) sensor circuit SC(K) is input as the sensor input logic signal of the (K + 1)-th sensor circuit SC(K + 1).
[0018] The output circuit 30 includes NOR circuits NR(0) to NR(N). The start signal ST and the output signal DO(1) are input to the NOR circuit NR(0). The output signal OS(1) and the output signal DO(2) are input to the NOR circuit NR(1). The output signal DO(1) is output from the NOR circuit NR(1). The output signal DO(1) is a logic signal represented by the following formula.
Equation
[0019] Similarly hereinafter, the output signal OS(K) output from the K-th sensor circuit SC(K) and the output signal DO(K + 1) output from the (K + 1)-th NOR circuit NR(K + 1) are input to the K-th NOR circuit NR(K). The output signal DO(K) output from the K-th NOR circuit NR(K) is input to the (K - 1)-th NOR circuit NR(K - 1). That is, it has a serial connection in which the output signal DO(K) of the K-th NOR circuit NR(K) is input as the input logic signal of the (K - 1)-th NOR circuit NR(K - 1). The output signal DO(K) is a logic signal represented by the following formula.
number
[0020] As can be seen from the above equation, the NOR circuit NR(K) inverts the output signal OS(K) when the output signal OS(K) input from the sensor circuit SC(K) is inverted, or when the output signal OS(K+1) input from the next NOR circuit NR(K+1) is inverted. In other words, the NOR circuit NR(K) is disabled when a high-level output signal OS(K) is input, and the output is fixed at a low level. On the other hand, it is enabled when a low-level output signal OS(K) is input. It then operates as a NOT circuit, inverting the output signal OS(K+1) input from the subsequent stage to generate the output signal OS(K), and outputting the generated output signal OS(K) to the preceding stage.
[0021] The final stage, the Nth NOR gate NR(N), receives the output signal OS(N) from the Nth sensor gate SC(N). The output signal DO(N) from the NOR gate NR(N) is input to the N-1th NOR gate NR(N-1). The output signal DO(N) is a logic signal shown in the following equation.
number
[0022] The NOR gate NR(0) of the first stage input / output circuit IO outputs the serial output signal Sout. The serial output signal Sout is a logic signal shown in the following equation.
number
[0023] The connection path CP(1) between the output terminal of NOR circuit NR(2) and the input terminal of NOR circuit NR(1) is connected to the negative power line NL via resistor element RD(1). Similarly, the connection path CP(K) between the output terminal of NOR circuit NR(K+1) and the input terminal of NOR circuit NR(K) is connected to the negative power line NL via resistor element RD(K). The input terminal of NOR circuit NR(N) is also connected to the negative power line NL via resistor element RD(N). Resistor elements RD(1) to RD(N) function as pull-down resistors. When the connection path CP(1) to CP(N) is broken, each of the resistor elements RD(1) to RD(N) can fix the input voltage of NOR circuits NR(1) to NR(N) to a low level. This prevents the input of the NOR circuit NR at the broken point from becoming floating and causing malfunction. Therefore, it is possible to reliably disable the sensor unit SU at the broken point. Furthermore, by fixing it to a low level, when a disconnection fault occurs in the connection path CP(K), the inversion of the output signal OS(K) output from the sensor circuit SC(K) can be propagated to the output signal DO(K) output from the NOR circuit NR(K).
[0024] The connection path SP(1) between the output terminal of sensor circuit SC(1) and the input terminal of sensor circuit SC(2) is connected to the positive power line PL via the resistor element RU(1). Similarly, the connection path SP(K) between the output terminal of sensor circuit SC(K) and the input terminal of sensor circuit SC(K+1) is connected to PL via the resistor element RU(K). The output terminal of sensor circuit SC(N) is also connected to the positive power line PL via the resistor element RU(N). The resistor elements RU(1) to RU(N) function as pull-up resistors. Each of the resistor elements RU(1) to RU(N) can fix the output voltage of sensor circuits SC(1) to SC(N) at a high level when the connection path SP(1) to SP(N) is broken. This prevents malfunctions.
[0025] (Configuration and operation of sensor circuit SC(K)) The circuit configuration of the Kth sensor circuit SC(K) is explained using Figure 2. Here, K is a natural number between 1 and N-1. The sensor circuit SC(K) comprises a pMOS transistor TP, an nMOS transistor TN, a resistor RN, a variable capacitance element CN(K), and a Schmitt trigger inverter SI. The resistor RN has a fixed resistance value R0. The variable capacitance element CN(K) has a capacitance value CV(K) to be detected.
[0026] The gate terminals of the pMOS transistor TP and the nMOS transistor TN are input to the output signal OS(K-1) output from the preceding sensor circuit SC(K-1). The source terminal and back gate terminal of the pMOS transistor TP are connected to the power supply voltage VDD. The source terminal and back gate terminal of the nMOS transistor TN are connected to the reference voltage GND. One end of the resistor RN is connected to the drain terminal of the pMOS transistor TP. The other end of the resistor RN is connected to the drain terminal of the nMOS transistor TN at the connection node NN. The connection node NN is connected to one end of the variable capacitor CN(K) and the input terminal of the Schmitt trigger inverter SI. The other end of the variable capacitor CN(K) is connected to the reference voltage GND. The input terminal of the Schmitt trigger inverter SI is input to the voltage signal AN(K). The positive power supply terminal of the Schmitt trigger inverter SI is connected to the power supply voltage VDD, and the negative power supply terminal is connected to the reference voltage GND.
[0027] The operation of the sensor circuit SC(K) will be explained using the waveform diagram in Figure 3. Before time t(K-1), the output signal OS(K-1) input to the sensor circuit SC(K) is at a high level, the pMOS transistor TP is in the off state, and the nMOS transistor TN is in the on state. At this time, the voltage signal AN(K) is 0[V], and the output signal OS(K) output from the Schmitt trigger inverter SI is at a high level.
[0028] When the output signal OS(K-1) switches from a high level to a low level at time t(K-1), the pMOS transistor TP turns on and the nMOS transistor TN turns off, and the variable capacitance element CN(K) starts charging, causing the voltage signal AN(K) to start rising. At this time, assuming that the on-resistance of the pMOS transistor TP is sufficiently small to be negligible compared to the resistance value R0 of the resistor element RN, the voltage signal AN(K) rises with a slope of "VDD / (R0×CV(K))" (see region A1).
[0029] When the voltage signal AN(K) reaches the rising logic threshold voltage VT1 of the Schmitt trigger inverter SI at time t(K), the output signal OS(K) inverts from a high level to a low level (see arrow Y1). The detection time DT(K) from time t(K-1) to t(K) is proportional to "R0 × CV(K)". Therefore, the detection time DT(K) corresponds to the output of the capacitance value CV(K) that is being detected. Subsequently, the voltage signal AN(K) rises until it reaches the power supply voltage VDD.
[0030] In other words, the sensor circuit SC(K) is a circuit that starts detection operation in response to the inversion of the input logic signal, output signal OS(K-1). After the input logic signal is inverted, and a detection time DT(K) proportional to the detected capacitance value CV(K) has elapsed, the circuit terminates detection operation by inverting the output logic signal, output signal OS(K).
[0031] From time t(K) onward, while the output signal OS(K-1) remains at a low level, the voltage signal AN(K) maintains the power supply voltage VDD, and the output signal OS(K) remains at a low level. Then, at time tres, when the output signal OS(K-1) switches from a low level to a high level, the pMOS transistor TP turns off and the nMOS transistor TN turns on. Since the on-resistance of the nMOS transistor TN is sufficiently small, the charge stored in the variable capacitance element CN(K) is discharged instantaneously, and the voltage signal AN(K) changes to 0[V] (see arrow Y2). In response to this, the output signal OS(K) output from the Schmitt trigger inverter SI inverts from a low level to a high level (see arrow Y3).
[0032] (Normal operation of sensor 1) The normal operation of sensor 1 will be explained using the waveform diagram in Figure 4. Figure 4 describes the case where the number of connection stages of sensor unit SU is even (i.e., when N is even). At times prior to time t(0) in Figure 4, the start signal ST is high level, and sensor 1 is in the off state. When sensor 1 is in the off state, the output signal OS(1) of the first stage sensor circuit SC(1) is high level. As shown in Figure 1, since the input of each sensor circuit is the output of the preceding sensor circuit, the output signals OS(1) to OS(N) of all sensor circuits are also high level. Also, as can be seen from the output circuit 30 in Figure 1, the output signals DO(1) to DO(N) of all NOR circuits NR are low level. The serial output signal Sout is also low level.
[0033] When the start signal ST is switched from a high level to a low level at time t(0), the detection operation of sensor 1 begins. In response to the transition of the start signal ST to a low level, charging of the variable capacitance element CN(1) in the first-stage sensor circuit SC(1) begins. At the same time, the serial output signal Sout output from the NOR circuit NR(0) inverts from a low level to a high level (arrow Y10).
[0034] At time t(1), when the output signal OS(1) of the first-stage sensor circuit SC(1) switches from a high level to a low level, the output signal DO(1) from the NOR circuit NR(1) switches to a high level (arrow Y11), causing the serial output signal Sout to invert from a high level to a low level (arrow Y12). The detection time DT(1) between both edges of the serial output signal Sout is proportional to the capacitance value CV(1) detected by the first-stage sensor circuit SC(1). Also, in response to the output signal OS(1) switching to a low level at time t(1), charging of the variable capacitance element CN(2) in the second-stage sensor circuit SC(2) begins.
[0035] Similarly, at time t(2), when the output signal OS(2) of the second-stage sensor circuit SC(2) switches from a high level to a low level, the output signal DO(2) from the NOR circuit NR(2) switches to a high level (arrow Y13). Therefore, the output signal DO(1) from the NOR circuit NR(1) switches to a low level (arrow Y14), and the serial output signal Sout inverts from a low level to a high level (arrow Y15). The detection time DT(2) between both edges of the serial output signal Sout is proportional to the capacitance value CV(2) detected by the second-stage sensor circuit SC(2). Also at time t(2), charging of the variable capacitance element CN(3) in the third-stage sensor circuit SC(3) begins.
[0036] Similarly, when the output signal OS(K) of the preceding sensor circuit SC(K) switches from a high level to a low level, the serial output signal Sout undergoes its K+1th inversion, and simultaneously, the variable capacitance element CN(K+1) in the next sensor circuit SC(K+1) begins charging. In this way, the detection operation is passed from the preceding stage to the succeeding stage in the order of serial connection. Furthermore, when the output signal OS(K) of sensor circuit SC(K) inverts and the detection operation of sensor circuit SC(K) ends, the output signal DO(K), which indicates the detection time detected by sensor circuit SC(K), is output from NOR circuit NR(K) to NOR circuit NR(K-1). In this way, the detection time is passed from the later stage to the earlier stage in the order of serial connection.
[0037] Then, at time t(N), when the output signal OS(N) of the final, Nth stage sensor circuit SC(N) switches from a high level to a low level, the output signal DO(N) from the NOR circuit NR(N) switches to a high level (arrow Y16). This edge inversion propagates from the NOR circuit NR(N-1) to the NOR circuit NR(0), causing the serial output signal Sout to invert to a high level (arrow Y17). This completes the detection operation of the N sensor circuits SC(1) to SC(N). The serial output signal Sout then continuously outputs signals indicating the N detection times DT(1) to DT(N) detected by the N sensor circuits SC(1) to SC(N).
[0038] Subsequently, at any given time tres, when the start signal ST is switched from a low level to a high level, all output signals OS(1) to OS(N) are reset to their initial high level (region A2). Also, all output signals DO(1) to DO(N), and the serial output signal Sout are reset to their initial low level (region A3). In other words, the transition of the start signal ST to a high level turns sensor 1 off.
[0039] As described above, in this embodiment, sensor 1 can initiate the detection operation of the K+1 sensor circuit when the detection operation of the K-th sensor circuit is completed. Therefore, the detection operation can proceed autonomously in the order of the serially connected sensor circuits SC(1) to SC(N). Since it is possible to read N sensor signals from N sensor circuits without the need for a scan circuit such as an XY decoder, the circuit size of sensor 1 can be reduced.
[0040] (Operation when sensor 1 is disconnected) The operation of sensor 1 when the wire is broken will be explained using the waveform diagram in Figure 5. In this embodiment, we will explain the case where the connection path CP(1) between the output terminal of NOR circuit NR(2) and the input terminal of NOR circuit NR(1) is broken, as shown in the broken wire region BA in Figure 1. When the connection path CP(1) is broken, the signal CP(1) of the connection path CP(1) input to NOR circuit NR(1) is fixed to a low level by the resistor element RD(1).
[0041] The operation up to time t(1) is the same as the normal operation shown in Figure 4, so the explanation is omitted. At time t(1), when the output signal OS(1) of the first-stage sensor circuit SC(1) switches from high level to low level, the output signal DO(1) output from the NOR circuit NR(1) switches to high level (arrow Y21), and the serial output signal Sout inverts from high level to low level (arrow Y22). As a result, the detection time DT(1) is output by the serial output signal Sout.
[0042] At time t(2), the output signal OS(2) of the sensor circuit SC(2) switches from a high level to a low level, and as a result, the output signal DO(2) is also inverted. However, the signal CP(1) input to the NOR circuit NR(1) is fixed at a low level by the resistor RD(1) due to a break in the connection path CP(1), and therefore is not inverted (arrow Y23). Consequently, the output signal DO(1) output from the NOR circuit NR(1) is also not inverted (arrow Y24), and therefore the serial output signal Sout is also not inverted (arrow Y25).
[0043] As explained above, if the connection path CP(K) of the NOR circuit NR(K) is broken, the propagation of output signals DO(K+1)~DO(N) from the NOR circuits NR(K+1)~NR(N) downstream of NOR circuit NR(K) is blocked by NOR circuit NR(K). As a result, only the detection time DT(1)~DT(K) upstream of the NOR circuit NR(K) where the break occurred is output by the serial output signal Sout.
[0044] (assignment) The problem will be explained using the comparative example sensor 100 shown in Figure 6. The comparative example sensor 100 differs from sensor 1 of this embodiment (Figure 1) in the configuration of the output circuit 130. Specifically, it is equipped with NAND circuits ND(1) to ND(N) instead of NOR circuits NR(1) to NR(N). In the comparative example's output circuit 130, the serial output signal Sout is output from the final stage sensor unit SU(N). Also, in sensor 100, the resistive elements RU and RD, the positive power line PL, and the negative power line NL are not shown. The other operating details of sensor 100 are the same as those of sensor 1, so the explanation will be omitted.
[0045] In the comparative example sensor 100, the propagation direction of the output signal OS from the sensor array 20 and the propagation direction of the output signal DO from the output circuit 130 are both in the same direction, from the preceding stage to the succeeding stage. Therefore, the serial output signal Sout is output from the final stage sensor unit SU(N). Consequently, if a break in the connection path CP(1) to CP(N-1) occurs, the output circuit 130, which is located downstream of the break, will inevitably become inoperable, and all detection times DT(1) to DT(N) will not be obtained.
[0046] (effect) In the sensor 1 of this embodiment, the output signal OS that starts the detection operation of the sensor circuit can be propagated from the preceding stage to the succeeding stage, such as the Kth, K+1th, and so on. In addition, the output signal DO indicating the detection time can be propagated from the succeeding stage to the preceding stage, such as the Kth, K-1st, and so on. Therefore, both the input of the start signal ST and the output of the serial output signal Sout can be aggregated to the first NOR circuit NR(1). As a result, even if a break in the connection path CP(1) to CP(N-1) occurs and the output circuit 30 located after the break becomes inoperable, the output circuit 30 located before the break can be used to output all the detection times DT detected by the sensor circuit SC located before the break. That is, if a break in the connection path CP(K) occurs, the detection times DT(1) to DT(K) detected by the sensor circuits SC(1) to SC(K-1) located before the break can be output as the serial output signal Sout. This makes it possible to improve robustness in the event of a wire break.
[0047] In the technology described herein, sensor 1 can be constructed by serially connecting sensor units SU(1) to SU(N) having the same structure. Therefore, additional sensor units SU can be added to the final sensor unit SU(N), or the sensor unit can be separated at an intermediate sensor unit SU(K). Since the number of connected sensor units SU can be freely changed, the design flexibility of sensor 1 can be increased. [Examples]
[0048] Figure 7 shows sensor 1a according to Example 2. The output circuit 30 of Example 1 (Figure 1) was a circuit configuration example that included NOR circuits NR(0) to NR(N). On the other hand, the output circuit 30a of Example 2 (Figure 7) is a circuit configuration example that includes NAND circuits NDa(0) to NDa(N). Note that the same reference numerals are used for parts that are the same as in Example 1, and their explanations are omitted. In addition, parts that are unique to Example 2 are distinguished by adding "a" to the end of the reference numeral.
[0049] The output circuit 30a includes NAND circuits NDA(1) to NDA(N) and inverters INVa(0) to INVa(N). The NAND circuit NDA(K) receives the start signal ST via inverter INVa(0) and the output signal DO(1). The K-th NAND circuit NDA(K) receives the output signal OS(K) output from the K-th sensor circuit SC(K) via inverter INVa(K), and also receives the output signal DO(K+1) output from the K+1-th NOR circuit NR(K+1). The output signal DO(K) output from the K-th NAND circuit NDA(K) is input to the K-1-th NAND circuit NDA(K-1). The output signal DO(K) is a logic signal shown in the following equation.
number
[0050] The NAND gate NDa(0) of the first stage input / output circuit IO outputs the serial output signal Sout. The serial output signal Sout is a logic signal shown in the following equation.
number
[0051] The connection path CP(K) between the output terminal of NAND circuit NDA(K+1) and the input terminal of NAND circuit NDA(K) is connected to the positive power supply line PL via the resistor element RUa(K). Resistor elements RUa(1) to RUa(N) function as pull-up resistors. When the connection path CP(1) to CP(N) is broken, each of the resistor elements RUa(1) to RUa(N) can fix the input voltage of NAND circuits NDA(1) to NDA(N) to a high level. Thus, malfunctions can be prevented.
[0052] The operation of the output circuit 30a in Example 2 is the same as that of the output circuit 30 in Example 1, so a description will be omitted. The sensor 1a in Example 2 can also be used to obtain the same effects as the sensor 1 in Example 1.
[0053] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness.
[0054] (modified version) Figure 5 illustrates the case where the number of connection stages in the sensor unit SU is even (N is even). In this case, at time t(N), the serial output signal Sout is inverted to a low level. On the other hand, when the number of connection stages in the sensor unit SU is odd (N is odd), at time t(N), the serial output signal Sout is inverted to a high level. In other words, the only difference between an even and an odd number of connection stages is the direction of the inversion of the final edge of the serial output signal Sout.
[0055] Figure 5 illustrates the case where a break occurs in the connection path CP(K) of the NOR circuit NR(K). Similarly, even if a break occurs in the connection path SP(K) of the sensor circuit SC(K), the output signal OS(K) can be fixed at a high level by the resistor element RU(K). This allows only the detection time DT of the stage preceding the sensor circuit SC(K) where the break occurred to be output by the serial output signal Sout.
[0056] In the sensor circuit SC(K) shown in Figure 2, the capacitance of the variable capacitance element CN is used as the physical quantity to be detected. However, the system is not limited to this configuration, and various physical quantities can be used as the detection target. For example, the detection current of the photodiode PD or the resistance value of the variable resistor element may be used as the detection target.
[0057] The NOR circuit NR and NAND circuit ND are examples of interface circuits. The output signal OS is an example of a sensor output logic signal. The output signal DO is an example of an interface output logic signal. The serial output signal Sout is an example of an interface output logic signal output from the first interface circuit. The resistor element RD is an example of a first resistor. The reference voltage element GND is an example of a first predetermined voltage element. The resistor element RU is an example of a second resistor. The power supply voltage element VDD is an example of a second predetermined voltage element.
[0058] The following are embodiments of this technology. [Aspect 1] A sensor comprising N sensor circuits (where N is a natural number greater than or equal to 2) and N interface circuits provided corresponding to each of the N sensor circuits, The N sensor circuits have a serial connection in which the sensor output logic signal of the K-th sensor circuit (where K is a natural number between 1 and N-1) is input as the sensor input logic signal of the K+1-th sensor circuit. The N interface circuits have a serial connection in which the interface output logic signal of the K-th interface circuit is input as the interface input logic signal of the K-1-th interface circuit. Each of the N sensor circuits is a circuit that starts a detection operation in response to the inversion of the sensor input logic signal, and ends the detection operation by inverting the sensor output logic signal after a detection time proportional to the amount detected by the sensor circuit has elapsed since the inversion of the sensor input logic signal. Each of the N interface circuits is a circuit that inverts the interface output logic signal in response to the inversion of the sensor output logic signal of the corresponding sensor circuit. In response to the inversion of the sensor output logic signal of the K-th sensor circuit and the termination of the detection operation of the K-th sensor circuit, the detection operation of the K+1-th sensor circuit is initiated. A sensor in which the first interface circuit outputs an interface output logic signal that continuously outputs N signals indicating the detection time detected by the Nth sensor circuit from the first sensor circuit. [Aspect 2] The K-th interface circuit receives the sensor output logic signal output from the K-th sensor circuit and the interface output logic signal output from the K+1-th interface circuit as inputs. The interface output logic signal output from the K-th interface circuit is input to the K-1th interface circuit. The sensor according to embodiment 1, wherein, in response to the inversion of the sensor output logic signal of the K-th sensor circuit and the termination of the detection operation of the K-th sensor circuit, the interface output logic signal indicating the detection time detected by the K-th sensor circuit is output from the K-th interface circuit to the K-1 interface circuit. [Aspect 3] Each of the N interface circuits is further provided with N first resistors, Each of the N interface circuits is equipped with a logic circuit. The input terminal of the K-th logic circuit is connected to the output terminal of the K-th sensor circuit and the output terminal of the K+1-th logic circuit. The sensor according to embodiment 1 or 2, wherein the connection path between the input terminal of the kth logic circuit and the output terminal of the (k+1)th logic circuit is connected to a first predetermined voltage point via the kth first resistor. [Aspect 4] Each of the N sensor circuits is further provided with N second resistors, The sensor according to any one of embodiments 1 to 3, wherein the connection path between the output terminal of the kth sensor circuit and the input terminal of the K+1th sensor circuit is connected to a second predetermined voltage point via the kth second resistor. [Aspect 5] Each of the N sensor circuits is equipped with a variable capacitance, The detected amount is the capacitance of the variable capacitance, The sensor according to any one of embodiments 1 to 4, wherein the detection time is a time proportional to the capacitance of the variable capacitance. [Aspect 6] Each of the N sensor circuits is equipped with a diode element. The detected amount is the reverse leakage current value of the diode element. The sensor according to any one of embodiments 1 to 4, wherein the detection time is a time inversely proportional to the reverse leakage current value. [Aspect 7] Each of the N sensor circuits is equipped with a variable resistor. The detected amount is the resistance value of the variable resistor, The sensor according to any one of embodiments 1 to 4, wherein the detection time is a time proportional to the resistance value of the variable resistor. [Explanation of Symbols]
[0059] 1: Sensor SC(1)~(N): Sensor circuit NR(1)~(N): NOR circuit OS(1)~(N): Output signal DO(1)~(N): Output signal DT(1)~(N): Detection time Sout: Serial output signal
Claims
1. A sensor comprising N sensor circuits (where N is a natural number greater than or equal to 2) and N interface circuits provided corresponding to each of the N sensor circuits, The N sensor circuits have a serial connection in which the sensor output logic signal of the K-th sensor circuit (where K is a natural number between 1 and N-1) is input as the sensor input logic signal of the K+1-th sensor circuit. The N interface circuits have a serial connection in which the interface output logic signal of the K-th interface circuit is input as the interface input logic signal of the K-1-th interface circuit. Each of the N sensor circuits is a circuit that starts a detection operation in response to the inversion of the sensor input logic signal, and ends the detection operation by inverting the sensor output logic signal after a detection time proportional to the amount detected by the sensor circuit has elapsed since the inversion of the sensor input logic signal. Each of the N interface circuits is a circuit that inverts the interface output logic signal in response to the inversion of the sensor output logic signal of the corresponding sensor circuit. In response to the inversion of the sensor output logic signal of the K-th sensor circuit and the termination of the detection operation of the K-th sensor circuit, the detection operation of the K+1-th sensor circuit is initiated. A sensor in which the first interface circuit outputs an interface output logic signal that continuously outputs N signals indicating the detection time detected by the Nth sensor circuit from the first sensor circuit.
2. The K-th interface circuit receives the sensor output logic signal output from the K-th sensor circuit and the interface output logic signal output from the K+1-th interface circuit as inputs. The interface output logic signal output from the K-th interface circuit is input to the K-1th interface circuit. The sensor according to claim 1, wherein, in response to the inversion of the sensor output logic signal of the K-th sensor circuit and the termination of the detection operation of the K-th sensor circuit, the interface output logic signal indicating the detection time detected by the K-th sensor circuit is output from the K-th interface circuit to the K-1th interface circuit.
3. Each of the N interface circuits is further provided with N first resistors, Each of the N interface circuits is equipped with a logic circuit, The input terminal of the K-th logic circuit is connected to the output terminal of the K-th sensor circuit and the output terminal of the K+1-th logic circuit. The sensor according to claim 1 or 2, wherein the connection path between the input terminal of the K-th logic circuit and the output terminal of the K+1-th logic circuit is connected to a first predetermined voltage point via the K-th first resistor.
4. Each of the N sensor circuits is further provided with N second resistors, The sensor according to claim 1, wherein the connection path between the output terminal of the K-th sensor circuit and the input terminal of the K+1-th sensor circuit is connected to a second predetermined voltage point via the K-th second resistor.
5. Each of the N sensor circuits is equipped with a variable capacitance, The detected amount is the capacitance of the variable capacitance, The sensor according to claim 1, wherein the detection time is a time proportional to the capacitance of the variable capacitance.
6. Each of the N sensor circuits is equipped with a diode element, The detected amount is the reverse leakage current value of the diode element. The sensor according to claim 1, wherein the detection time is inversely proportional to the reverse leakage current value.
7. Each of the N sensor circuits is equipped with a variable resistor, The detected amount is the resistance value of the variable resistor, The sensor according to claim 1, wherein the detection time is a time proportional to the resistance value of the variable resistor.
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