Indication device

Abstract

To provide a display device capable of preventing non-uniformity of in-plane luminance caused by feedthrough voltage.SOLUTION: A display device 1 includes: a plurality of pixels 110; a plurality of write signal lines WS to which a control signal WS for selecting a pixel row in which data voltage is to be written is supplied; a WS signal gate driver 12a3 that supplies the control signal WS; a plurality of data voltage lines Sig for writing the data voltage; a data driver 13 that supplies the data voltage; a selector circuit 120 that switches the data voltage line Sig to which the data voltage is supplied; a selector control line SEL to which a control signal SEL for controlling the selector circuit 120 is supplied; and a controller 20 that supplies the control signal SEL. The plurality of pixels 110 include a first pixel 110a and a second pixel 110b belonging to the same pixel row. The WS signal gate driver 12a3 supplies the control signal WS in a first direction. The controller 20 supplies the control signal SEL in a second direction opposite to the first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a display device. [Background technology]

[0002] Conventionally, there are known display devices equipped with a so-called data selector circuit that inputs data voltages corresponding to grayscale values ​​output from a data circuit (data driver) to each signal line in a time-division manner via multiple switches (e.g., RGB switches). Patent Document 1 discloses a display device equipped with such a data selector circuit and a pair of gate circuits (gate drivers) arranged at both ends of a gate line and outputting gate signals. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2012-208389 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, in the display device disclosed in Patent Document 1, the brightness may be non-uniform within the plane. For example, the field-through voltage caused by the off state of the pixel writing transistor and the data selector circuit switch may cause the brightness to be non-uniform within the plane.

[0005] Therefore, this disclosure provides a display device capable of suppressing in-plane brightness non-uniformity caused by field-through voltage. [Means for solving the problem]

[0006] A display device according to one aspect of the present disclosure includes: a plurality of pixels arranged in a matrix; a plurality of first gate control lines arranged for each different pixel row in the plurality of pixels and supplied with a first gate control signal for selecting a pixel row on which to write a data voltage corresponding to image data; a first gate driver that supplies the first gate control signal to the plurality of first gate control lines; a plurality of data voltage lines arranged for each different pixel column in the plurality of pixels and for writing a data voltage corresponding to image data; a data driver that supplies the data voltage to the plurality of data voltage lines; and a data driver connected between the plurality of data voltage lines and the data driver. The system includes a selector circuit for switching data voltage lines that supply the data voltage from a driver, a first selector control line to which a selector control signal for controlling the selector circuit is supplied, and a control unit that supplies the selector control signal to the first selector control line, wherein the plurality of pixels have a first pixel and a second pixel belonging to the same pixel row, the first gate driver supplies the first gate control signal to the plurality of first gate control lines so as to transmit in a first direction from the first pixel to the second pixel, and the control unit supplies the selector control signal to the first selector control line so as to transmit in a second direction from the second pixel to the first pixel. [Effects of the Invention]

[0007] According to one aspect of this disclosure, a display device can be realized that can suppress non-uniformity of in-plane brightness due to field-through voltage. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a block diagram showing an example of the functional configuration of a display device according to Embodiment 1. [Figure 2] Figure 2 is a magnified view of the region including the dashed line area in Figure 1. [Figure 3] Figure 3 is a circuit diagram showing an example of the pixel circuit configuration of a display device according to Embodiment 1. [Figure 4]Figure 4 shows the timing charts for various control signals. [Figure 5] Figure 5 is a schematic diagram illustrating the occurrence of brightness unevenness in a display device according to a comparative example. [Figure 6A] Figure 6A shows the magnitude of the field-through voltage for each pixel position in a comparative example of a display device. [Figure 6B] Figure 6B shows the magnitude of the field-through voltage for each switch position in the display device according to the comparative example. [Figure 6C] Figure 6C shows the magnitude of the field-through voltage for each in-plane position in a comparative example of a display device. [Figure 7] Figure 7 is a schematic diagram illustrating the suppression of brightness unevenness in the display device according to Embodiment 1. [Figure 8A] Figure 8A is a diagram showing the magnitude of the field-through voltage for each pixel position in the display device according to Embodiment 1. [Figure 8B] Figure 8B is a diagram showing the magnitude of the field-through voltage for each switch position in the display device according to Embodiment 1. [Figure 8C] Figure 8C is a diagram showing the magnitude of the field-through voltage for each in-plane position in the display device according to Embodiment 1. [Figure 9] Figure 9 is a schematic diagram illustrating the suppression of brightness unevenness in the display device according to Embodiment 2. [Figure 10] Figure 10 is a block diagram showing an example of the functional configuration of a display device according to Embodiment 3. [Figure 11] Figure 11 is a perspective view showing the external appearance of the display device according to each embodiment. [Modes for carrying out the invention]

[0009] The embodiments of this disclosure will be described below with reference to the drawings. Each embodiment described below is merely a specific example within this disclosure. Therefore, the numerical values, shapes, materials, components, arrangement positions of components, and connection configurations shown in the following embodiments are examples only and are not intended to limit this disclosure. Accordingly, any components in the following embodiments that are not described in the independent claims of this disclosure will be described as optional components.

[0010] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Also, the same reference numerals are used for substantially identical components in each figure, and redundant explanations are omitted or simplified.

[0011] Furthermore, in this specification, terms indicating relationships between elements such as orthogonal, parallel, and equal, as well as numerical values ​​and numerical ranges, do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent (e.g., about 10%).

[0012] (Embodiment 1) [1-1. Display Device Configuration] First, the configuration of the display device according to this embodiment will be described with reference to Figures 1 to 3. Figure 1 is a block diagram showing an example of the functional configuration of the display device 1 according to this embodiment. Figure 2 is a diagram showing an enlarged view of the area including the dashed area R in Figure 1. The dashed area R shows the configuration of one row of pixels. In Figure 2, the configuration of two adjacent pixel rows is shown.

[0013] In Figure 2, the pixel 110 within the dashed region R is shown as the first pixel 110a, and the pixel 110 connected to the same write signal line WS (e.g., write signal line WS1) as the first pixel 110a and positioned next to the first pixel 110a is shown as the second pixel 110b. The first pixel 110a and the second pixel 110b are pixels 110 belonging to the same pixel row, for example, adjacent pixels 110. Also, in Figure 2, each subpixel is referred to as a "pixel" for convenience.

[0014] For the sake of brevity, in the following explanation, signals and the wiring that transmits them may be referred to by the same symbol.

[0015] As shown in Figure 1, the display device 1 comprises a display panel 10, a control unit 20, and a power supply 30. The display panel 10 also includes a display unit 11, a first gate driver 12a, a second gate driver 12b, a data driver 13, and a selector circuit (data selector circuit) 120. Note that in Figure 1, only the pixel 110 connected to the data voltage line R_Sig (corresponding to the sub-pixel 110R shown in Figure 2) is shown among the data voltage lines B_Sig, G_Sig, and R_Sig.

[0016] The display unit 11 consists of a matrix of light-emitting elements (ELs) arranged in a grid. B , EL G , EL R The matrix has a plurality of pixels 110 (see Figure 3). The plurality of pixels 110 include the first pixel 110a and the second pixel 110b described above. Each row of the matrix is ​​provided with a control signal line (gate control line) that is commonly connected to the plurality of pixels 110 arranged in the same row, and each column of the matrix is ​​provided with data voltage lines B_Sig, G_Sig, and R_Sig (hereinafter also referred to as data voltage line B_Sig, etc.) that are commonly connected to the plurality of pixels 110 arranged in the same column.

[0017] The data voltage line B_Sig is connected to each subpixel 110B belonging to a pixel sequence containing one or more subpixels 110B (see Figure 2), and has the function of supplying a data voltage Vdat_b (see Figure 3) to each subpixel 110B. Note that a subpixel 110B is, for example, a subpixel that emits blue light. Each subpixel 110B constitutes one subpixel sequence.

[0018] The data voltage line G_Sig is connected to each subpixel 110G belonging to a pixel sequence containing one or more subpixels 110G (see Figure 2), and has the function of supplying a data voltage to each subpixel 110G. A subpixel 110G is, for example, a subpixel that emits green light. Each subpixel 110G constitutes one subpixel sequence.

[0019] The data voltage line R_Sig is connected to each subpixel 110R belonging to a pixel sequence containing one or more subpixels 110R, and has the function of supplying a data voltage Vdat_r (see Figure 3) to each subpixel 110R. Note that a subpixel 110R is, for example, a subpixel that emits red light. Each subpixel 110R constitutes one subpixel sequence.

[0020] In the following, sub-pixels 110B, 110G, and 110R will also be referred to as sub-pixel 110B, etc. Also, in the following, data voltages Vdat_b, Vdat_g, and Vdat_r will also be referred to as data voltage Vdat_b, etc.

[0021] Thus, data voltage lines B_Sig, etc., are arranged for each different pixel row in multiple pixels 110, and are provided to charge the sub-pixels 110B, etc., with data voltage Vdat_b, etc., corresponding to the image data. Hereafter, the act of charging will also be referred to as writing.

[0022] As shown in Figure 2, the selector circuit 120 is connected between the data voltage line B_Sig, etc. and the data driver 13, and switches the data voltage line B_Sig, etc. that supplies the data voltage Vdat_b, etc. from the data driver 13 in a time-division manner. The selector circuit 120 has a plurality of switch units (for example, switch units 120a and 120b). For example, switch unit 120a is connected between the data voltage line B_Sig, etc. and the data IC (Integrated Circuit) 13a, and has the function of selectively supplying the data voltage Vdat_b, etc. from one of the data ICs 13a that constitute the data driver 13 to one of the selected data voltage lines B_Sig, etc.

[0023] The switch section 120a is disposed for each pixel column and includes selection transistors TSeg that are disposed for each sub-pixel column. B TSeg G TSeg R It has. The selection transistors TSeg B TSeg G TSeg R are switching transistors that switch the connection between the data voltage line B_Sig and the data driver 13.

[0024] One of the source electrode and the drain electrode of the selection transistor TSeg B is connected to the data voltage line B_Sig, and the other of the source electrode and the drain electrode is connected to the data IC 13a. Also, the gate electrode of the selection transistor TSeg B is connected to the selector control line SEL1.

[0025] One of the source electrode and the drain electrode of the selection transistor TSeg G is connected to the data voltage line G_Sig, and the other of the source electrode and the drain electrode is connected to the data IC 13a. Also, the gate electrode of the selection transistor TSeg G is connected to the selector control line SEL2.

[0026] One of the source electrode and the drain electrode of the selection transistor TSeg R is connected to the data voltage line R_Sig, and the other of the source electrode and the drain electrode is connected to the data IC 13a. Also, the gate electrode of the selection transistor TSeg R is connected to the selector control line SEL3.

[0027] The selector circuit 120 includes the selection transistors TSeg B TSeg G TSeg RThe on and off states are controlled by the control unit 20 via selector control lines SEL1, SEL2, and SEL3, thereby supplying the data voltage Vdat from the data IC 13a (data driver 13) to the data voltage line B_Sig, etc., in a time-division manner. The selector circuit 120 is a column switching circuit (sub-pixel column switching circuit) that switches the electrical connection between the data IC 13a and either the data voltage line B_Sig, etc. Hereafter, selector control lines SEL1, SEL2, and SEL3 will also be simply referred to as selector control lines SEL.

[0028] The selector control line SEL is supplied from the control unit 20 with a control signal SEL that controls the selector circuit 120. For example, the selector control line SEL1 is connected to the selection transistor TSeg B The gate electrode is connected to the selector control line SEL1, and the selector transistor TSeg B A control signal SEL1 that controls the on and off of is supplied from the control unit 20. Also, for example, the selector control line SEL2 is connected to the selection transistor TSeg G The gate electrode is connected to the selector control line SEL2, and the selector transistor TSeg G A control signal SEL2 that controls the on and off of is supplied from the control unit 20. Also, for example, the selector control line SEL3 controls the selection transistor TSeg R The gate electrode is connected to the selector control line SEL3, and the selector transistor TSeg R A control signal SEL3 for controlling the on and off states is supplied from the control unit 20. Selector control line SEL is an example of a first selector control line, and control signal SEL is an example of a selector control signal.

[0029] For example, when the control signal SEL1 input to the selector control line SEL1 changes from a low level to a high level, the selection transistor TSeg BWhen it turns on, the data voltage Vdat_b from data IC13a is supplied to the data voltage line B_Sig. Next, when the control signal SEL1 input to selector control line SEL1 changes from a high level to a low level, and then the control signal SEL2 input to selector control line SEL2 changes from a low level to a high level, the selector transistor TSeg B The selected transistor TSeg is turned off. G As this is turned on, the data voltage Vdat_g from data IC13a is supplied to the data voltage line G_Sig. Next, when the control signal SEL2 input to the selector control line SEL2 changes from a high level to a low level, and then the control signal SEL3 input to the selector control line SEL3 changes from a low level to a high level, the selector transistor TSeg G The selected transistor TSeg is turned off. R Since this is turned on, the data voltage Vdat_r from data IC13a is supplied to the data voltage line R_Sig.

[0030] In this way, the switch unit 120a performs the operation of holding the data voltage Vdat_b etc. on the data voltage line B_Sig etc. connected to the switch unit 120a in a time-division manner. As a result, one data IC 13a sets the light-emitting element EL on each of the data voltage lines B_Sig etc. B , EL G , EL R It is possible to store data voltages such as Vdat_b corresponding to the pixel current supplied to each of them.

[0031] The configuration of the switch section 120b of the selector circuit 120 is the same as that of the switch section 120a, and therefore its explanation is omitted. The switch section 120b is connected between the data voltage line B_Sig, etc., and the data IC 13b, and has the function of selectively supplying the data voltage from one of the data ICs 13b that constitute the data driver 13 to one of the selected data voltage lines B_Sig, etc.

[0032] In this embodiment, the control signal SEL to the selector control line SEL is transmitted from right to left on the page. In other words, the control unit 20 supplies the control signal SEL to the selector control line SEL from the second pixel 110b side of the two pixels 110b, rather than the first pixel 110a. It can also be said that the control unit 20 supplies the control signal SEL to the selector control line SEL so as to transmit it in a second direction, from the second pixel 110b towards the first pixel 110a.

[0033] Each of the selector control lines SEL1, SEL2, and SEL3 has input terminals TSb, TSg, and TSr, respectively, at the right end of the page, which are connected to the control unit 20. Furthermore, each of the selector control lines SEL1, SEL2, and SEL3 does not have an input terminal connected to the control unit 20 at the left end of the page (the end where the WS signal gate driver 12a3 is located). In other words, in the example in Figure 1, the left ends of the page for the selector control lines SEL1, SEL2, and SEL3 (one example being the end on the first pixel 110a side) are not connected to any other control unit 20. Thus, control signals SEL are input to the selector control lines SEL1, SEL2, and SEL3 from one side.

[0034] Note that the data voltage line B_Sig etc. connected to the first pixel 110a within the dashed region R is an example of a first data voltage line, and the data voltage line B_Sig etc. connected to the second pixel 110b in the region adjacent to the dashed region R is an example of a second data voltage line. The first data voltage line and the second data voltage line are arranged adjacent to each other, for example.

[0035] The switch unit 120a is not limited to selectively switching three data voltage lines B-Sig, etc., but can be configured to selectively switch two or more data voltage lines B-Sig, etc. Such a switch unit 120a has the same number of selection transistors as the number of data voltage lines B-Sig, etc. to be switched.

[0036] Referring again to Figure 1, the control unit 20 is a circuit that controls the display panel 10. It receives a video signal from an external source and controls the first gate driver 12a, the second gate driver 12b, the data driver 13, and the selector circuit 120 so that the image represented by the video signal is displayed on the display unit 11. For example, the control unit 20 supplies a control signal SEL to the selector control line SEL to control the selector circuit 120. The control unit 20 is connected to only the end of the selector control line SEL on the second pixel 110b side (input terminals TSb, TSg, TSr), which is the end on the first pixel 110a side and the end on the second pixel 110b side.

[0037] The power supply 30 supplies power for the operation of the display device 1 to each part of the display device 1. For example, the power supply 30 supplies power for the display unit 11, the first gate driver 12a, the second gate driver 12b, the data driver 13, the control unit 20, and the selector circuit 120. The power supply 30 also supplies, for example, the initialization voltage VINI, the reference voltage VREF, the positive power supply voltage VCC, and the negative power supply voltage VCATH to the display unit 11.

[0038] The first gate driver 12a and the second gate driver 12b supply various control signals to the pixel 110 via control signal lines to control the operation of the pixel 110. The first gate driver 12a functions as a scan line drive circuit.

[0039] The control signal lines include a write signal line WS, an initialization signal line INI, and a reference signal line REF. The write signal line WS is an example of a first gate control line, and is arranged for each different pixel row in a plurality of pixels 110, and supplies a control signal WS for selecting the pixel row (e.g., a sub-pixel row) on which to write the data voltage Vdat_b, etc., corresponding to the image data. The initialization signal line INI is an example of a second gate control line, and is arranged for each different pixel row in a plurality of pixels 110, and is connected to the light-emitting element EL B , EL G , EL RA control signal INI is supplied to initialize the potential. The reference signal line REF is an example of a third gate control line, and is located for each different row of pixels in a plurality of pixels 110, and the drive transistor TD B , TD G , TD R A control signal REF is supplied to the gate electrode (see Figure 3) to supply a reference voltage VREF.

[0040] The first gate driver 12a comprises an INI signal gate driver 12a1, a Ref signal gate driver 12a2, and a WS signal gate driver 12a3. Each of the INI signal gate driver 12a1, the Ref signal gate driver 12a2, and the WS signal gate driver 12a3 comprises a plurality of shift registers. The shift registers are composed of, for example, CMOS (Complementary metal-oxide-semiconductor) circuits, or polysilicon thin-film transistors in which only N-channel or P-channel thin-film transistors are used, but are not limited to these.

[0041] The second gate driver 12b comprises an INI signal gate driver 12b1 and a Ref signal gate driver 12b2. In other words, the second gate driver 12b does not have a WS signal gate driver. The second gate driver 12b, which is located on the side of the selector control line SEL where the control signal SEL from the control unit 20 is input (right side in the paper), does not include a WS signal gate driver. In other words, in this embodiment, the display device 1 has a WS signal gate driver 12a3 only in the first gate driver 12a, which is located on the side of the selector circuit 120 where the control signal SEL from the control unit 20 is not input (left side in the paper).

[0042] INI signal gate drivers 12a1 and 12b1 are configured with initialization transistor T1 B , T1 G , T1 R(See Figure 3) Each gate electrode is connected via an initialization signal line INI, and the light-emitting element EL of pixel 110 B , EL G , EL R These are gate drivers for performing an initialization operation that initializes the potential of each electrode (e.g., anode). The INI signal gate drivers 12a1 and 12b1 are connected to the initialization transistor T1 B , T1 G , T1 R The on and off states are controlled by the control signal INI. The gate drivers 12a1 and 12b1 for the INI signal receive the control signal INI from both sides of the initialization signal line INI. The control signal INI is an example of a second gate control signal, and the gate driver 12a1 for the INI signal is an example of a second gate driver. Note that the initialization operation is performed before the threshold compensation operation.

[0043] The gate drivers 12a2 and 12b2 for the Ref signal are controlled by the compensation transistor T2 B , T2 G , T2 R (See Figure 3) Each gate electrode is connected via the reference signal line REF, and the drive transistor TD B , TD G , TD R This is a gate driver for performing threshold compensation operation to compensate for the threshold voltage of the Ref signal. The gate drivers 12a2 and 12b2 for the Ref signal are connected to the compensation transistor T2 B , T2 G , T2 R The on and off states are controlled by the control signal REF. The gate drivers 12a2 and 12b2 for the Ref signal each receive the control signal REF from both sides of the reference signal line REF. The control signal REF is an example of a third gate control signal, and the gate driver 12a2 for the Ref signal is an example of a third gate driver.

[0044] The gate driver 12a3 for the WS signal is connected to the writing transistor T3. B , T3 G , T3 R(See Figure 3) Each gate electrode is connected via the write signal line WS, and the data voltages Vdat_b, Vdat_g, and Vdat_r are held by the respective capacitances CS. B , CS G , CS R Each of them is held. The gate driver 12a3 for the WS signal is the writing transistor T3 B , T3 G , T3 R A control signal WS for turning the device on and off is supplied to the write signal line WS. The gate driver 12a3 for the WS signal receives the control signal WS from one side of the write signal line WS. The gate driver 12a3 for the WS signal is connected to only the end of the write signal line WS on the first pixel 110a side (input terminal TW1, etc.) and the end on the second pixel 110b side. The control signal WS is an example of a first gate control signal.

[0045] Thus, the display device 1 has a configuration in which control signals are input from both sides of the display unit 11 to the initialization signal line INI and the reference signal line REF, of which the write signal line WS, initialization signal line INI, and reference signal line REF are connected, and the control signal WS is input from one side of the display unit 11 to the write signal line WS. As a result, the number of circuit components is reduced compared to the case in which the control signal WS is input from both sides of the display unit 11 to the write signal line WS, and thus the bezel on at least one side of the display device 1 can be made smaller.

[0046] Furthermore, as shown in Figure 2, in this embodiment, the control signal WS to the write signal line WS is transmitted from left to right on the page. In other words, the gate driver 12a3 for the WS signal inputs the control signal WS to the write signal line WS from the left side of the page, for example, from the side of the first pixel 110a among the first pixel 110a and the second pixel 110b. It can also be said that the gate driver 12a3 for the WS signal supplies the control signal WS to the write signal line WS so as to transmit it in a first direction from the first pixel 110a to the second pixel 110b.

[0047] Each of the multiple write signal lines WS has an input terminal at the right-hand end of the page that is connected to the first gate driver 12a. For example, among the n rows (where n is an integer greater than or equal to 2) of write signal lines WS, write signal line WS1 is provided with input terminal TW1, write signal line WS2 is provided with input terminal TW2, write signal line WSn-1 is provided with input terminal TWn-1, and write signal line WSn is provided with input terminal TWn. Furthermore, each of the multiple write signal lines WS does not have an input terminal at the left-hand end of the page that is connected to the second gate driver 12b. In other words, in the example in Figure 1, the right-hand end of the page for the multiple write signal lines WS (one example of the end on the second pixel 110b side) is not connected to any other WS signal gate drivers.

[0048] Thus, the write signal line WS and the selector control line SEL have input terminals on opposite sides of the direction in which they extend (left-right direction on the paper). Control signals are input to the write signal line WS and the selector control line SEL from opposite sides of this direction. The transmission direction of the control signal WS on the write signal line WS and the transmission direction of the control signal SEL on the selector control line SEL are opposite.

[0049] Referring again to Figure 1, the data driver 13 supplies data voltages Vdat_b, etc., corresponding to the luminescence brightness to the pixel 110 via the data voltage line B_Sig, etc. The data voltages Vdat_b, etc., are voltage signals based on the display gradation of the pixel 110. The data driver 13 drives the circuit elements of the light-emitting pixel by outputting the data voltages Vdat_b, etc., to the data voltage line B_Sig, etc., in a time-division manner via the selector circuit 120. The data driver 13 functions as a signal line driving circuit.

[0050] Next, we will describe the multiple pixels 110 with reference to Figure 3. Figure 3 is a circuit diagram showing an example of the configuration of the pixel circuit of the display device 1 according to this embodiment.

[0051] As shown in Figure 3, the pixel (pixel circuit) 100 is composed of sub-pixels (sub-pixel circuits) 110B, 110G, and 110R. The sub-pixels 110B, 110G, and 110R are light-emitting elements (EL). B , EL G , EL R They have the same configuration as the others. Below, the configuration of the pixel circuit will be explained, focusing on the sub-pixel 110R.

[0052] Subpixel 110R is initialized by transistor T1 R And, compensation transistor T2 R And, the writing transistor T3 R And, retention capacity CS R And, the drive transistor TD R And, light-emitting element EL R It has the following: Initialization transistor T1 R And, compensation transistor T2 R And, the writing transistor T3 R And, the drive transistor TD R This is an example of a thin-film transistor that constitutes pixel 110. Furthermore, sub-pixel 110R has control signal lines (initialization signal line INI, reference signal line REF, write signal line WS), data voltage line R_Sig, positive power supply line VCC, and cathode power supply line VCATH. Note that initialization transistor T1 R , and compensation transistor T2 R It is not an essential component.

[0053] Initialization transistor T1 R The drive transistor TD turns ON according to the control signal INI. R The initialization voltage VINI is supplied to the source electrode (source node) of the initialization transistor T1. R The gate electrodes are connected to the INI signal gate drivers 12a1 and 12b1, respectively.

[0054] Compensation transistor T2 R The drive transistor TD turns ON according to the control signal REF. RA reference voltage VREF is supplied to the gate electrode (gate node). This corresponds to initializing the potential of the electrode (e.g., anode) of the light-emitting element EL. R The gate electrode of the compensation transistor T2 R is connected to each of the gate drivers 12a2 and 12b2 for the Ref signal.

[0055] The write transistor T3 R is turned on according to the control signal WS, and holds the data voltage Vdat_r in the holding capacitor CS. R The gate electrode of the write transistor T3 R is connected to the gate driver 12a3 for the WS signal.

[0056] The write transistor T3 R is connected between the data voltage line R_Sig and the gate electrode of the drive transistor TD. R Specifically, for the write transistor T3 R one of the source electrode and the drain electrode is connected to the data voltage line R_Sig, and the other of the source electrode and the drain electrode is connected to one of the source electrode and the drain electrode of the compensation transistor T2 R and the gate electrode of the drive transistor TD. R R

[0057] The holding capacitor CS R holds the data voltage Vdat_r supplied via the data voltage line R_Sig.

[0058] The drive transistor TD R has one of the source electrode and the drain electrode connected to the positive power supply line VCC, and the other of the source electrode and the drain electrode connected to the anode of the light-emitting element EL R and supplies current to the light-emitting element EL according to the data voltage Vdat_r held in the holding capacitor CS. R Thereby, the light-emitting element EL R emits light with a luminance corresponding to the data voltage Vdat_r. R R

[0059] Light-emitting element EL R This is a self-emitting light-emitting element, and in this embodiment, it is an organic EL (Electro-Luminescence) element. R The anode electrode is the drive transistor TD R It is connected to either the source electrode or the drain electrode. (EL light-emitting element) R A cathode voltage (negative power supply voltage) is applied to the cathode electrode by the cathode power supply line (negative power supply line) VCATH.

[0060] Note that the gate potential Vg shown in Figure 3... R The drive transistor TD R This shows the potential of the gate electrode, and the source potential Vs R The drive transistor TD R This shows the potential of the source electrode.

[0061] The transistors described above are, for example, n-type thin-film transistors (n-type TFTs), but they may also be composed of p-type thin-film transistors (p-type TFTs).

[0062] [1-2. Mechanisms for the occurrence of luminance unevenness and mechanisms for suppressing luminance unevenness] Next, the mechanism for generating brightness unevenness and the mechanism for suppressing brightness unevenness in the display device 1 will be explained with reference to Figures 4 to 8C.

[0063] First, we will explain the waveform distortion that occurs in the control signal WS, referring to Figure 4. Figure 4 is a diagram showing the timing charts of various control signals. Specifically, Figure 4(a) shows the timing chart of gate control signals (control signals INI, REF, WS), and Figure 4(b) shows the timing chart of selector control signals (control signals SEL1~SEL3). Note that the timing charts shown in Figure 4 are timing charts for one pixel row.

[0064] In the control signal WS shown in Figure 4(a), the solid line represents the waveform (pulse waveform) output from the WS signal date driver 12a3, and the dashed line represents the waveform (waveform including saturation) actually supplied to the write signal line WS. In the control signals SEL1, SEL2, and SEL3 shown in Figure 4(b), the solid line represents the waveform (pulse waveform) output from the control unit 20, and the dashed line represents the waveform (waveform including saturation) actually supplied to the selector control line SEL. Note that the shape of the dashed line (degree of waveform saturation) may change depending on the position from the input terminal, so the waveform shapes shown in Figure 4(a) and Figure 4(b) are just examples.

[0065] As shown in Figure 4(a), time t1 to time t4 is the off period. At time t1, the control signal REF changes from a low level to a high level, and the compensation transistor T2 B , T2 G , T2 R When this is turned on, the blackout period begins. Time t2 to t3 is the initialization period when the control signal REF is at a low level, the control signal INI is at a high level, and initialization operations are performed. Time t3 to t4 is the threshold compensation period (Vth compensation period) when the control signal REF is at a high level, the control signal INI is at a low level, and threshold compensation operations are performed.

[0066] Time t4 to time t5 is the period during which data voltages Vdat_b, etc. are supplied to each of the data voltage lines B_Sig, etc. in a time series. During time t4 to time t5, the data voltages Vdat_b, etc. are selectively charged to the data voltage lines B_Sig, etc. by the selector circuit 120 before the data writing period. For example, during time t4 to time t5, the control signal SEL supplied from the control unit 20 selectively switches the data voltage lines B-Sig, G-Sig, and R-Sig connected to the data IC 13a in synchronization with the timing of the sequential output of data voltages Vdat_b, Vdat_g, and Vdat_r of the data IC 13a, thereby charging each of the data voltage lines B-Sig, G-Sig, and R-Sig with data voltages Vdat_b, Vdat_g, and Vdat_r, respectively.

[0067] Between times t5 and t6, the control signals SEL1, SEL2, and SEL3 are all at low levels, so the data voltage line B_Sig, etc., is in a floating state. Also, between times t5 and t6, the control signal WS is at a high level, so the writing transistor T3 B , T3 G , T3 R When it turns on, the retention capacity CS B , CS G , CS R The data voltage Vdat_b and other data voltages held in each of the data voltage lines, such as B_Sig, are written to each of them. The period from time t5 to time t6 is the data writing period. The data writing period is a period that can directly affect the pixel current (sub-pixel current) that controls the grayscale display.

[0068] The blackout period is a period for initial setup, and specifically refers to the period during which the sub-pixel circuit is not lit (i.e., displays black). If there are n pixel rows and one horizontal period is defined as 1H, the blackout period is, for example, defined by n × H. Note that "black display" is not limited to being completely black (non-emitting), but also includes being substantially black, and may include being below a predetermined brightness level, for example.

[0069] As shown in Figure 4(a), the control signal WS exhibits waveform distortion (WS waveform distortion in Figure 4(a)) due to the signal delay of the control signal WS. The waveform distortion of the control signal WS increases in the write signal line WS as it moves away from the gate driver 12a3 for the WS signal (for example, as it moves away from the input terminal of the write signal line WS). The waveform distortion of the control signal WS can occur due to the parasitic capacitance of the pixel 110 and the signal delay caused by the wiring resistance of the write signal line WS. The parasitic capacitance of the pixel 110 is due to the write transistor T3 that constitutes the pixel 110. B , T3 G , T3 R Each of these, and the drive transistor TD B , TD G , TD R This includes the sum of the parasitic capacities between each of them.

[0070] Here, we will explain the field-through voltage ΔVfs_vg caused by the writing transistor T3 turning off at time t6. Let Ctot_vg be the parasitic capacitance of the entire pixel 110, and the writing transistor of pixel 110 (for example, writing transistor T3) R Let Cws_CR (=Cws_tft / Ctot_vg) be the capacitance ratio when Cws_tft is the capacitance between the gate and the line of the writing transistor (for example, the capacitance between the gate and drain of the writing transistor). Here, if the amplitude of the control signal WS is ΔVws, the field-through voltage ΔVfs_vg can be calculated by the following equation 1.

[0071] △Vfs_vg=△Vws×Cws_CR (Formula 1)

[0072] When the writing transistor T3 turns off at time t6, the voltage held on the data voltage line B_Sig, etc., decreases by the field-through voltage ΔVfs_vg calculated from the data voltage Vdat_b, etc., using Equation 1.

[0073] Note that Equation 1 shows the field-through voltage ΔVfs_vg that occurs when the control signal WS is a square wave, that is, when the control signal WS is not distorted. When waveform distortion occurs in the control signal WS, the field-through voltage ΔVfs_vg becomes smaller compared to when the control signal WS is a square wave. The larger the waveform distortion in the control signal WS, the smaller the field-through voltage ΔVfs_vg becomes. For example, if a data voltage Vdat_b of the same potential is supplied to the data voltage line B_Sig etc. between time t4 and time t5, the larger the waveform distortion in the control signal WS, the smaller the retaining capacitance CS after the writing transistor T3 is turned off. B , CS G , CS R The voltage written to the data becomes close to the data voltage Vdat_b, etc., held on the data voltage line B_Sig, etc.

[0074] Furthermore, the waveform distortion of the control signal WS is greater at positions further from the output of the WS signal gate driver 12a3 on the write signal line WS, i.e., at positions further from the input terminal TW1 on the write signal line WS, than at positions closer to the output of the WS signal gate driver 12a3 on the write signal line WS, i.e., at positions closer to the input terminal TW1 on the write signal line WS. For this reason, the field-through voltage △Vfs_vg at positions closer to the output of the WS signal gate driver 12a3 on the write signal line WS (for example, field-through voltages △Vfs_vg1 and △Vfs_vg3 shown in Figure 5) is greater than the field-through voltage △Vfs_vg at positions further from the output of the WS signal gate driver 12a3 on the write signal line WS (for example, field-through voltage △Vfs_vg2 shown in Figure 5).

[0075] As a result, in pixels 110 connected to data voltage lines B_Sig etc. that are close to the output of the gate driver 12a3 for the WS signal on the write signal line WS, the decrease in data voltage Vdat_b etc. after the write transistor T3 is turned off is large, and as a result the pixel current (sub-pixel current) becomes small. On the other hand, in pixels 110 connected to data voltage lines B_Sig etc. that are far from the output of the gate driver 12a3 for the WS signal on the write signal line WS, the decrease in data voltage Vdat_b etc. after the write transistor T3 is turned off is small, and as a result the pixel current becomes large. Thus, a difference in pixel current occurs due to the difference in field-through voltage ΔVfs_vg depending on the position of the pixel 110, and this difference in pixel current can cause brightness unevenness.

[0076] Furthermore, as shown in Figure 4(b), the control signal SEL exhibits waveform distortion (SEL waveform distortion in Figure 4(b)) due to the signal delay of the control signal SEL. This causes a charging delay of data voltage Vdat_b, etc., to data voltage line B_Sig, etc. The waveform distortion of the control signal SEL increases with distance from the input terminal in the selector control line SEL. The waveform distortion of the control signal SEL can be caused by parasitic capacitance between data voltage line B_Sig, etc., and the selector control line SEL, parasitic capacitance of the switch section (e.g., switch section 120a), and signal delay due to the wiring resistance of the selector control line SEL. The parasitic capacitance of the switch section is the selection transistor TSeg B TSeg G TSeg R This includes the parasitic capacitance between each gate and source / drain.

[0077] Here, between time t4 and time t5, the selected transistor TSeg B TSeg G TSeg R This section explains the field-through voltage ΔVfs_sig caused by the switching off of the selector. Let Ctot_sig be the total parasitic capacitance (sum of parasitic capacitance) between the data voltage line B_Sig etc. and the selector control line SEL, and selector transistor (e.g., selector transistor TSeg) R Let Csel_CR (=Csel_tft / Ctot_sig) be the capacitance ratio when the capacitance between the gate of the selected transistor and the source / drain of the selected transistor is Csel_tft. Here, if the amplitude of the control signal SEL is ΔVsel, the field-through voltage ΔVfs_sig can be calculated by the following equation 2.

[0078] △Vfs_sig=△Vsel×Csel_CR (Formula 2)

[0079] Selected transistor TSeg at time t4 to time t5 B TSeg G TSeg RAs the devices are sequentially turned off, the voltage held on the data voltage line B_Sig, etc. decreases by the field-through voltage ΔVfs_sig calculated by Equation 2 from the data voltage Vdat_b, etc. supplied from the data driver 13.

[0080] Equation 2 shows the field-through voltage ΔVfs_sig that occurs when the control signal SEL is a square wave, i.e., when the control signal SEL is not distorted. When waveform distortion occurs in the control signal SEL, the field-through voltage ΔVfs_sig becomes smaller compared to when the control signal SEL is a square wave. The larger the waveform distortion in the control signal SEL, the smaller the field-through voltage ΔVfs_sig becomes. For example, if a data voltage Vdat_b of the same potential is output to the data voltage line B_Sig etc. between time t4 and time t5, the larger the resulting waveform distortion, the smaller the field-through voltage ΔVfs_sig becomes. B TSeg G TSeg R After the device is turned off, the voltage held on the data voltage line B_Sig, etc., becomes close to the data voltage Vdat_b, etc., output from the data driver 13.

[0081] Furthermore, the waveform distortion of the control signal SEL is greater at positions further from the input terminal TSb on the selector control line SEL than at positions closer to the input terminal TSb on the selector control line SEL. Therefore, the field-through voltage ΔVfs_sig at positions close to the input terminal TSb on the selector control line SEL (for example, field-through voltages ΔVfs_sig1 and ΔVfs_sig3 shown in Figure 5) is greater than the field-through voltage ΔVfs_sig at positions far from the input terminal TSb on the selector control line SEL (for example, field-through voltage ΔVfs_sig2 shown in Figure 5).

[0082] As a result, the data voltage line B_Sig, etc., located close to the input terminal TSb, etc., in the selector control line SEL, is connected to the selector transistor TSeg of the switch section 120a. B TSeg G TSeg RAfter the switch is turned off, the data voltage line B_Sig etc. drops significantly, resulting in a smaller pixel current (sub-pixel current). On the other hand, for data voltage lines B_Sig etc. located far from the input terminal TSb etc. in the selector control line SEL, the select transistor TSeg of the switch section 120a is used. B TSeg G TSeg R After the switch is turned off, the decrease in the data voltage line B_Sig, etc., is small, resulting in a larger pixel current. Thus, a difference in pixel current occurs due to the difference in the field-through voltage ΔVfs_sig depending on the position of pixel 110, and this difference in pixel current can cause brightness unevenness.

[0083] Next, the brightness unevenness in the comparative example display device will be explained with reference to Figures 5 to 6C. Figure 5 is a schematic diagram illustrating the occurrence of brightness unevenness in the comparative example display device. Figure 6A shows the magnitude of the field-through voltage ΔVfs (ΔVfs_vg) for each pixel position in the comparative example display device. Figure 6B shows the magnitude of the field-through voltage ΔVfs (ΔVfs_sig) for each switch position in the comparative example display device. Figure 6C shows the magnitude of the field-through voltage ΔVfs (total field-through voltage) for each in-plane position in the comparative example display device.

[0084] In the comparative example, the display device receives control signals from both sides of the write signal line WS and the selector control line SEL. The comparative example has gate drivers 12a3 and 12b3 for the WS signal on both sides of the display unit 11.

[0085] Data voltage lines Sig1 and Sig3 are, for example, data voltage lines provided at both ends, and data voltage line Sig2 is a data voltage line positioned between data voltage lines Sig1 and Sig3, and is, for example, a data voltage line provided in the center of the display unit 11. Field-through voltages ΔVfs_vg1 and ΔVfs_sig1 indicate the field-through voltage generated at the pixel 110 connected to data voltage line Sig1, field-through voltages ΔVfs_vg2 and ΔVfs_sig2 indicate the field-through voltage generated at the pixel 110 connected to data voltage line Sig2, and field-through voltages ΔVfs_vg3 and ΔVfs_sig3 indicate the field-through voltage generated at the pixel 110 connected to data voltage line Sig3.

[0086] Furthermore, in Figure 5, for convenience, the writing transistor is shown as T3, the driving transistor as TD, and the light-emitting element as EL.

[0087] As shown in Figure 6A, the field-through voltage △Vfs_vg1 (position: left) shown in Figure 5 is large (slope: steep) because it is close to the WS signal gate driver 12a3 (close to the input terminal to which the control signal WS from the WS signal gate driver 12a3 is input) and the waveform distortion of the control signal WS is small. Similarly, the field-through voltage △Vfs_vg3 (position: right) shown in Figure 5 is large (slope: steep) because it is close to the WS signal gate driver 12b3 (close to the input terminal to which the control signal WS from the WS signal gate driver 12b3 is input) and the waveform distortion of the control signal WS is small. The slope indicates the slope of the control signal WS, and the steeper the slope, the smaller the waveform distortion. The position indicates the position of pixel 110 in the display unit 11.

[0088] On the other hand, the field-through voltage ΔVfs_vg2 (position: center) shown in Figure 5 is midway between the gate drivers 12a3 and 12b3 for the WS signal (horizontally in the center of the display unit 11), and the waveform distortion of the control signal WS is greater than that of both ends of the write signal line WS, so it becomes smaller than that of both ends of the write signal line WS (slope: midway).

[0089] As shown in Figure 6B, the field-through voltage △Vfs_sig1 (position: left) shown in Figure 5 is large (slope: steep) because it is close to the control unit (not shown) (close to the left input terminal of the control signal SEL) and the waveform distortion of the control signal SEL is small. Similarly, the field-through voltage △Vfs_sig3 (position: right) shown in Figure 5 is large (slope: steep) because it is close to the control unit (not shown) (close to the right input terminal of the control signal SEL) and the waveform distortion of the control signal SEL is small.

[0090] On the other hand, the field-through voltage ΔVfs_sig2 (position: center) shown in Figure 5 is midway between the two control units (midway between the left and right input terminals, and horizontally in the center of the display unit 11), and the waveform distortion of the control signal SEL is greater than around the left and right input terminals, so it is smaller than both ends of the control signal SEL (slope: midway).

[0091] As shown in Figure 6C, the results in Figures 6A and 6B indicate that significant brightness unevenness may occur between the left and right regions and the central region of the display unit 11. For example, if the data driver 13 outputs data voltages Vdat_b, etc., of the same potential to each data voltage line including data voltage lines Sig1, Seg2, and Sig3, the brightness should ideally be uniform across the display unit 11. However, in the comparative example display device, the central region is brighter than the left and right regions. In the comparative example display device, the pixel rows with a large field-through voltage △Vfs_vg due to waveform distortion of the control signal WS (left and right pixel rows) and the pixel rows with a large field-through voltage △Vfs_sig due to waveform distortion of the control signal SEL (left and right pixel rows) are the same, and the field-through voltage △Vfs_vg due to waveform distortion of the control signal WS is the same for the middle pixel row (center pixel row) and the field-through voltage △Vfs_sig due to waveform distortion of the control signal SEL is the same for the middle pixel row (center pixel row). Therefore, due to the superposition of field-through voltages △Vfs_vg and △Vfs_sig, the difference in the total field-through voltage △Vfs for each pixel 110 becomes large between the left and right and the center. As a result, in the comparative example display device device, a large difference occurs in the pixel current flowing through the light-emitting element EL of each pixel 110, which can lead to significant brightness unevenness.

[0092] As described above, in the comparative example, brightness unevenness may occur due to the superposition of brightness unevenness caused by the lateral (left-right direction of the paper) delay (signal delay) of the control signals WS supplied by the WS signal gate drivers 12a3 and 12b3, and brightness unevenness caused by the lateral (left-right direction of the paper) delay (signal delay) of the control signal SEL supplied by the control unit 20.

[0093] Next, the suppression of brightness unevenness in the display device 1 according to this embodiment will be explained with reference to Figures 7 to 8C. Figure 7 is a schematic diagram illustrating the suppression of brightness unevenness in the display device 1 according to this embodiment. Figure 8A is a diagram showing the magnitude of the field-through voltage ΔVfs (ΔVfs_vg) for each pixel position in the display device 1 according to this embodiment. Figure 8B is a diagram showing the magnitude of the field-through voltage ΔVfs (ΔVfs_sig) for each switch position in the display device 1 according to this embodiment. Figure 8C is a diagram showing the magnitude of the field-through voltage ΔVfs (total field-through voltage) for each in-plane position in the display device 1 according to this embodiment.

[0094] As shown in Figure 8A, the field-through voltage △Vfs_vg11 (position: left) shown in Figure 7 is close to the gate driver 12a3 for the WS signal (close to the input terminal to which the control signal WS from the gate driver 12a3 for the WS signal is input), and the waveform distortion of the control signal WS is small, so it is large (slope: steep). The field-through voltage △Vfs_vg12 (position: center) shown in Figure 5 is at the horizontal center of the display unit 11, and the waveform distortion of the control signal WS is larger than that of the left end of the write signal line WS, so it is smaller than the left end of the write signal line WS (slope: intermediate). In other words, the field-through voltage △Vfs_vg12 is smaller than the field-through voltage △Vfs_vg11. The magnitudes of the field-through voltages △Vfs_vg11 and △Vfs_vg12 are about the same as the magnitudes of the field-through voltages △Vfs_vg1 and △Vfs_vg2 of the display device in the comparative example.

[0095] The field-through voltage ΔVfs_vg13 (position: right side) shown in Figure 7 is even smaller than the center (slope: gentle) because it is far from the gate driver 12a3 for the WS signal (far from the input terminal to which the control signal WS from the gate driver 12a3 for the WS signal is input), and the waveform distortion of the control signal WS is even greater. The magnitude of the field-through voltage ΔVfs_vg13 is smaller than the magnitude of the field-through voltage ΔVfs_vg12. Also, the magnitude of the field-through voltage ΔVfs_vg13 is smaller than the magnitude of the field-through voltage ΔVfs_vg3 of the display device in the comparative example.

[0096] Thus, in the display device 1, the field-through voltage ΔVfs_vg decreases as you move away from the gate driver 12a3 for the WS signal, and in the example of Figure 7, it decreases as you move to the right.

[0097] As shown in Figure 8B, the field-through voltage △Vfs_sig13 (position: right) shown in Figure 7 is large (slope: steep) because it is close to the control unit 20 (close to the input terminal of the control signal SEL) and the waveform distortion of the control signal SEL is small. The field-through voltage △Vfs_sig12 (position: center) shown in Figure 5 is in the horizontal center of the display unit 11 and the waveform distortion of the control signal SEL is larger than around the input terminal, so it is smaller than the pixel 110 on the far right (slope: intermediate). In other words, the field-through voltage △Vfs_sig12 is smaller than the field-through voltage △Vfs_sig13. The magnitudes of the field-through voltages △Vfs_sig12 and △Vfs_sig13 are about the same as the magnitudes of the field-through voltages △Vfs_sig2 and △Vfs_sig3 of the display device in the comparative example.

[0098] The field-through voltage ΔVfs_sig11 (position: left side) shown in Figure 7 is even smaller than the center (slope: gentle) because it is far from the control unit 20 (far from the input terminal of the control signal SEL) and the waveform distortion of the control signal SEL is even greater. The magnitude of the field-through voltage ΔVfs_sig11 is smaller than the magnitude of the field-through voltage ΔVfs_sig12. Also, the magnitude of the field-through voltage ΔVfs_sig11 is smaller than the magnitude of the field-through voltage ΔVfs_sig1 of the display device in the comparative example.

[0099] Thus, in the display device 1, the field-through voltage ΔVfs_sig decreases as you move away from the input terminal connected to the control unit 20, and in the example of Figure 7, it decreases as you move to the left.

[0100] As shown in Figure 7, in the display device 1, the data voltage line Sig13 at the position where the waveform distortion of the control signal SEL of the selector circuit 120 is at its minimum coincides with the write signal line WS at the point where the waveform distortion of the control signal WS on the write signal line WS is at its maximum (for example, at the position of the pixel 110 located on the far right of the display unit 11). Also, as shown in Figure 7, in the display device 1, the data voltage line Sig11 at the position where the waveform distortion of the control signal SEL of the selector circuit 120 is at its maximum coincides with the write signal line WS at the point where the waveform distortion of the control signal WS on the write signal line WS is at its minimum (for example, at the position of the pixel 110 located on the far left of the display unit 11).

[0101] As shown in Figure 8C, the results in Figures 8A and 8B indicate that the display device 1 can suppress the occurrence of brightness unevenness between the left and right regions and the central region of the display unit 11. For example, if the data driver 13 outputs data voltages Vdat_b, etc., of the same potential to each data voltage line including data voltage lines Sig1, Seg2, and Sig3, the display device 1 can achieve more uniform brightness within the surface compared to the display device in the comparative example. In the display device 1, a pixel example where the field-through voltage △Vfs_vg due to waveform distortion of the control signal WS is large (for example, the left pixel column) and a pixel column where the field-through voltage △Vfs_sig due to waveform distortion of the control signal SEL is small (for example, the left pixel column) overlap, and a pixel column where the field-through voltage △Vfs_vg is small (for example, the right pixel column) overlaps with a pixel column where the field-through voltage △Vfs_sig is large (for example, the right pixel column) and a pixel column where the field-through voltage △Vfs_vg is in the middle (for example, the center pixel column) overlaps with a pixel column where the field-through voltage △Vfs_sig is in the middle (for example, the center pixel column). Therefore, the sum of the field-through voltage △Vfs for each pixel 110 can be made uniform by superimposing the field-through voltages △Vfs_vg and △Vfs_sig. As a result, the display device 1 can equalize the pixel current flowing through the light-emitting element EL of each pixel 110, thereby suppressing the occurrence of brightness unevenness.

[0102] As described above, the display device 1 can improve the uniformity of the in-plane brightness of the display unit 11 without incorporating a complex correction system (e.g., a calculation IC). In other words, the display device 1 can achieve both low cost and improved display quality.

[0103] [1-3. Effects, etc.] As described above, the display device 1 according to this embodiment comprises a plurality of pixels 110 arranged in a matrix, a plurality of write signal lines WS arranged for each different pixel row in the plurality of pixels 110 and supplied with a control signal WS for selecting the pixel row on which to write a data voltage Vdat_b, etc. corresponding to image data, a gate driver 12a3 for WS signals that supplies the control signal WS to the plurality of write signal lines WS, a plurality of data voltage lines B_Sig, etc. arranged for each different pixel column in the plurality of pixels 110 and for writing a data voltage Vdat_b, etc. corresponding to image data, a data driver 13 that supplies the data voltage Vdat_b, etc. to the plurality of data voltage lines B_Sig, etc., a selector circuit 120 connected between the plurality of data voltage lines B_Sig, etc. and the data driver 13 and switching the data voltage lines B_Sig, etc. that supply the data voltage Vdat_b, etc. from the data driver 13, a selector control line SEL supplied with a control signal SEL that controls the selector circuit 120, and a control unit 20 that supplies the control signal SEL to the selector control line SEL. Multiple pixels 110 have a first pixel 110a and a second pixel 110b belonging to the same pixel row. The WS signal gate driver 12a3 supplies a control signal WS to the write signal line WS to transmit in a first direction from the first pixel 110a to the second pixel 110b, and the control unit 20 supplies a control signal SEL to the selector control line SEL to transmit in a second direction from the second pixel 110b to the first pixel 110a.

[0104] As a result, the display device 1 can make the value of the field-through voltage ΔVfs generated at pixel 110, which is the sum of the field-through voltage ΔVfs_sig due to waveform distortion of the control signal SEL and the field-through voltage ΔVfs_vg due to waveform distortion of the control signal WS, more uniform compared to the display device in the comparative example. The display device 1, for example, uses the same data voltage Vdat_b, etc. to light-emitting element EL B , EL G , EL R When making it emit light, the light-emitting element EL B , EL G , EL RThe difference in pixel current flowing through the pixels can be made smaller compared to the display device according to the comparative example. Therefore, the display device 1 according to this embodiment can suppress in-plane brightness non-uniformity caused by the field-through voltage ΔVfs. In other words, the display device 1 can suppress the occurrence of brightness unevenness caused by the field-through voltage ΔVfs.

[0105] Furthermore, the WS signal gate driver 12a3 is connected only to the end of the first pixel 110a side (e.g., the input terminal) of the multiple write signal lines WS, of which there are two ends: the first pixel 110a side and the second pixel 110b side. In addition, the control unit 20 is connected only to the end of the second pixel 110b side (e.g., the input terminal) of the selector control line SEL, of which there are two ends: the first pixel 110a side and the second pixel 110b side.

[0106] As a result, the display device 1 can further equalize the value of the field-through voltage ΔVfs generated at the pixels 110. In addition, the display device 1 can reduce the number of inputs to the write signal line WS and the selector control line SEL compared to when control signals are input from both sides of each of the write signal line WS and the selector control line SEL. Therefore, a display device 1 in which in-plane brightness non-uniformity due to the field-through voltage ΔVfs is further suppressed can be realized at a low cost.

[0107] Furthermore, the end of the multiple write signal line WS on the second pixel 110b side is not connected to any other gate driver, and the end of the selector control line SEL on the first pixel 110a side is not connected to any other control unit.

[0108] As a result, the display device 1 can reduce the number of gate drivers for the WS signal that supply the control signal WS, and the number of control units that supply the control signal SEL. For example, the number of ICs for the control signal WS and the number of ICs for the control signal SEL can be reduced. Therefore, the display device 1 can achieve both low cost and suppression of brightness unevenness (improvement of display quality).

[0109] Furthermore, the light-emitting element (EL) is an organic EL element.

[0110] This makes it possible to suppress the occurrence of brightness unevenness in organic EL display panels.

[0111] (Embodiment 2) [2-1. Display Device Configuration] The display device according to this embodiment will be described below with reference to Figure 9. Figure 9 is a schematic diagram illustrating the suppression of brightness unevenness in the display device according to this embodiment. In the following description, the differences from Embodiment 1 will be the main focus, and the same or similar content as in Embodiment 1 will be omitted or simplified. The display device according to this embodiment differs from the display device 1 according to Embodiment 1 in that it includes a gate driver 12b3 for the WS signal, and the input position of the control signal to the selector control lines (first selector control line SELa and second selector control line SELb). Note that in Figure 9, gate drivers other than the gate driver for the WS signal are not shown.

[0112] As shown in Figure 9, the display device according to this embodiment is equipped with WS signal gate drivers 12a3 and 12b3 on both sides of the display unit 11. The display device according to this embodiment is supplied with control signals WS from both sides of the write signal line WS. The write signal line WS has input terminals at both ends that are connected to the WS signal gate drivers 12a3 or 12b3. Specifically, the write signal line WS has an input terminal TWa connected to the WS signal gate driver 12a3, and an input terminal TWb connected to the WS signal gate driver 12b3.

[0113] The WS signal gate driver 12a3 supplies the control signal WS to the embedded signal line WS so as to transmit it in a first direction from the first pixel 110a to the second pixel 110b, and the WS signal gate driver 12b3 supplies the control signal WS to the embedded signal line WS so as to transmit it in a second direction from the second pixel 110b to the first pixel 110a.

[0114] As a result, the waveform distortion of the control signal WS is the same as that of the corresponding part of the display device according to the comparative example of Embodiment 1.

[0115] Note that the WS signal gate driver 12b3 is an example of a fourth gate driver.

[0116] The selector control line SEL for controlling the selector circuit 120 includes a first selector control line SELa and a second selector control line SELb. The first selector control line SELa has an input terminal TS1 for connection to the control unit 20, and the second selector control line SELb has an input terminal TS2 for connection to the control unit 20. Input terminals TS1 and TS2 may be located close together, for example. The two control units 20 may be implemented by different ICs, for example.

[0117] The first selector control line SELa is connected to the control unit 20 at a position between the ends of the pixel row (the central position in the left-right direction), and extends from that position toward the first pixel 110a.

[0118] The second selector control line SELb is connected to the control unit 20 at a position between the ends of the pixel row (the central position in the left-right direction), and extends from that position toward the second pixel 110b.

[0119] The position in question is, for example, the center of a pixel row, but is not limited to this. Also, for example, the first selector control line SELa and the second selector control line SELb are transmission paths that extend from the center of a pixel row to both the left and right sides. The transmission direction of the control signal SELa in the first selector control line SELa and the transmission direction of the control signal SELb in the second selector control line SELb are opposite. Also, for example, the transmission direction of the control signal WS supplied from the WS signal gate driver 12a3 is opposite to the transmission direction of the control signal SELa in the first selector control line SELa, and the transmission direction of the control signal WS supplied from the WS signal gate driver 12b3 is opposite to the transmission direction of the control signal SELb in the second selector control line SELb.

[0120] The same control signal is input to the first selector control line SELa and the second selector control line SELb. The first selector control line SELa and the second selector control line SELb are input to control signals for supplying data voltage Vdat_b, etc., to the same data voltage line (a data voltage line to which pixels 110 that emit the same color are connected) among the data voltage lines B_Sig, etc.

[0121] Although Figure 9 shows that neither the first selector control line SELa nor the second selector control line SELb is connected to the data voltage line Sig2, either the first selector control line SELa or the second selector control line SELb is actually connected to the data voltage line Sig2.

[0122] [2-2. Effects, etc.] As described above, the first selector control line SELa of the display device according to this embodiment is connected to the control unit 20 at a position between the ends of a pixel row and extends from that position toward the first pixel 110a. The display device further includes a WS signal gate driver 12b3 that supplies control signals WS to a plurality of write signal lines WS from the second pixel 110b side of the first pixel 110a and the second pixel 110b, and a second selector control line SELb that is connected to the control unit 20 at the same position and extends from that position toward the second pixel 110b.

[0123] As a result, the display device can achieve high performance, such as high-speed operation, because the control signal WS is supplied from both sides of the write signal line WS. Furthermore, since the control signal SEL to the selector control line SEL can be supplied from between both ends of the pixel row, the occurrence of brightness unevenness caused by the field-through voltage ΔVfs can be suppressed compared to when the control signal SEL is supplied from both ends. Therefore, the display device 1 can achieve both high performance and suppression of in-plane brightness unevenness.

[0124] Furthermore, the position between the two ends of a pixel row is the center position within that pixel row.

[0125] As a result, the control signal SEL can be input from the center of the display unit 11, making the lengths of the first selector control line SELa and the second selector control line SELb equal. In other words, the field-through voltage ΔVfs_sig generated by the first selector control line SELa and the second selector control line SELb can be made equal on the left and right sides. Therefore, the display device 1 can suppress the occurrence of a difference in field-through voltage ΔVfs_sig due to the difference in the lengths of the first selector control line SELa and the second selector control line SELb, thereby further suppressing non-uniformity of in-plane brightness.

[0126] (Embodiment 3) [3-1. Display device configuration] The display device according to this embodiment will be described below with reference to Figure 10. Figure 10 is a block diagram showing an example of the functional configuration of the display device 1a according to this embodiment. In the following description, the differences from Embodiment 1 will be the main focus, and the same or similar content as in Embodiment 1 will be omitted or simplified. The display device 1a according to this embodiment differs from the display device 1 according to Embodiment 1 in that it does not have a second gate driver 12b.

[0127] As shown in Figure 10, the display panel 10a of the display device 1a is equipped with a first gate driver 12a on only one side of the display unit 11. The display device 1a does not have a gate driver or other control circuit on the opposite side of the first gate driver 12a (the right side of the display unit 11 in the example of Figure 10). The display device 1a is positioned only at the end on the first pixel 110a side and the second pixel 110b side.

[0128] The WS signal gate driver 12a3 is an example of a first gate driver, the INI signal gate driver 12a1 is an example of a second gate driver, and the Ref signal gate driver 12a2 is an example of a third gate driver.

[0129] [3-2. Effects, etc.] As described above, each of the multiple pixels 110 in the display device 1a according to this embodiment has a light-emitting element EL. The display device 1a has a drive transistor TD connected to the anode of the light-emitting element EL, and the light-emitting element EL is arranged in each of the multiple pixels 110 in different pixel rows. B , EL G , EL RThe system includes a plurality of initialization signal lines INI to which a control signal INI is supplied for initializing the potential of the pixel, an INI signal gate driver 12a1 that supplies the control signal INI to the plurality of initialization signal lines INI, a plurality of reference signal lines REF arranged for each different pixel row in the plurality of pixels 110 and to which a control signal REF is supplied for supplying a reference voltage VREF to the gate electrode of the drive transistor TD, and a Ref signal gate driver 12a2 that supplies the control signal REF to the plurality of reference signal lines REF. The WS signal gate driver 12a3, the INI signal gate driver 12a1, and the Ref signal gate driver 12a2 are each arranged only on the first pixel 110a side of the first pixel 110a side and the second pixel 110b side.

[0130] This allows the three gate drivers to be placed on only one side of the display panel 10a. Therefore, the layout area of ​​the drive circuit section located around the display unit 11 can be reduced, making it possible to realize a narrow-bezel display device 1a. In addition, for example, one side can have an ultra-narrow bezel without a gate driver, which is expected to broaden the product applications of the display device 1a.

[0131] (Other embodiments) The display devices described above have been explained based on each embodiment, but the display devices described here are not limited to the above embodiments. Other embodiments realized by combining any components in each embodiment, modified versions obtained by applying various modifications to each embodiment that a person skilled in the art could conceive of without departing from the spirit of this disclosure, and various devices incorporating the display devices described in these embodiments are also included in this disclosure.

[0132] For example, the display device 1 according to this disclosure may be implemented as a thin-film display device, for example, as shown in Figure 11. Figure 11 is a perspective view showing the external appearance of the display device 1 according to each embodiment. Such a display device 1 can suppress the occurrence of brightness unevenness in the display unit 11. The display device according to Embodiment 2 and the display device 1a according to Embodiment 3 may also be implemented as such a thin-film display device. Furthermore, the application of the display device according to this disclosure is not particularly limited. The display device may be used in personal information terminals, personal computers, televisions, etc., or in digital signage, etc.

[0133] Furthermore, while the above embodiments describe examples where the light-emitting element of the display device is an organic EL element, it is not limited to this. The light-emitting element may be any other self-emissive type. For example, the light-emitting element may be a QLED (Quantum-dot Light Emitting Diode).

[0134] Furthermore, although the above embodiments describe examples in which the pixel circuit has a single-gate write transistor, the invention is not limited to this and may have a double-gate write transistor.The first WS signal gate driver may supply a control signal in a first direction to the write signal line to which one of the double-gate write transistors is connected, and the second WS signal gate driver may supply a control signal in a second direction opposite to the first direction to the write signal line to which the other of the double-gate write transistors is connected.In this case, the display device does not need to have a selector circuit.

[0135] Furthermore, the amplitudes ΔVsel and ΔVws in each of the above embodiments may be the same. In other words, the potential difference between the low level and high level in the first gate control signal and the potential difference between the low level and high level in the selector control signal may be equal.

[0136] Furthermore, each component in the above embodiments, such as the first gate driver, second gate driver, data driver, and control unit, may be implemented by dedicated hardware or by executing a software program suitable for each component. Each component may also be implemented by a program execution unit, such as a processor, reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory. The processor consists of one or more electronic circuits, including a semiconductor integrated circuit (IC) or a large-scale integration (LSI). The IC may be directly mounted on the TFT substrate of the display panel using COG (Chip On Glass) technology, or it may be mounted on a flexible wiring board such as an FFC (Flexible Flat Cable) or FPC (Flexible Printed Cable) using COF (Chip On Film) technology.

[0137] Furthermore, the first gate driver in each of the above embodiments may be implemented with a single IC, or the gate driver for the WS signal, the gate driver for the Ref signal, and the gate driver for the INI signal may be implemented with different ICs.

[0138] Furthermore, the second gate driver in embodiments 1 and 3 described above may be implemented with a single IC, or the gate driver for the Ref signal and the gate driver for the INI signal may be implemented with different ICs.

[0139] Furthermore, the second gate driver in the above embodiment 2 may be implemented with a single IC, or the gate driver for the WS signal, the gate driver for the Ref signal, and the gate driver for the INI signal may be implemented with different ICs.

[0140] Furthermore, in the above embodiment 2, the display device may be configured such that only the gate drivers for the WS signal are arranged on both sides of the display unit, and the gate drivers for the Ref signal and the gate drivers for the INI signal are arranged on one side of the display unit.

[0141] Furthermore, the control unit and data driver in each of the above embodiments may be implemented by a single IC, or they may be implemented by different ICs.

[0142] Furthermore, the initialization transistor T1 in each of the above embodiments G and T1 B The function and configuration of the initialization transistor T1 R It is the same as compensation transistor T2 G and T2 B The function and configuration of the compensation transistor T2 R It is the same as the writing transistor T3 G and T3 B The function and configuration of the writing transistor T3 is, for example, R It is the same as the drive transistor TD G and TD B The function and configuration of the drive transistor TD is, for example, R It may be the same as this.

[0143] Furthermore, the light-emitting element EL in each of the above embodiments G and EL B The functions and configuration of the light-emitting element EL are, for example, R It may be the same as this.

[0144] Furthermore, the holding capacity CS in each of the above embodiments G and CS B The functions and configuration include, for example, the holding capacity CS R It may be the same as this.

[0145] Furthermore, although the above embodiments have described examples of displaying color images, the display devices are not limited to this, and for example, they may also display monochrome images.

[0146] Furthermore, the write signal lines and selector control lines in each of the above embodiments may be provided, for example, parallel to each other with respect to the pixel rows. [Industrial applicability]

[0147] This disclosure is useful, for example, for display devices using organic EL elements. [Explanation of Symbols]

[0148] 1, 1a Display device 10, 10a Display Panel 11 Display section 12a First gate driver 12a1, 12b1 INI signal gate driver Gate driver for 12a2 and 12b2 Ref signals 12a3, 12b3 WS signal gate driver 12b Second gate driver 13 Data Driver 13a, 13b Data IC 20 Control Unit 30 power supply 110 pixels 110a First pixel 110b Second pixel 110B, 110G, 110R sub-pixels 120 Selector Circuit 120a, 120b switch section B_Sig, G_Sig, R_Sig, Sig1, Sig2, Sig3 data voltage lines CS B , CS G , CS R holding capacity EL, EL B , EL G , EL R Light-emitting element INI initialization signal line, control signal R dashed area REF Reference signal line, control signal line SEL, SEL1, SEL2, SEL3 Selector control lines, control signals SELa First Selector Control Line SELb Second selector control line T1 B , T1 G , T1 R Initialization transistor T2 B , T2 G , T2 R Compensation transistor T3, T3 B , T3 G , T3 R Writing transistor TD, TD B , TD G , TD R Driving transistor TS1, TS2, TSb, TSg, TSr, TW1, TW2, TWa, TWb, TWn-1, TWn input terminal TSeg B TSeg G TSeg R Selective transistor Vdat, Vdat_b, Vdat_g, Vdat_r Data voltage VREF Reference Voltage WS, WS1, TS2, TSn-1, TSn: Write signal line, control signal line △Vfs, △Vfs_sig, △Vfs_sig1, △Vfs_sig2, △Vfs_sig3, △Vfs_sig11, △Vfs_sig12, △Vfs_sig13, △Vfs_vg, △Vfs_vg1, △Vfs_vg2, △Vfs_vg3, △Vfs_vg11, △Vfs_vg12, △Vfs_vg13 Field-through voltage

Claims

1. Multiple pixels arranged in a matrix, A plurality of first gate control lines are arranged for each of the plurality of pixels, each being a different pixel row, and to which a first gate control signal is supplied for selecting the pixel row on which to write a data voltage corresponding to the image data; A first gate driver that supplies the first gate control signals to the plurality of first gate control lines, Multiple data voltage lines are arranged for each different pixel row in the aforementioned plurality of pixels, and are used to write data voltages corresponding to image data. A data driver that supplies the data voltage to the plurality of data voltage lines, A selector circuit is connected between the plurality of data voltage lines and the data driver, and switches the data voltage line that supplies the data voltage from the data driver. A first selector control line to which a selector control signal for controlling the selector circuit is supplied, The system comprises a control unit that supplies the selector control signal to the first selector control line, The plurality of pixels include a first pixel and a second pixel belonging to the same pixel row, The first gate driver supplies the first gate control signal to the plurality of first gate control lines so as to transmit it in a first direction from the first pixel to the second pixel, The control unit supplies the selector control signal to the first selector control line so as to transmit it in a second direction from the second pixel to the first pixel. Each of the plurality of pixels has a light-emitting element, moreover, A drive transistor connected to the anode of the light-emitting element, A plurality of second gate control lines are arranged for each row of pixels that are different from each other, and to which a second gate control signal is supplied for initializing the potential of the light-emitting element, A second gate driver that supplies the second gate control signals to the plurality of second gate control lines, A plurality of third gate control lines are arranged in each of the plurality of pixels, each being a different pixel row, and to which a third gate control signal is supplied for supplying a reference voltage to the gate electrode of the drive transistor, The system includes a third gate driver that supplies the third gate control signals to the plurality of third gate control lines, Each of the first gate driver, the second gate driver, and the third gate driver is arranged only on the first pixel side of the first pixel side and the second pixel side. The control unit further controls the first gate driver and, after the data voltage has been supplied to the plurality of data voltage lines and while the plurality of data voltage lines are in a floating state, causes the first gate control signal to be supplied. Each of the plurality of pixels has a write transistor connected between the data voltage line and the drive transistor, to which the first gate control signal is supplied. In the floating state, the control unit prevents the switching of transistors other than the write transistor provided by the pixels of the selected pixel row from the time the write transistor is turned on by the first gate control signal until it is turned off. The data driver has a plurality of data ICs (Integrated Circuits), each of which supplies a data voltage to a data voltage line. The selector circuit switches the connection between each of the plurality of data ICs and two or more adjacent data voltage lines among the plurality of data voltage lines that correspond to the data IC. Display device.

2. The first gate driver is connected to only the first pixel-side end of the plurality of first gate control lines, of which the first pixel-side end and the second pixel-side end are connected. The control unit is connected to only the second pixel-side end of the first selector control line, out of the first pixel-side end and the second pixel-side end of the first selector control line. The display device according to claim 1.

3. The ends of the multiple first gate control lines on the second pixel side are not connected to other gate drivers. The first pixel-side end of the first selector control line is not connected to any other control unit. The display device according to claim 2.

4. The light-emitting element is an organic EL (Electroluminescence) element. The display device according to any one of claims 1 to 3.

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