Error rate measuring device and error rate measuring method

Abstract

This invention provides an error rate measurement device and method that can detect specific patterns, such as sequence blocks, in real time from input signals from an object under test equipped with a link state management mechanism, and can clearly notify the user of the detection status of the specific pattern, including the detection timing. [Solution] The error rate measuring device 1 includes: a lead detection unit 603c that compares a reference signal with an input signal and detects the beginning of a specific pattern in the input signal; an ED5b that processes error rate measurement of a specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the lead of the specific pattern is detected by the lead detection unit 603c with the internal signal generated by the internal signal generation circuit 603a; a log information generation management unit 603g that generates log information of the detection status of the specific pattern after the lead is detected and stores it in the data storage unit 4a; and a display unit 3 that reads out the log information and displays it based on a predetermined display request operation.

Description

Technical Field

[0001] The present invention relates to an error rate measurement device having a function of generating and displaying log information indicating the reception status of an input signal pattern input from a measurement target, and an error rate measurement method.

Background Art

[0002] In protocols such as PCI Express (registered trademark) (Peripheral Component Interconnect Express) (hereinafter referred to as PCIe) and USB (registered trademark) (Universal Serial Bus), a sequence operation for controlling a link state management mechanism (Link Training and Status State Machine: LTSSM) and switching the state of a device is essential. By sending a plurality of prescribed data patterns (hereinafter referred to as "sequence blocks") to a device in the correct order, the state of the device can be arbitrarily changed.

[0003] For example, PCIe has standards such as Gen1 to Gen6, and the communication speed also varies in the range of 2.5 GT / s to 32 GT / s for each standard. All PCIe devices are backward compatible and can switch the communication speed. The state switching is also used for this communication speed switching.

[0004] For example, in PCIe, the state transition diagram of LTSSM is as shown in FIG. 10, and states such as L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery are defined.

[0005] Manufacturers of PCIe and USB devices, as well as their controllers, need to verify during device development testing whether the devices can correctly send and receive sequence blocks. Logic analyzers and protocol analyzers are used for this verification. However, many of these measuring devices lack real-time capabilities and cannot simultaneously acquire and analyze data. Furthermore, some sequence blocks have very long cycles, which can make analysis time-consuming for these devices.

[0006] An error rate measuring device is known as a measuring device that can acquire and analyze data simultaneously in real time (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Patent No. 7132964 [Overview of the project] [Problems that the invention aims to solve]

[0008] Device manufacturers need to verify that the devices they develop are performing the correct state transitions according to the input sequence blocks. Since the data output from the device is determined by the state, the state of the device can be understood by identifying the data output from the device.

[0009] However, while existing error rate measurement devices can measure the error rate of continuous data, they lacked a mechanism to detect instantaneous data of about 1 msec and notify the user of the detection.

[0010] Since error rate measurement devices do not measure the error rate unless they detect data, it is possible for users to know that data has been detected based on whether or not the error rate measurement is being performed. However, the update cycle of the GUI (Graphical User Interface) of conventional error rate measurement devices is about 100 msec, so there is a problem that users cannot visually confirm the detection of data unless the data is several hundred msec or longer. Furthermore, even if the data is several hundred msec or longer, if the entire sequence is long, it is not practical for the user to check when the display of a several hundred msec period occurred.

[0011] In particular, regarding the error rate measuring device described in Patent Document 1, the device is intended to measure the BER (Bit Error Rate) of the signal to be measured output from the object under test, and is not intended to detect a predetermined pattern itself. Furthermore, even if a pattern is detected, it is not possible to know when the pattern was detected or whether the pattern changed after detection. Therefore, there was a problem in that it was impossible for the user to know when the pattern was actually detected, or when the state changed and the expected pattern was no longer detected.

[0012] The present invention has been made to solve the above-mentioned conventional problems, and aims to provide an error rate measurement device and an error rate measurement method that can detect specific patterns such as sequence blocks in real time from input signals from an object under test equipped with a link state management mechanism, and can clearly notify the user of the detection status of the specific pattern, including the detection timing. [Means for solving the problem]

[0013] To solve the above problems, the error rate measuring device according to the present invention is an error rate measuring device (1) that measures the error rate of an input signal from an object under test (10) equipped with a link state management mechanism, comprising: an internal signal generation circuit (603a) that generates an internal signal consisting of a specific pattern that is expected to be output from the object under test according to the state of the link state management mechanism; a reference signal holding unit (603b) that holds a part of the beginning of the internal signal as a reference signal; and a leading unit that compares the reference signal with the input signal and detects the beginning of the specific pattern in the input signal ( The device is characterized by comprising: 603c) an error rate measurement unit (5b) that performs error rate measurement processing of the error rate of the specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the beginning of the specific pattern is detected by the beginning detection unit with the internal signal generated by the internal signal generation circuit; a log information generation management unit (603g) that generates log information of the detection status of the specific pattern after the beginning has been detected and stores it in a data storage unit (4a); and a display unit (3) that reads the log information based on a predetermined display request operation and displays it on a detailed result display screen (80).

[0014] With this configuration, the error rate measuring device according to the present invention can detect specific patterns such as sequence blocks in real time, generate and store log information of the reception status of said specific patterns, and, in response to a display request from the user, display the log information on a detailed results screen. This allows the user to be notified not only that a specific pattern has been detected, but also the time when the specific pattern was detected and the subsequent reception status, in a display format that is easier to understand.

[0015] In other words, the present invention is configured to add a function for detecting sequence blocks such as PCIe and USB to an error rate measuring device that can measure the error rate in real time. As a result, users can instantly confirm the presence of a specific sequence block without requiring time for analysis, thereby improving usability.

[0016] Furthermore, in the error rate measuring device according to the present invention, the log information generation management unit may be configured to generate log information that includes the time when the specific pattern was detected, a count value counted from a predetermined count start time of the detected specific pattern, and good / bad judgment information that determines whether the error rate for the detected specific pattern was successfully obtained (Gain) or not (Loss).

[0017] With this configuration, the error rate measurement device according to the present invention can easily recognize detailed reception status of a specific pattern by looking at the displayed log information, including when a specific pattern was detected, whether it was good or bad, and whether the state changed and the expected data was no longer detected.

[0018] Furthermore, the error rate measuring device according to the present invention may further include a latch unit (603e) for holding the detection signal, and the display unit may be configured to display a detection notification image (601) indicating that the beginning of the specific pattern has been detected by the beginning detection unit during the period in which the detection signal is held by the latch unit.

[0019] With this configuration, the error rate measuring device according to the present invention can, upon receiving a display indicating that a specific pattern has been detected, smoothly proceed with the operation to request the display of log information in order to further confirm the detailed reception status of that specific pattern.

[0020] Furthermore, in the error rate measuring device according to the present invention, the display unit may be configured to further display a hold release instruction unit (62) for releasing the hold of the detection signal by the latch unit.

[0021] With this configuration, the error rate measuring device according to the present invention allows the user to release the hold of the detection signal by the latch unit by operating the hold release instruction unit, thereby enabling the detection of a new specific pattern to be initiated.

[0022] Further, the error rate measurement apparatus according to the present invention may be configured to further include a delay circuit (603f) that delays the input signal in which the head of the specific pattern is detected by the head detection unit and synchronizes the internal signal output from the internal signal generation circuit with the specific pattern in the input signal.

[0023] With this configuration, the error rate measurement apparatus according to the present invention can measure the error rate of the specific pattern in the input signal by synchronizing the internal signal output from the internal signal generation circuit with the specific pattern in the input signal.

[0024] Further, the error rate measurement apparatus according to the present invention may be configured to further include a pulse pattern generator (5a) that transmits a sequence block for transitioning the link state management mechanism to an arbitrary state to the object under measurement.

[0025] [[ID=II]] With this configuration, since the error rate measurement apparatus according to the present invention includes a pulse pattern generator, it is possible to perform the transmission and operation confirmation of the sequence block for error rate measurement in one apparatus. As a result, the error rate measurement apparatus according to the present invention can reduce the time and cost required for the test process related to error rate measurement and improve the efficiency of the test process.

[0026] In order to solve the above problems, an error rate measurement method according to the present invention is an error rate measurement method executed by an error rate measurement apparatus (1) that measures the error rate of an input signal from an object under measurement (10) equipped with a link state management mechanism, the method including: an internal signal generation step (S3) of generating an internal signal composed of a specific pattern that is expected to be output from the object under measurement according to the state of the link state management mechanism; a reference signal holding step (S4) of holding a part of the head of the internal signal as a reference signal; a head detection step (S6) of comparing the reference signal with the input signal to detect the head of the specific pattern in the input signal; a detection signal synchronized with the timing at which the head of the specific pattern is detected by the head detection step; InsideAn error rate measurement step (S9) for measuring the error rate of the specific pattern in the input signal by sequentially comparing the internal signal generated by the internal signal generation circuit; a log information generation and management step (S10) for generating log information on the detection state of the specific pattern after the head is detected and storing it in the data storage unit (4a); and a display step (S18) for reading the log information based on a predetermined display request operation and displaying it on the detailed result display screen (80). It is characterized by including these steps.

[0027] With this configuration, the error rate measurement method according to the present invention detects a specific pattern such as a sequence block in real time, generates and stores log information on the reception status of the specific pattern, and in response to a display request from the user, by displaying the log information on the detailed result screen, it not only notifies the user that a specific pattern has been detected, but also notifies the user in a more understandable display form that includes the time when the specific pattern was detected and the subsequent reception status.

Effect of the Invention

[0028] The present invention can provide an error rate measurement device and an error rate measurement method that can detect a specific pattern such as a sequence block in real time from an input signal from a measurement object equipped with a link state management mechanism and clearly notify the user of the detection status of the specific pattern including the detection timing.

Brief Description of the Drawings

[0029] [Figure 1] It is a block diagram showing the configuration of an error rate measurement device according to an embodiment of the present invention. [Figure 2] It is a diagram showing an example of a result display screen displayed on a display unit provided in an error rate measurement device according to an embodiment of the present invention. [Figure 3] It is a diagram showing an example of a pattern setting screen having setting functions for both the PPG side and the ED side displayed on a display unit provided in an error rate measurement device according to an embodiment of the present invention. [Figure 4]Figure 3 shows an example of the pattern setting screen displayed on the ED side. [Figure 5] This figure shows an example of a sequence editing screen displayed on the display unit of an error rate measuring device according to an embodiment of the present invention. [Figure 6] This figure shows an example of a detailed results screen that displays log information managed by the log information generation and management function of the error rate measurement device according to an embodiment of the present invention. [Figure 7] This is a schematic diagram illustrating how to establish synchronization of the transmission start timing t0 of a specific pattern between the PPG and ED, where (a) shows the connection method between the PPG and ED, and (b) shows the timing of transmitted and received data. [Figure 8] This is a flowchart illustrating the process of an error rate measurement method using an error rate measurement device according to an embodiment of the present invention. [Figure 9] Figure 8 is a flowchart showing the processing operation of the detection notification in step S15. [Figure 10] This diagram shows the state transitions of LTSSM. [Modes for carrying out the invention]

[0030] Hereinafter, embodiments of the error rate measuring device and error rate measuring method according to the present invention will be described with reference to the drawings.

[0031] As shown in Figure 1, the error rate measuring device 1 according to this embodiment measures the error rate of the input signal from the device under test (DUT) 10, and is configured to include an operation unit 2, a display unit 3, a storage unit 4, a measurement unit 5, and a control unit 6.

[0032] The DUT10 is equipped with an LTSSM, and when the LTSSM transitions to one of the states shown in Figure 10, for example, it outputs a data pattern such as a sequence block corresponding to that state as an input signal to the error rate measurement device 1. For example, when the DUT10 transitions to the loopback state "LOOPBACK_ACTIVE_MASTER", it outputs the output signal from the pulse pattern generator (PPG) 5a, which will be described later, as an input signal to the error rate measurement device 1. Examples of standards that the DUT10 supports include PCIe Gen1~6, USB3.1 (Gen1), and USB3.2 (Gen2).

[0033] In the error rate measuring device 1 shown in Figure 1, the operation unit 2 is for receiving user input and consists of a user interface such as an operation knob, various keys, switches, buttons, and a touch panel, mouse, or keyboard for operating the GUI of the display unit 3, which is provided on the main body of the error rate measuring device 1.

[0034] The display unit 3 consists of various display screens and display devices such as an LCD (Liquid Crystal Display) that displays GUI elements such as soft keys.

[0035] The storage unit 4 stores various types of information and includes a data storage unit 4a, which is composed of memory such as RAM. The data storage unit 4a stores specific patterns that are expected to be output from the DUT 10 when the LTSSM of the DUT 10 transitions to an arbitrary state. The data storage unit 4a also stores these specific patterns in advance in file units. Furthermore, the data storage unit 4a has a log information storage area for storing log information generated by the log information generation management unit 603g, which will be described later.

[0036] The specific patterns stored in the data storage unit 4a are, for example, sequence blocks that control state transitions between multiple states managed by the LTSSM of the DUT10. The data storage unit 4a pre-stores known sequence blocks in file units that the DUT10 outputs when it transitions to each state.

[0037] For example, if the standard is PCIe Gen5 and the state of DUT10 is "LOOPBACK_ENTRY_MASTER_TS1", the sequence block output from DUT10 will be recorded in a file named "PCIe5_LOOPBACK_ENTRY_MASTER_TS1". Note that the file naming is not limited to the above; any name that clearly indicates the combination of standard and state to the user is acceptable.

[0038] Alternatively, the specific pattern may be a PRBS (Pseudo Random Binary Sequence) pattern or any data pattern set by the user.

[0039] For example, when the state of the DUT10 is "LOOPBACK_ACTIVE_MASTER", the data storage unit 4a may store information in file units for generating known patterns such as PRBS patterns and arbitrary data patterns set by the user, which will be described later, in the PPG5a and the internal signal generation circuit 603a.

[0040] The measurement unit 5 includes a PPG 5a and an error rate measurement unit (Error Detector: ED) 5b. The PPG 5a is configured to send a sequence block for transitioning the LTSSM of the DUT 10 to an arbitrary state as an output signal to the DUT 10. Furthermore, if the state of the DUT 10 is "LOOPBACK_ACTIVE_MASTER", the PPG 5a reads a specific pattern of data stored in the data storage unit 4a, performs appropriate encoding processing on the read specific pattern data, generates a test signal consisting of repetitions of the specific pattern, and sends the test signal as an output signal to the DUT 10. The specific pattern read from the data storage unit 4a by the PPG 5a is set or edited in the pattern setting screen 70 and sequence editing screen 90, which will be described later.

[0041] ED5b measures the error rate of a specific pattern in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit 603a in the control unit 6 (described later) with the input signal (detection signal) output from the delay circuit 603f. In this embodiment, the error rate is the bit error rate (BER) when the input signal is an NRZ (Non Return to Zero) signal, and the symbol error rate (SER) when the input signal is a PAM4 (Pulse Amplitude Modulation 4) signal.

[0042] The control unit 6 is composed of a control device such as a computer, which includes, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and an HDD (Hard Disk Drive), and comprehensively controls each part of the error rate measurement device 1 (operation unit 2, display unit 3, storage unit 4, and measurement unit 5).

[0043] The control unit 6 implements the functions of the display control unit 601, PPG control unit 602, and ED control unit 603 by executing the respective programs stored in, for example, RAM in the control device described above.

[0044] The display control unit 601 performs display control to display various information on the display unit 3 based on operations performed on the operation unit 2. In this embodiment, the display control unit 601 selectively displays various screens on the LCD constituting the display unit 3, such as the pattern setting screen 70 (see Figure 3), pattern setting screen 70B (see Figure 4), sequence editing screen 90 (see Figure 5), result display screen 60 (see Figure 2), and detailed result display screen 80 (see Figure 6), and also controls the GUI function that accepts desired settings and commands on each screen.

[0045] The PPG control unit 602 controls the operation of PPG5a and includes a pattern setting control unit 602a and a pattern generation control unit 602b. The pattern setting control unit 602a accepts the setting and editing of each setting item of a sequence block using the setting function (GUI function) of the communication standard of the DUT10 supported by the pattern setting screen 70, such as PCIe Gen4~6, and performs setting control to store the setting information of each setting item in the data storage unit 4a, for example. The pattern generation control unit 602b generates specific patterns corresponding to the sequence blocks set by the pattern setting screen 70 and controls PPG5a to send these specific patterns to the DUT10 in order.

[0046] The ED control unit 603 controls the operation of ED5b. For example, it controls ED5b to receive data patterns such as sequence blocks that DUT10 outputs back according to the state transitioned by receiving a sequence block from PPG5a and performing a state transition, and to perform a process to measure the error rate of the data pattern.

[0047] The ED control unit 603 is configured to include an internal signal generation circuit 603a, a reference signal holding unit 603b, a leading unit detection unit 603c, a detection signal output unit 603d, a latch unit 603e, a delay circuit 603f, and a log information generation management unit 603g.

[0048] The internal signal generation circuit 603a reads data of a specific pattern that is expected to be output from the DUT10 according to the state of the LTSSM of the DUT10 from the data storage unit 4a, performs appropriate encoding processing on the read data of the specific pattern, and generates an internal signal consisting of repetitions of the said specific pattern.

[0049] The internal signal generation circuit 603a generates an internal signal triggered by a detection signal output from the detection signal output unit 603d (described later), and outputs the generated internal signal to ED5b.

[0050] The ED control unit 603 controls the PPG 5a and the internal signal generation circuit 603a to generate the same specific pattern when the state of the DUT 10 is "LOOPBACK_ACTIVE_MASTER".

[0051] The reference signal holding unit 603b holds a portion of the beginning of an internal signal consisting of a specific pattern set in the pattern setting screen 70 (described later), for example, the first tens of bits of the specific pattern, as a reference signal.

[0052] The leading edge detection unit 603c compares the reference signal held by the reference signal holding unit 603b with the input signal from the DUT 10 to detect the beginning of a specific pattern in the input signal.

[0053] The detection signal output unit 603d outputs a detection signal synchronized with the timing at which the leading edge of a specific pattern is detected by the leading edge detection unit 603c to the internal signal generation circuit 603a and the latch unit 603e. In addition, the detection signal output unit 603d also outputs the input signal pattern at which the leading edge of a specific pattern is detected by the leading edge detection unit 603c to the delay circuit 603f.

[0054] The latch unit 603e is configured to hold the detection signal output from the detection signal output unit 603d. The latch unit 603e is also configured to release the held detection signal if the error rate measured by ED5b (described later) exceeds a predetermined value. This is because the input signal may contain the same data as the beginning of a specific pattern in a location different from the specific pattern. In such cases, the subsequent bits of the input signal will no longer match the specific pattern, resulting in a high error rate.

[0055] Furthermore, the latch unit 603e is configured to release the held detection signal when the "History Reset" button 62 is pressed on the results display screen 60, which will be described later. After the latch unit 603e releases the held detection signal, the lead detection unit 603c detects the beginning of a specific pattern included in the input signal again.

[0056] The delay circuit 603f is a circuit that delays the input signal in which the beginning of a specific pattern has been detected by the leading-point detection unit 603c, and synchronizes the internal signal output from the internal signal generation circuit 603a with the specific pattern in the input signal.

[0057] In other words, the internal signal generation circuit 603a generates an internal signal triggered by the detection signal, and the delay circuit 603f delays the input signal where the beginning of a specific pattern has been detected, so that an internal signal synchronized with the input signal is output to ED5b. As described above, ED5b measures the error rate of a specific pattern in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit 603a with the input signal output from the delay circuit 603f.

[0058] The log information generation and management unit 603g generates log information indicating the reception status of a specific pattern based on the detection of the beginning of a specific pattern in the input signal by the beginning detection unit 603c and the measurement results of the error rate measurement of the specific pattern by ED5b (see step S10 in Figure 8), and stores it in the data storage unit 4a. The log information generated and managed by the log information generation and management unit 603g includes, for example, the time (Time) when the specific pattern was detected, the count value (Count) counted from the predetermined start time of counting for the detected specific pattern, and good / bad judgment information that determines whether the error rate for the detected specific pattern was successfully obtained (Gain) or not (Loss).

[0059] Log information stored in the data storage unit 4a is read from the data storage unit 4a and displayed on the display unit 3 by display control in the display control unit 601 in response to a predetermined display request operation. As a predetermined display request operation, the user needs to, for example, press the "Sync Gain" tab 81 on the detailed results screen 80 (see Figure 6) which is displayed by pressing the "Details" soft key (not shown) on the main display screen 50.

[0060] By clicking the "Sync Gain" tab 81 on the detailed results display screen 80, the log information display area 85 is displayed at the bottom of the tab 81, along with the "Clear" button 82 and the "Save" button 83.

[0061] In the log information display area 85, log information is displayed horizontally, divided into the following items: "Time," "Count," and "Gain / Loss." "Time" refers to the time when the expected specific pattern was detected, and in this example, the detection time is displayed in picoseconds. "Count" refers to the count value counted from the predetermined start of counting for the detected specific pattern. "Gain" is information indicating the judgment result that the error rate for the detected specific pattern was successfully obtained, and "Loss" is information indicating the judgment result that the error rate was not successfully obtained. In short, "Gain / Loss" functions as good / bad judgment information for determining whether the error rate for the detected specific pattern was successfully obtained (Gain) or not (Loss).

[0062] Here, we will explain the concept of the starting point for "Time" and "Count," which constitute the log information. The detection time of a specific pattern displayed in the "Time" column and the count value displayed in the "Count" column are both the time and count value counted from the start of counting, that is, from the start timing t0 of the transmission of the specific pattern.

[0063] As connection methods for establishing synchronization of the start timing t0 of sending a specific pattern between PPG5a and ED5b, for example, as shown in Figure 7(a), there is a first connection method in which PPG5a, DUT10, and ED5b are connected via a normal data path, and a second connection method in which the output terminal of the trigger signal that PPG5a outputs at the start timing t0 of sending a specific pattern is connected to the AUX input terminal of ED5b for receiving the above trigger signal.

[0064] On the other hand, Figure 7(b) shows a comparison between the transmission timing at PPG5a and the reception timing at ED5b (with the expected value set to "#1") when PPG5a transmits #1 to #5.

[0065] According to the second connection method described above, by inputting a trigger signal to the AUX input terminal of ED5b at the transmission timing of #1 to #5 from PPG5a, it is possible to establish synchronization of the transmission start timing t0 of a specific pattern between PPG5a and ED5b, and to obtain accurate values ​​for "Time" and "Count".

[0066] Furthermore, even in the first connection method described above, for example, DUT10 outputs data corresponding to the output of PPG5a, so even if the output of PPG5a is different, the output of DUT10 (input of ED5b) may be the same.

[0067] Next, an example of the GUI function provided in the error rate measuring device 1 according to this embodiment will be described.

[0068] Figure 2 shows the result display screen 60 displayed by the display unit 3 when the "Result" tab 51a is pressed by the operation unit 2 in the screen selection tab 51 of the main display screen 50 displayed by the display unit 3.

[0069] The results display screen 60 includes an image 61 of "SyncGain", a "History Reset" button 62, and a text box 63.

[0070] The image of "SyncGain" (hereinafter also referred to as the "detection notification image") 61 on the results display screen 60 is an image that mimics an LED.

[0071] The detection notification image 61 changes from a black off state to a green on state when the beginning of a specific pattern set in the pattern setting screen 70 (described later) is detected consecutively a number of times set in the text box 63. Here, the text box 63 is used to set the number of detections required for the detection notification image 61 to change from the off state to the on state, and is placed, for example, near the detection notification image 61 on the results display screen 60.

[0072] When the "History Reset" button 62 is pressed by the operation unit 2, the detection notification image 61 turns black and turns off, at which point the detection signal held by the latch unit 603e is released. The "History Reset" button 62 constitutes a hold release instruction unit for releasing the hold of the detection signal by the latch unit 603e.

[0073] In other words, the detection notification image 61 indicates, in a green illuminated state, that the leading edge of a specific pattern has been detected by the leading edge detection unit 603c during the period when the detection signal is held by the latch unit 603e. Note that the color of the detection notification image 61 is not limited to the black and green described above, but may be any combination of colors.

[0074] Furthermore, the release of the detection signal retention by the latch unit 603e can be controlled not only by pressing the "History Reset" button 62 on the operation unit 2, but also by using a remote command from an external control device.

[0075] Furthermore, the result display screen 60 may have a text box 64 near the detection notification image 61 that indicates the number of times the detection signal was detected consecutively by the latch unit 603e.

[0076] Furthermore, the detection notification image 61 may change from a black off state to a green on state when the error rate of a specific pattern measured by ED5b falls below a predetermined error rate during the period when the detection signal is held by the latch unit 603e. This has the advantage of increasing the reliability of detecting the specific pattern. For this purpose, the result display screen 60 may have a text box 65 for setting a predetermined error rate at which the detection notification image 61 will be in a green on state.

[0077] Depending on the error rate set in text box 65, it may take more than 1 msec from the time the detection signal is held by the latch unit 603e until the detection notification image 61 turns green (for example, at least 1E9 bits of data are required to confirm that the error rate is 1E-9 or less).

[0078] In practical use, the error rate measuring device 1 according to this embodiment will detect sequence blocks of, for example, 1 msec or longer. However, synchronization by the delay circuit 603f is completed within tens to hundreds of microseconds (less than 1 msec) from the input signal from the DUT 10. This is the delay time from the input signal to the synchronization. However, since the final notification method to the user is display on the GUI of the display unit 3, the actual final delay time is the update cycle of the GUI of the display unit 3.

[0079] Figure 3 shows an example of the pattern setting screen 70, which has a structure in which the pattern setting screen 70A for the PPG5a side and the pattern setting screen 70B for the ED5b pattern are integrated on a single surface. According to the pattern setting screen 70, the sequence blocks 75 can be set in block units by appropriately operating soft keys, tabs, etc., or by entering appropriate commands in the text boxes on each of the pattern setting screens 70A and 70B.

[0080] In Figure 3, an example is shown of setting a sequence block related to PCIe3 as the communication standard in order to support testing of the PCIe device, which is DUT10. However, this pattern setting screen 70 also supports setting functions that support PCIe1 to 6 (and USB3.1 (Gen1) and USB3.2 (Gen2)) standards.

[0081] Figure 4 shows an example of settings corresponding to the PCIe5 standard in the pattern setting screen 70B on the ED5b side. This pattern setting screen 70B is displayed along with the pattern setting screen 70A on the PPG5a side (not shown in Figure 4) when the "Pattern" tab 51b is pressed by the operation unit 2 in the screen selection tab 51 of the main display screen 50 of the display unit 3.

[0082] The pattern setting screen 70B is a screen for setting a specific pattern and includes a "Test Pattern" pull-down menu 71, an Edit button 72, an "Edit File Name" label 73, and a pull-down menu 74 for selecting a standard.

[0083] The "Test Pattern" pull-down menu 71 allows the user to select a specific pattern, such as a sequence block, PRBS pattern, or arbitrary data pattern, via the operation unit 2. Figure 4 shows the state where "HSSB Data," which represents sequence block data, is selected.

[0084] The Edit button 72 is used to select a file from among multiple files stored in the data storage unit 4a that contains a specific pattern selected in the "Test Pattern" pull-down menu 71. When the Edit button 72 is pressed by the operation unit 2, a separate screen (not shown) opens, allowing for file loading, saving, bit-level editing, and other operations.

[0085] The label 73 labeled "Edit File Name" displays the filename of the file specified by the Edit button 72 from among the multiple files stored in the data storage unit 4a. In other words, a specific pattern recorded in the file displayed here is set in the PPG 5a and the internal signal generation circuit 603a. Figure 4 shows the state where the filename "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" is displayed.

[0086] The pull-down menu 74 allows you to selectively set the desired PCIe standards (Gen1-Gen6) for DUT10's operational verification, as well as USB 3.1 (Gen1) and USB 3.2 (Gen2), from the pull-down menus it provides.

[0087] Figure 5 shows the sequence editing screen 90, which can be accessed by pressing the "Sequence Edit" soft key 76 on the pattern setting screen 70 shown in Figure 3. The sequence editing screen 90 has soft keys 91 such as "Add," "Delete," "Copy," "Cut," "Paste," "Clear All," "OK," and "Cancel." On the sequence editing screen 90, by operating these soft keys 91, it is possible to select HSB standards (PCIe Gen1, 2, 3, 4, 5, 6, and USB3.1 (Gen1) and USB3.2 (Gen2)), edit specific pattern blocks (#0 to #n) defined by the selected standard (editing sequence blocks 92), save the setting information of the blocks (sequence blocks) to the data storage unit 4a, and read the saved sequence block setting information.

[0088] Figure 6 shows an example of the detailed results display screen 80, which is displayed by selecting the "Details (Slot 6)" button (not shown) on a predetermined display screen 51. When the "Sync Gain" tab 81 is operated on the detailed results display screen 80, tab information is read from the data storage unit 4a and displayed in the log information display area 85.

[0089] The detailed results display screen 80, along with the log information display area 85, displays a "clear" button 82 and a "Save" button 83.

[0090] In the detailed results display screen 80, the log information display area 85 displays log information consisting of items such as "Time" and "Gain / Loss" side by side.

[0091] The "Time" column displays the timing (detection time) when a specific pattern was detected. In this example, the detection time is displayed in picoseconds.

[0092] The "Count" column displays the count value of the specific pattern detected at the detection time shown in the "Time" column. In this example, the "Count" column displays a count value such as "123456".

[0093] The "Gain / Loss" column displays pass / fail judgment information used to determine the pass / fail status of a specific pattern, corresponding to the detection time shown in the "Time" column. The pass / fail judgment information displays (Gain) if the error rate result for the detected specific pattern was successfully obtained, and (Loss) if it was not successfully obtained.

[0094] As shown in Figures 2 and 3, the main display screen 50 has a measurement start button 53 for specifying the start of measurement and a measurement stop button 54 for specifying the stop of measurement.

[0095] When the measurement start button 53 is pressed by the operation unit 2, the PPG 5a sequentially outputs sequence blocks to the DUT 10 that control the state transitions of the DUT 10. Subsequently, as the DUT 10 sequentially transitions states and outputs a specific pattern recorded in the file displayed on the label 73 of "Edit File Name", the beginning detection unit 603c detects the beginning of this specific pattern, and the detection signal output unit 603d outputs a detection signal.

[0096] For example, as shown in Figure 4, if "HSSB Data" is selected in the "Test Pattern" pull-down menu 71 and "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" is specified in the "Edit File Name" label 73, then when DUT10 reaches the PCIe Gen5 "LOOPBACK_ENTRY_MASTER_TS1" state and outputs a sequence block of this state, the lead detection unit 603c detects the beginning of this sequence block and the detection signal output unit 603d outputs a detection signal.

[0097] Furthermore, the log information generation and management unit 603g, located in the ED control unit 603, generates log information of the detection status of a specific pattern after the first detection and stores it in the data storage unit 4a. This log information can be read based on a predetermined display request operation and displayed on the detailed results display screen 80.

[0098] Below, an example of the error rate measurement method using the error rate measurement device 1 of this embodiment will be described with reference to the flowchart in Figure 8. Note that explanations that overlap with the above-described explanation of the configuration of the error rate measurement device 1 will be omitted as appropriate.

[0099] First, the control unit 6 displays the main display screen 50 on the display unit 3 through the display control of the display control unit 601 (step S1).

[0100] Next, the user sets the specific pattern to be detected by selecting, for example, a file named "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" on the pattern setting screen 70B via the operation unit 2 (step S2).

[0101] Next, when the user presses the measurement start button 53 via the control unit 2, the internal signal generation circuit 603a generates an internal signal consisting of a sequence block which is a specific pattern recorded in the "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" file (internal signal generation step S3).

[0102] Next, the reference signal holding unit 603b holds a portion of the beginning of the sequence block recorded in the "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" file as a reference signal, as preparation for the process of detecting the beginning of a specific pattern in the following step S6 (reference signal holding step S4).

[0103] Next, when the user presses the measurement start button 53 via the operation unit 2, the pattern generation control unit 602b controls the PPG 5a to sequentially send sequence blocks that control state transitions to the DUT 10 (step S5).

[0104] Next, the lead detection unit 603c compares the reference signal with the input signal from the DUT 10 and detects the beginning of the sequence block recorded in the "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" file in the input signal (YES in lead detection step S6). Then, the detection signal output unit 603d outputs a detection signal synchronized with the timing at which the beginning of the sequence block was detected in lead detection step S6 to the internal signal generation circuit 603a, the latch unit 603e, and the delay circuit 603f (detection signal output step S7).

[0105] Next, the latch unit 603e holds the detection signal output from the detection signal output unit 603d (latch step S8).

[0106] Next, ED5b measures the error rate of a specific pattern in the input signal based on the internal signal generated by the internal signal generation circuit 603a in step S3 and the input signal (detection signal) output from the detection signal output unit 603d and delayed by the delay circuit 603f (error rate measurement step S9).

[0107] Next, the log information generation and management unit 603g generates log information (step S10) of the detection status of the detection signal whose beginning was detected in step S6. Here, the log information generation and management unit 603g collects the time when the beginning of the detection signal (specific pattern) was detected in step S6, the error rate measurement results of the specific pattern in the error rate measurement step S9 thereafter, and generates log information that reflects this collected data.

[0108] Specifically, the log information generation and management unit 603g generates log information (see Figure 6) that includes the time when a specific pattern was detected, the count value counted from the predetermined start time of counting for the detected specific pattern, and good / bad judgment information that determines whether the error rate for the detected specific pattern was successfully obtained (Good - Gain) or not obtained (Loss).

[0109] Next, the log information generation and management unit 603g stores the log information generated in step S10 in, for example, the data storage unit 4a of the storage unit 4 (step S11).

[0110] In this error rate measuring device 1, in parallel with the processing in steps S10 and S11 described above, a detection notification process is performed to notify that a specific pattern has been detected (step S15).

[0111] The detection notification processing in step S15 is carried out according to the procedure shown in Figure 9. In this detection notification processing, the display control unit 601 changes the detection notification image 61 on the result display screen 60 from an off state to an on state during the period in which the detection signal is held by the latch unit 603e, indicating that the beginning of a specific pattern has been detected in the beginning detection step S6 (display step S16).

[0112] Here, the user can recognize that a specific pattern has been detected by the fact that the detection notification image 61 on the results display screen 60 is lit. In this state, the user can display the log information held in step S11 on the display unit 3 by performing a predetermined display request operation. Specifically, for example, by returning to the main display screen 50 and pressing the "Details" soft key (not shown) to display the detailed results display screen 80, the user can display the log information by pressing the "Sync Gain" tab 81 (corresponding to a predetermined display request operation). Alternatively, the user can return to the results display screen 60 from the main display screen 50 and press the "History Reset" button 62 to instruct the system to turn off the detection notification image 61.

[0113] To achieve the above functional operation, the display control unit 601 controls the detection notification image 61 to an illuminated state in step S16, and then checks whether or not a display request operation requesting the display of log information has been received (step S17).

[0114] If the request to display log information is not accepted (NO in step S17), the process proceeds to step S19.

[0115] In response to this, if a request to display log information is received (YES in step S17), the display control unit 601 reads the log information from the log information storage area of ​​the data storage unit 4a and displays the log information using the detailed result display screen 80 (see Figure 6) (log information display step S18).

[0116] As shown in Figure 6, the detailed results display screen 80 displays log information including the detection time, count value, and pass / fail judgment information (Good (Gain) or Loss) for a specific pattern, allowing the user to understand the reception status of a specific pattern from this log information. Furthermore, on the detailed results display screen 80, the user can send and store the log information to an external storage medium by pressing the "Save" button 83, and can erase it by pressing the "Clear" button 82.

[0117] In step S18 above, when the detailed results display screen 80 is canceled and the system returns to the results display screen 60, the display control unit 601 then checks whether the "History Reset" button 62 has been pressed (step S19).

[0118] If it is determined that the "History Reset" button 62 has not been pressed (NO in step S19), the process described in steps S17 to S19 continues.

[0119] If, while the processes described in steps S17 to S19 are continuing, it is determined in step S19 that the "History Reset" button 62 has been pressed (YES in step S19), the latch unit 603e releases the hold of the detection signal (step S20).

[0120] Next, the display control unit 601 controls the result display screen 60 to change the detection notification image 61 from the lit state to the off state (step S21), and then proceeds to step S12 in Figure 8.

[0121] If the user presses the measurement stop button 54 on the results display screen 60 via the control unit 2 (YES in step S12), the process in this flowchart ends. On the other hand, if the user does not press the measurement stop button 54 via the control unit 2 (NO in step S12), the process from step S6 onwards is executed again.

[0122] (Regarding the role of log information generation and management unit 603g) As explained with reference to Figures 8 and 9, in the error rate measuring device 1 according to this embodiment, the PPG 5a sets specific patterns that are expected to be sent from the DUT 10 based on a predetermined operation sequence as sequence blocks for each block and sends them to the DUT 10 in order.

[0123] In response, DUT10 receives the sequence block sent from PPG5a, performs a state transition, and sequentially sends a specific pattern (an expected specific pattern) corresponding to that state, or, depending on the situation, a pattern different from the expected specific pattern, to the error rate measuring device 1.

[0124] On the other hand, the ED5b detects the pattern sent from the DUT10 using its error rate measurement function, i.e., the BERTS (Bit Error Rate Test Set) function. When a specific expected pattern is detected, the log information generation and management unit 603g generates and stores log information indicating the detection status of that specific pattern. This log information can be read from the data storage unit 4a by a predetermined display request operation and displayed on the detailed results display screen 80.

[0125] As shown in Figure 6, the log information includes the detection time of a specific pattern, the count value, and good / bad judgment information that determines whether the specific pattern is good (Gain) or bad (Loss).

[0126] This allows the user to view the detailed results screen 80 and recognize the detection time, gain, or loss status of a specific pattern. For example, they can see if a specific pattern was sent 100 times and received 100 times, or if it was received 90 times and not received 10 times. Furthermore, based on these recognition results, the completeness of the DUT10 as a product under operational verification can be evaluated, and if it is evaluated as not meeting the required level of completeness, debugging for performance improvement can be efficiently carried out.

[0127] As described above, the error rate measuring device 1 according to this embodiment comprises: a lead detection unit 603c that detects the lead of a specific pattern in the input signal; an ED5b that performs error rate measurement processing of a specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the lead of the specific pattern is detected by the lead detection unit 603c with an internal signal generated by the internal signal generation circuit 603a; a log information generation management unit 603g that generates log information of the detection status of the specific pattern after the lead is detected and stores it in the data storage unit 4a; and a display unit 3 that reads the log information based on a predetermined display request operation and displays it on the detailed result display screen 80.

[0128] With this configuration, the error rate measuring device 1 according to this embodiment can detect specific patterns such as sequence blocks in real time, generate and store log information of the reception status of the specific pattern, and display the log information on the detailed results display screen 80 in response to a display request from the user. This allows the user to be notified not only that a specific pattern has been detected, but also the time when the specific pattern was detected and the subsequent reception status, in a display format that is easier to understand.

[0129] In particular, according to the error rate measurement device 1 of this embodiment, by using ED5b to detect sequence blocks used in device testing such as PCIe and USB, the user can instantly confirm the presence of a specific sequence block without requiring time for analysis, which is expected to improve usability.

[0130] Furthermore, by using an error rate measurement device that combines PPG5a and ED5b, it becomes possible to send sequences for testing devices such as PCIe and USB and verify their operation with a single device. This streamlines the testing process, allowing users to reduce time and costs, and accelerating the development of DUT10.

[0131] Furthermore, in the error rate measurement device 1 according to this embodiment, the log information generation management unit 603g has a configuration that generates log information including the time when a specific pattern was detected, a count value counted from a predetermined count start time of the detected specific pattern, and good / bad judgment information that determines whether the error rate for the detected specific pattern was successfully obtained (Gain) or not (Loss).

[0132] With this configuration, the error rate measuring device 1 according to this embodiment can easily recognize the detailed reception status of a specific pattern by looking at the displayed log information, including when a specific pattern was detected, whether it was good or bad, and whether the state changed and the expected data was no longer detected.

[0133] Furthermore, the error rate measuring device 1 according to this embodiment further includes a latch unit 603e that holds a detection signal, and the display unit 3 is configured to display a detection notification image 61 indicating that the beginning of a specific pattern has been detected by the beginning detection unit during the period in which the detection signal is held by the latch unit 603e.

[0134] With this configuration, the error rate measuring device 1 according to this embodiment can, upon receiving a display indicating that a specific pattern has been detected, smoothly proceed with the operation to request the display of log information in order to further confirm the detailed reception status of that specific pattern.

[0135] Furthermore, in the error rate measuring device 1 according to this embodiment, the display unit 3 is configured to further display a hold release instruction unit 62 for releasing the hold of the detection signal by the latch unit 603e.

[0136] With this configuration, the error rate measuring device 1 according to this embodiment is configured so that the user can release the hold of the detection signal by the latch unit 603e by operating the hold release instruction unit 62, thereby enabling the detection of a new specific pattern to be started.

[0137] Furthermore, the error rate measuring device 1 according to this embodiment further includes a delay circuit 603f that delays the input signal in which the leading edge of a specific pattern has been detected by the leading edge detection unit 603c, and synchronizes the internal signal output from the internal signal generation circuit 603a with the specific pattern in the input signal.

[0138] With this configuration, the error rate measuring device 1 according to this embodiment can synchronize the internal signal output from the internal signal generation circuit 603a with a specific pattern in the input signal and measure the error rate of a specific pattern in the input signal.

[0139] Furthermore, the error rate measurement device 1 according to this embodiment further includes a PPG5a that transmits a sequence block to the DUT10 for transitioning the LTSSM to an arbitrary state.

[0140] With this configuration, the error rate measurement device 1 according to this embodiment is equipped with a PPG5a, making it possible to send out sequence blocks for error rate measurement and verify their operation in a single device. As a result, the error rate measurement device 1 according to this embodiment can reduce the time and cost required for the test process related to error rate measurement, thereby making the test process more efficient.

[0141] Furthermore, the error rate measurement method according to this embodiment is an error rate measurement method executed by an error rate measurement device 1 that measures the error rate of an input signal from a DUT 10 equipped with an LTSSM, and includes an internal signal generation step (S3) that generates an internal signal consisting of a specific pattern that is expected to be output from the DUT 10 according to the state of the LTSSM; a reference signal holding step (S4) that holds a part of the beginning of the internal signal as a reference signal; a lead detection step (S6) that compares the reference signal with the input signal to detect the beginning of the specific pattern in the input signal; an error rate measurement step (S9) that measures the error rate of the specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the lead of the specific pattern was detected by the lead detection step with an internal signal generated by the internal signal generation circuit 603a; a log information generation and management step (S10) that generates log information of the detection state of the specific pattern after the lead has been detected and stores it in the data storage unit 4a; and a display step (S18) that reads the log information based on a predetermined display request operation and displays it on the detailed result display screen 80.

[0142] With this configuration, the error rate measurement method according to the present invention detects specific patterns such as sequence blocks in real time, generates and stores log information of the reception status of said specific patterns, and displays the log information on the detailed results display screen 80 in response to a display request from the user. This allows the user to be notified not only that a specific pattern has been detected, but also the time when the specific pattern was detected and the subsequent reception status, in a display format that is easier to understand. [Industrial applicability]

[0143] As described above, the present invention has the effect of detecting specific patterns such as sequence blocks in real time from input signals from an object under test equipped with a link state management mechanism, and clearly notifying the user of the detection status of the specific pattern, including the detection timing. It is useful for error rate measuring devices and error rate measuring methods in general for sending sequence blocks to an object under test and verifying its operation. [Explanation of symbols]

[0144] 1. Error rate measuring device 2 Control section 3 Display section 4 Storage section 4a Data storage unit 5 Measuring part 5a Pulse pattern generator (PPG) 5b Error Rate Measurement Unit (ED) 6 Control Unit 10 Device under test (DUT) 50 Main display screen 60 Results display screen 61 Images (Detection Notification Images) 62 buttons 63-65 Text boxes 70 Pattern Settings Screen 70A PPG side pattern setting screen Pattern setting screen for the 70B ED side 71. Pull-down menu 72 Edit button 73 Labels 74 75, 92 Sequence Blocks 76. Soft keys for "Sequence Edit" 80 Detailed result display screen 81. The "Sync Gain" tab 82 "Clear" button 83. "Save" button 85 Log information display area 90 Sequence Editing Screen 91 soft keys 601 Display Control Unit 602 PPG Control Unit 602a Pattern setting control unit 602b Pattern generation control unit 603 ED Control Unit 603a Internal signal generation circuit 603b Reference signal holding section 603c Front detection unit 603d Detection signal output section 603e Latch section 603f delay circuit 603g Log Information Generation and Management

Claims

1. An error rate measuring device (1) that measures the error rate of an input signal from an object (10) under test equipped with a link state management mechanism, An internal signal generation circuit (603a) generates an internal signal consisting of a specific pattern that is expected to be output from the object under test according to the state of the link state management mechanism, A reference signal holding unit (603b) holds a portion of the leading edge of the aforementioned internal signal as a reference signal, A leading detection unit (603c) compares the reference signal with the input signal to detect the leading edge of the specific pattern in the input signal, An error rate measurement unit (5b) performs error rate measurement processing of the error rate of the specific pattern in the input signal by sequentially comparing a detection signal synchronized with the timing at which the leading edge of the specific pattern is detected by the leading edge detection unit with the internal signal generated by the internal signal generation circuit, A log information generation management unit (603g) generates log information of the detection status of the specific pattern after the detection of the beginning and stores it in the data storage unit (4a), An error rate measuring device characterized by comprising a display unit (3) that reads the log information based on a predetermined display request operation and displays it on a detailed results display screen (80).

2. The error rate measuring device according to claim 1, characterized in that the log information generation and management unit generates log information including the time when the specific pattern was detected, a count value counted from a predetermined count start time of the detected specific pattern, and good / bad judgment information that determines whether the error rate for the detected specific pattern was successfully obtained (Gain) or not (Loss).

3. The system further includes a latch (603e) that holds the detection signal, The error rate measuring device according to claim 1 or 2, characterized in that the display unit displays a detection notification image (601) indicating that the leading edge of the specific pattern has been detected by the leading edge detection unit during the period in which the detection signal is held by the latch unit.

4. The error rate measuring device according to claim 3, characterized in that the display unit further displays a hold release instruction unit (62) for releasing the hold of the detection signal by the latch unit.

5. The error rate measuring device according to claim 1, further comprising a delay circuit (603f) that delays the input signal in which the leading edge of the specific pattern has been detected by the leading edge detection unit, and synchronizes the internal signal output from the internal signal generation circuit with the specific pattern in the input signal.

6. The error rate measuring device according to claim 1 or 2, further comprising a pulse pattern generator (5a) that transmits a sequence block to the object under measurement for causing the link state management mechanism to transition to an arbitrary state.

7. An error rate measurement method performed by an error rate measuring device (1) that measures the error rate of an input signal from an object (10) equipped with a link state management mechanism, An internal signal generation step (S3) is to generate an internal signal consisting of a specific pattern that is expected to be output from the object under measurement according to the state of the link state management mechanism, A reference signal holding step (S4) in which a portion of the beginning of the aforementioned internal signal is held as a reference signal, A leading detection step (S6) involves comparing the reference signal with the input signal to detect the beginning of the specific pattern in the input signal, An error rate measurement step (S9) is performed by sequentially comparing a detection signal synchronized with the timing at which the beginning of the specific pattern is detected in the preceding beginning detection step with the internal signal generated by the internal signal generation circuit, thereby measuring the error rate of the specific pattern in the input signal. A log information generation management step (S11) involves generating log information of the detection status of the specific pattern after the detection of the leading element and storing it in the data storage unit (4a), An error rate measurement method characterized by including a display step (S18) of reading the log information based on a predetermined display request operation and displaying it on a detailed results display screen (80).

Images