Gaming machine

Abstract

To provide a game machine that can update a random number value appropriately.SOLUTION: A random number for a winning symbol and a random number for a normal symbol winning symbol can be updated in each update range in a common update process. As for the random number for the normal symbol winning symbol, the total number of random number values contained in the update range is a prime number. As for at least one of the random number values that can be updated in the common update process, the total number of random number values contained in the update range is a prime number. A performance control CPU 120 performs a variation start action of a decorative symbol while performing a reservation shift display with the start of a variable display. A common shift display can be performed when variable display is executed on the basis of a variation pattern specification command of a first type and when variable display is executed on the basis of a variation pattern specification command of a second type.SELECTED DRAWING: Figure 10-12

Description

Technical Field

[0001] The present invention relates to a gaming machine capable of playing games.

Background Art

[0002] As gaming machines such as pachinko gaming machines, there are gaming machines that manage various random numbers using hardware random numbers and software random numbers (for example, Patent Document 1). In addition, there are those in which variable display of a plurality of types of decorative identification information (decorative patterns) is performed corresponding to variable display of specific identification information (special symbols) (for example, see Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, there was room for improving the commercial value of gaming machines having the functions and configurations of Patent Documents 1 and 2.

[0005] This invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine with enhanced commercial value.

Means for Solving the Problems

[0006] The gaming machine according to claim 1 is a gaming machine capable of performing variable display of identification information and controlling to an advantageous state favorable to the player, and capable of executing variable display of specific identification information based on a plurality of types of variable display patterns including a predetermined variable display pattern. In a performance mode that includes a first performance mode and a second performance mode, it is possible to switch between and display multiple types of background images, including a first background image and a second background image. In the first performance mode, when switching the background image from a first background image corresponding to the first performance mode to a second background image corresponding to the first performance mode, it is possible to perform a background fade-out display by gradually increasing the transparency of the first background image corresponding to the first performance mode, and a background fade-in display by gradually decreasing the transparency of the second background image corresponding to the first performance mode. In the first performance mode, when the variable display of the identification information corresponding to the first performance mode is started, the transparency of the identification information corresponding to the first performance mode is set From the first value to the second value which is higher than the first value. It is possible to perform a gradual increase in the display of identification information as it fades out. In the first performance mode, when the variable display of the identification information corresponding to the first performance mode is terminated, the transparency of the identification information corresponding to the first performance mode is From the second value to the first value It is possible to perform a gradual fading-in display of identification information, In the second performance mode, when switching the background image from the first background image corresponding to the second performance mode to the second background image corresponding to the second performance mode, it is possible to perform a background fade-out display by gradually increasing the transparency of the first background image corresponding to the second performance mode, and a background fade-in display by gradually decreasing the transparency of the second background image corresponding to the second performance mode. In the second performance mode, when the variable display of the identification information corresponding to the second performance mode is started, the transparency of the identification information corresponding to the second performance mode is set From the first value to the second value It is possible to perform a gradual increase in the display of identification information as it fades out. In the second performance mode, when the variable display of the identification information corresponding to the second performance mode is terminated, the transparency of the identification information corresponding to the second performance mode is From the second value to the first value It is possible to perform a gradual fading-in display of identification information, In the first performance mode, the duration of the execution period for the identification information fade-in display. but Shorter than the execution period of the background fade-in display, In the second performance mode, the duration of the execution period for the identification information fade-in display. but Shorter than the execution period of the background fade-in display, In the first performance mode, the execution period of the identification information fade-out display. between length but Shorter than the duration of the background fade-out display, In the second performance mode, the length of the execution period for the identification information fade-out display. but Shorter than the duration of the background fade-out display, When specific identification information is displayed variably in the predetermined variable display pattern, the fade-out display of the identification information in the first performance mode can be performed over the first execution period. When specific identification information is displayed in a variable manner using the predetermined variable display pattern, the fade-out display of the identification information in the second performance mode can be performed over a second execution period different from the first execution period. For pending displays corresponding to variable displays that have not yet been started, it is possible to update the display up to a predetermined number of times. The aforementioned identification information includes a character representation, As a variable display of the aforementioned identification information, a scroll action and a pre-start action in which the character display operates before the start of the scroll action can be executed. The aforementioned pre-start action is performed after the pending display is updated. It is characterized by the following. [Brief explanation of the drawing]

[0007] [Figure 1] This is a front view of a pachinko game machine. [Figure 2] This is a diagram showing the configuration of various control boards and other components. [Figure 3] This figure shows an example of a random number generator used for gaming. [Figure 4] This flowchart shows the main processing for game control. [Figure 5] It is a flowchart showing an example of timer interrupt processing for game control. [Figure 6] It is a flowchart showing an example of special symbol process processing. [Figure 7] It is a diagram showing a configuration example of a special symbol process processing jump table. [Figure 8] It is a flowchart showing the main processing for effect control. [Figure 9] It is a flowchart or the like showing an example of effect control process processing. [Figure 10-1] It is a diagram showing a configuration example of a microcomputer for game control. [Figure 10-2] It is a diagram showing an example of an address map. [Figure 10-3] It is a diagram showing main setting examples of addresses included in the function setting register area. [Figure 10-4] It is a diagram showing main setting examples of addresses included in the function control register area. [Figure 10-5] It is a diagram for explaining a setting example of game random numbers. [Figure 10-6] It is a diagram for explaining the random number update cycle. [Figure 10-7] It is a flowchart showing an example of power supply start corresponding processing. <​​​​​​​​​​​​​​​​​​​ [Figure 10-15] This flowchart shows an example of the random number update process for determining initial values. [Figure 10-16] This flowchart shows an example of the process of passing through the start switch. [Figure 10-17] This diagram illustrates an example of using the data structure. [Figure 10-18] This flowchart shows an example of the normal processing of special symbols. [Figure 10-19] This diagram illustrates an example of using the data structure. [Figure 10-20] This is a flowchart showing an example of the special symbol detection process. [Figure 10-21] This diagram illustrates an example of using the data structure. [Figure 10-22] This is a flowchart showing an example of the process for setting special pattern information. [Figure 10-23] This flowchart shows an example of the process for selecting jackpot information data. [Figure 10-24] This diagram illustrates an example of using the data structure. [Figure 10-25] This diagram illustrates an example of using the data structure. [Figure 10-26] This is a flowchart showing an example of the process for setting the variation pattern. [Figure 10-27] This is a flowchart illustrating an example of the process for selecting a table of patterns that vary during a hit. [Figure 10-28] This is a flowchart illustrating an example of the process for selecting a table of variable patterns when a loss occurs. [Figure 10-29] This diagram illustrates an example of the configuration of a variation pattern type distribution table. [Figure 10-30] This diagram illustrates an example of the configuration of a variation pattern distribution table. [Figure 10-31] This diagram illustrates an example of the configuration of a variation pattern distribution table. [Figure 10-32] This diagram illustrates an example of the configuration of a variation pattern distribution table. [Figure 10-33]This is a flowchart illustrating an example of a typical pattern processing method. [Figure 10-34] This diagram illustrates an example of using the data structure. [Figure 10-35] This flowchart shows an example of gate switch passage processing. [Figure 10-36] This flowchart shows an example of normal processing for regular symbols. [Figure 10-37] This diagram illustrates an example of using the data structure. [Figure 11] This is a front view showing the gaming machine in Embodiment 1. [Figure 12] This is a diagram showing the various control boards and other components installed in a pachinko gaming machine. [Figure 13] This diagram illustrates the effects control commands. [Figure 14] This is an explanatory diagram showing each random number. [Figure 15] This is an explanatory diagram showing the display result determination table. [Figure 16] (A) is an explanatory diagram showing the jackpot type determination table, and (B) is an explanatory diagram of the jackpot types. [Figure 17] This is an explanatory diagram of the fluctuation pattern. [Figure 18] This is an explanatory diagram of the variation pattern determination table. [Figure 19] This is an explanatory diagram showing the data storage area for game control. [Figure 20] (A) is an explanatory diagram showing the data storage area for performance control, and (B) is an explanatory diagram showing the command buffer received when a prize is won at the start of the game. [Figure 21] This flowchart shows an example of the main game control process. [Figure 22] This flowchart shows an example of timer interrupt processing for game control. [Figure 23] This is a flowchart showing an example of the special pattern processing. [Figure 24] This is a flowchart showing an example of the process for determining whether a player has entered the competition at the start of the competition. [Figure 25]This flowchart shows an example of the normal processing of special symbols. [Figure 26] This is a flowchart showing an example of the main processing for controlling the visual effects. [Figure 27] This flowchart shows an example of the performance control process. [Figure 28] This flowchart shows an example of the variable display start setting process. [Figure 29] This is a diagram to explain the decorative patterns and sub-patterns. [Figure 30] (A1)(A2) shows the first performance mode, (B1)(B2) shows the second performance mode, (C1)(C2) shows the third performance mode, and (D1)(D2) shows the fourth performance mode. [Figure 31] (A1) and (A2) are diagrams showing the relationship between the variable display area and decorative symbols in the first performance mode, and (B1) and (B2) are diagrams showing the relationship between the variable display area and decorative symbols in the second performance mode. [Figure 32] (C1) and (C2) are diagrams showing the relationship between the variable display area and decorative symbols in the third performance mode, (D1) and (D2) are diagrams showing the relationship between the variable display area and decorative symbols in the fourth performance mode, and (E) is a diagram for explaining the variable display of decorative symbols and small symbols. [Figure 33] (A) is the action to start the change of the decorative pattern, (B) is the action to stop the change, and (C) is the loop action. [Figure 34] (A) is a diagram comparing the duration of various actions of decorative patterns and the control of lamp illumination, and (B) is a diagram showing an example of loop illumination control of the lamp. [Figure 35] (A1)~(A4) and (B1)~(B4) are diagrams illustrating examples of how the hold display works. [Figure 36] This diagram shows the variable display flow of decorative symbols in the first performance mode. [Figure 37] This figure shows the flow of variable display of decorative patterns, following Figure 36. [Figure 38] This diagram shows the variable display flow of decorative symbols in the second performance mode. [Figure 39] This figure shows the flow of variable display of decorative patterns, following Figure 38. [Figure 40] This figure shows the details of the variable display flow of the decorative pattern in Figure 38. [Figure 41] This diagram shows the flow of variable display of decorative patterns as an example of modification 1. [Figure 42] This figure shows the flow of variable display of decorative patterns, following Figure 41. [Figure 43] This diagram shows the variable display flow of decorative symbols in the third performance mode. [Figure 44] This is a diagram to explain how the decorative patterns appear. [Figure 45] This diagram shows the variable display flow of decorative symbols in the fourth performance mode. [Figure 46] This diagram shows the sequence of stop displays for decorative symbols in the first performance mode (second performance mode). [Figure 47] This diagram shows the sequence of stop displays for the decorative patterns, following Figure 46. [Figure 48] Figures (A) to (G) show the sequence of stop displays for decorative symbols when there are 3 reserved symbols in the first performance mode (second performance mode). [Figure 49] Figures (A) and (B) show the sequence of stop displays for decorative symbols in the fourth performance mode (third performance mode). [Figure 50] (A1) is a diagram showing the first background image, (A2) is a diagram showing the first predetermined background image, and (B) is a diagram explaining the background change. [Figure 51] This diagram shows the background change sequence in the first performance mode. [Figure 52] This is a timing chart showing the flow of each part of the variable display in the first performance mode. [Figure 53] This is a timing chart showing the flow of each part of the variable display in the second performance mode. [Figure 54] This is a timing chart showing the flow of each part of the variable display in the third and fourth performance modes. [Figure 55](A) shows the first presentation mode, (B) shows the second presentation mode, and (C) is a timing chart showing the states of each part at the start of variable display in the third and fourth presentation modes. [Figure 56] It is a diagram showing an operation example of a customer waiting demo presentation. [Figure 57] It is a diagram showing an operation example when a starting winning occurs during a customer waiting demo presentation. [Figure 58] It is a diagram showing the flow of pseudo consecutive announcements. [Figure 59] (A) is a diagram showing an example of pseudo consecutive number display and symbol color, (B) is a diagram showing the types of pseudo consecutive number display and symbol color, and (C) is a diagram showing a pseudo consecutive number display color determination table. [Figure 60] It is a diagram showing the flow of reach presentation. [Figure 61] It is a diagram showing the flow of reach presentation following FIG. 60. [Figure 62] It is a diagram showing an operation example of each part in reach presentation. [Figure 63] It is a diagram showing the flow of SP reach presentation. [Figure 64] It is a diagram showing the flow of SP reach presentation following FIG. 63. [Figure 65] It is a diagram showing an operation example of each part in SP reach presentation. [Figure 66] (A1) to (A7) are diagrams showing Modification 2 of the present invention. [Figure 67] (A) to (D) are diagrams showing Modification 3 of the present invention.

Mode for Carrying Out the Invention

[0008] (Basic Explanation) First, the basic configuration and control of the pachinko gaming machine 1 will be explained.

[0009] (Configuration etc. of the pachinko gaming machine 1) Figure 1 is a front view of the pachinko game machine 1, showing the layout of its main components. The pachinko game machine (game machine) 1 is broadly composed of a game board (gauge board) 2 that constitutes the game surface, and a game machine frame (frame) 3 that supports and fixes the game board 2. A game area is formed on the game board 2, and game balls, which serve as the game medium, are launched from a predetermined ball launching device and fired into this game area.

[0010] A first special symbol display device 4A and a second special symbol display device 4B are provided at predetermined positions on the game board 2. In the example shown in Figure 1, they are located on the right side of the game area. The first special symbol display device 4A and the second special symbol display device 4B can each perform variable displays of multiple types of special symbols as special identification information. Special symbols are also called "special symbols." The variable display of special symbols is also called a "special symbol game." Both the first special symbol display device 4A and the second special symbol display device 4B are constructed using 7-segment LEDs or the like. Special symbols are represented by numbers from "0" to "9," symbols such as "-", and other arbitrary lighting patterns. Special symbols may also include patterns in which all LEDs are turned off.

[0011] "Variable display" of special symbols refers to, for example, the display of multiple types of special symbols in a variable manner. Similarly, for other symbols such as performance symbols, small symbols, and regular symbols, "variable display" also refers to the display of multiple types of symbols in a variable manner. Performance symbols are also called decorative symbols or ornamental symbols. Variable display is also called variable display, or simply variable. Variation includes updating the display of multiple symbols, scrolling the display of multiple symbols, and transforming, enlarging, or shrinking one or more symbols. Variation may also include the display of a symbol blinking. In variable display of special symbols or regular symbols, multiple types of special symbols or regular symbols are displayed in an updated manner. In variable display of performance symbols, multiple types of performance symbols are displayed in a scrolling or updated display, or one or more performance symbols are transformed, enlarged, or shrunk. In variable display of any symbol, a predetermined symbol is displayed as the final display result. A stopped display is also called a derived display, or simply derived. In variable display, the symbol that is ultimately stopped and displayed is also called the final stop symbol or confirmed symbol. In special symbol games, the final stop symbol is also called the confirmed special symbol. The display result of the variable display includes the display result of the special symbol and is also called the variable display result. The display result of the special symbol is also called the special symbol display result. The execution time of the variable display includes the special symbol variation time, which is the variation time of the special symbol, and is also called the variable display time. The special symbol variation time can be set to different times corresponding to the variation patterns of the special symbol, of which multiple patterns are prepared in advance.

[0012] Special symbols that are variably displayed in the first special symbol display device 4A are also called "first special symbols." Special symbols that are variably displayed in the second special symbol display device 4B are also called "second special symbols." Special symbol games using the first special symbols are also called "first special symbol games." Special symbol games using the second special symbols are also called "second special symbol games." There may be only one type of special symbol display device that performs the variability display of special symbols.

[0013] A regular symbol display unit 20 is provided at a predetermined position on the game board 2. In the example shown in Figure 1, it is provided on the left side of the game area. The regular symbol display unit 20 can display a variable number of regular symbols, which are different from special symbols, as regular identification information. Regular symbols are also called "regular symbols." The variable display of regular symbols is also called a "regular symbol game." The regular symbol display unit 20 is constructed using 7-segment LEDs or the like. Regular symbols are represented by numbers from "0" to "9," symbols such as "-", and other arbitrary lighting patterns. Regular symbols may include patterns in which some or all of the multiple LEDs are lit, or patterns in which all of the multiple LEDs are turned off. The final stopping symbol in a regular symbol game is also called a confirmed regular symbol. The display result of the regular symbols is also called a regular symbol display result. The execution time during which the regular symbols are variably displayed in a regular symbol game is also called the regular symbol variation time. The regular symbol variation time can be set to different times corresponding to the variation patterns of the regular symbols, for which multiple patterns are pre-defined.

[0014] An image display device 5 is provided near the center of the game area on the game board 2. The image display device 5 can be any device capable of forming any image, such as an LCD (liquid crystal display), an organic EL (electroluminescence), a dot matrix LED, a projector and screen, a stereoscopic image projection device, or any other mechanism. The image display device 5 can display various types of performance images. Furthermore, the image display device 5 is not limited to performance images, but can also display any control-related images, such as inspection images or setting images.

[0015] For example, on the screen of the image display device 5, variable display of performance symbols can be performed in synchronization with the first special game and the second special game. Performance symbols are display symbols that show numbers, etc., and are multiple types of decorative identification information that are different from special symbols and ordinary symbols. On the screen of the image display device 5 shown in Figure 1, there are performance symbol display areas 5L, 5C, and 5R for the "left," "center," and "right," respectively, and variable display of performance symbols is performed in synchronization with the first special game or the second special game, for example, by scrolling or updating the performance symbols vertically. Synchronization of the variable display is sufficient if the timing at which the variation of the symbols starts and the timing at which the variation ends and the symbols finally stop are the same for different types of symbols. The final stopping symbol in the variable display of performance symbols is also called a confirmed performance symbol, confirmed decorative symbol, or confirmed ornamental symbol. The variable display of the performance symbols is synchronized with the first and second special symbol games, so the time for the variable display of the performance symbols is the same as the time for the special symbol variation.

[0016] The screen of the image display device 5 may be provided with display areas capable of displaying performance images corresponding to pending displays and active displays. A pending display is a display corresponding to a variable display that is pending and has not yet been executed. An active display is a display corresponding to a variable display that is currently being executed. Pending displays and active displays are also collectively referred to as variable display-compatible displays. The display area for pending displays is also called the pending display area. The display area for active displays is also called the active display area. The number of pending variable displays is also called the pending memory count. The pending memory count corresponding to the first special game is also called the first pending memory count. The pending memory count corresponding to the second special game is also called the second pending memory count. The sum of the first and second pending memory counts is also called the total pending memory count.

[0017] Above the first special symbol display device 4A and the second special symbol display device 4B shown in Figure 1, a first hold indicator 25A and a second hold indicator 25B, each composed of multiple LEDs, are provided. The first hold indicator 25A displays the first hold memory count by the number of lit LEDs. The second hold indicator 25B displays the second hold memory count by the number of lit LEDs. Above the normal symbol display device 20 shown in Figure 1, a normal symbol hold indicator 25C, composed of multiple LEDs, is provided. The normal symbol hold indicator 25C displays the normal symbol hold memory count by the number of lit LEDs. The normal symbol hold memory count is the hold memory count corresponding to the normal symbol game.

[0018] Below the image display device 5, a prize ball entry device 6A and a variable prize ball entry device 6B are provided. The prize ball entry device 6A forms a first starting prize entry opening that is always kept in a constant open state, allowing game balls to enter, by means of a predetermined ball receiving member, for example. The variable prize ball entry device 6B forms a second starting prize entry opening that can be changed between a closed state and an open state by a standard electric mechanism solenoid 81 shown in Figure 2, as a standard electric mechanism. The variable prize ball entry device 6B includes, for example, an electric tulip-type mechanism with a pair of movable wing pieces, and when the standard electric mechanism solenoid 81 is in the off state, the movable wing pieces are in a vertical position, so that the second starting prize entry opening is in a closed state where game balls cannot enter, or in a normally open state where it is difficult for game balls to enter. The variable prize ball entry device 6B, when the normal electric mechanism solenoid 81 is in the ON state, causes the movable wing piece to tilt, thereby opening the second starting prize entry point to either an open state allowing game balls to enter or an enlarged open state that facilitates game ball entry. The open state allowing game balls to enter or the enlarged open state that facilitates entry of the second starting prize entry point is also called the first variable state. The closed state in which game balls cannot enter the second starting prize entry point or the normal open state that makes entry difficult is also called the second variable state. The variable prize ball entry device 6B does not need to be one that can change between the first variable state and the second variable state, and is not limited to one equipped with an electric tulip-type mechanism.

[0019] When a game ball enters the first starting prize entry opening formed by the prize ball entry device 6A, this is also called a first starting prize. When a game ball enters the second starting prize entry opening formed by the variable prize ball entry device 6B, this is also called a second starting prize. A game ball that enters the first starting prize entry opening is detected by the first starting opening switch 22A shown in Figure 2. A game ball that enters the second starting prize entry opening is detected by the second starting opening switch 22B shown in Figure 2. Based on the occurrence of a first starting prize, a predetermined number of prize balls, such as 3, are dispensed, and the first reserved memory count can be updated to increment by 1. However, if the first reserved memory count has reached its upper limit, the first reserved memory count will not be updated even if a first starting prize occurs. When the first reserved memory count is incremented by 1, the first starting condition is met, and the first special symbol game, in which the first special symbol display device 4A variably displays special symbols, becomes executable. Based on the occurrence of a second start win, a predetermined number of prize balls, such as 3, are dispensed, and the second reserve memory count can be updated to increment by 1. However, if the second reserve memory count has reached its upper limit, the second reserve memory count will not be updated even if a second start win occurs. When the second reserve memory count is incremented by 1, the second start condition is met, and the second special symbol game, in which the second special symbol display device 4B variably displays special symbols, becomes playable.

[0020] A general prize entry point 10 is provided at a predetermined position on the game board 2, which is always kept in a constant open state by a predetermined ball receiving member. In the example shown in Figure 1, general prize entry points 10 are provided at two locations in the lower left of the game area. When a game ball enters either of the general prize entry points 10, a predetermined number of prize balls, such as 10, are dispensed.

[0021] In the game area formed by the game board 2, a first path and a second path are provided as flow paths for the game balls. The first path is mainly provided in the area to the left of the image display device 5 when viewed from the front. The second path is mainly provided in the area to the right of the image display device 5 when viewed from the front. The area to the left of the image display device 5 is also called the left game area or left play area. The area to the right of the image display device 5 is also called the right game area or right play area. The left game area and the right game area can be distinguished, for example, by the end face of the image display device 5 in the game area or by the arrangement of the game pins. Shooting the game ball towards the left game area to make it flow down the first path is also called left-handed shooting. Shooting the game ball towards the right game area to make it flow down the second path is also called right-handed shooting. The first path is also called the left-handed shooting path. The second path is also called the right-handed shooting path. The first and second routes may be composed of different routes, or they may be routes that share a portion of each other.

[0022] In response to the operation of the ball launching handle on the ball launching device, a game ball is launched from the ball launching device and driven into the game area. When a game ball driven into the game area is guided to the left game area and flows down the first path, it is guided, for example, along the arrangement of the game pins, making it impossible or difficult to guide it to the second path in the right game area. When a game ball driven into the game area is guided to the right game area and flows down the second path, it is guided, for example, along the arrangement of the game pins, making it impossible or difficult to guide it to the first path in the left game area.

[0023] The prize ball entry device 6A is provided in the first path in the left-side game area, allowing game balls flowing down the first path to enter. The variable prize ball entry device 6B is provided in the second path in the right-side game area, allowing game balls flowing down the second path to enter. The variable prize ball entry device 6B may also allow game balls flowing down the first path in the left-side game area to enter. The variable prize ball entry device 6B may be positioned so that game balls flowing down the second path in the right-side game area can enter more easily than game balls flowing down the first path in the left-side game area.

[0024] The second path in the right-side game area is provided with a passage gate 41 and a special variable prize ball device 50. The passage gate 41 forms a passage area through which game balls can pass. Game balls that have passed through the passage gate 41 are detected by the gate switch 21 shown in Figure 2. Based on the fact that game balls have passed through the passage gate 41, it becomes possible to add and update the normal reserve memory count, and as a normal symbol game, it becomes possible to perform variable display of normal symbols by the normal symbol display 20. The passage gate 41 can be configured as a normal symbol activation opening into which game balls can enter. In this case, the gate switch 21 can be configured as a normal symbol activation opening switch that can detect game balls that have entered the normal symbol activation opening.

[0025] The special variable prize ball device 50 forms a large prize opening that can be changed between a closed state and an open state by a large prize opening solenoid 82, acting as a special electric mechanism. The upper part of the special variable prize ball device 50 has a guide passage with a width in the front-to-back direction sufficient for game balls to pass through. This guide passage slopes downward from the right to the left, and walls are provided on both the front and back sides of the extended passage. In the center of the guide passage, a mechanism entrance that will become the large prize opening is formed. In the special variable prize ball device 50, a movable member 52 that can move in the front-to-back direction is provided as a large prize opening opening / closing member at a position where the large prize opening can be opened and closed. In the special variable prize ball device 50, a fixed member 53 is provided in the portion of the guide passage where the large prize opening is not formed, forming a fixed passage.

[0026] The movable member 52 is driven by the large prize opening solenoid 82 and is capable of moving forward and backward to open and close the prize opening, which is the entry point for the special prize. In the special variable prize ball device 50, game balls that enter the interior from the large prize opening are detected by the count switch 23. Inside the special variable prize ball device 50, there is a V prize area 51 which is a specific area that game balls can pass through. In addition, there is a normal area inside the special variable prize ball device 50 that is different from the V prize area 51. Above the V prize area 51, there is a plate-shaped distribution member that can switch the V prize area 51 between an open state and a closed state, acting as a V prize opening opening / closing member. The distribution member is driven by the specific area solenoid 83 and is capable of moving forward and backward to open and close the V prize area 51. When the V prize area 51 is in the open state, game balls can pass through, and when it is in the closed state, game balls cannot pass through. Game balls that pass through the V-winning area 51 are detected by the specific area switch 24. Game balls that do not pass through the V-winning area 51 pass through the normal area. Both game balls that pass through the V-winning area 51 and game balls that pass through the normal area without passing through the V-winning area 51 are detected by the discharge switch 26 and then discharged to the outside of the special variable prize ball device 50.

[0027] In addition to the above configuration, the surface of the game board 2 is equipped with a windmill and numerous obstacle pins that change the direction and speed of the game balls. At the bottom of the game area, there is an outlet for game balls that do not enter any of the winning pockets. Speakers 8L and 8R for playing and outputting sound effects are provided at the upper left and right positions of the game machine frame 3, and game effect lamps 9 for lighting effects are provided around the game area. The game effect lamps 9 are composed of LEDs. A movable body 32 that operates according to the effects is provided at a predetermined position on the game board 2.

[0028] A ball-shooting operation handle is provided at the lower right position of the gaming machine frame 3, which is operated by the player or others to launch game balls towards the game area using a ball-shooting device. The ball-shooting operation handle is also called an operating knob. A ball-shooting supply tray is provided at a predetermined position on the gaming machine frame 3 below the game area, which holds game balls dispensed as prize balls and game balls dispensed by a predetermined ball-dispensing machine so that they can be supplied to the ball-shooting device. The ball-shooting supply tray is also called an upper tray. Below the upper tray is a prize ball storage tray, into which prize balls dispensed when the upper tray is full flow down and are stored. The prize ball storage tray is also called a lower tray.

[0029] A stick controller 31A and a push button 31B are provided at predetermined positions on the gaming machine frame 3 below the gaming area. The stick controller 31A can be grasped and tilted by the player, and is equipped with a trigger button that the player can push and pull. Operation on the stick controller 31A is detected by the controller sensor unit 35A shown in Figure 2. The push button 31B can be pressed by the player. Operation on the push button 31B is detected by the push sensor 35B shown in Figure 2. In the pachinko gaming machine 1, the stick controller 31A and the push button 31B are used as detection means to detect actions such as player operations, but other detection means may also be used.

[0030] (Outline of how the game progresses) The player rotates the ball-shooting handle on the pachinko game machine 1, launching the game ball towards the game area. When the game ball passes through the passage gate 41, the regular symbol game is started by the regular symbol display unit 20. However, if the game ball passes through the passage gate 41 during the period when the previous regular symbol game is in progress, the regular symbol game based on that passage cannot be immediately executed, so the regular symbol game based on that passage is held in reserve until a predetermined upper limit, such as "4", is reached. In the regular symbol game, when a specific regular symbol, such as a regular symbol winning symbol, is displayed as a confirmed regular symbol, the display result of the regular symbol becomes "regular symbol win". Conversely, when a regular symbol other than a regular symbol, such as a regular symbol losing symbol, is displayed as a confirmed regular symbol, the display result of the regular symbol becomes "regular symbol loss". When it is a "regular symbol win", the variable prize ball device 6B is opened or wide-open for a predetermined period of time. At this time, the second starting prize entry point opens or expands to an open state.

[0031] When a game ball passes through the first starting entry opening formed in the prize ball entry device 6A, the first special symbol game can be started by the first special symbol display device 4A. When a game ball passes through the second starting entry opening formed in the variable prize ball entry device 6B, the second special symbol game can be started by the second special symbol display device 4B. However, if a special symbol game is in progress, or if the game is controlled to be in a jackpot or minor jackpot state, even if a game ball enters the starting entry opening and a starting entry occurs, the special symbol game based on that starting entry cannot be immediately executed. Therefore, the special symbol game based on that starting entry is held up to a predetermined upper limit, such as "4". In the special symbol game, when a specific special symbol, such as a jackpot symbol, is displayed as a confirmed special symbol, the display result of the special symbol becomes "jackpot". In contrast, if a designated special symbol different from the jackpot symbol, such as a minor win symbol, stops and is displayed as a confirmed special symbol, the display result of the special symbol will be "minor win". Also, if a special symbol different from the jackpot symbol or minor win symbol, such as a losing symbol, stops and is displayed as a confirmed special symbol, the display result of the special symbol will be "loser". Furthermore, if a special symbol different from the jackpot symbol, minor win symbol, or losing symbol, such as a time-saving symbol, stops and is displayed as a confirmed special symbol, the display result of the special symbol may be "time-saving". Special symbols do not necessarily have to include time-saving symbols. In other words, the display result of the special symbol does not necessarily have to include "time-saving".

[0032] In the special symbol game, after the display result of the special symbol is a "jackpot," the game is controlled to a jackpot game state, which is an advantageous state for the player. In the jackpot game state, the large prize slot formed in the special variable prize ball device 50 can be opened in a predetermined manner. This open state continues until the earlier of the following timings: the passage of a predetermined period, such as 29 seconds or 1.8 seconds, or the timing when the number of game balls that have entered the large prize slot reaches a predetermined number. The predetermined period during which the large prize slot can be controlled to be open is the upper limit period for which the large prize slot can be opened in one round, and is also called the upper limit period of opening. One cycle in which the large prize slot is open in the jackpot game state is called a round or round game. In the jackpot game state, such rounds can be repeated until a predetermined upper limit is reached, such as 15 times or 2 times. In the jackpot game state, the player can obtain prize balls by getting game balls into the large prize slot. Therefore, the jackpot state is an advantageous state for the player. The more rounds there are in the jackpot state, and the longer the maximum period of play, the more advantageous it is for the player.

[0033] When the display result of a special symbol is "Big Win," it includes multiple types of big wins. For example, the opening manner of the big prize slot, such as the number of rounds and the maximum opening period, and the game state after the end of the big win game state, such as the normal state, time-saving state, and probability change state, can be set to multiple different types, and a type of big win is specified corresponding to each setting. Multiple types of big wins may include some or all of the types of big wins that award many prize balls, types that award few prize balls, or types that award almost no prize balls, or they may include types of big wins with a similar amount of prize balls that can be obtained. Controlling the game state to a big win state based on the display result of a special symbol being "Big Win" is also called a symbol big win, a big win by a special symbol, a variable display big win, or a direct hit big win.

[0034] In the special symbol game, after the display result of the special symbol is "minor win," the game is controlled to a minor win game state. In the minor win game state, the large prize slot formed in the special variable prize ball device 50 can be opened in a predetermined opening manner. For example, in the minor win game state, the large prize slot may be opened in the same opening manner as in the jackpot game state for some jackpot types. The large prize slot can be opened in the same manner by having the same number of openings and opening period. Alternatively, in the minor win game state, the large prize slot may be opened in a different opening manner than in the jackpot game state. Similar to jackpot types, there may be multiple minor win types when the display result of the special symbol is "minor win." Jackpot types and minor win types are also collectively referred to as win types. The operation of opening and closing the large prize slot in the minor win game state is also called the starting operation. When the game is in a minor win state, the entry point for the special variable prize ball device 50, which is the main prize entry point, is opened, and when the game ball passes through the V prize area 51 and is detected by the specific area switch 24, the conditions for a big win are met, and the game can be controlled to a big win state. When the game is controlled to a big win state based on the occurrence of a V prize by the game ball passing through the V prize area 51 in a minor win state, it is also called a big win via a minor win.

[0035] After a jackpot game state ends, the game state can be controlled to a time-saving state or a probability variation state, corresponding to the type of jackpot. Also, in the special symbol game, after the display result of the special symbol is "time-saving," the game state is controlled to the time-saving state without being controlled to a jackpot game state. The time-saving state is a game state in which the second special symbol game by the second special symbol display device 4B is more likely to be executed than in the normal state. A game state in which the second special symbol game is more likely to be executed than in the normal state is a game state in which the game ball is more likely to pass through and enter the second starting prize entry point than in the normal state. The control of whether or not the game ball is likely to pass through the second starting prize entry point is also called base control. Base control in the normal state is also called normal base control or low base control. Base control in the time-saving state includes high base control. In addition to high base control, the time-saving state may also include medium base control. Medium base control is a base control that makes it easier for game balls to pass through the second starting prize entry point than low base control, but makes it more difficult for game balls to pass through the second starting prize entry point than high base control. The game state in which medium base control is performed is also called the medium base state. The game state in which high base control is performed is also called the high base state. High base control is also called high open control.

[0036] In the normal state, the medium base state, and the high base state, it is possible to display the time-saving symbol as a result of displaying the special symbol. However, in the medium base state and the high base state, even if the time-saving symbol is displayed as a result of displaying the special symbol, no base control based on that time-saving symbol is performed, and no new control to transition to the medium base state or high base state is initiated. In the time-saving state, time-saving control is possible, which shortens the average variable display time compared to the normal state. For this reason, the time-saving state is also called the time-reduced state.

[0037] The time-saving state is a state in which the efficiency of special symbols, especially the second special symbol, is improved, and is therefore included in the category of special states that are advantageous to the player, different from the jackpot game state. When the game state is a probability variation state, in addition to time-saving control, probability variation control is possible in which the probability of the special symbol display result being a "jackpot" is higher than in the normal state. For this reason, the probability variation state is also called the probability variation state. The probability variation state is a state in which the efficiency of special symbol fluctuations is improved and it is easier to get a "jackpot", and is therefore included in the category of special states that are advantageous to the player, different from the jackpot game state. The time-saving state and probability variation state continue until one of the predetermined termination conditions is met first, such as the execution of a predetermined number of special symbol games or the game being controlled to the next jackpot game state. When the termination condition is the execution of a predetermined number of special symbol games, it is also called a count cut. The time-saving state with a count cut is also called a count cut time-saving state. The probability variation state with a count cut is also called a count cut probability variation state.

[0038] The normal game state is a game state that is not included in advantageous states such as the jackpot game state, predetermined states such as the minor win game state, or special states such as the time-saving state or the probability variation state. The normal state is a game state in which the probability of the display result in the normal game being "normal win" and the probability of the display result in the special game being "jackpot" are controlled to be the same as the initial setting state of the pachinko machine 1. The initial setting state of the pachinko machine 1 is the control state after the initial setting process is executed without executing the predetermined recovery process after power-on, for example, when a system reset is performed.

[0039] The state in which probability variation control is being performed is also called the high probability state, and the state in which probability variation control is not being performed is also called the low probability state. The state in which time reduction control is being performed is also called the high base state, and the state in which time reduction control is not being performed is also called the low base state. Combining these, the time reduction state is also called the low probability high base state, the probability variation state is also called the high probability high base state, and the normal state is also called the low probability low base state. The state that is both high probability and low base is also called the high probability low base state. Note that pachinko game machine 1 may not include the probability variation state as a game state.

[0040] After the minor win game state ends, there are cases where the game state is controlled to a big win game state based on the occurrence of a V-win, and cases where the game state remains unchanged from before the minor win game state if a V-win does not occur. However, if the display result of the special symbol game is "minor win" and the special symbol game is executed for a predetermined number of times in the count limit, the control of the time-saving state or probability change state may end and the game may return to the normal state. Note that the pachinko game machine 1 may not include the minor win game state as a game state. In other words, the display result of the special symbols may not include "minor win".

[0041] If a time-saving condition based on the number of times the variable display is executed is met, the game state may be controlled to a time-saving state. Such a time-saving state is also called a rescue time-saving state. The time-saving condition is one that can be met when, after power is turned on to the pachinko game machine 1, after a jackpot occurs, or after the display result of the special symbol game becomes "time-saving," the variable display is executed a specific number of times but control to a new jackpot game state or time-saving state is not performed.

[0042] (Regarding the progress of the performance, etc.) In the pachinko game machine 1, various effects can be executed in accordance with the progress of the game. These effects include effects that notify the progress of the game and effects that enhance the excitement of the game. These effects include displaying various effect images on the image display device 5, outputting sound effects from speakers 8L and 8R, lighting up the game effect lamp 9, operating the movable body 32, vibrating the stick controller 31A and push button 31B, or any combination of some or all of these, and can be executed using any effect device.

[0043] The effects that can be executed in accordance with the progress of the game include the variable display of effect symbols. When the first or second special symbol game starts, the variable display of effect symbols starts in the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R provided on the screen of the image display device 5. When the confirmed special symbol that will be the display result in the first or second special symbol game stops and is displayed, the confirmed effect symbol that will be the display result in the variable display of effect symbols stops and is displayed. The confirmed effect symbol consists of a combination of three effect symbols corresponding to the "left," "center," and "right" effect symbol display areas 5L, 5C, and 5R. During the period from when the variable display of effect symbols starts until it ends, the display mode in the variable display of effect symbols may become a reach mode. A reach mode is a mode in which the effect symbols that have stopped on the screen of the image display device 5 form part of a jackpot combination, and the variation of the effect symbols that have not yet stopped continues. When the display pattern of the reel symbols in the animation becomes a "reach" pattern, it is also said that a "reach" is established.

[0044] The pachinko machine 1 can execute a reach animation in response to the variable display of the animation symbols becoming a reach animation. The pachinko machine 1 can execute multiple types of reach animations such that the proportion of "jackpot" results in the variable display differs depending on the animation animation type. The proportion of "jackpots" corresponding to the animation animation type is also called the jackpot reliability or jackpot expectation. Reach animations include, for example, a normal reach and a super reach which has a higher jackpot reliability than a normal reach. In addition, depending on the execution time of the reach animation, it may also include a short reach and a long reach which has a longer execution time than a short reach.

[0045] When the display result of the special symbols is a "jackpot," the confirmed winning symbols, which are predetermined jackpot combinations, are stopped and displayed on the screen of the image display device 5 as the display result of the winning symbols. For example, identical winning symbols, such as a winning symbol showing the number "7," are lined up and stopped and displayed on a predetermined active line in the "left," "center," and "right" winning symbol display areas 5L, 5C, and 5R. In the case of a "probability-increasing jackpot," which is controlled to a probability-increasing state after the jackpot game state ends, odd-numbered winning symbols, such as a winning symbol showing the number "7," may be lined up and stopped and displayed. In the case of a "non-probability-increasing jackpot," which is not controlled to a probability-increasing state after the jackpot game state ends, even-numbered winning symbols, such as a winning symbol showing the number "6," may be lined up and stopped and displayed. A "non-probability-increasing jackpot" is also called a "normal jackpot." In this case, odd-numbered winning symbols are also called probability-increasing symbols. Even-numbered winning symbols are also called non-probability-increasing symbols or normal symbols. It is also possible to have a bonus round sequence that starts with a non-bonus symbol and then ultimately results in a "bonus jackpot."

[0046] When the display result of the special symbols is a "minor win," the confirmed winning symbols, which are predetermined minor win combinations, are stopped and displayed on the screen of the image display device 5 as the display result of the winning symbols. For example, the same winning symbols, such as winning symbols showing numbers other than "7," may be lined up and stopped and displayed on a predetermined active line in the "left," "center," and "right" winning symbol display areas 5L, 5C, and 5R. The same confirmed winning symbols may be stopped and displayed whether the display result of the special symbols is a "big win" or a "minor win."

[0047] When the display result of a special symbol is a "miss," the variable display of the performance symbols may not result in a reach pattern, and the display result may simply stop. In this case, the display result of the performance symbols will be a confirmed performance symbol that is not a reach combination. A display result in which a confirmed performance symbol that is not a reach pattern is simply stopped without resulting in a reach pattern is also called a "non-reach miss." When the display result of a special symbol is a "miss," the variable display of the performance symbols may result in a reach pattern, and the display result may stop after the reach animation is executed. In this case, the display result of the performance symbols will be a confirmed performance symbol that is not a big win combination or a small win combination. A display result in which a confirmed performance symbol of a reach combination is simply stopped after a reach pattern has been created is also called a "reach miss."

[0048] The effects that the pachinko game machine 1 can perform include variable display-compatible displays such as hold displays and active displays. In addition, for example, a pre-announcement effect that foreshadows the probability of a big win can be performed while the display of the performance symbols is variable. The pre-announcement effect may include a variable pre-announcement effect that foreshadows the probability of a big win corresponding to the variable display that is currently being performed, and a pre-announcement effect that foreshadows the probability of a big win corresponding to the variable display that is currently pending execution. The pre-announcement effect may perform a change effect that changes the display mode of the variable display-compatible displays, such as hold displays and active displays, to a mode different from the normal mode.

[0049] On the screen of the image display device 5, it may be possible to perform a pseudo-consecutive display by temporarily pausing the display of the performance symbols during their variable display and then resuming the variable display, thereby making one variable display appear as if it were multiple variable displays. The pseudo-consecutive display may be set so that the probability of a big win is higher when there are more re-spins after temporarily pausing the display of the performance symbols than when there are fewer re-spins. The pseudo-consecutive display of the performance symbols may include cases where the pseudo-consecutive display is performed before the reach state is reached, and cases where the pseudo-consecutive display is performed after the reach state is reached. In addition, it may be possible to perform the pseudo-consecutive display of the performance symbols at multiple timings.

[0050] During control of a jackpot game state, a jackpot animation can be executed to notify the player of the jackpot game state. The jackpot animation may include an animation that notifies the number of rounds and an upgrade animation that suggests or notifies an improvement in the advantage of the jackpot game state. During control of a minor win game state, a minor win animation can be executed to notify the player of the minor win game state. By executing the same animation during control of the jackpot game state and during control of the minor win game state, it may be made impossible or difficult for the player to recognize whether the current game state is a jackpot game state or a minor win game state.

[0051] In a non-game state where no special feature games or other events are being played and the game is not progressing, demonstration images can be displayed on the screen of the image display device 5. Demonstration images are also called demo images. Displaying demo images is also called a demo display. The performance using the demo display is also called a customer-waiting demo performance.

[0052] (Circuit board configuration) The pachinko game machine 1 is equipped with, for example, a main board 11, a performance control board 12, a sound control board 13, a lamp control board 14, a relay board 15, a power supply board 17, and other components as shown in Figure 2. In addition, various other boards are located on the back of the pachinko game machine 1, such as a payout control board, an information terminal board, and a launch control board.

[0053] The main board 11 is the main control board and has the function of controlling the progress of the game in the pachinko game machine 1. The progress of the game includes the execution of special game with reserve management, execution of regular game with reserve management, big win game state, small win game state, time-saving state, probability change state, etc., as well as the execution of various game states and transitions between game states. The main board 11 includes a game control microcomputer 100, a switch circuit 110, and a solenoid circuit 111.

[0054] The game control microcomputer 100 on the main board 11 is, for example, a single-chip microcomputer and can be configured to include a ROM (Read Only Memory) 101, a RAM (Random Access Memory) 102, a CPU (Central Processing Unit) 103, a random number circuit 104, and an I / O (Input / Output port) 105. Some or all of the ROM 101, RAM 102, and random number circuit 104 may be configured to be externally connected to the game control microcomputer 100, or they may be built into the game control microcomputer 100. The switch circuit 110 receives detection signals from various switches for detecting game balls and transmits them to the game control microcomputer 100. The various switches for detecting game balls include, for example, a gate switch 21, starter switches such as the first starter switch 22A and the second starter switch 22B, a count switch 23, a specific area switch 24, and an outlet switch 26. The detection signal indicates that a game ball has passed through or entered, causing the switch to be turned on. The transmission of the detection signal indicates that the passage or entry of a game ball has been detected. The solenoid circuit 111 can supply solenoid drive signals from the game control microcomputer 100 to the ordinary electric prize solenoid 81, the large prize winning slot solenoid 82, and the specific area solenoid 83. The solenoid drive signals can be any signals that turn on each solenoid.

[0055] The ROM 101 in the game control microcomputer 100 is a non-volatile memory device that stores computer programs and data used for game control. The data stored in the ROM 101 includes variable patterns, performance control commands, and table data that constitutes tables used for various settings, judgments, and decisions. The RAM 102 in the game control microcomputer 100 is a temporary memory device that provides a work area and a stack for saving data used for game control. The RAM 102 should be a backup RAM that saves the contents of part or all of the memory area so that they can be recovered within a predetermined period even if the power supply to the pachinko game machine 1 is stopped. The RAM 102 is also called RWM (Read / Write Memory). The work area of ​​the RAM 102 includes a memory area capable of storing various data used for game control, such as counters, timers, buffers, and storage areas for various codes and numerical values. The CPU 103 of the game control microcomputer 100 can control the progress of the game in the pachinko game machine 1 by executing processing corresponding to the program stored in the ROM 101.

[0056] The random number circuit 104 in the game control microcomputer 100 counts updatable numerical data representing various random values ​​used to control the progress of the game. The random numbers used to control the progress of the game are also called game random numbers. Some or all of the game random numbers may be updated by hardware using a dedicated circuit, or by software such as a computer program executed by the CPU 103.

[0057] Figure 3 shows an example of a random number used for gameplay. The random number used for gameplay includes MR1-1 for determining special symbols, MR1-2 for winning symbols, MR1-3 which is the initial value for winning symbols, MR2-1 for regular winning symbols, MR2-2 which is the initial value for regular winning symbols, MR3-1 for regular symbol variation patterns, MR3-2 for selecting losing animations, MR3-3 for selecting variation pattern types, and MR3-4 for variation patterns.

[0058] The random number MR1-1 for determining special symbols is used to determine whether the display result of a special symbol will be a "jackpot" or a "minor win". The random number MR1-2 for winning symbols is used to select a confirmed special symbol from multiple special symbols, such as the jackpot symbol when the display result of a special symbol is a "jackpot", or the minor win symbol when the display result of a special symbol is a "minor win". The random number MR1-3, which is the initial value for winning symbols, is used to set the initial value of the random number MR1-2. The random number MR2-1 for normal symbol winning symbols is used to select a confirmed normal symbol from multiple normal symbols that will be displayed when the display result is a "normal symbol win" in the variable display of normal symbols. The random number MR2-2, which is the initial value for normal symbol winning symbols, is used to set the initial value of the random number MR2-1. Random number MR3-1 for normal symbol variation patterns is used to determine the variation pattern of the normal symbols to one of several pre-prepared patterns. Random number MR3-2 for selecting the losing animation is used to select whether or not the variable display of the animation symbols will result in a "reach" when the display result of the special symbols is a "lose". Random number MR3-3 for selecting the variation pattern type is used to select the variation pattern type of the special symbols. The variation pattern type of the special symbols is a group of special symbol variation patterns that have been pre-classified based on, for example, the animation type during the variable display of the animation symbols, and it is sufficient for the group to contain one or more variation patterns. Random number MR3-4 for variation patterns is used to select the variation pattern of the special symbols.

[0059] The CPU 103 reads and refers to various tables from the ROM 101 when making various judgments and decisions based on random values, such as numerical data indicating the value of a random number used for gameplay. Even when random values ​​are not used, the CPU may read and refer to the necessary tables from the ROM 101 to make various judgments, decisions, and settings.

[0060] The I / O 105 of the game control microcomputer 100 is configured to include an input port into which various signals are input and an output port into which various signals are output. The various signals input to the input port of the I / O 105 only need to include detection signals from various switches transmitted via the switch circuit 110. The various signals output from the output port of the I / O 105 only need to include signals that control the first special symbol display device 4A, the second special symbol display device 4B, the normal symbol display device 20, the first hold indicator 25A, the second hold indicator 25B, the normal symbol hold indicator 25C, etc., and solenoid drive signals that drive the normal electric mechanism solenoid 81, the big prize opening solenoid 82, the specific area solenoid 83, etc.

[0061] The main board 11, as part of the operation of controlling the progress of the game using the game control microcomputer 100, outputs performance control commands corresponding to the progress of the game, which can be transmitted to the performance control board 12. Performance control commands are commands that specify or notify the progress of the game, etc. Performance control commands output from the main board 11 are relayed by the relay board 15 and supplied to the performance control board 12. Performance control commands should include commands that specify various decision results on the main board 11, such as the display result of the special feature game, the type of win, the variation pattern, etc., commands that specify the status of the game, such as the start and end of the variable display, the opening status of the big prize slot, the occurrence of a win, the number of reserved memories, the game state, etc., and commands that specify the occurrence of an error, etc.

[0062] The performance control board 12 is a sub-control board independent of the main board 11, and has the function of receiving performance control commands and controlling performances based on the received performance control commands. The performances that can be controlled by the performance control board 12 are various performances that correspond to the progress of the game, such as the driving of the movable body 32, and also include various notifications such as error notifications and power outage recovery notifications. The performance control board 12 comprises a performance control CPU 120, a ROM 121, a RAM 122, a display control unit 123, a random number circuit 124, and an I / O 125.

[0063] The CPU 120 for performance control performs processing to control the execution of performances together with the display control unit 123 by executing a program stored in the ROM 121. This processing is for realizing the various functions of the performance control board 12 and includes determining which performance to execute. The CPU 120 for performance control uses various data stored in the ROM 121, such as data from various tables, and uses the RAM 122 as its main memory. The CPU 120 for performance control may also instruct the display control unit 123 to execute performances based on detection signals from the controller sensor unit 35A and the push sensor 35B. The detection signal here is a signal output when an operation by a player is detected, and any signal that appropriately indicates the content of the operation is acceptable.

[0064] The display control unit 123 includes a VDP (Video Display Processor), CGROM (Character Generator ROM), VRAM (Video RAM), etc., and controls the execution of effects mainly related to display based on the execution instructions for effects from the effect control CPU 120. The display control unit 123 supplies video signals corresponding to the effects to be executed to the image display device 5, thereby displaying the effects images on the screen of the image display device 5. The display control unit 123 also supplies sound specification signals to the sound control board 13 and lamp signals to the lamp control board 14. The sound specification signals specify the sound output from speakers 8L and 8R. The lamp signals specify the lighting and extinguishing modes of the game effect lamps 9. By supplying sound specification signals and lamp signals, it becomes possible to output sound from speakers 8L and 8R and to light up or extinguish the game effect lamps 9 in synchronization with the display of the effects images. The display control unit 123 may be capable of supplying signals to operate the movable body 32 to the motor or solenoid of the movable body 32, or to a driver circuit that drives the movable body 32. A separate driver board for driving the movable body 32 may be provided in addition to the performance control board 12.

[0065] The random number circuit 124 keeps updatable numerical data representing various random values ​​used to control the execution of various effects. The random numbers used to control the execution of effects are also called effect random numbers. The effect random numbers may be updated by software such as a computer program executed by the effect control CPU 120. When the effect control CPU 120 makes various judgments and decisions based on random values, such as numerical data representing the value of the effect random numbers, it reads and refers to various tables from the ROM 121. Even when random values ​​are not used, the effect control CPU 120 may read and refer to the necessary tables from the ROM 121 to make various judgments, decisions, and settings.

[0066] The I / O 125 comprises an input port for receiving, for example, performance control commands transmitted from the main board 11, and an output port for transmitting various signals. The input port of the I / O 125 only needs to include an input terminal for detection signals supplied from the controller sensor unit 35A and an input terminal for detection signals supplied from the push sensor 35B. The output port of the I / O 125 only needs to include an output terminal for video signals supplied to the image display device 5, an output terminal for sound specification signals supplied to the sound control board 13, and an output terminal for lamp signals supplied to the lamp control board 14.

[0067] The audio control board 13 is equipped with various circuits for driving speakers 8L and 8R, and drives speakers 8L and 8R based on sound specification signals from the display control unit 123, and outputs the sound specified by the sound specification signal from speakers 8L and 8R. The lamp control board 14 is equipped with various circuits for driving the game effect lamp 9, and drives the game effect lamp 9 based on lamp signals from the display control unit 123, and turns the game effect lamp 9 on or off in the manner specified by the lamp signals. In this way, the audio output from speakers 8L and 8R and the turning on and off of the game effect lamp 9 can be controlled based on signals from the display control unit 123. Note that the control of audio output and turning on and off of lamps, such as supplying sound specification signals and lamp signals, and the control of the movable body 32, such as supplying signals to operate the movable body 32, may be partially or entirely performed by the performance control CPU 120. Other boards besides the main board 11, such as the performance control board 12, the sound control board 13, and the lamp control board 14, are also called sub-boards. As shown in the example configuration in Figure 2, multiple sub-boards may be provided for each function, or, unlike the example configuration in Figure 2, one sub-board may be configured to have multiple functions.

[0068] The power supply board 17 can supply power from an AC power source such as AC100V from an external power source such as a commercial power supply to electrical components including the main board 11 and various control boards such as the performance control board 12. The power supply board 17 is equipped with, for example, a rectifier circuit for converting alternating current (AC) to direct current (DC), and a power supply circuit for converting a predetermined DC voltage to a specific DC voltage (for example, DC12V or DC5V). The pachinko game machine 1 can be switched on and off by operating the power switch 91. The switch circuit 110 of the main board 11 receives the reset signal, power off signal, and clear signal from the power supply board 17 and transmits them to the game control microcomputer 100. The reset signal is an operation stop signal for stopping the operation of control circuits such as the game control microcomputer 100, and can be output using any of the following: a power supply monitoring circuit, a watchdog timer built-in IC, or a system reset IC. The power-off signal is turned off when the predetermined power supply voltage used in the pachinko game machine 1 exceeds a predetermined value, and turned on when the period during which the predetermined power supply voltage remains below the predetermined value continues for a period longer than the power-off reference time. The clear signal is turned on in response to, for example, a press operation on the clear switch 92 provided on the power supply board 17.

[0069] (operation) Next, we will explain the operation (function) of the pachinko game machine 1.

[0070] (Main operations of the main board 11) First, let's explain the main operations of the main board 11. When power is supplied to the pachinko machine 1, the game control microcomputer 100 starts up, and the CPU 103 executes the main processing for game control.

[0071] Figure 4 is a flowchart of the main game control process P_MAIN executed by the CPU 103 on the main board 11. When the main game control process P_MAIN shown in Figure 4 is started, the CPU 103 executes the power supply start response process P_POWER_ON (step S1), followed by the RWM check process P_RWM_CHK (step S2). The power supply start response process P_POWER_ON in step S1 can perform initial settings of the game control microcomputer 100 in response to the start of power supply in the pachinko game machine 1. The initial settings of the game control microcomputer 100 only need to include initialization of output ports, setting of interrupt vectors, setting of built-in device registers, and setting of specific registers. The RWM check process P_RWM_CHK in step S2 includes a checksum calculation process, and the checksum data obtained as a result of the process is compared with the data stored in the checksum buffer. If the two data match, it is determined that the contents stored in RAM 102 are normal.

[0072] Next, it is determined whether or not predetermined recovery conditions have been met (step S3). Recovery conditions can be met if the clear signal corresponding to the operation of the clear switch 92 is in the off state, there is normal stored data in the checksum buffer, and the stored contents in RAM 102, which serves as backup RAM, are normal. When the power of the pachinko game machine 1 is turned on, for example, if the clear switch 92 provided on the power supply board 17 is pressed, an ON clear signal is input to the game control microcomputer 100. If such an ON clear signal is input, it is sufficient to determine in step S3 that the recovery conditions have not been met. The checksum buffer stores the checksum data calculated in the checksum calculation process when the backup determination time was measured by the backup monitoring timer during the previous power outage. If the timing value of the backup monitoring timer does not match a specific value corresponding to the backup determination time, it is sufficient to determine in step S3 that the recovery conditions have not been met. The backup data can be any stored data in the game work area of ​​RAM 102, which serves as backup RAM for game control. In step S3, based on the results of the RWM check process P_RWM_CHK in step S2, which confirmed or inspected whether backup data exists and whether there are any data errors, it is necessary to determine whether the recovery conditions can be met.

[0073] If the recovery conditions are met (Step S3; Yes), the backup setting process P_BACKUP_SET is executed (Step S4). The backup setting process P_BACKUP_SET uses the backup command transmission table to enable the transmission of corresponding performance control commands from the main board 11 to the performance control board 12 during backup. The backup setting process P_BACKUP_SET also enables initialization by clearing the process code, timer, counter, and flags specified by the backup setting table.

[0074] If the recovery conditions are not met (Step S3; No), the initialization setting process P_INIT_SET is executed (Step S5). The initialization setting process P_INIT_SET makes it possible to transfer clear data to the game work area, which is the working area in RAM 102. This initializes the game work area in RAM 102. The initialization setting process P_INIT_SET then uses the initialization command transmission table to make it possible to send the corresponding performance control command from the main board 11 to the performance control board 12 during initialization. In addition, the initialization setting process P_INIT_SET makes the buffers, timers, pointers, and counters specified by the initialization setting table initialized by clearing them.

[0075] Subsequently, the control start setting process P_STACON is executed (step S6). The control start setting process P_STACON may include a wait process. The wait process ensures that sub-boards such as the performance control board 12 can be reliably started up by executing a loop process until a set waiting time has elapsed. The control start setting process P_STACON may also include a specific count command transmission process or a chip individual number information command transmission process. The specific count command transmission process enables the transmission of a performance control command specifying the count value of a specific count counter from the main board 11 to the performance control board 12 when the power is turned on. The specific count counter is located at a predetermined address in RAM 102 and only needs to be able to count the remaining number of executions until the number of executions of the variable display reaches a specific number corresponding to the time reduction condition. The chip individual number information command transmission process enables the transmission of a performance control command specifying the stored value of the chip individual number register from the main board 11 to the performance control board 12. The chip-specific number register can be included in the built-in registers of the game control microcomputer 100, and it is sufficient that it can store a different value assigned to each chip as the chip-specific number.

[0076] The control start setting process P_STACON may include startup-time out-of-area processing. The startup-time out-of-area processing is executed when the pachinko game machine 1 starts up due to the start of power supply, by reading a program stored in the non-game program area of ​​ROM 101. The startup-time out-of-area processing may be, for example, a performance display RWM initial value setting process. The performance display RWM initial value setting process makes it possible to set an initial value for initial display using the 7-segment LEDs that constitute the performance display monitor. The performance display monitor may be mounted on, for example, the main board 11 and may be capable of displaying information related to the setting value and information related to the base. The setting value can be changed to one of several levels, such as 6 levels, when the settings of the pachinko game machine 1 are in a setting change state in which the settings can be changed, and it is possible to set the probability that the display result of the special symbols will be a "jackpot". The base is calculated by dividing the number of prize balls dispensed when a game ball passes through each prize slot (such as the starting prize slot, general prize slot, and big prize slot) by the number of game balls launched into the game area.

[0077] Following the control start setting process P_STACON in step S6, the timer interrupt counter is set (step S7). In step S7, the PTC counter output value is set so that a periodic timer interrupt occurs at predetermined intervals, for example, every 4 [ms (milliseconds)]. After that, the main process P_MAIN for game control enters a loop. In this loop, interrupts are disabled (step S8), the random number update process P_TFINIT for determining the initial value is executed (step S9), the loop-out-of-area processing P_REGOUT is executed (step S10), interrupts are enabled (step S11), and the process returns to step S8. Then, when the interrupt is enabled, each time an interrupt request signal is input from the PTC to the CPU 103, the CPU 103 becomes capable of executing the timer interrupt process. As a result, the CPU 103 can execute the timer interrupt process every time a predetermined interval has elapsed, for example, every 4 [ms].

[0078] Figure 5 is a flowchart showing an example of a timer interrupt process P_PCT for game control. In the timer interrupt process P_PCT shown in Figure 5, the power off process P_POWER_OFF is executed (step S51). Next, it is determined whether the fraudulent activity monitoring flag is "0" or not (step S52). The fraudulent activity monitoring flag is set to "1", which corresponds to the ON state, when magnetism is detected by the magnetic sensor or when radio waves are detected by the frame radio wave sensor. In all other cases, the fraudulent activity monitoring flag is set to "0", which corresponds to the OFF state.

[0079] If the fraud monitoring flag is "1" (step S52; No), the game stop process P_GAME_STOP is executed (step S53). The game stop process P_GAME_STOP only needs to initialize the output port and turn off the output of the connection confirmation signal. The connection confirmation signal is transmitted from the main board 11 to the payout control board, and if it is in the off state, the execution of the payout process on the payout control board is stopped.

[0080] If the fraud monitoring flag is "0" (Step S52; Yes), the switch process P_SW is executed (Step S54), the switch error notification process P_CON_CHK is executed (Step S55), the random number update process P_RANDOM is executed (Step S56), and the random number update process for initial value determination P_TFINIT is executed (Step S57). In addition, the special symbol process process P_TPROC is executed (Step S58), the normal symbol process process P_FPROC is executed (Step S59), the information output process P_JYOUHOU is executed (Step S60), the prize ball process P_PAY is executed (Step S61), and the display process P_HYOUZI is executed (Step S62). Furthermore, other timer interrupt handling processes are executed (Step S63). After that, the timer interrupt process P_PCT is terminated after the interrupt enable is set (Step S64).

[0081] Step S51, the power-off process P_POWER_OFF, determines the power confirmation signal transmitted from the power supply board 17 and enables the execution of checksum calculation processing when the power is off. Step S54, the switch process P_SW, determines the state of the input port and enables the updating of the switch-on buffer, etc. Step S55, the switch error notification process P_CON_CHK, enables the updating of the count value of the sensor-on counter specified by, for example, the switch error notification judgment table, and enables the execution of error notification display when the count value reaches the sensor abnormal error judgment value. Step S56, the random number update process P_RANDOM, enables the software to update the software random numbers among the random numbers used for the game. Step S57, the random number update process P_TFINIT for determining the initial value, enables the software to update the random numbers used as the initial value among the random numbers used for the game.

[0082] Step S58, the special symbol process processing P_TPROC, includes processing related to the variable display of special symbols and the game state, such as managing the execution and holding of special symbol games, controlling the jackpot game state and the minor jackpot game state, and controlling the game state. Step S59, the normal symbol process processing P_FPROC, includes processing related to the variable display of normal symbols and the state control of the second start prize slot, such as managing the execution and holding of normal symbol games based on detection signals from the gate switch 21, and controlling the opening and closing of the variable prize ball device 6B based on "normal symbol win". Step S60, the information output processing P_JYOUHOU, sets the information output signal. The information output signal is a signal corresponding to information supplied to a hall management computer installed outside the pachinko game machine 1, such as jackpot information, start information, and probability variation information. Jackpot information indicates the number of times a jackpot has occurred. Start information indicates the number of start prizes. Probability variation information indicates the number of times the game entered a probability variation state. Step S61's prize ball processing P_PAY includes prize ball command output counter increment processing and prize ball control processing. The prize ball command output counter increment processing uses the prize ball count table to determine if the switch is ON, and when ON is detected, it updates the prize ball command output counter and the prize information output counter. The prize ball control processing selects processing corresponding to the prize ball process code and controls the system to dispense prize balls based on the detection of game balls. Step S62's display processing P_HYOUZI sets the display for the first reserve indicator 25A, the second reserve indicator 25B, the general reserve indicator 25C, and various other status indicator lights.

[0083] Figure 6 is a flowchart showing an example of a process that can be executed in step S58 shown in Figure 5 as the special pattern process P_TPROC. In the special pattern process P_TPROC, the CPU 103 sets the first start prize response flag (step S101). The first start prize response flag setting is done by executing a logical operation instruction, etc., to reflect the state of the first start port switch 22A included in the switch-on buffer in the flag register of the CPU 103. At this time, if the zero flag in the flag register is on, it indicates that the first start prize response flag is off. Conversely, if the zero flag is off, it indicates that the first start prize response flag is on. Next, the first start port prize table is set by a transfer instruction to set the table pointer (step S102). After that, it is determined whether or not the first start prize response flag is on (step S103). If the flag for the first start prize is on (step S103; Yes), the start port switch pass-through process P_TZU_ON is executed (step S104).

[0084] If the first start-up prize flag is off in step S103 (step S103; No), or after the start-up switch pass-through process P_TZU_ON in step S104, the second start-up prize flag is set (step S105). The second start-up prize flag is set by reflecting the state of the second start-up switch 22B contained in the switch-on buffer in the flag register of the CPU 103 through the execution of a logical operation instruction, etc. At this time, if the zero flag in the flag register is on, it indicates that the second start-up prize flag is off. Conversely, if the zero flag is off, it indicates that the second start-up prize flag is on. Next, the second start-up prize table is set by a transfer instruction to set the table pointer (step S106). After that, it is determined whether or not the second start-up prize flag is on (step S107). If the flag for the second start prize is on (step S107; Yes), the start port switch pass-through process P_TZU_ON is executed (step S108).

[0085] In step 104, the start gate switch pass-through process P_TZU_ON uses the first start gate prize table set in step S102 to update the first reserve memory count and the total reserve memory count by 1 if the first reserve memory count is less than the upper limit. It then extracts the random numbers MR1-1 for special symbol determination, MR3-2 for losing animation selection, MR3-3 for variation pattern type selection, and MR3-4 for variation pattern, stores them in their respective random number buffers, and then transfers them to the first special symbol reserve buffer. Additionally, the first reserve memory information specification command transmission table is used to enable transmission of the first reserve memory information specification command, which specifies the first reserve memory count, from the main board 11 to the animation control board 12. Finally, a value indicating "1" as the start gate prize specification value is stored in the start gate prize buffer.

[0086] In step S108, the start gate switch pass-through process P_TZU_ON uses the second start gate prize table set in step S106 to update the second reserve memory count and the total reserve memory count by 1 if the second reserve memory count is less than the upper limit. It then extracts the random numbers MR1-1 for special symbol determination, MR3-2 for losing animation selection, MR3-3 for variation pattern type selection, and MR3-4 for variation pattern, stores them in their respective random number buffers, and then transfers them to the second special symbol reserve buffer. Additionally, the second reserve memory information specification command transmission table is used to enable the transmission of a second reserve memory information specification command, which specifies the second reserve memory count, from the main board 11 to the animation control board 12. Finally, a value indicating "2" as the start gate prize specification value is stored in the start gate prize buffer.

[0087] In steps S104 and S108, a common start gate switch pass-through process P_TZU_ON can be executed. However, the start gate switch pass-through process P_TZU_ON in step S104 uses the first start gate prize table set in step S102, while the start gate switch pass-through process P_TZU_ON in step S108 uses the second start gate prize table set in step S106. In this way, the common start gate switch pass-through process P_TZU_ON is executed using different start gate prize tables. Therefore, different data settings and controls are possible through common processing depending on whether the game ball enters the first start gate prize entry or the second start gate prize entry. Note that the start gate switch pass-through process P_TZU_ON may include prize entry animation processing using extracted random numbers for gameplay.

[0088] If the second start prize response flag is off in step S107 (step S107; No), or after the start gate switch pass processing P_TZU_ON in step S108, the special symbol process processing jump table is set by a transfer command that sets a pointer (step S109). The special symbol process processing jump table is an address management table that makes the processing corresponding to the read value of the special symbol process code selectable and executable. The special symbol process code can be updated to one of 00[H] to 0B[H] in accordance with the progress of game control in the pachinko game machine 1, and is also called the special symbol process code. Here, [H] indicates a hexadecimal number. Note that [B] may also indicate a binary number.

[0089] Following step S109, a transfer command to read stored data loads the special symbol process code (step S110). Next, by executing the 2-byte data selection process P_ABXEXEC (step S111), the address of the process selected in accordance with the special symbol process code is obtained. The address obtained at this time is set as a pointer. After this, by executing the process pointed to by the pointer using a subroutine call command (step S112), the process selected in accordance with the special symbol process code becomes executable. When the selected process finishes and returns to the special symbol process process P_TPROC by a return command, the special symbol process process P_TPROC also finishes, and returns to the timer interrupt process P_PCT for game control by a return command.

[0090] Figure 7 shows an example configuration TT01 of the special symbol process processing jump table used in the special symbol process processing P_TPROC. The special symbol process processing jump table is configured to include table data that can be set in an internal register of the CPU 103, which is used as a pointer, to the address of the processing selected in accordance with the special symbol process code. The special symbol process processing jump table in configuration example TT01 includes the special symbol normal processing P_TNORMAL when the special symbol process code is 00[H], the special symbol variation processing P_TSTART when the special symbol process code is 01[H], the special symbol stop processing P_TSTOP when the special symbol process code is 02[H], the small win opening pre-processing P_TLFAN when the special symbol process code is 03[H], the small win opening in-processing P_TLOPEN when the special symbol process code is 04[H], and the small win opening post-processing P_TLCLSF when the special symbol process code is 05[H]. The table data includes address values ​​that can be set to pointers for the following processes: P_TLOUT, which is the small win ball dispensing waiting process when the alternate symbol process code is 06[H]; P_TLEND, which is the small win termination process when the special symbol process code is 07[H]; P_TINT, which is the pre-opening process for the big prize slot when the special symbol process code is 08[H]; P_TOPEN, which is the in-opening process for the big prize slot when the special symbol process code is 09[H]; P_TCLSF, which is the post-opening process for the big prize slot when the special symbol process code is 0A[H]; and P_TEND, which is the big win termination process when the special symbol process code is 0B[H].

[0091] The special symbol normal processing P_TNORMAL enables the following: determining whether or not to start the special symbol game based on the presence or absence of stored hold information, determining the special symbol display result using the random number MR1-1 for special symbol determination, determining the confirmed special symbol to be stopped in the variable display of special symbols, and determining the variation pattern of the special symbol. The special symbol display result includes "jackpot," "minor win," "miss," etc. If it is determined to be a "jackpot," it is decided to control the game to a jackpot game state, which is an advantageous state for the player. Also, if the special symbol display result is a "jackpot," it is determined which of several types of jackpot game states, each with a different degree of advantage for the player, will be controlled to correspond to the jackpot symbol that becomes the confirmed special symbol. Therefore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can determine whether or not to control the game to an advantageous state for the player, and can decide which of several types of advantageous states, each with a different degree of advantage for the player, to control the game to. Furthermore, by executing the special symbol normal processing P_TNORMAL, the CPU 103 can decide on one of several types of variation patterns.

[0092] The special symbol variation process P_TSTART measures the elapsed time since the special symbol started to vary in the first special symbol display device 4A and the second special symbol display device 4B, enabling a determination of whether the special symbol variation time corresponding to the variation pattern has elapsed. The special symbol stop process P_TSTOP measures the elapsed time since the special symbol stopped varying in the first special symbol display device 4A and the second special symbol display device 4B, enabling a determination of whether the symbol stop time has elapsed. The symbol stop time only needs to be set as the time for displaying the special symbol as stopped when the special symbol variation time is determined to have elapsed in the special symbol variation process P_TSTART. When the symbol stop time has elapsed, the special symbol process code is updated and various settings are made in accordance with the special symbol display result. For example, it would be sufficient if the special symbol process code could be updated to 08[H] when the special symbol display result is "Big Win", to 03[H] when the special symbol display result is "Small Win", and to 00[H] when the special symbol process code is "Miss".

[0093] The pre-minor win opening process P_TLFAN, the in-minor win opening process P_TLOPEN, the post-minor win opening process P_TLCLSF, the minor win ball discharge waiting process P_TLOUT, and the minor win termination process P_TLEND are processes to control the progress of the game in the minor win state. The pre-major win opening process P_TINT, the in-major win opening process P_TOPEN, the post-major win opening process P_TCLSF, and the jackpot termination process P_TEND are processes to control the progress of the game in the jackpot state.

[0094] (Main operations of the performance control board 12) Next, the main operations of the performance control board 12 will be explained. When the performance control board 12 receives power voltage from the power supply board 17 or the like, the performance control CPU 120 starts up and executes the main performance control processing.

[0095] Figure 8 is a flowchart of the main processing S_MAIN for performance control executed by the performance control CPU 120 on the performance control board 12. When the main processing S_MAIN for performance control shown in Figure 8 is started, the performance control CPU 120 executes the performance control initialization process S_INIT (step S71). The performance control initialization process S_INIT includes clearing the RAM 122, setting various initial values, and setting registers for the timer circuit mounted on the performance control board 12. Next, the initial operation control process S_SYOKI is executed (step S72). The initial operation control process S_SYOKI enables control of the initial operation of the movable body 32, such as control to drive the movable body 32 back to its initial position and control to perform predetermined operation checks. After that, it is determined whether the timer interrupt flag is on or off (step S73). The timer interrupt flag is set to the on state every time a predetermined time has elapsed, for example, 2 [ms (milliseconds)], based on the register settings for the timer circuit. The timer interrupt flag is set to off (step S73; No), and step S73 is repeated while waiting.

[0096] If the timer interrupt flag is turned ON (step S73; Yes), the timer interrupt flag is cleared and turned OFF (step S74), the command analysis process S_COMMAND is executed (step S75), the performance control process S_CPROC is executed (step S76), the random number update process for performances S_RANDOM is executed (step S77), and the output process for performances S_OUT is executed (step S78). Then, other timer interrupt handling processes are executed (step S79), and the process returns to step S73.

[0097] The command analysis process S_COMMAND in step S75 enables the reading of the production control command stored in the buffer for receiving the production control command and the setting and control corresponding to the read production control command. By executing the command analysis process S_COMMAND, the production control CPU 120 can update storage data indicating the state of the flag, stored data in the register, and any other storage data in the working area of the RAM 122 corresponding to the production control command transmitted from the main board 11. The production control process S_CPROC in step S76 enables the control of the execution of various productions using various production devices, including, for example, the display of production images on the screen of the image display device 5, the audio output from the speakers 8L and 8R, the lighting or extinguishing of the decorative light emitters such as the game effect lamp 9 and the decorative LED, and the drive control of the movable body 32. The control content of the production using various production devices may be determined, decided, set, etc. based on the production control command transmitted from the main board 11, the execution result of the process by the production control CPU 120, etc. The production random number update process S_RANDOM in step S77 enables at least a part of the production random numbers used on the side of the production control board 12 to be updated by executing a program as software.

[0098] FIG. 9(A) is a flowchart showing an example of the process executable in step S76 shown in FIG. 8 as the production control process S_CPROC. In the production control process, the production control CPU 120 executes the pre-reading production setting process S_SAKI_SET (step S151). The pre-reading production setting process S_SAKI_SET enables, for example, the determination, decision, setting, etc. regarding the execution of the pre-reading preview production based on the production control command at the time of starting winning transmitted from the main board 11. Also, the pre-reading production setting process S_SAKI_SET enables the update of the hold display based on the number of hold memories specified from the production control command.

[0099] In step S151, after the pre-read performance setting process S_SAKI_SET, the performance control process jump table is set by a transfer command that sets a pointer (step S152). The performance control process jump table is an address management table that makes the process corresponding to the read value of the performance control process code selectable and executable. The performance control process code can be updated to one of 00[H] to 0A[H] in accordance with the progress of performance control in the pachinko game machine 1, and is also called the performance process code. The performance control process code is loaded by a transfer command to read stored data (step S153). The address of the process to be selected corresponding to the performance control process code obtained in this way is set in the performance control pointer (step S154). Therefore, by executing the process pointed to by the performance control pointer (step S115), the process selected corresponding to the performance control process code becomes executable.

[0100] Figure 9(B) shows an example configuration TT02 of the performance control process jump table used in the performance control process S_CPROC. The performance control process jump table is composed of table data that can be set in a register used as a performance control pointer, which contains the address of the process selected in accordance with the performance control process code. The jump table for the performance control process in configuration example TT02 includes table data that allows setting address values ​​corresponding to the following processes in the performance control pointer: waiting for a variation pattern command when the performance control process code is 00[H], starting the variation of the performance symbols when the performance control process code is 01[H], processing while the performance symbols are changing when the performance control process code is 02[H], stopping the variation of the performance symbols when the performance control process code is 03[H], displaying a minor win when the performance control process code is 04[H], processing while the minor win is open when the performance control process code is 05[H], the ending performance of the minor win when the performance control process code is 06[H], displaying a big win when the performance control process code is 07[H], processing during a round when the performance control process code is 08[H], processing after a round when the performance control process code is 09[H], and ending the performance of the big win when the performance control process code is 0A[H].

[0101] The variable pattern command reception waiting process makes it possible to determine whether or not a variable pattern specification command transmitted from the game control microcomputer 100 on the main board 11 has been received. If it is determined that a variable pattern specification command has been received, the performance control process code is updated to 01[H], which corresponds to the performance symbol variation start process. If it is determined that no variable pattern specification command has been received, the demo display becomes controllable. The performance symbol variation start process makes it possible to start the variation-time performance corresponding to the special feature game. For example, in response to a variable pattern command transmitted from the main board 11, it makes it possible to select the performance pattern to be used to control the variation-time performance and to start updating the performance process timer that measures the performance execution time. The performance symbol variation in progress process makes it possible to control the switching timing of each performance element that makes up the performance pattern, and makes it possible to determine whether or not the performance execution time has elapsed based on the timing value of the performance process timer. If it is determined that the performance execution time has elapsed, the performance control process code is updated to 03[H], which corresponds to the performance symbol variation stop process. The symbol variation stop process enables termination control of the variation-time effect and display control of the effect result corresponding to the confirmed special symbol, based on the fulfillment of termination conditions for the variation-time effect, such as the expiration of the effect execution time or the receipt of the effect symbol confirmation command. At this time, the effect control process code is updated and various settings are made in accordance with the display result of the variable display. For example, if the display result of the variable display is "Big Win", the effect control process code can be updated to 07[H], if the display result of the variable display is "Small Win", the effect control process code can be updated to 04[H], and if the display result of the variable display is "Miss", the effect control process code can be updated to 00[H].

[0102] The minor win display process, minor win opening process, and minor win ending animation process are processes that control the progress of animations corresponding to the minor win game state. The big win display process, round process, round post-process, and big win ending animation process are processes that control the progress of animations corresponding to the big win game state.

[0103] (Examples of basic explanations, etc.) The pachinko game machine 1 is not limited to the configuration, functions, processes, and operations described in the basic description and other descriptions, and is subject to various modifications and applications. For example, the pachinko game machine 1 does not have to possess all the technical features shown in the embodiments, and may have some of the configurations described in the embodiments so as to solve at least one problem in the prior art. When a subordinate concept is described in an embodiment, a higher-level invention using related or similar matters, or a higher-level invention using common properties, is included in the present invention and may have some of the structures and characteristics described in the embodiments so as to solve at least one problem in the prior art.

[0104] The pachinko game machine 1 may be a payout type game machine that dispenses a predetermined number of game media as prizes based on the occurrence of winnings, or it may be a sealed type game machine that encloses game media and awards points when winnings occur.

[0105] During the variable display of the special symbol, only one type of symbol may be displayed, such as a "-" symbol, and the variable display may be configured to repeatedly show and unshow this symbol. During the variable display, one type of symbol may be displayed, and this symbol may not be displayed when the variable display stops. For example, the display result may be that a "-" symbol is not displayed, resulting in a non-display state where no special symbol is shown.

[0106] Pachinko game machine 1 may have a configuration in which the probability of winning a jackpot and the payout rate change in response to multiple setting values. For example, in the special symbol normal processing of the special symbol processing, the probability of winning a jackpot and the payout rate may be changed by using different jackpot determination values ​​for each set setting value. As a specific example, the setting value can be set to one of six levels from 1 to 6, with 6 having the highest probability of winning a jackpot, and the probability of winning a jackpot decreasing as the value decreases in the order of 6, 5, 4, 3, 2, and 1. In this case, if the setting value is set to 6, it is the most advantageous for the player, and the advantage decreases in stages as the value decreases in the order of 6, 5, 4, 3, 2, and 1. If the probability of winning a jackpot changes according to the setting value, the payout rate may also change according to the setting value. The probability of winning a jackpot may remain constant regardless of the setting value, while the number of rounds in the jackpot game state may change according to the setting value. The pachinko game machine 1 only needs to be configured to allow the player to set one of several setting values ​​that offer different levels of advantage. The setting value set in the pachinko game machine 1 may be notified by a setting value specification command being sent from the main board 11 to the performance control board 12. During the execution of the variable display, a setting suggestion performance that hints at the setting value in the pachinko game machine 1 may be executed at a predetermined rate. The hint regarding the setting value of the pachinko game machine 1 is not limited to hinting at the setting value of the pachinko game machine 1, but may also, for example, hint whether or not the setting value of the pachinko game machine 1 has been changed. The setting suggestion performance may also be able to hint at the probability of winning a jackpot through an arbitrary performance, as well as provide hints regarding the setting value of the pachinko game machine 1.

[0107] In lieu of, or in conjunction with, some or all of the suggestions regarding the control of the jackpot game state, suggestions regarding the control of a state that is advantageous to the player but different from the jackpot game state may be provided. For example, suggestions regarding a probability variation state that is controlled after the end of the jackpot game state may be provided. In addition, as an advantageous state, suggestions may be provided regarding a state in which any game value that is advantageous to the player is granted, depending on whether or not it is controlled.

[0108] The invention relating to gaming machines is not limited to pachinko gaming machines 1, but can also be applied to slot machines as appropriate. A slot machine is capable of running a game in which a predetermined number of tokens are inserted, a predetermined number of tokens are set, multiple types of symbols are rotated in response to the operation of a lever by the player, and when the symbols are stopped in response to the operation of a stop button by the player, a predetermined number of tokens are paid out to the player if the combination of stopped symbols matches a specific combination of symbols. In a slot machine, an advantageous state for the player only needs to include one or more of the so-called bonuses, such as a big bonus, regular bonus, RT, AT, ART, and CZ.

[0109] Programs and data for realizing various controls, including the progress of the game and the execution of effects, may be distributed and provided to the computer device included in the game machine, such as the pachinko game machine 1, via a removable recording medium, or they may be distributed and provided by being pre-installed on the storage device of the computer device. Alternatively, they may be provided with a communication processing unit that can connect to external devices on a network via a communication line, and distribution and provision may be possible by downloading programs and data from such external devices. The execution methods for games and effects may also be such that they can be executed by attaching a removable recording medium, or by temporarily storing programs and data downloaded via a communication line in internal memory, or by directly using hardware resources on external devices on a network connected via a communication line, or by exchanging data with other computer devices via a network.

[0110] When comparing various percentages, such as the percentage of processing or data decisions, or the percentage of performance executions, expressions like "high," "low," or "different" may include cases where one of them is at a percentage of "0%" or "100%." ​​For example, one of the decision results or executions may include cases where there is no decision or execution at a percentage of "0%", or cases where there is always a decision or execution at a percentage of "100%".

[0111] (Explanation of feature section 01AK) Figure 10-1 shows an example configuration of the game control microcomputer 100 with respect to feature unit 01AK. The game control microcomputer 100 of feature unit 01AK is configured with ROM 101, RAM 102, CPU 103, as well as an external bus interface 131, a clock circuit 132, a unique information storage circuit 133, a reset controller 134, an interrupt controller 135, a timer circuit 136, an address decode circuit 137, a free-run counter 138, and a serial communication circuit 139. The random number circuit 104 shown in Figure 2 is configured to include a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The I / O 105 shown in Figure 2 is configured to include a PIP (Parallel Input Port) 105A and a POP (Parallel Output Port) 105B.

[0112] The external bus interface 131 is a bus interface that has the function of interface between the external bus and the internal bus of the chip constituting the game control microcomputer 100, as well as functions for controlling the direction of the address bus, data bus, and various control signals. For example, the external bus interface 131 is connected to an external memory or external input / output device attached to the game control microcomputer 100, and it is sufficient that it is able to send and receive address signals, data signals, and various control signals to and from these external devices. The external bus interface 131 may also include an internal resource access control circuit that controls access to the internal data of the game control microcomputer 100 from external devices.

[0113] The clock circuit 132 can generate an internal system clock SCLK using an oscillation signal input to the external control clock terminal EXC. The external control clock terminal EXC may receive a control clock generated by a control clock generation circuit provided in the game control microcomputer 100. The internal system clock SCLK generated by the clock circuit 132 can be supplied to various circuits in the game control microcomputer 100, such as the CPU 103, the 16-bit random number circuit 104A, and the 8-bit random number circuit 104B. The internal system clock SCLK can also be output to the outside of the game control microcomputer 100 from the system clock output terminal CLKO. Alternatively, the output of the internal system clock SCLK to the outside of the game control microcomputer 100 may be restricted to make it difficult to determine the operating state of the game control microcomputer 100 from the outside.

[0114] The unique information storage circuit 133 can store multiple types of unique information, such as internal information of the game control microcomputer 100. For example, the unique information storage circuit 133 only needs to be able to store ROM codes, chip individual numbers, and ID numbers as unique information that differs for each chip of the game control microcomputer 100. The ROM code is numerical data that can be generated from stored data in a predetermined area of ​​the ROM 101. The chip individual number and ID number are numbers assigned to the game control microcomputer 100 during manufacturing, and represent different numerical values ​​for each chip. The chip individual number can be read by a user program such as a game program, while the ID number can be set so that it cannot be read by a user program. The unique information storage circuit 133 may be included in a predetermined area of ​​the ROM 101, or it may be included in the built-in registers of the game control microcomputer 100.

[0115] The reset controller 134 can control various resets that occur inside or outside the game control microcomputer 100. The resets controllable by the reset controller 134 include system resets and user resets. A system reset occurs when the input signal to the external system reset terminal XSRST is low for a certain period of time. A user reset occurs due to predetermined factors, such as the occurrence of a timeout signal from the watchdog timer 134A or the occurrence of an Inappropriate Attack (IAT) event. The reset controller 134 includes the watchdog timer 134A. The watchdog timer 134A can be set to a timer value corresponding to the monitoring time, and is capable of counting down to periodically decrement the timer value by 1. When the timer value becomes "0" and a timeout occurs, it can output a timeout signal to reset and restart the game control microcomputer 100. As a result, the watchdog timer 134A can measure the monitoring time and reset the game control microcomputer 100 when it is measured that the monitoring time has elapsed. The watchdog timer 134A can be configured to enable or disable its operation according to, for example, a game program.

[0116] The interrupt controller 135 can control various interrupt requests that occur inside or outside the game control microcomputer 100. The interrupts that can be controlled by the interrupt controller 135 include non-maskable interrupts NMI and maskable interrupts INT. The non-maskable interrupt NMI is an interrupt that is accepted unconditionally even when the CPU 103 is in an interrupt-disabled state, and it occurs when the input signal of the external non-maskable interrupt terminal XNMI (shared with input port PI6) is at a low level for a certain period of time. The maskable interrupt INT is an interrupt whose acceptance can be permitted or prohibited by a setting instruction of the CPU 103, and it is possible to execute multiple interrupts by setting priority. The causes of the maskable interrupt INT include several types of interrupt causes, such as the input signal of the external maskable interrupt terminal XINT (shared with input port PI5) being low level for a certain period of time, a timeout occurring in the timer circuit 136, and numerical data representing a random value being stored in the random value register by the 16-bit random number circuit 104A or the 8-bit random number circuit 104B. It is sufficient if some or all of these causes can be set.

[0117] The timer circuit 136 is configured to include a Programmable Timer Counter (PTC) corresponding to three channels PTC0 to PTC2, enabling real-time interrupt generation and time measurement. Each channel PTC0 to PTC2 of the timer circuit 136 only needs to be able to update the timer value in response to changes in the count clock signal, such as the falling edge timing when the clock signal changes from a high level to a low level, using a count clock generated based on the internal system clock SCLK.

[0118] The address decoding circuit 137 can decode various signals acquired from each functional block inside the game control microcomputer 100 and can output a chip select signal, which is a decoding signal for external devices. The chip select signal selectively enables the operation of the internal circuits of the game control microcomputer 100 or external peripheral devices, allowing access from the CPU 103. The output terminals that the address decoding circuit 137 can use are multi-function terminals that can selectively output the parallel output signal from POP 105B, the serial transmission signal from serial communication circuit 139, the clock output signal from clock circuit 132, and the chip select signal generated by the address decoding circuit 137.

[0119] The free-run counter 138 is configured with counter circuits corresponding to four channels FRC0 to FRC3, and can update its count value independently of the operation of the CPU 103. Each channel FRC0 to FRC3 of the free-run counter 138 can be started with an independent update clock, and its operation can be stopped or changed according to the game program, for example. The count value from the free-run counter 138 can be stored in a hard latch register in response to a latch signal transmitted from the input terminal, which is the latch signal input terminal of the PIP 105A. The count value stored in the hard latch register can be read by the CPU 103 and used when executing the game program, etc.

[0120] The serial communication circuit 139 is configured to include a serial communication unit corresponding to three channels SCU0, SCU1, and STU2, enabling communication with external devices via a serial communication method. Each channel SCU0, SCU1, and STU2 of the serial communication circuit 139 can process communication data in, for example, full-duplex, asynchronous, and standard NRZ (Non-Return to Zero) format. Channels SCU0 and SCU1 of the serial communication circuit 139 are included in a first channel transmit / receive circuit that can send and receive serial data bidirectionally to and from an external circuit. Channel STU2 of the serial communication circuit 139 is included in a second channel transmit circuit that can only transmit serial data in one direction to and from an external circuit. For example, channel SCU0 of the serial communication circuit 139 is used for data communication with the payout control board. Channel SCU1 of the serial communication circuit 139 is used for data communication with the performance control board 12. Channel STU2 of the serial communication circuit 139 may be used for data communication with the performance control board 12 instead of channel SCU1.

[0121] The 16-bit random number circuit 104A is composed of random number generation units corresponding to four channels RL0 to RL3, each operating independently to generate random numbers from "0" to "65535" using numerical data representing 16-bit pseudo-random numbers. The maximum value of the random numbers generated by each channel RL0 to RL3 in the 16-bit random number circuit 104A can be set to any value within the range of "256" to "65535". Setting such a maximum value allows for an initial setting to select the random number activation method so that the update of the numerical data representing the random number value begins. Alternatively, each channel RL0 to RL3 in the 16-bit random number circuit 104A can be initially set to activate automatically when the operating mode of the game control microcomputer 100 transitions from security mode to user mode. The 16-bit random number circuit 104A can update the random number MR1-1 for special symbol determination via channel RL0, and the random number MR3-2 for selecting the losing animation via channel RL2.

[0122] The 8-bit random number circuit 104B is composed of random number generation units corresponding to four channels RS0 to RS3, each operating independently to generate random values ​​from "0" to "255" using numerical data representing 8-bit pseudo-random numbers. The maximum value of the random numbers generated by each channel RS0 to RS3 in the 8-bit random number circuit 104B can be set to any value within the range of "16" to "255". Setting such a maximum value allows for an initial setting to select the random number activation method so that the updating of the numerical data representing the random value begins. Alternatively, each channel RS0 to RS3 in the 8-bit random number circuit 104B may be set to automatically activate when the operating mode of the game control microcomputer 100 transitions from security mode to user mode, so that the random number activation method can be selected. The 8-bit random number circuit 104B can update the random number MR3-3 for selecting the variation pattern type via channel RS1, the random number MR3-4 for the variation pattern via channel RS2, and the random number MR3-1 for the normal pattern variation pattern via channel RS3.

[0123] The PIP105A incorporates, for example, an 8-bit wide input-only port, allowing various signals to be input from outside the game control microcomputer 100. The PIP105A can use input terminals corresponding to input ports PI0 to PI7. Input port PI5 uses a function-sharing terminal that can be used in conjunction with the external maskable interrupt terminal XINT. Input port PI6 uses a function-sharing terminal that can be used in conjunction with the external non-maskable interrupt terminal XNMI. Input port PI7 uses a function-sharing terminal that can be used in conjunction with the receiving terminal of channel SCU0 in the serial communication circuit 139. The POP105B incorporates, for example, an 11-bit wide output-only port, allowing various signals to be output to outside the game control microcomputer 100. The POP105B can supply parallel output signals corresponding to output ports PO0 to PO7 and PO10 to PO12 to the address decoding circuit 137.

[0124] Figure 10-2 shows an example of an address map in the game control microcomputer 100. In the example shown in Figure 10-2, the area from addresses 0000[H] to 3FFF[H] is allocated to ROM 101 and includes the game program area, game data area, non-game program area, non-game data area, ROM comment area, program management area, and other unused areas. The area from addresses F000[H] to F3FF[H] is allocated to RAM 102 and includes the game work area, game stack area, non-game work area, non-game stack area, and other unused areas. The area from addresses FE00[H] to FEBF[H] is the function setting register area allocated to the built-in registers of the game control microcomputer 100. The area from addresses FF00[H] to FFFF[H] is the function control register area allocated to the built-in registers of the game control microcomputer 100.

[0125] In ROM 101, the game program area can store game programs, which are computer programs related to the progress of the game. The game data area can store game data used by the game programs. The non-game program area can store non-game programs, which are computer programs related to control and processing other than the progress of the game. The non-game data area can store non-game data used by the non-game programs. The programs and data stored in these ROM 101 are pre-designed and created by the manufacturer of the pachinko game machine 1, which is the user of the game control microcomputer 100. Therefore, game programs and non-game programs are included in the user program. Game data and non-game data are included in the user data.

[0126] The ROM 101's memory area is divided into two separate areas: a game program area capable of storing game programs related to the progress of the game, and a non-game program area capable of storing control and processing unrelated to the progress of the game. The area in front of the non-game program area to which a later address is assigned becomes an unused area with a memory area of ​​a number of bytes greater than or equal to the boundary byte count, such as 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to the progress of the game and the non-game program area capable of storing control and processing unrelated to the progress of the game, thereby simplifying the design and management of programs and data stored in the ROM 101.

[0127] The ROM 101's memory area is divided into two separate areas: a game program area capable of storing game programs related to the progress of the game, and a game data area capable of storing game data used by the game program. The area in front of the game data area to which the later address of the game program area is assigned becomes an unused area with a memory area of ​​a number of bytes greater than or equal to the boundary byte count, such as 16 bytes. This makes it easy to identify the game program area capable of storing game programs related to the progress of the game and the game data area capable of storing game data used by the game program, thereby simplifying the design and management of programs and data stored in the ROM 101.

[0128] The ROM 101's memory area includes a non-game program area capable of storing non-game programs related to control and processing separate from the game's progression, and a non-game data area capable of storing non-game data used by these non-game programs, both located adjacent to each other. The area behind the non-game program area to which the forward address is assigned becomes the non-game data area, and the area in front of the non-game data area to which the backward address is assigned becomes the non-game program area. This allows for the integration of the non-game program area, capable of storing non-game programs related to control and processing separate from the game's progression, and the non-game data area, capable of storing non-game data used by these programs, by providing them in a memory area with consecutively assigned addresses, thereby facilitating the design and management of programs and data stored in the ROM 101. Furthermore, by providing an unused area of ​​memory space equal to or greater than the boundary byte count between the non-game program area and the non-game data area, it may be possible to easily distinguish between the two areas.

[0129] In the memory area of ​​ROM101, data showing the value "0" may be stored in all unused memory areas. This makes it easy to distinguish between the game program area and game data area, the non-game program area and non-game data area, and the unused area. Furthermore, if invalid data is stored in the unused area, that data can be easily detected. Alternatively, data showing the value "1" may be stored in all unused memory areas. In other words, data showing the same value should be stored in all unused memory areas. This makes it easy to distinguish between multiple types of memory areas and to easily detect invalid stored data.

[0130] In RAM 102, the game work area can be used as a work area when the CPU 103 executes a game program. The game stack area can be used as a stack area when the CPU 103 executes a game program. The non-game work area can be used as a work area when the CPU 103 executes a non-game program. The non-game stack area can be used as a stack area when the CPU 103 executes a non-game program.

[0131] The game program area and game data area provided in the memory area of ​​ROM101, and the game work area and game stack area provided in the memory area of ​​RAM102 are included in the memory area for game control. The non-game program and non-game data area provided in the memory area of ​​ROM101, and the non-game work area and non-game stack area provided in the memory area of ​​RAM102 are included in the memory area for non-game control.

[0132] The ROM comment area in the ROM 101's memory area stores data that indicates arbitrary program-specific information, such as the program title and version. The program management area in the ROM 101's memory area can store setting information necessary for the internal settings of the game control microcomputer 100 so that the CPU 103 can execute game programs and non-game programs.

[0133] Figure 10-3 shows a main example of address settings AKA01, which is included in the function setting register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function setting register area is the first area for setting functions using various circuits included in the game control microcomputer 100, such as the watchdog timer 134A of the reset controller 134, the interrupt controller 135, the timer circuit 136, and the serial communication circuit 139.

[0134] In setting example AKA01, the settings of the WDT start register at address FE1A[H] and the WDT clear registers at addresses FE1B[H] to FE1C[H] are invalid values ​​corresponding to unused states. As a result, the monitoring time measurement function using the watchdog timer 134A of the reset controller 134 is set to an unused state. The interrupt mask register at address FE00[H] is set to 7E[H], so the interrupt control function using the interrupt controller 135 is set to an enabled state for the maskable interrupt IR0. The register settings for channel PTC0 of the timer circuit 136 at addresses FE01[H] to FE03[H] are valid values, so the timing function using channel PTC0 of the timer circuit 136 is set to an enabled state. The register settings for channels PTC1 and PTC2 of the timer circuit 136 at addresses FE04[H] to FE09[H] are invalid values ​​corresponding to unused states, so the timing function using channels PTC1 and PTC2 of the timer circuit 136 is set to an unused state.

[0135] At addresses FE0A[H] to FE11[H], if the register settings for channels SCU0 and SCU1 of the serial communication circuit 139 are valid, the serial communication function using channels SCU0 and SCU1 of the serial communication circuit 139 is set to an enabled state. At addresses FE12[H] to FE14[H], if the register setting for channel STU2 of the serial communication circuit 139 is an invalid value corresponding to unused, the serial communication function using channel STU2 of the serial communication circuit 139 is set to an unused state.

[0136] At addresses FE2C[H]~FE2E[H], if the register settings for the input ports of the PIP105A are valid, the signal input function using each input port is set to an enabled state. At addresses FE36[H]~FE4A[H], if the register settings for the random number circuit 104 include both valid and invalid values, the random number generation function using the random number circuit 104 is set to an enabled state for channels corresponding to valid values, and to an unused state for channels corresponding to invalid values. For example, of the four channels RL0~RL3 in the 16-bit random number circuit 104A, channels RL0 and RL2, whose corresponding maximum value setting registers are valid, are set to an enabled state for the random number generation function, while channels RL1 and RL3, whose corresponding maximum value setting registers are invalid, are set to an unused state for the random number generation function. Furthermore, in the 8-bit random number circuit 104B, of the four channels RS0 to RS3, channels RS1 to RS3, whose corresponding maximum value setting register is a valid value, are set to an enabled state for random number generation, while channel RS0, whose corresponding maximum value setting register is an invalid value, is set to an unused state for random number generation.

[0137] Thus, the various circuits included in the game control microcomputer 100 only need to be able to be set to either an enabled state or an disabled state, corresponding to the setting values ​​in the function setting register area. The function setting register area is not limited to the various circuits included in the game control microcomputer 100, but may be a first area for setting any function.

[0138] Figure 10-4 shows a main example of address settings AKA02, which is included in the function control register area among the addresses assigned to the built-in registers of the game control microcomputer 100. The function control register area is a second area for function control using various circuits included in the game control microcomputer 100, such as RAM 102, random number circuit 104, PIP 105A, and serial communication circuit 139.

[0139] In configuration example AKA02, the RWM access protect register at address FF00[H] enables functional control to either prohibit or allow access to RAM102, which is RWM, depending on the setting value of 00[H] or 01[H]. The internal information register at address FF01[H] has an invalid value corresponding to an unused setting value, and the functional control using the corresponding circuit becomes unused. The internal information register can store data indicating internal information such as abnormalities in the random number update state, abnormalities in the frequency of the random number update clock, system reset occurrence, WDT timeout occurrence, and IAT occurrence, but in this embodiment it is not used when it is unused.

[0140] The registers at addresses FF25[H] to FF28[H] can store setting values ​​used to control the serial communication function using channel SCU0 of the serial communication circuit 139, corresponding to the state in which the serial communication function is enabled. The registers at addresses FF29[H] to FF2C[H] can store setting delays used to control the serial communication function using channel SCU1 of the serial communication circuit 139, corresponding to the state in which the serial communication function is enabled.

[0141] Each register at addresses FF60[H] to FF67[H] can store random values ​​that can be obtained using the soft latch random value acquisition function of the 16-bit random number circuit 104A. Of these, the RL0 soft latch random value register at addresses FF60[H] to FF61[H] can store the numerical data indicating the value of a random number that can be generated by channel RL0 of the 16-bit random number circuit 104A when the data is obtained by the soft latch. The RL1 soft latch random value register at addresses FF62[H] to FF63[H] can store the numerical data indicating the value of a random number that can be generated by channel RL1 of the 16-bit random number circuit 104A when the data is obtained by the soft latch. The RL2 soft latch random value register at addresses FF64[H] to FF65[H] can store the numerical data indicating the value of a random number that can be generated by channel RL2 of the 16-bit random number circuit 104A when the data is obtained by the soft latch. The RL3 soft latch random value registers at addresses FF66[H] to FF67[H] can store numerical data representing the value of a random number that can be generated by channel RL3, which is provided in the 16-bit random number circuit 104A, when the data is acquired by the soft latch.

[0142] Each register at addresses FF68[H] to FF6B[H] can store random values ​​that can be obtained using the soft latch random value acquisition function of the 8-bit random number circuit 104B. Of these, the RS0 soft latch random value register at address FF68[H] can store the numerical data representing the value of a random number that can be generated by channel RS0 of the 8-bit random number circuit 104B when the data is obtained by the soft latch. The RS1 soft latch random value register at address FF69[H] can store the numerical data representing the value of a random number that can be generated by channel RS1 of the 8-bit random number circuit 104B when the data is obtained by the soft latch. The RS2 soft latch random value register at address FF6A[H] can store the numerical data representing the value of a random number that can be generated by channel RS2 of the 8-bit random number circuit 104B when the data is obtained by the soft latch. The RS3 soft latch random number register at address FF6B[H] can store numerical data representing the value of a random number that can be generated by channel RS3, which is provided in the 8-bit random number circuit 104B, when the data is obtained by the soft latch.

[0143] The RL0 hard latch random value register number "0" at addresses FF88[H] to FF89[H] and the RL0 hard latch random value register number "1" at addresses FF98[H] to FF99[H] can store numerical data representing the value of a random number that can be generated by channel RL0, provided in the 16-bit random number circuit 104A, when the value is acquired by the hard latch. Here, the RL0 hard latch random value register includes multiple storage areas corresponding to multiple register numbers, and different hard latch conditions can be set corresponding to the storage areas of different register numbers. For example, the RL0 hard latch random value register number "0", which corresponds to register number "0", can satisfy the hard latch condition when the game ball detection signal from the first start switch 22A is ON. In contrast, the RL0 hard latch random value register number "1", which corresponds to register number "1", can satisfy the hard latch condition when the game ball detection signal from the second start switch 22B is ON. As a result, RL0 hard latch random value register number "0" can store numerical data representing the value of the random number MR1-1 used for special symbol determination, which is acquired in response to the occurrence of the first starting win, when the hard latch has acquired it. RL0 hard latch random value register number "1" can store numerical data representing the value of the random number MR1-1 used for special symbol determination, which is acquired in response to the occurrence of the second starting win, when the hard latch has acquired it.

[0144] The registers at addresses FFF0[H]~FFF2[H] and FF35[H] can store the signal values ​​input at each input port, corresponding to the state in which the signal input function using the input ports of the PIP105A is enabled. Of these, the input port number "0" register at address FFF0[H] can store the signal value input to input port "0" on the PIP105A. The input port number "1" register at address FFF1[H] can store the signal value input to input port "1" on the PIP105A. The input port number "2" register at address FFF2[H] can store the signal value input to input port "2" on the PIP105A. The input port number "3" register at address FF35[H] can store the signal value input to input port "3" on the PIP105A.

[0145] Thus, the various circuits included in the game control microcomputer 100 only need to be able to control their respective operating states in accordance with the values ​​stored in the function control register area. Furthermore, the various circuits included in the game control microcomputer 100 may also be able to update the values ​​stored in the function control register area in accordance with their respective operating states. The function control register area is not limited to the various circuits included in the game control microcomputer 100, but may be a second area for arbitrary function control.

[0146] Figure 10-5 is a diagram illustrating an example of the settings for the random numbers used for gameplay shown in Figure 3 in this embodiment. The random numbers used for gameplay shown in Figure 3 can be classified according to their respective uses into random numbers used to determine the display result in the variable display of special symbols, random numbers used to determine the display result in the variable display of ordinary symbols, and random numbers used to determine the display mode in the variable display of special symbols and ordinary symbols.

[0147] Figure 10-5(A) shows an example of setting AKA11 for the random numbers used in the variable display of special symbols. The random numbers used in setting example AKA11 include a random number MR1-1 for special symbol determination, a random number MR1-2 for winning symbols, and a random number MR1-3 which is the initial value for winning symbols. For example, the random number MR1-1 for special symbol determination can be used to determine whether the special symbol display result is a "big win" or a "small win". The random number MR1-2 for winning symbols can be used to determine the big win symbol specification value or small win symbol specification value corresponding to the confirmed special symbol when the special symbol display result is a "big win" or a "small win". The random number MR1-3 which is the initial value for winning symbols can be used when setting the initial value of the random number MR1-2.

[0148] The range of the random number MR1-1 is the range of numbers within which the random number MR1-1 can be updated, from "0" to "65535". The magnitude of the random number MR1-1 is the total number of random values ​​included in the update range of the random number MR1-1, which is "65536", corresponding to the range of "0" to "65535" for the random number MR1-1. Since the magnitude of the random number MR1-1 is "65536", the total number of random values ​​included in the update range is not a prime number. The number of bytes of numerical data used to update the value of the random number MR1-1 is "2". The method for setting the maximum value of the random number MR1-1 is by initializing a register provided in accordance with the 16-bit random number circuit 104A. The method for updating the random number MR1-1 is by hardware update using the 16-bit random number circuit 104A. The condition for updating the random number MR1-1 is the system clock input to the 16-bit random number circuit 104A. The conditions for obtaining the random number MR1-1 include a hard latch corresponding to the initial win and a software read of that win into a random number buffer. The period of the random number MR1-1 is 4.369 [ms].

[0149] The range of the random number MR1-2 is the range of numbers that can be updated, from "0" to "199". The magnitude of the random number MR1-2 is the total number of random values ​​included in the update range of the random number MR1-2, which is "200", corresponding to the range of "0" to "199" for the random number MR1-2. Since the magnitude of the random number MR1-2 is "200", the total number of random values ​​included in the update range is not a prime number. The number of bytes of numerical data used to update the value of the random number MR1-2 is "1". The method for setting the maximum value of the random number MR1-2 is by setting an immediate value in the program code. The method for updating the random number MR1-2 is software update SA1. The condition for updating the random number MR1-2 is a timer interrupt after a predetermined time has elapsed. The condition for acquiring the random number MR1-2 is reading by software corresponding to the start prize. The period of the random number MR1-2 is 800 [ms].

[0150] The range of random numbers MR1-3 is the range of numbers that can be updated, and is the same as random numbers MR1-2, from "0" to "199". The magnitude of random numbers MR1-3 is the total number of random values ​​included in the update range of random numbers MR1-3, and is the same as random numbers MR1-2, from "0" to "199". Since the magnitude of random numbers MR1-3 is "200", the total number of random values ​​included in the update range is not a prime number. The number of bytes of numerical data used to update the value of random numbers MR1-3 is "1". The method for setting the maximum value of random numbers MR1-3 is by setting an immediate value in the program code. The method for updating random numbers MR1-3 is software update SA2. The conditions for updating random numbers MR1-3 include a timer interrupt due to the elapsed time and during a loop process that becomes a standby process within the main processing P_MAIN for game control. The condition for obtaining random numbers MR1-3 is that random numbers MR1-2 have completed a cycle. The period of random numbers MR1-3 is undefined due to its update conditions.

[0151] Figure 10-5(B) shows an example of setting AKA12 for the random numbers used in the variable display of normal symbols. The random numbers used in setting example AKA12 include a random number MR2-1 for normal symbol winning symbols and a random number MR2-2 which is the initial value for normal symbol winning symbols. For example, the random number MR2-1 for normal symbol winning symbols can be used to determine the normal symbol specification value corresponding to the confirmed normal symbol as the display result of the normal symbol. The random number MR2-2 which is the initial value for normal symbol winning symbols can be used when setting the initial value of the random number MR1-2.

[0152] The range of the random number MR2-1 is the range of numbers that can be updated, from "0" to "198". The magnitude of the random number MR2-1 is the total number of random values ​​included in the update range of the random number MR2-1, which is "199", corresponding to the range of "0" to "198" for the random number MR2-1. Since the magnitude of the random number MR2-1 is "199", the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of the random number MR2-1 is "1". The method for setting the maximum value of the random number MR2-1 is by setting an immediate value in the program code. The method for updating the random number MR2-1 is software update SA1. The condition for updating the random number MR2-1 is a timer interrupt due to the elapsed time. The condition for acquiring the random number MR2-1 is software reading corresponding to the game ball passing through the passage gate 41 which can be configured as a normal symbol activation opening. The period of the random number MR2-1 is 796 ms.

[0153] The range of random number MR2-2 is the range of numbers that can be updated, and is the same as random number MR2-1, from "0" to "198". The magnitude of random number MR2-2 is the total number of random values ​​included in the update range of random number MR2-2, and is the same as random number MR2-1, from "0" to "198". Since the magnitude of random number MR2-2 is "199", the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR2-2 is "1". The method for setting the maximum value of random number MR2-2 is by setting an immediate value in the program code. The method for updating random number MR2-2 is software update SA2. The conditions for updating random number MR2-2 include a timer interrupt due to the elapsed time and during a loop process that becomes a standby process within the main processing P_MAIN for game control. The condition for obtaining the random number MR2-2 is that the random number MR2-1 has completed one cycle. The period of the random number MR2-2 is undefined due to its update conditions.

[0154] Figure 10-5(C) shows an example of setting AKA13 for random numbers used in games, which are used to determine the display patterns in the variable display of special and regular symbols. The random numbers used in setting example AKA13 include MR3-1 for the regular symbol variation pattern, MR3-2 for selecting the losing animation, MR3-3 for selecting the variation pattern type, and MR3-4 for the variation pattern. For example, MR3-1 for the regular symbol variation pattern can be used to determine the regular symbol variation pattern corresponding to the variable display of regular symbols. MR3-2 for selecting the losing animation can be used to determine the variable display pattern corresponding to the variable display of special symbols where the special symbol display result is "losing". MR3-3 for selecting the variation pattern type can be used to select the variation pattern type corresponding to the variable display of special symbols. MR3-4 for the variation pattern can be used to determine the variation pattern corresponding to the variable display of special symbols.

[0155] The range of the random number MR3-1 is the range of numbers within which the random number MR3-1 can be updated, from "0" to "232". The magnitude of the random number MR3-1 is the total number of random values ​​included in the update range of the random number MR3-1, which is "233", corresponding to the range of "0" to "232" for the random number MR3-1. Since the magnitude of the random number MR3-1 is "233", the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of the random number MR3-1 is "1". The method for setting the maximum value of the random number MR3-1 is by initializing a register provided in correspondence with the 8-bit random number circuit 104B. The method for updating the random number MR3-1 is by hardware update using the 8-bit random number circuit 104B. The condition for updating the random number MR3-1 is the system clock input to the 8-bit random number circuit 104B. The condition for acquiring the random number MR3-1 is the start of variation in the variable display of a normal pattern. The period of the random number MR3-1 is 0.249 [ms].

[0156] The range of the random number MR3-2 is the range of numbers within which the random number MR3-2 can be updated, from "0" to "65518". The magnitude of the random number MR3-2 is the total number of random values ​​included in the update range of the random number MR3-2, which is "65519", corresponding to the range of "0" to "65518" for the random number MR3-2. Since the magnitude of the random number MR3-2 is "65519", the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of the random number MR3-2 is "2". The method for setting the maximum value of the random number MR3-2 is by initializing a register provided in conjunction with the 16-bit random number circuit 104A. The method for updating the random number MR3-2 is by hardware update using the 16-bit random number circuit 104A. The condition for updating the random number MR3-2 is the system clock input to the 16-bit random number circuit 104A. The conditions for obtaining the random number MR3-2 include reading it into a random number buffer by software corresponding to the start-up prize. The period of the random number MR3-2 is 139.774 [ms].

[0157] The range of the random number MR3-3 is the range of numbers within which the random number MR3-3 can be updated, from "0" to "240". The magnitude of the random number MR3-3 is the total number of random values ​​included in the update range of the random number MR3-3, which is "241", corresponding to the range of "0" to "240". Since the magnitude of the random number MR3-3 is "241", the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of the random number MR3-3 is "1". The method for setting the maximum value of the random number MR3-3 is by initializing a register provided in conjunction with the 8-bit random number circuit 104B. The method for updating the random number MR3-3 is by hardware update using the 8-bit random number circuit 104B. The condition for updating the random number MR3-3 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining the random number MR3-3 include reading it into a random number buffer by software corresponding to the start-up prize. The period of the random number MR3-3 is 0.257 [ms].

[0158] The range of random number MR3-4 is the range of numbers within which random number MR3-4 can be updated, from "0" to "250". The magnitude of random number MR3-4 is the total number of random values ​​included in the update range of random number MR3-4, which is "251", corresponding to the range of "0" to "250" for random number MR3-4. Since the magnitude of random number MR3-4 is "251", the total number of random values ​​included in the update range is a prime number. The number of bytes of numerical data used to update the value of random number MR3-4 is "1". The method for setting the maximum value of random number MR3-4 is by initializing a register provided in conjunction with the 8-bit random number circuit 104B. The method for updating random number MR3-4 is by hardware update using the 8-bit random number circuit 104B. The condition for updating random number MR3-4 is the system clock input to the 8-bit random number circuit 104B. The conditions for obtaining random numbers MR3-4 include reading them into a random number buffer by software corresponding to the start-up prize. The period of random numbers MR3-4 is 0.268 [ms].

[0159] The software update SA1 method for updating random numbers MR1-2 and MR2-1 allows the values ​​to be updated by adding 1 to the previous value each time the software update process is executed. If the updated value exceeds the maximum random number value, it is changed to "0", which is the minimum random number value. If the updated value matches the initial random number value, the current random number value is set using the corresponding initial random number and stored as the new initial random number value. For example, for random number MR1-2, if the updated value matches the initial random number value, the current random number value is set using random number MR1-3, which is the initial value for winning symbols, and that random number value is stored as the new initial random number value. For random number MR2-1, if the updated value matches the initial random number value, the current random number value is set using random number MR2-2, which is the initial value for normal symbols and winning symbols, and that random number value is stored as the new initial random number value.

[0160] The software update SA2 method, which updates random numbers MR1-3 and MR2-2, allows the values ​​to be updated by adding 1 to the previous value each time the software update process is executed. If the updated value exceeds the maximum random number value, it is changed to "0", which is the minimum random number value. In this case, unlike software update SA1, an initial random number value is not used, so the updated value will be either the previous value plus 1, or the minimum random number value, "0".

[0161] Figure 10-6 is a diagram illustrating the random number update period when updating random values ​​using the 16-bit random number circuit 104A and the 8-bit random number circuit 104B included in the random number circuit 104. Here, the random numbers that can be generated by channels RL0 to RL4 provided in the 16-bit random number circuit 104A are referred to as 16-bit random numbers RLn. Similarly, the random numbers that can be generated by channels RS0 to RS4 provided in the 8-bit random number circuit 104B are referred to as 8-bit random numbers RSn. The period for one cycle of the 16-bit random number RLn that can be updated by the 16-bit random number circuit 104A is determined by a different relational expression depending on whether the maximum value of the 16-bit random number RLn is a specific maximum value expressed using a power of 2. The period for one cycle of the 8-bit random number RSn that can be updated by the 8-bit random number circuit 104B is determined by a different relational expression depending on whether the maximum value of the 8-bit random number RSn is a specific maximum value expressed using a power of 2.

[0162] Figure 10-6(A) shows an example AKA21 of setting the 16-bit random number period in the 16-bit random number circuit 104A. The 16-bit random number period is the period it takes for the 16-bit random number RLn, which can be updated by the 16-bit random number circuit 104A, to complete one cycle. In the example AKA21 of setting the 16-bit random number period, when the maximum value of the 16-bit random number RLn corresponds to 2m-1 when m=9 to 16, the period for completing one cycle of the 16-bit random number sequence is proportional to the reciprocal of the count clock frequency, i.e., the count clock period. It is then a linear function with the value obtained by adding 1 to the maximum value, i.e., the magnitude of the 16-bit random number RLn, as the variable. In contrast, when the maximum value of the 16-bit random number RLn does not correspond to 2m-1 when m=9 to 16, the period for completing one cycle of the 16-bit random number sequence is proportional to the reciprocal of the count clock frequency, i.e., 32 times the count clock period. Then, it becomes a linear function with the value obtained by adding 1 to the maximum value, that is, the magnitude of the 16-bit random number RLn, as the variable. In this way, when the maximum value of the 16-bit random number RLn, which can be updated by the 16-bit random number circuit 104A, is a specific maximum value, the random number update period becomes shorter, that is, the random value update speed becomes faster than when its maximum value is not the specific maximum value.

[0163] Figure 10-6(B) shows an example of setting the 8-bit random number period in the 8-bit random number circuit 104B, AK22. The 8-bit random number period is the period it takes for the 8-bit random number RSn, which can be updated by the 8-bit random number circuit 104B, to complete one cycle. In the 8-bit random number period setting example AKA22, when the maximum value of the 8-bit random number RSn corresponds to 2m-1 when m=5 to 8, the period for completing one cycle of the 8-bit random number sequence is proportional to the reciprocal of the count clock frequency, i.e., the count clock period. It is then a linear function with the value obtained by adding 1 to the maximum value, i.e., the magnitude of the 8-bit random number RSn, as the variable. In contrast, when the maximum value of the 8-bit random number RSn does not correspond to 2m-1 when m=5 to 8, the period for completing one cycle of the 8-bit random number sequence is proportional to the reciprocal of the count clock frequency, i.e., 16 times the count clock period. Then, it becomes a linear function with the value obtained by adding 1 to the maximum value, that is, the magnitude of the 8-bit random number RSn, as the variable. In this way, when the maximum value of the 8-bit random number RSn, which can be updated by the 8-bit random number circuit 104B, is a specific maximum value, the random number update period becomes shorter, that is, the random value update speed becomes faster than when its maximum value is not the specific maximum value.

[0164] Figure 10-6(C) shows a comparison example AKA23 of random number values ​​that can be updated by a 16-bit random number circuit 104A and an 8-bit random number circuit 104B. The 16-bit random number circuit 104A can update the random numbers corresponding to the random number MR1-1 for special symbol determination and the random number MR3-2 for selecting the losing animation. The 8-bit random number circuit 104B can update the random numbers corresponding to the random number MR3-3 for selecting the variation pattern type and the random number MR3-4 for the variation pattern.

[0165] Random number MR1-1 has a maximum value of "65535", which corresponds to 2m-1 when m=16. As a result, the period of random number MR1-1 is 4.369 [ms], and the update rate at this time is 15000 [times / ms]. Random number MR3-2 has a maximum value of "65518", which does not correspond to 2m-1 when m=9 to 16. As a result, the period of random number MR3-2 is 139.774 [ms], and the update rate at this time is 469 [times / ms]. Random number MR3-3 has a maximum value of "240", which does not correspond to 2m-1 when m=5 to 8. As a result, the period of random number MR3-3 is 0.257 [ms], and the update rate at this time is 938 [times / ms]. The random number generator MR3-4 has a maximum value of "250" and does not correspond to 2m-1 when m=5 to 8. As a result, the period of the random number generator MR3-4 is 0.268 [ms], and the update rate at this time is 938 [times / ms].

[0166] Thus, the random numbers for gameplay that can be updated by the 16-bit random number circuit 104A include random number MR1-1 for determining special symbols and random number MR3-2 for selecting losing animations. Both random numbers MR1-1 and MR3-2 have a numerical data size of "2", and are composed of 2 bytes as a specific number. The magnitude of random number MR1-1 is "65536", and the magnitude of random number MR3-2 is "65519", so if the total number of random values ​​included in the update range of random number MR1-1 is a specific number, then the total number of random values ​​included in the update range of random number MR3-2 is a predetermined number that is smaller than the specific number. The update speed of random number MR1-1 is 15000 [times / ms], and the update speed of random number MR3-2 is 469 [times / ms], so random number MR1-1 has a faster update speed than random number MR3-2. This suppresses the synchronous generation of random values ​​and enables appropriate updating of random values.

[0167] Furthermore, the random numbers for gameplay that can be updated by the 16-bit random number circuit 104A include the random number MR3-2 for selecting the losing animation. The random numbers for gameplay that can be updated by the 8-bit random number circuit 104B include the random number MR3-3 for selecting the type of variation pattern and the random number MR3-4 for the variation pattern. In all of these random numbers MR3-2 to MR3-4, the total number of random values ​​included in the update range is a prime number. The update rate of random number MR3-2 is 469 [times / ms], while the update rates of random numbers MR3-3 and MR3-4 are 938 [times / ms]. In other words, the update rates of random numbers MR3-3 and MR3-4 are twice as fast as the update rate of random number MR3-2, which is an integer multiple. Therefore, if random number MR3-2 is used as the first random number, and random numbers MR3-3 and MR3-4 are used as the second random numbers, the update speed of the first random number is the first speed, and the update speed of the second random number is the second speed, which is an integer multiple of the first speed. Furthermore, the update range of random number MR3-2 is "0" to "65518", the update range of random number MR3-3 is "0" to "240", and the update range of random number MR3-4 is "0" to "250". Thus, the total number of random numbers included in the update ranges of the first and second random numbers are different, and in both cases, the total number of random numbers included in the update range is a prime number. This suppresses the synchronous generation of random numbers and enables appropriate random number updates.

[0168] The CPU 103 contains multiple registers, including a program counter, interrupt register, stack pointer, index register, flag register, address register, and general-purpose registers including an accumulator. The index register, flag register, and general-purpose register may have both a main register and sub-registers. The registers included in the main register and sub-register, and the stack pointer, may be configured to form multiple register banks. The multiple register banks may include a first register bank for use within the area usable when executing a game program, and a second register bank for use outside the area usable when executing a non-game program. This eliminates the need to save values ​​stored in general-purpose registers, etc., to and restore them from the stack area when switching between executing a game program and a non-game program, thus preventing an increase in program size and processing burden.

[0169] The program counter is used by the CPU 103 to hold the address value of the next instruction to be executed, and is also called the PC register. The value stored in the program counter is sequentially incremented each time an instruction is executed, or the address value of the branch destination of a branch instruction is set. The interrupt register can hold the upper address value of the interrupt vector table, and is also called the I register. The value stored in the I register is set in response to the start of power supply to the pachinko game machine 1.

[0170] The stack pointer, also known as the SP register, can hold address values ​​corresponding to the game stack area and the non-game stack area. The stack pointer's stored value can be set to a save address for storing the stored or immediate values ​​of predefined registers, including the program counter, or registers specified by instructions, in response to interrupt occurrences, execution of PUSH instructions, and execution of subroutine call instructions such as CALL, CALLF, and RST instructions. Upon this saving, the value is updated to indicate the starting address of the storage area holding the stored value. Furthermore, the stack pointer's stored value can be set to a read address for restoring the saved register values ​​in response to the end of interrupt processing, execution of POP instructions, and completion of subroutine processing. Upon this restoration, the value is updated to indicate the address corresponding to the read value. Additionally, the stack pointer's stored value can be set to the stored or immediate values ​​of registers specified by load instructions such as the LD instruction.

[0171] The index registers include the IX register and the IY register, each with a 2-byte storage capacity capable of storing 16-bit data. The accumulator is also called the A register. Other general-purpose registers include several registers with a 1-byte storage capacity capable of storing 8-bit data, such as the B register, C register, D register, E register, H register, and L register. The B and C registers can be used as the BC registers of a pair of registers capable of storing 16-bit data. The D and E registers can be used as the DE registers of a pair of registers capable of storing 16-bit data. The H and L registers can be used as the HL registers of a pair of registers capable of storing 16-bit data.

[0172] The internal registers of the CPU 103 can be updated to reflect the values ​​stored in them in response to arithmetic instructions and transfer instructions executed by the CPU 103. They are used for specifying program addresses, data addresses, or built-in register addresses of the game control microcomputer 100, as well as for holding arithmetic data and transfer data.

[0173] In the game control microcomputer 100, the instruction set for the CPU 103 to execute a program consists of transfer instructions such as load instructions, subroutine call instructions, jump instructions, and other arithmetic and logical operation instructions, as well as input / output instructions. Computer programs that the CPU 103 can execute, such as game programs and non-game programs, are prepared in advance as program code that describes these various instructions and are stored in the ROM 101.

[0174] A load instruction is a transfer instruction that can be used to set data read from the memory area of ​​ROM101 or RAM102 or the internal device area and store it in the internal register of the CPU103; to store a value stored in the internal register of the CPU103 by writing it to the memory area of ​​RAM102 or the internal device area; or to set or store a numerical value specified by an operand as an immediate value in the internal register of the CPU103 or the memory area of ​​RAM102 or the internal device area. The target of data transfer by a load instruction can be identified in accordance with the instruction code and operand, and generally includes the data source and destination. However, when an immediate value is specified by an operand, the data source is not included.

[0175] Load instructions include the normal LD ​​instruction, the special LDQ instruction, the special LDF instruction, and the special ICPLD instruction. The normal LD ​​instruction is also called a normal transfer instruction. The special LDQ instruction is also called a first special transfer instruction. The special LDF instruction is also called a second special transfer instruction. The special ICPLD instruction is also called a third special transfer instruction.

[0176] The LD instruction, a standard data transfer instruction, allows data to be transferred to the storage area of ​​ROM101 or RAM102 or to the built-in device area by specifying both the upper and lower addresses. Furthermore, when transferring data to the storage area of ​​ROM101 or RAM102 or to the built-in device area using the LD instruction, the destination or source address can be specified by a pointer using a pair register such as the HL register.

[0177] The LDQ instruction, the first special transfer instruction, uses the Q register, a special register included in the CPU 103's internal registers, to transfer data by specifying only the lower address. The Q register has a pre-set value indicating the upper address, and by combining this with the lower address specified by the LDQ instruction, the destination or source address can be identified and the data transferred.

[0178] The LDQ instruction, the first special transfer instruction, can transfer data with less program code than the LD instruction, a normal transfer instruction. However, in programs that frequently change the value stored in the Q register, the amount of program code may actually increase compared to using the normal LD ​​instruction. Therefore, it is sufficient to be able to execute data transfer using the LDQ instruction, the first special transfer instruction, to handle processes that require transferring various data multiple times to the game work area at addresses F000[H] to F0D7[H], the function setting register area at addresses FE00[H] to FEBF[H], and the function control register area at addresses FF00[H] to FFFF[H].

[0179] The LDF instruction, a second special transfer instruction, allows data transfer by specifying only the lower addresses of stored data within a specific address range. This specific address range is, for example, from address 1200[H] to 1DFF[H]. Therefore, by pre-configuring the game data area of ​​ROM101 to be included within this specific address range, and combining it with the lower addresses specified by the LDF instruction, the source address can be identified and the data transferred. Note that the game data area of ​​ROM101 is read-only and cannot be written to, so the address of the game data area can never be specified as the destination address.

[0180] The LDF instruction, a second special transfer instruction, can transfer data with less program code than the LD instruction, a normal transfer instruction. However, since a specific address range is fixed by the specifications, it is sufficient to set the storage area for frequently used data, such as the game data area of ​​ROM101, to be included in the specific address range, and then execute data transfer using the LDF instruction.

[0181] The ICPLD instruction, the third special transfer instruction, compares the value to be updated with a comparison value. If the value to be updated is less than the comparison value, it is updated by adding 1 to the value; otherwise, if the value to be updated is greater than or equal to the comparison value, it is changed to the minimum value, "0". The value to be updated may be the value indicated by the stored data at the address pointed to by the pointer, or it may be the value stored in a register. The comparison value may be the value stored in a register, or it may be the value indicated by the operand of the ICPLD instruction.

[0182] Thus, the ICPLD instruction, which is the third special transfer instruction, is a single compare-add instruction that includes comparing the value to be updated with a comparison judgment value, adding 1 to the value to be updated if the result of the comparison is less than the comparison judgment value, and changing the value to be updated to the minimum value if the result of the comparison is equal to or greater than the comparison judgment value.

[0183] Setting a value in the CPU 103's internal registers using an immediate value from the operand of a transfer instruction is also called "setting." Reading stored data from the ROM 101's game data area or the RAM 102's game work area and storing it in the CPU 103's internal registers is also called "loading." Storing the value stored in the CPU 103's internal registers in a buffer, counter, timer, or other arbitrary storage area provided in the RAM 102's game work area is also called "storing."

[0184] Figure 10-7 is a flowchart showing an example of the power supply start response process P_POWER_ON. The power supply start response process P_POWER_ON is included in the processes that can be called from the main game control process P_MAIN shown in Figure 4, and can be executed in step S1 in response to the start of power supply in the pachinko game machine 1. When the CPU 103 executes the power supply start response process P_POWER_ON, it sets interrupts to disabled (step AKS1), and then sets the initial value of the stack pointer in the area to the stack pointer (step AKS2). The initial value of the stack pointer in the area should be address F200[H], which is the last address of the game stack area plus 1, corresponding to the initial state in which no saved data is stored in the game stack area.

[0185] Following step AKS2, a transfer instruction to set the internal registers of the CPU 103 sets the connection confirmation signal ON output value (step AKS3). The connection confirmation signal ON output value is a value that indicates the connection confirmation signal is ON, and can be, for example, 00[H]. At this time, a transfer instruction to set the Q register, which is included in the internal registers of the CPU 103, sets the upper address of the function control register in the Q register (step AKS4). The upper address of the function control register is the value FF[H] which indicates the upper address of the function control register area in the setting example AKA02 shown in Figure 10-4. Once the upper address of the function control register is set, a transfer instruction using the upper address indicated by the value stored in the Q register stores the connection confirmation signal ON output value (step AKS5). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set to the upper address of the function control register area by step AKS4. Therefore, a transfer instruction, such as a special 2-byte LDQ instruction that specifies a lower address, can be used to store the connection confirmation signal ON output value set in step AKS3 in the function control register at the specified address in the function control register area. In step AKS5, the connection confirmation signal ON output value is stored in the output port number "1" register provided in the function control register area. This sets the connection confirmation signal transmitted from the main board 11 to the dispensing control board to the ON state.

[0186] Step AKS5 sets the connection confirmation signal to the ON state, and a transfer instruction using the higher address indicated by the value stored in the Q register stores the SCU0 command register clear output value (Step AKS6). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set to the higher address of the function control register area by Step AKS4. The SCU0 command register clear output value can be specified by the operand of the transfer instruction. Therefore, the SCU0 command register clear output value can be stored in the function control register at the specified address in the function control register area by a transfer instruction for writing to the storage area at the specified address, such as a special 3-byte LDQ instruction that specifies the lower address and the SCU0 command register clear output value. In Step AKS6, the SCU0 command register clear output value is stored in the SCU0 command register located at address FF28[H] in the function control register area in the setting example AKA02 shown in Figure 10-4. This controls the serial communication function using channel SCU0 of the serial communication circuit 139 to its initial state.

[0187] After step AKS6, the SCU1 command register clear output value is stored using a transfer instruction that uses the higher address indicated by the value stored in the Q register (step AKS7). In this case, the lower address of the transfer destination can be specified by the operand of the transfer instruction. The value stored in the Q register is set to the higher address of the function control register area by step AKS4. The SCU1 command register clear output value can be specified by the operand of the transfer instruction. Therefore, the SCU1 command register clear output value can be stored in the function control register at the specified address in the function control register area by a transfer instruction that writes to the storage area at the specified address, such as a special 3-byte LDQ instruction that specifies the lower address and the SCU0 command register clear output value. In step AKS7, the SCU1 command register clear output value is stored in the SCU1 command register located at address FF2C[H] in the function control register area in the setting example AKA02 shown in Figure 10-4. This controls the serial communication function using channel SCU1 of the serial communication circuit 139 to its initial state.

[0188] When these serial communication functions are controlled to their initial state, a transfer instruction to set the internal registers of the CPU 103 sets the upper address of the interrupt vector table (step AKS8). The upper address of the interrupt vector table is the upper address of the interrupt vector table located in the game program area of ​​the ROM 101. For example, for the timer interrupt processing P_PCT for game control that is executed in response to the occurrence of a timer interrupt, the starting address is stored at a table position corresponding to the interrupt order. Such an upper address of the interrupt vector table is set in the I register by a transfer instruction to set the internal registers of the CPU 103 (step AKS9).

[0189] Following step AKS9, the value stored in the Q register is updated by subtracting 1 (step AKS10). The value stored in the Q register was set to the upper address of the function control register area by step AKS4. When this value is subtracted by 1, the upper address of the function setting register area in the setting example AKA01 shown in Figure 103 becomes stored in the Q register. In this way, after the function control registers in the function control register area have been set, the function setting registers in the function setting register area become configurable. At this time, the function setting register storage value table address is set by a transfer instruction to set the pointer (step AKS11). The function setting register storage value table address is the address of the function setting register storage value table stored in the game data area of ​​ROM101. Then, the number of processes is loaded by a transfer instruction to read the stored data at the address pointed to by the pointer (step AKS12). In addition, the function setting register store instruction is used to perform the setting using the function setting register storage value table (step AKS13). The function setting register store instruction should be an instruction that identifies the function setting register using the stored data at the address obtained by adding 1 to the address pointed to by the pointer, stores the function setting register setting value indicated by the stored data at the address obtained by adding 2 to the address pointed to by the pointer into the identified function setting register, adds 2 to the stored value of the pointer, and subtracts 1 from the number of operations, repeating this until the number of operations becomes 0. In this way, the initial setup of the function setting register is made possible.

[0190] Step AKS13 completes the initial setup of the function setting registers, and then the access permission output value is stored in the RWM access protect register (step AKS14). The access permission output value of the RWM access protect register is set to, for example, 01[H] by a transfer instruction to set the internal registers of the CPU 103. Such an access permission output value is stored in the RWM access protect register by a transfer instruction to write it to the memory area at the starting address of the function setting register area. The RWM access protect register enables function control that grants access to RAM 102, which is RWM, in response to the setting of the access permission output value 01[H]. Therefore, when the access permission output value is stored in the RWM access protect register by step AKS14, access to RAM 102 is permitted in response to the start of power supply in the pachinko game machine 1.

[0191] After step AKS14, the upper address of the game work area, which is the working area of ​​RAM102, is set in the Q register (step AKS15), and then the power supply start corresponding process P_POWER_ON is completed. In this way, after access to RAM102 is permitted by step AKS14, the value F0[H] indicating the upper address of the game work area in RAM102 is set in the Q register. After step AKS15, when the LDQ instruction, which is the first special transfer instruction, is executed, the value F0[H] stored in the Q register can be used as the upper address of the transfer destination or transfer source without specifying it as an operand. This reduces the program capacity of the processing using the game work area in RAM102, thereby improving the marketability of the gaming machine.

[0192] Figure 10-8 shows an example configuration AKT01 of the function setting register storage value table used in the power supply start processing P_POWER_ON. In the power supply start processing P_POWER_ON, for example, the number of processes is loaded in step AKS12 using the function setting register storage table whose address is set in step AKS11, and the storage value of each function setting register is stored by the function setting register store instruction in step AKS13. In the function setting register storage value table of configuration example AKT01, the value 18[H] indicating the number of processes is stored at the starting address 1200[H]. In step AKS12, this table data is read and loaded into the internal register of the CPU 103. Subsequently, the function setting register store instruction in step AKS13 sequentially reads the table data, which combines the lower address and storage value of the function setting register, and makes it possible to store the storage value in the function setting register corresponding to each lower address.

[0193] In the example configuration AKT01, the function setting register storage value table is structured so that the storage values ​​of function setting registers with smaller values ​​indicating lower addresses can be set first, and the storage values ​​of function setting registers with larger values ​​indicating lower addresses can be set later. As a result, in the function setting register area, the storage values ​​of function setting registers closer to the starting address are set first, and the storage values ​​of function setting registers closer to the final address are set later. This makes it easier to design and manage the data indicating the storage values ​​of function setting registers, thereby improving the marketability of the gaming machine.

[0194] The 16-bit random number circuit 104A corresponds to four channels RL0 to RL3, and updates can be initiated from the channel where the maximum value setting register has been set to indicate the maximum random number value. The 8-bit random number circuit 104B corresponds to four channels RS0 to RS3, and updates can be initiated from the channel where the maximum value setting register has been set to indicate the maximum random number value. The function setting register area of ​​the setting example AKA01 shown in Figure 10-3 is provided with the RL0 maximum value setting register at addresses FE3F[H] to FE40[H], the RL1 maximum value setting register at addresses FE41[H] to FE42[H], the RL2 maximum value setting register at addresses FE43[H] to FE44[H], and the RL3 maximum value setting register at addresses FE45[H] to FE46[H], corresponding to the four channels RL0 to RL3 of the 16-bit random number circuit 104A. Furthermore, this function setting register area includes the RS0 maximum value setting register at address FE47[H], the RS1 maximum value setting register at address FE48[H], the RS2 maximum value setting register at address FE49[H], and the RS3 maximum value setting register at address FE4A[H], corresponding to the four channels RS0 to RS4 in the 8-bit random number circuit 104B. In the example configuration AKT01, the function setting register storage value table is configured such that the storage value of the RL0 maximum value setting register is set first, followed by the RL2 maximum value setting register, then the RS1 maximum value setting register, then the RS2 maximum value setting register, and finally the RS3 maximum value setting register. Therefore, the updating of channel RL0 in the 16-bit random number circuit 104A starts first, followed by the updating of channel RL2 in the 16-bit random number circuit 104A, then the updating of channel RS1 in the 8-bit random number circuit 104B, then the updating of channel RS2 in the 8-bit random number circuit 104B, and finally the updating of channel RS3 in the 8-bit random number circuit 104B. In this way, the updates start sequentially from the random number values ​​for which the maximum random number value has been set, so the uncertainty of the random number values ​​is increased by the timing of when the random number values ​​are updated, reducing the processing load and enabling appropriate updating of random number values.

[0195] The power supply start-up processing P_POWER_ON is a startup process executed based on the start of power supply in the pachinko game machine 1 and is included in the processes that can be called from the main game control processing P_MAIN. Using the function setting register storage value table in configuration example AKT01, it is possible to set a storage value in the function setting register area, which is a storage area for functions. At this time, the maximum random number value of the random number value updated by the 16-bit random number circuit 104A and the 8-bit random number circuit 104B can be set, so the power supply start-up processing P_POWER_ON can be executed as a maximum value setting process. The 16-bit random number circuit 104A can update a first random number value consisting of 16 bits corresponding to 2 bytes as a specific number of bytes. The 8-bit random number circuit 104B can update a second random number value consisting of 8 bits corresponding to 1 byte as a predetermined number of bytes smaller than the specific number of bytes. Then, when executing the power supply start processing P_POWER_ON, the maximum random value of the first random number that can be updated by the 16-bit random number circuit 104A is set using the function setting register storage value table of configuration example AKT01, and then the maximum random value of the second random number that can be updated by the 8-bit random number circuit 104B is set. In this way, by setting the first random number of a specific number of bytes and then setting the second random number of a predetermined number of bytes, the first and second random numbers can be updated stably, enabling the updating of appropriate random numbers.

[0196] Figure 10-9 shows an example configuration of the RWM access protect register. The RWM access protect register is located at address FF00[H] in the example configuration AKA02 of the function control register area shown in Figure 10-4. The value stored in the RWM access protect register will be different depending on whether access to RAM102, which will be RWM, is denied or permitted.

[0197] Figure 10-9(A) shows an example of the bit configuration of the RWM access protect register. The RWM access protect register can store 8-bit data RAP with bit numbers from "0" to "7", and the bit data RAP0 with bit number "0" can be set to 0[B] or 1[B]. In contrast, the bit data with bit numbers from "1" to "7" always represents a fixed value that is set to 0[B] and is never set to "1".

[0198] Figure 10-9(B) is a diagram illustrating an example of using the bit data RAP of the RWM access protect register. In the bit data RAP, bit number "0" (RAP0) is the RWM access control bit. Setting it to 0[B] prohibits RWM access, and setting it to 1[B] allows RWM access. In response to the start of power supply to the pachinko machine 1, bit number "0" (RAP0) is set to its initial value of 0[B]. This makes it possible to prohibit access to RAM 102, which is RWM, in response to the start of power supply to the pachinko machine 1.

[0199] Figure 10-10 is a flowchart showing an example of the power-off process P_POWER_OFF. The power-off process P_POWER_OFF is included in the processes that can be called from the timer interrupt process P_PCT for game control shown in Figure 5, and can be executed in step S51 each time a timer interrupt occurs. When the CPU 103 executes the power-off process P_POWER_OFF, it sets the backup monitoring timer address by a transfer instruction for setting a pointer (step AKS31). The backup monitoring timer address is the address of the backup monitoring timer located in the game work area of ​​RAM 102.

[0200] Input port number "3" (step AKS32). Input port number "3" is an input port assigned the port number "3" and includes a power confirmation signal input bit. A logical AND operation is then performed using the input data of input port number "3" and the check data corresponding to the bit position of the power confirmation signal input bit. At this time, it is determined whether the power confirmation signal input bit is "0" or not based on whether the zero flag is on or not (step AKS33). The power confirmation signal input bit indicates that the power confirmation signal is off when its bit value corresponds to "0" (0[B]) and that the power confirmation signal is on when its bit value corresponds to "1" (1[B]).

[0201] If the power confirmation signal input bit is "1" instead of "0" (step AKS33; No), the backup monitoring timer clear data is stored using a transfer command that can update the stored data at the address pointed to by the pointer (step AKS34). In step AKS34, by storing the clear data in the backup monitoring timer, the backup monitoring timer can be cleared when the power confirmation signal is ON, corresponding to the fact that it is not in the process of determining if a power failure has occurred.

[0202] If the power confirmation signal input bit is "0" in response to step AKS33 (step AKS33; Yes), the timing value from the backup monitoring timer is updated to increment by 1 (step AKS35). The backup monitoring timer is also loaded by a transfer instruction to read the stored data at the address pointed to by the pointer (step AKS36). Then, a return operation instruction that allows comparison between the timing value from the backup monitoring timer and the judgment value corresponding to the backup judgment time is used (step AKS37) to confirm that the backup monitoring timer is not indicating the backup judgment time (step AKS38). This return operation instruction corresponds to a zero flag that is turned off when the timing value from the backup monitoring timer and the judgment value corresponding to the backup judgment time are different, allowing the power-off process to end and the return to the special pattern process to begin. Thus, if the backup monitoring timer is not indicating the backup judgment time (step AKS38; Yes), the power-off process ends.

[0203] If the backup monitoring timer indicates the backup determination time in response to step AKS38 (step AKS38; No), the checksum calculation process P_SUM_CALC is executed (step AKS39). The checksum calculation process P_SUM_CALC in step AKS39 only needs to be the same process as the checksum calculation process included in the RWM check process P_RWM_CHK in step S2 in the main process P_MAIN for game control shown in Figure 4. By executing a common checksum calculation process in response to the start and stop of power supply in the pachinko game machine 1, it becomes possible to determine whether recovery with backup data is possible based on whether the contents of the game work area of ​​RAM 102 have been retained without change. The checksum data created by the checksum calculation process P_SUM_CALC in step AKS39 is stored in the checksum buffer by a transfer instruction to write it to the memory area at the address pointed to by the pointer (step AKS40).

[0204] Following step AKS40, an exclusive OR operation instruction sets the clear data to the output value data (step AKS41). This exclusive OR operation instruction calculates the exclusive OR of the stored values ​​in a single register, resulting in an exclusive OR of identical bit values, thus allowing the stored value to be initialized to the clear data 00[H]. This clear data is then stored in the RWM access protect register by a transfer instruction to write it to the memory area at the starting address in the function setting register area (step AKS42). The RWM access protect register enables function control that prohibits access to RAM102, which is RWM, in response to the setting of the clear data 00[H]. Therefore, when the clear data is stored in the RWM access protect register by step AKS42, access to RAM102 is prohibited in response to the power supply to the pachinko machine 1 being stopped.

[0205] After step AKS42, output port numbers "0" through "10" are cleared (step AKS43). Output port numbers "0" through "10" are the output ports with port numbers from "0" to "10", and are all the output ports in the game control microcomputer 100. Therefore, in step AKS43, in response to the cessation of power supply to the pachinko game machine 1, all output ports in the game control microcomputer 100 are set to a clear state. At this time, a transfer instruction to set the internal register of the CPU 103 sets the connection confirmation signal off output value (step AKS44). The connection confirmation signal off output value is a value that indicates the connection confirmation signal is in the off state, and can be, for example, 01[H]. Such a connection confirmation signal off output value is stored in the output port number "1" register by a transfer instruction to write it to the memory area at the specified address in the function control register area (step AKS45). As a result, the connection confirmation signal transmitted from the main board 11 to the payout control board is set to the off state.

[0206] Following step AKS45, a transfer instruction is used to set the PTC0 interrupt disable output value in the CPU 103's internal registers (step AKS46). The PTC0 interrupt disable output value is an output value that disables the generation of timer interrupts using channel PTC0 of the timer circuit 136. This PTC0 interrupt disable output value is stored in the PTC0 control register by a transfer instruction to write it to the function setting register at the specified address in the function setting register area (step AKS47). The PTC0 control register can set the usage state of the timing function using channel PTC0 of the timer circuit 136. In step AKS47, the PTC0 interrupt disable output value set in step AKS46 is stored in the PTC0 control register, and in response to the power supply to the pachinko game machine 1 being stopped, the timer interrupt for game control is disabled.

[0207] Once the settings corresponding to the elapsed backup judgment time are configured, the system transitions to a standby state by executing a loop process. In this standby state, input port number "3" is input (step AKS48), and it is determined whether the power confirmation signal input bit is "0" or not (step AKS49). If the power confirmation signal is off and the power confirmation signal input bit is "0" (step AKS49; Yes), the loop process returns to step AKS48 and continues. This allows the system to maintain a standby state until the operation stops due to a power outage in response to a power supply interruption in the pachinko game machine 1, thereby preventing undesirable changes to stored data and runaway processing by the CPU 103.

[0208] If the power confirmation signal input bit is "1" and not "0" in response to step AKS49 (step AKS49; No), the power-off recovery vector table address is set to the stack pointer (step AKS50), and then the power-off process P_POWER_OFF is terminated by an interrupt return instruction. The power-off recovery vector table address is the address of the power-off recovery vector table located in the game program area of ​​ROM101. The interrupt return instruction uses the stack pointer as a pointer to set the data stored in the memory area indicated by the value stored in the stack pointer to the program counter. For example, the data stored in the memory area indicated by the value stored in the stack pointer is set to the lower byte of the program counter, and the data stored in the memory area indicated by the value specified by the value obtained by adding 1 to the value stored in the stack pointer is set to the upper byte of the program counter.

[0209] Figure 10-11 illustrates an example of the data configuration used for the power outage processing P_POWER_OFF. In the power outage processing P_POWER_OFF, for example, step AKS38 executes branch processing using the timing value of the backup monitoring timer, and step AKS40 saves checksum data using the checksum buffer. Furthermore, by setting the power outage recovery vector table address in step AKS50, if the pachinko game machine 1 does not stop operating after detecting a power outage and normal power supply is restored, the game control program can be executed from the beginning. In this way, the power outage processing P_POWER_OFF enables control of the pachinko game machine 1 when the power supply is interrupted, using the backup monitoring timer, checksum buffer, and power outage recovery vector table.

[0210] Figure 10-11(A) shows a configuration example AKB01 of a memory area serving as a backup data area. The backup data area of the configuration example AKB01 can store backup setting data used when backing up the stored data in the game work area of the RAM 102. This backup data area includes a backup monitoring timer at address F000[H] and a checksum buffer at address F0DE[H]. Address F000[H] is the start address of the game work area, and address F0DE[H] is the end address of the game work area. By providing the backup data area at the start address and the end address of the game work area in this way, appropriate backup of the stored data in the game work area of the RAM 102 is enabled.

[0211] Figure 10-11(B) shows a configuration example AKT11 of a power-off recovery vector table. The power-off recovery vector table of the configuration example AKT11 can specify the return address from the power-off process in response to an interrupt return instruction when normal power supply resumes. The power-off recovery vector table is configured to include, as table data, lower address specification data 00[H] stored at address 0016[H] in the game program area of the ROM 101 and upper address specification data 00[H] stored at address 0017[H] in the game program area of the ROM 101. In step AKS50 of the power-off process P_POWER_OFF, data indicating address 0016[H] is set in the stack pointer as the power-off recovery vector table address. Thereafter, by setting the stored value of the program counter to 0000[H] with an interrupt return instruction and resuming the process, the main process P_MAIN for game control can be executed from the beginning.

[0212] Figure 10-12 is a flowchart showing an example of the random number update process P_RANDOM. The random number update process P_RANDOM is included in the processes that can be called from the timer interrupt process P_PCT for game control shown in Figure 5, and can be executed in step S56 in response to the occurrence of a periodic timer interrupt due to the elapsed of a predetermined time, such as 4ms. On the other hand, the random number update process P_RANDOM is not included in the processes that can be called from the main process P_MAIN for game control shown in Figure 4, and is not executed in the loop process that is repeated after step S7 until a timer interrupt occurs. Therefore, although the random number update process P_RANDOM is included in the first process that can be executed in response to a timer interrupt due to the elapsed time, it is not included in the second process that can be repeatedly executed until the first process is executed. Furthermore, while the random number update process P_RANDOM can be called and executed in the timer interrupt process P_PCT for game control that controls the progress of the game, it cannot be called and executed in the standby process, which is a loop process that is repeated after the startup process such as the power supply start response process P_POWER_ON in step S1, in the main process P_MAIN for game control that is executed based on the start of power supply in the pachinko game machine 1.

[0213] The random number update process P_RANDOM enables the update of numerical data representing the values of random numbers MR1-2 for the winning symbol and MR2-1 for the normal symbol's winning symbol using internal registers of the CPU 103, such as the B register, DE register, and HL register. The random number MR1-2 for the winning symbol is used for determining the definite special symbol that is the display result of the special symbol in the special symbol variable display in the first special symbol display device 4A or the second special symbol display device 4B, corresponding to the special symbol game. The random number MR2-1 for the normal symbol's winning symbol is used for determining the definite normal symbol that is the display result of the normal symbol in the normal symbol variable display in the normal symbol display 20, corresponding to the normal symbol game. The random number update process P_RANDOM can update the respective random number values using the B register, DE register, and HL register as common internal registers when updating the random number MR1-2 for the winning symbol and when updating the random number MR2-1 for the normal symbol's winning symbol.

[0214] When the CPU 103 executes the random number update process P_RANDOM, the address of the random number counter for the winning symbol is set by a transfer instruction for setting the HL register used as the random number pointer (step AKS61). The address of the random number counter for the winning symbol is the address of the random number counter for the winning symbol provided in the game work area of the RAM 102. The random number pointer can store the address of the random number counter corresponding to the update target random number value, and the update target random number value can be specified by setting the stored value. In step AKS61, by storing the address of the random number counter for the winning symbol in the random number pointer using the LDQ instruction, the random number MR1-2 for the winning symbol can be set as the update target random number value.

[0215] Following step AKS61, a transfer instruction is used to set the B register, which will be used as the maximum random number register, to set the maximum random number corresponding to the maximum random number determination value for the winning symbol (step AKS62). The maximum random number register can store the maximum value that the random number to be updated can take, and the maximum random number can be specified by setting the stored value. In step AKS62, for the random numbers MR1-2 for the winning symbol, the LD instruction is used to store the maximum value included in the update range of the random numbers MR1-2, such as C7[H] corresponding to "199", in the maximum random number register. This makes it possible to set the maximum random number of the random numbers MR1-2 that were used as the random number to be updated in step AKS61.

[0216] Following step AKS62, a transfer instruction is used to set the DE register, which will be used as the initial value pointer, thereby setting the address of the random number initial value data buffer for the winning symbols (step AKS63). The random number initial value data buffer address for the winning symbols is the address of the random number initial value data buffer for the winning symbols located in the game work area of ​​RAM102. The initial value pointer can store the address of the random number initial value data buffer corresponding to the random number to be updated, and the random number initial value can be obtained or changed by setting the stored value. In step AKS63, the LDQ instruction is used to store the address of the random number initial value data buffer for the winning symbols in the initial value pointer, thereby setting the random number initial value to be obtainable and changeable, corresponding to the random numbers MR1-2 which were set as the random numbers to be updated in step AKS61. Subsequently, a subroutine call instruction is used to execute the initial value change random number update process P_RANCP (step AKS64). Step AKS64's initial value change random number update process P_RANCP enables the updating of the random numbers MR1-2 for the winning symbols, which are the random values ​​to be updated, and the change of the initial value of the random numbers, based on the settings made in steps AKS61 to AKS63.

[0217] In step AKS64, after the initial value change random number update process P_RANCP, a transfer instruction is used to set the HL register to be used as a random number pointer, thereby setting the address of the random number counter for normal winning symbols (step AKS65). The address of the random number counter for normal winning symbols is the address of the random number counter for normal winning symbols located in the game work area of ​​RAM102. In step AKS65, the LDQ instruction is used to store the address of the random number counter for normal winning symbols in the random number pointer, thereby setting the random number MR2-1 for normal winning symbols as the random value to be updated.

[0218] Following step AKS65, a transfer instruction is used to set the B register, which will be used as the maximum random number register, to set the maximum random number corresponding to the maximum random number determination value for the winning symbol in normal symbols (step AKS66). In step AKS66, for the random number MR2-1 used for the winning symbol in normal symbols, the LD instruction is used to store the maximum value within the update range of the random number MR2-1, such as C6[H] corresponding to the maximum value "198", in the maximum random number register. This makes it possible to set the maximum random number of the random number MR2-1 that was the random number value to be updated in step AKS65.

[0219] Following step AKS66, a transfer instruction is used to set the DE register to be used as the initial value pointer, thereby setting the address of the random number initial value data buffer for normal winning symbols (step AKS67). The random number initial value data buffer address for normal winning symbols is the address of the random number initial value data buffer for normal winning symbols located in the game work area of ​​RAM102. In step AKS67, the LDQ instruction stores the address of the random number initial value data buffer for normal winning symbols in the initial value pointer, thereby making it possible to obtain and change the initial value of the random number MR2-1, which was set as the random value to be updated in step AKS65. Subsequently, a subroutine call instruction, which is common to step AKS64, is used to execute the initial value change random number update process P_RANCP (step AKS68). Step AKS68's initial value change random number update process P_RANCP enables the updating of the random number MR2-1, which is the random number to be updated for the normal winning symbols, and the change of the initial value of the random number, based on the settings made in steps AKS65 to AKS67.

[0220] Figure 10-13 is a diagram illustrating an example of the data structure used for the random number update process P_RANDOM. In the random number update process P_RANDOM, the initial value change random number update process P_RANCP in step AKS64 is executed using the random number counter for winning symbols, whose address is set in the random number pointer by step AKS61, and the initial random number data buffer for winning symbols, whose address is set in the initial value pointer by step AKS63. Furthermore, in the random number update process P_RANDOM, the initial value change random number update process P_RANCP in step AKS68 is executed using the random number counter for normal winning symbols, whose address is set in the random number pointer by step AKS65, and the initial random number data buffer for normal winning symbols, whose address is set in the initial value pointer by step AKS67. The random number counter for winning symbols is located in the special symbol random number buffer area and can store numerical data corresponding to the random numbers MR1-2 for winning symbols. The random number initial value data buffer for winning symbols is located in the random number data area for winning symbols and can store numerical data corresponding to the random number initial values ​​of random numbers MR1-2. The random number counter for normal winning symbols is located in the random number data area for winning symbols and can store numerical data corresponding to the random number MR2-1 for normal winning symbols. The random number initial value data buffer for normal winning symbols is located in the random number data area for winning symbols and can store numerical data corresponding to the random number initial value of random number MR2-1. In this way, the random number update process P_RANDOM enables software-based updating of random numbers MR1-2 and MR2-1 using the random number initial value data buffer for winning symbols located in the random number data area for winning symbols, the random number counter for normal winning symbols, the random number initial value data buffer for normal winning symbols, and the random number counter for winning symbols located in the special symbol random number buffer area.

[0221] Figure 10-13(A) shows an example configuration of the random number data area for winning symbols, AKB11. The random number data area for winning symbols in example configuration AKB11 includes a random number initial value data buffer for winning symbols at address F050[H], a random number initial value counter for winning symbols at address F051[H], a random number counter for normal winning symbols at address F052[H], a random number initial value data buffer for normal winning symbols at address F053[H], and a random number initial value counter for normal winning symbols at address F054[H]. Of these, the address F050[H] of the random number initial value data buffer for winning symbols is set to the initial value pointer by step AKS63 of the random number update process P_RANDOM, the address F052[H] of the random number counter for normal winning symbols is set to the random number pointer by step AKS65 of the random number update process P_RANDOM, and the address F053[H] of the random number initial value data buffer for normal winning symbols is set to the initial value pointer by step AKS67 of the random number update process P_RANDOM. The random number counter for winning symbols can store numerical data corresponding to the random numbers MR1-3 that become the initial values ​​for winning symbols. The random number counter for normal winning symbols can store numerical data corresponding to the random numbers MR2-2 that become the initial values ​​for normal winning symbols.

[0222] Figure 10-13(B) shows an example configuration AKB12 for the special symbol random number buffer area. The special symbol random number buffer area in example AKB12 includes a random number buffer for special symbol determination at address F07F[H], a random number counter for winning symbols at address F081[H], a random number buffer for selecting the variation pattern type at address F082[H], a random number buffer for variation patterns at address F083[H], and a random number buffer for selecting the losing animation at address F084[H]. Of these, address F081[H] of the random number counter for winning symbols is set to a random number pointer by step AKS61 of the random number update process P_RANDOM. The random number buffer for special symbol determination can store numerical data corresponding to the random number MR1-1 for special symbol determination obtained from the 16-bit random number circuit 104A. The random number buffer for selecting the type of variation pattern can store numerical data corresponding to the random number MR3-3 for selecting the type of variation pattern, obtained from the 8-bit random number circuit 104B. The random number buffer for variation patterns can store numerical data corresponding to the random number MR3-4 for variation patterns, obtained from the 8-bit random number circuit 104B. The random number buffer for selecting the losing animation can store numerical data corresponding to the random number MR3-2 for selecting the losing animation, obtained from the 16-bit random number circuit 104A.

[0223] Figure 10-14 is a flowchart showing an example of the initial value change random number update process P_RANCP. The initial value change random number update process P_RANCP is included in the processes that can be called from the random number update process P_RANDOM shown in Figure 10-12. It can be executed in step AKS64 after setting the random numbers MR1-2 for the winning symbols in steps AKS61 to AKS63, and in step AKS68 after setting the random numbers MR2-1 for the normal symbols and winning symbols in steps AKS65 to AKS67. In this initial value change random number update process P_RANCP, the value of the random number MR1-2 can be updated in step AKS64 using the numerical data corresponding to the random numbers MR1-2 for the winning symbols. In addition, in step AKS68, the initial value change random number update process P_RANCP can be updated using the numerical data corresponding to the random numbers MR2-1 for the normal symbols and winning symbols.

[0224] When CPU103 executes the initial value change random number update process P_RANCP, it first executes a comparison addition instruction (step AKS101). This comparison addition instruction uses the data stored at the address indicated by the value of the HL register, which is a random number pointer, as the value to be updated, and the value of the B register, which is a random number maximum value register, as the comparison judgment value, and can be executed by a single ICPLD instruction, which is the third special transfer instruction. The value of the HL register, which is a random number pointer, indicates the address of the random number counter where the numerical data corresponding to the random number to be updated is stored. The value of the B register, which is a random number maximum value register, indicates the random number maximum value set corresponding to the random number to be updated. If the count value of the random number counter indicating the random number to be updated is less than the value of the random number maximum value register, the count value of the random number counter is updated to be incremented by 1, thereby increasing the random number to be updated by 1. Conversely, if the count value of the random number counter indicating the random number to be updated is greater than or equal to the value of the random number maximum value register, the random number counter is cleared and the count value is initialized to "0", thereby changing the random number to be updated to the random number minimum value. Therefore, the comparison-add instruction in step AKS101 is a single instruction that includes comparing the random number to be updated with the maximum random number value, adding 1 to the random number to be updated if the comparison result is less than the maximum random number value, and changing the random number to be updated to the minimum random number value if the comparison result is greater than or equal to the maximum random number value. In this way, when updating the random number to be updated by the initial value change random number update process P_RANCP, a single comparison-add instruction is executed first. By executing such a single comparison-add instruction first, the occurrence of malfunctions is suppressed and appropriate random number updates become possible.

[0225] In step AKS101, when a compare-add instruction is executed, a transfer instruction is used to load the random number pointed to by the random number pointer (step AKS102). The random number pointer and the initial value pointer are also swapped (step AKS103). Then, the random number loaded in step AKS102 is compared with the random number initial value data buffer pointed to by the initial value pointer (step AKS104). At this time, it is determined whether the compared random number is different from the value stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS105). The value stored in the DE register, which is the initial value pointer, indicates the address of the random number initial value data buffer corresponding to the random number to be updated. Therefore, in step AKS104, after executing the compare-add instruction in step AKS101, the random number to be updated after the comparison-add instruction is compared with the random number initial value.

[0226] If, in response to step AKS105, the random value is different from the value stored in the random initial value data buffer pointed to by the initial value pointer (step AKS105; Yes), the initial value change random number update process P_RANCP terminates. When the comparison addition instruction in step AKS101 is executed, the count value of the random number counter indicating the random value to be updated will indicate the updated random value. Then, if the initial value change random number update process P_RANCP terminates based on the result of the determination in step AKS105, the value stored in the random number counter indicating the updated random value is stored as the current random value. Therefore, in step AKS105, if the updated random value does not match the random initial value, the initial value change random number update process P_RANCP terminates, allowing the updated random value to be stored as the current random value.

[0227] In step AKS105, if the random value is the same as the value stored in the random initial value data buffer pointed to by the initial value pointer (step AKS105; No), the initial random number counter pointed to by adding 1 to the value stored in the initial value pointer is loaded (step AKS106). In the example configuration AKB11 for the winning symbol random number data area shown in Figure 10-13(A), the winning symbol initial random number counter is located at the next address F051[H] after adding 1 to address F050[H], where the winning symbol random initial value data buffer is located. Also, the normal symbol winning symbol initial random number counter is located at the next address F054[H] after adding 1 to address F053[H], where the normal symbol winning symbol random initial value data buffer is located. Therefore, in step AKS106, if the stored value of the initial value pointer points to the address of the initial random number data buffer for winning symbols, the count value of the initial random number counter for winning symbols is read out. Also, in step AKS106, if the stored value of the initial value pointer points to the address of the initial random number data buffer for normal winning symbols, the count value of the initial random number counter for normal winning symbols is read out. In this way, in step AKS106, the count value of the initial random number counter can be read out as the initial random number value.

[0228] In step AKS106, when the initial random number counter is loaded, the count value of the initial random number counter read is stored in the random number counter pointed to by the random number pointer (step AKS107). Since the value stored in the random number pointer indicates the address of the random number counter corresponding to the random number to be updated, step AKS107 allows the count value of the initial random number counter to be stored as the current random number to be updated. Therefore, if the updated random number to be updated matches the initial random number based on the result of the judgment in step AKS105, step AKS107 allows the initial random number read in step AKS106 to be stored as the current random number.

[0229] Following step AKS107, the count value of the initial random number counter read in step AKS106 is stored in the random number initial value data buffer pointed to by the initial value pointer (step AKS108), after which the initial value change random number update process P_RANCP is completed. The value stored in the initial value pointer indicates the address of the random number initial value data buffer corresponding to the random number to be updated, so step AKS108 allows the count value of the initial random number counter to be stored as the new random number initial value. Therefore, if the random number to be updated after the determination result in step AKS105 matches the random number initial value, step AKS107 stores the initial value random number as the current random number, and step AKS108 allows the initial value random number read in step AKS106 to be stored as the new random number initial value. In this way, setting a new random number initial value increases the uncertainty of the random number, and by storing it as the current random number, an increase in data capacity is prevented, enabling appropriate updates of the random number.

[0230] The random number update process P_RANDOM shown in Figure 10-12, after setting the target random number value, maximum random number value, and initial random number value for the winning symbols MR1-2 in steps AKS61 to AKS63, executes the initial value change random number update process P_RANCP in step AKS64. The initial value change random number update process P_RANCP enables the updating of the target random number value and the change of the initial random number value based on the settings for the target random number value, maximum random number value, and initial random number value. The initial value change random number update process P_RANCP in step AKS64 enables the updating of the winning symbols MR1-2, which were set as the target random number value in step AKS61, using the maximum random number value set in step AKS62 and the initial random number value set in step AKS63. Furthermore, the initial value change random number update process P_RANCP in step AKS64 allows the random number initial value to be changed if the value of the random numbers MR1-2 for the winning symbols, which were set as the random values ​​to be updated in step AKS61, matches the initial random value set in step AKS63. In this way, appropriate random value updates become possible by updating the set random values ​​to be updated.

[0231] The random number update process P_RANDOM executes the initial value change random number update process P_RANCP in step AKS68, after setting the target random number value, maximum random number value, and initial random number value for the random number MR2-1 used for normal winning symbols in steps AKS65 to AKS67. The initial value change random number update process P_RANCP in step AKS68 enables the updating of the random number MR2-1 used for normal winning symbols, which was set as the target random number value in step AKS65, using the maximum random number value set in step AKS66 and the initial random number value set in step AKS67. Furthermore, the initial value change random number update process P_RANCP in step AKS68 enables the change of the initial random number value if the value of the random number MR2-1 used as the target random number value in step AKS65 matches the initial random number value set in step AKS67. In this way, appropriate random number updates are possible by updating the set target random number value, etc. Furthermore, updating the set target random number values ​​or changing the initial random number values ​​enables the updating of appropriate random numbers.

[0232] The random number update process P_RANDOM can update the random numbers MR1-2 for winning symbols, which are used to determine the display result of special symbols, through a first update process consisting of steps AKS61-AKS64, and the random numbers MR2-1 for winning symbols, which are used to determine the display result of normal symbols, through a second update process consisting of steps AKS65-AKS68. Steps AKS61-AKS64 update the random numbers MR1-2 for winning symbols as the first random value, and then steps AKS65-AKS68 update the random numbers MR2-1 for winning symbols for normal symbols as the second random value. The confirmed special symbols that result in the display of special symbols correspond to the maximum number of times the big prize slot is opened during a jackpot game. In addition, the confirmed special symbols that result in the display of special symbols may also correspond to whether or not the game is controlled to a probability variation state after the end of the jackpot game state, or to the maximum number of variable display counts that can be executed in the time-saving state after the end of the jackpot game state. In contrast, the confirmed regular symbols, which are the display results of regular symbols, correspond to the opening time and number of times the second major prize slot is opened. Therefore, the display results of special symbols attract more attention from players than the display results of regular symbols. By updating random numbers MR1-2 as the first random value and then updating random numbers MR2-1 as the second random value using the random number update process P_RANDOM, which is a specific update process, the first random value used to determine the display result that attracts the player's attention is updated before the second random value, thereby suppressing the occurrence of malfunctions and enabling appropriate random number updates.

[0233] In the random number update process P_RANDOM, steps AKS61 to AKS64 can update the random number MR1-2 that becomes the first random number value, and steps AKS65 to AKS68 can update the random number MR2-1 that becomes the second random number value. Then, corresponding to the random number MR1-2 that becomes the first random number value, the initial value change random number update process P_RANCP in step AKS64 can be called and executed, and corresponding to the random number MR2-1 that becomes the second random number value, the initial value change random number update process P_RANCP in step AKS68 can be called and executed. Thus, the random number update process P_RANDOM, which is a specific update process, updates the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value by calling the initial value change random number update process P_RANCP that is a common update process corresponding to the first and second random number values, and makes it possible to change their initial values. The initial value change random number update process P_RANCP, which is such a common update process, prevents an increase in program capacity, stably updates the first and second random number values, and enables appropriate random number value updates.

[0234] In the random number update process P_RANDOM, steps AKS61 to AKS64 that enable updating of the random number MR1-2 that becomes the first random number value are the first update process, and steps AKS65 to AKS68 that enable updating of the random number MR2-1 that becomes the second random number value are the second update process. Then, in the first update process, the initial value change random number update process P_RANCP can be called and executed by step AKS64, and in the second update process, the initial value change random number update process P_RANCP can be called and executed by step AKS68. Thus, the random number update process P_RANDOM updates the random number MR1-2 as the first random number value and the random number MR2-1 as the second random number value by calling the initial value change random number update process P_RANCP as a common update process in the first and second update processes, and makes it possible to change their initial values. The initial value change random number update process P_RANCP, which is such a common update process, prevents an increase in program capacity, stably updates the first and second random number values, and enables appropriate random number value updates.

[0235] In the random number update process P_RANDOM, steps AKS61 to AKS64, which enable updating of the first random number MR1-2, constitute the first update process, and steps AKS65 to AKS68, which enable updating of the second random number MR2-1, constitute the second update process. In both the first and second update processes, the HL register, B register, and DE register of the CPU103, which are common internal storage means, are used to enable updating of the first random number MR1-2 and the second random number MR2-1. In this way, the first and second random numbers can be stably updated using common internal storage means, enabling the updating of appropriate random numbers.

[0236] In the random number update process P_RANDOM, before executing the initial value change random number update process P_RANCP in step AKS64, reference information such as the random number counter address for winning symbols, the maximum judgment value for random numbers for winning symbols, and the initial value data buffer address for random numbers for winning symbols are stored in the HL register, B register, and DE register of the CPU 103, which are internal storage means, in steps AKS61 to AKS63. Also, in the random number update process P_RANDOM, before executing the initial value change random number update process P_RANDCP in step AKS68, reference information such as the random number counter address for normal symbols and winning symbols, the maximum judgment value for random numbers for normal symbols and winning symbols, and the initial value data buffer address for normal symbols and winning symbols are stored in the HL register, B register, and DE register of the CPU 103, which are internal storage means, in steps AKS65 to AKS67. The instructions used in step AKS61 to update the random numbers MR1-2, which become the first random value, and the instructions used in step AKS65 to update the random numbers MR2-1, which become the second random value, are common instructions in that they set the HL register of CPU103. Step AKS61 sets the random number counter address for the winning symbol, but step AKS65 sets the random number counter address for the normal symbol winning symbol, so different reference information can be set. The instructions used in step AKS62 to update the random numbers MR1-2, which become the first random value, and the instructions used in step AKS66 to update the random numbers MR2-1, which become the second random value, are common instructions in that they set the B register of CPU103. Step AKS62 sets the maximum random number value corresponding to the maximum random number judgment value for the winning symbol, but step AKS66 sets the maximum random number value corresponding to the maximum random number judgment value for the normal symbol winning symbol, so different reference information can be set.Steps AKS63 and AKS67 both use a common instruction to update the random numbers MR1-2, which become the first random value, and step AKS67 uses a common instruction to update the random numbers MR2-1, which become the second random value. These instructions set the DE register of the CPU 103. Step AKS63 sets the data buffer address for the initial random number value for the winning symbol, while step AKS67 sets the data buffer address for the initial random number value for the normal winning symbol, allowing for the setting of different reference information. Steps AKS61-AKS63 and AKS65-AKS67 use common instructions, such as the LD and LDQ instructions, which are transfer instructions for setting the internal registers of the CPU 103, to set different reference information. Then, steps AKS64 and AKS68 call a common subroutine, P_RANCP, to execute the initial value change random number update process. Thus, in the random number update process P_RANDOM, which is a specific update process, the instructions used to update the first random number MR1-2 and the instructions used to update the second random number MR2-1 are common. By making it possible to update the first random number MR1-2 and the second random number MR2-1 using common instructions, it becomes possible to stably update the first and second random numbers and update the random numbers appropriately.

[0237] The random number update process P_RANDOM enables the updating of the first random number, MR1-2, through steps AKS61-AKS64 (the first update process), and enables the updating of the second random number, MR2-1, through steps AKS65-AKS68 (the second update process). Then, steps AKS64 and AKS68 enable the calling and execution of the initial value change random number update process P_RANCP. As shown in Figure 10-14, the initial value change random number update process P_RANCP first executes a single comparison-add instruction, so that the comparison-add instruction is executed first in both the case of updating the first random number MR1-2 and the case of updating the second random number MR2-1. By executing such a comparison-add instruction first, the occurrence of errors in the first and second random numbers is suppressed, and appropriate random number updates become possible.

[0238] The initial value change random number update process P_RANCP, when executed in step AKS64 of the random number update process P_RANDOM, can update the random numbers MR1-2 for winning symbols, and can change the initial random number values ​​corresponding to the random numbers MR1-2 for winning symbols using the random numbers MR1-3, which are the initial values ​​for winning symbols. Furthermore, when the initial value change random number update process P_RANCP is executed in step AKS68 of the random number update process P_RANDOM, it can update the random numbers MR2-1 for normal winning symbols, and can change the initial random number values ​​corresponding to the random numbers MR2-1 for normal winning symbols using the random numbers MR2-2, which are the initial values ​​for normal winning symbols. Therefore, the random numbers MR1-3, which are the initial values ​​for the winning symbols, are the first initial values ​​used when changing the initial random number values ​​in the random number update process P_RANCP, which is executed in step AKS64 of the random number update process P_RANDOM, in cases where the random number to be updated is the first random number for the winning symbols, MR1-2. The random numbers MR2-2, which are the initial values ​​for the winning symbols in the normal symbols, are the second initial values ​​used when changing the initial random number values ​​in the random number update process P_RANCP, which is executed in step AKS68 of the random number update process P_RANDOM, in cases where the random number to be updated is the second random number for the winning symbols, MR2-1.

[0239] Figure 10-15 is a flowchart showing an example of the random number update process P_TFINIT for determining initial values. The random number update process P_TFINIT for determining initial values ​​is included in the processes that can be called from the main process P_MAIN for game control shown in Figure 4, and can be executed in step S9 of a loop process that is repeated after step S7 until a timer interrupt occurs. Furthermore, the random number update process P_TFINIT for determining initial values ​​is included in the processes that can be called from the timer interrupt process P_PCT for game control shown in Figure 5, and can be executed in step AKS57 in response to the occurrence of a periodic timer interrupt due to the elapsed of a predetermined time, such as 4ms. Therefore, the random number update process P_TFINIT for determining initial values ​​consists of a first process that can be executed in response to a timer interrupt due to the elapsed time, and a second process that can be repeatedly executed until the first process is executed. Furthermore, the random number update process for determining the initial value P_TFINIT can be called and executed in the timer interrupt process P_PCT for game control, which controls the progress of the game. It can also be called and executed in step S9, which is part of the standby process that is repeated as a loop process, after the startup process such as the power supply start response process P_POWER_ON in step S1, in the main process P_MAIN for game control, which is executed based on the start of power supply in the pachinko game machine 1. In this way, the random number update process for determining the initial value P_IFINIT is included in the processes that can be executed in response to periodic timer interrupts, as well as in the processes that can be executed repeatedly at irregular intervals. As a result, the update period and update speed of the random value for the initial value become indeterminate, increasing the uncertainty of the random value for the initial value and enabling appropriate updating of the random value.

[0240] When CPU 103 executes the P_TINIT random number update process for determining the initial value, it sets the address of the initial random number counter for the winning symbol using a transfer instruction to set a pointer (step AKS81). The address of the initial random number counter for the winning symbol is address F051[H], which is assigned to the initial random number counter for the winning symbol in the example configuration AKB11 of the random number data area for the winning symbol shown in Figure 10-13(A). When the pointer is set in this way, the count value of the initial random number counter for the winning symbol can be updated within the update range of "0" to "199" using a comparison and addition instruction (step AKS82). This comparison and addition instruction uses the stored data at the address pointed to by the pointer as the value to be updated, and the immediate value specified by the operand as the comparison judgment value, and can be executed by a single ICPLD instruction, which is the third special transfer instruction. The stored value of the pointer indicates the address of the random number counter where the numerical data corresponding to the initial random value to be updated is stored. The immediate value specified by the operand indicates the maximum value of the initial random number set corresponding to the random number value to be updated. If the count of the random number counter indicating the random number value to be updated is less than the maximum value of the initial random number, the random number counter is updated by adding 1 to its count, thereby increasing the random number value to be updated by 1. Conversely, if the count of the random number counter indicating the random number value to be updated is greater than or equal to the value stored in the maximum value of the initial random number register, the random number counter is cleared and its count is initialized to "0", thereby changing the random number value to be updated to the minimum value of the initial random number. Therefore, the comparison-add instruction in step AKS82 is a single instruction that includes setting the random numbers MR1-3, which will be the initial values ​​for the winning symbols, as random values ​​for the initial values ​​to be updated, comparing the random values ​​for the initial values ​​to be updated with the maximum value for the initial random numbers, adding 1 to the random values ​​for the initial values ​​to be updated if the result of the comparison is less than the maximum value for the initial random numbers, and changing the random values ​​for the initial values ​​to be updated to the minimum value for the initial random numbers if the result of the comparison is greater than or equal to the maximum value for the initial random numbers. Note that the comparison-add instruction is not limited to the ICPLD instruction in which the address of the stored data indicating the value to be updated is specified by a pointer, but can also be the ICPLDQ instruction in which, for example, the upper address is set using the Q register and the lower address is set using the immediate value specified in the first operand of the comparison-add instruction.In this case, the immediate value specified in the second operand of the comparison-add instruction should be set as the comparison judgment value. By updating the random value used for the initial value to be updated using such a comparison-add instruction, the occurrence of malfunctions can be suppressed, and the appropriate updating of the random value becomes possible.

[0241] After step AKS82, a transfer instruction to set a pointer sets the address of the initial random number counter for the winning symbol (step AKS83). The address of the initial random number counter for the winning symbol is address F054[H], which is assigned to the initial random number counter for the winning symbol in the example configuration AKB11 for the winning symbol random number data area shown in Figure 10-13(A). Once the pointer is set in this way, a comparison and addition instruction makes the count value of the initial random number counter for the winning symbol updateable within the update range of "1" to "198" (step AKS84), and the initial value determination random number update process P_TFINIT ends. The comparison and addition instruction in step AKS84 can be the same as the comparison and addition instruction in step AKS82. However, in the comparison-add instruction of step AKS84, the random number MR2-2, which is the initial value for the winning symbol in a normal symbol game, is set as the random value for the initial value to be updated. Therefore, the immediate value specified by the operand indicating the maximum value of the initial random number is set to a different value than that of the comparison-add instruction of step AKS82. Consequently, the comparison-add instruction of step AKS84 is a single instruction that includes setting the random number MR2-2, which is the initial value for the winning symbol in a normal symbol game, as the random value for the initial value to be updated, comparing that random value for the initial value to be updated with the maximum value of the initial random number, adding 1 to the random value for the initial value to be updated if the result of the comparison is less than the maximum value of the initial random number, and changing the random value for the initial value to be updated to the minimum random number if the result of the comparison is greater than or equal to the maximum value of the initial random number. By updating the random value for the initial value to be updated using such a comparison-add instruction, the occurrence of malfunctions can be suppressed, and appropriate random value updates can be made possible.

[0242] The random number update process P_TFINIT for determining initial values ​​updates the random numbers MR1-3, which will be the initial values ​​for the winning symbols, in steps AKS81 and AKS82 as an update to the first random number value for initial values. At the same time, the random number update process P_TFINIT for determining initial values ​​updates the random numbers MR2-2, which will be the initial values ​​for the winning symbols of the normal symbols, in steps AKS83 and AKS84 as an update to the second random number value for initial values. The random numbers MR1-3, which will be the initial values ​​for the winning symbols, are the first random number values ​​used when changing the initial random number value when the random number value to be updated is the first random number value for the winning symbols, MR1-2. The random number value MR2-2, which will be the initial values ​​for the winning symbols of the normal symbols, are the second random number values ​​used when changing the initial random number value when the random number value to be updated is the second random number value for the winning symbols, MR2-1. Then, steps AKS81 and AKS82 of the random number update process P_TFINIT for determining initial values ​​become the first initial value update process, which allows updating the first random number value for the initial value. Steps AKS83 and AKS84 of the random number update process P_TFINIT for determining initial values ​​become the second initial value update process, which allows updating the second random number value for the initial value. By updating the first and second random number values ​​for the initial value in this way, it becomes possible to update the random numbers appropriately so that the uncertainty of the first and second random numbers is reliably increased.

[0243] Furthermore, the random number update process P_TFINIT for determining initial values ​​updates the random numbers MR1-3, which will be the initial values ​​for the winning symbols, as the first random values ​​for initial values ​​in steps AKS81 and AKS82, and then updates the random numbers MR2-2, which will be the initial values ​​for the normal symbols and winning symbols, as the second random values ​​for initial values ​​in steps AKS83 and AKS84. Therefore, the random number update process P_TFINIT for determining initial values ​​updates the random numbers MR1-3, which will be the initial values ​​for the winning symbols, as the first random values ​​for initial values ​​in steps AKS81 and AKS82, which are the first random values ​​for initial values, and then updates the random numbers MR2-1, which will be the initial values ​​for the normal symbols and winning symbols, as the second random values ​​for initial values ​​in steps AKS83 and AKS84.

[0244] Figure 10-16 is a flowchart showing an example of the start gate switch pass-through process P_TZU_ON. The start gate switch pass-through process P_TZU_ON is included in the processes that can be called from the special symbol process process P_TPROC shown in Figure 6, and can be executed in step S104 if the first start prize response flag is on in step S103, and can be executed in step S108 if the second start prize response flag is on in step S107. When the CPU 103 executes the start gate switch pass-through process P_TZU_ON, it sets the start gate prize memory counter address by a transfer instruction to set a pointer (step AKS201). The start gate prize memory counter address is the address of the first start gate prize memory counter or the second start gate prize memory counter provided in the game work area of ​​RAM 102. In step AKS201, different addresses in the game work area can be specified corresponding to the first or second start-up prize table set by the special symbol process P_TPROC. For example, the upper address F0[H] of the game work area, which is the work area, is set to the upper byte of the pointer by a transfer instruction, and the lower address of the start-up prize memory counter stored in the first or second start-up prize table pointed to by the table pointer is set to the lower byte of the pointer by a transfer instruction. As a result, the value indicating the address of the first or second start-up prize memory counter is stored in the internal register of the CPU 103, which is the pointer. Subsequently, the start-up prize memory counter is loaded by a transfer instruction to read the stored data at the address pointed to by the pointer (step AKS202).

[0245] Following step AKS202, it is determined whether the count value of the start gate prize memory counter is greater than or equal to the maximum counter value (step AKS203). For example, a comparison return instruction allows comparison between the value loaded in step AKS202 and the maximum counter value, such as "4". If it is greater than or equal to the maximum counter value (step AKS203; Yes), the start gate switch passage process P_TZU_ON ends and the process returns to the special symbol process P_TPROC. On the other hand, if it is less than the maximum counter value (step AKS203; No), the count value of the start gate prize memory counter is updated to increment by 1 (step AKS204). In this case, an arithmetic logic operation instruction that increments the stored data at the address pointed to by the pointer makes it possible to update the count value of the first start gate prize memory counter or the second start gate prize memory counter by incrementing by 1.

[0246] After step AKS204, the special symbol determination buffer address is set as the transfer destination (step AKS205). The special symbol determination buffer address is the address of the first special symbol determination buffer contained in the first special symbol hold buffer or the second special symbol determination buffer contained in the second special symbol hold buffer, both located in the game work area of ​​RAM102. In step AKS205, different addresses in the game work area can be specified, corresponding to the first start gate entry table or the second start gate entry table set by the special symbol process P_TPROC, and the count value of the first start gate entry counter or the second start gate entry counter loaded in step AKS202.

[0247] The first special symbol hold buffer consists of a first hold memory buffer comprising a first special symbol judgment buffer, a first winning symbol buffer, a first variation pattern type selection buffer, a first variation pattern buffer, and a first losing effect selection buffer. This buffer is secured as multiple memory areas, such as five memory areas corresponding to buffer numbers from "0" to "4", corresponding to the number of first hold memories when the variable display of the first special symbol is being executed and the number of first hold memories that have not yet been executed. The second special symbol hold buffer consists of a second special symbol judgment buffer, a second winning symbol buffer, a second variation pattern type selection buffer, a second variation pattern buffer, and a second losing effect selection buffer. This buffer is secured as multiple memory areas, such as five memory areas corresponding to buffer numbers from "0" to "4", corresponding to the number of second hold memories when the variable display of the second special symbol is being executed and the number of second hold memories that have not yet been executed.

[0248] In step AKS205, the value corresponding to the buffer size of the first and second reserved memory buffers is multiplied by the count value of the start gate entry counter, and this multiplied value is added to the lower address of the first or second reserved memory buffer with buffer number "1". By setting such an added value to the transfer destination pointer, it is sufficient to set the buffer address for special symbol determination as the transfer destination.

[0249] Following step AKS205, the RL0 hard latch random value register address is set (step AKS206). The RL0 hard latch random value register address is the address of the RL0 hard latch random value register located in the function control register area. For example, the upper address FF[H] of the function control register area is set to the upper byte of the pointer by a transfer instruction, and the lower address of the RL0 hard latch random value register stored in the first start-up prize table or the second start-up prize table pointed to by the table pointer is set to the lower byte of the pointer by a transfer instruction. The first start-up prize table stores the lower address of the RL0 hard latch random value register with buffer number "0". The second start-up prize table stores the lower address of the RL0 hard latch random value register with buffer number "1". As a result, different addresses for the first start-up prize and the second start-up prize are stored in the internal register of the CPU 103, which acts as the pointer, as the address of the RL0 hard latch random value register.

[0250] Following step AKS206, a transfer instruction is used to load the RL0 hard latch random number register by reading the stored data at the address pointed to by the pointer (step AK207). The value stored in the RL0 hard latch random number register obtained in this way is stored in the special symbol determination random number buffer by a transfer instruction to write it to the storage area at the specified address in the game work area of ​​RAM102 (step AKS208). In this way, by storing the numerical data obtained from the RL0 hard latch random number register in the special symbol determination random number buffer, numerical data indicating the value of the special symbol determination random number MR1-1 can be extracted, and the value of the random number MR1-1 can be stored in the special symbol determination random number buffer.

[0251] After step AKS208, the RL2 soft latch random value register is loaded by a transfer command to read stored data from the storage area at the specified address in the function control register area (step AKS209). The value stored in the RL2 soft latch random value register obtained at this time is stored in the random number buffer for selecting a losing animation by a transfer command to write it to the storage area at the specified address in the game work area of ​​RAM102 (step AKS210). In this way, by storing the numerical data obtained from the RL2 soft latch random value register in the random number buffer for selecting a losing animation, numerical data indicating the value of the random number MR3-2 for selecting a losing animation can be extracted, and the value of the random number MR3-2 can be stored in the random number buffer for selecting a losing animation.

[0252] After step AKS210, the RS1 soft latch random value register is loaded by a transfer instruction to read stored data from the storage area at the specified address in the function control register area (step AKS211). The value stored in the RS1 soft latch random value register obtained at this time is stored in the random number buffer for variable pattern type selection by a transfer instruction to write it to the storage area at the specified address in the game work area of ​​RAM102 (step AKS212). In this way, by storing the numerical data obtained from the RS1 soft latch random value register in the random number buffer for variable pattern type selection, numerical data indicating the value of the random number MR3-3 for variable pattern type selection can be extracted, and the value of the random number MR3-3 can be stored in the random number buffer for variable pattern type selection.

[0253] Following step AKS212, the RS2 soft latch random value register is loaded by a transfer instruction to read stored data from the storage area at the specified address in the function control register area (step AKS213). The value stored in the RS2 soft latch random value register obtained at this time is stored in the random number buffer for the variation pattern by a transfer instruction to write it to the storage area at the specified address in the game work area of ​​RAM102 (step AKS214). In this way, by storing the numerical data obtained from the RS2 soft latch random value register in the random number buffer for the variation pattern, numerical data indicating the value of the random numbers MR3-4 for the variation pattern can be extracted, and the value of the random numbers MR3-4 can be stored in the random number buffer for the variation pattern.

[0254] Following step AKS214, a block transfer is performed from the random number buffer to the special symbol determination buffer (step AKS215). The random number buffer consists of a special symbol determination random number buffer in which the values ​​of random numbers MR1-1 are stored by step AKS208, a loss animation selection random number buffer in which the values ​​of random numbers MR3-2 are stored by step AKS210, a variation pattern type selection random number buffer in which the values ​​of random numbers MR3-3 are stored by step AKS212, and a variation pattern random number buffer in which the values ​​of random numbers MR3-4 are stored by step AKS214. In step AKS215, the address of the special symbol determination random number buffer is set as the transfer source, and the value corresponding to the buffer size of the random number buffer is set as the transfer count. The address of the special symbol determination buffer, which is the transfer destination, is set by step AKS205. Based on these settings, by executing a block transfer instruction, the values ​​of each random number temporarily stored in the random number buffer can be stored as new reserved information in the first reserved storage buffer or the second reserved storage buffer.

[0255] Step AKS215 stores new memory information, and then it is determined whether the conditions for the winning animation are met (Step AKS216). The conditions for the winning animation only need to be pre-set as conditions that enable the execution of the pre-read animation. For example, if the starting gate winning designation value is "2", it is determined that the conditions for the winning animation are met. Also, if the starting gate winning designation value is "1", and the time-saving function flag is "0" corresponding to not being in a time-saving state, and the special symbol process code is less than 03[H] corresponding to not being in a minor win game state or a major win game state, it is determined that the conditions for the winning animation are met. If it is determined that the conditions for the winning animation are met (Step AKS216; Yes), the winning animation process P_GAME_CHK is executed (Step AKS217). The winning animation process P_GAME_CHK includes a special symbol win determination, selects an animation designation value corresponding to the determination result, and makes it possible to send the winning animation command.

[0256] If, in response to step AKS216, it is determined that the conditions for the winning animation are not met (step AKS216; No), or after the winning animation processing is executed by step AKS217, the animation memory information specification command transmission table address is set by a transfer command to set a pointer (step AKS218). The animation memory information specification command transmission table address is the address of the animation memory information specification command transmission table stored in the game data area of ​​ROM101. Then, by executing the command set process P_COM_SET (step AKS219), the first animation memory information specification command or the second animation memory information specification command can be sent as the starting winning command. The first animation memory information specification command is an animation control command that specifies the first reserved memory number indicated by the count value of the first starting gate winning memory counter. The second animation memory information specification command is an animation control command that specifies the second reserved memory number indicated by the count value of the second starting gate winning memory counter. In this way, the command set process P_COM_SET in step AKS219 allows the main board 11 to send the performance control command, which is the command for when a prize is won, to the performance control board 12.

[0257] Following step AKS219, a transfer instruction to set a pointer sets the address of the start gate prize buffer storage counter (step AKS220). The start gate prize buffer storage counter address is the address of the start gate prize buffer storage counter located in the game work area of ​​RAM102. The count value of the start gate prize buffer storage counter, whose address has been set in this way, is updated by adding 1 (step AKS221). Furthermore, a compound transfer instruction to set registers and pointers is used to update the pointer corresponding to the start gate prize buffer storage counter (step AKS222). For example, the count value of the start gate prize buffer storage counter after the update in step AKS221 is loaded into the internal register of CPU103, and the stored value of the pointer is updated by adding 1, so that a value indicating the starting address of the start gate prize buffer is stored in the pointer. Furthermore, by adding the loaded count value of the start gate prize buffer storage counter to the stored value of the pointer, the storage area of ​​the buffer number to be updated in the start gate prize buffer can be identified.

[0258] Step AKS222 updates the pointer, loading the start gate prize designation value (Step AKS223). The start gate prize designation value corresponds to the first start gate prize table or the second start gate prize table set by the special symbol process P_TPROC, and can be set to "1" indicating a first start gate prize or "2" indicating a second start gate prize. In Step AKS223, the start gate prize designation value is made available by a transfer command to read table data from the first start gate prize table or the second start gate prize table. The thus obtained start gate prize designation value is stored in the start gate prize buffer by a transfer command to write it to the memory area at the address pointed to by the pointer (Step AKS224), and the start gate switch pass-through process P_TZU_ON ends.

[0259] Figure 10-17 is a diagram illustrating an example of the use of the data configuration related to the start gate switch pass-through process P_TZU_ON. In the start gate switch pass-through process P_TZU_ON, various settings and controls are performed using the first start gate prize table set in step S102 of the special symbol process P_TPROC shown in Figure 6, or the second start gate prize table set in step S106. For example, the first start gate prize memory counter and the second start gate prize memory counter, whose count values ​​can be updated by step AKS204, are provided in the special symbol control data area and can store data corresponding to the first and second reserved memory counts. The start gate prize buffer memory counter, whose count values ​​can be updated by AKS221, and the start gate prize buffer, where the start gate prize specified value is stored by AKS224, are provided in the start gate prize buffer area and can store the total number of first and second start gate prizes and their occurrence order. Furthermore, in the command set processing P_COM_SET of step AKS219, the first performance memory information specification command transmission table or the second performance memory information specification command transmission table, whose address was set in step AKS218, is used.

[0260] In this way, the start gate switch pass-through process P_TZU_ON enables control related to the special symbol game, which is a variable display of special symbols, using the first start gate prize table or the second start gate prize table, the first start gate prize memory counter or the second start gate prize memory counter provided in the special symbol control data area, the start gate prize buffer memory counter and start gate prize buffer provided in the start gate prize buffer area, the first performance memory information specification command transmission table or the second performance memory information specification command transmission table.

[0261] Figure 10-17(A1) shows an example configuration of the first start gate prize table AKT21. The first start gate prize table of the example configuration AKT21 is configured to include table data that indicates the lower address of the first start gate prize memory counter, the lower address of the RL0 hard latch random value register number "0", the lower address of the first special symbol determination buffer number "1", the address of the first performance memory information specification command transmission table, and the start gate prize specification value "1".

[0262] The first start slot entry memory counter is located in the game work area of ​​RAM 102 and can store data corresponding to the first reserved memory count. The RL0 hard latch random value register number "0" is the RL0 hard latch random value register of register number "0" located in the function control register area, and can store numerical data indicating the value of the random number MR1-1 for special symbol determination that can be generated by channel RL0 located in the 16-bit random number circuit 104A, by acquiring it via a hard latch. The first special symbol determination buffer number "1" is the first special symbol determination buffer included in the first reserved memory buffer of buffer number "1" in the first special symbol reserved buffer. The first performance memory information specification command transmission table is stored in the game data area of ​​ROM 101 and is used when transmitting the first performance memory information specification command that specifies the first reserved memory count. The start slot entry specification value "1" is a specification value that specifically indicates that the first start slot entry has occurred.

[0263] Figure 10-17(A2) shows an example configuration of the second start gate prize table, AKT22. The second start gate prize table in example configuration AKT22 is configured to include table data that shows the lower address of the second start gate prize memory counter, the lower address of the RL0 hard latch random value register number "1", the lower address of the second special symbol determination buffer number "1", the address of the second performance memory information specification command transmission table, and the start gate prize specification value "2".

[0264] The second start slot entry memory counter is located in the game work area of ​​RAM 102 and can store data corresponding to the second reserved memory count. The RL0 hard latch random value register number "1" is the RL0 hard latch random value register of register number "1" located in the function control register area. For the random number MR1-1 for special symbol determination that can be generated by channel RL0 of the 16-bit random number circuit 104A, numerical data indicating its value can be acquired and stored by the hard latch. The second special symbol determination buffer number "1" is the second special symbol determination buffer included in the second reserved memory buffer of buffer number "1" in the second special symbol reserved buffer. The second performance memory information specification command transmission table is stored in the game data area of ​​ROM 101 and is used when transmitting the second performance memory information specification command that specifies the second reserved memory count. The start slot entry specification value "2" is a specification value that specifically indicates that a second start slot entry has occurred.

[0265] Figure 10-17(B1) shows an example configuration of the special symbol control data area AKB21. The special symbol control data area of ​​example configuration AKB21 can store various data related to control by the special symbol process processing P_TPROC, such as the special symbol game, which is a variable display of special symbols, and the minor win game state and major win game state that can be controlled based on the display results. This special symbol control data area includes a special symbol process timer at address F030[H], a winning flag at address F032[H], a special symbol process code at address F033[H], a first start gate entry memory counter at address F034[H], a big win symbol judgment buffer at address F035[H], a small win symbol judgment buffer at address F036[H], a big prize gate entry count counter at address F037[H], a big prize gate opening count counter at address F038[H], a big prize gate opening pattern timer at address F039[H], a big prize gate opening pattern table pointer at address F03B[H], a demo display flag at address F03D[H], and a second start gate entry memory counter at address F099[H].

[0266] The special symbol process timer can store a timing value corresponding to the control time by the special symbol process P_TPROC. The special symbol process code can specify the process selected in the special symbol process P_TPROC. The first start slot prize memory counter can store a count value corresponding to the first reserved memory count. The jackpot symbol judgment buffer can store data corresponding to the jackpot symbol specification value. The jackpot symbol specification value is a specification value corresponding to the confirmed special symbol displayed when the display result is "jackpot" in the variable display of special symbols, and allows setting the type of jackpot game state. The minor win symbol judgment buffer can store data corresponding to the minor win symbol specification value. The minor win symbol specification value is a specification value corresponding to the confirmed special symbol displayed when the display result is "minor win" in the variable display of special symbols, and allows setting the type of minor win game state. The large prize slot ball entry counter can store a count value corresponding to the number of game balls that have passed through the large prize slot formed by the special variable prize ball entry device 50. The large prize slot opening count counter can store a count value corresponding to the number of times the large prize slot has been opened during minor win game states and major win game states. The large prize slot opening pattern timer can store a timing value corresponding to the remaining time to control the large prize slot to an open state during minor win game states and major win game states. The large prize slot opening pattern table pointer can specify the storage address of the large prize slot opening pattern table in which the opening time of the large prize slot is set. The demo display flag can store a flag value corresponding to an on or off state, depending on whether or not a demonstration display is being executed. The second start slot ball entry memory counter can store a count value corresponding to the second reserved memory count.

[0267] Figure 10-17(B2) shows an example configuration of the starting gate prize buffer area AKB22. The starting gate prize buffer area of ​​example configuration AKB22 can store various data related to the first and second starting gate prizes that occur when a game ball enters the first or second starting gate prize area. This starting gate prize buffer area includes a starting gate prize buffer storage counter at address F0BA[H] and starting gate prize buffer numbers "0" to "8" at addresses F0BB[H] to F0C3[H].

[0268] The start-up entry buffer memory counter can store a count corresponding to the number of valid start-up entry designated values ​​stored in the start-up entry buffer area. Therefore, the count of the start-up entry buffer memory counter indicates the total number of first and second start-up entries. Start-up entry buffer numbers "0" to "8" are start-up entry buffers to which buffer numbers "0" to "8" are assigned, and they can store the start-up entry designated values ​​in the order in which the first and second start-up entries occurred. As a result, the information stored in the start-up entry buffer indicates the order in which the first and second start-up entries occurred.

[0269] Figure 10-17(C1) shows an example configuration AKT23 of the first performance memory information specification command transmission table. The first performance memory information specification command transmission table of example configuration AKT23 is configured to include table data that indicates the upper byte of the first performance memory information specification command and the reference specification value of the first start slot prize memory counter. The command set process P_COM_SET in step AKS219 enables the transmission of the first performance memory information specification command when the first performance memory information specification command transmission table is used. The lower byte of the first performance memory information specification command can be set to correspond to the count value of the first start slot prize memory counter. By transmitting such a first performance memory information specification command, the first reserved memory count can be notified to the performance control board 12.

[0270] Figure 10-17(C2) shows an example configuration AKT24 of the second performance memory information specification command transmission table. The second performance memory information specification command transmission table of example configuration AKT24 is configured to include table data that indicates the upper byte of the second performance memory information specification command and the reference specification value of the second start slot prize memory counter. The command set process P_COM_SET in step AKS219 enables the transmission of the second performance memory information specification command when the second performance memory information specification command transmission table is used. The lower byte of the second performance memory information specification command can be set to correspond to the count value of the second start slot prize memory counter. By transmitting such a second performance memory information specification command, the number of second reserved memories can be notified to the performance control board 12.

[0271] As shown in Figure 10-16, the start gate switch pass-through process P_TZU_ON stores the value stored in the RL2 soft latch random value register loaded in step AKS209 into the random number buffer for selecting the losing animation by step AKS210, thereby enabling the extraction of numerical data representing the value of the random number MR3-2 for selecting the losing animation. Furthermore, the start gate switch pass-through process P_TZU_ON stores the value stored in the RS1 soft latch random value register loaded in step AKS211 into the random number buffer for selecting the variation pattern type by step AKS212, thereby enabling the extraction of numerical data representing the value of the random number MR3-3 for selecting the variation pattern type. In addition, the start gate switch pass-through process P_TZU_ON stores the value stored in the RS2 soft latch random value register loaded in step AKS213 into the random number buffer for the variation pattern by step AKS214, thereby enabling the extraction of numerical data representing the value of the random number MR3-4 for the variation pattern. Here, if we set the random number MR3-2 for selecting the losing animation as the first random number, the random number MR3-3 for selecting the type of variation pattern as the second random number, and the random number MR3-4 for the variation pattern as the third random number, the start gate switch passing process P_TZU_ON is executed in response to the occurrence of a start win. Therefore, the first, second, and third random numbers can be extracted when the common extraction condition of the occurrence of a start win is met. The random number MR3-2 for selecting the losing animation is included in the game random numbers that can be updated by the 16-bit random number circuit 104A, and the random numbers MR3-3 for selecting the type of variation pattern and MR3-4 for the variation pattern are included in the game random numbers that can be updated by the 8-bit random number circuit 104B, and in all cases the total number of random numbers included in the update range is a prime number. Furthermore, while the update rate of random number MR3-2 is 469 [times / ms], the update rates of random number MR3-3 and MR3-4 are 938 [times / ms]. In other words, the update rates of random number MR3-3 and MR3-4 are twice as fast as the update rate of random number MR3-2, which is an integer multiple.The update range for random number MR3-2 is "0" to "65518", the update range for random number MR3-3 is "0" to "240", and the update range for random number MR3-4 is "0" to "250". Therefore, the total number of random values ​​included in each update range is different, and in all cases, the total number of random values ​​included in the update range is a prime number. In this way, when the update speed of the second and third random values ​​is an integer multiple of the update speed of the first random value, the total number of random values ​​included in each update range is different, and in all cases, the total number of random values ​​included in the update range is a prime number. This suppresses the synchronous generation of the first, second, and third random values, enabling appropriate random number updates.

[0272] Figure 10-18 is a flowchart showing an example of the special symbol normal processing P_TNORMAL. The special symbol normal processing P_TNORMAL is included in the processing that can be called from the special symbol process processing P_TPROC shown in Figure 6, and can be executed in step S112 if the special symbol process code loaded in step S110 is 00[H]. When the CPU 103 executes the special symbol normal processing P_TNORMAL, it sets the start gate prize buffer storage counter address by a transfer instruction for setting a pointer (step AKS241). The start gate prize buffer storage counter address is the address of the start gate prize buffer storage counter provided in the game work area of ​​RAM 102. In this way, it is determined whether the count value of the start gate prize buffer storage counter whose address has been set is "0" or not (step AKS242). For example, a jump operation instruction that branches the processing depending on whether the stored data at the address pointed to by the pointer is 00[H] corresponding to "0" allows different processing to be executed depending on whether the count value of the starting gate prize buffer storage counter is "0" or not.

[0273] If the count value of the start-gate prize buffer memory counter is not "0" in response to step AKS242 (step AKS242; No), the count value of the start-gate prize buffer memory counter is updated to be decremented by 1 (step AKS243). Also, a block transfer for shifting the start-gate prize buffer is performed (step AKS244). In step AKS244, the destination address is set to the lower address BB[H] of start-gate prize buffer number "0", the source address is set to the lower address BC[H] of start-gate prize buffer number "1", and the number of transfers is set to "8", which is the buffer size of the start-gate prize buffer. After that, by executing the block transfer instruction, the contents stored in the start-gate prize buffer are transferred one unit at a time to the previous buffer and shifted. Then, the memory area of ​​start-gate prize buffer number "8" is initialized by clearing it.

[0274] Following step AKS244, a transfer instruction to set the table pointer sets the address of the second special symbol determination control table (step AKS245). The address of the second special symbol determination control table is the address of the second special symbol determination control table stored in the game data area of ​​ROM101. At this time, the start-up entry check process is executed to determine whether the start-up entry specified value is "1" or not (step AKS246). For example, in the start-up entry check process, the zero flag is turned on when the start-up entry specified value is "1", and the zero flag is turned off when the start-up entry specified value is "2". After such a start-up entry check process is executed, a jump instruction is used to branch the process depending on whether the zero flag is off or not, making it possible to execute different processing depending on whether the start-up entry specified value is "1" or "2".

[0275] In step AKS246, if the starting slot prize entry designation value is "1" (step AKS246; Yes), the first special symbol judgment control table address is set by a transfer command to set the table pointer (step AKS247). The first special symbol judgment control table address is the address of the first special symbol judgment control table stored in the game data area of ​​ROM 101. In step AKS247, the value of the table pointer is overwritten by a transfer command to set the table pointer. Thus, in the special symbol normal processing P_TNORMAL, after setting the second special symbol judgment control table address in step AKS245, in step AKS246, if the starting slot prize entry designation value is "1", the first special symbol judgment control table address is reset by overwriting in step AKS247. This reduces the program capacity required for table setting when the usage frequency of the second special symbol judgment control table is higher than that of the first special symbol judgment control table, thereby improving the marketability of the pachinko game machine 1. Furthermore, if the usage frequency of the second special symbol judgment control table is higher than that of the first special symbol judgment control table, the processing using jump instructions as branch instructions can be simplified, making it easier to verify during the design phase and improving the marketability of the pachinko game machine 1.

[0276] If the starting gate prize entry specified value is "2" and not "1" in response to step AKS246 (step AKS246; No), or after step AKS247, the special symbol judgment process P_TDECISION is executed (step AKS248), the variation pattern setting process P_TPATSET is executed (step AKS249), and then the special symbol normal processing ends.

[0277] If the count value of the start-up entry buffer memory counter is "0" in response to step AKS242 (step AKS242; Yes), it is determined whether the demo display flag is on or off (step AKS250). The demo display flag is a flag that indicates that a demonstration display is being executed. If the demo display flag is on (step AKS250; Yes), the normal processing of the special symbols ends. On the other hand, if the demo display flag is off (step AKS250; No), a transfer command to set the demo display flag stores 01[H], which is the value specified during demo display, into the demo display flag (step AKS251). This sets the demo display flag to the on state. Also, a transfer command to set the pointer sets the standby command transmission table address (step AKS252). The standby command transmission table address is the address of the standby command transmission table stored in the game data area of ​​ROM101. Then, the command set process P_COM_SET is executed (step AKS253), and the normal processing of special symbols ends.

[0278] Figure 10-19 is a diagram illustrating an example of the data structure used for the special symbol normal processing P_TNORMAL. In the special symbol normal processing P_TNORMAL, the special symbol determination processing in step AKS248 is executed using the second special symbol determination control table, whose address is set in step AKS245, or the first special symbol determination control table, whose address is set in step AKS247. In addition, the command set processing P_COM_SET in step AKS253 uses the standby command transmission table, whose address is set in step AKS252. In this way, the special symbol normal processing P_TNORMAL enables control over the special symbol game, which is a variable display of special symbols, using the first special symbol determination control table or the second special symbol determination control table and the standby command transmission table.

[0279] Figure 10-19(A1) shows an example configuration AKT31 of the first special symbol determination control table. The first special symbol determination control table of example configuration AKT31 is configured to include table data that indicates the address of the first special symbol buffer shift control table, the lower address of buffer number "0" for first special symbol determination, the lower address of buffer number "0" for first winning symbol, the lower address of the first special symbol buffer, and the address of the work setting table after first special symbol win determination. The first special symbol buffer shift control table is stored in the game data area of ​​ROM101 and is used when shifting the contents of the first special symbol hold buffer. Buffer number "0" for first special symbol determination is the first special symbol determination buffer included in the first hold storage buffer of buffer number "0" in the first special symbol hold buffer. The buffer number "0" for the first winning symbol is the buffer for the first winning symbol included in the first reserve storage buffer of buffer number "0" in the first special symbol reserve buffer. The first special symbol buffer is provided in the game work area of ​​RAM 102 and can store special symbol pattern specification values ​​corresponding to the confirmed special symbols that are stopped and displayed in the first special symbol game by the first special symbol display device 4A. The work setting table after the first special symbol win determination is stored in the game data area of ​​ROM 101 and is used when initializing the data in response to the end of the special symbol determination process P_TDECISION.

[0280] Figure 10-19(A2) shows an example configuration of the second special symbol determination control table AKT32. The second special symbol determ...

Claims

[Claim 1] A gaming machine that displays identification information in a variable manner and can be controlled to create a favorable state for the player, It is possible to perform variable display of specific identification information based on multiple types of variable display patterns, including a predetermined variable display pattern. In a performance mode that includes a first performance mode and a second performance mode, it is possible to switch between and display multiple types of background images, including a first background image and a second background image. In the first performance mode, when switching the background image from a first background image corresponding to the first performance mode to a second background image corresponding to the first performance mode, it is possible to perform a background fade-out display by gradually increasing the transparency of the first background image corresponding to the first performance mode, and a background fade-in display by gradually decreasing the transparency of the second background image corresponding to the first performance mode. In the first performance mode, when the variable display of the identification information corresponding to the first performance mode is started, it is possible to perform an identification information fade-out display in which the transparency of the identification information corresponding to the first performance mode is gradually increased from a first value to a second value that is higher than the first value. In the first performance mode, when the variable display of the identification information corresponding to the first performance mode ends, it is possible to perform an identification information fade-in display in which the transparency of the identification information corresponding to the first performance mode is gradually reduced from the second value to the first value. In the second performance mode, when switching the background image from the first background image corresponding to the second performance mode to the second background image corresponding to the second performance mode, it is possible to perform a background fade-out display in which the transparency of the first background image corresponding to the second performance mode is gradually increased, and a background fade-in display in which the transparency of the second background image corresponding to the second performance mode is gradually decreased. In the second performance mode, when the variable display of the identification information corresponding to the second performance mode is started, it is possible to perform an identification information fade-out display in which the transparency of the identification information corresponding to the second performance mode is gradually increased from the first value to the second value. In the second performance mode, when the variable display of the identification information corresponding to the second performance mode ends, it is possible to perform an identification information fade-in display in which the transparency of the identification information corresponding to the second performance mode is gradually reduced from the second value to the first value. In the first performance mode, the duration of the execution period for the identification information fade-in display is shorter than the duration of the execution period for the background fade-in display. In the second performance mode, the duration of the execution period for the identification information fade-in display is shorter than the duration of the execution period for the background fade-in display. In the first performance mode, the duration of the execution period for the identification information fade-out display is shorter than the duration of the execution period for the background fade-out display. In the second performance mode, the duration of the execution period for the identification information fade-out display is shorter than the duration of the execution period for the background fade-out display. When specific identification information is displayed variably in the predetermined variable display pattern, the fade-out display of the identification information in the first performance mode can be performed over the first execution period. When specific identification information is displayed in a variable manner using the predetermined variable display pattern, the fade-out display of the identification information in the second performance mode can be performed over a second execution period different from the first execution period. For pending displays corresponding to variable displays that have not yet been started, it is possible to update the display up to a predetermined number of times. The aforementioned identification information includes a character representation, As a variable display of the aforementioned identification information, a scroll action and a pre-start action in which the character display operates before the start of the scroll action can be executed. The aforementioned pre-start action is performed after the pending display is updated. A gaming machine characterized by the following features.

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