Indication device

Abstract

To provide a display device.SOLUTION: The display device includes a first light emission layer including a first host in an optical area where low-resolution pixels are disposed, and a second light emission layer including a second host different from the first host. The display device is capable of reducing a difference in luminance between an area where the low-resolution pixels are disposed and an area where high-resolution pixels are disposed.SELECTED DRAWING: Figure 7a

Description

[Technical Field]

[0001] The embodiments of this disclosure relate to display devices. [Background technology]

[0002] Technological advancements allow display devices to offer not only image display capabilities but also functions such as image capture and various sensing capabilities.

[0003] For this purpose, the display device must be equipped with optical electronic devices (also referred to as light receiving devices or sensors), such as a camera and a sensing sensor.

[0004] Since optical electronic devices must receive light from the front of the display device, they must be installed in a location where light reception is advantageous.

[0005] Therefore, conventionally, the only way to install the display device was to expose the camera (camera lens) and the sensing sensor on the front.

[0006] This results in either a wider bezel for the display panel, or a notch or physical hole being formed in the display area of ​​the display panel where a camera or sensing sensor is installed.

[0007] Therefore, even when a display device is equipped with optical electronic devices such as a camera or sensing sensor that receive and detect light from the front, it may be required to have high transmittance in order to perform its intended function. [Overview of the project] [Problems that the invention aims to solve]

[0008] To realize a full-screen display, a proposed solution involves creating an area within the display panel screen where low-resolution pixels are arranged, and positioning a camera and / or various sensors below the display panel, opposite the area with low-resolution pixels.

[0009] However, pixels are also placed in areas where low-resolution pixels are located, reducing the light-emitting area. Therefore, to maintain the same brightness, it may be necessary to use 1.5 times or more of the current required to drive the low-resolution pixels.

[0010] An increase in the amount of current required can reduce the lifespan of pixels. Over time, a large difference in brightness develops between areas with low-resolution pixels and areas with high-resolution pixels, resulting in the problem of the boundary of the low-resolution pixel area becoming clearly visible.

[0011] To address this problem, the inventors of this specification have invented a display device that can increase the lifespan only in the area where low-resolution pixels are located, thereby reducing the brightness difference between the area where low-resolution pixels are located and the area where high-resolution pixels are located, even during long-term operation.

[0012] The embodiments of this disclosure can provide a display device that can reduce the difference in brightness between areas where low-resolution pixels are located and areas where high-resolution pixels are located. [Means for solving the problem]

[0013] Embodiments of the present disclosure can provide a display device comprising: a substrate including a general region having a first resolution in which a plurality of first pixels are arranged and an optical region having a second resolution smaller than the first resolution in which a plurality of second pixels are arranged; a first electrode layer located on the substrate; a first light-emitting layer located on the first electrode layer and including a first host in the general region and the optical region; a second light-emitting layer located on the first light-emitting layer and including a first host in the general region and a second host different from the first host in the optical region; and a second electrode layer located on the second light-emitting layer.

[0014] Embodiments of the present disclosure include a general area where a plurality of first sub-pixels are arranged and an optical area where a plurality of second sub-pixels are arranged. The number of second sub-pixels per unit area in the optical area is less than the number of first sub-pixels per unit area in the general area. Each of the first sub-pixels in the general area and the second sub-pixels in the optical area includes a light-emitting element. The light-emitting element includes a first electrode layer on a substrate, one or more stacks, and a second electrode layer on the one or more stacks. Each of the one or more stacks is located on the first electrode layer. A display device can be provided that includes a first light-emitting layer including a first host in both the general area and the optical area and a second light-emitting layer located on the first light-emitting layer, the second light-emitting layer including a first host in the general area and a second host different from the first host in the optical area.

[0015] According to embodiments of the present disclosure, a display device capable of reducing the luminance difference between an area where low-resolution pixels are arranged and an area where high-resolution pixels are arranged and enabling low-power driving can be provided.

Brief Description of the Drawings

[0016] [Figure 1] It is a plan view of a display device according to an embodiment of the present specification. [Figure 2] It is a system configuration diagram of a display device according to an embodiment of the present specification. [Figure 3] It is an equivalent circuit of sub-pixels in a display panel according to an embodiment of the present specification. [[ID=第十九]] [Figure 4] It is an arrangement diagram of sub-pixels in three types of areas included in the display area of a display device according to an embodiment of the present specification. [Figure 5] It is a cross-sectional view of a light-emitting element included in a display device according to an embodiment of the present specification. [Figure 6] Similarly, it is a cross-sectional view of a light-emitting element included in a display device according to an embodiment of the present specification. [Figure 7a] It is a cross-sectional view of light-emitting elements located in the general area and the optical area of a display device according to an embodiment of the present specification. [Figure 7b] It is a cross-sectional view of light-emitting elements located in the general area and the optical area of a display device according to an embodiment of the present specification. [Figure 8a] This figure shows the triple-state energy levels of the light-emitting elements according to the embodiments described herein. [Figure 8b] This figure shows the triple-state energy levels of the light-emitting elements according to the embodiments described herein. [Figure 8c] This figure shows the triple-state energy levels of the light-emitting elements according to the embodiments described herein. [Figure 9a] This graph shows the manufacturing evaluation results for a light-emitting element according to one embodiment of this specification. [Figure 9b] This graph shows the manufacturing evaluation results for a light-emitting element according to one embodiment of this specification. [Figure 9c] This graph shows the manufacturing evaluation results for a light-emitting element according to one embodiment of this specification. [Figure 9d] This graph shows the manufacturing evaluation results for a light-emitting element according to one embodiment of this specification. [Figure 10a] This graph shows the manufacturing evaluation results for light-emitting elements of other embodiments of this specification. [Figure 10b] This graph shows the manufacturing evaluation results for light-emitting elements of other embodiments of this specification. [Figure 10c] This graph shows the manufacturing evaluation results for light-emitting elements of other embodiments of this specification. [Figure 10d] This graph shows the manufacturing evaluation results for light-emitting elements of other embodiments of this specification. [Modes for carrying out the invention]

[0017] Hereinafter, some embodiments of this embodiment will be described in detail with reference to illustrative drawings. When assigning reference numerals to the components in each drawing, identical components may have the same numeral whenever possible, even if they appear in other drawings. Furthermore, when describing this embodiment, if it is determined that a specific description of a related known configuration or function would obscure the gist of this embodiment, such detailed description may be omitted. Where “includes,” “has,” “is made,” etc., as mentioned herein, other parts may be added unless “only” is used. When a component is expressed singly, it may include multiple components unless otherwise explicitly stated.

[0018] Furthermore, in describing the components of this embodiment, terms such as first, second, A, B, (a), (b), etc., can be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the component in question.

[0019] In descriptions of the positional relationships of constituent elements, when it is stated that two or more constituent elements are “linked,” “joined,” or “connected,” it should be understood that while two or more constituent elements can be directly “linked,” “joined,” or “connected,” they can also be “linked,” “joined,” or “connected” through the “intermediation” of other constituent elements. Here, other constituent elements can also be included in one or more of the two or more constituent elements that are “linked,” “joined,” or “connected” to each other.

[0020] In descriptions of temporal relationships related to constituent elements, methods of operation, or methods of production, if the temporal sequence or flow sequence is described using phrases such as "after," "following," "next," or "before," it can include cases that are not continuous unless "immediately" or "directly" is used.

[0021] On the other hand, if numerical values ​​or corresponding information (e.g., levels) for a component are mentioned, even without further explicit mention, these numerical values ​​or corresponding information may be interpreted to include a range of errors that can occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0022] Various embodiments of this disclosure will be described in detail below with reference to the attached drawings.

[0023] Figure 1 is a plan view of a display device 100 according to an embodiment of this specification.

[0024] Referring to Figure 1, the display device 100 according to the embodiments of this specification may include a display panel 110 for displaying images and one or more optical electronic devices 11, 12.

[0025] The display panel 110 may include a display area (DA) where video is displayed and a non-display area (NDA) where video is not displayed.

[0026] The display area (DA) can accommodate multiple subpixels, and various signal lines for driving these subpixels can be arranged within it.

[0027] The Non-Disclosure Area (NDA) may be an area outside the Display Area (DA).

[0028] Various signal lines can be placed in the non-display area (NDA), and various drive circuits can be connected to it.

[0029] Non-Disclosure Areas (NDAs) may be bent out of view or hidden by a case (not shown).

[0030] The non-display area (NDA) is also called the bezel or bezel area.

[0031] Referring to Figure 1, in the display device 100 according to the embodiment of this specification, one or more optical electronic devices 11, 12 are electronic components located below the display panel 110 (on the opposite side of the viewing surface).

[0032] Light can enter the front (viewing surface) of the display panel 110, pass through the display panel 110, and be transmitted to one or more optical electronic devices 11, 12 located below the display panel 110 (opposite the viewing surface).

[0033] One or more optical electronic devices 11, 12 may be devices that receive light transmitted through the display panel 110 and perform a function determined by the received light.

[0034] For example, one or more optical electronic devices 11, 12 may include one or more imaging devices such as cameras (image sensors), proximity sensors, and illuminance sensors.

[0035] Here, the illuminance sensor may be an ambient light sensor, but is not limited to this.

[0036] With the display device 100 turned off, the illuminance sensor can be used to detect ambient light around the display device 100, and the brightness of the screen output through the display panel 110 can be adjusted according to the brightness of the ambient light.

[0037] Referring to Figure 1, in the display device 100 according to the embodiment of this specification, the display area (DA) may include a general area (NA) and one or more optical areas (OA1, OA2).

[0038] Referring to Figure 1, one or more optical regions (OA1, OA2) can be regions superimposed on one or more optical electronic devices 11, 12.

[0039] As illustrated in Figure 1, the display area (DA) may include a general area (NA), a first optical area (OA1), and a second optical area (OA2).

[0040] In the example shown in Figure 1, a general region (NA) exists between the first optical region (OA1) and the second optical region (OA2).

[0041] Figure 1 shows a structure in which the optical regions (OA1, OA2) are circular, but the shape of the optical regions (OA1, OA2) in the embodiments of this specification is not limited to this.

[0042] The first optical region (OA1) can have a variety of patterns, such as circular, oval, square, hexagonal, or octagonal.

[0043] The second optical region (OA2) can have a variety of patterns, such as circular, oval, square, hexagonal, or octagonal.

[0044] The first optical region (OA1) and the second optical region (OA2) may have the same pattern or may have different patterns.

[0045] For the sake of explanation, the following explanation will use the example that the first optical region (OA1) and the second optical region (OA2) are both circular.

[0046] Here, at least a portion of the first optical region (OA1) can be superimposed with the first optical electronic device 11, and at least a portion of the second optical region (OA2) can be superimposed with the second optical electronic device 12.

[0047] One or more optical regions (OA1, OA2) must have both an image display structure and a light transmission structure formed within them.

[0048] In other words, since one or more optical regions (OA1, OA2) are part of the display region (DA), subpixels for image display must be placed in one or more optical regions (OA1, OA2).

[0049] Furthermore, one or more optical regions (OA1, OA2) must have a light-transmitting structure formed in them that allows light to pass through one or more optical electronic devices 11, 12.

[0050] One or more optical electronic devices 11, 12 are devices that require light reception, but are located behind (below, opposite the viewing surface) the display panel 110 and receive light that has passed through the display panel 110.

[0051] One or more optical electronic devices 11, 12 are not exposed on the front (viewing surface) of the display panel 110.

[0052] Therefore, when the user looks at the front of the display panel 110, the optical electronic devices 11 and 12 are not visible to the user.

[0053] For example, the first optical electronic device 11 can be a camera, and the second optical electronic device 12 can be a sensing sensor such as a proximity sensor or an illuminance sensor.

[0054] For example, the sensing sensor could be an infrared sensor that detects infrared light.

[0055] Conversely, the first optical electronic device 11 can be a sensing sensor, and the second optical electronic device 12 can be a camera.

[0056] In the following explanation, for the sake of clarity, we will use an example where the first optical electronic device 11 is a camera and the second optical electronic device 12 is a sensing sensor.

[0057] Here, the camera can be either a camera lens or an image sensor.

[0058] If the first optical electronic device 11 is a camera, this camera is located behind (below) the display panel 110, but it may be a front camera that captures images in the direction of the front of the display panel 110.

[0059] Therefore, the user can take pictures through a camera that is not visible on the viewing surface of the display panel 110 while looking at the viewing surface.

[0060] The general area (NA) and one or more optical areas (OA1, OA2) included in the display area (DA) are areas where images can be displayed. However, the general area (NA) is an area where a light-transmitting structure does not need to be formed, while one or more optical areas (OA1, OA2) are areas where a light-transmitting structure must be formed.

[0061] Therefore, one or more optical regions (OA1, OA2) must have a transmittance of a certain level or higher, while the general region (NA) may have no light transmittance or a low transmittance below a certain level.

[0062] For example, one or more optical regions (OA1, OA2) and a general region (NA) may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure.

[0063] For example, the number of subpixels per unit area in one or more optical regions (OA1, OA2) may be smaller than the number of subpixels per unit area in the general region (NA).

[0064] In other words, the resolution of one or more optical regions (OA1, OA2) may be lower than the resolution of the general region (NA).

[0065] Here, the number of subpixels per unit area is a unit for measuring resolution, and can also be called PPI (Pixels Per Inch), which means the number of pixels within one inch.

[0066] For example, the number of subpixels per unit area in the first optical region (OA1) may be smaller than the number of subpixels per unit area in the general region (NA).

[0067] The number of subpixels per unit area in the second optical region (OA2) may be greater than or equal to the number of subpixels per unit area in the first optical region (OA1).

[0068] In the display device 100 according to the embodiments of this specification, if the first optical electronic device 11, which is not exposed to the outside and is hidden at the bottom of the display panel 110, is a camera, then the display device 100 according to the embodiments of this specification can be described as a display to which UDC (Under Display Camera) technology is applied.

[0069] According to this, in the case of the display device 100 according to the embodiment of this specification, a notch or camera hole for camera exposure does not need to be formed in the display panel 110, and therefore no reduction in the area of ​​the display area (DA) occurs.

[0070] This eliminates the need for a notch or camera hole to be formed on the display panel 110 for camera exposure, which can reduce the size of the bezel area and eliminate design constraints, thus increasing the freedom of design.

[0071] In the display device 100 according to the embodiments of this specification, one or more optical electronic devices 11, 12 are positioned hidden behind the display panel 110, yet one or more optical electronic devices 11, 12 must be able to receive light normally and perform their predetermined functions normally.

[0072] Furthermore, in the display device 100 according to the embodiments of this specification, even though one or more optical electronic devices 11, 12 are positioned hidden behind the display panel 110 and superimposed on the display area (DA), it must be possible to display a normal image in one or more optical areas (OA1, OA2) that are superimposed on the display area (DA) with the one or more optical electronic devices 11, 12.

[0073] Figure 2 is a system configuration diagram of the display device 100 according to an embodiment of this specification.

[0074] Referring to Figure 2, the display device 100 can include a display panel 110 and a display driver circuit as components for displaying images.

[0075] The display driving circuit may include a data driving circuit 220, a gate driving circuit 230, and a display controller 240, as circuits for driving the display panel 110.

[0076] The display panel 110 may include a display area (DA) where video is displayed and a non-display area (NDA) where video is not displayed.

[0077] The non-display area (NDA) can be the outer boundary of the display area (DA), and can also be called the bezel area.

[0078] The entire or a portion of the non-display area (NDA) may be an area visible from the front of the display device 100, or it may be an area that is bent and not visible from the front of the display device 100.

[0079] The display panel 110 may include a substrate (SUB) and a plurality of subpixels (SP) arranged on the substrate (SUB).

[0080] Furthermore, the display panel 110 may include various types of signal lines to drive multiple subpixels (SPs).

[0081] The display device 100 in the embodiments of this specification may be a liquid crystal display device, and the display panel 110 may be a self-illuminating display device that emits light on its own.

[0082] If the display device 100 according to the embodiments herein is a self-emitting display device, each of the multiple subpixels (SPs) may include a light-emitting element.

[0083] For example, the display device 100 according to the embodiments of this specification may be an organic light-emitting display device in which the light-emitting element is an organic light-emitting diode (OLED).

[0084] In another example, the display device 100 according to the embodiments herein may be an inorganic light-emitting display device in which the light-emitting element is embodied by a light-emitting diode on an inorganic substrate.

[0085] In another example, the display device 100 according to the embodiments of this specification may be a quantum dot display device in which the light-emitting element is a quantum dot, which is a semiconductor crystal that emits light itself.

[0086] The structure of each of the multiple subpixels (SPs) may vary depending on the type of display device 100.

[0087] For example, if the display device 100 is a self-emissive display device in which subpixels (SPs) emit light themselves, each subpixel (SP) may include a light-emitting element that emits light itself, one or more transistors, and one or more capacitors.

[0088] For example, various types of signal lines may include multiple data lines (DL) that transmit data signals (also called data voltages or video signals) and multiple gate lines (GL) that transmit gate signals (also called scan signals).

[0089] Multiple data lines (DLs) and multiple gate lines (GLs) can intersect with each other.

[0090] Multiple data lines (DLs) can be arranged while each extends in the first direction.

[0091] Each of the multiple gate lines (GLs) can be positioned while extending in a second direction.

[0092] Here, the first direction may be the column direction, and the second direction may be the row direction.

[0093] Alternatively, the first direction may be the row direction, and the second direction may be the column direction.

[0094] The data drive circuit 220 is a circuit for driving multiple data lines (DLs) and can output data signals to multiple data lines (DLs).

[0095] The gate drive circuit 230 is a circuit for driving multiple gate lines (GL) and can output gate signals to multiple gate lines (GL).

[0096] The display controller 240 is a device for controlling the data drive circuit 220 and the gate drive circuit 230, and can control the drive timing for multiple data lines (DL) and multiple gate lines (GL).

[0097] The display controller 240 can supply a data drive control signal (DCS) to the data drive circuit 220 to control the data drive circuit 220, and can supply a gate drive control signal (GCS) to the gate drive circuit 230 to control the gate drive circuit 230.

[0098] The display controller 240 receives input video data from the host system 250 and can supply video data (Data) to the data drive circuit 220 based on the input video data.

[0099] The data drive circuit 220 can supply data signals to multiple data lines (DLs) by controlling the drive timing of the display controller 240.

[0100] The data drive circuit 220 receives digital video data (Data) from the display controller 240, converts the received video data (Data) into analog data signals, and outputs them to multiple data lines (DL).

[0101] The gate drive circuit 230 can supply gate signals to multiple gate lines (GL) through timing control by the display controller 240.

[0102] The gate drive circuit 230 receives various gate drive control signals (GCS) along with a first gate voltage corresponding to the turn-on level voltage and a second gate voltage corresponding to the turn-off level voltage, generates a gate signal, and can supply the generated gate signal to multiple gate lines (GL).

[0103] For example, the data drive circuit 220 can be connected to the display panel 110 by tape-automated bonding (TAB), or connected to the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) methods, or implemented by chip-on-film (COF) methods and connected to the display panel 110.

[0104] The gate drive circuit 230 can be connected to the display panel 110 by tape automatic bonding (TAB), or to the bonding pad of the display panel 110 by chip-on-glass (COG) or chip-on-panel (COP) method, or to the display panel 110 according to the chip-on-film (COF) method.

[0105] Alternatively, the gate drive circuit 230 can be a gate-in-panel (GIP) type and be formed in the non-display area (NDA) of the display panel 110.

[0106] The gate drive circuit 230 can be placed on the substrate or connected to the substrate.

[0107] In other words, the gate drive circuit 230 can be placed in the non-display area (NDA) of the substrate in the case of a GIP type.

[0108] The gate drive circuit 230 can be connected to the substrate in the case of chip-on-glass (COG) type, chip-on-film (COF) type, etc.

[0109] On the other hand, at least one of the data drive circuit 220 and gate drive circuit 230 can also be placed in the display area (DA) of the display panel 110.

[0110] For example, at least one of the data drive circuit 220 and the gate drive circuit 230 can be arranged so as not to overlap with the subpixel (SP), or it can be arranged so that it partially or entirely overlaps with the subpixel (SP).

[0111] The data drive circuit 220 can also be connected to one side of the display panel 110 (for example, the top or bottom side).

[0112] Depending on the drive method and panel design, the data drive circuit 220 may be connected to both sides of the display panel 110 (for example, the top and bottom sides), or it may be connected to two or more of the four sides of the display panel 110.

[0113] The gate drive circuit 230 can also be connected to one side of the display panel 110 (for example, the left or right side).

[0114] Depending on the drive method, panel design method, etc., the gate drive circuit 230 may be connected to both sides of the display panel 110 (for example, the left and right sides), or it may be connected to two or more of the four sides of the display panel 110.

[0115] The display controller 240 can be implemented as a separate component from the data drive circuit 220, or it can be implemented as an integrated circuit by being integrated with the data drive circuit 220.

[0116] The display controller 240 may be a timing controller used in conventional display technology, or a control device that includes a timing controller and can also perform other control functions, or it may be a timing controller and other control devices, or it may be a circuit within a control device.

[0117] The display controller 240 can be implemented using a variety of circuits and electronic components, such as ICs (Integrated Circuits), FPGAs (Field Programmable Gate Arrays), ASICs (Application Specific Integrated Circuits), or processors.

[0118] The display controller 240 can be mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to the data drive circuit 220 and the gate drive circuit 230 through the printed circuit board, flexible printed circuit, etc.

[0119] The display controller 240 can send and receive signals with the data drive circuit 220 via one or more predetermined interfaces.

[0120] For example, the interface can include LVDS (Low Voltage Differential Signaling) interface, EPI interface, SP (Serial Peripheral) interface, etc.

[0121] The display device 100 according to the embodiments of this specification may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or pen, or to detect the touch position, in order to further provide a touch sensing function in addition to the video display function.

[0122] The touch sensing circuit may include a touch drive circuit 260 that drives a touch sensor to sense and generate and output touch sensing data, and a touch controller 270 that can use the touch sensing data to detect a touch or to detect the touch position.

[0123] A touch sensor can include multiple touch electrodes.

[0124] The touch sensor may further include multiple touch lines to electrically connect multiple touch electrodes and the touch drive circuit 260.

[0125] The touch sensor can exist outside the display panel 110 in the form of a touch panel, or it can be located inside the display panel 110.

[0126] When a touch sensor is located outside the display panel 110 in the form of a touch panel, the touch sensor is referred to as an external type.

[0127] If the touch sensor is an external type, the touch panel and the display panel 110 can be manufactured separately and combined during the assembly process.

[0128] An externally mounted touch panel may include a touch panel substrate and multiple touch electrodes on the touch panel substrate.

[0129] If the touch sensor is located inside the display panel 110, the touch sensor can be formed on the substrate (SUB) along with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0130] The touch drive circuit 260 can supply a touch drive signal to at least one of the multiple touch electrodes and sense at least one of the multiple touch electrodes to generate touch sensing data.

[0131] The touch sensing circuit can perform touch sensing using either a self-capacitance sensing method or a mutual-capacitance sensing method.

[0132] When a touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and the touch object (e.g., finger, pen, etc.).

[0133] In the self-capacitance sensing method, each of the multiple touch electrodes can act as both a driving touch electrode and a sensing touch electrode.

[0134] The touch drive circuit 260 can drive all or part of the multiple touch electrodes to sense all or part of the multiple touch electrodes.

[0135] When a touch sensing circuit performs touch sensing using a mutual capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes.

[0136] According to the mutual capacitance sensing method, multiple touch electrodes can be divided into driving touch electrodes and sensing touch electrodes.

[0137] The touch drive circuit 260 can drive the drive touch electrode to sense the sensing touch electrode.

[0138] The touch drive circuit 260 and touch controller 270 included in the touch sensing circuit can be implemented in separate devices or in a single device.

[0139] Furthermore, the touch drive circuit 260 and the data drive circuit 220 can be implemented in separate devices, or they can be implemented in a single device.

[0140] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or touch sensing circuit.

[0141] The display device 100 according to the embodiments of this specification may be a mobile device such as a smartphone or tablet, or a monitor or television (TV) of various sizes, and is not limited to these, but may be any type or size of display capable of displaying information or images.

[0142] As mentioned above, the display area (DA) of the display panel 110 can include a general area (NA) and one or more optical areas (OA1, OA2).

[0143] The general area (NA) and one or more optical areas (OA1, OA2) are areas where images can be displayed.

[0144] However, the general region (NA) is a region where a light-transmitting structure does not need to be formed, while one or more optical regions (OA1, OA2) are regions where a light-transmitting structure must be formed.

[0145] As mentioned above, the display area (DA) in the display panel 110 may include one or more optical areas (OA1, OA2) along with the general area (NA). However, for the sake of explanation, we will use the example where the display area (DA) includes both the first optical area (OA1) and the second optical area (OA2).

[0146] Figure 3 shows the equivalent circuit of a subpixel (SP) in the display panel 110 according to the embodiment described herein.

[0147] Each subpixel (SP) located in the general area (NA), first optical area (OA1), and second optical area (OA2) within the display area (DA) of the display panel 110 may include a light-emitting element (ED), a drive transistor (DRT) for driving the light-emitting element (ED), a scan transistor (SCT) for transmitting a data voltage (Vdata) to the first node (N1) of the drive transistor (DRT), and a storage capacitor (Cst) for maintaining a constant voltage during one frame.

[0148] The drive transistor (DRT) may include a first node (N1) to which a data voltage can be applied, a second node (N2) electrically connected to a light-emitting element (ED), and a third node (N3) to which a drive voltage (ELVDD) is applied from a drive voltage line (DVL).

[0149] In a drive transistor (DRT), the first node (N1) is the gate node, the second node (N2) can be either the source node or the drain node, and the third node (N3) can be either the drain node or the source node.

[0150] The light-emitting element (ED) may include a first electrode layer (AE), an emissive layer (EL), and a second electrode layer (CE).

[0151] The first electrode layer (AE) can be a pixel electrode placed on each subpixel (SP) and can be electrically connected to the second node (N2) of the drive transistor (DRT) of each subpixel (SP).

[0152] The second electrode layer (CE) can be a common electrode placed in common by multiple subpixels (SP), and a ground voltage (ELVSS) can be applied to it.

[0153] For example, the first electrode layer (AE) can be a pixel electrode, and the second electrode layer (CE) can be a common electrode.

[0154] Conversely, the first electrode layer (AE) can be a common electrode, and the second electrode layer (CE) can be a pixel electrode.

[0155] For the sake of explanation, we will assume below that the first electrode layer (AE) is the pixel electrode and the second electrode layer (CE) is the common electrode.

[0156] The light-emitting element (ED) can be an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot (QD) light-emitting element.

[0157] In this case, if the light-emitting element (ED) is an organic light-emitting diode, the light-emitting layer (EL) of the light-emitting element (ED) may include an organic light-emitting layer containing organic material.

[0158] A scan transistor (SCT) is controlled on and off by a scan signal (SCAN), which is a gate signal applied through the gate line (GL), and can be electrically coupled between the first node (N1) and the data line (DL) of a drive transistor (DRT).

[0159] A storage capacitor (Cst) can be electrically connected between the first node (N1) and the second node (N2) of the drive transistor (DRT).

[0160] Each subpixel (SP) may have a 2T (Transistor) 1C (Capacitor) structure, as shown in Figure 3, which includes two transistors (DRT, SCT) and one capacitor (Cst), and may also include one or more transistors or one or more capacitors, depending on the circumstances.

[0161] The storage capacitor (Cst) may be an external capacitor intentionally designed outside the drive transistor (DRT), rather than a parasitic capacitor (e.g., Cgs, Cgd) which is an internal capacitor that can exist between the first node (N1) and the second node (N2) of the drive transistor (DRT).

[0162] The drive transistor (DRT) and the scan transistor (SCT) can each be either an n-type transistor or a p-type transistor.

[0163] Furthermore, the drive transistor (DRT) and the scan transistor (SCT) can each be composed of low-temperature polycrystalline silicon transistors.

[0164] However, it is not limited to this, and at least one of them can be composed of an oxide thin-film transistor.

[0165] Since the circuit elements within each subpixel (SP), particularly the light-emitting elements (EDs), are vulnerable to external moisture and oxygen, an encapsulation layer (ENCAP) can be arranged to cover the light-emitting elements (EDs) to prevent external moisture and oxygen from penetrating the circuit elements (particularly the light-emitting elements (EDs)).

[0166] Figure 4 is a diagram showing the arrangement of subpixels (SP) in three regions (NA, OA1, OA2) included in the display area of ​​the display device 100 according to the embodiment of this specification.

[0167] Referring to Figure 4, multiple subpixels (SP) can be placed in each of the general area (NA), first optical area (OA1), and second optical area (OA2) included in the display area (DA).

[0168] For example, multiple subpixels (SPs) may include red subpixels (Red SPs) that emit red light, green subpixels (Green SPs) that emit green light, and blue subpixels (Blue SPs) that emit blue light.

[0169] As a result, the general region (NA), the first optical region (OA1), and the second optical region (OA2) can each contain an emission region (EA) for a red subpixel (Red SP), an emission region (EA) for a green subpixel (Green SP), and an emission region (EA) for a blue subpixel (Blue SP).

[0170] Referring to Figure 4, the general region (NA) does not contain a light-transmitting structure, but it can contain an emissive region (EA).

[0171] In this case, the first optical region (OA1) and the second optical region (OA2) must not only include an emissive region (EA) but also include a light-transmitting structure.

[0172] Therefore, the first optical region (OA1) may include an emission region (EA) and a first transmission region (TA1), and the second optical region (OA2) may include an emission region (EA) and a second transmission region (TA2).

[0173] The light-emitting region (EA) and the light-transmitting regions (TA1, TA2) can be distinguished by whether or not light can pass through them.

[0174] In other words, the light-emitting region (EA) can be a region where light transmission is impossible, and the light-transmitting regions (TA1, TA2) can be a region where light transmission is possible.

[0175] Furthermore, the light-emitting region (EA) and the transmission region (TA1, TA2) can be distinguished by the presence or absence of the second electrode layer (CE).

[0176] For example, a second electrode layer (CE) may be formed in the light-emitting region (EA), while a second electrode layer (CE) may not be formed in the transmission regions (TA1, TA2).

[0177] On the other hand, a light shield layer (LSL) may be formed in the light-emitting region (EA), while a light shield layer may not be formed in the light-transmitting regions (TA1, TA2).

[0178] Since the first optical region (OA1) includes the first transmission region (TA1) and the second optical region (OA2) includes the second transmission region (TA2), both the first optical region (OA1) and the second optical region (OA2) are regions through which light can be transmitted.

[0179] The transmittance (degree of transmission) of the first optical region (OA1) and the transmittance (degree of transmission) of the second optical region (OA2) may be substantially equal.

[0180] In this specification, "substantially equivalent" can mean being equivalent to a certain extent, taking into account minute differences due to manufacturing errors.

[0181] In this case, the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) may have substantially the same pattern or size.

[0182] Alternatively, even if the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) differ in pattern and size, the proportion of the first transmission region (TA1) within the first optical region (OA1) and the proportion of the second transmission region (TA2) within the second optical region (OA2) may be substantially equal.

[0183] However, this is not limited to the above, and the transmittance (degree of transmission) of the first optical region (OA1) and the transmittance (degree of transmission) of the second optical region (OA2) may differ from each other.

[0184] In this case, the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) may have different patterns or sizes.

[0185] Alternatively, even if the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) are substantially identical in pattern and size, the proportion of the first transmission region (TA1) within the first optical region (OA1) and the proportion of the second transmission region (TA2) within the second optical region (OA2) may differ from each other.

[0186] For example, if the first optical electronic device 11 onto which the first optical region (OA1) is superimposed is a camera, and the second optical electronic device 12 onto which the second optical region (OA2) is superimposed is a sensing sensor, the camera may require a greater amount of light than the sensing sensor.

[0187] Therefore, the transmittance (degree of transmission) of the first optical region (OA1) may be higher than that of the second optical region (OA2).

[0188] In this case, the first transmission region (TA1) of the first optical region (OA1) can have an even larger area than the second transmission region (TA2) of the second optical region (OA2).

[0189] Alternatively, even if the first transmission region (TA1) of the first optical region (OA1) and the second transmission region (TA2) of the second optical region (OA2) are substantially the same in size, the proportion of the first transmission region (TA1) within the first optical region (OA1) may be larger than the proportion of the second transmission region (TA2) within the second optical region (OA2).

[0190] On the other hand, as shown in Figure 4, the first transmission region (TA1) of the first optical region (OA1) can be circular in cross-section, but the cross-sectional structure of the first transmission region (TA1) in the embodiments of this specification is not limited to this.

[0191] For example, the shape of the first transmission region (TA1) of the first optical region (OA1) may be an octagon on a plane, while in other examples it may be an ellipse or a polygon.

[0192] In this way, the area of ​​the light-emitting region of the first optical region (OA1) can be adjusted while adjusting the transmittance of the first transmission region (TA1) by changing the shape of the first transmission region (TA1).

[0193] In the following explanation, for the sake of clarity, we will use the example where the transmittance (degree of transmission) of the first optical region (OA1) is higher than the transmittance (degree of transmission) of the second optical region (OA2).

[0194] Furthermore, as shown in Figure 4, in the embodiments of this specification, the transparent regions (TA1, TA2) can also be referred to as transparent regions, and transmittance can also be referred to as transparency.

[0195] Furthermore, as shown in Figure 4, in the embodiments of this specification, we assume that the first optical region (OA1) and the second optical region (OA2) are located at the upper edge of the display region (DA) of the display panel 110 and are arranged side by side.

[0196] Referring to Figure 4, the horizontal display area where the first optical area (OA1) and the second optical area (OA2) are located is referred to as the first horizontal display area (HA1), and the horizontal display area where the first optical area (OA1) and the second optical area (OA2) are not located is referred to as the second horizontal display area (HA2).

[0197] Referring to Figure 4, the first horizontal display area (HA1) can include a general area (NA), a first optical area (OA1), and a second optical area (OA2).

[0198] The second horizontal display area (HA2) may contain only the general area (NA).

[0199] Figures 5 and 6 are cross-sectional views of light-emitting elements (EDs) included in the display device 100 according to the embodiments of this specification.

[0200] Referring to Figure 5, one embodiment of the light-emitting element (ED) includes a red subpixel (R), a green subpixel (G), and a blue subpixel (B) on the substrate 10 that emit light of different hues from each other.

[0201] The light-emitting element (ED) may include a first electrode layer 51 disposed on the substrate 10, a second electrode layer 58 disposed opposite the first electrode layer 51, and a light-emitting layer 55 formed between the first electrode layer 51 and the second electrode layer 58.

[0202] The first electrode layer 51 may be an anode (positive electrode) and the second electrode layer 58 may be a cathode (negative electrode), but the embodiments of the present invention are not limited to this.

[0203] For example, in the case of an inverter type, the first electrode layer 51 can be the cathode and the second electrode layer 58 can be the anode.

[0204] However, in the embodiments described later, the explanation will focus on a configuration in which the first electrode layer 51 of the light-emitting element (ED) is the anode (positive electrode) and the second electrode layer 58 is the cathode (negative electrode).

[0205] The first electrode layer 51 is a transistor that includes a source, drain, gate, and active layer, and can be electrically connected to either the source or drain through a contact hole formed in the insulating film.

[0206] The first electrode layer 51 can be made of a material with a relatively high work function.

[0207] The first electrode layer 51 can be made of a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), AZO (Al-doped zinc oxide), In2O3 (indium oxide), or SnO2 (tin oxide), but is not limited to these.

[0208] The second electrode layer 58 can be made of a metal, alloy, electrically conductive compound, or a mixture of two or more of these having a relatively low work function.

[0209] For example, a transmissive electrode can be obtained by forming a thin film of lithium (Li), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), etc.

[0210] On the other hand, the present invention can be modified in various ways, such as by forming transmissive electrodes using ITO or IZO to obtain a top-emitting device.

[0211] A capping layer (not shown) may be included on the second electrode layer 58 to improve optical properties and maximize luminescence efficiency.

[0212] For example, this can be done with a metal oxide layer, a metal nitride layer, or a metal nitrate layer.

[0213] For example, this can be done with MoOx (x=2~4), Al2O3, Sb2O3, BaO, CdO, CaO, Ce2O3, CoO, Cu2O, DyO, GdO, HfO2, La2O3, Li2O, MgO, NbO, NiO, Nd2O3, PdO, Sm2O3, ScO, SiO2, SrO, TA2O3, TiO, WO3, VO2, YbO, Y2O3, ZnO, ZrO, AlN, BN, NbN, SiN, TAN, TiN, VN, YbN, ZrN, SiON, AlON, or mixtures thereof, but is not limited to these.

[0214] The light-emitting layer 55 may include a red light-emitting layer 55R placed on the red subpixel (R), a green light-emitting layer 55G placed on the green subpixel (G), and a blue light-emitting layer 55B placed on the blue subpixel (B).

[0215] At this time, the wavelength of the emitted light increases in the order of red light-emitting layer 55R, green light-emitting layer 55G, and blue light-emitting layer 55B.

[0216] The red light-emitting layer 55R may contain a red host and a red dopant.

[0217] The red host may be, but is not limited to, Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more of these.

[0218] Compounds containing PtOEP, Ir(piq)3, Btp2Ir(acac), Ir(2-phq)2(acac), Ir(2-phq)3, Ir(flq)2(acac), Ir(fliq)2(acac), DCM, or DCJTB can be used as red dopants, but are not limited to these.

[0219] The green light-emitting layer 55G may contain a green host and a green dopant.

[0220] The green host may be, but is not limited to, Alq3, CBP, PVK, AND, TCTA, TPBI, TBADN, E3, DSA, or a mixture of two or more of these.

[0221] Green dopants that can be used include, but are not limited to, Ir(ppy)3tris(2-phenylpyridine)iridium, Ir(ppy)2(acac)(Bis(2-phenylpyridine)(Acetylacetonato)iridium(III), Ir(mppy)3(tris(2-(4-tolyl)phenylpyridine)iridium, C545T10-(2benzothiazolyl)-1,1,7,7-tetramethyl-2,3,6,7-tetrahydro-1H,5H,11H-[1]benzopyrano[6,7,8-ij]-quinolizin11-one.

[0222] The blue light-emitting layer 55B may contain a blue host and a blue dopant.

[0223] The blue host can be, but is not limited to, Alq3, CBP (4,4'-N,N'-dicabazole-biphenyl), PVK (poly(n-vinylcabazole), ADN (9,10-di(naphthalene-2-yl)anthracene), TCTA, TPBI (1,3,5-tris(N-phenylbenzimidazole-2-yl)benzene), TBADN (3-tert-butyl-9,10-di(naphth-2-yl)anthracene), E3, DSA (distyrylarylene), or a mixture of two or more of these.

[0224] The blue dopant can be derived from, but is not limited to, compounds containing F2Irpic, (F2ppy)2Ir(tmd), Ir(dfppz)3, ter-fluorene, DPAVBi(4, 4'-bis(4diphenylaminostyryl)biphenyl, TBPe, etc.

[0225] The light-emitting element (ED) may include a hole transport layer 53 disposed between the first electrode layer 51 and the light-emitting layer 55.

[0226] The hole transport layer 53 may include a common hole transport layer 53C located on the hole injection layer 52.

[0227] The hole transport layer 53 may include a light-emitting auxiliary layer positioned between the hole transport layer 53 and the common hole transport layer 53C.

[0228] The light-emitting auxiliary layer may include a red light-emitting auxiliary layer 53R, a green light-emitting auxiliary layer 53G, and a blue light-emitting auxiliary layer (not shown) located on the hole transport layer 53C.

[0229] The luminescence-enhancing layer is just one example; it can perform a hole transport function and can be made of a hole transport material. Each luminescence-enhancing layer can be made of the same material or compound, or of different materials or compounds.

[0230] For example, the hole transport layer 53, the common hole transport layer 53C, the red light emission auxiliary layer 53R, the green light emission auxiliary layer 53G, and the blue light emission auxiliary layer (not shown) may contain, but are not limited to, a tertiary amine or a substance containing a tertiary amine containing fluorine.

[0231] The light-emitting element (ED) may include, but is not limited to, a hole injection layer 52 disposed on the first electrode layer 51, a hole transport layer 53 disposed on the hole injection layer 52, a light-emitting layer 55 disposed on the hole transport layer 53, and an electron transport layer 57 disposed on the light-emitting layer 55.

[0232] When a voltage is applied to the first electrode layer 51 and the second electrode layer 58 of the light-emitting element (ED), holes that have passed through the hole transport layer 53 and electrons that have passed through the electron transport layer 57 are moved to the light-emitting layer 55 to form excitons, and visible light can be emitted from the light-emitting layer 55.

[0233] The light-emitting element (ED) may include an electron-blocking layer 54 between the hole transport layer 53 and the light-emitting layer 55.

[0234] However, this is not necessarily the only option, and the light-emitting element (ED) may not include the electron-blocking layer 54.

[0235] The electron barrier layer 54 may contain, but is not limited to, at least one of Tris(phenylpyrazole)iridium, BPAPF (9,9-bis[04-(N,N-bis-biphenyl-4-ylamino)phenyl]-9H-fluorene), Bis[04-(p,p-dITOlylamino)phenyl]diphenylsilane, NPD (4,4'-bis[0N-1-napthyl)-N-phenyl-amino]biphenyl), mCP (N,N'-dicarbazolyl-3,5-benzene), MPMP (bis[04-(N,N-diethylamino)-2-methylphenyl](4-methylphenyl)methane), or a combination thereof.

[0236] Furthermore, the electron barrier layer 54 may contain inorganic compounds. For example, the electron barrier layer 144 may contain, but is not limited to, at least one or a combination thereof from halide compounds such as LiF, NaF, KF, RbF, CsF, FrF, MgF2, CaF2, SrF2, BaF2, LiCl, NaCl, KCl, RbCl, CsCl, FrCl and oxides such as Li2O, Li2O2, Na2O, K2O, Rb2O, Rb2O2, Cs2O, Cs2O2, LiAlO2, LiBO2, LiTaO3, LiNbO3, LiWO4, Li2CO, NaWO4, KAlO2, K2SiO3, B2O5, Al2O3, SiO2.

[0237] The electron-blocking layer 54 acts as a buffer layer that blocks direct contact between the hole transport layer 53 and the light-emitting layer 55, thereby preventing electrons from easily flowing into the hole transport layer 53.

[0238] In other words, the electron-blocking layer 54 can improve the efficiency and lifespan of the light-emitting element 50 by regulating electron injection, movement, and coupling with holes.

[0239] The electron transport layer 57 can be placed on the light-emitting layer 55.

[0240] The electron transport layer 57 can adjust the electron movement speed so that electrons and holes meet in the light-emitting layer 55 and emit light.

[0241] The electron transport layer 57 may contain materials in which the electron movement speed is several times greater than that of other materials.

[0242] The electron transport layer 57 may, but is not limited to, include at least one of Alq3 (tris(8-hydroxyquinolino)aluminum), PBD, TAZ, spiro-PBD, BAlq, and SAlq, or a combination thereof.

[0243] An electron injection layer (not shown) can be placed on the electron transport layer 57.

[0244] The electron injection layer (not shown) can transfer electrons flowing in from the second electrode layer 58 to the electron transport layer 57.

[0245] The light-emitting element (ED) may include a hole-blocking layer 56 between the light-emitting layer 55 and the electron transport layer 57.

[0246] However, this is not necessarily the only option, and the light-emitting element (ED) may not include the hole-blocking layer 56.

[0247] The hole-blocking layer 56 acts as a buffer layer that blocks direct contact between the electron-transport layer 57 and the light-emitting layer 55, thereby preventing holes from easily flowing into the electron-transport layer 57.

[0248] The hole blocking layer 56 can improve the efficiency and lifespan of the light-emitting element (ED) by regulating hole injection, migration, and coupling with electrons.

[0249] The above explanation, with reference to Figure 5, uses the case of a single-stack structure for the light-emitting element as an example.

[0250] The following explanation will use Figure 6 as an example to illustrate the case where the light-emitting element (ED) has a multi-stack structure.

[0251] Referring to Figure 6, the light-emitting element (ED) can be a multi-stack structure including a first stacked light-emitting layer 651 and a second stacked light-emitting layer 652. Each light-emitting element (ED) may include a first electrode layer 61 disposed on the substrate 10, a hole injection layer 62 on the first electrode layer 61, and a second electrode layer 68 disposed on the opposite side of the first electrode layer 61.

[0252] Here, the first stacked light-emitting layer 651 and the second stacked light-emitting layer 652 may contain light-emitting materials of the same hue.

[0253] Referring to Figure 6, the light-emitting element (ED) can be composed of a first stack structure including a first stack light-emitting layer 651 and a second stack structure including a second stack light-emitting layer 652.

[0254] The matters relating to the first hole transport layers 631, 631C, 6331G, and 631R of the first stack structure, the first electron barrier layer 641, the first stack light-emitting layers 651, 651R, 651G, and 651B, the first hole barrier layer 661, and the first electron transport layer 671 may be substantially the same as the matters relating to the hole transport layer 53, electron barrier layer 54, light-emitting layer 55, hole barrier layer 56, and electron transport layer 57 described in Figure 5.

[0255] In the case of the second stack structure, a charge generation layer 69, a second hole transport layer (including 632, 632R, 632G, and 632B), a second electron barrier layer 642, a second stack light-emitting layer (including 652, 652R, 652G, and 652B), a second hole barrier layer 662, and a second electron transport layer 672 can be placed between the second electrode layer 68 and the first electron transport layer 671.

[0256] Specifically, a charge generation layer 69 can be located on the first electron transport layer 671, a second hole transport layer 632 on the charge generation layer 69, a second electron barrier layer 642 on the second hole transport layer 632, a second stacked light-emitting layer 652 on the second electron barrier layer 642, a second hole barrier layer 662 on the second stacked light-emitting layer 652, and a second electron transport layer 672 on the second hole barrier layer 662.

[0257] The second electron transport layer 672 is positioned in contact with the second stacked light-emitting layer 652, enabling it to transfer electrons to the second stacked light-emitting layer 652.

[0258] The charge generation layer 69 is positioned between the first electron transport layer 671 and the second hole transport layer 632, and can transfer electrons to the first electron transport layer 671.

[0259] The first hole transport layer 671 is positioned in contact with the first stacked light-emitting layer 651 so that it can transmit holes to the first stacked light-emitting layer 651.

[0260] Figure 6 illustrates a light-emitting element with a two-stack structure as an example, but the embodiments of this disclosure are not limited to this and can be equally applied to multi-stack structures such as three-stack and four-stack configurations.

[0261] Figures 7a and 7b are cross-sectional views of light-emitting elements (ED) located in the general area (NA) and optical area (OA) of a display device according to an embodiment of this specification.

[0262] Figures 7a and 7b illustrate a single-stack light-emitting element for ease of explanation, but the theory is not limited to this and can be equally applied to multi-stack structures.

[0263] Furthermore, for the sake of clarity, Figures 7a and 7b may show some of the materials constituting the light-emitting layer 75 in particle form. For example, the first host (H1) and the second host (H2), which are parts of the materials constituting the light-emitting layer 75, can be shown in particle form.

[0264] Referring to Figure 7a, the matters concerning the first electrode layer 71, hole injection layer 72, common hole transport layer 73C, hole transport layer 73, electron barrier layer 74, light-emitting layer 75, hole barrier layer 76, electron transport layer 77, and second electrode layer 78 in the general region (NA) and optical region (OA) are substantially the same as the matters concerning the first electrode layer 51, hole injection layer 52, common hole transport layer 53C, hole transport layer 53, electron barrier layer 54, light-emitting layer 55, hole barrier layer 56, electron transport layer 57, and second electrode layer 58 described in Figure 5.

[0265] Referring to Figure 7a, the light-emitting layer 75 in the general region (NA) and the optical region (OA) may include a first light-emitting layer 751 and a second light-emitting layer 752.

[0266] The first light-emitting layer 751 is located on the electron-blocking layer 74, and the second light-emitting layer 752 can be located on the first light-emitting layer 751.

[0267] In this case, in the general region (NA), the first light-emitting layer 751 and the second light-emitting layer 752 may contain the first host (H1).

[0268] In the general region (NA), the layers are shown separated into a first light-emitting layer 751 and a second light-emitting layer 752, but this is not the only way to represent them. If the first light-emitting layer 751 and the second light-emitting layer 752 are composed of the same material including a first host (H1), then the first light-emitting layer 751 and the second light-emitting layer 752 can also be viewed as a single layer.

[0269] In the case of the optical region (OA), the first light-emitting layer 751 may include a first host (H1), and the second light-emitting layer 752 may include a second host (H2).

[0270] At this time, the second host (H2) may be different from the first host (H1).

[0271] In FIG. 7a, the number of particles of the first host (H1) and the second host (H2) illustrated in the general region (NA) and the optical region (OA) is merely exemplary for the convenience of explanation and is not limited thereto, and the amount of particles may vary due to process errors.

[0272] On the other hand, in the case of the general region (NA), the first light-emitting layer 751 and the second light-emitting layer 752 may include the same type of dopant.

[0273] Also, in the case of the optical region (OA), the first light-emitting layer 751 may include a first dopant (not shown), and the second light-emitting layer 752 may include a second dopant (not shown). Referring to FIG. 7a, the thickness of the first light-emitting layer 751 in the optical region (OA) is greater than the thickness of the first light-emitting layer 751 in the general region (NA), and the thickness of the second light-emitting layer 752 in the optical region (OA) is greater than the thickness of the second light-emitting layer 752 in the general region (NA). Therefore, the light-emitting area and efficiency increase.

[0274] At this time, the second dopant and the first dopant may be different.

[0275] However, it is not limited thereto, and in the case of the optical region (OA), the first light-emitting layer 751 and the second light-emitting layer 752 may also include the same type of dopant.

[0276] Different from the general region (NA), by adjusting the types and amounts of the host and dopant in the first light-emitting layer 751 and the second light-emitting layer 752 in the optical region (OA), the lifetime of the light-emitting device (ED) disposed in the optical region (OA) can be increased.

[0277] Referring to Figure 7a, the thickness (B1, B2) of the light-emitting layer 75 can be increased by increasing the number of light-emitting layers, such as by adding a first light-emitting layer 751 and a second light-emitting layer 752.

[0278] Thus, the thickness (A1, A2) of the hole transport layer 73 or the common hole transport layer 73C can be adjusted to compensate for the increased thickness (B1, B2) of the light-emitting layer 75. The combination of hole transport layers 73 and the common hole transport layer 73C can also be referred to as the hole transport layer 73. The common hole transport layer 73C can also be omitted.

[0279] Referring to Figure 7a, the thickness of the light-emitting layer 75 in the optical region (OA) (B2) increases compared to the thickness of the light-emitting layer 75 in the general region (NA) (B1). To compensate for this, the thickness of the hole transport layer 73 and common hole transport layer 73C in the optical region (OA) (A2) can be reduced compared to the thickness of the hole transport layer 73 and common hole transport layer 73C in the general region (NA) (A1).

[0280] Preferably, the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, and the second light-emitting layer 752 in the general region (NA) may be equal to the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, and the second light-emitting layer 752 in the optical region (OA).

[0281] On the other hand, the first light-emitting layer 751 and the second light-emitting layer 752 of the light-emitting element (ED) can use a phosphorescent host and a phosphorescent dopant, or a fluorescent host and a fluorescent dopant, depending on the application.

[0282] The above explanation uses Figure 7a as an example to illustrate the case where the light-emitting layer 75 consists of two layers.

[0283] The following explanation uses Figure 7b as an example, illustrating the case where the light-emitting layer 75 has three layers.

[0284] Referring to Figure 7b, the matters concerning the first electrode layer 71, hole injection layer 72, common hole transport layer 73C, hole transport layer 73, electron barrier layer 74, light-emitting layer 75, hole barrier layer 76, electron transport layer 77, and second electrode layer 78 in the general region (NA) and optical region (OA) are substantially the same as the matters concerning the first electrode layer 51, hole injection layer 52, common hole transport layer 53C, hole transport layer 53, electron barrier layer 54, light-emitting layer 55, hole barrier layer 56, electron transport layer 57, and second electrode layer 58 described in Figure 5.

[0285] Referring to Figure 7b, the light-emitting layer 75 in the general region (NA) and the optical region (OA) may include a first light-emitting layer 751, a second light-emitting layer 752, and a third light-emitting layer 753.

[0286] The first light-emitting layer 751 may be located on the electron-blocking layer 74, the second light-emitting layer 752 on the first light-emitting layer 751, and the third light-emitting layer 753 on the second light-emitting layer 752.

[0287] In this case, in the general region (NA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 may contain the first host (H1).

[0288] In the general region (NA), the layers are shown separated into a first light-emitting layer 751, a second light-emitting layer 752, and a third light-emitting layer 753. However, this is not the only way to represent them. If the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 are composed of the same material including a first host (H1), then the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 can also be viewed as a single layer.

[0289] In the optical region (OA), the first light-emitting layer 751 and the third light-emitting layer 753 may contain a first host (H1), and the second light-emitting layer 752 may contain a second host (H2).

[0290] In this case, the second host (H2) may be different from the first host (H1).

[0291] In FIG. 7b, the number of particles of the first host (H1) and the second host (H2) illustrated in the general area (NA) and the optical area (OA) is only exemplary for convenience of explanation, and is not limited thereto, and the amount of particles may vary due to process errors.

[0292] On the other hand, in the case of the general area (NA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 can contain the same type of dopant.

[0293] Also, in the case of the optical area (OA), the first light-emitting layer 751 and the third light-emitting layer 753 can contain the first dopant, and the second light-emitting layer 752 can contain the second dopant.

[0294] At this time, the second dopant and the first dopant may be different.

[0295] However, it is not limited thereto, and in the case of the optical area (OA), the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 can also contain the same type of dopant.

[0296] Different from the general area (NA), by adjusting the types and amounts of the host and dopant in the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the optical area (OA), the lifetime of the light-emitting element (ED) disposed in the optical area (OA) can be increased.

[0297] Referring to FIG. 7b, by increasing the number of light-emitting layers in the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753, the thicknesses (B1, B2) of the light-emitting layer 75 can be increased.

[0298] Thus, in order to compensate for the increased thicknesses (B1, B2) of the light-emitting layer 75, the thicknesses (A1, A2) of the hole transport layer 73 or the common hole transport layer 73C can be adjusted.

[0299] Referring to Figure 7b, the thickness of the light-emitting layer 75 in the optical region (OA) (B2) increases compared to the thickness of the light-emitting layer 75 in the general region (NA) (B1). To compensate for this, the thickness of the hole transport layer 73 and common hole transport layer 73C in the optical region (OA) (A2) can be reduced compared to the thickness of the hole transport layer 73 and common hole transport layer 73C in the general region (NA) (A1).

[0300] Preferably, the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the general region (NA) may be equal to the sum of the thicknesses of the hole transport layers 73, 73C, the first light-emitting layer 751, the second light-emitting layer 752, and the third light-emitting layer 753 in the optical region (OA).

[0301] On the other hand, the first light-emitting layer 751 and the second light-emitting layer 752 of the light-emitting element (ED) can use a phosphorescent host and a phosphorescent dopant, or a fluorescent host and a fluorescent dopant, depending on the application.

[0302] Figures 8a to 8c are diagrams showing the triplet state energy levels of light-emitting elements (EDs) according to the embodiments described herein.

[0303] Figures 8a and 8b show a case in which the light-emitting layer 85 of a light-emitting element (ED) according to an embodiment of this specification is composed of a first light-emitting layer 851 and a second light-emitting layer 852, and there are two light-emitting layers disposed between the electron-blocking layer 84 and the hole-blocking layer 86.

[0304] Figure 8c is a diagram showing a case in which the light-emitting layer 85 of a light-emitting element (ED) according to an embodiment of this specification is composed of a first light-emitting layer 851, a second light-emitting layer 852, and a third light-emitting layer 853, and there are three light-emitting layers disposed between the electron-blocking layer 84 and the hole-blocking layer 86.

[0305] Referring to Figure 8a, a second light-emitting layer 852 can be placed between the hole-blocking layer 86 and the first light-emitting layer 851 to prevent triplet polaron quenching (TPQ).

[0306] The thickness of the second light-emitting layer 852 is preferably between 2 nm and 5 nm.

[0307] In this case, the first light-emitting layer 851 may be the main light-emitting layer, and the second light-emitting layer 852 may be the auxiliary light-emitting layer.

[0308] In other words, the second light-emitting layer 852 can transfer energy created by combining holes accumulated at the interface of the hole-blocking layer 86 with electrons transmitted through the hole-blocking layer 86 to the first light-emitting layer 851.

[0309] Here, for stable electron transport and hole blocking, it is also possible to satisfy equation 1 in the optical region (OA) and at least one of equations 2 or 3.

[0310] (Formula 1) T1 <T2<T HB

[0311] In equation 1, T HB T1 is the triplet state energy level of the hole-blocking layer, T1 is the triplet state energy level of the first emitting layer, and T2 is the triplet state energy level of the second emitting layer.

[0312] (Formula 2) L HB <L2<L1

[0313] In equation 2, L HB L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole-blocking layer, L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first emitting layer, and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second emitting layer.

[0314] (Formula 3) |H2-H1|≦0.1eV

[0315] In Equation 3, H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first emissive layer, and H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second emissive layer.

[0316] If the light-emitting element (ED) satisfies Equation 1 and at least one of Equations 2 or 3, the phosphorescence efficiency can be increased.

[0317] Referring to Figure 8b, a second light-emitting layer 852 can be placed between the hole-blocking layer 86 and the first light-emitting layer 851 to prevent triplet-triplet annihilation (TTA).

[0318] The thickness of the first light-emitting layer 851 is preferably between 2 nm and 5 nm.

[0319] In this case, the second light-emitting layer 852 may be the main light-emitting layer, and the first light-emitting layer 851 may be the auxiliary light-emitting layer.

[0320] In other words, the first light-emitting layer 851 can transfer energy created by coupling electrons accumulated at the interface of the electron-blocking layer 84 with holes transmitted through the electron-blocking layer 84 to the second light-emitting layer 852.

[0321] Here, for stable hole transfer and electron blockade, it is also possible to satisfy equation 4 in the optical region (OA) and at least one of equations 5 or 6.

[0322] (Formula 4) T2 <T1<T EB

[0323] In Equation 4, TEB is the triplet state energy level of the electron blocking layer, T1 is the triplet state energy level of the first light-emitting layer, and T2 is the triplet state energy level of the second light-emitting layer.

[0324] (Equation 5) L2 < L1 < L EB

[0325] In Equation 5, L EB is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the electron blocking layer, L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0326] (Equation 6) H2 < H1 < H EB

[0327] In Equation 6, H EB is the HOMO (Highest Occupied Molecular Orbital) energy level of the electron blocking layer, H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, and H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0328] If the light-emitting device (ED) satisfies Equation 4 and at least one of Equation 5 or Equation 6, the fluorescence efficiency can be increased.

[0329] Referring to FIG. 8c, a third light-emitting layer 853 can be disposed between the hole blocking layer 86 and the second light-emitting layer 852 to prevent triplet polaron quenching (TPQ) in the light-emitting layer 85 and the hole blocking layer 86.

[0330] The thickness of the first light-emitting layer 851 and the third light-emitting layer 853 is preferably between 2 nm and 5 nm.

[0331] In this case, the second light-emitting layer 852 can be the main light-emitting layer, and the first light-emitting layer 851 and the third light-emitting layer 853 can be auxiliary light-emitting layers.

[0332] Here, the first light-emitting layer 851 has lower electron transport capability compared to the second light-emitting layer 852 and the third light-emitting layer 853, but it may have excellent hole transport capability.

[0333] Here, in order to ensure stable energy transfer and light emission, equations 7 and 8 can be satisfied in the optical region (OA).

[0334] (Formula 7) T1>T2

[0335] (Formula 8) T3 > T2

[0336] In equations 7 and 8, T1 is the triplet state energy level of the first light-emitting layer, T2 is the triplet state energy level of the second light-emitting layer, and T3 is the triplet state energy level of the third light-emitting layer.

[0337] When the light-emitting element (ED) satisfies equations 7 and 8, the triplet energy level (T2) of the second light-emitting layer 852 becomes lower than the triplet energy level (T1) of the first light-emitting layer 851 and the triplet energy level (T3) of the third light-emitting layer 853, so that the energy can be transferred from the auxiliary light-emitting layers 851 and 853 to the main light-emitting layer 852.

[0338] In this case, for stable energy transfer and light emission, it is desirable that at least one of equations 9, 10, 11, and 12 be satisfied.

[0339] (Formula 9) T EB >T1>T2

[0340] In Equation 9, T1 is the triplet state energy level of the first emitting layer, T2 is the triplet state energy level of the second emitting layer, and T EB This is the triplet state energy level of the electron barrier layer.

[0341] (Formula 10) T HB >T3>T2

[0342] T2 is the triplet state energy level of the second emissive layer, T3 is the triplet state energy level of the third emissive layer, and T HB This is the triplet state energy level of the hole barrier layer.

[0343] (Formula 11) L1>L2

[0344] In equation 11,

[0345] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first emissive layer, and L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second emissive layer.

[0346] (Formula 12) H1>H2

[0347] In equation 12,

[0348] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first emissive layer, and H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second emissive layer.

[0349] The HOMO, LUMO, and T values ​​explained in Figures 8a to 8c were measured using the cyclic voltage-current method.

[0350] Luminescence Manufacturing Evaluation

[0351] (Example 1) A hole injection layer was formed by vacuum deposition of a 2-TNATA film onto an ITO (Indium tin oxide) layer (positive electrode) formed on a glass substrate. Subsequently, a hole transport layer was formed by vacuum deposition of an NPD onto the hole injection layer.

[0352] Subsequently, a first light-emitting layer containing a first host material and a dopant material was deposited on top of the hole transport layer to a thickness of 5 nm, and then a second light-emitting layer containing a second host material and a dopant material was deposited on top of the first light-emitting layer to a thickness of 17.5 nm.

[0353] Next, BAlq was vacuum deposited onto the second light-emitting layer to form a hole-blocking layer, and Alq3 was deposited on the hole-blocking layer to form an electron-transport layer.

[0354] Subsequently, LiF was deposited on the electron transport layer to form an electron injection layer, and then Al was deposited on the electron injection layer to form a cathode.

[0355] (Example 2) A light-emitting element was manufactured in the same manner as in Example 1, except that a second light-emitting layer containing a second host material and a dopant material was deposited on top of the hole transport layer to a thickness of 17.5 nm, and then a first light-emitting layer containing a first host material and a dopant material was deposited on top of the second light-emitting layer to a thickness of 5 nm.

[0356] (Comparative example) A light-emitting element was manufactured in the same manner as in Example 1, except that a light-emitting layer containing a second host material and a dopant material was deposited on top of the hole transport layer to a thickness of 22.5 nm.

[0357] The light-emitting elements manufactured according to Examples 1 to 2 and Comparative Examples of the present invention were subjected to a pure bios DC voltage to measure their electroluminescent (EL) characteristics, and their T95 lifetime was measured using lifetime measurement equipment. The measurement results are shown in Table 1 below.

[0358] Table 1 JPEG0007871346000001.jpg59170

[0359] Figures 9a to 9d are graphs comparing Example 1 with the comparative example, and Figures 10a to 10d are graphs comparing Example 2 with the comparative example. As can be seen from the results in Table 1, when the first light-emitting layer is incorporated between the electron-blocking layer and the second light-emitting layer, as in Example 1, it can be confirmed that the efficiency and lifetime (T95) increase compared to the comparative example.

[0360] Furthermore, it can be confirmed that the lifetime (T95) increases compared to the comparative example when the first light-emitting layer is incorporated between the hole-blocking layer and the second light-emitting layer, as in Example 2.

[0361] A brief description of the embodiments of this disclosure described above is as follows.

[0362] A display device according to an embodiment of the present disclosure may include a substrate having a general region having a first resolution in which a plurality of first pixels are arranged and an optical region having a second resolution smaller than the first resolution in which a plurality of second pixels are arranged; a first electrode layer located on the substrate; a first light-emitting layer located on the first electrode layer and containing a first host in the general region and the optical region; a second light-emitting layer located on the first light-emitting layer and containing a first host in the general region and a second host different from the first host in the optical region; and a second electrode layer located on the second light-emitting layer.

[0363] In a display device according to an embodiment of the present disclosure, the first light-emitting layer and the second light-emitting layer each include a first dopant and a second dopant in the optical region, and the first dopant and the second dopant may be equal or different.

[0364] In the display device according to the embodiments of this disclosure, the first host and the second host may be phosphorescent hosts or fluorescent hosts, and the first dopant and the second dopant may be phosphorescent dopants or fluorescent dopants.

[0365] In the display device according to the embodiment of the present disclosure, the sum of the thicknesses of the first light-emitting layer and the second light-emitting layer in the optical region can be greater than the sum of the thicknesses of the first light-emitting layer and the second light-emitting layer in the general region.

[0366] A display device according to an embodiment of the present disclosure may further include a hole transport layer between the first electrode layer and the first light-emitting layer.

[0367] In a display device according to an embodiment of the present disclosure, the sum of the thicknesses of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the general region may be equal to the sum of the thicknesses of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the optical region.

[0368] A display device according to an embodiment of the present disclosure further includes a third light-emitting layer on the second light-emitting layer, wherein the third light-emitting layer may include the first host in the general region and the optical region.

[0369] In a display device according to an embodiment of the present disclosure, the third light-emitting layer in the optical region includes a third dopant, which may be equal to or different from the first dopant and the second dopant.

[0370] In the display device according to the embodiment of the present disclosure, the sum of the thicknesses of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region may be greater than the sum of the thicknesses of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region.

[0371] A display device according to an embodiment of the present disclosure may further include a hole transport layer between the first electrode layer and the first light-emitting layer.

[0372] In a display device according to an embodiment of the present disclosure, the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region may be equal to the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region.

[0373] A display device according to an embodiment of the present disclosure may further include an electron-blocking layer between the hole transport layer and the first light-emitting layer and a hole-blocking layer on the second light-emitting layer.

[0374] A display device according to an embodiment of the present disclosure may further include an electron-blocking layer between the hole transport layer and the first light-emitting layer and a hole-blocking layer on the third light-emitting layer.

[0375] A display device according to an embodiment of the present disclosure can satisfy the following formula 1 in the optical region, or at least one of the following formulas 2 or 3.

[0376] (Formula 1) T1 <T2<T HB

[0377] In the above formula 1,

[0378] T HB This is the triplet state energy level of the hole barrier layer,

[0379] T1 is the triplet state energy level of the first light-emitting layer,

[0380] T2 is the triplet state energy level of the second luminescent layer.

[0381] (Formula 2) L HB <L2<L1

[0382] In the above equation 2,

[0383] L HBThis is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole-blocking layer,

[0384] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer,

[0385] L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0386] (Formula 3) |H2-H1|≦0.1eV

[0387] In the above equation 3,

[0388] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer,

[0389] H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0390] In the display device according to the embodiments of this disclosure, the thickness of the second light-emitting layer may be 2 nm or more and 5 nm or less.

[0391] A display device according to an embodiment of the present disclosure can satisfy the following formula 4 in the optical region, or satisfy at least one of the following formulas 5 or 6.

[0392] (Formula 4) T2 <T1<T EB

[0393] In the aforementioned formula 4,

[0394] T EB This is the triplet state energy level of the electron barrier layer,

[0395] T1 is the triplet state energy level of the first light-emitting layer,

[0396] T2 is the triplet state energy level of the second luminescent layer.

[0397] (Formula 5) L 2< L1 <L EB

[0398] In the above equation 5,

[0399] L EB This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the electron barrier layer,

[0400] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer,

[0401] L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0402] (Formula 6) H2 EB

[0403] In the aforementioned formula 6,

[0404] H EB This is the HOMO (Highest Occupied Molecular Orbital) energy level of the electron barrier layer,

[0405] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer,

[0406] ​H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0407] In the display device according to the embodiments of this disclosure, the thickness of the first light-emitting layer may be 2 nm or more and 5 nm or less.

[0408] A display device according to an embodiment of the present disclosure satisfies either formulas 7 and 8 in the optical domain, or satisfies at least one of formulas 9, 10, 11, and 12.

[0409] (Formula 7) T1>T2

[0410] (Formula 8) T3 > T2

[0411] In equations 7 and 8,

[0412] T1 is the triplet state energy level of the first light-emitting layer,

[0413] T2 is the triplet state energy level of the second light-emitting layer,

[0414] T3 is the triplet state energy level of the third light-emitting layer.

[0415] (Formula 9) T EB >T1>T2

[0416] In the above formula 9,

[0417] T1 is the triplet state energy level of the first light-emitting layer,

[0418] T2 is the triplet state energy level of the second light-emitting layer,

[0419] TEB This is the triplet state energy level of the electron barrier layer.

[0420] (Formula 10) T HB >T3>T2

[0421] In the above formula 10,

[0422] T2 is the triplet state energy level of the second light-emitting layer,

[0423] T3 is the triplet state energy level of the third light-emitting layer,

[0424] T HB This is the triplet state energy level of the hole barrier layer.

[0425] (Formula 11) L1>L2

[0426] In the above equation 11,

[0427] L1 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer,

[0428] L2 is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer.

[0429] (Formula 12) H1>H2

[0430] In the above equation 12,

[0431] H1 is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer,

[0432] H2 is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

[0433] In the display device according to the embodiments of this disclosure, the thickness of the first light-emitting layer and the third light-emitting layer may be 2 nm or more and 5 nm or less.

[0434] A display device according to an embodiment of the present disclosure includes a general region in which a plurality of first subpixels are arranged and an optical region in which a plurality of second subpixels are arranged, wherein the number of second subpixels per unit area in the optical region is less than the number of first subpixels per unit area in the general region, and each of the first subpixels in the general region and each of the second subpixels in the optical region includes a light-emitting element, the light-emitting element includes a first electrode layer on a substrate, one or more stacks, and a second electrode layer on the one or more stacks, the one or more stacks may include a first light-emitting layer located on the first electrode layer and including a first host in the general region and the optical region, and a second host located on the first light-emitting layer and including a first host in the general region and different from the first host in the optical region.

[0435] The above explanation is merely illustrative of the technical concept of this disclosure, and a person with ordinary skill in the art to which this disclosure belongs could make various modifications and variations without deviating from the essential characteristics of this disclosure. Furthermore, the embodiments disclosed in this disclosure are for illustrative purposes only, not to limit the technical concept of this disclosure, and therefore the scope of the technical concept of this disclosure is not limited by such embodiments.

Claims

1. A substrate including a general region having a first resolution in which a plurality of first pixels are arranged, and an optical region having a second resolution smaller than the first resolution in which a plurality of second pixels are arranged, A first electrode layer located on the substrate, A first light-emitting layer located on the first electrode layer, comprising the general region and the optical region, and containing a first host, A second light-emitting layer located on the first light-emitting layer, which includes the first host in the general region and a second host different from the first host in the optical region, The invention includes a second electrode layer located on the second light-emitting layer, A display device in which the lifespan of the optical region is increased by using multiple light-emitting layers, including the first and second light-emitting layers, compared to the case in which only one light-emitting layer is used in the optical region.

2. The display device according to claim 1, wherein in the optical region, the first light-emitting layer and the second light-emitting layer each include a first dopant and a second dopant, and the first dopant and the second dopant are either the same or different.

3. The display device according to claim 2, wherein the first host and the second host are phosphorescent hosts or fluorescent hosts, and the first dopant and the second dopant are phosphorescent dopants or fluorescent dopants.

4. The display device according to claim 1, wherein the sum of the thicknesses of the first light-emitting layer and the second light-emitting layer in the optical region is greater than the sum of the thicknesses of the first light-emitting layer and the second light-emitting layer in the general region.

5. The display device according to claim 1, further comprising a hole transport layer between the first electrode layer and the first light-emitting layer.

6. The display device according to claim 5, wherein the sum of the thicknesses of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the general region is equal to the sum of the thicknesses of the hole transport layer, the first light-emitting layer, and the second light-emitting layer in the optical region.

7. The invention further includes a third light-emitting layer on the second light-emitting layer, The display device according to claim 2, wherein the third light-emitting layer includes the first host in the general region and the optical region.

8. The display device according to claim 7, wherein in the optical region, the third light-emitting layer includes a third dopant, and the third dopant is the same as or different from the first dopant and the second dopant.

9. The display device according to claim 7, wherein the sum of the thicknesses of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region is greater than the sum of the thicknesses of the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region.

10. The display device according to claim 9, further comprising a hole transport layer between the first electrode layer and the first light-emitting layer.

11. The display device according to claim 10, wherein the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the general region is equal to the sum of the thicknesses of the hole transport layer, the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer in the optical region.

12. The electron-blocking layer between the hole transport layer and the first light-emitting layer, The display device according to claim 5, further comprising a hole-blocking layer on the second light-emitting layer.

13. The electron-blocking layer between the hole transport layer and the first light-emitting layer, The display device according to claim 10, further comprising a hole-blocking layer on the third light-emitting layer.

14. The display device according to claim 12, wherein the optical region satisfies formula 1 below, or at least one of formulas 2 or 3 below: (Formula 1) T １ <T ２ <T ＨＢ In the above formula 1, T ＨＢ This is the triplet state energy level of the hole barrier layer, T １ This is the triplet state energy level of the first light-emitting layer, T ２ This is the triplet state energy level of the second light-emitting layer, (Formula 2) L ＨＢ <L ２ <L １ In the above equation 2, L ＨＢ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the hole blocking layer, L １ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, L ２ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer, (Formula 3) |H ２ -H １ |≦0.1eV In the above equation 3, H １ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, H ２ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

15. The display device according to claim 14, wherein the thickness of the second light-emitting layer is 2 nm or more and 5 nm or less.

16. The display device according to claim 12, wherein the optical region satisfies the following formula 4, or satisfies at least one of the following formulas 5 or 6: (Formula 4) T ２ <T １ <T ＥＢ In the aforementioned equation 4, T ＥＢ This is the triplet state energy level of the electron barrier layer, T １ This is the triplet state energy level of the first light-emitting layer, T ２ This is the triplet state energy level of the second light-emitting layer, (Formula 5) L ２ <L １ <L ＥＢ In the above formula 5, L ＥＢ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the electron barrier layer, L １ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, L ２ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer, (Formula 6) H ２ <H １ <H ＥＢ In the aforementioned formula 6, H ＥＢ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the electron barrier layer, H １ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, H ２ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

17. The display device according to claim 16, wherein the thickness of the first light-emitting layer is 2 nm or more and 5 nm or less.

18. The display device according to claim 13, which satisfies the following formulas 7 and 8 in the optical region, or satisfies at least one of the following formulas 9, 10, 11, and 12: (Formula 7) T １ >T ２ (Formula 8) T ３ >T ２ In equations 7 and 8, T １ This is the triplet state energy level of the first light-emitting layer, T ２ This is the triplet state energy level of the second light-emitting layer, T ３ This is the triplet state energy level of the third light-emitting layer, (Formula 9) T ＥＢ >T １ >T ２ In the above formula 9, T １ This is the triplet state energy level of the first light-emitting layer, T ２ This is the triplet state energy level of the second light-emitting layer, T ＥＢ This is the triplet state energy level of the electron barrier layer, (Formula 10) T ＨＢ >T ３ >T ２ In the above formula 10, T ２ This is the triplet state energy level of the second light-emitting layer, T ３ This is the triplet state energy level of the third light-emitting layer, T ＨＢ This is the triplet state energy level of the hole barrier layer, (Formula 11) L １ >L ２ In the above formula 11, L １ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the first light-emitting layer, L ２ This is the LUMO (Lowest Unoccupied Molecular Orbital) energy level of the second light-emitting layer, (Formula 12) H １ >H ２ In the above formula 12, H １ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the first light-emitting layer, H ２ This is the HOMO (Highest Occupied Molecular Orbital) energy level of the second light-emitting layer.

19. The display device according to claim 18, wherein the thickness of the first light-emitting layer and the third light-emitting layer are 2 nm or more and 5 nm or less.

20. A general region in which multiple first subpixels are arranged, An optical region in which multiple second subpixels are arranged, The number of second subpixels per unit area in the optical region is less than the number of first subpixels per unit area in the general region. Each of the first subpixels in the general region and each of the second subpixels in the optical region include an light-emitting element. The light-emitting element is A first electrode layer on the substrate, One or more stacks, The stack includes a second electrode layer on one or more stacks, Each of the aforementioned one or more stacks is: A first light-emitting layer located on the first electrode layer, comprising the general region and the optical region, and containing a first host, A second light-emitting layer located on the first light-emitting layer, which includes the first host in the general region and a second host different from the first host in the optical region, is included. A display device in which the lifespan of the optical region is increased by using multiple light-emitting layers, including the first and second light-emitting layers, compared to the case in which only one light-emitting layer is used in the optical region.

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