Atomic layer etching by electron wavefronts

Abstract

We present atomic layer etching (ALE) of substrates using precisely controlled wafer-scale waves of electrons. A gaseous plasma volume containing a uniform steady-state composition of diluent, reactive species, and electrons is generated in the positive column of a direct-current plasma close to the substrate. A corrosion layer forms on the substrate through adsorption of reactive species to atoms at the substrate surface. The substrate is positively biased to attract electrons from the volume to the substrate surface, energizing the electrons to stimulate electronic transitions of the corrosion layer species, resulting in their expulsion via electron-stimulated desorption (ESD). The substrate is negatively biased to repel electrons from the substrate surface back into the volume, followed by zero bias to restore the steady-state composition of the volume.

Description

[Technical Field] 【0001】 [Cross-references to related applications] This application claims priority to U.S. Application No. 18 / 149,893, filed on 4 January 2023, entitled “Atomic Layer Etching by Electron Wavefront,” the contents of which are incorporated herein by reference. Furthermore, this application relates to U.S. Application No. 17,524,330, filed on 11 November 2021, entitled “DC Plasma Control for Electron Enhanced Material Processing” (Patent Attorney Docket No. P2641-US), the entire disclosure of which is incorporated herein by reference. This application is further related to U.S. Patent Application No. 17,668,301, filed on 9 February 2022, entitled “Electron Bias Control Signals for Electron Enhanced Material Processing” (Patent Docket No. P2645-US), the entire disclosure of which is incorporated herein by reference. 【0002】 This disclosure generally relates to systems and methods for material processing, including atomic layer etching in a DC plasma at room temperature (or other temperatures if desired). This disclosure generally relates to systems and methods for controlling free electrons in a DC plasma reaction chamber used for material processing, in particular to the generation of waveforms for bias signals to control the kinetic energy of free electrons to generate precisely controlled wafer-scale waves of electrons in a DC plasma at room temperature (or other temperatures if desired). [Background technology] 【0003】 For example, the manufacturing of integrated circuits involves a step of processing a corresponding substrate in a DC plasma reaction chamber, in which electrons and / or ions are accelerated toward the substrate surface, initiating a reaction that physically alters the substrate surface. In some cases, and primarily because electrons have a relatively small mass compared to ions, electron-mediated substrate processing may be preferable to reduce damage to the substrate surface beyond the target physical changes expected by the processing step itself. 【0004】 In some cases, plasma treatment may involve positioning the substrate within a region of a DC plasma reaction chamber so that the exact value of the substrate's surface stray potential is unknown. Therefore, an externally applied bias signal to the substrate may impart free electron energy in the plasma region near the substrate surface, and this energy does not correlate with the electron energy threshold / level of the (atomic) material present on the substrate surface. 【0005】 U.S. Patent Application No. 17,524,330, referenced above, whose entire disclosure is incorporated herein by reference, describes a method and system for precisely and selectively controlling the values ​​of surface stray potentials of a substrate, and thus precisely and selectively controlling the energy levels of atoms on the substrate surface. U.S. Patent Application No. 17,668,301, referenced above, whose entire disclosure is incorporated herein by reference, utilizes such precise and selective control of the energy levels of atoms on a substrate surface to generate waveforms of timing and amplitude corresponding to signals used to bias free electrons in a DC plasma chamber, so as to generate wafer-scale waves that specifically target the energy levels of atoms on the substrate surface. 【0006】 The teachings in this disclosure utilize the ability to generate wafer-scale electron waves (e.g., electron wavefronts) that specifically target the energy levels of atoms on the substrate surface in order to etch away atomic layers of the substrate. [Overview of the project] 【0007】 Systems and methods are disclosed for material processing, particularly atomic layer etching (ALE), using precisely controlled wafer-scale electron waves in a DC plasma at room temperature (or other temperatures as necessary). In this disclosure, such material processing is referred to as electron-enhanced material processing (EEMP), where the kinetic energy of free electrons in the DC plasma can be precisely (and selectively) targeted to the electron energy levels of atoms on the substrate surface being processed. Such atoms may include atoms of an adsorbed layer above the outermost atomic layer of the substrate. Under the local conditions created through the methods and systems of this teaching, the low energy of free electrons reaching the substrate surface as electron wavefronts can promote the desorption of the adsorbed layer along with the surface atomic layer of the substrate directly beneath them. 【0008】 According to a first embodiment of the present disclosure, a method for atomic layer etching of a substrate is disclosed, comprising the steps of: generating a gaseous plasma amount containing a diluent species, a reactive species, and electrons of a uniform steady-state composition in a positive column of DC plasma adjacent to the substrate, thereby generating a floating potential on the substrate surface; adjusting the floating potential to a reference potential; forming a corrosion layer on the substrate, the corrosion layer comprising corrosion layer species formed by the adsorption of reactive species to atoms of an atomic layer on the substrate surface; applying a positive bias potential to the substrate relative to the floating potential; drawing electrons from the gaseous plasma amount to the substrate surface based on the step of applying the bias potential, assigning energy levels to the drawn electrons to stimulate electron transitions of the corrosion layer species; and detaching the corrosion layer based on the stimulating step, thereby etching and removing the atomic layer. 【0009】 A second embodiment of the present disclosure discloses a method for atomic layer etching of a substrate via an electron wavefront, comprising the steps of: generating a gaseous plasma amount containing a diluent species, a reactant species, and electrons of a uniform steady-state composition within a positive column of DC plasma adjacent to the substrate, thereby generating a floating potential on the substrate surface; adjusting the floating potential to a reference potential; and applying a sequence of periodic bias signals to the substrate, wherein the periodic bias signal is a reference to the reference potential, and the sequence is a positive bias potential followed by a negative bias potential, and then a zero bias potential equal to the reference potential, thereby causing the arrival of an electron wavefront having uniform energy and density across the entire surface of the substrate at arrival times predetermined by the periodic bias signal, wherein at each arrival time, the electron wavefront stimulates electron transitions in an erosion layer formed on the substrate surface, thereby etching one atomic layer in the substrate. 【0010】 Further aspects of this disclosure are shown in the specification, drawings and claims of this application. [Brief explanation of the drawing] 【0011】 The accompanying drawings incorporated herein and constituting part thereof illustrate one or more embodiments of the present disclosure and, together with the description of exemplary embodiments, are useful in illustrating the principles and embodiments of the present disclosure. [Figure 1A] This is a simplified schematic diagram of a DC plasma reaction chamber that can be used in a DC plasma processing system. [Figure 1B] Figure 1A is a graph showing the change in the (electrical) potential of the plasma during operation of the DC plasma reaction chamber. [Figure 1C] Figure 1A shows a simplified schematic diagram of a DC plasma processing system, including a (substrate) stage located in the region of the DC plasma reaction chamber. [Figure 1D] Figure 1C shows an exemplary bias of the stage of the DC plasma processing system via an external bias signal generator. [Figure 1E]Figure 1D shows an exemplary bias signal generated by the external bias signal generator and the potential generated on the corresponding stage surface. [Figure 1F] This shows exemplary energy levels of atoms on the surface of the stage. [Figure 2A] A simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, which includes means for controlling the surface potential of a stage, is shown. [Figure 2B] Figure 2A is a graph showing the control of the surface potential of the stage in the DC plasma processing apparatus. [Figure 2C] Figure 2A is a graph showing the adjustment of the stage surface potential relative to the reference ground potential of the DC plasma processing system. [Figure 3A] A simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure is shown, comprising means for controlling the surface potential of a stage and means for measuring the surface potential. [Figure 3B] A simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure is shown, based on the system of Figure 3A, which has been modified to include means for automatic control of the surface potential. [Figure 4A] This is a simplified schematic diagram of a DC plasma processing system according to one embodiment of the present disclosure, based on the system in Figure 3B, in which a biasing means for the stage has been added. [Figure 4B] Figure 4A shows an exemplary bias signal supplied to the stage of the DC plasma processing system and the potential generated at the corresponding stage surface. [Figure 4C] This shows exemplary energy levels of atoms on the surface of the stage. [Figure 5] This is a process chart illustrating various steps of a method according to one embodiment of the present disclosure for treating the surface of a substrate. [Figure 6A] This graph shows the reaction rates of electron-accelerated material processing (EEMP) on different materials, as disclosed herein. [Figure 6B]This graph shows the reaction rates of electron-accelerated material processing (EEMP) on different materials, as disclosed herein. [Figure 6C] This graph shows the reaction rates of electron-accelerated material processing (EEMP) on different materials, as disclosed herein. [Figure 7A] This is a graph showing the waveform of the EEMP bias signal for processing different materials according to some exemplary embodiments of the present disclosure. [Figure 7B] This is a graph showing the waveform of the EEMP bias signal for processing different materials according to some exemplary embodiments of the present disclosure. [Figure 7C] This is a graph showing the waveform of the EEMP bias signal for processing different materials according to some exemplary embodiments of the present disclosure. [Figure 8A] This graph shows the idealized waveform of the EEMP bias signal. [Figure 8B] This graph shows the actual waveform of the EEMP bias signal. [Figure 8C] This graph shows the analog waveform under capacitive load conditions. [Figure 9A] Figure 8B is a graph showing the digitized waveform used to generate the practical waveform, and the corresponding digitized waveform with pre-distortion. [Figure 9B] This graph shows the analog waveform generated from the digitized waveform with pre-distortion shown in Figure 9A, under capacitive load conditions. [Figure 10A] This graph shows the gain-to-frequency ratio of a band-limited linear power amplifier according to an embodiment of the present disclosure, and the gain-to-frequency ratio of a conventional power amplifier. [Figure 10B] This graph shows the analog waveform generated from the pre-distorted digitized waveform in Figure 9A via the band-limited linear power amplifier in Figure 10A, under capacitive load conditions. [Figure 11] This is a process chart illustrating various steps of a method for treating the surface of a substrate according to another embodiment of the present disclosure. [Figure 12A]This disclosure shows various schematic diagrams representing the initialization task of a DC plasma reaction chamber and the corresponding states in preparation for atomic layer etching (ALE) of a substrate surface via electron-accelerated material processing (EEMP) as described herein. [Figure 12B] This disclosure shows various schematic diagrams representing the initialization task of a DC plasma reaction chamber and the corresponding states in preparation for atomic layer etching (ALE) of a substrate surface via electron-accelerated material processing (EEMP) as described herein. [Figure 12C] This disclosure shows various schematic diagrams representing the initialization task of a DC plasma reaction chamber and the corresponding states in preparation for atomic layer etching (ALE) of a substrate surface via electron-accelerated material processing (EEMP) as described herein. [Figure 13A] The following schematic diagrams represent various states of the DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to this disclosure. [Figure 13B] The following schematic diagrams represent various states of the DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to this disclosure. [Figure 13C] The following schematic diagrams represent various states of the DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to this disclosure. [Figure 13D] The following schematic diagrams represent various states of the DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to this disclosure. [Figure 13E] The following schematic diagrams represent various states of the DC plasma reaction chamber during the active phase of atomic layer etching (ALE) according to this disclosure. [Figure 14] This is a schematic diagram that typically shows the state of the DC plasma reaction chamber during the neutralization phase of atomic layer etching (ALE) according to this disclosure. [Figure 15] This is a schematic diagram that typically shows the state of the DC plasma reaction chamber during the initialization phase of atomic layer etching (ALE) according to this disclosure. 【0012】 Similar reference numbers and symbols in various drawings indicate the same elements. [Modes for carrying out the invention] 【0013】 Figure 1A shows a simplified schematic diagram of a conventional DC plasma reaction chamber (110) that may be used in a DC plasma processing system. The bias of the DC plasma reaction chamber (110) may be provided by a DC voltage source (150) coupled between the anode A and cathode C of the DC plasma reaction chamber (110). During operation, a glow discharge (plasma) may be formed within the chamber (110) based on the interaction of the gas with the electrons of the current flowing between anode A and cathode C. This generates free ions and free electrons within the chamber. The operating principle of such a DC plasma reaction chamber (110) is well known to those skilled in the art, and therefore relevant details are omitted in this disclosure. 【0014】 As shown in Figure 1A, the glow discharge formed within the chamber (110) may include glow regions (G1, G2, G3, G4) that emit considerable light and dark regions (D1, D2, D3, D4) that may not emit light. Such regions may represent different operating characteristics of the DC plasma reaction chamber (110), including, for example, temperature and potential. 【0015】 Figure 1B shows the (electrical) potential V of the plasma along the axial direction (longitudinal direction) X of the operating chamber (110). PP This is a graph showing the change in plasma potential V, as shown in Figure 1B. PP V represents the potential applied to cathode C by the DC voltage source (150 in Figure 1A). C Therefore, V represents the potential applied to anode A by the DC voltage source (150 in Figure 1A). A It changes up to a certain value. For example, as shown in Figure 1D below, the value is generally V. A This is zero volts (e.g., reference ground), and the value is V C It should be noted that this value is negative (for example, a negative value within the range of approximately 0 to 500 volts). 【0016】 Continuing to refer to FIG. 1B, the potential V in regions close to the cathode C (e.g., D1, G1, D2) and regions close to the anode A (e.g., G4) PP of the abrupt variation may correspond to a region of higher operating temperature of the chamber (110). The other region G3, also called the plasma column, is a region of a somewhat uniform / constant potential, V PP and a region of low operating temperature. For example, as shown in FIG. 1B, considering that a segment [X G31 , X G32 along the axial direction X of the chamber (110) is included within the plasma column region G3, the variation of the plasma potential V G31 , X G32 across such a segment [X PP is minimal. In other words, it can be considered that the potential V G31 , X G32 across the segment [X PP is constant. Therefore, as shown in FIG. 1B, it can be considered that the plasma potential V G31 , X G32 across the segment [X pp is equal to the value V G3 . Due to the lower operating temperature and the constant potential value of the plasma in the plasma column region G3, as shown in FIGS. 1C and 1D, such a region can be used for substrate processing. 【0017】 ' FIG. 1C shows a simplified schematic diagram of a DC plasma processing system (100C) including a (substrate) stage S disposed in the plasma column region G3 of a DC plasma reaction chamber (110). The stage S may be designed to support a flat substrate and thus may include a flat surface on the upper surface. The stage S shown in FIG. 1C is electrically insulated (not connected to an external potential). Thus, as is well known to those skilled in the art, in the presence of the plasma potential V PP , a potential V S is generated on the surface of the stage S, and this potential V S is referred to as the surface floating potential V FP . The (surface) floating potential V FP and the plasma potential V PPThe relationship is shown in Figure 1C. In particular, as shown in Figure 1C, the region [X] of the chamber (110) where the stage S is located G31 , X G32 Plasma potential V in ] PP is V G3 Equal to the floating potential V FP The plasma potential is V G3 Lower than (Plasma potential V G3 (It is negative to [the specified value].) 【0018】 The floating potential V shown in the graph in Figure 1C FP This can be due to a “plasma sheath” that develops in the presence of stage S. As is known to those skilled in the art, a negative potential is generated at walls or barriers within a plasma relative to the plasma bulk. As a result, an equilibrium potential drop occurs between the plasma bulk and the wall or barrier. Such a potential drop is confined to a small region of space adjacent to the wall or barrier due to a charge imbalance between the plasma and the wall or barrier. This layer of charge imbalance has a finite thickness characterized by a Debye length and is called a “plasma sheath” or “sheath”. The thickness of such a layer is several Debye lengths, and its magnitude depends on various properties of the plasma. If the dimensions of the bulk plasma (e.g., chamber 110) are much larger than, for example, the Debye length, then the Debye length depends on the plasma temperature and electron density. In certain cases of DC plasma operating conditions supported by the teachings of this disclosure (e.g., EEMP systems near to moderately above room temperature), the Debye length is on the order of several millimeters (e.g., less than 10 millimeters), and the potential V G3 and V FP The difference between these is on the order of a few volts (e.g., less than 10 volts). It should be noted that plasma sheath can occur in the presence of any wall or barrier, whether conductive or not. Therefore, once the substrate (whether conductive or insulating) is placed on the stage S, the same floating potential V described above, with reference to Figure 1C, is present. FP This can occur on the surface of the substrate. 【0019】 Figure 1D shows an exemplary bias application to the stage S of the DC plasma processing system in Figure 1C via an external bias signal generator (180) capacitively coupled to the stage S by a capacitor C. In the exemplary configuration (100D) shown in Figure 1D, the potential V applied to the anode A is A The voltage is zero volts (e.g., coupled to the reference earth, Gnd). Furthermore, as shown in Figure 1D, a bias signal V is applied to the stage S by an external bias signal generator (180). B The reference can be the reference to the reference earth potential Gnd. In some embodiments of the prior art, the bias signal V B Although the stage S may be DC-coupled, the teachings of this disclosure strictly prohibit such DC coupling to the stage in order to avoid the discharge path of the DC current passing through any intermediate point in the chamber (110), as this could significantly alter the operating conditions within the chamber (110). 【0020】 In the DC plasma processing system shown in Figure 1D, the bias signal V B This refers to the potential observed by free electrons and / or ions near the stage S, or, if present, the substrate (e.g., surface potential V). S ) can be used to control the energy of free electrons and / or ions. This allows the energy of free electrons and / or ions to be controlled to the material-specific levels required for the (optimal) processing of the substrate. For example, as shown in the graph on the left side of Figure 1E, the bias signal V generated by an external bias signal generator (e.g., 180 in Figure 1D) B It starts from zero and increases the voltage amplitude V in a short time. B1 It can reach (represented by the leading edge slope). As shown in the upper right graph of Figure 1E, the voltage amplitude V during processing step (a) B1 When applied to stage S (e.g., AC coupling), the voltage amplitude V B1 V is the surface floating potential. FPa It is added (or subtracted if negative) to the surface potential V near stage S. S This occurs. However, free electrons and / or ions are at the plasma potential V PPaBecause of its location, what is observed by free electrons and / or ions is the plasma potential V PPa Surface potential V greater than S This is only a part of it. For example, as shown in the upper right graph of Figure 1E, the (kinetic) energy of free electrons and / or ions is Potential difference V KEa =(V B1 -ΔV FPa ) may also be based on this, and here, ΔV FPa ,=(V PPa -V FPa ) 【0021】 On the other hand, there is a different difference ΔV FPb ,=(V PPb -V FPb ) may occur, different plasma potentials V PPb , or different floating potentials V FPb Considering the processing step (b), represented by the graph in the lower right of Figure 1E, which may have different operating conditions than the processing step (a) that includes the same applied voltage amplitude V B1 For this to occur, different (kinetic) energies of free electrons and / or ions can be obtained. The teachings of this disclosure eliminate and / or compensate for variations in operating conditions within the chamber (e.g., 110 in Figure 1D) to enable precise control of the energy of free electrons (and / or ions), for example. It should be noted that variations in operating conditions are to be expected when considering different types of operations performed within the chamber (110) (e.g., Figures 1E(a) and (b)), including etching of a substrate with different reactive gases, cleaning of a substrate, or other processes that may change and / or remove composition / materials from the surface of a substrate. As is known to those skilled in the art, it should be noted that different operating conditions for performing different types of operations may further include corresponding variations and / or adjustments to any one of the DC plasma current, temperature, gas mixture, or flow rate within the chamber (110). 【0022】 When the substrate is placed on the surface of the stage S, the bias signal V described above is received. BThe kinetic energy of free electrons and / or ions obtained by applying a potential can accelerate the free electrons and / or ions toward the substrate surface, potentially causing them to collide with the substrate and release their kinetic energy into atoms on the substrate surface. However, these atoms are affected by the potential in which they exist, in other words, the stray potential, V FP The energy levels are based on the following. Referring to Figure 1E, the various energy levels of one such atom for the processing type (a) described above are the energy levels of the nuclei of the atoms on the substrate surface E n , the energy level E of electrons bonded to the atomic nuclei of atoms on the substrate surface B , and the energy level E of electrons in the orbitals of electrons bonded to atomic nuclei on the substrate surface e This is shown in Figure 1F. 【0023】 As can be seen in Figure 1F, the energy level E of the atomic nucleus n V is a (negative) potential. FPa It is located at the electron energy level E e is (negative) potential (E n +E B ) is located at. In other words, to excite an atom to an energy level that breaks the bond between the electron and the nucleus, the electron's energy level E e Energy equal to or greater than this must be imparted to the atoms. Therefore, considering a plasma processed only through free electrons, the potential difference V in Figure 1F KEa =(V B1 -ΔV FPa The bias signal V is represented by ). B The kinetic energy of the free electrons supplied by the application of is the energy level E e It must be equal to or greater than [a certain value]. However, E e =(E n +E B ) and E n The a priori unknown floating potential V FPa Because it is based on, energy level E e It may be impossible to precisely control the kinetic energy of free electrons in order to accurately target a target. 【0024】 Floating potential (for example, V in Figure 1F) FPa The stray potential can be determined empirically and / or experimentally for a given process under stable operating conditions of a DC plasma chamber; however, inconsistencies and / or lack of reproducibility of such operating conditions may invalidate the determined stray potential. Furthermore, since different types of processes yield inherently different stray potentials, the task of precisely controlling the kinetic energy of free electrons to precisely target the energy levels of atoms on the substrate surface may be impractical. Consequently, in some embodiments of the prior art, atoms on the substrate surface may be imparted with kinetic energy substantially greater than the energy level of the target atom, thus lacking selectivity (because atoms of different materials / compositions with different energy levels may receive equally high energy levels sufficient to break orbital bonds). Electron-assisted material processing (EEMP) according to the teachings of this disclosure overcomes these drawbacks and thus enables precise control of the kinetic energy of free electrons to precisely and selectively target the energy levels of atoms on the substrate surface. 【0025】 Figure 2A shows a simplified schematic diagram of a DC plasma processing system (200A) according to one embodiment of the present disclosure, which includes means (250, 260) for controlling the surface potential of the stage S when electrically insulated. In other words, these means (250, 260) control the stray potential V FP This allows for adjustment of the voltage. As shown in Figure 2A, the means (250, 260) includes an adjustable DC voltage source (250) coupled to anode A of the DC plasma reaction chamber (110) and a DC current source (260) coupled to cathode C of the DC plasma reaction chamber (110). Thus, the potential VA of anode A can be controlled to be in the range of zero volts or greater (positive) relative to reference earth (Gnd at zero volts), and the (drain) current Ip flowing between anode A and cathode C through the reaction chamber (110) can be set by the DC current source (260). Thus, the potential V of cathode C Cis not forced by an external DC voltage source (e.g., 150 in FIG. 1D), but rather (floats) settles to a (negative) voltage based on the adjustable potential V of anode A A and the set current Ip. Such a configuration establishes and maintains a higher level of process stability and optimization by maintaining a constant set current Ip through the reaction chamber (110) while independently controlling / adjusting the floating potential V FP . 【0026】 FIG. 2B is two graphs representing the control of the surface potential V FP of stage S of the DC plasma processing system (200A) described above with reference to FIG. 2A. In particular, FIG. 2B shows two graphs distinguished by the use of solid or dashed lines, and each graph shows the plasma potential V A1 across the longitudinal extent X of the chamber (110) for two different voltages (V A2 ) applied to anode A by an adjustable DC voltage source (250). As seen in FIG. 2B, for a positive step increase in the anode potential, +ΔV PP from voltage V A1 to voltage V A2 , the floating potential (V 12 , V FP1 ) and the cathode potential (V FP2 , V C1 ) increase by the same positive step, +ΔV C2 . In fact, as shown in FIG. 2B, for the entire plasma potential V 12 , the curve shifts positively by only the step +ΔV PP . In other words, for any longitudinal coordinate X within the range [X 12 , X C , X A , the corresponding plasma potential V PP (X) follows the step increase, +ΔV 12 . A similar behavior applies to a negative step variation applied to anode A by the adjustable DC voltage source. In other words, the control of the potential of anode A by the adjustable DC voltage source linearly affects the plasma potential V PP at any longitudinal coordinate X, and thus the floating potential VFP and the voltage V at the top of stage S S This linearly affects the floating potential V when operating a DC plasma chamber for different types of material processing. As described later in this disclosure, such linearity affects the floating potential V FP This teaching can be used in an EEMP system to implement a closed-loop control subsystem that automatically controls the value to a preset value (e.g., zero volts). 【0027】 Figure 2C shows the anode voltage V A1 Refer to Figure 2B to see two graphs similar to the graph described above, including the special case where is equal to zero volts (solid line). As seen in Figure 2B, the stray potential voltage in such a case is a negative value V FP1 Equal to, therefore, plasma potential V PP It is negative for (and below). Furthermore, as can be seen in Figure 2C, the positive step increase of the anode potential, +ΔV 13 =(V A1 -V FP1 For ) the stray potential is a value equal to zero volts V FP3 It can be adjusted to the floating potential V. According to one embodiment of the present disclosure, the floating potential V FP Such zeroing can enable precise control of the kinetic energy of free electrons in a DC plasma to precisely (and selectively) target the energy levels of atoms on the surface of the substrate being processed (whether conductive or insulating). In other words, referring back to Figure 1F, the energy levels E of the nuclei of the atoms targeted / selected for processing. n The a priori unknown floating potential that determines this is the floating potential V FP It is removed by zeroing out. On the other hand, as shown in Figure 4B below, this removes the energy level E of the target electron. e , the kinetic energy levels of free electrons in a DC plasma (for example, V in Figure 1F) KEa ), and the bias voltage V applied to stage S B This makes it possible to use the same known and fixed reference, the zero-volt potential Gnd, as the reference. (Floating potential V) FPWhile the provision of known energy levels can be provided by zeroing out such potentials as described above, it should be noted that such zeroing should not be considered limiting to the scope of this disclosure, as other preset / tuned non-zero values ​​of the floating potential can similarly function as reference potentials for precisely controlling the kinetic energy of free electrons in a DC plasma in order to precisely (selectively) target the energy levels of atoms on the surface of the substrate being processed (whether conductive or insulating). 【0028】 Figure 3A shows the means for controlling the surface potential of stage S (250, 260 in Figure 2A) and the surface potential V at the top of the stage. S (For example, floating potential, V FP ) means for measuring (R, 311, V in Figure 3A) R A simplified schematic diagram of a DC plasma processing system (300A) according to an embodiment of the present disclosure, comprising the following: As will be understood by those skilled in the art, the system (300A) has a surface potential V S Means for measuring (R, 311, V R ), or in other words, the floating potential V at the top (surface) of the stage. FP Means for measuring (R, 311, V R The addition of ) represents an improvement to the system (200A) described above, with reference to Figure 2A. Floating potential V FP By enabling such measurements, the adjustment of the DC voltage source (250) as described above (see Figures 2A-2C) can be performed to measure the surface potential V FP This can be done while monitoring / measuring the floating potential V. This includes, for example, setting such a potential to zero (VFP = 0 volts). FP This will enable precise control. 【0029】 Continuing to refer to Figure 3A, the means (R, 311, V RThe stage S includes a reference plate R positioned within the DC plasma chamber (110) in the same (longitudinal coordinate) segment [XG31, XG32] as the stage S. The reference plate R may be made of any conductive material capable of withstanding the (internal) operating conditions of the chamber (110) and may have any planar shape, including, for example, a square, rectangle, circle, pentagon, trapezoid or other planar shape. The reference plate R is positioned in the same region as the stage S and therefore at the same substantially constant plasma potential V PP Because it is positioned in the region, the reference plate R has the same floating potential V as the stage S. FP Look at this. In other words, the (surface) potential V at the reference plate R. R By measuring this, the stray potential at stage S can be determined. The insulated conductive wire (311) attached to the reference plate R has a potential of V. R This can be used to route / couple to measuring electronic equipment (e.g., a transducer) installed outside the chamber (110). It should be noted that such measuring electronic equipment should not provide a DC current path to the plasma through the plate R. 【0030】 Continuing to refer to Figure 3A, the location of the reference plate R may be any longitudinally extending portion of the chamber (110) within a technically viable and practical segment [XG31, XG32]. The chamber (110) may include an access door adjacent to the stage S on one side of the chamber (110), and in some exemplary embodiments, the reference plate R may be positioned against or near the wall of the chamber (110) on the opposite side of the access door and the stage S. Furthermore, according to exemplary embodiments, the center R of the reference plate and the center of the stage S (e.g., the intersection of the two T-shaped segments of the stage as shown in the figure) may be contained within a line perpendicular to the axial direction of the chamber (110) (e.g., the center line, the direction of the longitudinally extending portion). The applicant of this disclosure has found that in tracking the floating potential of the stage S, means (R, 311, V R We confirmed that the accuracy of ) is high. 【0031】 Figure 3B shows the surface potential V at stage S, based on the system (300A) in Figure 3A. FP A simplified schematic diagram of a DC plasma processing system (300B) according to an embodiment of the present disclosure is shown, with the addition of means (320, CT) for automatic control of the floating potential V at the stage S while operating the DC plasma chamber for different types of processing. FP The control electronics (320) is configured to incorporate a closed-loop control system that automatically controls the value of to a preset value (e.g., zero volts). In particular, as shown in Figure 3B, the control electronics (320) controls the (surface) potential V of the reference plate R via coupling provided by an insulated conductive wire (311). R The input is taken, and the voltage V supplied from there to anode A is then taken. A To adjust this, a control (error) signal CT is generated, and therefore, as described above with reference to Figures 2A-2C, the floating potential V at stage S is generated. FP Adjust the control (error) signal CT, for example, a floating potential V such as zero volts. FP It can be generated with respect to the desired target / preset value. Those skilled in the art are familiar with the design techniques for implementing control electronics (320) which are outside the scope of this disclosure. In particular, those skilled in the art are familiar with the use of operational amplifiers or error amplifiers in such control electronics (320), where the input to such an amplifier is a potential V R , and floating potential V FP It can be coupled to a desired target / preset value (e.g., zero volts) and generate an error signal (e.g., CT) based on the input difference. 【0032】 Figure 4A shows the biasing means (C) for biasing stage S. S A simplified schematic diagram of a DC plasma processing system (400A) according to one embodiment of the present disclosure is shown, based on the system of Figure 3B with added bias means (C). S , 480) is the capacitor C of the biasing means. SIt includes a bias signal generator (480) which is coupled to the stage S via the bias signal generator (480). In other words, the bias signal V generated at the output of the bias signal generator (480) B is a capacitor C S Capacitively coupled to stage S via . As already described in this disclosure, such capacitive coupling allows for the removal of any DC current paths from or to the DC plasma chamber (110), thereby preventing any undesirable perturbations to the operating conditions of the chamber (110). The bias signal generator (480) generates a bias signal V according to desired characteristics, for example, amplitude, frequency, duty cycle and / or rising / falling edge / slope. B It should be noted that this may include a programmable waveform generator configured to output the waveform of V. Furthermore, stage S receives the bias signal V. B A first conductive part (e.g., capacitor C) for electrically coupling to the stage S S It should be noted that the stage may include a vertical lead connected to the stage and a second part of the stage (e.g., a horizontal support plate) which may include conductive and / or insulating materials. 【0033】 Figure 4B shows an exemplary bias signal V supplied to stage S of the DC plasma processing system (400A) shown in Figure 4A. B1 , and the corresponding surface potential V generated on the surface of stage S S This is shown. As will be clearly understood by those skilled in the art, the graph shown in Figure 4B represents the floating potential V. FP This corresponds to the configuration of a system (400) that is adjusted or controlled so that the potential difference V is zero. Thus, considering the above description with reference to Figure 1E (or in contrast), the (kinetic) energy of free electrons and / or ions attracted to the stage S or the surface of the substrate thereon is the potential difference V KE =(V B1 -ΔV FP ) is based on ΔV FP =(V PP -V FPTherefore, for practical substrate processing applications using a DC plasma chamber, ΔV FP The value of is V KE The value of (for example, the energy level E of the target electron in Figure 4C) e Because the approximation V may be considerably smaller (for example, a ratio of 1 / 50 or less) than the approximation V (based on the approximation V), KE =V B1 This is considered reasonable. On the other hand, a bias signal V is provided to the stage S for performing electron-assisted material processing (EEMP) as taught in this disclosure, which precisely and selectively targets the energy levels of atoms (e.g., bound electrons) on the surface of the substrate. B1 This makes simple and easy generation possible. 【0034】 Referring further to Figures 4A and 4B, the excitation of atomic energy levels on the surface of the stage S, or on the surface of the substrate placed on the stage S, is mainly due to the surface potential V S It should be noted that this may also be based on instantaneous changes. Therefore, the excitation of the energy levels is based on the target value V of the bias voltage. B1 This can be achieved immediately at the end of the transition to, in other words, at the end of the slope shown in Figure 4B. 【0035】 Figure 4C shows exemplary energy levels of atoms on the surface of stage S of the DC plasma processing system (400A) of Figure 4A. Figure 4C is based on the reference plate R as described above with reference to Figures 2A-2C, as described above with reference to Figure 3A, as well as on the (optional) closed-loop control system provided by control electronics (320) as described above with reference to Figure 3B, and as well as on the capacitive coupling of the bias signal VB provided by the bias signal generator (480) as described above with reference to Figure 4A, with respect to the floating potential V FP Based on the zeroing of the atoms, the energy levels of atoms on the substrate surface (for example, Ee ≈ V in Figure 4C) KE This disclosure highlights the advantages of electronically accelerating material processing (EEMP) as taught, which enables precise and selective targeting of the material. 【0036】 Figure 5 is a process chart (500) showing various steps of a method according to an embodiment of the present disclosure for processing the surface of a substrate. As shown in Figure 5, such steps include, according to step (510), positioning a substrate support stage in the region of a DC plasma reaction chamber configured to generate a positive column of DC plasma; according to step (520), generating DC plasma by coupling an adjustable DC voltage source and a DC current source to the anode and cathode of the DC plasma reaction chamber, respectively; based on this generating step, generating a stray potential on the surface of the substrate support stage according to step (530); adjusting the potential of the anode via an adjustable DC voltage source while maintaining a constant DC current between the anode and cathode via a DC current source according to step (540); and based on this adjustment and maintenance step, setting the stray potential to the potential of a reference ground of the adjustable DC voltage source according to step (550). 【0037】 Figures 6A–6C are graphs showing the reaction rates of electron-accelerated material processing (EEMP) according to this disclosure for different (category / type / class) materials, including single crystal or two-dimensional (2D) materials such as semiconductor or insulating materials (Figure 6A), metals and metal alloys (Figure 6B), and composite materials such as polymers, composites, nanomaterials, or three-dimensional (3D) materials (Figure 6C). In this case, the reaction, or target reaction, is driven by a bias signal V applied to the stage (e.g., S in Figure 4A). B In response to the level of the reaction threshold voltage V, the chemical bonds between the atoms of the material on the surface of the substrate placed on the stage (e.g., S in Figure 4A) can be described as breaking (e.g., the bonds between electrons and atomic nuclei). As is clear from such a graph, the reaction rate RR is equal to the reaction threshold voltage V RTH , reaction cutoff voltage V RCO , and reaction threshold fluctuation voltage V RTHV It can be characterized by the following. It should be noted that such characteristic voltages may differ depending on the material or type of material, and are generally part of a priori acquired knowledge base. For example, the V of a crystalline material (e.g., Figure 6A) RTHThis is the V of a metallic material (for example, Figure 6B). RTH or V of composite materials (e.g., Figure 6C) RTH It can be different, and the V of crystalline materials (for example, Figure 6A) RTHV This refers to the V of a metallic material (e.g., Figure 6B) or a complex material (e.g., Figure 6C). RTHV It may differ from that. 【0038】 Examples of 2D materials suitable for the electron-accelerated material processing (EEMP) according to this disclosure include graphene, boron nitride, molybdenum disulfide, tungsten diselenium, or platinum diselenium. Examples of nanomaterials suitable for the EEMP according to this disclosure include carbon nanotubes, nanosilver particles, titanium oxide particles, or quantum dots. Examples of 3D materials suitable for the EEMP according to this disclosure include polymers, collagen fibers, or metals such as titanium, or any 3D structures formed from materials including 3D-printed polymer / polymer, polymer / carbon, or polymer / metal microstructures. Examples of single crystals suitable for the EEMP according to this disclosure include semiconducting single crystals such as group IV silicon, germanium, group III-V gallium arsenide, gallium nitride, silicon carbide, and indium gallium arsenide, as well as quantum well stacks containing alternating group II-VI zinc selenide and group II-VI compound semiconductors and / or group III-V compound semiconductors. Examples of single crystals suitable for the EEMP of this disclosure include semiconducting single crystals such as quartz, sapphire, or diamond. Examples of polymers suitable for the EEMP of this disclosure include polypropylene, polyethylene, polyetheretherketone, and polycarbonate. Examples of composites suitable for the EEMP of this disclosure include polymers containing metal particles, carbon particles, carbon fibers, or carbon nanotubes. The materials and structures listed herein should be considered non-limiting with respect to the list of material suitability for the EEMP of this teaching, and this list may increase as new materials / structures and corresponding bond and reaction energies (which may be subject to this EEMP) are obtained, for example, through advanced methods for computer simulation of chemical bonding. 【0039】 Continuing to refer to Figures 6A-6C, for example, as described above with reference to Figure 4B, when the substrate is placed on the stage (for example, S in Figure 4A), the floating potential (for example, V in Figure 4B) FP The bias voltage V can be adjusted (controlled) to a known potential (e.g., zero volts or other). Therefore, the energy levels of atoms on the substrate surface may take the same potential (e.g., as the ground state), and no reaction may be observed on the substrate surface, or in other words, as shown in Figures 6A-6C, the reaction rate RR of the target bond (in the ground state) is zero. B As increases, the reaction rate RR of the target bond remains zero, and then a small number (e.g., a few) of the target bonds begin to react slowly, or in other words, when a few of the target bonds reach their respective excited states, the reaction cutoff voltage V RCO It rises up to this point. Bias voltage V B The reaction threshold voltage V RTH When it reaches this point, most of the target couplings begin to react (for example, reaching their respective excited states), and the bias voltage V B As the bias voltage V increases further, the reaction rate RR increases according to a (virtually) constant slope, and this slope corresponds to the bias voltage V B The reaction threshold voltage V RTHV Continue until it reaches the reaction threshold voltage V. RTH and reaction threshold fluctuation voltage V RTHV Between these points, the reaction rate RR increases until (almost) all target bonds react. As shown in Figures 6A-6C, the reaction threshold voltage V RTHV Beyond that, the bias voltage V B Increasing V slightly increases the reaction rate RR, or in other words, increases it to the point of "diminishing returns." On the other hand, the bias voltage V B As V decreases, the reaction rate RR becomes similar to the graphs shown in Figures 6A-6C. In particular, the bias voltage V B The reaction cutoff voltage V RCO When the reaction rate drops below a certain level, all target bonds on the substrate surface return to their respective ground states, causing the reaction rate RR to drop to zero. 【0040】 As is clear from the graphs in Figures 6A to 6C, the voltage V RTH and V RTHV The (substantially) constant slope of the reaction rate RR between and the two voltages, or the difference between the two voltages, may be a function of the material used for the substrate (surface) being processed. In particular, the voltage V RTH and V RTHV The difference may be due to atomic-level defects on the surface of single-crystal materials such as semiconductors or insulators (e.g., Figure 6A), atomic-level defects and associated grain boundaries on the surface of metals, metal alloys or nanomaterials (e.g., Figure 6B), or the presence of three-dimensional (3D) structures in polymers, composites or other 3D materials (e.g., Figure 6C). As will be discussed later in this disclosure, the teachings of this disclosure involve a voltage level V specifically targeted to the material used in the substrate to control the activation (or deactivation) of a reaction governed by the reaction rate RR, for example, as shown in the graphs in Figures 6A-6C. B The waveforms for generating a bias signal having the following characteristics are described. In particular, the specific waveforms for each material represented in the reaction rate RR graphs in Figures 6A, 6B, and 6C are shown in Figures 7A, 7B, and 7C, respectively. 【0041】 Figures 7A–7C are graphs showing the waveforms of the EEMP bias signal V(t) according to several exemplary embodiments of the present disclosure relating to the processing of different materials. In particular, Figure 7A shows the waveform when processing single-crystal materials such as semiconductors or insulators, Figure 7B shows the waveform when processing metals, metal alloys or nanomaterials, and Figure 7C shows the waveform when processing polymers, composites or three-dimensional materials. Such graphs represent the ideal voltage level (e.g., V) of the bias signal V(t) for use in the EEMP processes according to the present disclosure described above. B , V BN This represents the potential V FP The steps include controlling the voltage to a known level such as zero volts or another fixed, known level, and the potential V FP Voltage / potential level relative to (e.g., V B Note that this may include the step of biasing free electrons in a DC plasma. 【0042】 The graphs in Figures 7A to 7C show the (periodic) bias signal V(t) and T EEMP This represents one cycle of the waveform. The EEMP process of the material on the surface of the substrate is performed in a predetermined number of cycles, T, according to priori-obtained process knowledge. EEMP This can be performed by a bias signal V(t) generated through the repetition of ,. Different EEMP processes (e.g., each with its own RR characteristics) are performed by different layers of different materials in the substrate and / or different operating conditions and / or potential V of the DC plasma reaction chamber. FP Considering the (controlled / preset) levels, this can be performed sequentially on the same circuit board. 【0043】 Continuing to refer to Figures 7A to 7C, according to one embodiment of the present disclosure, the cycle T of the waveform of the bias signal V(t) EEMP Each of these phases (e.g., time interval, time segment, duration) ΔT includes voltage levels above zero volts (or reference voltage level), below zero volts, and equal to zero volts. BP ΔT BN , and ΔT BZ This may include the time interval ΔT. BP During this time, the level of the bias signal V(t) V B It is strictly greater than zero volts (or the reference voltage level), with a time interval ΔT BN During this time, the level of the bias signal V(t) V BN It is strictly less than zero volts, with a time interval ΔT BZ During this time, the level of the bias signal V(t) is equal to zero volts. 【0044】 According to one embodiment of the present disclosure, the duration T of the cycle of the waveform shown in Figures 7A to 7C EEMPThe frequency may be in the range of 1 μs to 10 μs, or in other words, the frequency of the bias signal V(t) may be in the range of 100 kHz to 1 MHz. According to further embodiments of the present disclosure, the waveform of the bias signal V(t) may be free of DC components, or in other words, the integral over the cycle of the waveform shown in Figures 7A to 7C may have a value of zero. Such DC component-free characteristics of the waveform according to this teaching can be achieved by, for example, referring to Figures 2A to 4C as described above, the preset / controlled local surface potential of the substrate (e.g., V FP ) can be maintained at the average local surface potential of the substrate while a bias signal V(t) is applied that is (substantially) equal to ). In other words, the characteristics of the waveform that do not contain a DC component allow for the maintenance of (substantially) identical voltage levels (e.g., V) shown in Figures 7A-7C. B , V BN This makes it possible to apply a potential V to the substrate surface. FP When the voltage is adjusted (e.g., preset, controlled) to a level different from zero volts (a fixed, known level), the waveform is at potential V. FP The DC component is adjusted to include a level equal to that of, or in other words, the 0V reference in Figures 7A-7C is adjusted to a potential V FP Please note that this can be adjusted by replacing it with the value of . 【0045】 According to one embodiment of the present disclosure, the time interval ΔT shown in Figures 7A to 7C BP ΔT BN , and ΔT BZ Each length can be based on the type of material (on the surface) of the substrate, including the corresponding reaction rate RR described above with reference to Figures 6A-6C. In particular, the length of the time interval ΔT BP The length of the time interval ΔT BNThe ratio to can be in the range of (approximately) 1 / 10 to (approximately) 1 / 1. For example, in the case of crystalline materials (e.g., Figure 7A), the ratio may be approximately 10 / 65 (±10%), in the case of metallic materials (e.g., Figure 7B), the ratio may be approximately 1 / 2 (±10%), and in the case of composite materials (e.g., Figure 7C), the ratio may be approximately 1 / 1 (±10%). Furthermore, as shown in Figures 7A to 7C, the total cycle length T EEMP The length of the time interval ΔT BZ The ratio can be approximately 1 / 4 (±10%). According to non-limiting embodiments of this disclosure, the time interval ΔT BZ The length is the total length of the period T EEMP It may also be based solely on the time interval ΔT BP and ΔT BN The lengths of each element may be independent of the others. 【0046】 For the exemplary and non-limiting cases shown in Figures 7A-7C, the time interval (ΔT BP ΔT BN ΔT BZ The total length of the cycle T EEMP The ratio to (e.g., ±10%) can be approximately (10 / 100, 65 / 100, 25 / 100) for crystalline materials (e.g., Figure 7A), approximately (25 / 100, 50 / 100, 25 / 100) for metallic materials (e.g., Figure 7B), and approximately (37.5 / 100, 37.5 / 100, 25 / 100) for composite materials (e.g., Figure 7C). Figures 7A-7C show cycle T with a length of 4 μs (frequency 250 KHz). EEMP Although this indicates the above, as stated above in this disclosure, such lengths may be in the range of 1 μs to 10 μs (for example, frequencies of 100 KHz to 1 MHz) and should not be considered as limiting the scope of this disclosure. 【0047】 Continuing to refer to the waveforms in Figures 7A to 7C, the phase ΔT BPDuring this time, the waveform is at a (positive) level (e.g., V) to activate the (targeted) EEMP reaction at the substrate surface based on collisions between the biased (free) electrons and target bonds at the substrate surface (e.g., surface materials including single crystal for Figure 7A, metal for Figure 7B, and composite material for Figure 7C), where the bias voltage V(t) is at a (positive) level. B ) can be set to ). According to one embodiment of the present disclosure, the (high) level V of the bias voltage V(t) B The length over which this is maintained must be long enough to retain the biased (free) electrons on the substrate surface and react with the target bond. Such a length corresponds to the phase ΔT shown in Figures 7A-7C. BP The rising or falling slope (or part thereof) included in the bias voltage (V(t) is at the target high level V B It should be noted that it is not necessary to include the period that is not included. 【0048】 Furthermore, phase ΔT BN During this time, the waveforms in Figures 7A-7C show that the bias signal V(t) is set to a (negative) level V to inactivate the EEMP reaction on the substrate surface and to discharge (e.g., repel) any free electrons from the substrate surface, thereby neutralizing the charge on the substrate. BN It can be set to Phase ΔT. BN During this time, the kinetic energy is at the (negative) level V of the bias signal V(t). BN It should be noted that this can impart energy to free ions in the DC plasma, causing the energized free ions to slowly move toward the substrate surface, thereby potentially contributing to the neutralization of the substrate. Furthermore, it should be noted that, due to their low energy levels, the energized free ions may not (and should not) react with the bonds on the substrate surface. Voltage level V of bias signal V(t) BN The magnitude of is therefore high enough (for example, it may be more negative) for free ions to move slowly toward the substrate, and the phase ΔT BN The duration is at voltage level V BN Size and phase ΔT BPCombined with the duration of ΔT, it may be long enough to cause suppression (or control) of the DC component of the bias signal V(t). ΔT should be such that free electrons do not have enough energy to damage the corrosion layer, nor do they have too little energy to reach the substrate and neutralize it to zero net charge and net current. BN Length and V BN The depth / size can be controlled. 【0049】 Phase ΔT BZ During this time, the waveforms in Figures 7A to 7C show that the voltage level of the bias signal V(t) is zero (or the floating potential V). FP It may also be set to the same preset level. Therefore, phase ΔT BZ This is each cycle T of the bias signal V(t). EEMP At the start of the process, it may be used to restore a similar initial bias state of the substrate, such an initial bias state is a floating potential V FP Based on the preset level, this may enable a more stable and accurate process (EEMP) compared to other conventional processes. Therefore, based on the provided description, cycle T describes the waveform of the bias signal V(t). EEMP Each phase ΔT BP ΔT BN , and ΔT BZ These can be referred to as the active (EEMP) reaction phase, the (EEMP) neutralization phase, and the (EEMP) reactivation phase, respectively, with the latter two phases being the inactivation phases for the targeted (EEMP) reaction. 【0050】 Figure 8 shows the activity phase ΔT. BP Further timing details describing each part of the waveform (e.g., time interval t) BR , t BH , and t BR This graph shows the idealized waveform of the EEMP bias signal V(t) described above, including the time interval t, with reference to Figures 7A-7C. BRThis is when the bias signal V(t) moves from its starting value at the start of the phase (e.g., V(t)=0) to the target high level V. B The transition time until it reaches a certain point can be defined, and the time interval t BH This is when the bias signal V(t) reaches the target high level V B The effective duration can be defined, and the time interval t BF The bias signal V(t) is active during phase ΔT. BP The transition time until returning to the starting value (e.g., V(t)=0) at the end of the process can be defined. In other words, the time interval t BR This is a high level V from the starting value. B The rising edge gradient (e.g., leading edge) of the bias signal V(t) to reach the time interval t can be defined. BF This allows us to define the falling edge gradient (e.g., trailing edge) of the bias signal V(t) to return to the starting value. 【0051】 Continuing to refer to Figure 8A, the time interval t BH During this time, the bias signal V(t) is equal to the response threshold voltage V RTH A higher level V (greater than) B Therefore, as described above with reference to Figures 6A-6C, for example, the target coupling is, as described above with reference to Figures 7A-7C, for example, the time interval t BH Each excited state can be reached as long as the duration is long enough to retain the biased (free) electrons on the substrate surface to react with the target bond. According to exemplary embodiments of this disclosure, the length of the active phase ΔT BP The length of the time interval t BH The ratio can be in the range of approximately 1 / 4 (e.g., ±10%) to approximately 3 / 4 (e.g., ±10%). Thus, a periodic bias signal V(t) with a frequency of 250 kHz and a cycle length T equal to 4 μs. EEMP Now, let's consider the case where EEMP treatment is performed on a single crystal material (for example, Figures 6A and 7A above). The length of the time interval t BHThis can be within the range of approximately 0.1 μs to approximately 0.3 μs. 【0052】 Referring further to Figure 8A, the bias signal V(t) is active during the ΔT phase. BP As it rises from the start, the response threshold voltage V RTH The level of the bias signal V(t) that exceeds this value occurs during the time interval t. BR It can reach a certain point during a portion of the time interval t. Similarly, the bias signal V(t) can reach a time interval t BH As it decreases towards the end, the response threshold voltage V RTH The level of the bias signal V(t) above this value corresponds to the time interval t. BF This can be maintained for a portion of the time. Therefore, in the ideal case where the voltage level shown in Figure 8A is effectively seen by free electrons in the DC plasma, the level of the bias signal V(t) is equal to the reaction threshold voltage V RTH The above is the time interval t BR and t BF A portion of this can be included in the determination (or interpretation) of the reaction rate graph RR described above, with reference to Figures 6A-6C. However, the time interval t BR and t BF The slopes of the rising and falling edges defined by can be very steep (high level V B (The voltage can be in the range of 10 volts to approximately 200 volts), and a portion of the aforementioned time may be considered irrelevant / insignificant compared to the minimum time required to retain the biased (free) electrons on the substrate surface to react with the target bond. 【0053】 Figure 8B is a graph showing a practical waveform of the EEMP bias signal. Such a waveform represents a actually achievable waveform that can be modeled from the ideal waveform described above with reference to Figure 8A. In particular, the practical waveform in Figure 8B, as illustrated, corresponds to the steady-state level (e.g., V B , V BNThe waveform includes a gradual and curvilinear transition to and from zero volts. Such a practical waveform may be generated by electronic equipment that may include a power amplifier (e.g., coupled to and / or part thereof) whose output is coupled to a load under perfect matching conditions. However, such perfect matching conditions are not provided by a capacitive load in the DC plasma processing according to this disclosure (e.g., stage S in Figure 4A), and therefore, as shown in Figure 8C, a steady-state level (e.g., V B , V BN Before settling to zero volts, signal reflections, including ringing (resonance), and associated distortions can be expected. 【0054】 The ringing shown in Figure 8C is the target high level V. B The activation stage phase ΔT before settling down BP During and targeting a lower level V BN Neutralization phase ΔT before settling down BN Ringing of the bias signal V(t) during the interval (for example, V BU ) may include. As shown in Figure 8C, ringing ΔT during the activation phase BP This is the overshoot voltage V BOS The high level V that is targeted by B It spreads upwards, and the undershoot voltage V BUS The high level V that is targeted by B The spread of the uncertain voltage V extending downwards BU It can be expressed by the undershoot voltage V BUS The level of the bias signal V(t) corresponds to the response threshold voltage V RTH Reduce the overshoot voltage to less than V BOS The level of the bias signal V(t) does not affect the coupling reaction threshold voltage V' which may exist on the substrate surface. RTH Because it may reach a certain level, the spread of the uncertain voltage V BU This clearly demonstrates that the activation of the EEMP target reaction may be disrupted during the activation phase. On the other hand, the neutralization phase ΔT BNThe ringing within does not significantly affect the EEMP process because the free ions are kept well below the reaction energy of any ion-driven reaction (e.g., thermochemical reaction). According to one embodiment of the present disclosure, the active phase ΔT BP The reduction of ringing, including the ringing within the signal, as shown in Figure 8C, can be provided by pre-distorting (e.g., distortion compensation) the bias signal V(t). 【0055】 Figure 9A shows the digitized waveform (WF, the circled digital sample) and the corresponding pre-distorted digitized waveform (WF) for generating the practical waveform in Figure 8B. P This is a graph representing the digital samples (square marks). In particular, the generation of the practical waveform in Figure 8B can be provided by uploading the corresponding digital samples WF of the digitized waveform to a digital signal generator whose output can be supplied to a power amplifier (e.g., coupled to or part of the bias signal generator in Figure 4A). Similarly, the generation of the corresponding practical waveform with pre-distortion can be provided by uploading the digital samples WF of the pre-distorted digitized waveform. P This can be provided by uploading it to a digital signal generator. 【0056】 Continuing to refer to Figure 9A, pre-distortion, when subjected to capacitive loading conditions on the stage (e.g., S in Figure 4A), can provide a practical pre-distortion waveform (e.g., WF) that can reduce the amount of ringing, as shown in Figure 9B. P It can be used to modify / equalize the gradient / transition of a digitized waveform with pre-distortion, so as to generate ΔT. As shown in Figure 9B, by using pre-distortion, the entire active phase ΔT BP During this time, the level of the bias signal V(t) is equal to the target response threshold voltage V RTH If it exceeds the arbitrary non-target response threshold voltage V' RTH The spread of the uncertain voltage V should be less than BU This can cause a decrease in the bias signal V(t) to the target high level V. Such pre-distortion can cause the bias signal V(t) to fail to reach the target high level V.B The desired length of the time interval t during which BH It should be noted that this may result in a waveform containing . In other words, pre-distortion can result in the time interval t mentioned above, for example, referring to Figure 8A. BH It can maintain its length. 【0057】 Figure 10A shows a graph representing the gain-to-frequency ratio (e.g., graph G1) of a band-limited linear power amplifier according to an embodiment of the present disclosure, and a graph representing the gain-to-frequency ratio of a conventional power amplifier (e.g., graph G2). According to one embodiment of the present disclosure, a band-limited linear power amplifier used for EEMP processing may include a flat gain G1 of 0.75 dB or less in the frequency range of 10 kHz to 10 MHz, as shown in Figure 10A. Such an operating (passband) range of a band-limited linear power amplifier is affected by any corresponding (higher frequency) high frequencies that may be reflected from a capacitive load, as well as some of the ringing shown in Figures 8C and 9B (e.g., uncertainty voltage spread, V BU The frequency range of the bias signal V(t) operation is selected considering the 100KHz to 1MHz frequency range to reduce any corresponding (higher frequency) harmonics that may generate signal distortion, including ). 【0058】 Figure 10B shows the pre-distorted digitized waveform WF of Figure 9A through the band-limited linear power amplifier of Figure 10A under capacitive load conditions. P This graph shows the analog waveform generated from [the source]. In particular, when compared with the waveform described above, referring to Figure 9B, the spread of the uncertain voltage V is [the value of the waveform]. BU A decrease is observed, indicating a larger process window for controlling / manipulating the target EEMP response. It should be noted that the waveform in Figure 9B shows that the gain versus frequency G2 can be reproduced by a conventional power amplifier shown in Figure 10A. In particular, the cutoff frequency f of a conventional power amplifier is as shown in Figure 10A. C2 The cutoff frequency f of the band-limited linear power amplifier according to this instruction is C1This is substantially larger and allows high-frequency harmonics of the bias signal V(t) to pass through, potentially reproducing such harmonics as distortion. 【0059】 Figure 11 is a process chart (1100) showing various steps of a method according to one embodiment of the present disclosure for processing the surface of a substrate. As shown in Figure 11, such steps include, according to step (1110), placing the substrate on a support stage within the region of a DC plasma reaction chamber configured to generate a positive column of DC plasma; according to step (1120), generating DC plasma; according to step (1130), presetting the stray potential of the substrate surface to a reference potential; and according to step (1140), capacitively coupling a periodic bias signal having a bias voltage referenced to the stray potential to the support stage, wherein the periodic bias signal includes an activation phase having a positive voltage referenced to a known reaction threshold voltage of a target chemical bond of atoms on the substrate surface, a neutralization phase having a negative voltage, and an initialization phase having a zero voltage. 【0060】 The various steps in the process chart (1100) in Figure 11 can be used for atomic layer etching (ALE) of a substrate surface. Such steps can target chemical bonding of atoms on the substrate surface via low-energy electrons (e.g., less than 500 eV), thereby avoiding surface damage to the substrate beyond what is related to the targeted chemical bonding. Atomic layer etching according to this disclosure may also be based on electron-stimulated desorption (ESD), where the desorption process is stimulated by the electronic excitation of quantum transitions (e.g., energy level jumps) on the surface of the substrate (e.g., wafer) and controlled by material-specific energy thresholds. ESD proceeds by a fundamentally different mechanism from (conventional) subsurface impact cascades initiated by momentum transfer via ion bombardment (impact). These material-specific energy thresholds provide an opportunity to tune / target electron energy to specific materials, thereby enabling atomic layer etching according to this disclosure to achieve high specificity and selectivity across different materials. 【0061】 Low-energy electrons (e.g., less than 500 eV), including a portion of the precisely controlled wafer-scale electron wave generated according to this instruction, can interact with the substrate surface located, for example, in the DC plasma reaction chamber (110) of the DC plasma processing system described above, with reference to Figure 4A. These electrons can cause physical and chemical changes on the substrate surface. 【0062】 The atomic layer etching according to this disclosure involves the use of an adsorption layer on the surface of the substrate to be etched. The adsorption layer is composed of reactive species present in the plasma. The formation of the adsorption layer is purely chemical and may involve weak or strong bonding interactions between the reactive species and the substrate. The reactive species include H atoms (radicals), H+, H-, H2, H2+, and H 2ー(In this example, species H is defined as the reactive species) may be included. The presence of an adsorption layer can lead to more pronounced physical and chemical changes on the substrate surface. The reactive layer (adsorption layer) attached to the surface layer below is defined as the corrosion layer. Combined with low-energy electrons reaching the substrate surface, the conditions that arise within a DC plasma reaction chamber (e.g., 110 in Figure 4A) can promote the desorption of the corrosion layer attached to the substrate as ionic species, neutral atomic species and / or molecular species (e.g., desorption or removal of the corrosion layer). 【0063】 The process described above for removing the corrosive layer (adsorbed layer along with the underlying surface atomic layer) using low-energy electrons, which may be used in atomic layer etching (ALE) according to this disclosure, is referred to herein as electron-stimulated desorption (ESD). This effect arises from electron excitation and not from thermal excitation resulting from collisions (momentum transfer) of low-energy electrons. It should be noted that momentum transfer from low-energy electrons may not provide sufficient energy to desorb the corrosive layer (surface species containing reactive species bonded to the surface atomic layer of the substrate). Because the mass of electrons is very small compared to the colliding corrosive layer species (surface-bonded atoms and surface reactive species), there is little energy transfer to the surface-bonded atoms by collision (typically less than 0.1 eV), which is insufficient to cause the removal of reactive species that may include bonds in the range of about 1 eV to 8 eV. However, electron excitation may have enough energy to cause the desorption of the (targeted) corrosive layer by ESD. 【0064】 It should be noted that the EEMP process described herein is distinctly different from electron beam-based processes and ion bombardment processes (e.g., RIE) known in the art. Although the EEMP process described herein differs from electron beam-based processes, both can utilize ESD for the removal of corrosive layer species; the difference lies in the scale on which they operate. Such beam technologies are at best on a millimeter scale and are extremely localized. In stark contrast, and advantageously, the EEMP process described herein can operate at any scale that a DC plasma sunbeam can or can be made to occupy, including a range (width) from millimeters to meters. The EEMP process described herein and ion bombardment processes differ in their fundamental operating mechanisms. The EEMP process described herein operates via ESD. In ESD, arriving electrons increase the binding energy of only the corrosive layer species through resonant excitation, destabilizing only the corrosive layer species (without momentum transfer). The corrosive layer species generate a repulsive force toward the layer (excited state) beneath the substrate. As a result, only the corrosive layer species are ejected (removed) from the substrate by kinetic energy and then enter (and are swept out) by the sunlight column. Ion bombardment processes known in the art, due to the large mass of ions, transfer momentum to the corrosive layer species via collisions that cause subsurface collision cascades. With sufficient momentum, this subsurface collision cascade can expel the corrosive layer species. Essentially, such subsurface momentum cascades inevitably leave traces / effects of the surface layer removal on the newly exposed layer (subsurface). The interaction between the ion strengthening process and the subsurface layer is an undesirable outcome for smooth finish, stoichiometry maintenance, ion embedding in the substrate, and collision damage, which are not present in EEMP. 【0065】 Electronic excitation can occur when electrons reaching the surface transfer energy to the binding electrons of the corrosive layer species, increasing their binding energy (resonant excitation of binding electrons by the reaching electrons), thereby destabilizing the corrosive layer species on the surface. In this case, the excited corrosive layer species can move from a stable ground state electron configuration to an excited state electron configuration with a repulsive potential. As a result, kinetic energy due to this repulsive potential is imparted to the corrosive layer species, promoting its removal from the substrate surface, thereby completing the removal / etching of the top layer of the substrate. As mentioned above, these removal thresholds are material-dependent, so by adjusting the energy of the incident electrons and providing various reaction species, ESD can affect a variety of materials with high specificity and selectivity. 【0066】 The electron-accelerated material processing (EEMP) atomic layer etching (ALE) according to this disclosure includes the steps of: providing a substance to be adsorbed onto atoms in the outermost atomic layer of a substrate to be etched in order to generate a corrosive layer species on the substrate surface; generating electrons with energy that target the chemical bonding of the corrosive layer species; and exciting the corrosive layer species using an electron-stimulated desorption (ESD) process, thereby evacuating / releasing the corrosive layer species, thereby etching away the outermost atomic layer of the substrate. 【0067】 Figures 12A, 12B, and 12C show various schematic diagrams representing the initialization task and corresponding states of a DC plasma reaction chamber (e.g., 110 in Figure 4A) in preparation for atomic layer etching (ALE) of the surface of a substrate Sub via electron-accelerated material processing (EEMP) according to the present disclosure. 【0068】 As shown in Figure 12A, and further with reference to Figure 4A, the substrate Sub is placed on a stage S located in the region of a DC plasma reaction chamber (110) configured to include a sun column region G3, as previously described. In Figure 12A (and the following figures), the substrate Sub is represented by atomic layers (L1, L2, L3), each of which contains atoms of the material constituting the substrate Sub. In the exemplary non-limiting case of the substrate Sub shown in Figure 12A, three layers (L1, L2, L3) are shown, each of which contains atoms represented by a (large) circle. In the exemplary non-limiting case of the substrate Sub shown in Figure 12A, each layer (L1, L2, L3) contains silicon atoms Si, in other words, the exemplary non-limiting substrate Sub can be considered a silicon substrate. As previously described in this disclosure, the electron-accelerated material processing (EEMP) according to this disclosure, including its application to atomic layer etching (ALE), is applicable to different categories / types / classes of materials and, therefore, can be applied to different substrates containing such materials. In other words, the substrate Sub may contain any of such materials in one of its layers (e.g., L1, L2, L3, ... and subsequent layers). Furthermore, two such layers may contain the same material (i.e., atoms) or different materials (e.g., adjacent atomic layers). 【0069】 The legend in the upper right of Figure 12A (and the following figures) relates to the symbols used in the figures, which represent material particles such as atoms, ions, or molecules that may be present in the plasma reaction chamber (110) during the various states / phases of processing of the substrate Sub. Such material particles correspond to reaction (e.g., soluble) gases represented by small circles, diluent (e.g., solvent) gases represented by crosses, electrons (legend: e-) represented by dots, excited state substrate Sub atoms represented by large circles containing asterisks, and ground state substrate Sub atoms represented by large (empty) circles. The legend related to such symbols includes exemplary reaction gases that may contain hydrogen (H atoms, e.g., hydrogen molecules H2), diluent gases that may contain argon (Ar+), and excited state (Si *This refers to exemplary non-limiting material particles corresponding to silicon atoms (e.g., atomic bonds) in their ground state (Si). 【0070】 As shown in Figure 12A, the silicon substrate Sub is placed on the stage S in preparation for the atomic layer etching (ALE) process. In this case, the plasma reaction chamber (110), and therefore the stage S and substrate Sub, can be placed under vacuum by means well known to those skilled in the art. For example, temperature (including stage / substrate) and other parameters within the plasma reaction chamber that may affect the substrate Sub can also be set / controlled. Furthermore, in Figure 12A, material particles (H species, Ar+, e-, Si * The absence of either of these indicates that a DC plasma, and therefore excited silicon atoms, are not present in the plasma reaction chamber (110). 【0071】 Figure 12A shows the time t when the stage S, and therefore the substrate Sub, is not actively biased by the bias signal generator (e.g., 480 in Figure 4A). OFF This can represent the state of the atomic layer etching process (ALE) in . Therefore, as shown in Figure 12A, t OFF At this point, there is no bias signal V(t) coupled to the stage S, and therefore to the substrate Sub. As described above in this disclosure, the bias signal V(t) is a time-varying bias voltage capacitively coupled to the stage S (e.g., V in Figure 4A). B ) can represent the corresponding voltage level (e.g., V RTH and V BN ) and phase (for example, ΔT BP ΔT BN , and ΔT BZ Exemplary waveforms of the bias signal V(t) including ) are shown above with reference to, for example, Figures 7 to 10. 【0072】 Figure 12B may represent the state of the atomic layer etching process (ALE) at time t0, in which a diluent gas (e.g., argon) or a reaction gas (e.g., hydrogen) is present in the plasma reaction chamber (110) and generates a DC plasma (in the sun column, e.g., glow region G3). Once the DC plasma is generated (e.g., ignited), some of the diluent gas and some (but not all) of the reaction gas are ionized to generate free electrons e- as shown in Figure 12B. As a result, the distribution of ionic species in the sun column of the DC plasma may include ions of the diluent gas represented as Ar+ in Figure 12B, as well as particles of the reaction gas that may contain H species as shown in Figure 12B and subsequent figures. 【0073】 The diluent and reaction gases may be introduced simultaneously as a mixed gas into the plasma reaction chamber (110) or separately and sequentially, and it should be noted that such gases may be ionized / ignited simultaneously or separately within the plasma reaction chamber. Furthermore, according to some exemplary embodiments, the reaction species (e.g., H species) may be generated in a separate chamber and then introduced into the plasma reaction chamber (110) to provide the ion species distribution shown in Figure 12B. Furthermore, it should be noted that the majority of the free electrons e- shown in Figure 12B may correspond to the current flowing between the anode A and cathode C of the plasma reaction chamber (110) (e.g., Ip in Figure 4A). 【0074】 As described above in this disclosure, the atomic layer etching (ALE) process according to this disclosure is not limited to argon as the diluent gas and hydrogen as the reactant gas. Some non-limiting exemplary diluent gases may include argon (Ar), neon (Ne), or xenon (Xe). Some non-limiting exemplary reactant gases may include hydrogen (H2), chlorine (Cl2), methane (CH4), carbon monoxide (CO), oxygen (O2), or others, either alone or in combination. Furthermore, according to one embodiment of this disclosure, the ratio of the reactant gas to the diluent gas used in the atomic layer etching (ALE) process according to this disclosure (before plasma ignition) can be in the range of about 2 / 100 to about 50 / 100 or more. 【0075】 As described above in this disclosure, during the atomic layer etching (ALE) process in this teaching, a portion of the reaction gas introduced into the chamber (110) (e.g., about a few percent to about 100%, e.g., completely ionized) may be ionized to generate reactant species (e.g., H species). The ionized portion of such reaction gas, as well as the distribution of the corresponding reactant species, in other words, the relative number of H species in the exemplary case of hydrogen, can be controlled via process parameters, including the magnitude of the current Ip as described above, for example with reference to Figure 4A. While the H species of the ionized reaction gas is considered in this specification for the atomic layer etching (ALE) process (e.g., in the formation of adsorbed layers), it should be noted that other components of the ionized reaction gas (e.g., reactant species), including H+ and / or H- in the exemplary case of hydrogen, may be used instead to provide different etching performance, including, for example, selectivity with respect to the finish / smoothness of the target material / atom and / or substrate surface. 【0076】 For example, as described above with reference to Figure 1C, the presence of a DC plasma, and therefore the corresponding plasma potential V PP Considering the distribution of ion species shown in Figure 12B, the (surface) stray potential V in the sun column of a DC plasma FPThis can occur on the surface of stage S in Figure 12B, and therefore on the substrate Sub. For example, as described above with reference to Figure 5, the floating potential V FP This can be adjusted to a known reference potential, for example, the reference ground potential of a DC plasma processing apparatus used in the atomic layer process described herein (e.g., Figure 4A). Floating potential V FP It should be noted that the adjustment can be made after the distribution of ion species in the DC plasma reaction chamber (110) has stabilized (for example, after reaching a steady state or equilibrium), and before applying a bias voltage to state S. 【0077】 At time t0, as shown in Figure 12B, the stage S, and therefore the substrate Sub, can be actively biased by a bias signal generator (e.g., 480 in Figure 4A) (e.g., stage voltage V S In Figure 12B, V S (The bias signal V(t), represented by a thick voltage line such as =0V, is shown as the intersection point of the bias signal V(t) and the stage S). In other words, at time t0, the bias signal generator (e.g., 480 in Figure 4A) can bias the stage S, and therefore the substrate Sub, with the voltage provided by the bias signal V(t) coupled to the stage S, and therefore the substrate Sub. The bias signal V(t) is equal to the floating potential V FP Since it can be referenced to the same reference ground potential to which it is adjusted, the coupling of a bias signal V(t) having an amplitude of zero volts (0V) at time t0 to the stage S and therefore the substrate Sub, as shown in Figure 12B, may not substantially alter or affect the distribution of ion species supplied to the sun column of the DC plasma. 【0078】 Continuing to refer to Figure 12B, we can see that some of the reactive species (e.g., H species) are bonded (i.e., adsorbed) to atoms (e.g., Si) of the (topmost) surface layer L1 of the substrate Sub. In other words, Figure 12B shows the formation (initiation) of an adsorbed layer of reactive species on the surface layer L1 (e.g., shown in Figure 12B as three individual H species bonded to layer L1). The combination of reactive species adsorbed on the surface layer L1 is removed by electron-stimulated desorption (ESD) and can be referred to as an erosion layer that effectively etches away the atomic layer (e.g., L1) of the substrate Sub. 【0079】 The formation of the corrosion layer may proceed in stages (but rapidly) and depend on parameters observed at the location of stage S. These may include the temperature of stage S, the pressure within the DC plasma reaction chamber (110), the current flowing between the anode A and cathode C of the plasma reaction chamber (110) (e.g., Ip in Figure 4A), and / or the flow rate of the DC plasma which can determine the residence time of the reaction species (e.g., H species) in contact with the surface of the substrate Sub (e.g., layer L1). To etch away the entire surface layer L1 of the substrate Sub, each atom (e.g., Si) of the surface layer L1 may contain at least one adsorbed reaction species, as shown in Figure 12C. 【0080】 Figure 12C may represent the state of the atomic layer etching (ALE) process at time t1, when the corrosion layer is formed. In other words, as shown in Figure 12C, each atom (e.g., Si) in the surface layer L1 contains (e.g., is attached to) at least one adsorbed reactive species (e.g., H species, which includes one or more of SiH1, SiH2, or SiH3 to form the corrosion layer species). It should be noted that the corrosion layer formation time in the atomic layer etching (ALE) process according to this teaching is relatively fast, on the order of a few microseconds (μs) to about 10 microseconds. Such rapid formation of the corrosion layer is thought to be mainly due to the fact that the reactive species (e.g., H species) are continuously present (e.g., not switched on and off) throughout the plasma for the (entire) duration of the atomic layer etching process. This is related to the (initialization) phase ΔT described earlier, for example, with reference to Figures 7A / 7B / 7C. BZ See Figure 12C for reference. 【0081】 Assuming that time t0 shown in Figure 12C corresponds to the start time of corrosion layer formation, the period from time t0 to time t1 when the corrosion layer is formed is at least the duration of the (initialization) phase ΔT. BZ This is equivalent to the time ΔT of the bias signal V(t) in Figure 12C. BP (For example, refer to the cycle T described above in Figures 7A / 7B / 7C) EEMP It is represented by (part of) 【0082】 Figures 13A, 13B, 13C, 13D, and 13E show various schematic diagrams representing the state of the DC plasma reaction chamber (110) during the active phase of atomic layer etching (ALE) according to this disclosure. In other words, during such an active phase, the stage S is the cycle T (waveform) of the bias signal V(t) described above, referring, for example, to Figures 7A / 7B / 7C. EEMP The positive pulse ΔT of the activation phase BP The corresponding voltage V S This can be biased. In such a state, the rise time / fall time / edge of the positive pulse (e.g., t in Figures 8A / B / C and 9A / B) BR and t BF ) during the period, as well as the target response threshold voltage V RTH High levels of positive pulses provided by the corresponding (high) positive voltage (e.g., t in Figures 8A / B / C and 9A / B) BH ) during the activity phase ΔT BP This state may be included. 【0083】 Figure 13A shows the formation of a corrosive layer (for example, as shown in Figure 12C), and the stage voltage V S This can represent the state of the atomic layer etching (ALE) process at time t2 when it tracks (or begins to track) the rising edge of a positive pulse. In this case, the stage voltage V SThe target response threshold voltage V RTH It can be made substantially smaller (for example, less than half). However, the stage voltage V S That is, the substrate surface Sub has a floating potential V as shown in Figure 13A. FP Because it is in a positive voltage range, some of the (negatively charged) free electrons e- are attracted to the stage S and therefore move toward the substrate surface Sub. On the other hand, the ions (Ar+) of the diluent gas have a substantially larger mass than the mass of the free electrons e-, so they move toward the stage S and therefore move toward the substrate surface Sub. BP For example, at intervals of less than 4 μs, its spatial position can be considered substantially constant, as provided, for example, by the ion distribution shown in Figure 12C. 【0084】 A positive pulse, i.e., the stage voltage V S As the voltage increases, more free electrons e- are attracted to the substrate surface Sub. This is shown in Figure 13B, where at time t3, the stage voltage V S The target response threshold voltage V RTH It is not equal to, but closer. In this case, the corrosion layer formed on the surface of the substrate Sub (i.e., H species adsorbed on the Si atoms of L1) may be in contact with electrons e- that have an energy level that is not equal to, but close to, the target reaction energy level required to stimulate electronic transitions in the corrosion layer. 【0085】 A positive pulse occurs once, and therefore the stage voltage V S The target response threshold voltage V RTH When it reaches this point, the electrons e- on the substrate surface Sub can have enough energy to stimulate electron transitions in the corrosion layer. This is shown in Figure 13C, where at time t4, the stage voltage V S The target response threshold voltage V RTH This becomes equal to the atoms of the surface layer L1 of the substrate Sub (i.e., the corrosion layer species) in their respective excited states (for example, Si representing the excited states of corrosion layer species SiH1, SiH2, or SiH3). *) is reached. In other words, Figure 13C shows the initiation of the electron-stimulated desorption (ESD) process used in atomic layer etching (ALE) in this teaching (e.g., via the arrival of a wafer-scale wavefront, E-wave, of electrons with uniform density and energy on the substrate surface). This E-wave can be smaller than the diameter of the substrate stage and can be extended to the dimensions of the sunbeam. Target reaction threshold voltage V of the eroded layer RTH This is clearly different from the reaction threshold voltage of the uncorroded layer (e.g., L1 in Figure 12A). V of the corrosive layer species in the corroded layer RTH They are similar. The V of ESD used in the ALE of this specification RTH The highest V present in the corrosive layer RTH By setting the value, all species present in the corroded layer can be removed. It should be noted that the electronic stimulation of the transition is considered to be quasi-instantaneous (e.g., a fraction of a microsecond) once the surface species comes into contact with the electrons e- of the target reaction energy level. 【0086】 As shown in Figure 13D, at time t5, the stage voltage V S The target reaction threshold voltage V is still RTH Equivalent to the result of the ESD process, each excited state (for example, Si in Figure 13C) * The repulsive potential of the corrosive layer species in ) can impart sufficient kinetic energy to the corrosive layer species to expel it from the substrate surface Sub. This is shown in Figure 13D as the expelled corrosive layer species (SiH) detached from / separated from the surface of the substrate Sub, and thus resulting in the disappearance of the surface layer L1 from the substrate Sub. X ) * This is represented by [equation]. Therefore, as shown in Figure 13D, the outermost surface of the substrate Sub becomes layer L2 because the previous outermost surface L1 has been etched away. It should be noted that the timing of executing the sequence of states in the atomic layer etching (ALE) process shown in Figures 13C and 13D is on the order of a fraction of a microsecond (μs), and may be less than a few microseconds. For example, as described above with reference to Figure 7A, a periodic bias signal V(t) with a frequency of 250 kHz, and therefore cycle T equal to 4 μs. EEMPConsidering the length, the stage voltage V S The target response threshold voltage V RTH The length of the time interval t corresponding to the time equal to t BH This can range from approximately 0.1 μs to approximately 0.3 μs. 【0087】 Figure 13E shows the corrosion layer being removed (for example, as shown in Figure 13D), and the stage voltage V S This can represent the state of the atomic layer etching (ALE) process at time t6 when the stage voltage V follows (or begins to follow) the falling edge of the positive pulse. S The target response threshold voltage V RTH It may be smaller, but greater than zero volts. As shown in Figure 13E, once the corrosive layer species are discharged, they can be converted to neutral (e.g., gas) molecules (e.g., SiH4) by the presence of atoms and / or related species of the reaction gas (e.g., H species) in the region of the DC plasma reaction chamber (110) surrounding the substrate Sub. This allows all residues / species of the etched-off corrosive layer (e.g., SiH4) to be removed, for example, by a preset flow rate of diluent gas (e.g., argon) in the DC plasma reaction chamber (110). 【0088】 Figure 13E may represent the final state of the DC plasma reaction chamber (110) during the active phase of atomic layer etching (ALE) according to this disclosure. As described above in this disclosure, such an active phase is the cycle T of the bias signal V(t) described above, for example, with reference to Figures 7A / 7B / 7C. EEMP Duration ΔT equal to the length of the active phase BPThe bias signal V(t) can be defined by a positive pulse having . The application of such a positive pulse can remove the corrosive layer by an ESD mechanism initiated by the transfer of energy from low-energy electrons to excite the corrosive layer seeds, without ion bombardment (as occurs, for example, in conventional ALE processes). The application of such a positive pulse can remove the corrosive layer by an ESD mechanism initiated by the transfer of energy from low-energy electrons to excite the corrosive layer seeds, without ion bombardment (as occurs, for example, in conventional ALE processes), resulting in virtually no heat generation and no (undesirable) damage to the substrate structure (e.g., lattice). 【0089】 As shown in Figures 13A / 13B / 13C / 13D / 13E, the distribution of ion species surrounding the substrate Sub in the DC plasma reaction chamber (110) is as follows: Stage voltage V greater than zero volts S The stage S is perturbed by actively biasing it. In particular, electrons e- move toward the surface of the substrate Sub, and as a result, the distribution of ion species is characterized as heterogeneous, or at least different from the steady-state (e.g., equilibrium) distribution described above with reference to Figure 12B. As shown in Figure 13E, the following negative bias signal (e.g., V(t)=V) is applied to restore the steady-state distribution in the DC plasma reaction chamber (110). BN ) but for a sufficiently long time, ΔT BN , can be applied to stage S. 【0090】 Figure 14 is a schematic diagram that typically shows the state of the DC plasma reaction chamber 110) at time t7 of the neutralization phase of atomic layer etching (ALE) according to this disclosure. During this neutralization phase, the stage S undergoes the cycle T of the bias signal V(t) described above, for example, referring to Figures 7A / 7B / 7C. EEMP Negative pulse ΔT in the neutralization phase BN The corresponding negative voltage V S =V BN It can be biased with such a negative bias voltage V. BNThis can be used to repel electrons e- from the substrate surface Sub in order to restore (gradually but rapidly) the steady-state distribution (of ions) within the DC plasma reaction chamber (110) in preparation for atomic etching of the next layer (e.g., L2). Time ΔT BN During this time, a negative bias voltage V BN It should be noted that throughout the neutralization phase, defined by applying the ΔT, all other process parameters governing the presence of the seed / plasma in the DC plasma reaction chamber, including, for example, dilution and reactant gas inflow, anode / cathode voltage / current, and temperature, pressure, and flow rate, may remain unchanged. In other words, upon completion of the neutralization phase, the conditions in the DC plasma reaction chamber (110) may be substantially the same as those described above at time t0, referring to Figure 12B. As shown in Figure 14, in order to restore the conditions under which a corrosion layer is formed on the exposed surface layer L2 of the substrate Sub, a zero bias signal (e.g., V(t)=0V) is applied for a sufficiently long time, ΔT BZ A plasma stray potential V is applied to the stage S over a certain period of time, at the surface of the substrate Sub. FP This allows the potential to be returned to exactly the same value (e.g., 0V) with each ALE cycle. This enables precise control of the voltage / energy of all E-wave electrons delivered to the substrate Sub with each ALE cycle following this instruction, thereby improving reproducibility. 【0091】 Figure 15 is a schematic diagram that typically shows the state of the DC plasma reaction chamber 110) at time t8 of the initialization phase of atomic layer etching (ALE) according to this disclosure. During this initialization phase, the stage S undergoes the cycle T of the bias signal V(t) described above, for example, referring to Figures 7A / 7B / 7C. EEMP Initialization phase ΔT BZ Zero volt, V SThe bias voltage can be set to 0V. Such a zero-volt bias voltage can be applied for a length sufficient to allow the formation of the corrosion layer, as described above with reference to Figures 12B and 12C, for example. In other words, at the completion of the phase stage, the conditions inside the DC plasma reaction chamber (110) may be substantially the same as those described above at time t1, with reference to Figure 12C. 【0092】 Once the initialization phase is complete, the activation phase ΔT described above is performed to remove the next atomic layer (e.g., L2). BP , neutralization phase ΔT BN , and initialization phase ΔT BZ A new atomic layer etching (ALE) cycle including can be initiated. For example, time t8 shown in Figure 15 corresponds to the completion of the initialization phase (i.e., ΔT BZ A time length equal to a negative bias voltage V BN Assuming that time has elapsed since the application of the current, the positive pulse of the activation phase of the next ALE cycle will be any time t8 + ΔT Start It can be supplied by time ΔT Start This can be made as small as zero. In other words, the atomic layer etching (ALE) process according to this disclosure is, for example, cycle T as described above with reference to Figures 7A / 7B / 7C. EEMP Atomic layers of the substrate (e.g., L1, l2, etc.) can be removed at a rate corresponding to the speed. It should be noted that, for example, if different etching performance or different target reactions (e.g., different reaction species and / or different material atomic layers) are desired for etching the next layer of the substrate, the conditions in the DC reaction chamber (110) and / or the waveform of the bias signal V(t) can be changed / selected before starting the next ALE cycle. Furthermore, the reaction chamber can be purged before introducing different reaction gases. The time for such changes / selections can be varied by inserting an initialization bias signal longer than zero volts before starting the next EEMP cycle, or as short as zero (e.g., ΔT Start =0). 【0093】 As shown in various figures (e.g., Figures 13-15) used to illustrate the various states of a DC plasma reaction chamber (e.g., 110) during an atomic layer etching (ALE) process of a substrate (e.g., Sub) according to this disclosure, a volume of gaseous plasma is formed in a solar column (e.g., G3) on a stage (e.g., S) containing ions (e.g., Ar+ and H species) and electrons (e.g., e-) having a uniform steady-state composition (including a fixed / controlled temperature) and a narrow distribution of electron energy (e.g., Figures 12B / 12C). 【0094】 During the activation phase of the ALE cycle (e.g., Figures 13A / 13B / 13C / 13D / 13E), when a positive bias is applied to the stage (e.g., S), electrons (e.g., e-) uniformly distributed throughout the stage are attracted / drawn from the volume within the DC plasma reaction chamber (e.g., 110) located above the stage to the stage surface. During the neutralization phase of the ALE cycle (e.g., Figure 14), when a negative bias is applied to the stage (e.g., S), electrons (e.g., e-) are uniformly repelled from the stage surface to the volume above the stage. During the initialization phase of the ALE cycle (e.g., Figure 15), when a zero-volt bias voltage is applied to the stage (e.g., S), the initial state described above is reproduced inside the DC plasma reaction chamber (110) in close proximity to the stage, with reference to Figure 12C. This includes the stray potential V FP This involves returning the potential to its initial state, thereby returning the electrons in the plasma volume above the stage to their initial state, and allowing for (precise and) consistent control of the energy of the E-wave electrons used in each ALE cycle. When such ALE cycles are repeated at a constant pace, electrons (e.g., e-) arrive at distinct intervals with uniform density and energy across the entire surface area of ​​the stage (e.g., S). Each arrival of electrons at the stage surface at these intervals (e.g., arrival time) is referred herein to as an "electron wavefront" or a wafer-scale wave of precisely controlled electrons (e.g., represented as an E-wave in Figure 13C). 【0095】 Numerous embodiments of this disclosure have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of this disclosure. Therefore, other embodiments are within the scope of the following claims. 【0096】 The above embodiments are provided to those skilled in the art as a complete disclosure and description of the manufacturing methods and uses of the embodiments of this disclosure, and are not intended to limit the scope that the inventors consider to be disclosed. 【0097】 Modifications of the above-described embodiments for carrying out the methods and systems disclosed herein that are obvious to those skilled in the art are intended to be included in the following claims. All patents and publications referenced herein are indicative of the level of skill of those skilled in the art to which this disclosure relates. All references cited herein are to the same extent as if each reference in its entirety were referenced individually. 【0098】 This disclosure is not limited to any particular method or system and should be understood to be modifiable. Furthermore, the terms used herein are solely for the purpose of describing a particular embodiment and are not intended to limit it. Where used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless explicitly indicated otherwise. The term "plural" includes two or more references unless explicitly indicated otherwise. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs.

Claims

[Claim 1] A method for atomic layer etching of a substrate, The process involves generating a gaseous plasma containing diluted species, reactive species, and electrons of a uniform steady-state composition in a sunlight column of DC plasma close to the substrate, thereby generating a floating potential on the substrate surface. The steps include adjusting the floating potential to a known reference potential, The step of forming a corrosion layer on the substrate, wherein the corrosion layer includes corrosion layer species formed by the adsorption of reactive species onto atoms of the atomic layer on the surface of the substrate, The steps include applying a positive bias potential to the substrate relative to the floating potential, Based on the above application step, the steps include drawing electrons from the gaseous plasma to the substrate surface and energizing the drawn electrons to induce electron transitions in the corrosion layer species, and Based on the step of applying the energy, the corrosive layer species is detached, thereby etching and removing the atomic layer. A method that includes [a certain feature]. [Claim 2] In the method according to claim 1, the step of applying the positive bias potential is based on capacitive coupling of a positive pulse signal to a substrate support stage with respect to a known reference potential, The method wherein the positive pulse signal includes a high voltage level equal to a reaction threshold voltage for stimulating the electronic transition of the corrosive layer species. [Claim 3] The method according to claim 2, wherein the duration of the high voltage level is in the range of 0.1 μs to 0.3 μs. [Claim 4] A method according to any one of claims 1 to 3, further, The steps include applying a negative bias potential to the substrate relative to the floating potential, and Based on the step of applying the aforementioned negative bias potential, the electrons are repelled from the substrate surface into the volume of the gaseous plasma, thereby restoring a uniform steady-state composition. A method that includes [a certain feature]. [Claim 5] The method according to claim 4, wherein the step of applying the negative bias potential follows immediately after the step of applying the positive bias potential. [Claim 6] The method according to claim 5, wherein the duration for which the positive bias potential is applied is within the range of 1 / 10 to 1 / 1 of the duration for which the negative bias potential is applied. [Claim 7] The method described in claim 4, further, The steps include: a step of generating an electron wavefront having uniform energy and density across the entire surface of the substrate by changing the sequence of the step of applying the positive bias potential and the step of applying the negative bias potential; and The steps include: repeating the modification of the sequence at a regular pace, thereby causing the electron wavefront to reach the surface of the substrate at time intervals established by the regular pace, and etching away the corresponding atomic layer on the substrate surface at each time interval; A method that includes [a certain feature]. [Claim 8] The method according to any one of claims 1 to 3, wherein the substrate includes a first atomic layer made of atoms of a first material and a second atomic layer made of atoms of a second material, the first atomic layer is adjacent to and in contact with the second atomic layer, and A method wherein the uniform energy of the electron wavefront at a first arrival time for etching away the first atomic layer is different from the uniform energy of the electron wavefront at a second arrival time for etching away the second atomic layer. [Claim 9] The method according to claim 7, further, A method comprising the step of applying the negative bias potential, followed by the step of applying an initialization bias potential equal to the floating potential to the substrate for a time sufficient to form another corrosion layer on the substrate. [Claim 10] The method according to claim 9, further, A method comprising the step of restoring a uniform steady state within the sun column based on the step of applying the initialization bias potential. [Claim 11] The method according to claim 9, further, The step involves capacitively coupling a periodic bias signal, which is based on the known reference potential, to the substrate support stage. The step of applying the positive bias potential to the substrate is performed by a positive voltage during the activation phase of the periodic bias signal, and the positive voltage is based on a known reaction threshold voltage for stimulating the electronic transitions of the corrosion layer species. The step of applying the negative bias potential to the substrate is performed by a negative voltage in the neutralization phase of the periodic bias signal, and A method comprising the step of capacitively coupling the periodic bias signal to a substrate support stage, wherein the step of applying the initialization bias potential to the substrate is performed by the zero voltage of the initialization phase of the periodic bias signal. [Claim 12] The method according to claim 11, wherein the positive voltage is equal to or greater than the reaction threshold voltage. [Claim 13] The method according to claim 11, wherein the positive voltage is strictly greater than the reaction threshold voltage over a duration in the range of 1 / 4 to 3 / 4 of the total time length of the activation phase. [Claim 14] The method according to claim 11, wherein the negative voltage is low enough to maintain the energy level of the dilution species in the volume of the gaseous plasma below the reaction energy level of the corrosive layer species. [Claim 15] A method according to claim 11, wherein the DC component of the periodic bias signal is zero. [Claim 16] The method according to claim 11, wherein the frequency of the periodic bias signal is in the range of 100 kHz to 1 MHz. [Claim 17] A method according to claim 16, wherein the ratio of the duration of the active phase to the duration of the neutralization phase is in the range of 1 / 10 to 1 / 1. [Claim 18] In the method according to claim 16, The method wherein the ratio of the time length of the initialization phase to the time length of the cycle of the periodic bias signal is 1 / 4. [Claim 19] A method according to any one of claims 1 to 3, wherein the atoms of the atomic layer on the substrate surface are composed of any of a) a single crystal or two-dimensional material, b) a metal, c) a composite material or a three-dimensional material. [Claim 20] A method according to claim 19, wherein the single crystal or two-dimensional material includes a semiconductor or an insulator. [Claim 21] The method according to claim 20, wherein the semiconductor comprises one of IV silicon, germanium, III-V gallium arsenide, gallium nitride, silicon carbide, and indium gallium arsenide. [Claim 22] The method according to claim 19, wherein the single crystal or two-dimensional material comprises one of graphene, boron, nitride, molybdenum disulfide, tungsten selenide, or platinum diselenide. [Claim 23] The method according to claim 19, wherein the composite material or three-dimensional material includes a polymer, a composite material, or a nanomaterial. [Claim 24] The method according to claim 19, wherein the composite material or three-dimensional material comprises one of carbon nanotubes, nanosilver particles, titanium oxide particles, or quantum dots. [Claim 25] In the method according to any one of claims 1 to 3, The diluent gas includes one or a combination of argon, neon, or xenon. A method wherein the reaction gas comprises hydrogen, chlorine, methane, carbon monoxide, oxygen, or any one of the others, or a combination thereof. [Claim 26] The method according to claim 25, wherein the ratio of the reaction gas to the diluent gas is in the range of 2 / 100 to 50 / 100. [Claim 27] A method according to claim 25, wherein the diluent is an argon ion and the reactant is a hydrogen species. [Claim 28] A method for atomically etching a substrate via an electron wavefront, The process involves generating a gaseous plasma containing a uniform steady-state composition of diluted species, reactive species, and electrons within a sunbeam of DC plasma close to the substrate, thereby generating a floating potential on the substrate surface. The steps include adjusting the floating potential to a reference potential, The steps of forming a corrosion layer on a substrate that includes corrosion layer species formed by the adsorption of reactive species onto atoms in the atomic layer on the surface of the substrate, and The process includes the step of applying a sequence of periodic bias signals to the substrate, which is a periodic bias signal based on the aforementioned reference potential, wherein a positive bias potential is followed by a negative bias potential, and then a zero bias potential equal to the aforementioned reference potential, thereby causing an electron wavefront having uniform energy and density across the entire surface of the substrate to arrive at a predetermined arrival time determined by the periodic bias signal. When a positive bias potential is applied, an electron wavefront crossing the substrate surface arrives at each arrival time, thereby inducing an electron transition in the corrosion layer, and one atomic layer of the substrate is etched away. When a negative bias potential is applied, the electron wavefront is repelled from the substrate surface, thereby restoring a uniform steady-state composition within the sun column. When a zero bias potential is applied, another corrosion layer is formed on the substrate. method. [Claim 29] The method according to claim 28, wherein the step of adjusting the floating potential includes adjusting the potential applied to the anode of a DC plasma chamber including the sun column, and the cathode of the DC plasma chamber is allowed to float and remain constant at a potential based on a fixed current conducted between the anode and the cathode, the fixed current being supplied by a current source coupled to the cathode.

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